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b43: N-PHY: update code for sending sample tone
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
89e43dad
RM		 72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
2a2d0589
RM		 80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
76b002bd
RM		 88};
89
6aa38725
RM		 90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
76b002bd
RM		 93};
94
c002831a
RM		 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
e0c9a021
RM		 102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
ab499217 109/**************************************************
89e43dad 110 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 111 **************************************************/
18c8adeb 112
ab499217
RM		 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
d1591314 116{
ab499217
RM		 117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 127
ab499217 128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 129
ab499217
RM		 130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
e5255ccc 142
c071b9f6 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
146 u8 override)
c071b9f6
RM		 147{
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
151 };
152 u16 en_addr;
153 u16 en_mask = field;
154 u16 val_addr;
155 u8 i;
156
157 /* Remember: we can get NULL! */
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
159
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
163 return;
164 }
165 en_addr = en_addrs[override][i];
166
8ce9beac
FP		 167 if (e)
168 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 169
170 if (off) {
171 b43_phy_mask(dev, en_addr, ~en_mask);
172 if (e) /* Do it safer, better than wl */
173 b43_phy_mask(dev, val_addr, ~e->val_mask);
174 } else {
175 if (!core || (core & (1 << i))) {
176 b43_phy_set(dev, en_addr, en_mask);
177 if (e)
178 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
179 }
180 }
181 }
182}
183
ab499217 184/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 185static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
186 u16 value, u8 core, bool off)
ab499217
RM		 187{
188 int i;
189 u8 index = fls(field);
190 u8 addr, en_addr, val_addr;
191 /* we expect only one bit set */
192 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 193
ab499217
RM		 194 if (dev->phy.rev >= 3) {
195 const struct nphy_rf_control_override_rev3 *rf_ctrl;
196 for (i = 0; i < 2; i++) {
197 if (index == 0 || index == 16) {
198 b43err(dev->wl,
199 "Unsupported RF Ctrl Override call\n");
200 return;
201 }
e5255ccc 202
ab499217
RM		 203 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
204 en_addr = B43_PHY_N((i == 0) ?
205 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
206 val_addr = B43_PHY_N((i == 0) ?
207 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 208
ab499217
RM		 209 if (off) {
210 b43_phy_mask(dev, en_addr, ~(field));
211 b43_phy_mask(dev, val_addr,
212 ~(rf_ctrl->val_mask));
213 } else {
b97c0718 214 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 215 b43_phy_set(dev, en_addr, field);
216 b43_phy_maskset(dev, val_addr,
217 ~(rf_ctrl->val_mask),
218 (value << rf_ctrl->val_shift));
219 }
220 }
221 }
222 } else {
223 const struct nphy_rf_control_override_rev2 *rf_ctrl;
224 if (off) {
225 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
226 value = 0;
227 } else {
228 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
229 }
d4814e69 230
ab499217
RM		 231 for (i = 0; i < 2; i++) {
232 if (index <= 1 || index == 16) {
233 b43err(dev->wl,
234 "Unsupported RF Ctrl Override call\n");
235 return;
236 }
d4814e69 237
ab499217
RM		 238 if (index == 2 || index == 10 ||
239 (index >= 13 && index <= 15)) {
240 core = 1;
241 }
d4814e69 242
ab499217
RM		 243 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
244 addr = B43_PHY_N((i == 0) ?
245 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 246
b97c0718 247 if ((1 << i) & core)
ab499217
RM		 248 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
249 (value << rf_ctrl->shift));
250
251 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
252 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
253 B43_NPHY_RFCTL_CMD_START);
254 udelay(1);
255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
256 }
257 }
d4814e69
RM		 258}
259
4256ba77
RM		 260static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
261 enum n_intc_override intc_override,
262 u16 value, u8 core_sel)
263{
264 u16 reg, tmp, tmp2, val;
265 int core;
266
267 for (core = 0; core < 2; core++) {
268 if ((core_sel == 1 && core != 0) ||
269 (core_sel == 2 && core != 1))
270 continue;
271
272 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
273
274 switch (intc_override) {
275 case N_INTC_OVERRIDE_OFF:
276 b43_phy_write(dev, reg, 0);
277 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
278 break;
279 case N_INTC_OVERRIDE_TRSW:
280 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
281 b43_phy_set(dev, reg, 0x400);
282
283 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
284 b43_phy_set(dev, 0x2ff, 0x2000);
285 b43_phy_set(dev, 0x2ff, 0x0001);
286 break;
287 case N_INTC_OVERRIDE_PA:
288 tmp = 0x0030;
289 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
290 val = value << 5;
291 else
292 val = value << 4;
293 b43_phy_maskset(dev, reg, ~tmp, val);
294 b43_phy_set(dev, reg, 0x1000);
295 break;
296 case N_INTC_OVERRIDE_EXT_LNA_PU:
297 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
298 tmp = 0x0001;
299 tmp2 = 0x0004;
300 val = value;
301 } else {
302 tmp = 0x0004;
303 tmp2 = 0x0001;
304 val = value << 2;
305 }
306 b43_phy_maskset(dev, reg, ~tmp, val);
307 b43_phy_mask(dev, reg, ~tmp2);
308 break;
309 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
310 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
311 tmp = 0x0002;
312 tmp2 = 0x0008;
313 val = value << 1;
314 } else {
315 tmp = 0x0008;
316 tmp2 = 0x0002;
317 val = value << 3;
318 }
319 b43_phy_maskset(dev, reg, ~tmp, val);
320 b43_phy_mask(dev, reg, ~tmp2);
321 break;
322 }
323 }
324}
325
ab499217 326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 327static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
328 enum n_intc_override intc_override,
329 u16 value, u8 core)
d4814e69 330{
ab499217
RM		 331 u8 i, j;
332 u16 reg, tmp, val;
38646eba 333
4256ba77
RM		 334 if (dev->phy.rev >= 7) {
335 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
336 core);
337 return;
338 }
339
d4814e69
RM		 340 B43_WARN_ON(dev->phy.rev < 3);
341
ab499217
RM		 342 for (i = 0; i < 2; i++) {
343 if ((core == 1 && i == 1) || (core == 2 && !i))
344 continue;
38646eba 345
ab499217
RM		 346 reg = (i == 0) ?
347 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 348 b43_phy_set(dev, reg, 0x400);
38646eba 349
89e43dad
RM		 350 switch (intc_override) {
351 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 352 b43_phy_write(dev, reg, 0);
353 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
354 break;
89e43dad 355 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 356 if (!i) {
357 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
358 0xFC3F, (value << 6));
359 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
360 0xFFFE, 1);
361 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
362 B43_NPHY_RFCTL_CMD_START);
363 for (j = 0; j < 100; j++) {
603431e9 364 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 365 j = 0;
366 break;
367 }
368 udelay(10);
38646eba 369 }
ab499217
RM		 370 if (j)
371 b43err(dev->wl,
372 "intc override timeout\n");
373 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
374 0xFFFE);
38646eba 375 } else {
ab499217
RM		 376 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
377 0xFC3F, (value << 6));
378 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
379 0xFFFE, 1);
380 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
381 B43_NPHY_RFCTL_CMD_RXTX);
382 for (j = 0; j < 100; j++) {
603431e9 383 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 384 j = 0;
385 break;
386 }
387 udelay(10);
388 }
389 if (j)
390 b43err(dev->wl,
391 "intc override timeout\n");
392 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
393 0xFFFE);
38646eba 394 }
ab499217 395 break;
89e43dad 396 case N_INTC_OVERRIDE_PA:
ab499217
RM		 397 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
398 tmp = 0x0020;
399 val = value << 5;
400 } else {
401 tmp = 0x0010;
402 val = value << 4;
403 }
404 b43_phy_maskset(dev, reg, ~tmp, val);
405 break;
89e43dad 406 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 407 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
408 tmp = 0x0001;
409 val = value;
410 } else {
411 tmp = 0x0004;
412 val = value << 2;
413 }
414 b43_phy_maskset(dev, reg, ~tmp, val);
415 break;
89e43dad 416 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 417 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
418 tmp = 0x0002;
419 val = value << 1;
420 } else {
421 tmp = 0x0008;
422 val = value << 3;
423 }
424 b43_phy_maskset(dev, reg, ~tmp, val);
425 break;
38646eba 426 }
38646eba 427 }
ab499217 428}
38646eba 429
ab499217
RM		 430/**************************************************
431 * Various PHY ops
432 **************************************************/
433
434/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
435static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
436 const u16 *clip_st)
437{
438 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
439 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 440}
441
ab499217
RM		 442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
443static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 444{
ab499217
RM		 445 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
446 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 447}
448
ab499217
RM		 449/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
450static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 451{
ab499217 452 u16 tmp;
161d540c 453
ab499217
RM		 454 if (dev->dev->core_rev == 16)
455 b43_mac_suspend(dev);
161d540c 456
ab499217
RM		 457 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
458 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
459 B43_NPHY_CLASSCTL_WAITEDEN);
460 tmp &= ~mask;
461 tmp |= (val & mask);
462 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 463
ab499217
RM		 464 if (dev->dev->core_rev == 16)
465 b43_mac_enable(dev);
161d540c 466
ab499217
RM		 467 return tmp;
468}
161d540c 469
ab499217
RM		 470/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
471static void b43_nphy_reset_cca(struct b43_wldev *dev)
472{
473 u16 bbcfg;
161d540c 474
ab499217
RM		 475 b43_phy_force_clock(dev, 1);
476 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
477 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
478 udelay(1);
479 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
480 b43_phy_force_clock(dev, 0);
481 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
482}
161d540c 483
ab499217
RM		 484/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
485static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
486{
487 struct b43_phy *phy = &dev->phy;
488 struct b43_phy_n *nphy = phy->n;
161d540c 489
ab499217
RM		 490 if (enable) {
491 static const u16 clip[] = { 0xFFFF, 0xFFFF };
492 if (nphy->deaf_count++ == 0) {
493 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
bc36e994
RM		 494 b43_nphy_classifier(dev, 0x7,
495 B43_NPHY_CLASSCTL_WAITEDEN);
ab499217
RM		 496 b43_nphy_read_clip_detection(dev, nphy->clip_state);
497 b43_nphy_write_clip_detection(dev, clip);
498 }
499 b43_nphy_reset_cca(dev);
161d540c 500 } else {
ab499217
RM		 501 if (--nphy->deaf_count == 0) {
502 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
503 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 504 }
161d540c 505 }
161d540c
RM		 506}
507
64712095
RM		 508/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
509static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 510{
161d540c 511 struct b43_phy_n *nphy = dev->phy.n;
161d540c 512
64712095
RM		 513 u8 i;
514 s16 tmp;
515 u16 data[4];
516 s16 gain[2];
517 u16 minmax[2];
518 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 519
520 if (nphy->hang_avoid)
521 b43_nphy_stay_in_carrier_search(dev, 1);
522
64712095 523 if (nphy->gain_boost) {
161d540c 524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 525 gain[0] = 6;
526 gain[1] = 6;
161d540c 527 } else {
64712095
RM		 528 tmp = 40370 - 315 * dev->phy.channel;
529 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
530 tmp = 23242 - 224 * dev->phy.channel;
531 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 532 }
64712095
RM		 533 } else {
534 gain[0] = 0;
535 gain[1] = 0;
161d540c 536 }
161d540c
RM		 537
538 for (i = 0; i < 2; i++) {
64712095
RM		 539 if (nphy->elna_gain_config) {
540 data[0] = 19 + gain[i];
541 data[1] = 25 + gain[i];
542 data[2] = 25 + gain[i];
543 data[3] = 25 + gain[i];
161d540c 544 } else {
64712095
RM		 545 data[0] = lna_gain[0] + gain[i];
546 data[1] = lna_gain[1] + gain[i];
547 data[2] = lna_gain[2] + gain[i];
548 data[3] = lna_gain[3] + gain[i];
161d540c 549 }
64712095 550 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 551
64712095 552 minmax[i] = 23 + gain[i];
161d540c
RM		 553 }
554
64712095
RM		 555 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
556 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
557 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
558 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 559
560 if (nphy->hang_avoid)
561 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 562}
563
ab499217
RM		 564/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
565static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
566 u8 *events, u8 *delays, u8 length)
0eff8fcd 567{
ab499217
RM		 568 struct b43_phy_n *nphy = dev->phy.n;
569 u8 i;
570 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
571 u16 offset1 = cmd << 4;
572 u16 offset2 = offset1 + 0x80;
0eff8fcd 573
ab499217
RM		 574 if (nphy->hang_avoid)
575 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 576
ab499217
RM		 577 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
578 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 579
ab499217
RM		 580 for (i = length; i < 16; i++) {
581 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
582 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 583 }
ab499217
RM		 584
585 if (nphy->hang_avoid)
586 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 587}
7955de0c 588
572d37a4
RM		 589/**************************************************
590 * Radio 0x2057
591 **************************************************/
592
593/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
594static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
595{
596 struct b43_phy *phy = &dev->phy;
597 u16 tmp;
598
599 if (phy->radio_rev == 5) {
600 b43_phy_mask(dev, 0x342, ~0x2);
601 udelay(10);
602 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
603 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
604 }
605
606 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
607 udelay(10);
608 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
609 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
610 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
611 return 0;
612 }
613 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
614 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
615 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
616
617 if (phy->radio_rev == 5) {
618 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
619 b43_radio_mask(dev, 0x1ca, ~0x2);
620 }
621 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
622 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
623 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
624 tmp << 2);
625 }
626
627 return tmp & 0x3e;
628}
629
630/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
631static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
632{
633 struct b43_phy *phy = &dev->phy;
634 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
635 phy->radio_rev == 6);
636 u16 tmp;
637
638 if (special) {
639 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
640 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
641 } else {
642 b43_radio_write(dev, 0x1AE, 0x61);
643 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
644 }
645 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
646 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
647 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
648 5000000))
649 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
650 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
651 if (special) {
652 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
653 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
654 } else {
655 b43_radio_write(dev, 0x1AE, 0x69);
656 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
657 }
658 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
659 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
660 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
661 5000000))
6c187236 662 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
572d37a4
RM		 663 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
664 if (special) {
665 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
666 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
667 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
668 } else {
669 b43_radio_write(dev, 0x1AE, 0x73);
670 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
671 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
672 }
673 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
674 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
675 5000000)) {
676 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
677 return 0;
678 }
679 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
680 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
681 return tmp;
682}
683
684static void b43_radio_2057_init_pre(struct b43_wldev *dev)
685{
686 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
687 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
688 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
689 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
690 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
691}
692
693static void b43_radio_2057_init_post(struct b43_wldev *dev)
694{
695 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
696
697 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
698 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
699 mdelay(2);
700 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
701 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
702
90e569d1 703 if (dev->phy.do_full_init) {
572d37a4
RM		 704 b43_radio_2057_rcal(dev);
705 b43_radio_2057_rccal(dev);
706 }
707 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
572d37a4
RM		 708}
709
710/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
711static void b43_radio_2057_init(struct b43_wldev *dev)
712{
713 b43_radio_2057_init_pre(dev);
714 r2057_upload_inittabs(dev);
715 b43_radio_2057_init_post(dev);
716}
717
ab499217 718/**************************************************
884a5228 719 * Radio 0x2056
ab499217 720 **************************************************/
7955de0c 721
d4814e69
RM		 722static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
723 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 724{
d4814e69
RM		 725 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
726 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
727 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
728 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
729 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
730 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
731 e->radio_syn_pll_loopfilter1);
732 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
733 e->radio_syn_pll_loopfilter2);
734 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
735 e->radio_syn_pll_loopfilter3);
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
737 e->radio_syn_pll_loopfilter4);
738 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
739 e->radio_syn_pll_loopfilter5);
740 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
741 e->radio_syn_reserved_addr27);
742 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
743 e->radio_syn_reserved_addr28);
744 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
745 e->radio_syn_reserved_addr29);
746 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
747 e->radio_syn_logen_vcobuf1);
748 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
749 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
750 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
751
752 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
753 e->radio_rx0_lnaa_tune);
754 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
755 e->radio_rx0_lnag_tune);
756
757 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
758 e->radio_tx0_intpaa_boost_tune);
759 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
760 e->radio_tx0_intpag_boost_tune);
761 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
762 e->radio_tx0_pada_boost_tune);
763 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
764 e->radio_tx0_padg_boost_tune);
765 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
766 e->radio_tx0_pgaa_boost_tune);
767 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
768 e->radio_tx0_pgag_boost_tune);
769 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
770 e->radio_tx0_mixa_boost_tune);
771 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
772 e->radio_tx0_mixg_boost_tune);
773
774 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
775 e->radio_rx1_lnaa_tune);
776 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
777 e->radio_rx1_lnag_tune);
778
779 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
780 e->radio_tx1_intpaa_boost_tune);
781 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
782 e->radio_tx1_intpag_boost_tune);
783 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
784 e->radio_tx1_pada_boost_tune);
785 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
786 e->radio_tx1_padg_boost_tune);
787 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
788 e->radio_tx1_pgaa_boost_tune);
789 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
790 e->radio_tx1_pgag_boost_tune);
791 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
792 e->radio_tx1_mixa_boost_tune);
793 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
794 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 795}
796
d4814e69
RM		 797/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
798static void b43_radio_2056_setup(struct b43_wldev *dev,
799 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 800{
39e971ef 801 struct b43_phy *phy = &dev->phy;
0581483a 802 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 803 enum ieee80211_band band = b43_current_band(dev->wl);
804 u16 offset;
805 u8 i;
d3d178f0
RM		 806 u16 bias, cbias;
807 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
808 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
b88cdde9 809 bool is_pkg_fab_smic;
036cafe4 810
d4814e69 811 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 812
b88cdde9
RM		 813 is_pkg_fab_smic =
814 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
815 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
816 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
817 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
818
d4814e69 819 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 820 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
821
822 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
823 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
824 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
825 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
b88cdde9
RM		 826 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
827 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 828 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
829 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
830 } else {
831 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
832 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 833 }
53a6e234 834 }
b88cdde9
RM		 835 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
836 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
837 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
838 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
839 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
840 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
841 }
38646eba
RM		 842 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
843 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
844 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
845 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
846 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
847 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 848 }
53a6e234 849
38646eba
RM		 850 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
851 for (i = 0; i < 2; i++) {
852 offset = i ? B2056_TX1 : B2056_TX0;
853 if (dev->phy.rev >= 5) {
854 b43_radio_write(dev,
855 offset | B2056_TX_PADG_IDAC, 0xcc);
856
b88cdde9
RM		 857 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
858 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 859 bias = 0x40;
860 cbias = 0x45;
861 pag_boost = 0x5;
862 pgag_boost = 0x33;
863 mixg_boost = 0x55;
864 } else {
865 bias = 0x25;
866 cbias = 0x20;
b88cdde9
RM		 867 if (is_pkg_fab_smic) {
868 bias = 0x2a;
869 cbias = 0x38;
870 }
38646eba
RM		 871 pag_boost = 0x4;
872 pgag_boost = 0x03;
873 mixg_boost = 0x65;
874 }
875 padg_boost = 0x77;
876
877 b43_radio_write(dev,
878 offset | B2056_TX_INTPAG_IMAIN_STAT,
879 bias);
880 b43_radio_write(dev,
881 offset | B2056_TX_INTPAG_IAUX_STAT,
882 bias);
883 b43_radio_write(dev,
884 offset | B2056_TX_INTPAG_CASCBIAS,
885 cbias);
886 b43_radio_write(dev,
887 offset | B2056_TX_INTPAG_BOOST_TUNE,
888 pag_boost);
889 b43_radio_write(dev,
890 offset | B2056_TX_PGAG_BOOST_TUNE,
891 pgag_boost);
892 b43_radio_write(dev,
893 offset | B2056_TX_PADG_BOOST_TUNE,
894 padg_boost);
895 b43_radio_write(dev,
896 offset | B2056_TX_MIXG_BOOST_TUNE,
897 mixg_boost);
898 } else {
bee6d4b2 899 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
38646eba
RM		 900 b43_radio_write(dev,
901 offset | B2056_TX_INTPAG_IMAIN_STAT,
902 bias);
903 b43_radio_write(dev,
904 offset | B2056_TX_INTPAG_IAUX_STAT,
905 bias);
906 b43_radio_write(dev,
907 offset | B2056_TX_INTPAG_CASCBIAS,
908 0x30);
909 }
910 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
911 }
912 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
39e971ef 913 u16 freq = phy->chandef->chan->center_freq;
d3d178f0
RM		 914 if (freq < 5100) {
915 paa_boost = 0xA;
916 pada_boost = 0x77;
917 pgaa_boost = 0xF;
918 mixa_boost = 0xF;
919 } else if (freq < 5340) {
920 paa_boost = 0x8;
921 pada_boost = 0x77;
922 pgaa_boost = 0xFB;
923 mixa_boost = 0xF;
924 } else if (freq < 5650) {
925 paa_boost = 0x0;
926 pada_boost = 0x77;
927 pgaa_boost = 0xB;
928 mixa_boost = 0xF;
929 } else {
930 paa_boost = 0x0;
931 pada_boost = 0x77;
932 if (freq != 5825)
933 pgaa_boost = -(freq - 18) / 36 + 168;
934 else
935 pgaa_boost = 6;
936 mixa_boost = 0xF;
937 }
938
b88cdde9
RM		 939 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
940
d3d178f0
RM		 941 for (i = 0; i < 2; i++) {
942 offset = i ? B2056_TX1 : B2056_TX0;
943
944 b43_radio_write(dev,
945 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
946 b43_radio_write(dev,
947 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
948 b43_radio_write(dev,
949 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
950 b43_radio_write(dev,
951 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
952 b43_radio_write(dev,
953 offset | B2056_TX_TXSPARE1, 0x30);
954 b43_radio_write(dev,
955 offset | B2056_TX_PA_SPARE2, 0xee);
956 b43_radio_write(dev,
957 offset | B2056_TX_PADA_CASCBIAS, 0x03);
958 b43_radio_write(dev,
b88cdde9 959 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
d3d178f0 960 b43_radio_write(dev,
b88cdde9 961 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
d3d178f0 962 b43_radio_write(dev,
b88cdde9 963 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
d3d178f0 964 }
a2d9bc6f 965 }
38646eba 966
d4814e69
RM		 967 udelay(50);
968 /* VCO calibration */
969 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
970 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
971 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
972 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
973 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
974 udelay(300);
53a6e234
MB		 975}
976
d3d178f0
RM		 977static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
978{
979 struct b43_phy *phy = &dev->phy;
980 u16 mast2, tmp;
981
982 if (phy->rev != 3)
983 return 0;
984
985 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
986 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
987
988 udelay(10);
989 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
990 udelay(10);
991 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
992
993 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
994 1000000)) {
995 b43err(dev->wl, "Radio recalibration timeout\n");
996 return 0;
997 }
998
999 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1000 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1001 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1002
1003 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1004
1005 return tmp & 0x1f;
1006}
1007
ea7ee14b
RM		 1008static void b43_radio_init2056_pre(struct b43_wldev *dev)
1009{
1010 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1011 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1012 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1013 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1014 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1015 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1016 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1017 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1018 B43_NPHY_RFCTL_CMD_CHIP0PU);
1019}
1020
1021static void b43_radio_init2056_post(struct b43_wldev *dev)
1022{
1023 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1024 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1025 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1026 msleep(1);
1027 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1028 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1029 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
90e569d1 1030 if (dev->phy.do_full_init)
d3d178f0 1031 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 1032}
1033
d817f4e1
RM		 1034/*
1035 * Initialize a Broadcom 2056 N-radio
1036 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1037 */
1038static void b43_radio_init2056(struct b43_wldev *dev)
1039{
ea7ee14b
RM		 1040 b43_radio_init2056_pre(dev);
1041 b2056_upload_inittabs(dev, 0, 0);
1042 b43_radio_init2056_post(dev);
d817f4e1
RM		 1043}
1044
884a5228
RM		 1045/**************************************************
1046 * Radio 0x2055
1047 **************************************************/
1048
1049static void b43_chantab_radio_upload(struct b43_wldev *dev,
1050 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1051{
884a5228
RM		 1052 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1053 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1054 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1055 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1056 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 1057
884a5228
RM		 1058 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1059 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1060 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1061 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1062 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1063
884a5228
RM		 1064 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1065 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1066 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1067 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1068 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1069
884a5228
RM		 1070 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1071 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1072 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1073 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1074 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1075
884a5228
RM		 1076 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1077 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1078 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1079 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1080 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1081
884a5228
RM		 1082 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1083 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 1084}
1085
884a5228
RM		 1086/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1087static void b43_radio_2055_setup(struct b43_wldev *dev,
1088 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1089{
884a5228 1090 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 1091
884a5228
RM		 1092 b43_chantab_radio_upload(dev, e);
1093 udelay(50);
1094 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1095 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1096 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1097 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1098 udelay(300);
95b66bad
MB		 1099}
1100
884a5228 1101static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1102{
884a5228
RM		 1103 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1104 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1105 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1106 B43_NPHY_RFCTL_CMD_CHIP0PU |
1107 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1108 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1109 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1110}
1111
884a5228 1112static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1113{
1114 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1115 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1116 bool workaround = false;
2faa6b83 1117
884a5228
RM		 1118 if (sprom->revision < 4)
1119 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1120 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1121 && dev->dev->board_rev >= 0x41);
2faa6b83 1122 else
884a5228
RM		 1123 workaround =
1124 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1125
884a5228
RM		 1126 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1127 if (workaround) {
1128 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1129 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1130 }
1131 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1132 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1133 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1134 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1135 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1136 msleep(1);
1137 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1138 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1139 b43err(dev->wl, "radio post init timeout\n");
1140 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1141 b43_switch_channel(dev, dev->phy.channel);
1142 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1143 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1144 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1145 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1146 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1147 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1148 if (!nphy->gain_boost) {
1149 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1150 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1151 } else {
1152 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1153 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1154 }
1155 udelay(2);
2faa6b83
RM		 1156}
1157
884a5228
RM		 1158/*
1159 * Initialize a Broadcom 2055 N-radio
1160 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1161 */
1162static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1163{
884a5228
RM		 1164 b43_radio_init2055_pre(dev);
1165 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1166 /* Follow wl, not specs. Do not force uploading all regs */
1167 b2055_upload_inittab(dev, 0, 0);
a67162ab 1168 } else {
884a5228
RM		 1169 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1170 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1171 }
884a5228 1172 b43_radio_init2055_post(dev);
a67162ab
RM		 1173}
1174
8be89535
RM		 1175/**************************************************
1176 * Samples
1177 **************************************************/
026816fc 1178
8be89535
RM		 1179/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1180static int b43_nphy_load_samples(struct b43_wldev *dev,
1181 struct b43_c32 *samples, u16 len) {
1182 struct b43_phy_n *nphy = dev->phy.n;
1183 u16 i;
1184 u32 *data;
1185
1186 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1187 if (!data) {
1188 b43err(dev->wl, "allocation for samples loading failed\n");
1189 return -ENOMEM;
1190 }
1191 if (nphy->hang_avoid)
1192 b43_nphy_stay_in_carrier_search(dev, 1);
1193
1194 for (i = 0; i < len; i++) {
1195 data[i] = (samples[i].i & 0x3FF << 10);
1196 data[i] |= samples[i].q & 0x3FF;
1197 }
1198 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1199
1200 kfree(data);
1201 if (nphy->hang_avoid)
1202 b43_nphy_stay_in_carrier_search(dev, 0);
1203 return 0;
026816fc
RM		 1204}
1205
8be89535
RM		 1206/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1207static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1208 bool test)
026816fc 1209{
8be89535
RM		 1210 int i;
1211 u16 bw, len, rot, angle;
1212 struct b43_c32 *samples;
026816fc 1213
bee6d4b2 1214 bw = b43_is_40mhz(dev) ? 40 : 20;
8be89535 1215 len = bw << 3;
026816fc 1216
8be89535
RM		 1217 if (test) {
1218 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1219 bw = 82;
1220 else
1221 bw = 80;
026816fc 1222
bee6d4b2 1223 if (b43_is_40mhz(dev))
8be89535
RM		 1224 bw <<= 1;
1225
1226 len = bw << 1;
026816fc
RM		 1227 }
1228
8be89535
RM		 1229 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1230 if (!samples) {
1231 b43err(dev->wl, "allocation for samples generation failed\n");
1232 return 0;
1233 }
1234 rot = (((freq * 36) / bw) << 16) / 100;
1235 angle = 0;
026816fc 1236
8be89535
RM		 1237 for (i = 0; i < len; i++) {
1238 samples[i] = b43_cordic(angle);
1239 angle += rot;
1240 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1241 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1242 }
8be89535
RM		 1243
1244 i = b43_nphy_load_samples(dev, samples, len);
1245 kfree(samples);
1246 return (i < 0) ? 0 : len;
026816fc
RM		 1247}
1248
8be89535
RM		 1249/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1250static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
ed03033e
RM		 1251 u16 wait, bool iqmode, bool dac_test,
1252 bool modify_bbmult)
34a56f2c 1253{
8be89535 1254 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1255 int i;
8be89535
RM		 1256 u16 seq_mode;
1257 u32 tmp;
34a56f2c 1258
bc36e994 1259 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1260
8be89535
RM		 1261 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1262 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1263 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1264 }
34a56f2c 1265
ed03033e
RM		 1266 if (modify_bbmult) {
1267 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747;
1268 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1269 }
34a56f2c 1270
8be89535 1271 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1272
8be89535
RM		 1273 if (loops != 0xFFFF)
1274 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1275 else
1276 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1277
8be89535 1278 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1279
8be89535 1280 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1281
8be89535
RM		 1282 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1283 if (iqmode) {
1284 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1285 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1286 } else {
ed03033e
RM		 1287 tmp = dac_test ? 5 : 1;
1288 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp);
8be89535
RM		 1289 }
1290 for (i = 0; i < 100; i++) {
2c8ac7eb 1291 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1292 i = 0;
1293 break;
34a56f2c 1294 }
8be89535 1295 udelay(10);
34a56f2c 1296 }
8be89535
RM		 1297 if (i)
1298 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1299
8be89535 1300 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
bc36e994
RM		 1301
1302 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c
RM		 1303}
1304
4d9f46ba
RM		 1305/**************************************************
1306 * RSSI
1307 **************************************************/
1308
1309/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1310static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1311 s8 offset, u8 core,
1312 enum n_rail_type rail,
2a2d0589 1313 enum n_rssi_type rssi_type)
09146400 1314{
4d9f46ba
RM		 1315 u16 tmp;
1316 bool core1or5 = (core == 1) || (core == 5);
1317 bool core2or5 = (core == 2) || (core == 5);
09146400 1318
4d9f46ba
RM		 1319 offset = clamp_val(offset, -32, 31);
1320 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1321
e5ab1fd7 1322 switch (rssi_type) {
2a2d0589 1323 case N_RSSI_NB:
e5ab1fd7
RM		 1324 if (core1or5 && rail == N_RAIL_I)
1325 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1326 if (core1or5 && rail == N_RAIL_Q)
1327 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1328 if (core2or5 && rail == N_RAIL_I)
1329 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1330 if (core2or5 && rail == N_RAIL_Q)
1331 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1332 break;
2a2d0589 1333 case N_RSSI_W1:
e5ab1fd7
RM		 1334 if (core1or5 && rail == N_RAIL_I)
1335 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1336 if (core1or5 && rail == N_RAIL_Q)
1337 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1338 if (core2or5 && rail == N_RAIL_I)
1339 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1340 if (core2or5 && rail == N_RAIL_Q)
1341 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1342 break;
2a2d0589 1343 case N_RSSI_W2:
e5ab1fd7
RM		 1344 if (core1or5 && rail == N_RAIL_I)
1345 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1346 if (core1or5 && rail == N_RAIL_Q)
1347 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1348 if (core2or5 && rail == N_RAIL_I)
1349 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1350 if (core2or5 && rail == N_RAIL_Q)
1351 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1352 break;
2a2d0589 1353 case N_RSSI_TBD:
e5ab1fd7
RM		 1354 if (core1or5 && rail == N_RAIL_I)
1355 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1356 if (core1or5 && rail == N_RAIL_Q)
1357 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1358 if (core2or5 && rail == N_RAIL_I)
1359 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1360 if (core2or5 && rail == N_RAIL_Q)
1361 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1362 break;
2a2d0589 1363 case N_RSSI_IQ:
e5ab1fd7
RM		 1364 if (core1or5 && rail == N_RAIL_I)
1365 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1366 if (core1or5 && rail == N_RAIL_Q)
1367 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1368 if (core2or5 && rail == N_RAIL_I)
1369 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1370 if (core2or5 && rail == N_RAIL_Q)
1371 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1372 break;
2a2d0589 1373 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1374 if (core1or5)
1375 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1376 if (core2or5)
1377 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1378 break;
2a2d0589 1379 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1380 if (core1or5)
1381 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1382 if (core2or5)
1383 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1384 break;
1385 }
8987a9e9
RM		 1386}
1387
a3764ef7
RM		 1388static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1389 enum n_rssi_type rssi_type)
bbec398c 1390{
4d9f46ba
RM		 1391 u8 i;
1392 u16 reg, val;
bbec398c 1393
4d9f46ba
RM		 1394 if (code == 0) {
1395 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1396 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1397 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1398 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1399 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1400 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1401 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1402 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1403 } else {
1404 for (i = 0; i < 2; i++) {
1405 if ((code == 1 && i == 1) || (code == 2 && !i))
1406 continue;
bbec398c 1407
4d9f46ba
RM		 1408 reg = (i == 0) ?
1409 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1410 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1411
a3764ef7
RM		 1412 if (rssi_type == N_RSSI_W1 ||
1413 rssi_type == N_RSSI_W2 ||
1414 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1415 reg = (i == 0) ?
1416 B43_NPHY_AFECTL_C1 :
1417 B43_NPHY_AFECTL_C2;
1418 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1419
4d9f46ba
RM		 1420 reg = (i == 0) ?
1421 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1422 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1423 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1424
a3764ef7 1425 if (rssi_type == N_RSSI_W1)
4d9f46ba 1426 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1427 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1428 val = 16;
1429 else
1430 val = 32;
1431 b43_phy_set(dev, reg, val);
5c1a140a 1432
4d9f46ba
RM		 1433 reg = (i == 0) ?
1434 B43_NPHY_TXF_40CO_B1S0 :
1435 B43_NPHY_TXF_40CO_B32S1;
1436 b43_phy_set(dev, reg, 0x0020);
1437 } else {
a3764ef7 1438 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1439 val = 0x0100;
a3764ef7 1440 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1441 val = 0x0200;
1442 else
1443 val = 0x0300;
5c1a140a 1444
4d9f46ba
RM		 1445 reg = (i == 0) ?
1446 B43_NPHY_AFECTL_C1 :
1447 B43_NPHY_AFECTL_C2;
53ae8e8c 1448
4d9f46ba
RM		 1449 b43_phy_maskset(dev, reg, 0xFCFF, val);
1450 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1451
a3764ef7
RM		 1452 if (rssi_type != N_RSSI_IQ &&
1453 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1454 enum ieee80211_band band =
1455 b43_current_band(dev->wl);
53ae8e8c 1456
4d9f46ba
RM		 1457 if (b43_nphy_ipa(dev))
1458 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1459 else
1460 val = 0x11;
1461 reg = (i == 0) ? 0x2000 : 0x3000;
1462 reg |= B2055_PADDRV;
0c201cfb 1463 b43_radio_write(dev, reg, val);
53ae8e8c 1464
4d9f46ba
RM		 1465 reg = (i == 0) ?
1466 B43_NPHY_AFECTL_OVER1 :
1467 B43_NPHY_AFECTL_OVER;
1468 b43_phy_set(dev, reg, 0x0200);
1469 }
1470 }
1471 }
53ae8e8c 1472 }
53ae8e8c
RM		 1473}
1474
a3764ef7
RM		 1475static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1476 enum n_rssi_type rssi_type)
9442e5b5 1477{
4d9f46ba 1478 u16 val;
a3764ef7 1479 bool rssi_w1_w2_nb = false;
9442e5b5 1480
a3764ef7
RM		 1481 switch (rssi_type) {
1482 case N_RSSI_W1:
1483 case N_RSSI_W2:
1484 case N_RSSI_NB:
4d9f46ba 1485 val = 0;
a3764ef7
RM		 1486 rssi_w1_w2_nb = true;
1487 break;
1488 case N_RSSI_TBD:
4d9f46ba 1489 val = 1;
a3764ef7
RM		 1490 break;
1491 case N_RSSI_IQ:
4d9f46ba 1492 val = 2;
a3764ef7
RM		 1493 break;
1494 default:
4d9f46ba 1495 val = 3;
a3764ef7 1496 }
9442e5b5 1497
4d9f46ba
RM		 1498 val = (val << 12) | (val << 14);
1499 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1500 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1501
a3764ef7 1502 if (rssi_w1_w2_nb) {
4d9f46ba 1503 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1504 (rssi_type + 1) << 4);
4d9f46ba 1505 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1506 (rssi_type + 1) << 4);
9442e5b5
RM		 1507 }
1508
4d9f46ba
RM		 1509 if (code == 0) {
1510 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1511 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1512 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1513 ~(B43_NPHY_RFCTL_CMD_RXEN |
1514 B43_NPHY_RFCTL_CMD_CORESEL));
1515 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1516 ~(0x1 << 12 |
1517 0x1 << 5 |
1518 0x1 << 1 |
1519 0x1));
1520 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1521 ~B43_NPHY_RFCTL_CMD_START);
1522 udelay(20);
1523 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1524 }
1525 } else {
1526 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1527 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1528 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1529 ~(B43_NPHY_RFCTL_CMD_RXEN |
1530 B43_NPHY_RFCTL_CMD_CORESEL),
1531 (B43_NPHY_RFCTL_CMD_RXEN |
1532 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1533 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1534 (0x1 << 12 |
1535 0x1 << 5 |
1536 0x1 << 1 |
1537 0x1));
1538 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1539 B43_NPHY_RFCTL_CMD_START);
1540 udelay(20);
1541 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1542 }
9442e5b5 1543 }
9442e5b5
RM		 1544}
1545
4d9f46ba 1546/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1547static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1548 enum n_rssi_type type)
d24019ad 1549{
4d9f46ba
RM		 1550 if (dev->phy.rev >= 3)
1551 b43_nphy_rev3_rssi_select(dev, code, type);
1552 else
1553 b43_nphy_rev2_rssi_select(dev, code, type);
1554}
d24019ad 1555
5ecab603 1556/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1557static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1558 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1559{
1560 int i;
d24019ad 1561 for (i = 0; i < 2; i++) {
a3764ef7 1562 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1563 if (i == 0) {
1564 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1565 0xFC, buf[0]);
1566 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1567 0xFC, buf[1]);
1568 } else {
1569 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1570 0xFC, buf[2 * i]);
1571 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1572 0xFC, buf[2 * i + 1]);
1573 }
d24019ad 1574 } else {
5ecab603
RM		 1575 if (i == 0)
1576 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1577 0xF3, buf[0] << 2);
1578 else
1579 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1580 0xF3, buf[2 * i + 1] << 2);
d24019ad 1581 }
d24019ad 1582 }
d24019ad
RM		 1583}
1584
5ecab603 1585/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1586static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1587 s32 *buf, u8 nsamp)
ef5127a4 1588{
5ecab603
RM		 1589 int i;
1590 int out;
1591 u16 save_regs_phy[9];
1592 u16 s[2];
ef5127a4
RM		 1593
1594 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1595 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1596 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1597 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1598 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1599 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1600 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1601 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1602 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1603 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1604 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1605 save_regs_phy[8] = 0;
ef5127a4 1606 } else {
5ecab603
RM		 1607 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1608 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1609 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1610 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1611 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1612 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1613 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1614 save_regs_phy[7] = 0;
1615 save_regs_phy[8] = 0;
1616 }
ef5127a4 1617
a3764ef7 1618 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1619
5ecab603
RM		 1620 if (dev->phy.rev < 2) {
1621 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1622 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1623 }
ef5127a4 1624
5ecab603
RM		 1625 for (i = 0; i < 4; i++)
1626 buf[i] = 0;
1627
1628 for (i = 0; i < nsamp; i++) {
1629 if (dev->phy.rev < 2) {
1630 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1631 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1632 } else {
5ecab603
RM		 1633 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1634 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1635 }
1636
5ecab603
RM		 1637 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1638 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1639 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1640 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1641 }
1642 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1643 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1644
5ecab603
RM		 1645 if (dev->phy.rev < 2)
1646 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1647
5ecab603 1648 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1649 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1650 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1651 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1652 save_regs_phy[2]);
5ecab603 1653 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1654 save_regs_phy[3]);
5ecab603
RM		 1655 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1656 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1657 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1658 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1659 } else {
1660 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1661 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1662 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1663 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1664 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1665 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1666 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1667 }
ef5127a4 1668
5ecab603
RM		 1669 return out;
1670}
ef5127a4 1671
e0c9a021
RM		 1672/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1673static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1674{
39e971ef 1675 struct b43_phy *phy = &dev->phy;
e0c9a021
RM		 1676 struct b43_phy_n *nphy = dev->phy.n;
1677
1678 u16 saved_regs_phy_rfctl[2];
97e2a1a1
RM		 1679 u16 saved_regs_phy[22];
1680 u16 regs_to_store_rev3[] = {
e0c9a021
RM		 1681 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1682 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1683 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1684 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1685 B43_NPHY_RFCTL_CMD,
1686 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1687 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1688 };
97e2a1a1
RM		 1689 u16 regs_to_store_rev7[] = {
1690 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1691 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1692 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1693 0x342, 0x343, 0x346, 0x347,
1694 0x2ff,
1695 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1696 B43_NPHY_RFCTL_CMD,
1697 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1698 0x340, 0x341, 0x344, 0x345,
1699 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1700 };
1701 u16 *regs_to_store;
1702 int regs_amount;
e0c9a021
RM		 1703
1704 u16 class;
1705
1706 u16 clip_state[2];
1707 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1708
1709 u8 vcm_final = 0;
2e1253d6 1710 s32 offset[4];
e0c9a021
RM		 1711 s32 results[8][4] = { };
1712 s32 results_min[4] = { };
1713 s32 poll_results[4] = { };
1714
1715 u16 *rssical_radio_regs = NULL;
1716 u16 *rssical_phy_regs = NULL;
1717
1718 u16 r; /* routing */
1719 u8 rx_core_state;
37859a75 1720 int core, i, j, vcm;
e0c9a021 1721
97e2a1a1
RM		 1722 if (dev->phy.rev >= 7) {
1723 regs_to_store = regs_to_store_rev7;
1724 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1725 } else {
1726 regs_to_store = regs_to_store_rev3;
1727 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1728 }
1729 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1730
e0c9a021
RM		 1731 class = b43_nphy_classifier(dev, 0, 0);
1732 b43_nphy_classifier(dev, 7, 4);
1733 b43_nphy_read_clip_detection(dev, clip_state);
1734 b43_nphy_write_clip_detection(dev, clip_off);
1735
1736 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1737 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
97e2a1a1 1738 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1739 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1740
89e43dad
RM		 1741 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1742 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
97e2a1a1
RM		 1743
1744 if (dev->phy.rev >= 7) {
1745 /* TODO */
1746 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1747 } else {
1748 }
e0c9a021 1749 } else {
97e2a1a1
RM		 1750 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1751 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1752 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1753 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1754 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1755 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1756 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1757 } else {
1758 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1759 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1760 }
e0c9a021
RM		 1761 }
1762
1763 rx_core_state = b43_nphy_get_rx_core_state(dev);
1764 for (core = 0; core < 2; core++) {
1765 if (!(rx_core_state & (1 << core)))
1766 continue;
1767 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1768 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1769 N_RSSI_NB);
1770 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1771 N_RSSI_NB);
37859a75
RM		 1772
1773 /* Grab RSSI results for every possible VCM */
1774 for (vcm = 0; vcm < 8; vcm++) {
97e2a1a1
RM		 1775 if (dev->phy.rev >= 7)
1776 ;
1777 else
1778 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1779 0xE3, vcm << 2);
a3764ef7 1780 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1781 }
37859a75
RM		 1782
1783 /* Find out which VCM got the best results */
cddec902 1784 for (i = 0; i < 4; i += 2) {
37859a75 1785 s32 currd;
e67dd874 1786 s32 mind = 0x100000;
e0c9a021
RM		 1787 s32 minpoll = 249;
1788 u8 minvcm = 0;
1789 if (2 * core != i)
1790 continue;
37859a75
RM		 1791 for (vcm = 0; vcm < 8; vcm++) {
1792 currd = results[vcm][i] * results[vcm][i] +
1793 results[vcm][i + 1] * results[vcm][i];
1794 if (currd < mind) {
1795 mind = currd;
1796 minvcm = vcm;
e0c9a021 1797 }
37859a75
RM		 1798 if (results[vcm][i] < minpoll)
1799 minpoll = results[vcm][i];
e0c9a021
RM		 1800 }
1801 vcm_final = minvcm;
1802 results_min[i] = minpoll;
1803 }
37859a75
RM		 1804
1805 /* Select the best VCM */
97e2a1a1
RM		 1806 if (dev->phy.rev >= 7)
1807 ;
1808 else
1809 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1810 0xE3, vcm_final << 2);
37859a75 1811
e0c9a021
RM		 1812 for (i = 0; i < 4; i++) {
1813 if (core != i / 2)
1814 continue;
1815 offset[i] = -results[vcm_final][i];
1816 if (offset[i] < 0)
1817 offset[i] = -((abs(offset[i]) + 4) / 8);
1818 else
1819 offset[i] = (offset[i] + 4) / 8;
1820 if (results_min[i] == 248)
1821 offset[i] = -32;
1822 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1823 (i / 2 == 0) ? 1 : 2,
6aa38725 1824 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1825 N_RSSI_NB);
e0c9a021
RM		 1826 }
1827 }
37859a75 1828
e0c9a021
RM		 1829 for (core = 0; core < 2; core++) {
1830 if (!(rx_core_state & (1 << core)))
1831 continue;
1832 for (i = 0; i < 2; i++) {
6aa38725
RM		 1833 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1834 N_RAIL_I, i);
1835 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1836 N_RAIL_Q, i);
e0c9a021
RM		 1837 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1838 for (j = 0; j < 4; j++) {
cddec902 1839 if (j / 2 == core) {
e0c9a021 1840 offset[j] = 232 - poll_results[j];
cddec902
RM		 1841 if (offset[j] < 0)
1842 offset[j] = -(abs(offset[j] + 4) / 8);
1843 else
1844 offset[j] = (offset[j] + 4) / 8;
1845 b43_nphy_scale_offset_rssi(dev, 0,
1846 offset[2 * core], core + 1, j % 2, i);
1847 }
e0c9a021
RM		 1848 }
1849 }
1850 }
1851
1852 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1853 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1854
1855 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1856
1857 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1858 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1859 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1860
1861 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1862 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
bc36e994 1863 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
e0c9a021 1864
97e2a1a1 1865 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1866 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1867
1868 /* Store for future configuration */
1869 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1870 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1871 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1872 } else {
1873 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1874 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1875 }
9a98979e
RM		 1876 if (dev->phy.rev >= 7) {
1877 } else {
1878 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1879 B2056_RX_RSSI_MISC);
1880 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1881 B2056_RX_RSSI_MISC);
1882 }
e0c9a021
RM		 1883 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1884 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1885 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1886 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1887 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1888 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1889 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1890 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1891 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1892 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1893 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1894 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1895
1896 /* Remember for which channel we store configuration */
1897 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
39e971ef 1898 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
e0c9a021 1899 else
39e971ef 1900 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
e0c9a021
RM		 1901
1902 /* End of calibration, restore configuration */
1903 b43_nphy_classifier(dev, 7, class);
1904 b43_nphy_write_clip_detection(dev, clip_state);
1905}
1906
5ecab603 1907/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 1908static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 1909{
37859a75 1910 int i, j, vcm;
5ecab603
RM		 1911 u8 state[4];
1912 u8 code, val;
1913 u16 class, override;
1914 u8 regs_save_radio[2];
1915 u16 regs_save_phy[2];
1916
2e1253d6 1917 s32 offset[4];
5ecab603
RM		 1918 u8 core;
1919 u8 rail;
1920
1921 u16 clip_state[2];
1922 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1923 s32 results_min[4] = { };
1924 u8 vcm_final[4] = { };
1925 s32 results[4][4] = { };
1926 s32 miniq[4][2] = { };
1927
a3764ef7 1928 if (type == N_RSSI_NB) {
5ecab603
RM		 1929 code = 0;
1930 val = 6;
a3764ef7 1931 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 1932 code = 25;
1933 val = 4;
1934 } else {
1935 B43_WARN_ON(1);
1936 return;
1937 }
1938
1939 class = b43_nphy_classifier(dev, 0, 0);
1940 b43_nphy_classifier(dev, 7, 4);
1941 b43_nphy_read_clip_detection(dev, clip_state);
1942 b43_nphy_write_clip_detection(dev, clip_off);
1943
1944 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1945 override = 0x140;
1946 else
1947 override = 0x110;
1948
1949 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 1950 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 1951 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 1952 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 1953
1954 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 1955 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 1956 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 1957 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 1958
0c201cfb
RM		 1959 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1960 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 1961 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1962 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 1963 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1964 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 1965
1966 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 1967 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1968 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 1969
37859a75 1970 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 1971 u8 tmp[4];
1972 for (j = 0; j < 4; j++)
37859a75 1973 tmp[j] = vcm;
a3764ef7 1974 if (type != N_RSSI_W2)
5ecab603 1975 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 1976 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 1977 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 1978 for (j = 0; j < 2; j++)
37859a75
RM		 1979 miniq[vcm][j] = min(results[vcm][2 * j],
1980 results[vcm][2 * j + 1]);
5ecab603
RM		 1981 }
1982
1983 for (i = 0; i < 4; i++) {
e67dd874 1984 s32 mind = 0x100000;
5ecab603
RM		 1985 u8 minvcm = 0;
1986 s32 minpoll = 249;
37859a75
RM		 1987 s32 currd;
1988 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 1989 if (type == N_RSSI_NB)
542e15f3 1990 currd = abs(results[vcm][i] - code * 8);
5ecab603 1991 else
37859a75 1992 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 1993
37859a75
RM		 1994 if (currd < mind) {
1995 mind = currd;
1996 minvcm = vcm;
5ecab603
RM		 1997 }
1998
37859a75
RM		 1999 if (results[vcm][i] < minpoll)
2000 minpoll = results[vcm][i];
8e60b044 2001 }
5ecab603
RM		 2002 results_min[i] = minpoll;
2003 vcm_final[i] = minvcm;
2004 }
ef5127a4 2005
a3764ef7 2006 if (type != N_RSSI_W2)
5ecab603 2007 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 2008
5ecab603
RM		 2009 for (i = 0; i < 4; i++) {
2010 offset[i] = (code * 8) - results[vcm_final[i]][i];
2011
2012 if (offset[i] < 0)
2013 offset[i] = -((abs(offset[i]) + 4) / 8);
2014 else
2015 offset[i] = (offset[i] + 4) / 8;
2016
2017 if (results_min[i] == 248)
2018 offset[i] = code - 32;
2019
2020 core = (i / 2) ? 2 : 1;
6aa38725 2021 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 2022
2023 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2024 type);
2025 }
2026
2027 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2028 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2029
2030 switch (state[2]) {
2031 case 1:
a3764ef7 2032 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 2033 break;
2034 case 4:
a3764ef7 2035 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 2036 break;
2037 case 2:
a3764ef7 2038 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2039 break;
2040 default:
a3764ef7 2041 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2042 break;
2043 }
2044
2045 switch (state[3]) {
2046 case 1:
a3764ef7 2047 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 2048 break;
2049 case 4:
a3764ef7 2050 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 2051 break;
2052 default:
a3764ef7 2053 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 2054 break;
2055 }
2056
2057 b43_nphy_rssi_select(dev, 0, type);
2058
2059 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 2060 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 2061 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 2062 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 2063
2064 b43_nphy_classifier(dev, 7, class);
2065 b43_nphy_write_clip_detection(dev, clip_state);
2066 /* Specs don't say about reset here, but it makes wl and b43 dumps
2067 identical, it really seems wl performs this */
2068 b43_nphy_reset_cca(dev);
2069}
2070
5ecab603
RM		 2071/*
2072 * RSSI Calibration
2073 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2074 */
2075static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2076{
2077 if (dev->phy.rev >= 3) {
2078 b43_nphy_rev3_rssi_cal(dev);
2079 } else {
2a2d0589
RM		 2080 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2081 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2082 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 2083 }
2084}
2085
64712095
RM		 2086/**************************************************
2087 * Workarounds
2088 **************************************************/
2089
2090static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2091{
2092 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2093
2094 bool ghz5;
2095 bool ext_lna;
2096 u16 rssi_gain;
2097 struct nphy_gain_ctl_workaround_entry *e;
2098 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2099 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2100
2101 /* Prepare values */
2102 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2103 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 2104 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2105 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 2106 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2107 if (ghz5 && dev->phy.rev >= 5)
2108 rssi_gain = 0x90;
2109 else
2110 rssi_gain = 0x50;
2111
2112 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2113
2114 /* Set Clip 2 detect */
04519dc6
RM		 2115 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2116 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 2117
2118 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2119 0x17);
2120 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2121 0x17);
2122 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2123 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2124 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2125 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2126 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2127 rssi_gain);
2128 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2129 rssi_gain);
2130 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2131 0x17);
2132 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2133 0x17);
2134 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2135 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2136
2137 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2138 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2139 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2140 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2141 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2142 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2143 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2144 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2145 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2146 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2147 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2148 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2149
04519dc6
RM		 2150 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2151 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2152
64712095
RM		 2153 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2154 e->rfseq_init);
64712095 2155
04519dc6
RM		 2156 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2157 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2158 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2159 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2160 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2161 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2162
2163 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2164 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2165 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2166 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2167 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2168 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2169 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2170 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2171 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2172 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2173}
2174
2175static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2176{
2177 struct b43_phy_n *nphy = dev->phy.n;
2178
2179 u8 i, j;
2180 u8 code;
2181 u16 tmp;
2182 u8 rfseq_events[3] = { 6, 8, 7 };
2183 u8 rfseq_delays[3] = { 10, 30, 1 };
2184
2185 /* Set Clip 2 detect */
2186 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2187 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2188
2189 /* Set narrowband clip threshold */
2190 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2191 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2192
bee6d4b2 2193 if (!b43_is_40mhz(dev)) {
64712095
RM		 2194 /* Set dwell lengths */
2195 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2196 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2197 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2198 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2199 }
2200
2201 /* Set wideband clip 2 threshold */
2202 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2203 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2204 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2205 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2206
bee6d4b2 2207 if (!b43_is_40mhz(dev)) {
64712095
RM		 2208 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2209 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2210 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2211 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2212 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2213 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2214 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2215 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2216 }
2217
2218 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2219
2220 if (nphy->gain_boost) {
2221 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
bee6d4b2 2222 b43_is_40mhz(dev))
64712095
RM		 2223 code = 4;
2224 else
2225 code = 5;
2226 } else {
bee6d4b2 2227 code = b43_is_40mhz(dev) ? 6 : 7;
64712095
RM		 2228 }
2229
2230 /* Set HPVGA2 index */
2231 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2232 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2233 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2234 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2235
2236 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2237 /* specs say about 2 loops, but wl does 4 */
2238 for (i = 0; i < 4; i++)
2239 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2240
2241 b43_nphy_adjust_lna_gain_table(dev);
2242
2243 if (nphy->elna_gain_config) {
2244 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2245 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2246 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2247 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2248 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2249
2250 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2251 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2252 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2253 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2254 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2255
2256 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2257 /* specs say about 2 loops, but wl does 4 */
2258 for (i = 0; i < 4; i++)
2259 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2260 (code << 8 | 0x74));
2261 }
2262
2263 if (dev->phy.rev == 2) {
2264 for (i = 0; i < 4; i++) {
2265 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2266 (0x0400 * i) + 0x0020);
2267 for (j = 0; j < 21; j++) {
2268 tmp = j * (i < 2 ? 3 : 1);
2269 b43_phy_write(dev,
2270 B43_NPHY_TABLE_DATALO, tmp);
2271 }
2272 }
ef5127a4 2273 }
64712095
RM		 2274
2275 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2276 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2277 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2278 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2279
2280 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2281 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2282}
2283
2284/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2285static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2286{
d11d354b
RM		 2287 if (dev->phy.rev >= 7)
2288 ; /* TODO */
2289 else if (dev->phy.rev >= 3)
64712095
RM		 2290 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2291 else
2292 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2293}
2294
d11d354b
RM		 2295/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2296static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2297{
2298 if (!offset)
bee6d4b2 2299 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
d11d354b
RM		 2300 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2301}
2302
2303static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2304{
2305 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2306 struct b43_phy *phy = &dev->phy;
2307
2308 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2309 0x1F };
2310 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2311
2312 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2313 u8 ntab7_138_146[] = { 0x11, 0x11 };
2314 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2315
2316 u16 lpf_20, lpf_40, lpf_11b;
2317 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2318 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2319 bool rccal_ovrd = false;
2320
2321 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2322 u16 bias, conv, filt;
2323
2324 u32 tmp32;
2325 u8 core;
2326
2327 if (phy->rev == 7) {
2328 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2329 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2330 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2331 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2332 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2333 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2334 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2335 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2336 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2337 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2338 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2339 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2340 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2341 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2342 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2343 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2344 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2345 }
2346 if (phy->rev <= 8) {
04519dc6
RM		 2347 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2348 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2349 }
2350 if (phy->rev >= 8)
2351 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2352
2353 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2354 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2355 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2356 tmp32 &= 0xffffff;
2357 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2358 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2359 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2360
2361 if (b43_nphy_ipa(dev))
2362 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2363 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2364
04519dc6
RM		 2365 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2366 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2367
2368 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2369 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2370 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2371 if (b43_nphy_ipa(dev)) {
bee6d4b2 2372 if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
d11d354b
RM		 2373 phy->radio_rev == 7 || phy->radio_rev == 8) {
2374 bcap_val = b43_radio_read(dev, 0x16b);
2375 scap_val = b43_radio_read(dev, 0x16a);
2376 scap_val_11b = scap_val;
2377 bcap_val_11b = bcap_val;
bee6d4b2 2378 if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
d11d354b
RM		 2379 scap_val_11n_20 = scap_val;
2380 bcap_val_11n_20 = bcap_val;
2381 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2382 rccal_ovrd = true;
2383 } else { /* Rev 7/8 */
2384 lpf_20 = 4;
2385 lpf_11b = 1;
2386 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2387 scap_val_11n_20 = 0xc;
2388 bcap_val_11n_20 = 0xc;
2389 scap_val_11n_40 = 0xa;
2390 bcap_val_11n_40 = 0xa;
2391 } else {
2392 scap_val_11n_20 = 0x14;
2393 bcap_val_11n_20 = 0x14;
2394 scap_val_11n_40 = 0xf;
2395 bcap_val_11n_40 = 0xf;
2396 }
2397 rccal_ovrd = true;
2398 }
2399 }
2400 } else {
2401 if (phy->radio_rev == 5) {
2402 lpf_20 = 1;
2403 lpf_40 = 3;
2404 bcap_val = b43_radio_read(dev, 0x16b);
2405 scap_val = b43_radio_read(dev, 0x16a);
2406 scap_val_11b = scap_val;
2407 bcap_val_11b = bcap_val;
2408 scap_val_11n_20 = 0x11;
2409 scap_val_11n_40 = 0x11;
2410 bcap_val_11n_20 = 0x13;
2411 bcap_val_11n_40 = 0x13;
2412 rccal_ovrd = true;
2413 }
2414 }
2415 if (rccal_ovrd) {
2416 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2417 (scap_val_11b << 3) |
2418 lpf_11b;
2419 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2420 (scap_val_11n_20 << 3) |
2421 lpf_20;
2422 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2423 (scap_val_11n_40 << 3) |
2424 lpf_40;
2425 for (core = 0; core < 2; core++) {
2426 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2427 rx2tx_lut_20_11b);
2428 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2429 rx2tx_lut_20_11n);
2430 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2431 rx2tx_lut_20_11n);
2432 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2433 rx2tx_lut_40_11n);
2434 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2435 rx2tx_lut_40_11n);
2436 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2437 rx2tx_lut_40_11n);
2438 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2439 rx2tx_lut_40_11n);
2440 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2441 rx2tx_lut_40_11n);
2442 }
78ae7532 2443 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2444 }
2445 b43_phy_write(dev, 0x32F, 0x3);
2446 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2447 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2448
2449 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2450 if (sprom->revision &&
2451 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2452 b43_radio_write(dev, 0x5, 0x05);
2453 b43_radio_write(dev, 0x6, 0x30);
2454 b43_radio_write(dev, 0x7, 0x00);
2455 b43_radio_set(dev, 0x4f, 0x1);
2456 b43_radio_set(dev, 0xd4, 0x1);
2457 bias = 0x1f;
2458 conv = 0x6f;
2459 filt = 0xaa;
2460 } else {
2461 bias = 0x2b;
2462 conv = 0x7f;
2463 filt = 0xee;
2464 }
2465 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2466 for (core = 0; core < 2; core++) {
2467 if (core == 0) {
2468 b43_radio_write(dev, 0x5F, bias);
2469 b43_radio_write(dev, 0x64, conv);
2470 b43_radio_write(dev, 0x66, filt);
2471 } else {
2472 b43_radio_write(dev, 0xE8, bias);
2473 b43_radio_write(dev, 0xE9, conv);
2474 b43_radio_write(dev, 0xEB, filt);
2475 }
2476 }
2477 }
2478 }
2479
2480 if (b43_nphy_ipa(dev)) {
2481 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2482 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2483 phy->radio_rev == 6) {
2484 for (core = 0; core < 2; core++) {
2485 if (core == 0)
2486 b43_radio_write(dev, 0x51,
2487 0x7f);
2488 else
2489 b43_radio_write(dev, 0xd6,
2490 0x7f);
2491 }
2492 }
2493 if (phy->radio_rev == 3) {
2494 for (core = 0; core < 2; core++) {
2495 if (core == 0) {
2496 b43_radio_write(dev, 0x64,
2497 0x13);
2498 b43_radio_write(dev, 0x5F,
2499 0x1F);
2500 b43_radio_write(dev, 0x66,
2501 0xEE);
2502 b43_radio_write(dev, 0x59,
2503 0x8A);
2504 b43_radio_write(dev, 0x80,
2505 0x3E);
2506 } else {
2507 b43_radio_write(dev, 0x69,
2508 0x13);
2509 b43_radio_write(dev, 0xE8,
2510 0x1F);
2511 b43_radio_write(dev, 0xEB,
2512 0xEE);
2513 b43_radio_write(dev, 0xDE,
2514 0x8A);
2515 b43_radio_write(dev, 0x105,
2516 0x3E);
2517 }
2518 }
2519 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
bee6d4b2 2520 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2521 b43_radio_write(dev, 0x5F, 0x14);
2522 b43_radio_write(dev, 0xE8, 0x12);
2523 } else {
2524 b43_radio_write(dev, 0x5F, 0x16);
2525 b43_radio_write(dev, 0xE8, 0x16);
2526 }
2527 }
2528 } else {
39e971ef 2529 u16 freq = phy->chandef->chan->center_freq;
d11d354b
RM		 2530 if ((freq >= 5180 && freq <= 5230) ||
2531 (freq >= 5745 && freq <= 5805)) {
2532 b43_radio_write(dev, 0x7D, 0xFF);
2533 b43_radio_write(dev, 0xFE, 0xFF);
2534 }
2535 }
2536 } else {
2537 if (phy->radio_rev != 5) {
2538 for (core = 0; core < 2; core++) {
2539 if (core == 0) {
2540 b43_radio_write(dev, 0x5c, 0x61);
2541 b43_radio_write(dev, 0x51, 0x70);
2542 } else {
2543 b43_radio_write(dev, 0xe1, 0x61);
2544 b43_radio_write(dev, 0xd6, 0x70);
2545 }
2546 }
2547 }
2548 }
2549
2550 if (phy->radio_rev == 4) {
2551 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2552 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2553 for (core = 0; core < 2; core++) {
2554 if (core == 0) {
2555 b43_radio_write(dev, 0x1a1, 0x00);
2556 b43_radio_write(dev, 0x1a2, 0x3f);
2557 b43_radio_write(dev, 0x1a6, 0x3f);
2558 } else {
2559 b43_radio_write(dev, 0x1a7, 0x00);
2560 b43_radio_write(dev, 0x1ab, 0x3f);
2561 b43_radio_write(dev, 0x1ac, 0x3f);
2562 }
2563 }
2564 } else {
2565 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2566 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2567 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2568 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2569
2570 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2571 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2572 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2573 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2574 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2575 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2576
2577 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2578 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2579 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2580 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2581 }
2582
2583 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2584
2585 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2586 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2587 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2588 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2589 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2590 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2591 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2592
bee6d4b2 2593 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2594 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2595 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2596 } else {
2597 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2598 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2599 }
2600
2601 b43_nphy_gain_ctl_workarounds(dev);
2602
2603 /* TODO
2604 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2605 aux_adc_vmid_rev7_core0);
2606 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2607 aux_adc_vmid_rev7_core1);
2608 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2609 aux_adc_gain_rev7);
2610 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2611 aux_adc_gain_rev7);
2612 */
2613}
2614
73d07a39 2615static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2616{
0eff8fcd 2617 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2618 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2619
0eff8fcd 2620 /* TX to RX */
c378bb97
RM		 2621 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2622 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 2623 /* RX to TX */
2624 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2625 0x1F };
2626 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2627 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2628 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2629
c378bb97
RM		 2630 u16 vmids[5][4] = {
2631 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2632 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2633 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2634 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2635 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2636 };
2637 u16 gains[5][4] = {
2638 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2639 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2640 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2641 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2642 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2643 };
2644 u16 *vmid, *gain;
2645
2646 u8 pdet_range;
ba9a6214
RM		 2647 u16 tmp16;
2648 u32 tmp32;
2649
04519dc6
RM		 2650 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2651 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2652
73d07a39
RM		 2653 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2654 tmp32 &= 0xffffff;
2655 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2656
73d07a39
RM		 2657 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2658 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2659 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2660 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2661 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2662 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2663
04519dc6
RM		 2664 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2665 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2666
0eff8fcd 2667 /* TX to RX */
c56da252
RM		 2668 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2669 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2670
2671 /* RX to TX */
2672 if (b43_nphy_ipa(dev))
c56da252
RM		 2673 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2674 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2675 if (nphy->hw_phyrxchain != 3 &&
2676 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2677 if (b43_nphy_ipa(dev)) {
2678 rx2tx_delays[5] = 59;
2679 rx2tx_delays[6] = 1;
2680 rx2tx_events[7] = 0x1F;
2681 }
fa0f2b38 2682 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2683 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2684 }
ba9a6214 2685
73d07a39
RM		 2686 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2687 0x2 : 0x9C40;
2688 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2689
04519dc6 2690 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2691
bee6d4b2 2692 if (!b43_is_40mhz(dev)) {
fa0f2b38
RM		 2693 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2694 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2695 } else {
2696 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2697 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2698 }
ba9a6214 2699
3ccd0957 2700 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2701
c56da252
RM		 2702 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2703 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2704
c378bb97
RM		 2705 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2706 pdet_range = sprom->fem.ghz2.pdet_range;
2707 else
2708 pdet_range = sprom->fem.ghz5.pdet_range;
2709 vmid = vmids[min_t(u16, pdet_range, 4)];
2710 gain = gains[min_t(u16, pdet_range, 4)];
2711 switch (pdet_range) {
2712 case 3:
2713 if (!(dev->phy.rev >= 4 &&
2714 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2715 break;
2716 /* FALL THROUGH */
2717 case 0:
2718 case 1:
2719 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2720 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2721 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2722 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2723 break;
2724 case 2:
2725 if (dev->phy.rev >= 6) {
2726 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2727 vmid[3] = 0x94;
2728 else
2729 vmid[3] = 0x8e;
2730 gain[3] = 3;
2731 } else if (dev->phy.rev == 5) {
2732 vmid[3] = 0x84;
2733 gain[3] = 2;
2734 }
2735 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2736 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2737 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2738 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2739 break;
2740 case 4:
2741 case 5:
2742 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2743 if (pdet_range == 4) {
2744 vmid[3] = 0x8e;
2745 tmp16 = 0x96;
2746 gain[3] = 0x2;
2747 } else {
2748 vmid[3] = 0x89;
2749 tmp16 = 0x89;
2750 gain[3] = 0;
2751 }
2752 } else {
2753 if (pdet_range == 4) {
2754 vmid[3] = 0x89;
2755 tmp16 = 0x8b;
2756 gain[3] = 0x2;
2757 } else {
2758 vmid[3] = 0x74;
2759 tmp16 = 0x70;
2760 gain[3] = 0;
2761 }
2762 }
2763 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2764 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2765 vmid[3] = tmp16;
2766 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2767 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2768 break;
2769 }
ba9a6214 2770
73d07a39
RM		 2771 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2772 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2773 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2774 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2775 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2776 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2777 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2778 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2779 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2780 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2781 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2782 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2783
2784 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2785
2786 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2787 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2788 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2789 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2790 tmp32 = 0x00088888;
2791 else
2792 tmp32 = 0x88888888;
2793 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2794 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2795 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2796
2797 if (dev->phy.rev == 4 &&
fa0f2b38 2798 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2799 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2800 0x70);
2801 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2802 0x70);
2803 }
ba9a6214 2804
fa0f2b38 2805 /* Dropped probably-always-true condition */
04519dc6
RM		 2806 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2807 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
bc36e994 2808 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
04519dc6
RM		 2809 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2810 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2811 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2812 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2813 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2814 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2815 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2816 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2817 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 2818
2819 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2820 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2821}
ba9a6214 2822
73d07a39
RM		 2823static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2824{
2825 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2826 struct b43_phy *phy = &dev->phy;
2827 struct b43_phy_n *nphy = phy->n;
ba9a6214 2828
73d07a39
RM		 2829 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2830 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2831
73d07a39
RM		 2832 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2833 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2834
fa0f2b38 2835 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 2836 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 2837 delays1[0] = 0x1;
2838 delays1[5] = 0x14;
2839 }
2840
73d07a39
RM		 2841 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2842 nphy->band5g_pwrgain) {
2843 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2844 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2845 } else {
73d07a39
RM		 2846 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2847 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2848 }
28fd7daa 2849
73d07a39
RM		 2850 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2851 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2852 if (dev->phy.rev < 3) {
2853 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2854 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2855 }
73d07a39
RM		 2856
2857 if (dev->phy.rev < 2) {
2858 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2859 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2860 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2861 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2862 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2863 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2864 }
28fd7daa 2865
73d07a39
RM		 2866 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2867 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2868 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2869 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2870
73d07a39
RM		 2871 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2872 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2873
3ccd0957 2874 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2875
2876 if (dev->phy.rev < 2) {
2877 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2878 b43_hf_write(dev, b43_hf_read(dev) |
2879 B43_HF_MLADVW);
2880 } else if (dev->phy.rev == 2) {
2881 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2882 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2883 }
28fd7daa 2884
73d07a39
RM		 2885 if (dev->phy.rev < 2)
2886 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2887 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2888
2889 /* Set phase track alpha and beta */
2890 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2891 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2892 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2893 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2894 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2895 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2896
fa0f2b38
RM		 2897 if (dev->phy.rev < 3) {
2898 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2899 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2900 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2901 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2902 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2903 }
73d07a39
RM		 2904
2905 if (dev->phy.rev == 2)
2906 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2907 B43_NPHY_FINERX2_CGC_DECGC);
2908}
28fd7daa 2909
73d07a39
RM		 2910/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2911static void b43_nphy_workarounds(struct b43_wldev *dev)
2912{
2913 struct b43_phy *phy = &dev->phy;
2914 struct b43_phy_n *nphy = phy->n;
28fd7daa 2915
73d07a39
RM		 2916 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2917 b43_nphy_classifier(dev, 1, 0);
2918 else
2919 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2920
73d07a39
RM		 2921 if (nphy->hang_avoid)
2922 b43_nphy_stay_in_carrier_search(dev, 1);
2923
2924 b43_phy_set(dev, B43_NPHY_IQFLIP,
2925 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2926
d11d354b
RM		 2927 if (dev->phy.rev >= 7)
2928 b43_nphy_workarounds_rev7plus(dev);
2929 else if (dev->phy.rev >= 3)
73d07a39
RM		 2930 b43_nphy_workarounds_rev3plus(dev);
2931 else
2932 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2933
2934 if (nphy->hang_avoid)
2935 b43_nphy_stay_in_carrier_search(dev, 0);
2936}
2937
9dd4d9b9
RM		 2938/**************************************************
2939 * Tx/Rx common
2940 **************************************************/
2941
2942/*
2943 * Transmits a known value for LO calibration
2944 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2945 */
2946static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
ed03033e 2947 bool iqmode, bool dac_test, bool modify_bbmult)
9dd4d9b9
RM		 2948{
2949 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2950 if (samp == 0)
2951 return -1;
ed03033e
RM		 2952 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test,
2953 modify_bbmult);
9dd4d9b9
RM		 2954 return 0;
2955}
2956
2957/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2958static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2959{
2960 struct b43_phy_n *nphy = dev->phy.n;
2961
2962 bool override = false;
2963 u16 chain = 0x33;
2964
2965 if (nphy->txrx_chain == 0) {
2966 chain = 0x11;
2967 override = true;
2968 } else if (nphy->txrx_chain == 1) {
2969 chain = 0x22;
2970 override = true;
2971 }
2972
2973 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2974 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2975 chain);
2976
2977 if (override)
2978 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2979 B43_NPHY_RFSEQMODE_CAOVER);
2980 else
2981 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2982 ~B43_NPHY_RFSEQMODE_CAOVER);
2983}
2984
2985/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2986static void b43_nphy_stop_playback(struct b43_wldev *dev)
2987{
2988 struct b43_phy_n *nphy = dev->phy.n;
2989 u16 tmp;
2990
2991 if (nphy->hang_avoid)
2992 b43_nphy_stay_in_carrier_search(dev, 1);
2993
2994 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2995 if (tmp & 0x1)
2996 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2997 else if (tmp & 0x2)
2998 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2999
3000 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3001
3002 if (nphy->bb_mult_save & 0x80000000) {
3003 tmp = nphy->bb_mult_save & 0xFFFF;
3004 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3005 nphy->bb_mult_save = 0;
3006 }
3007
3008 if (nphy->hang_avoid)
3009 b43_nphy_stay_in_carrier_search(dev, 0);
3010}
3011
3012/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3013static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3014 struct nphy_txgains target,
3015 struct nphy_iqcal_params *params)
3016{
3017 int i, j, indx;
3018 u16 gain;
3019
3020 if (dev->phy.rev >= 3) {
3021 params->txgm = target.txgm[core];
3022 params->pga = target.pga[core];
3023 params->pad = target.pad[core];
3024 params->ipa = target.ipa[core];
3025 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
3026 (params->pad << 4) | (params->ipa);
3027 for (j = 0; j < 5; j++)
3028 params->ncorr[j] = 0x79;
3029 } else {
3030 gain = (target.pad[core]) | (target.pga[core] << 4) |
3031 (target.txgm[core] << 8);
3032
3033 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3034 1 : 0;
3035 for (i = 0; i < 9; i++)
3036 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3037 break;
3038 i = min(i, 8);
3039
3040 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3041 params->pga = tbl_iqcal_gainparams[indx][i][2];
3042 params->pad = tbl_iqcal_gainparams[indx][i][3];
3043 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3044 (params->pad << 2);
3045 for (j = 0; j < 4; j++)
3046 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3047 }
3048}
3049
884a5228 3050/**************************************************
104cfa88 3051 * Tx and Rx
884a5228 3052 **************************************************/
5f6393ec 3053
884a5228
RM		 3054static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3055{//TODO
3056}
59af099b 3057
884a5228
RM		 3058static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3059 bool ignore_tssi)
3060{//TODO
3061 return B43_TXPWR_RES_DONE;
3062}
59af099b 3063
161d540c
RM		 3064/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3065static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3066{
3067 struct b43_phy_n *nphy = dev->phy.n;
3068 u8 i;
c9c0d9ec
RM		 3069 u16 bmask, val, tmp;
3070 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 3071
161d540c
RM		 3072 if (nphy->hang_avoid)
3073 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 3074
161d540c
RM		 3075 nphy->txpwrctrl = enable;
3076 if (!enable) {
c9c0d9ec
RM		 3077 if (dev->phy.rev >= 3 &&
3078 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3079 (B43_NPHY_TXPCTL_CMD_COEFF |
3080 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3081 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3082 /* We disable enabled TX pwr ctl, save it's state */
3083 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3084 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3085 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3086 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3087 }
59af099b 3088
161d540c
RM		 3089 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3090 for (i = 0; i < 84; i++)
3091 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3092
161d540c
RM		 3093 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3094 for (i = 0; i < 84; i++)
3095 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3096
161d540c
RM		 3097 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3098 if (dev->phy.rev >= 3)
3099 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3100 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 3101
161d540c
RM		 3102 if (dev->phy.rev >= 3) {
3103 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3104 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3105 } else {
3106 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3107 }
10a79873 3108
161d540c
RM		 3109 if (dev->phy.rev == 2)
3110 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3111 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3112 else if (dev->phy.rev < 2)
3113 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3114 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 3115
bee6d4b2 3116 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3117 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 3118 } else {
c9c0d9ec
RM		 3119 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3120 nphy->adj_pwr_tbl);
3121 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3122 nphy->adj_pwr_tbl);
10a79873 3123
c9c0d9ec
RM		 3124 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3125 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3126 /* wl does useless check for "enable" param here */
3127 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3128 if (dev->phy.rev >= 3) {
3129 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3130 if (val)
3131 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3132 }
3133 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3134
c9c0d9ec
RM		 3135 if (band == IEEE80211_BAND_5GHZ) {
3136 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3137 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3138 if (dev->phy.rev > 1)
3139 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3140 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3141 0x64);
3142 }
10a79873 3143
c9c0d9ec
RM		 3144 if (dev->phy.rev >= 3) {
3145 if (nphy->tx_pwr_idx[0] != 128 &&
3146 nphy->tx_pwr_idx[1] != 128) {
3147 /* Recover TX pwr ctl state */
3148 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3149 ~B43_NPHY_TXPCTL_CMD_INIT,
3150 nphy->tx_pwr_idx[0]);
3151 if (dev->phy.rev > 1)
3152 b43_phy_maskset(dev,
3153 B43_NPHY_TXPCTL_INIT,
3154 ~0xff, nphy->tx_pwr_idx[1]);
3155 }
3156 }
10a79873 3157
c9c0d9ec
RM		 3158 if (dev->phy.rev >= 3) {
3159 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3160 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3161 } else {
3162 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3163 }
10a79873 3164
c9c0d9ec
RM		 3165 if (dev->phy.rev == 2)
3166 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3167 else if (dev->phy.rev < 2)
3168 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3169
bee6d4b2 3170 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3171 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3172
c002831a 3173 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3174 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3175 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3176 }
10a79873 3177 }
10a79873 3178
161d540c
RM		 3179 if (nphy->hang_avoid)
3180 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3181}
3182
161d540c 3183/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3184static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91 3185{
39e971ef 3186 struct b43_phy *phy = &dev->phy;
6dcd9d91 3187 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3188 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3189
161d540c
RM		 3190 u8 txpi[2], bbmult, i;
3191 u16 tmp, radio_gain, dac_gain;
39e971ef 3192 u16 freq = phy->chandef->chan->center_freq;
161d540c
RM		 3193 u32 txgain;
3194 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3195
3196 if (nphy->hang_avoid)
161d540c 3197 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3198
dd5f13b8
RM		 3199 if (dev->phy.rev >= 7) {
3200 txpi[0] = txpi[1] = 30;
3201 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3202 txpi[0] = 40;
3203 txpi[1] = 40;
3204 } else if (sprom->revision < 4) {
3205 txpi[0] = 72;
3206 txpi[1] = 72;
3207 } else {
3208 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3209 txpi[0] = sprom->txpid2g[0];
3210 txpi[1] = sprom->txpid2g[1];
3211 } else if (freq >= 4900 && freq < 5100) {
3212 txpi[0] = sprom->txpid5gl[0];
3213 txpi[1] = sprom->txpid5gl[1];
3214 } else if (freq >= 5100 && freq < 5500) {
3215 txpi[0] = sprom->txpid5g[0];
3216 txpi[1] = sprom->txpid5g[1];
3217 } else if (freq >= 5500) {
3218 txpi[0] = sprom->txpid5gh[0];
3219 txpi[1] = sprom->txpid5gh[1];
3220 } else {
3221 txpi[0] = 91;
3222 txpi[1] = 91;
6dcd9d91
RM		 3223 }
3224 }
dd5f13b8 3225 if (dev->phy.rev < 7 &&
9bd28571 3226 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3227 txpi[0] = txpi[1] = 91;
6dcd9d91 3228
161d540c
RM		 3229 /*
3230 for (i = 0; i < 2; i++) {
3231 nphy->txpwrindex[i].index_internal = txpi[i];
3232 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3233 }
161d540c 3234 */
75377b24 3235
161d540c 3236 for (i = 0; i < 2; i++) {
aeab5751
RM		 3237 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3238
3239 if (dev->phy.rev >= 3)
161d540c 3240 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3241 else
161d540c 3242 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3243
dd5f13b8
RM		 3244 if (dev->phy.rev >= 7)
3245 dac_gain = (txgain >> 8) & 0x7;
3246 else
3247 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3248 bbmult = txgain & 0xFF;
75377b24 3249
161d540c
RM		 3250 if (dev->phy.rev >= 3) {
3251 if (i == 0)
3252 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3253 else
3254 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3255 } else {
3256 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3257 }
75377b24 3258
161d540c
RM		 3259 if (i == 0)
3260 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3261 else
3262 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3263
44f4008b 3264 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3265
44f4008b 3266 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3267 if (i == 0)
3268 tmp = (tmp & 0x00FF) | (bbmult << 8);
3269 else
3270 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3271 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3272
0eff8fcd
RM		 3273 if (b43_nphy_ipa(dev)) {
3274 u32 tmp32;
3275 u16 reg = (i == 0) ?
3276 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3277 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3278 576 + txpi[i]));
0eff8fcd
RM		 3279 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3280 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3281 }
3282 }
75377b24 3283
161d540c 3284 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3285
161d540c
RM		 3286 if (nphy->hang_avoid)
3287 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3288}
67cbc3ed 3289
3dda07b6
RM		 3290static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3291{
3292 struct b43_phy *phy = &dev->phy;
3293
3294 u8 core;
3295 u16 r; /* routing */
3296
3297 if (phy->rev >= 7) {
3298 for (core = 0; core < 2; core++) {
3299 r = core ? 0x190 : 0x170;
3300 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3301 b43_radio_write(dev, r + 0x5, 0x5);
3302 b43_radio_write(dev, r + 0x9, 0xE);
3303 if (phy->rev != 5)
3304 b43_radio_write(dev, r + 0xA, 0);
3305 if (phy->rev != 7)
3306 b43_radio_write(dev, r + 0xB, 1);
3307 else
3308 b43_radio_write(dev, r + 0xB, 0x31);
3309 } else {
3310 b43_radio_write(dev, r + 0x5, 0x9);
3311 b43_radio_write(dev, r + 0x9, 0xC);
3312 b43_radio_write(dev, r + 0xB, 0x0);
3313 if (phy->rev != 5)
3314 b43_radio_write(dev, r + 0xA, 1);
3315 else
3316 b43_radio_write(dev, r + 0xA, 0x31);
3317 }
3318 b43_radio_write(dev, r + 0x6, 0);
3319 b43_radio_write(dev, r + 0x7, 0);
3320 b43_radio_write(dev, r + 0x8, 3);
3321 b43_radio_write(dev, r + 0xC, 0);
3322 }
3323 } else {
3324 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3325 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3326 else
3327 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3328 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3329 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3330
3331 for (core = 0; core < 2; core++) {
3332 r = core ? B2056_TX1 : B2056_TX0;
3333
3334 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3335 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3336 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3337 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3338 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3339 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3340 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3341 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3342 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3343 0x5);
3344 if (phy->rev != 5)
3345 b43_radio_write(dev, r | B2056_TX_TSSIA,
3346 0x00);
3347 if (phy->rev >= 5)
3348 b43_radio_write(dev, r | B2056_TX_TSSIG,
3349 0x31);
3350 else
3351 b43_radio_write(dev, r | B2056_TX_TSSIG,
3352 0x11);
3353 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3354 0xE);
3355 } else {
3356 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3357 0x9);
3358 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3359 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3360 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3361 0xC);
3362 }
3363 }
3364 }
3365}
3366
3367/*
3368 * Stop radio and transmit known signal. Then check received signal strength to
3369 * get TSSI (Transmit Signal Strength Indicator).
3370 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3371 */
3372static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3373{
3374 struct b43_phy *phy = &dev->phy;
3375 struct b43_phy_n *nphy = dev->phy.n;
3376
3377 u32 tmp;
3378 s32 rssi[4] = { };
3379
3380 /* TODO: check if we can transmit */
3381
3382 if (b43_nphy_ipa(dev))
3383 b43_nphy_ipa_internal_tssi_setup(dev);
3384
3385 if (phy->rev >= 7)
78ae7532 3386 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3387 else if (phy->rev >= 3)
78ae7532 3388 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3389
3390 b43_nphy_stop_playback(dev);
ed03033e 3391 b43_nphy_tx_tone(dev, 4000, 0, false, false, false);
3dda07b6 3392 udelay(20);
a3764ef7 3393 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3394 b43_nphy_stop_playback(dev);
a3764ef7 3395 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6
RM		 3396
3397 if (phy->rev >= 7)
78ae7532 3398 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3399 else if (phy->rev >= 3)
78ae7532 3400 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6
RM		 3401
3402 if (phy->rev >= 3) {
3403 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3404 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3405 } else {
3406 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3407 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3408 }
3409 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3410 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3411}
3412
d3fd8bf7
RM		 3413/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3414static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3415{
3416 struct b43_phy_n *nphy = dev->phy.n;
3417
3418 u8 idx, delta;
3419 u8 i, stf_mode;
3420
55757927
RM		 3421 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3422 * 21 groups, each containing 4 entries.
3423 *
3424 * First group has entries for CCK modulation.
3425 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3426 *
3427 * Group 0 is for CCK
3428 * Groups 1..4 use BPSK (group per coding rate)
3429 * Groups 5..8 use QPSK (group per coding rate)
3430 * Groups 9..12 use 16-QAM (group per coding rate)
3431 * Groups 13..16 use 64-QAM (group per coding rate)
3432 * Groups 17..20 are unknown
3433 */
3434
d3fd8bf7
RM		 3435 for (i = 0; i < 4; i++)
3436 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3437
3438 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3439 delta = 0;
3440 switch (stf_mode) {
3441 case 0:
bee6d4b2 3442 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
d3fd8bf7
RM		 3443 idx = 68;
3444 } else {
3445 delta = 1;
bee6d4b2 3446 idx = b43_is_40mhz(dev) ? 52 : 4;
d3fd8bf7
RM		 3447 }
3448 break;
3449 case 1:
bee6d4b2 3450 idx = b43_is_40mhz(dev) ? 76 : 28;
d3fd8bf7
RM		 3451 break;
3452 case 2:
bee6d4b2 3453 idx = b43_is_40mhz(dev) ? 84 : 36;
d3fd8bf7
RM		 3454 break;
3455 case 3:
bee6d4b2 3456 idx = b43_is_40mhz(dev) ? 92 : 44;
d3fd8bf7
RM		 3457 break;
3458 }
3459
3460 for (i = 0; i < 20; i++) {
3461 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3462 nphy->tx_power_offset[idx];
3463 if (i == 0)
3464 idx += delta;
3465 if (i == 14)
3466 idx += 1 - delta;
3467 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3468 i == 13)
3469 idx += 1;
3470 }
3471 }
3472}
3473
3474/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3475static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3476{
39e971ef 3477 struct b43_phy *phy = &dev->phy;
d3fd8bf7
RM		 3478 struct b43_phy_n *nphy = dev->phy.n;
3479 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3480
3481 s16 a1[2], b0[2], b1[2];
3482 u8 idle[2];
3483 s8 target[2];
3484 s32 num, den, pwr;
3485 u32 regval[64];
3486
39e971ef 3487 u16 freq = phy->chandef->chan->center_freq;
d3fd8bf7
RM		 3488 u16 tmp;
3489 u16 r; /* routing */
3490 u8 i, c;
3491
3492 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3493 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3494 b43_read32(dev, B43_MMIO_MACCTL);
3495 udelay(1);
3496 }
3497
3498 if (nphy->hang_avoid)
3499 b43_nphy_stay_in_carrier_search(dev, true);
3500
3501 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3502 if (dev->phy.rev >= 3)
3503 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3504 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3505 else
3506 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3507 B43_NPHY_TXPCTL_CMD_PCTLEN);
3508
3509 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3510 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3511
3512 if (sprom->revision < 4) {
3513 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3514 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3515 target[0] = target[1] = 52;
3516 a1[0] = a1[1] = -424;
3517 b0[0] = b0[1] = 5612;
3518 b1[0] = b1[1] = -1393;
3519 } else {
3520 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3521 for (c = 0; c < 2; c++) {
3522 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3523 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3524 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3525 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3526 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3527 }
3528 } else if (freq >= 4900 && freq < 5100) {
3529 for (c = 0; c < 2; c++) {
3530 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3531 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3532 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3533 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3534 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3535 }
3536 } else if (freq >= 5100 && freq < 5500) {
3537 for (c = 0; c < 2; c++) {
3538 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3539 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3540 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3541 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3542 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3543 }
3544 } else if (freq >= 5500) {
3545 for (c = 0; c < 2; c++) {
3546 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3547 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3548 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3549 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3550 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3551 }
3552 } else {
3553 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3554 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3555 target[0] = target[1] = 52;
3556 a1[0] = a1[1] = -424;
3557 b0[0] = b0[1] = 5612;
3558 b1[0] = b1[1] = -1393;
3559 }
3560 }
3561 /* target[0] = target[1] = nphy->tx_power_max; */
3562
3563 if (dev->phy.rev >= 3) {
3564 if (sprom->fem.ghz2.tssipos)
3565 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3566 if (dev->phy.rev >= 7) {
3567 for (c = 0; c < 2; c++) {
3568 r = c ? 0x190 : 0x170;
3569 if (b43_nphy_ipa(dev))
3570 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3571 }
3572 } else {
3573 if (b43_nphy_ipa(dev)) {
3574 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3575 b43_radio_write(dev,
3576 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3577 b43_radio_write(dev,
3578 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3579 } else {
3580 b43_radio_write(dev,
3581 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3582 b43_radio_write(dev,
3583 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3584 }
3585 }
3586 }
3587
3588 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3589 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3590 b43_read32(dev, B43_MMIO_MACCTL);
3591 udelay(1);
3592 }
3593
3594 if (dev->phy.rev >= 7) {
3595 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3596 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3597 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3598 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3599 } else {
3600 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3601 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3602 if (dev->phy.rev > 1)
3603 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3604 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3605 }
3606
3607 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3608 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3609
3610 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3611 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3612 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3613 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3614 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3615 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3616 B43_NPHY_TXPCTL_ITSSI_BINF);
3617 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3618 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3619 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3620
3621 for (c = 0; c < 2; c++) {
3622 for (i = 0; i < 64; i++) {
3623 num = 8 * (16 * b0[c] + b1[c] * i);
3624 den = 32768 + a1[c] * i;
3625 pwr = max((4 * num + den / 2) / den, -8);
3626 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3627 pwr = max(pwr, target[c] + 1);
3628 regval[i] = pwr;
3629 }
3630 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3631 }
3632
3633 b43_nphy_tx_prepare_adjusted_power_table(dev);
d3fd8bf7
RM		 3634 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3635 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
d3fd8bf7
RM		 3636
3637 if (nphy->hang_avoid)
3638 b43_nphy_stay_in_carrier_search(dev, false);
3639}
3640
0eff8fcd
RM		 3641static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3642{
3643 struct b43_phy *phy = &dev->phy;
67cbc3ed 3644
0eff8fcd 3645 const u32 *table = NULL;
0eff8fcd
RM		 3646 u32 rfpwr_offset;
3647 u8 pga_gain;
3648 int i;
0eff8fcd 3649
aeab5751 3650 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3651 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3652 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3653
3654 if (phy->rev >= 3) {
3655#if 0
3656 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3657#endif
0eff8fcd
RM		 3658
3659 for (i = 0; i < 128; i++) {
3660 pga_gain = (table[i] >> 24) & 0xF;
3661 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3662 rfpwr_offset =
3663 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3664 else
34c5cf20
RM		 3665 rfpwr_offset =
3666 0; /* FIXME */
0eff8fcd
RM		 3667 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3668 rfpwr_offset);
3669 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3670 rfpwr_offset);
3671 }
67cbc3ed
RM		 3672 }
3673}
3674
e50cbcf6
RM		 3675/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3676static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3677{
e50cbcf6
RM		 3678 struct b43_phy_n *nphy = dev->phy.n;
3679 enum ieee80211_band band;
3680 u16 tmp;
95b66bad 3681
e50cbcf6
RM		 3682 if (!enable) {
3683 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3684 B43_NPHY_RFCTL_INTC1);
3685 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3686 B43_NPHY_RFCTL_INTC2);
3687 band = b43_current_band(dev->wl);
3688 if (dev->phy.rev >= 3) {
3689 if (band == IEEE80211_BAND_5GHZ)
3690 tmp = 0x600;
3691 else
3692 tmp = 0x480;
3693 } else {
3694 if (band == IEEE80211_BAND_5GHZ)
3695 tmp = 0x180;
3696 else
3697 tmp = 0x120;
3698 }
3699 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3700 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3701 } else {
3702 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3703 nphy->rfctrl_intc1_save);
3704 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3705 nphy->rfctrl_intc2_save);
95b66bad 3706 }
95b66bad
MB		 3707}
3708
fe3e46e8
RM		 3709/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3710static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3711{
3712 u16 tmp;
3c95627d 3713
fe3e46e8 3714 if (dev->phy.rev >= 3) {
c002831a 3715 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3716 tmp = 4;
3717 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3718 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3719 }
76b002bd 3720
fe3e46e8
RM		 3721 tmp = 1;
3722 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3723 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3724 }
3725}
76b002bd 3726
2faa6b83
RM		 3727/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3728static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3729 u16 samps, u8 time, bool wait)
3c95627d 3730{
2faa6b83
RM		 3731 int i;
3732 u16 tmp;
3c95627d 3733
2faa6b83
RM		 3734 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3735 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3736 if (wait)
3737 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3738 else
2faa6b83 3739 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3740
2faa6b83 3741 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3742
2faa6b83
RM		 3743 for (i = 1000; i; i--) {
3744 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3745 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3746 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3747 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3748 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3749 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3750 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3751 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3752
2faa6b83
RM		 3753 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3754 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3755 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3756 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3757 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3758 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3759 return;
3c95627d 3760 }
2faa6b83 3761 udelay(10);
3c95627d 3762 }
2faa6b83 3763 memset(est, 0, sizeof(*est));
3c95627d
RM		 3764}
3765
a67162ab
RM		 3766/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3767static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3768 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3769{
a67162ab
RM		 3770 if (write) {
3771 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3772 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3773 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3774 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3775 } else {
a67162ab
RM		 3776 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3777 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3778 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3779 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3780 }
3781}
6e3b15a9 3782
c7455cf9
RM		 3783#if 0
3784/* Ready but not used anywhere */
026816fc
RM		 3785/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3786static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3787{
3788 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3789
026816fc
RM		 3790 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3791 if (core == 0) {
3792 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3793 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3794 } else {
3795 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3796 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3797 }
3798 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3799 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3800 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3801 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3802 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3803 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3804 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3805 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3806}
6e3b15a9 3807
026816fc
RM		 3808/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3809static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3810{
3811 u8 rxval, txval;
3812 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3813
026816fc
RM		 3814 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3815 if (core == 0) {
3816 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3817 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3818 } else {
3819 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3820 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3821 }
3822 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3823 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3824 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3825 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3826 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3827 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3828 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3829 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3830
026816fc
RM		 3831 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3832 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3833
acd82aa8
LF		 3834 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3835 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3836 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3837 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3838 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3839 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3840 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3841 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3842 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3843
026816fc
RM		 3844 if (core == 0) {
3845 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3846 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3847 } else {
3848 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3849 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3850 }
6e3b15a9 3851
89e43dad 3852 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 3853 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 3854 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3855
026816fc
RM		 3856 if (core == 0) {
3857 rxval = 1;
3858 txval = 8;
3859 } else {
3860 rxval = 4;
3861 txval = 2;
6e3b15a9 3862 }
89e43dad
RM		 3863 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3864 core + 1);
3865 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3866 2 - core);
99b82c41 3867}
c7455cf9 3868#endif
99b82c41 3869
34a56f2c
RM		 3870/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3871static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3872{
3873 int i;
34a56f2c
RM		 3874 s32 iq;
3875 u32 ii;
3876 u32 qq;
3877 int iq_nbits, qq_nbits;
3878 int arsh, brsh;
3879 u16 tmp, a, b;
3880
3881 struct nphy_iq_est est;
3882 struct b43_phy_n_iq_comp old;
3883 struct b43_phy_n_iq_comp new = { };
3884 bool error = false;
3885
3886 if (mask == 0)
3887 return;
3888
3889 b43_nphy_rx_iq_coeffs(dev, false, &old);
3890 b43_nphy_rx_iq_coeffs(dev, true, &new);
3891 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3892 new = old;
3893
dfb4aa5d 3894 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3895 if (i == 0 && (mask & 1)) {
3896 iq = est.iq0_prod;
3897 ii = est.i0_pwr;
3898 qq = est.q0_pwr;
3899 } else if (i == 1 && (mask & 2)) {
3900 iq = est.iq1_prod;
3901 ii = est.i1_pwr;
3902 qq = est.q1_pwr;
dfb4aa5d 3903 } else {
34a56f2c 3904 continue;
dfb4aa5d 3905 }
dfb4aa5d 3906
34a56f2c
RM		 3907 if (ii + qq < 2) {
3908 error = true;
3909 break;
3910 }
dfb4aa5d 3911
34a56f2c
RM		 3912 iq_nbits = fls(abs(iq));
3913 qq_nbits = fls(qq);
dfb4aa5d 3914
34a56f2c
RM		 3915 arsh = iq_nbits - 20;
3916 if (arsh >= 0) {
3917 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3918 tmp = ii >> arsh;
3919 } else {
3920 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3921 tmp = ii << -arsh;
3922 }
3923 if (tmp == 0) {
3924 error = true;
3925 break;
3926 }
3927 a /= tmp;
dfb4aa5d 3928
34a56f2c
RM		 3929 brsh = qq_nbits - 11;
3930 if (brsh >= 0) {
3931 b = (qq << (31 - qq_nbits));
3932 tmp = ii >> brsh;
dfb4aa5d 3933 } else {
34a56f2c
RM		 3934 b = (qq << (31 - qq_nbits));
3935 tmp = ii << -brsh;
3936 }
3937 if (tmp == 0) {
3938 error = true;
3939 break;
dfb4aa5d 3940 }
34a56f2c 3941 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3942
34a56f2c
RM		 3943 if (i == 0 && (mask & 0x1)) {
3944 if (dev->phy.rev >= 3) {
3945 new.a0 = a & 0x3FF;
3946 new.b0 = b & 0x3FF;
3947 } else {
3948 new.a0 = b & 0x3FF;
3949 new.b0 = a & 0x3FF;
3950 }
3951 } else if (i == 1 && (mask & 0x2)) {
3952 if (dev->phy.rev >= 3) {
3953 new.a1 = a & 0x3FF;
3954 new.b1 = b & 0x3FF;
3955 } else {
3956 new.a1 = b & 0x3FF;
3957 new.b1 = a & 0x3FF;
3958 }
3959 }
dfb4aa5d 3960 }
dfb4aa5d 3961
34a56f2c
RM		 3962 if (error)
3963 new = old;
dfb4aa5d 3964
34a56f2c
RM		 3965 b43_nphy_rx_iq_coeffs(dev, true, &new);
3966}
dfb4aa5d 3967
09146400
RM		 3968/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3969static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3970{
3971 u16 array[4];
44f4008b 3972 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3973
3974 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3975 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3976 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3977 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3978}
3979
9442e5b5
RM		 3980/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3981static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3982{
3983 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3984
204a665b 3985 u8 channel = dev->phy.channel;
9442e5b5
RM		 3986 int tone[2] = { 57, 58 };
3987 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3988
9442e5b5 3989 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3990
9442e5b5
RM		 3991 if (nphy->hang_avoid)
3992 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3993
9442e5b5
RM		 3994 if (nphy->gband_spurwar_en) {
3995 /* TODO: N PHY Adjust Analog Pfbw (7) */
bee6d4b2 3996 if (channel == 11 && b43_is_40mhz(dev))
9442e5b5
RM		 3997 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3998 else
3999 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4000 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 4001 }
4002
9442e5b5
RM		 4003 if (nphy->aband_spurwar_en) {
4004 if (channel == 54) {
4005 tone[0] = 0x20;
4006 noise[0] = 0x25F;
4007 } else if (channel == 38 || channel == 102 || channel == 118) {
4008 if (0 /* FIXME */) {
4009 tone[0] = 0x20;
4010 noise[0] = 0x21F;
4011 } else {
4012 tone[0] = 0;
4013 noise[0] = 0;
90b9738d 4014 }
9442e5b5
RM		 4015 } else if (channel == 134) {
4016 tone[0] = 0x20;
4017 noise[0] = 0x21F;
4018 } else if (channel == 151) {
4019 tone[0] = 0x10;
4020 noise[0] = 0x23F;
4021 } else if (channel == 153 || channel == 161) {
4022 tone[0] = 0x30;
4023 noise[0] = 0x23F;
4024 } else {
4025 tone[0] = 0;
4026 noise[0] = 0;
90b9738d 4027 }
90b9738d 4028
9442e5b5
RM		 4029 if (!tone[0] && !noise[0])
4030 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 4031 else
9442e5b5
RM		 4032 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4033 }
90b9738d 4034
9442e5b5
RM		 4035 if (nphy->hang_avoid)
4036 b43_nphy_stay_in_carrier_search(dev, 0);
4037}
90b9738d 4038
5ecab603
RM		 4039/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4040static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4041{
4042 struct b43_phy_n *nphy = dev->phy.n;
4043 int i, j;
4044 u32 tmp;
4045 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 4046
5ecab603 4047 u16 buffer[7];
90b9738d 4048
5ecab603
RM		 4049 if (nphy->hang_avoid)
4050 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 4051
5ecab603 4052 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 4053
5ecab603
RM		 4054 for (i = 0; i < 2; i++) {
4055 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4056 (buffer[i * 2 + 1] & 0x3FF);
4057 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4058 (((i + 26) << 10) | 320));
4059 for (j = 0; j < 128; j++) {
4060 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4061 ((tmp >> 16) & 0xFFFF));
4062 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4063 (tmp & 0xFFFF));
90b9738d 4064 }
90b9738d 4065 }
90b9738d 4066
5ecab603
RM		 4067 for (i = 0; i < 2; i++) {
4068 tmp = buffer[5 + i];
4069 real_part = (tmp >> 8) & 0xFF;
4070 imag_part = (tmp & 0xFF);
4071 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4072 (((i + 26) << 10) | 448));
90b9738d 4073
5ecab603
RM		 4074 if (dev->phy.rev >= 3) {
4075 cur_real = real_part;
4076 cur_imag = imag_part;
4077 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4078 }
4cb99775 4079
5ecab603
RM		 4080 for (j = 0; j < 128; j++) {
4081 if (dev->phy.rev < 3) {
4082 cur_real = (real_part * loscale[j] + 128) >> 8;
4083 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4084 tmp = ((cur_real & 0xFF) << 8) |
4085 (cur_imag & 0xFF);
4086 }
4087 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4088 ((tmp >> 16) & 0xFFFF));
4089 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4090 (tmp & 0xFFFF));
4091 }
90b9738d 4092 }
4cb99775 4093
4cb99775 4094 if (dev->phy.rev >= 3) {
5ecab603
RM		 4095 b43_shm_write16(dev, B43_SHM_SHARED,
4096 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4097 b43_shm_write16(dev, B43_SHM_SHARED,
4098 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 4099 }
90b9738d 4100
5ecab603
RM		 4101 if (nphy->hang_avoid)
4102 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 4103}
4104
42e1547e
RM		 4105/*
4106 * Restore RSSI Calibration
4107 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4108 */
4109static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4110{
4111 struct b43_phy_n *nphy = dev->phy.n;
4112
4113 u16 *rssical_radio_regs = NULL;
4114 u16 *rssical_phy_regs = NULL;
4115
4116 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4117 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 4118 return;
4119 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4120 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4121 } else {
204a665b 4122 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 4123 return;
4124 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4125 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4126 }
4127
9a98979e
RM		 4128 if (dev->phy.rev >= 7) {
4129 } else {
4130 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4131 rssical_radio_regs[0]);
4132 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4133 rssical_radio_regs[1]);
4134 }
42e1547e
RM		 4135
4136 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4137 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4138 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4139 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4140
4141 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4142 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4143 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4144 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4145
4146 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4147 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4148 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4149 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4150}
4151
c4a92003
RM		 4152/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4153static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4154{
4155 struct b43_phy_n *nphy = dev->phy.n;
4156 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4157 u16 tmp;
4158 u8 offset, i;
c4a92003
RM		 4159
4160 if (dev->phy.rev >= 3) {
52cb5e97
RM		 4161 for (i = 0; i < 2; i++) {
4162 tmp = (i == 0) ? 0x2000 : 0x3000;
4163 offset = i * 11;
4164
0c201cfb
RM		 4165 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4166 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4167 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4168 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4169 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4170 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4171 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4172 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4173 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4174 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4175 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4176
4177 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4178 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4179 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4180 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4181 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4182 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4183 if (nphy->ipa5g_on) {
0c201cfb
RM		 4184 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4185 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4186 } else {
0c201cfb
RM		 4187 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4188 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4189 }
0c201cfb 4190 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4191 } else {
0c201cfb
RM		 4192 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4193 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4194 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4195 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4196 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4197 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4198 if (nphy->ipa2g_on) {
0c201cfb
RM		 4199 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4200 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4201 (dev->phy.rev < 5) ? 0x11 : 0x01);
4202 } else {
0c201cfb
RM		 4203 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4204 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4205 }
4206 }
0c201cfb
RM		 4207 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4208 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4209 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4210 }
c4a92003 4211 } else {
0c201cfb
RM		 4212 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4213 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4214
0c201cfb
RM		 4215 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4216 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4217
0c201cfb
RM		 4218 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4219 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4220
0c201cfb
RM		 4221 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4222 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4223
0c201cfb
RM		 4224 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4225 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4226
4227 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4228 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4229 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4230 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4231 } else {
0c201cfb
RM		 4232 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4233 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4234 }
4235
4236 if (dev->phy.rev < 2) {
4237 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4238 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4239 } else {
4240 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4241 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4242 }
4243 }
4244}
4245
de7ed0c6
RM		 4246/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4247static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4248{
4249 struct b43_phy_n *nphy = dev->phy.n;
4250 int i;
4251 u16 scale, entry;
4252
4253 u16 tmp = nphy->txcal_bbmult;
4254 if (core == 0)
4255 tmp >>= 8;
4256 tmp &= 0xff;
4257
4258 for (i = 0; i < 18; i++) {
4259 scale = (ladder_lo[i].percent * tmp) / 100;
4260 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4261 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4262
4263 scale = (ladder_iq[i].percent * tmp) / 100;
4264 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4265 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4266 }
4267}
4268
45ca697e
RM		 4269/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4270static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4271{
4272 int i;
4273 for (i = 0; i < 15; i++)
4274 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4275 tbl_tx_filter_coef_rev4[2][i]);
4276}
4277
4278/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4279static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4280{
4281 int i, j;
4282 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4283 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4284
4285 for (i = 0; i < 3; i++)
4286 for (j = 0; j < 15; j++)
4287 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4288 tbl_tx_filter_coef_rev4[i][j]);
4289
bee6d4b2 4290 if (b43_is_40mhz(dev)) {
45ca697e
RM		 4291 for (j = 0; j < 15; j++)
4292 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4293 tbl_tx_filter_coef_rev4[3][j]);
4294 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4295 for (j = 0; j < 15; j++)
4296 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4297 tbl_tx_filter_coef_rev4[5][j]);
4298 }
4299
4300 if (dev->phy.channel == 14)
4301 for (j = 0; j < 15; j++)
4302 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4303 tbl_tx_filter_coef_rev4[6][j]);
4304}
4305
b0022e15
RM		 4306/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4307static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4308{
4309 struct b43_phy_n *nphy = dev->phy.n;
4310
4311 u16 curr_gain[2];
4312 struct nphy_txgains target;
4313 const u32 *table = NULL;
4314
161d540c 4315 if (!nphy->txpwrctrl) {
b0022e15
RM		 4316 int i;
4317
4318 if (nphy->hang_avoid)
4319 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4320 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4321 if (nphy->hang_avoid)
4322 b43_nphy_stay_in_carrier_search(dev, false);
4323
4324 for (i = 0; i < 2; ++i) {
4325 if (dev->phy.rev >= 3) {
4326 target.ipa[i] = curr_gain[i] & 0x000F;
4327 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4328 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4329 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4330 } else {
4331 target.ipa[i] = curr_gain[i] & 0x0003;
4332 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4333 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4334 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4335 }
4336 }
4337 } else {
4338 int i;
4339 u16 index[2];
4340 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4341 B43_NPHY_TXPCTL_STAT_BIDX) >>
4342 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4343 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4344 B43_NPHY_TXPCTL_STAT_BIDX) >>
4345 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4346
4347 for (i = 0; i < 2; ++i) {
aeab5751 4348 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4349 if (dev->phy.rev >= 3) {
b0022e15
RM		 4350 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4351 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4352 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4353 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4354 } else {
b0022e15
RM		 4355 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4356 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4357 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4358 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4359 }
4360 }
4361 }
4362
4363 return target;
4364}
4365
e53de674
RM		 4366/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4367static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4368{
4369 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4370
4371 if (dev->phy.rev >= 3) {
4372 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4373 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4374 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4375 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4376 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4377 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4378 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4379 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4380 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4381 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4382 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4383 b43_nphy_reset_cca(dev);
4384 } else {
4385 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4386 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4387 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4388 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4389 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4390 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4391 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4392 }
4393}
4394
4395/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4396static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4397{
4398 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4399 u16 tmp;
4400
4401 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4402 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4403 if (dev->phy.rev >= 3) {
4404 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4405 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4406
4407 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4408 regs[2] = tmp;
4409 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4410
4411 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4412 regs[3] = tmp;
4413 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4414
4415 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4416 b43_phy_mask(dev, B43_NPHY_BBCFG,
4417 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4418
c643a66e 4419 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4420 regs[5] = tmp;
d41a3552 4421 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4422
4423 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4424 regs[6] = tmp;
d41a3552 4425 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4426 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4427 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4428
89e43dad
RM		 4429 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4430 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4431 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4432
4433 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4434 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4435 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4436 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4437 } else {
4438 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4439 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4440 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4441 regs[2] = tmp;
4442 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4443 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4444 regs[3] = tmp;
4445 tmp |= 0x2000;
d41a3552 4446 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4447 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4448 regs[4] = tmp;
4449 tmp |= 0x2000;
d41a3552 4450 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4451 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4452 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4453 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4454 tmp = 0x0180;
4455 else
4456 tmp = 0x0120;
4457 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4458 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4459 }
4460}
4461
bbc6dc12
RM		 4462/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4463static void b43_nphy_save_cal(struct b43_wldev *dev)
4464{
4465 struct b43_phy_n *nphy = dev->phy.n;
4466
4467 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4468 u16 *txcal_radio_regs = NULL;
902db91d 4469 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4470 u16 *table = NULL;
4471
4472 if (nphy->hang_avoid)
4473 b43_nphy_stay_in_carrier_search(dev, 1);
4474
4475 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4476 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4477 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4478 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4479 table = nphy->cal_cache.txcal_coeffs_2G;
4480 } else {
4481 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4482 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4483 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4484 table = nphy->cal_cache.txcal_coeffs_5G;
4485 }
4486
4487 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4488 /* TODO use some definitions */
4489 if (dev->phy.rev >= 3) {
4490 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4491 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4492 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4493 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4494 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4495 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4496 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4497 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4498 } else {
4499 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4500 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4501 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4502 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4503 }
39e971ef 4504 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
427fa00b
RM		 4505 iqcal_chanspec->channel_type =
4506 cfg80211_get_chandef_type(dev->phy.chandef);
5818e989 4507 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4508
4509 if (nphy->hang_avoid)
4510 b43_nphy_stay_in_carrier_search(dev, 0);
4511}
4512
2f258b74
RM		 4513/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4514static void b43_nphy_restore_cal(struct b43_wldev *dev)
4515{
4516 struct b43_phy_n *nphy = dev->phy.n;
4517
4518 u16 coef[4];
4519 u16 *loft = NULL;
4520 u16 *table = NULL;
4521
4522 int i;
4523 u16 *txcal_radio_regs = NULL;
4524 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4525
4526 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4527 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4528 return;
4529 table = nphy->cal_cache.txcal_coeffs_2G;
4530 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4531 } else {
204a665b 4532 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4533 return;
4534 table = nphy->cal_cache.txcal_coeffs_5G;
4535 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4536 }
4537
2581b143 4538 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4539
4540 for (i = 0; i < 4; i++) {
4541 if (dev->phy.rev >= 3)
4542 table[i] = coef[i];
4543 else
4544 coef[i] = 0;
4545 }
4546
2581b143
RM		 4547 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4548 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4549 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4550
4551 if (dev->phy.rev < 2)
4552 b43_nphy_tx_iq_workaround(dev);
4553
4554 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4555 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4556 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4557 } else {
4558 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4559 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4560 }
4561
4562 /* TODO use some definitions */
4563 if (dev->phy.rev >= 3) {
4564 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4565 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4566 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4567 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4568 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4569 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4570 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4571 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4572 } else {
4573 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4574 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4575 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4576 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4577 }
4578 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4579}
4580
fb43b8e2
RM		 4581/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4582static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4583 struct nphy_txgains target,
4584 bool full, bool mphase)
4585{
39e971ef 4586 struct b43_phy *phy = &dev->phy;
fb43b8e2
RM		 4587 struct b43_phy_n *nphy = dev->phy.n;
4588 int i;
4589 int error = 0;
4590 int freq;
4591 bool avoid = false;
4592 u8 length;
fb23d863 4593 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4594 const u16 *table;
4595 bool phy6or5x;
4596
4597 u16 buffer[11];
4598 u16 diq_start = 0;
4599 u16 save[2];
4600 u16 gain[2];
4601 struct nphy_iqcal_params params[2];
4602 bool updated[2] = { };
4603
4604 b43_nphy_stay_in_carrier_search(dev, true);
4605
4606 if (dev->phy.rev >= 4) {
4607 avoid = nphy->hang_avoid;
3db1cd5c 4608 nphy->hang_avoid = false;
fb43b8e2
RM		 4609 }
4610
9145834e 4611 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4612
4613 for (i = 0; i < 2; i++) {
4614 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4615 gain[i] = params[i].cal_gain;
4616 }
2581b143
RM		 4617
4618 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4619
4620 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4621 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4622
4623 phy6or5x = dev->phy.rev >= 6 ||
4624 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4625 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4626 if (phy6or5x) {
bee6d4b2 4627 if (b43_is_40mhz(dev)) {
38bb9029
RM		 4628 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4629 tbl_tx_iqlo_cal_loft_ladder_40);
4630 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4631 tbl_tx_iqlo_cal_iqimb_ladder_40);
4632 } else {
4633 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4634 tbl_tx_iqlo_cal_loft_ladder_20);
4635 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4636 tbl_tx_iqlo_cal_iqimb_ladder_20);
4637 }
fb43b8e2
RM		 4638 }
4639
4640 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4641
bee6d4b2 4642 if (!b43_is_40mhz(dev))
fb43b8e2
RM		 4643 freq = 2500;
4644 else
4645 freq = 5000;
4646
4647 if (nphy->mphase_cal_phase_id > 2)
bee6d4b2 4648 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
ed03033e 4649 0xFFFF, 0, true, false, false);
fb43b8e2 4650 else
ed03033e 4651 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false);
fb43b8e2
RM		 4652
4653 if (error == 0) {
4654 if (nphy->mphase_cal_phase_id > 2) {
4655 table = nphy->mphase_txcal_bestcoeffs;
4656 length = 11;
4657 if (dev->phy.rev < 3)
4658 length -= 2;
4659 } else {
4660 if (!full && nphy->txiqlocal_coeffsvalid) {
4661 table = nphy->txiqlocal_bestc;
4662 length = 11;
4663 if (dev->phy.rev < 3)
4664 length -= 2;
4665 } else {
4666 full = true;
4667 if (dev->phy.rev >= 3) {
4668 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4669 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4670 } else {
4671 table = tbl_tx_iqlo_cal_startcoefs;
4672 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4673 }
4674 }
4675 }
4676
2581b143 4677 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4678
4679 if (full) {
4680 if (dev->phy.rev >= 3)
4681 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4682 else
4683 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4684 } else {
4685 if (dev->phy.rev >= 3)
4686 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4687 else
4688 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4689 }
4690
4691 if (mphase) {
4692 count = nphy->mphase_txcal_cmdidx;
4693 numb = min(max,
4694 (u16)(count + nphy->mphase_txcal_numcmds));
4695 } else {
4696 count = 0;
4697 numb = max;
4698 }
4699
4700 for (; count < numb; count++) {
4701 if (full) {
4702 if (dev->phy.rev >= 3)
4703 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4704 else
4705 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4706 } else {
4707 if (dev->phy.rev >= 3)
4708 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4709 else
4710 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4711 }
4712
4713 core = (cmd & 0x3000) >> 12;
4714 type = (cmd & 0x0F00) >> 8;
4715
4716 if (phy6or5x && updated[core] == 0) {
4717 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4718 updated[core] = true;
fb43b8e2
RM		 4719 }
4720
4721 tmp = (params[core].ncorr[type] << 8) | 0x66;
4722 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4723
4724 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4725 buffer[0] = b43_ntab_read(dev,
4726 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4727 diq_start = buffer[0];
4728 buffer[0] = 0;
d41a3552
RM		 4729 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4730 0);
fb43b8e2
RM		 4731 }
4732
4733 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4734 for (i = 0; i < 2000; i++) {
4735 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4736 if (tmp & 0xC000)
4737 break;
4738 udelay(10);
4739 }
4740
9145834e
RM		 4741 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4742 buffer);
2581b143
RM		 4743 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4744 buffer);
fb43b8e2
RM		 4745
4746 if (type == 1 || type == 3 || type == 4)
4747 buffer[0] = diq_start;
4748 }
4749
4750 if (mphase)
4751 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4752
4753 last = (dev->phy.rev < 3) ? 6 : 7;
4754
4755 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4756 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4757 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4758 if (dev->phy.rev < 3) {
4759 buffer[0] = 0;
4760 buffer[1] = 0;
4761 buffer[2] = 0;
4762 buffer[3] = 0;
4763 }
2581b143
RM		 4764 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4765 buffer);
bc53e512 4766 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4767 buffer);
4768 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4769 buffer);
4770 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4771 buffer);
fb43b8e2
RM		 4772 length = 11;
4773 if (dev->phy.rev < 3)
4774 length -= 2;
9145834e
RM		 4775 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4776 nphy->txiqlocal_bestc);
fb43b8e2 4777 nphy->txiqlocal_coeffsvalid = true;
204a665b 4778 nphy->txiqlocal_chanspec.center_freq =
39e971ef 4779 phy->chandef->chan->center_freq;
204a665b 4780 nphy->txiqlocal_chanspec.channel_type =
427fa00b 4781 cfg80211_get_chandef_type(phy->chandef);
fb43b8e2
RM		 4782 } else {
4783 length = 11;
4784 if (dev->phy.rev < 3)
4785 length -= 2;
9145834e
RM		 4786 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4787 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4788 }
4789
53ae8e8c 4790 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4791 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4792 }
4793
e53de674 4794 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4795 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4796
4797 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4798 b43_nphy_tx_iq_workaround(dev);
4799
4800 if (dev->phy.rev >= 4)
4801 nphy->hang_avoid = avoid;
4802
4803 b43_nphy_stay_in_carrier_search(dev, false);
4804
4805 return error;
4806}
4807
984ff4ff
RM		 4808/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4809static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4810{
4811 struct b43_phy_n *nphy = dev->phy.n;
4812 u8 i;
4813 u16 buffer[7];
4814 bool equal = true;
4815
902db91d 4816 if (!nphy->txiqlocal_coeffsvalid ||
39e971ef 4817 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
427fa00b 4818 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef))
984ff4ff
RM		 4819 return;
4820
4821 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4822 for (i = 0; i < 4; i++) {
4823 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4824 equal = false;
4825 break;
4826 }
4827 }
4828
4829 if (!equal) {
4830 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4831 nphy->txiqlocal_bestc);
4832 for (i = 0; i < 4; i++)
4833 buffer[i] = 0;
4834 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4835 buffer);
4836 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4837 &nphy->txiqlocal_bestc[5]);
4838 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4839 &nphy->txiqlocal_bestc[5]);
4840 }
4841}
4842
15931e31
RM		 4843/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4844static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4845 struct nphy_txgains target, u8 type, bool debug)
4846{
4847 struct b43_phy_n *nphy = dev->phy.n;
4848 int i, j, index;
4849 u8 rfctl[2];
4850 u8 afectl_core;
4851 u16 tmp[6];
c7455cf9 4852 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4853 u32 real, imag;
4854 enum ieee80211_band band;
4855
4856 u8 use;
4857 u16 cur_hpf;
4858 u16 lna[3] = { 3, 3, 1 };
4859 u16 hpf1[3] = { 7, 2, 0 };
4860 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4861 u32 power[3] = { };
15931e31
RM		 4862 u16 gain_save[2];
4863 u16 cal_gain[2];
4864 struct nphy_iqcal_params cal_params[2];
4865 struct nphy_iq_est est;
4866 int ret = 0;
4867 bool playtone = true;
4868 int desired = 13;
4869
4870 b43_nphy_stay_in_carrier_search(dev, 1);
4871
4872 if (dev->phy.rev < 2)
984ff4ff 4873 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4874 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4875 for (i = 0; i < 2; i++) {
4876 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4877 cal_gain[i] = cal_params[i].cal_gain;
4878 }
2581b143 4879 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4880
4881 for (i = 0; i < 2; i++) {
4882 if (i == 0) {
4883 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4884 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4885 afectl_core = B43_NPHY_AFECTL_C1;
4886 } else {
4887 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4888 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4889 afectl_core = B43_NPHY_AFECTL_C2;
4890 }
4891
4892 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4893 tmp[2] = b43_phy_read(dev, afectl_core);
4894 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4895 tmp[4] = b43_phy_read(dev, rfctl[0]);
4896 tmp[5] = b43_phy_read(dev, rfctl[1]);
4897
4898 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4899 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4900 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4901 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4902 (1 - i));
4903 b43_phy_set(dev, afectl_core, 0x0006);
4904 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4905
4906 band = b43_current_band(dev->wl);
4907
4908 if (nphy->rxcalparams & 0xFF000000) {
4909 if (band == IEEE80211_BAND_5GHZ)
4910 b43_phy_write(dev, rfctl[0], 0x140);
4911 else
4912 b43_phy_write(dev, rfctl[0], 0x110);
4913 } else {
4914 if (band == IEEE80211_BAND_5GHZ)
4915 b43_phy_write(dev, rfctl[0], 0x180);
4916 else
4917 b43_phy_write(dev, rfctl[0], 0x120);
4918 }
4919
4920 if (band == IEEE80211_BAND_5GHZ)
4921 b43_phy_write(dev, rfctl[1], 0x148);
4922 else
4923 b43_phy_write(dev, rfctl[1], 0x114);
4924
4925 if (nphy->rxcalparams & 0x10000) {
4926 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4927 (i + 1));
4928 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4929 (2 - i));
4930 }
4931
30115c22 4932 for (j = 0; j < 4; j++) {
15931e31
RM		 4933 if (j < 3) {
4934 cur_lna = lna[j];
4935 cur_hpf1 = hpf1[j];
4936 cur_hpf2 = hpf2[j];
4937 } else {
4938 if (power[1] > 10000) {
4939 use = 1;
4940 cur_hpf = cur_hpf1;
4941 index = 2;
4942 } else {
4943 if (power[0] > 10000) {
4944 use = 1;
4945 cur_hpf = cur_hpf1;
4946 index = 1;
4947 } else {
4948 index = 0;
4949 use = 2;
4950 cur_hpf = cur_hpf2;
4951 }
4952 }
4953 cur_lna = lna[index];
4954 cur_hpf1 = hpf1[index];
4955 cur_hpf2 = hpf2[index];
4956 cur_hpf += desired - hweight32(power[index]);
4957 cur_hpf = clamp_val(cur_hpf, 0, 10);
4958 if (use == 1)
4959 cur_hpf1 = cur_hpf;
4960 else
4961 cur_hpf2 = cur_hpf;
4962 }
4963
4964 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4965 (cur_lna << 2));
78ae7532 4966 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 4967 false);
de9a47f9 4968 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4969 b43_nphy_stop_playback(dev);
15931e31
RM		 4970
4971 if (playtone) {
59af099b
RM		 4972 ret = b43_nphy_tx_tone(dev, 4000,
4973 (nphy->rxcalparams & 0xFFFF),
ed03033e 4974 false, false, true);
15931e31
RM		 4975 playtone = false;
4976 } else {
ed03033e
RM		 4977 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false,
4978 false, true);
15931e31
RM		 4979 }
4980
4981 if (ret == 0) {
4982 if (j < 3) {
4983 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4984 false);
4985 if (i == 0) {
4986 real = est.i0_pwr;
4987 imag = est.q0_pwr;
4988 } else {
4989 real = est.i1_pwr;
4990 imag = est.q1_pwr;
4991 }
4992 power[i] = ((real + imag) / 1024) + 1;
4993 } else {
4994 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4995 }
53ae8e8c 4996 b43_nphy_stop_playback(dev);
15931e31
RM		 4997 }
4998
4999 if (ret != 0)
5000 break;
5001 }
5002
5003 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5004 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5005 b43_phy_write(dev, rfctl[1], tmp[5]);
5006 b43_phy_write(dev, rfctl[0], tmp[4]);
5007 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5008 b43_phy_write(dev, afectl_core, tmp[2]);
5009 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5010
5011 if (ret != 0)
5012 break;
5013 }
5014
78ae7532 5015 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 5016 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 5017 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5018
5019 b43_nphy_stay_in_carrier_search(dev, 0);
5020
5021 return ret;
5022}
5023
5024static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5025 struct nphy_txgains target, u8 type, bool debug)
5026{
5027 return -1;
5028}
5029
5030/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5031static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5032 struct nphy_txgains target, u8 type, bool debug)
5033{
5034 if (dev->phy.rev >= 3)
5035 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5036 else
5037 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5038}
5039
4e687b22
GS		 5040/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5041static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5042{
5043 struct b43_phy *phy = &dev->phy;
5044 struct b43_phy_n *nphy = phy->n;
0b81c23d 5045 /* u16 buf[16]; it's rev3+ */
4e687b22 5046
049fbfee
RM		 5047 nphy->phyrxchain = mask;
5048
4e687b22
GS		 5049 if (0 /* FIXME clk */)
5050 return;
5051
5052 b43_mac_suspend(dev);
5053
5054 if (nphy->hang_avoid)
5055 b43_nphy_stay_in_carrier_search(dev, true);
5056
5057 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5058 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5059
049fbfee 5060 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 5061 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5062 if (dev->phy.rev >= 3) {
5063 /* TODO */
5064 }
5065 } else {
5066 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5067 if (dev->phy.rev >= 3) {
5068 /* TODO */
5069 }
5070 }
5071
5072 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5073
5074 if (nphy->hang_avoid)
5075 b43_nphy_stay_in_carrier_search(dev, false);
5076
5077 b43_mac_enable(dev);
5078}
5079
104cfa88
RM		 5080/**************************************************
5081 * N-PHY init
5082 **************************************************/
5083
104cfa88
RM		 5084/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5085static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5086{
5087 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5088
5089 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5090 if (preamble == 1)
5091 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5092 else
5093 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5094
5095 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5096}
5097
5098/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5099static void b43_nphy_bphy_init(struct b43_wldev *dev)
5100{
5101 unsigned int i;
5102 u16 val;
5103
5104 val = 0x1E1F;
5105 for (i = 0; i < 16; i++) {
5106 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5107 val -= 0x202;
5108 }
5109 val = 0x3E3F;
5110 for (i = 0; i < 16; i++) {
5111 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5112 val -= 0x202;
5113 }
5114 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5115}
5116
5117/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5118static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5119{
5120 if (dev->phy.rev >= 3) {
5121 if (!init)
5122 return;
5123 if (0 /* FIXME */) {
5124 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5125 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5126 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5127 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5128 }
5129 } else {
5130 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5131 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5132
5133 switch (dev->dev->bus_type) {
5134#ifdef CONFIG_B43_BCMA
5135 case B43_BUS_BCMA:
5136 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5137 0xFC00, 0xFC00);
5138 break;
5139#endif
5140#ifdef CONFIG_B43_SSB
5141 case B43_BUS_SSB:
5142 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5143 0xFC00, 0xFC00);
5144 break;
5145#endif
5146 }
5147
5056635c
RM		 5148 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5149 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5150 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5151 0);
104cfa88
RM		 5152
5153 if (init) {
5154 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5155 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5156 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5157 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5158 }
5159 }
5160}
5161
5162/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5163static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5164{
0581483a 5165 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5166 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5167 struct b43_phy_n *nphy = phy->n;
5168 u8 tx_pwr_state;
5169 struct nphy_txgains target;
95b66bad 5170 u16 tmp;
0988a7a1
RM		 5171 enum ieee80211_band tmp2;
5172 bool do_rssi_cal;
5173
5174 u16 clip[2];
5175 bool do_cal = false;
95b66bad 5176
0988a7a1 5177 if ((dev->phy.rev >= 3) &&
0581483a 5178 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5179 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5180 switch (dev->dev->bus_type) {
42c9a458
RM		 5181#ifdef CONFIG_B43_BCMA
5182 case B43_BUS_BCMA:
5183 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5184 BCMA_CC_CHIPCTL, 0x40);
5185 break;
5186#endif
6cbab0d9
RM		 5187#ifdef CONFIG_B43_SSB
5188 case B43_BUS_SSB:
5189 chipco_set32(&dev->dev->sdev->bus->chipco,
5190 SSB_CHIPCO_CHIPCTL, 0x40);
5191 break;
5192#endif
5193 }
0988a7a1
RM		 5194 }
5195 nphy->deaf_count = 0;
95b66bad 5196 b43_nphy_tables_init(dev);
0988a7a1
RM		 5197 nphy->crsminpwr_adjusted = false;
5198 nphy->noisevars_adjusted = false;
95b66bad
MB		 5199
5200 /* Clear all overrides */
0988a7a1
RM		 5201 if (dev->phy.rev >= 3) {
5202 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5203 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5204 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5205 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5206 } else {
5207 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5208 }
95b66bad
MB		 5209 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5210 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5211 if (dev->phy.rev < 6) {
5212 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5213 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5214 }
95b66bad
MB		 5215 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5216 ~(B43_NPHY_RFSEQMODE_CAOVER |
5217 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5218 if (dev->phy.rev >= 3)
5219 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5220 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5221
0988a7a1
RM		 5222 if (dev->phy.rev <= 2) {
5223 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5224 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5225 ~B43_NPHY_BPHY_CTL3_SCALE,
5226 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5227 }
95b66bad
MB		 5228 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5229 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5230
0eff8fcd 5231 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5232 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5233 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5234 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5235 else
5236 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5237 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5238 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5239 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5240
ad9716e8 5241 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 5242 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5243
5244 if (phy->rev < 2) {
5245 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5246 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5247 }
0988a7a1
RM		 5248
5249 tmp2 = b43_current_band(dev->wl);
c002831a 5250 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5251 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5252 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5253 nphy->papd_epsilon_offset[0] << 7);
5254 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5255 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5256 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5257 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5258 } else if (phy->rev >= 5) {
45ca697e 5259 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5260 }
5261
95b66bad 5262 b43_nphy_workarounds(dev);
95b66bad 5263
0988a7a1 5264 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5265 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5266 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5267 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5268 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5269 b43_phy_force_clock(dev, 0);
0988a7a1 5270
858a1652 5271 b43_mac_phy_clock_set(dev, true);
0988a7a1 5272
e50cbcf6 5273 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5274 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5275 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5276 b43_nphy_pa_override(dev, true);
0988a7a1 5277
bbec398c
RM		 5278 b43_nphy_classifier(dev, 0, 0);
5279 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5280 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5281 b43_nphy_bphy_init(dev);
5282
0988a7a1 5283 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5284 b43_nphy_tx_power_ctrl(dev, false);
5285 b43_nphy_tx_power_fix(dev);
3dda07b6 5286 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5287 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5288 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5289
0988a7a1 5290 if (nphy->phyrxchain != 3)
4e687b22 5291 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5292 if (nphy->mphase_cal_phase_id > 0)
5293 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5294
5295 do_rssi_cal = false;
5296 if (phy->rev >= 3) {
5297 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5298 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5299 else
204a665b 5300 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5301
5302 if (do_rssi_cal)
4cb99775 5303 b43_nphy_rssi_cal(dev);
0988a7a1 5304 else
42e1547e 5305 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5306 } else {
4cb99775 5307 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5308 }
5309
5310 if (!((nphy->measure_hold & 0x6) != 0)) {
5311 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5312 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5313 else
204a665b 5314 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5315
5316 if (nphy->mute)
5317 do_cal = false;
5318
5319 if (do_cal) {
b0022e15 5320 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5321
5322 if (nphy->antsel_type == 2)
8987a9e9 5323 b43_nphy_superswitch_init(dev, true);
0988a7a1 5324 if (nphy->perical != 2) {
90b9738d 5325 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5326 if (phy->rev >= 3) {
5327 nphy->cal_orig_pwr_idx[0] =
5328 nphy->txpwrindex[0].index_internal;
5329 nphy->cal_orig_pwr_idx[1] =
5330 nphy->txpwrindex[1].index_internal;
5331 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5332 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5333 }
e7797bf2
RM		 5334 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5335 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5336 b43_nphy_save_cal(dev);
5337 } else if (nphy->mphase_cal_phase_id == 0)
5338 ;/* N PHY Periodic Calibration with arg 3 */
5339 } else {
5340 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5341 }
5342 }
5343
6dcd9d91 5344 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5345 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5346 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5347 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5348 if (phy->rev >= 3 && phy->rev <= 6)
bc36e994 5349 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
fe3e46e8 5350 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5351 if (phy->rev >= 3)
5352 b43_nphy_spur_workaround(dev);
95b66bad 5353
53a6e234 5354 return 0;
424047e6 5355}
ef1a628d 5356
104cfa88
RM		 5357/**************************************************
5358 * Channel switching ops.
5359 **************************************************/
5360
5361static void b43_chantab_phy_upload(struct b43_wldev *dev,
5362 const struct b43_phy_n_sfo_cfg *e)
5363{
5364 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5365 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5366 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5367 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5368 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5369 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5370}
5371
49d55cef
RM		 5372/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5373static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5374{
d66be829
RM		 5375 switch (dev->dev->bus_type) {
5376#ifdef CONFIG_B43_BCMA
5377 case B43_BUS_BCMA:
9b383672
HM		 5378 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5379 avoid);
d66be829 5380 break;
8b1fdb53 5381#endif
d66be829
RM		 5382#ifdef CONFIG_B43_SSB
5383 case B43_BUS_SSB:
46fc4c90
RM		 5384 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5385 avoid);
d66be829
RM		 5386 break;
5387#endif
5388 }
49d55cef
RM		 5389}
5390
1b69ec7b 5391/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5392static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5393 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5394 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5395{
5396 struct b43_phy *phy = &dev->phy;
5397 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5398 int ch = new_channel->hw_value;
1b69ec7b 5399
087de74a 5400 u16 old_band_5ghz;
12cd43c6 5401 u16 tmp16;
1b69ec7b 5402
087de74a
RM		 5403 old_band_5ghz =
5404 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5405 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 5406 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5407 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 5408 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 5409 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 5410 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5411 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 5412 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 5413 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5414 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 5415 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 5416 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 5417 }
5418
5419 b43_chantab_phy_upload(dev, e);
5420
a656b6a9 5421 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5422 b43_nphy_classifier(dev, 2, 0);
5423 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5424 } else {
5425 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5426 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5427 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5428 }
5429
161d540c 5430 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5431 b43_nphy_tx_power_fix(dev);
5432
5433 if (dev->phy.rev < 3)
5434 b43_nphy_adjust_lna_gain_table(dev);
5435
5436 b43_nphy_tx_lp_fbw(dev);
5437
49d55cef
RM		 5438 if (dev->phy.rev >= 3 &&
5439 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5440 bool avoid = false;
5441 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5442 avoid = true;
427fa00b 5443 } else if (!b43_is_40mhz(dev)) {
49d55cef
RM		 5444 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5445 avoid = true;
5446 } else { /* 40MHz */
5447 if (nphy->aband_spurwar_en &&
5448 (ch == 38 || ch == 102 || ch == 118))
5449 avoid = dev->dev->chip_id == 0x4716;
5450 }
5451
5452 b43_nphy_pmu_spur_avoid(dev, avoid);
5453
5454 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5455 dev->dev->chip_id == 43225) {
5456 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5457 avoid ? 0x5341 : 0x8889);
5458 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5459 }
5460
5461 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5462 ; /* TODO: reset PLL */
5463
5464 if (avoid)
5465 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5466 else
5467 b43_phy_mask(dev, B43_NPHY_BBCFG,
5468 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5469
5470 b43_nphy_reset_cca(dev);
5471
5472 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5473 }
5474
5475 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5476
5477 if (phy->rev >= 3)
5478 b43_nphy_spur_workaround(dev);
5479}
5480
eff66c51 5481/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5482static int b43_nphy_set_channel(struct b43_wldev *dev,
5483 struct ieee80211_channel *channel,
5484 enum nl80211_channel_type channel_type)
eff66c51 5485{
a656b6a9 5486 struct b43_phy *phy = &dev->phy;
eff66c51 5487
2eeb6fd0
JL		 5488 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5489 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5490
5491 u8 tmp;
eff66c51
RM		 5492
5493 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5494 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5495 channel->center_freq);
f19ebe7d
RM		 5496 if (!tabent_r3)
5497 return -ESRCH;
ffd2d9bd 5498 } else {
a656b6a9
RM		 5499 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5500 channel->hw_value);
f19ebe7d 5501 if (!tabent_r2)
ffd2d9bd 5502 return -ESRCH;
eff66c51
RM		 5503 }
5504
204a665b
RM		 5505 /* Channel is set later in common code, but we need to set it on our
5506 own to let this function's subcalls work properly. */
5507 phy->channel = channel->hw_value;
eff66c51 5508
427fa00b 5509#if 0
e5c407f9
RM		 5510 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5511 b43_channel_type_is_40mhz(channel_type))
5512 ; /* TODO: BMAC BW Set (channel_type) */
427fa00b 5513#endif
eff66c51 5514
a656b6a9
RM		 5515 if (channel_type == NL80211_CHAN_HT40PLUS)
5516 b43_phy_set(dev, B43_NPHY_RXCTL,
5517 B43_NPHY_RXCTL_BSELU20);
5518 else if (channel_type == NL80211_CHAN_HT40MINUS)
5519 b43_phy_mask(dev, B43_NPHY_RXCTL,
5520 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5521
5522 if (dev->phy.rev >= 3) {
a656b6a9 5523 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5524 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5525 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5526 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5527 } else {
a656b6a9 5528 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5529 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5530 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5531 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5532 }
5533
5534 return 0;
5535}
5536
104cfa88
RM		 5537/**************************************************
5538 * Basic PHY ops.
5539 **************************************************/
5540
ef1a628d
MB		 5541static int b43_nphy_op_allocate(struct b43_wldev *dev)
5542{
5543 struct b43_phy_n *nphy;
5544
5545 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5546 if (!nphy)
5547 return -ENOMEM;
5548 dev->phy.n = nphy;
5549
ef1a628d
MB		 5550 return 0;
5551}
5552
fb11137a 5553static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5554{
fb11137a
MB		 5555 struct b43_phy *phy = &dev->phy;
5556 struct b43_phy_n *nphy = phy->n;
c7d64310 5557 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5558
fb11137a 5559 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5560
aca434d3 5561 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5562 nphy->spur_avoid = (phy->rev >= 3) ?
5563 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
0b81c23d
RM		 5564 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5565 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5566 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5567 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5568 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5569 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5570 nphy->tx_pwr_idx[0] = 128;
5571 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5572
5573 /* Hardware TX power control and 5GHz power gain */
5574 nphy->txpwrctrl = false;
5575 nphy->pwg_gain_5ghz = false;
5576 if (dev->phy.rev >= 3 ||
5577 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5578 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5579 nphy->txpwrctrl = true;
5580 nphy->pwg_gain_5ghz = true;
5581 } else if (sprom->revision >= 4) {
5582 if (dev->phy.rev >= 2 &&
5583 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5584 nphy->txpwrctrl = true;
5585#ifdef CONFIG_B43_SSB
5586 if (dev->dev->bus_type == B43_BUS_SSB &&
5587 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5588 struct pci_dev *pdev =
5589 dev->dev->sdev->bus->host_pci;
5590 if (pdev->device == 0x4328 ||
5591 pdev->device == 0x432a)
5592 nphy->pwg_gain_5ghz = true;
5593 }
5594#endif
5595 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5596 nphy->pwg_gain_5ghz = true;
5597 }
5598 }
5599
5600 if (dev->phy.rev >= 3) {
5601 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5602 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5603 }
ef1a628d
MB		 5604}
5605
fb11137a 5606static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5607{
fb11137a
MB		 5608 struct b43_phy *phy = &dev->phy;
5609 struct b43_phy_n *nphy = phy->n;
ef1a628d 5610
ef1a628d 5611 kfree(nphy);
fb11137a
MB		 5612 phy->n = NULL;
5613}
5614
5615static int b43_nphy_op_init(struct b43_wldev *dev)
5616{
5617 return b43_phy_initn(dev);
ef1a628d
MB		 5618}
5619
5620static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5621{
5622#if B43_DEBUG
5623 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5624 /* OFDM registers are onnly available on A/G-PHYs */
5625 b43err(dev->wl, "Invalid OFDM PHY access at "
5626 "0x%04X on N-PHY\n", offset);
5627 dump_stack();
5628 }
5629 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5630 /* Ext-G registers are only available on G-PHYs */
5631 b43err(dev->wl, "Invalid EXT-G PHY access at "
5632 "0x%04X on N-PHY\n", offset);
5633 dump_stack();
5634 }
5635#endif /* B43_DEBUG */
5636}
5637
5638static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5639{
5640 check_phyreg(dev, reg);
5641 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5642 return b43_read16(dev, B43_MMIO_PHY_DATA);
5643}
5644
5645static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5646{
5647 check_phyreg(dev, reg);
5648 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5649 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5650}
5651
755fd183
RM		 5652static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5653 u16 set)
5654{
5655 check_phyreg(dev, reg);
5656 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5657 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5658}
5659
ef1a628d
MB		 5660static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5661{
5662 /* Register 1 is a 32-bit register. */
5663 B43_WARN_ON(reg == 1);
a6aa05d6
RM		 5664
5665 if (dev->phy.rev >= 7)
5666 reg |= 0x200; /* Radio 0x2057 */
5667 else
5668 reg |= 0x100;
ef1a628d
MB		 5669
5670 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5671 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5672}
5673
5674static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5675{
5676 /* Register 1 is a 32-bit register. */
5677 B43_WARN_ON(reg == 1);
5678
5679 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5680 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5681}
5682
c2b7aefd 5683/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5684static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5685 bool blocked)
c2b7aefd
RM		 5686{
5687 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5688 b43err(dev->wl, "MAC not suspended\n");
5689
5690 if (blocked) {
5691 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5692 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5693 if (dev->phy.rev >= 7) {
5694 /* TODO */
5695 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5696 b43_radio_mask(dev, 0x09, ~0x2);
5697
5698 b43_radio_write(dev, 0x204D, 0);
5699 b43_radio_write(dev, 0x2053, 0);
5700 b43_radio_write(dev, 0x2058, 0);
5701 b43_radio_write(dev, 0x205E, 0);
5702 b43_radio_mask(dev, 0x2062, ~0xF0);
5703 b43_radio_write(dev, 0x2064, 0);
5704
5705 b43_radio_write(dev, 0x304D, 0);
5706 b43_radio_write(dev, 0x3053, 0);
5707 b43_radio_write(dev, 0x3058, 0);
5708 b43_radio_write(dev, 0x305E, 0);
5709 b43_radio_mask(dev, 0x3062, ~0xF0);
5710 b43_radio_write(dev, 0x3064, 0);
5711 }
5712 } else {
572d37a4 5713 if (dev->phy.rev >= 7) {
6fe55143
RM		 5714 if (!dev->phy.radio_on)
5715 b43_radio_2057_init(dev);
572d37a4
RM		 5716 b43_switch_channel(dev, dev->phy.channel);
5717 } else if (dev->phy.rev >= 3) {
6fe55143
RM		 5718 if (!dev->phy.radio_on)
5719 b43_radio_init2056(dev);
78159788 5720 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5721 } else {
5722 b43_radio_init2055(dev);
5723 }
5724 }
ef1a628d
MB		 5725}
5726
0f4091b9 5727/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5728static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5729{
2a870831
RM		 5730 u16 override = on ? 0x0 : 0x7FFF;
5731 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5732
2a870831
RM		 5733 if (dev->phy.rev >= 3) {
5734 if (on) {
5735 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5736 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5737 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5738 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5739 } else {
5740 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5741 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5742 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5743 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5744 }
5745 } else {
5746 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5747 }
cb24f57f
MB		 5748}
5749
ef1a628d
MB		 5750static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5751 unsigned int new_channel)
5752{
675a0b04
KB		 5753 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5754 enum nl80211_channel_type channel_type =
5755 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5756
ef1a628d
MB		 5757 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5758 if ((new_channel < 1) || (new_channel > 14))
5759 return -EINVAL;
5760 } else {
5761 if (new_channel > 200)
5762 return -EINVAL;
5763 }
5764
a656b6a9 5765 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5766}
5767
5768static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5769{
5770 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5771 return 1;
5772 return 36;
5773}
5774
ef1a628d
MB		 5775const struct b43_phy_operations b43_phyops_n = {
5776 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5777 .free = b43_nphy_op_free,
5778 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5779 .init = b43_nphy_op_init,
ef1a628d
MB		 5780 .phy_read = b43_nphy_op_read,
5781 .phy_write = b43_nphy_op_write,
755fd183 5782 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5783 .radio_read = b43_nphy_op_radio_read,
5784 .radio_write = b43_nphy_op_radio_write,
5785 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5786 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5787 .switch_channel = b43_nphy_op_switch_channel,
5788 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5789 .recalc_txpower = b43_nphy_op_recalc_txpower,
5790 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5791};
Linux kernel - Deliverables
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