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b43: N-PHY: complete 0x2057 radio init calibration
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b 38struct nphy_txgains {
40c68f20 39 u16 tx_lpf[2];
f8187b5b
RM		 40 u16 txgm[2];
41 u16 pga[2];
42 u16 pad[2];
43 u16 ipa[2];
44};
45
46struct nphy_iqcal_params {
40c68f20 47 u16 tx_lpf;
f8187b5b
RM		 48 u16 txgm;
49 u16 pga;
50 u16 pad;
51 u16 ipa;
52 u16 cal_gain;
53 u16 ncorr[5];
54};
55
56struct nphy_iq_est {
57 s32 iq0_prod;
58 u32 i0_pwr;
59 u32 q0_pwr;
60 s32 iq1_prod;
61 u32 i1_pwr;
62 u32 q1_pwr;
63};
424047e6 64
67c0d6e2
RM		 65enum b43_nphy_rf_sequence {
66 B43_RFSEQ_RX2TX,
67 B43_RFSEQ_TX2RX,
68 B43_RFSEQ_RESET2RX,
69 B43_RFSEQ_UPDATE_GAINH,
70 B43_RFSEQ_UPDATE_GAINL,
71 B43_RFSEQ_UPDATE_GAINU,
72};
73
40c68f20
RM		 74enum n_rf_ctl_over_cmd {
75 N_RF_CTL_OVER_CMD_RXRF_PU = 0,
76 N_RF_CTL_OVER_CMD_RX_PU = 1,
77 N_RF_CTL_OVER_CMD_TX_PU = 2,
78 N_RF_CTL_OVER_CMD_RX_GAIN = 3,
79 N_RF_CTL_OVER_CMD_TX_GAIN = 4,
80};
81
89e43dad
RM		 82enum n_intc_override {
83 N_INTC_OVERRIDE_OFF = 0,
84 N_INTC_OVERRIDE_TRSW = 1,
85 N_INTC_OVERRIDE_PA = 2,
86 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
87 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
88};
89
2a2d0589
RM		 90enum n_rssi_type {
91 N_RSSI_W1 = 0,
92 N_RSSI_W2,
93 N_RSSI_NB,
94 N_RSSI_IQ,
95 N_RSSI_TSSI_2G,
96 N_RSSI_TSSI_5G,
97 N_RSSI_TBD,
76b002bd
RM		 98};
99
6aa38725
RM		 100enum n_rail_type {
101 N_RAIL_I = 0,
102 N_RAIL_Q = 1,
76b002bd
RM		 103};
104
c002831a
RM		 105static inline bool b43_nphy_ipa(struct b43_wldev *dev)
106{
107 enum ieee80211_band band = b43_current_band(dev->wl);
108 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
109 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
110}
111
e0c9a021
RM		 112/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
113static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
114{
115 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
116 B43_NPHY_RFSEQCA_RXEN_SHIFT;
117}
118
ab499217 119/**************************************************
89e43dad 120 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 121 **************************************************/
18c8adeb 122
ab499217
RM		 123/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
124static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
125 enum b43_nphy_rf_sequence seq)
d1591314 126{
ab499217
RM		 127 static const u16 trigger[] = {
128 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
129 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
130 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
131 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
132 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
133 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
134 };
135 int i;
136 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 137
ab499217 138 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 139
ab499217
RM		 140 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
141 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
142 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
143 for (i = 0; i < 200; i++) {
144 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
145 goto ok;
146 msleep(1);
147 }
148 b43err(dev->wl, "RF sequence status timeout\n");
149ok:
150 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
151}
e5255ccc 152
303415e2
RM		 153static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field,
154 u16 value, u8 core, bool off,
155 u8 override_id)
156{
157 /* TODO */
158}
159
c071b9f6 160/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 161static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
162 u16 value, u8 core, bool off,
163 u8 override)
c071b9f6 164{
303415e2 165 struct b43_phy *phy = &dev->phy;
c071b9f6
RM		 166 const struct nphy_rf_control_override_rev7 *e;
167 u16 en_addrs[3][2] = {
168 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
169 };
170 u16 en_addr;
171 u16 en_mask = field;
172 u16 val_addr;
173 u8 i;
174
303415e2
RM		 175 if (phy->rev >= 19 || phy->rev < 3) {
176 B43_WARN_ON(1);
177 return;
178 }
179
c071b9f6
RM		 180 /* Remember: we can get NULL! */
181 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
182
183 for (i = 0; i < 2; i++) {
184 if (override >= ARRAY_SIZE(en_addrs)) {
185 b43err(dev->wl, "Invalid override value %d\n", override);
186 return;
187 }
188 en_addr = en_addrs[override][i];
189
8ce9beac
FP		 190 if (e)
191 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 192
193 if (off) {
194 b43_phy_mask(dev, en_addr, ~en_mask);
195 if (e) /* Do it safer, better than wl */
196 b43_phy_mask(dev, val_addr, ~e->val_mask);
197 } else {
198 if (!core || (core & (1 << i))) {
199 b43_phy_set(dev, en_addr, en_mask);
200 if (e)
201 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
202 }
203 }
204 }
205}
206
40c68f20
RM		 207/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */
208static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev,
209 enum n_rf_ctl_over_cmd cmd,
210 u16 value, u8 core, bool off)
211{
212 struct b43_phy *phy = &dev->phy;
213 u16 tmp;
214
215 B43_WARN_ON(phy->rev < 7);
216
217 switch (cmd) {
218 case N_RF_CTL_OVER_CMD_RXRF_PU:
219 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1);
220 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1);
221 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1);
222 break;
223 case N_RF_CTL_OVER_CMD_RX_PU:
224 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1);
225 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
226 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1);
227 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2);
228 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1);
229 break;
230 case N_RF_CTL_OVER_CMD_TX_PU:
231 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0);
232 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
233 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2);
234 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1);
235 break;
236 case N_RF_CTL_OVER_CMD_RX_GAIN:
237 tmp = value & 0xFF;
238 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0);
239 tmp = value >> 8;
240 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0);
241 break;
242 case N_RF_CTL_OVER_CMD_TX_GAIN:
243 tmp = value & 0x7FFF;
244 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0);
245 tmp = value >> 14;
246 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0);
247 break;
248 }
249}
250
ab499217 251/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 252static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
253 u16 value, u8 core, bool off)
ab499217
RM		 254{
255 int i;
256 u8 index = fls(field);
257 u8 addr, en_addr, val_addr;
258 /* we expect only one bit set */
259 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 260
ab499217
RM		 261 if (dev->phy.rev >= 3) {
262 const struct nphy_rf_control_override_rev3 *rf_ctrl;
263 for (i = 0; i < 2; i++) {
264 if (index == 0 || index == 16) {
265 b43err(dev->wl,
266 "Unsupported RF Ctrl Override call\n");
267 return;
268 }
e5255ccc 269
ab499217
RM		 270 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
271 en_addr = B43_PHY_N((i == 0) ?
272 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
273 val_addr = B43_PHY_N((i == 0) ?
274 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 275
ab499217
RM		 276 if (off) {
277 b43_phy_mask(dev, en_addr, ~(field));
278 b43_phy_mask(dev, val_addr,
279 ~(rf_ctrl->val_mask));
280 } else {
b97c0718 281 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 282 b43_phy_set(dev, en_addr, field);
283 b43_phy_maskset(dev, val_addr,
284 ~(rf_ctrl->val_mask),
285 (value << rf_ctrl->val_shift));
286 }
287 }
288 }
289 } else {
290 const struct nphy_rf_control_override_rev2 *rf_ctrl;
291 if (off) {
292 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
293 value = 0;
294 } else {
295 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
296 }
d4814e69 297
ab499217
RM		 298 for (i = 0; i < 2; i++) {
299 if (index <= 1 || index == 16) {
300 b43err(dev->wl,
301 "Unsupported RF Ctrl Override call\n");
302 return;
303 }
d4814e69 304
ab499217
RM		 305 if (index == 2 || index == 10 ||
306 (index >= 13 && index <= 15)) {
307 core = 1;
308 }
d4814e69 309
ab499217
RM		 310 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
311 addr = B43_PHY_N((i == 0) ?
312 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 313
b97c0718 314 if ((1 << i) & core)
ab499217
RM		 315 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
316 (value << rf_ctrl->shift));
317
318 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
319 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
320 B43_NPHY_RFCTL_CMD_START);
321 udelay(1);
322 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
323 }
324 }
d4814e69
RM		 325}
326
4256ba77
RM		 327static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
328 enum n_intc_override intc_override,
329 u16 value, u8 core_sel)
330{
331 u16 reg, tmp, tmp2, val;
332 int core;
333
303415e2
RM		 334 /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */
335
4256ba77
RM		 336 for (core = 0; core < 2; core++) {
337 if ((core_sel == 1 && core != 0) ||
338 (core_sel == 2 && core != 1))
339 continue;
340
341 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
342
343 switch (intc_override) {
344 case N_INTC_OVERRIDE_OFF:
345 b43_phy_write(dev, reg, 0);
346 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
347 break;
348 case N_INTC_OVERRIDE_TRSW:
349 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
350 b43_phy_set(dev, reg, 0x400);
351
352 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
353 b43_phy_set(dev, 0x2ff, 0x2000);
354 b43_phy_set(dev, 0x2ff, 0x0001);
355 break;
356 case N_INTC_OVERRIDE_PA:
357 tmp = 0x0030;
358 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
359 val = value << 5;
360 else
361 val = value << 4;
362 b43_phy_maskset(dev, reg, ~tmp, val);
363 b43_phy_set(dev, reg, 0x1000);
364 break;
365 case N_INTC_OVERRIDE_EXT_LNA_PU:
366 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
367 tmp = 0x0001;
368 tmp2 = 0x0004;
369 val = value;
370 } else {
371 tmp = 0x0004;
372 tmp2 = 0x0001;
373 val = value << 2;
374 }
375 b43_phy_maskset(dev, reg, ~tmp, val);
376 b43_phy_mask(dev, reg, ~tmp2);
377 break;
378 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
379 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
380 tmp = 0x0002;
381 tmp2 = 0x0008;
382 val = value << 1;
383 } else {
384 tmp = 0x0008;
385 tmp2 = 0x0002;
386 val = value << 3;
387 }
388 b43_phy_maskset(dev, reg, ~tmp, val);
389 b43_phy_mask(dev, reg, ~tmp2);
390 break;
391 }
392 }
393}
394
ab499217 395/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 396static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
397 enum n_intc_override intc_override,
398 u16 value, u8 core)
d4814e69 399{
ab499217
RM		 400 u8 i, j;
401 u16 reg, tmp, val;
38646eba 402
4256ba77
RM		 403 if (dev->phy.rev >= 7) {
404 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
405 core);
406 return;
407 }
408
d4814e69
RM		 409 B43_WARN_ON(dev->phy.rev < 3);
410
ab499217
RM		 411 for (i = 0; i < 2; i++) {
412 if ((core == 1 && i == 1) || (core == 2 && !i))
413 continue;
38646eba 414
ab499217
RM		 415 reg = (i == 0) ?
416 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 417 b43_phy_set(dev, reg, 0x400);
38646eba 418
89e43dad
RM		 419 switch (intc_override) {
420 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 421 b43_phy_write(dev, reg, 0);
422 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
423 break;
89e43dad 424 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 425 if (!i) {
426 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
427 0xFC3F, (value << 6));
428 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
429 0xFFFE, 1);
430 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
431 B43_NPHY_RFCTL_CMD_START);
432 for (j = 0; j < 100; j++) {
603431e9 433 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 434 j = 0;
435 break;
436 }
437 udelay(10);
38646eba 438 }
ab499217
RM		 439 if (j)
440 b43err(dev->wl,
441 "intc override timeout\n");
442 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
443 0xFFFE);
38646eba 444 } else {
ab499217
RM		 445 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
446 0xFC3F, (value << 6));
447 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
448 0xFFFE, 1);
449 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
450 B43_NPHY_RFCTL_CMD_RXTX);
451 for (j = 0; j < 100; j++) {
603431e9 452 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 453 j = 0;
454 break;
455 }
456 udelay(10);
457 }
458 if (j)
459 b43err(dev->wl,
460 "intc override timeout\n");
461 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
462 0xFFFE);
38646eba 463 }
ab499217 464 break;
89e43dad 465 case N_INTC_OVERRIDE_PA:
ab499217
RM		 466 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
467 tmp = 0x0020;
468 val = value << 5;
469 } else {
470 tmp = 0x0010;
471 val = value << 4;
472 }
473 b43_phy_maskset(dev, reg, ~tmp, val);
474 break;
89e43dad 475 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 476 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
477 tmp = 0x0001;
478 val = value;
479 } else {
480 tmp = 0x0004;
481 val = value << 2;
482 }
483 b43_phy_maskset(dev, reg, ~tmp, val);
484 break;
89e43dad 485 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 486 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
487 tmp = 0x0002;
488 val = value << 1;
489 } else {
490 tmp = 0x0008;
491 val = value << 3;
492 }
493 b43_phy_maskset(dev, reg, ~tmp, val);
494 break;
38646eba 495 }
38646eba 496 }
ab499217 497}
38646eba 498
ab499217
RM		 499/**************************************************
500 * Various PHY ops
501 **************************************************/
502
503/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
504static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
505 const u16 *clip_st)
506{
507 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
508 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 509}
510
ab499217
RM		 511/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
512static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 513{
ab499217
RM		 514 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
515 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 516}
517
ab499217
RM		 518/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
519static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 520{
ab499217 521 u16 tmp;
161d540c 522
ab499217
RM		 523 if (dev->dev->core_rev == 16)
524 b43_mac_suspend(dev);
161d540c 525
ab499217
RM		 526 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
527 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
528 B43_NPHY_CLASSCTL_WAITEDEN);
529 tmp &= ~mask;
530 tmp |= (val & mask);
531 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 532
ab499217
RM		 533 if (dev->dev->core_rev == 16)
534 b43_mac_enable(dev);
161d540c 535
ab499217
RM		 536 return tmp;
537}
161d540c 538
ab499217
RM		 539/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
540static void b43_nphy_reset_cca(struct b43_wldev *dev)
541{
542 u16 bbcfg;
161d540c 543
ab499217
RM		 544 b43_phy_force_clock(dev, 1);
545 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
546 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
547 udelay(1);
548 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
549 b43_phy_force_clock(dev, 0);
550 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
551}
161d540c 552
ab499217
RM		 553/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
554static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
555{
556 struct b43_phy *phy = &dev->phy;
557 struct b43_phy_n *nphy = phy->n;
161d540c 558
ab499217
RM		 559 if (enable) {
560 static const u16 clip[] = { 0xFFFF, 0xFFFF };
561 if (nphy->deaf_count++ == 0) {
562 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
bc36e994
RM		 563 b43_nphy_classifier(dev, 0x7,
564 B43_NPHY_CLASSCTL_WAITEDEN);
ab499217
RM		 565 b43_nphy_read_clip_detection(dev, nphy->clip_state);
566 b43_nphy_write_clip_detection(dev, clip);
567 }
568 b43_nphy_reset_cca(dev);
161d540c 569 } else {
ab499217
RM		 570 if (--nphy->deaf_count == 0) {
571 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
572 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 573 }
161d540c 574 }
161d540c
RM		 575}
576
40c68f20
RM		 577/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
578static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
579{
580 if (!offset)
581 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
582 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
583}
584
64712095
RM		 585/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
586static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 587{
161d540c 588 struct b43_phy_n *nphy = dev->phy.n;
161d540c 589
64712095
RM		 590 u8 i;
591 s16 tmp;
592 u16 data[4];
593 s16 gain[2];
594 u16 minmax[2];
595 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 596
597 if (nphy->hang_avoid)
598 b43_nphy_stay_in_carrier_search(dev, 1);
599
64712095 600 if (nphy->gain_boost) {
161d540c 601 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 602 gain[0] = 6;
603 gain[1] = 6;
161d540c 604 } else {
64712095
RM		 605 tmp = 40370 - 315 * dev->phy.channel;
606 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
607 tmp = 23242 - 224 * dev->phy.channel;
608 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 609 }
64712095
RM		 610 } else {
611 gain[0] = 0;
612 gain[1] = 0;
161d540c 613 }
161d540c
RM		 614
615 for (i = 0; i < 2; i++) {
64712095
RM		 616 if (nphy->elna_gain_config) {
617 data[0] = 19 + gain[i];
618 data[1] = 25 + gain[i];
619 data[2] = 25 + gain[i];
620 data[3] = 25 + gain[i];
161d540c 621 } else {
64712095
RM		 622 data[0] = lna_gain[0] + gain[i];
623 data[1] = lna_gain[1] + gain[i];
624 data[2] = lna_gain[2] + gain[i];
625 data[3] = lna_gain[3] + gain[i];
161d540c 626 }
64712095 627 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 628
64712095 629 minmax[i] = 23 + gain[i];
161d540c
RM		 630 }
631
64712095
RM		 632 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
633 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
634 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
635 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 636
637 if (nphy->hang_avoid)
638 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 639}
640
ab499217
RM		 641/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
642static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
643 u8 *events, u8 *delays, u8 length)
0eff8fcd 644{
ab499217
RM		 645 struct b43_phy_n *nphy = dev->phy.n;
646 u8 i;
647 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
648 u16 offset1 = cmd << 4;
649 u16 offset2 = offset1 + 0x80;
0eff8fcd 650
ab499217
RM		 651 if (nphy->hang_avoid)
652 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 653
ab499217
RM		 654 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
655 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 656
ab499217
RM		 657 for (i = length; i < 16; i++) {
658 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
659 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 660 }
ab499217
RM		 661
662 if (nphy->hang_avoid)
663 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 664}
7955de0c 665
572d37a4
RM		 666/**************************************************
667 * Radio 0x2057
668 **************************************************/
669
fe255b40
RM		 670static void b43_radio_2057_chantab_upload(struct b43_wldev *dev,
671 const struct b43_nphy_chantabent_rev7 *e_r7,
672 const struct b43_nphy_chantabent_rev7_2g *e_r7_2g)
673{
674 if (e_r7_2g) {
675 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
676 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
677 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
678 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
679 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
680 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
681 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
682 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
683 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
684 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
685 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
686 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
687 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
688 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
689 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
690 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
691 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
692 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);
693
694 } else {
695 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
696 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
697 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
698 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
699 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
700 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
701 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
702 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
703 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
704 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
705 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
706 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
707 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
708 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
709 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
710 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
711 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
712 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
713 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
714 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
715 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
716 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
717 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
718 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
719 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
720 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
721 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
722 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
723 }
724}
725
726static void b43_radio_2057_setup(struct b43_wldev *dev,
727 const struct b43_nphy_chantabent_rev7 *tabent_r7,
728 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g)
729{
730 struct b43_phy *phy = &dev->phy;
731
732 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g);
733
734 switch (phy->radio_rev) {
735 case 0 ... 4:
736 case 6:
737 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
738 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
739 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
740 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
741 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
742 } else {
743 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
744 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
745 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
746 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
747 }
748 break;
162bee1a
RM		 749 case 9: /* e.g. PHY rev 16 */
750 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20);
751 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18);
752 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
753 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38);
754 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f);
755
756 if (b43_is_40mhz(dev)) {
757 /* TODO */
758 } else {
759 b43_radio_write(dev,
760 R2057_PAD_BIAS_FILTER_BWS_CORE0,
761 0x3c);
762 b43_radio_write(dev,
763 R2057_PAD_BIAS_FILTER_BWS_CORE1,
764 0x3c);
765 }
766 }
767 break;
3b7caa29
RM		 768 case 14: /* 2 GHz only */
769 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b);
770 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
771 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f);
772 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f);
773 break;
fe255b40
RM		 774 }
775
162bee1a
RM		 776 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
777 u16 txmix2g_tune_boost_pu = 0;
778 u16 pad2g_tune_pus = 0;
779
780 if (b43_nphy_ipa(dev)) {
781 switch (phy->radio_rev) {
782 case 9:
783 txmix2g_tune_boost_pu = 0x0041;
784 /* TODO */
785 break;
3b7caa29
RM		 786 case 14:
787 txmix2g_tune_boost_pu = 0x21;
788 pad2g_tune_pus = 0x23;
789 break;
162bee1a 790 }
162bee1a
RM		 791 }
792
793 if (txmix2g_tune_boost_pu)
794 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
795 txmix2g_tune_boost_pu);
796 if (pad2g_tune_pus)
797 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0,
798 pad2g_tune_pus);
799 if (txmix2g_tune_boost_pu)
800 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
801 txmix2g_tune_boost_pu);
802 if (pad2g_tune_pus)
803 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1,
804 pad2g_tune_pus);
805 }
fe255b40
RM		 806
807 usleep_range(50, 100);
808
809 /* VCO calibration */
810 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01);
811 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
812 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
813 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01);
814 usleep_range(300, 600);
815}
816
e90cf1c7
RM		 817/* Calibrate resistors in LPF of PLL?
818 * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal
819 */
572d37a4
RM		 820static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
821{
822 struct b43_phy *phy = &dev->phy;
ef0d635e
RM		 823 u16 saved_regs_phy[12];
824 u16 saved_regs_phy_rf[6];
825 u16 saved_regs_radio[2] = { };
826 static const u16 phy_to_store[] = {
827 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2,
828 B43_NPHY_RFCTL_LUT_TRSW_LO1, B43_NPHY_RFCTL_LUT_TRSW_LO2,
829 B43_NPHY_RFCTL_RXG1, B43_NPHY_RFCTL_RXG2,
830 B43_NPHY_RFCTL_TXG1, B43_NPHY_RFCTL_TXG2,
831 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
832 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
833 };
834 static const u16 phy_to_store_rf[] = {
835 B43_NPHY_REV3_RFCTL_OVER0, B43_NPHY_REV3_RFCTL_OVER1,
836 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
837 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
838 };
572d37a4 839 u16 tmp;
ef0d635e 840 int i;
572d37a4 841
ef0d635e
RM		 842 /* Save */
843 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
844 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]);
845 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
846 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]);
847
848 /* Set */
849 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
850 b43_phy_write(dev, phy_to_store[i], 0);
851 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff);
852 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff);
853 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff);
854 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff);
855 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f);
856 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f);
857
858 switch (phy->radio_rev) {
859 case 5:
860 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2);
572d37a4
RM		 861 udelay(10);
862 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
ef0d635e
RM		 863 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1);
864 break;
865 case 9:
866 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
867 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
868 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
869 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11);
870 break;
871 case 14:
872 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
873 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2);
874 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
875 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
876 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2);
877 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1);
878 break;
572d37a4
RM		 879 }
880
e90cf1c7 881 /* Enable */
572d37a4
RM		 882 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
883 udelay(10);
e90cf1c7
RM		 884
885 /* Start */
886 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2);
887 usleep_range(100, 200);
888
889 /* Stop */
890 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
891
892 /* Wait and check for result */
893 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
572d37a4
RM		 894 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
895 return 0;
896 }
572d37a4 897 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
e90cf1c7
RM		 898
899 /* Disable */
572d37a4
RM		 900 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
901
ef0d635e
RM		 902 /* Restore */
903 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
904 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]);
905 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
906 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]);
907
908 switch (phy->radio_rev) {
909 case 0 ... 4:
910 case 6:
572d37a4
RM		 911 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
912 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
913 tmp << 2);
ef0d635e
RM		 914 break;
915 case 5:
916 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
917 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2);
918 break;
919 case 9:
920 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
921 break;
922 case 14:
923 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
924 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]);
925 break;
572d37a4
RM		 926 }
927
928 return tmp & 0x3e;
929}
930
e90cf1c7
RM		 931/* Calibrate the internal RC oscillator?
932 * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal
933 */
572d37a4
RM		 934static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
935{
936 struct b43_phy *phy = &dev->phy;
937 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
938 phy->radio_rev == 6);
939 u16 tmp;
940
e90cf1c7 941 /* Setup cal */
572d37a4
RM		 942 if (special) {
943 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
944 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
945 } else {
e90cf1c7 946 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61);
ef0d635e 947 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9);
572d37a4
RM		 948 }
949 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
e90cf1c7
RM		 950
951 /* Start, wait, stop */
572d37a4 952 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7 953 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4
RM		 954 5000000))
955 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
e90cf1c7 956 usleep_range(35, 70);
572d37a4 957 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 958 usleep_range(70, 140);
959
960 /* Setup cal */
572d37a4
RM		 961 if (special) {
962 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
963 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
964 } else {
e90cf1c7 965 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69);
572d37a4
RM		 966 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
967 }
968 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
e90cf1c7
RM		 969
970 /* Start, wait, stop */
971 usleep_range(35, 70);
572d37a4 972 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7
RM		 973 usleep_range(70, 140);
974 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4 975 5000000))
6c187236 976 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
e90cf1c7 977 usleep_range(35, 70);
572d37a4 978 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 979 usleep_range(70, 140);
980
981 /* Setup cal */
572d37a4
RM		 982 if (special) {
983 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
984 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
985 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
986 } else {
e90cf1c7 987 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73);
572d37a4
RM		 988 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
989 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
990 }
e90cf1c7
RM		 991
992 /* Start, wait, stop */
993 usleep_range(35, 70);
572d37a4 994 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7
RM		 995 usleep_range(70, 140);
996 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4
RM		 997 5000000)) {
998 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
999 return 0;
1000 }
1001 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
e90cf1c7 1002 usleep_range(35, 70);
572d37a4 1003 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 1004 usleep_range(70, 140);
1005
1006 if (special)
1007 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1);
1008 else
1009 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1);
1010
572d37a4
RM		 1011 return tmp;
1012}
1013
1014static void b43_radio_2057_init_pre(struct b43_wldev *dev)
1015{
1016 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1017 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1018 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
1019 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1020 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
1021}
1022
1023static void b43_radio_2057_init_post(struct b43_wldev *dev)
1024{
1025 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
1026
ef0d635e
RM		 1027 if (0) /* FIXME: Is this BCM43217 specific? */
1028 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2);
1029
572d37a4
RM		 1030 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
1031 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
1032 mdelay(2);
1033 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
1034 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
1035
90e569d1 1036 if (dev->phy.do_full_init) {
572d37a4
RM		 1037 b43_radio_2057_rcal(dev);
1038 b43_radio_2057_rccal(dev);
1039 }
1040 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
572d37a4
RM		 1041}
1042
1043/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
1044static void b43_radio_2057_init(struct b43_wldev *dev)
1045{
1046 b43_radio_2057_init_pre(dev);
1047 r2057_upload_inittabs(dev);
1048 b43_radio_2057_init_post(dev);
1049}
1050
ab499217 1051/**************************************************
884a5228 1052 * Radio 0x2056
ab499217 1053 **************************************************/
7955de0c 1054
d4814e69
RM		 1055static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
1056 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 1057{
d4814e69
RM		 1058 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
1059 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
1060 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
1061 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
1062 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
1063 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
1064 e->radio_syn_pll_loopfilter1);
1065 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
1066 e->radio_syn_pll_loopfilter2);
1067 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
1068 e->radio_syn_pll_loopfilter3);
1069 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
1070 e->radio_syn_pll_loopfilter4);
1071 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
1072 e->radio_syn_pll_loopfilter5);
1073 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
1074 e->radio_syn_reserved_addr27);
1075 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
1076 e->radio_syn_reserved_addr28);
1077 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
1078 e->radio_syn_reserved_addr29);
1079 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
1080 e->radio_syn_logen_vcobuf1);
1081 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
1082 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
1083 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
1084
1085 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
1086 e->radio_rx0_lnaa_tune);
1087 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
1088 e->radio_rx0_lnag_tune);
1089
1090 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
1091 e->radio_tx0_intpaa_boost_tune);
1092 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
1093 e->radio_tx0_intpag_boost_tune);
1094 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
1095 e->radio_tx0_pada_boost_tune);
1096 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
1097 e->radio_tx0_padg_boost_tune);
1098 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
1099 e->radio_tx0_pgaa_boost_tune);
1100 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
1101 e->radio_tx0_pgag_boost_tune);
1102 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
1103 e->radio_tx0_mixa_boost_tune);
1104 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
1105 e->radio_tx0_mixg_boost_tune);
1106
1107 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
1108 e->radio_rx1_lnaa_tune);
1109 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
1110 e->radio_rx1_lnag_tune);
1111
1112 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
1113 e->radio_tx1_intpaa_boost_tune);
1114 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
1115 e->radio_tx1_intpag_boost_tune);
1116 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
1117 e->radio_tx1_pada_boost_tune);
1118 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
1119 e->radio_tx1_padg_boost_tune);
1120 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
1121 e->radio_tx1_pgaa_boost_tune);
1122 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
1123 e->radio_tx1_pgag_boost_tune);
1124 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
1125 e->radio_tx1_mixa_boost_tune);
1126 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
1127 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 1128}
1129
d4814e69
RM		 1130/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
1131static void b43_radio_2056_setup(struct b43_wldev *dev,
1132 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 1133{
39e971ef 1134 struct b43_phy *phy = &dev->phy;
0581483a 1135 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 1136 enum ieee80211_band band = b43_current_band(dev->wl);
1137 u16 offset;
1138 u8 i;
d3d178f0
RM		 1139 u16 bias, cbias;
1140 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
1141 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
b88cdde9 1142 bool is_pkg_fab_smic;
036cafe4 1143
d4814e69 1144 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 1145
b88cdde9
RM		 1146 is_pkg_fab_smic =
1147 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
1148 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
1149 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
1150 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
1151
d4814e69 1152 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 1153 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
1154
1155 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1156 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1157 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1158 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
b88cdde9
RM		 1159 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
1160 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 1161 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
1162 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
1163 } else {
1164 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
1165 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 1166 }
53a6e234 1167 }
b88cdde9
RM		 1168 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
1169 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1170 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
1171 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
1172 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
1173 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
1174 }
38646eba
RM		 1175 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1176 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1177 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1178 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1179 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
1180 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 1181 }
53a6e234 1182
38646eba
RM		 1183 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
1184 for (i = 0; i < 2; i++) {
1185 offset = i ? B2056_TX1 : B2056_TX0;
1186 if (dev->phy.rev >= 5) {
1187 b43_radio_write(dev,
1188 offset | B2056_TX_PADG_IDAC, 0xcc);
1189
b88cdde9
RM		 1190 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
1191 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 1192 bias = 0x40;
1193 cbias = 0x45;
1194 pag_boost = 0x5;
1195 pgag_boost = 0x33;
1196 mixg_boost = 0x55;
1197 } else {
1198 bias = 0x25;
1199 cbias = 0x20;
b88cdde9
RM		 1200 if (is_pkg_fab_smic) {
1201 bias = 0x2a;
1202 cbias = 0x38;
1203 }
38646eba
RM		 1204 pag_boost = 0x4;
1205 pgag_boost = 0x03;
1206 mixg_boost = 0x65;
1207 }
1208 padg_boost = 0x77;
1209
1210 b43_radio_write(dev,
1211 offset | B2056_TX_INTPAG_IMAIN_STAT,
1212 bias);
1213 b43_radio_write(dev,
1214 offset | B2056_TX_INTPAG_IAUX_STAT,
1215 bias);
1216 b43_radio_write(dev,
1217 offset | B2056_TX_INTPAG_CASCBIAS,
1218 cbias);
1219 b43_radio_write(dev,
1220 offset | B2056_TX_INTPAG_BOOST_TUNE,
1221 pag_boost);
1222 b43_radio_write(dev,
1223 offset | B2056_TX_PGAG_BOOST_TUNE,
1224 pgag_boost);
1225 b43_radio_write(dev,
1226 offset | B2056_TX_PADG_BOOST_TUNE,
1227 padg_boost);
1228 b43_radio_write(dev,
1229 offset | B2056_TX_MIXG_BOOST_TUNE,
1230 mixg_boost);
1231 } else {
bee6d4b2 1232 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
38646eba
RM		 1233 b43_radio_write(dev,
1234 offset | B2056_TX_INTPAG_IMAIN_STAT,
1235 bias);
1236 b43_radio_write(dev,
1237 offset | B2056_TX_INTPAG_IAUX_STAT,
1238 bias);
1239 b43_radio_write(dev,
1240 offset | B2056_TX_INTPAG_CASCBIAS,
1241 0x30);
1242 }
1243 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
1244 }
1245 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
39e971ef 1246 u16 freq = phy->chandef->chan->center_freq;
d3d178f0
RM		 1247 if (freq < 5100) {
1248 paa_boost = 0xA;
1249 pada_boost = 0x77;
1250 pgaa_boost = 0xF;
1251 mixa_boost = 0xF;
1252 } else if (freq < 5340) {
1253 paa_boost = 0x8;
1254 pada_boost = 0x77;
1255 pgaa_boost = 0xFB;
1256 mixa_boost = 0xF;
1257 } else if (freq < 5650) {
1258 paa_boost = 0x0;
1259 pada_boost = 0x77;
1260 pgaa_boost = 0xB;
1261 mixa_boost = 0xF;
1262 } else {
1263 paa_boost = 0x0;
1264 pada_boost = 0x77;
1265 if (freq != 5825)
1266 pgaa_boost = -(freq - 18) / 36 + 168;
1267 else
1268 pgaa_boost = 6;
1269 mixa_boost = 0xF;
1270 }
1271
b88cdde9
RM		 1272 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
1273
d3d178f0
RM		 1274 for (i = 0; i < 2; i++) {
1275 offset = i ? B2056_TX1 : B2056_TX0;
1276
1277 b43_radio_write(dev,
1278 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
1279 b43_radio_write(dev,
1280 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
1281 b43_radio_write(dev,
1282 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
1283 b43_radio_write(dev,
1284 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
1285 b43_radio_write(dev,
1286 offset | B2056_TX_TXSPARE1, 0x30);
1287 b43_radio_write(dev,
1288 offset | B2056_TX_PA_SPARE2, 0xee);
1289 b43_radio_write(dev,
1290 offset | B2056_TX_PADA_CASCBIAS, 0x03);
1291 b43_radio_write(dev,
b88cdde9 1292 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
d3d178f0 1293 b43_radio_write(dev,
b88cdde9 1294 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
d3d178f0 1295 b43_radio_write(dev,
b88cdde9 1296 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
d3d178f0 1297 }
a2d9bc6f 1298 }
38646eba 1299
d4814e69
RM		 1300 udelay(50);
1301 /* VCO calibration */
1302 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
1303 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1304 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
1305 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1306 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
1307 udelay(300);
53a6e234
MB		 1308}
1309
d3d178f0
RM		 1310static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
1311{
1312 struct b43_phy *phy = &dev->phy;
1313 u16 mast2, tmp;
1314
1315 if (phy->rev != 3)
1316 return 0;
1317
1318 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
1319 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
1320
1321 udelay(10);
1322 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1323 udelay(10);
1324 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
1325
1326 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
1327 1000000)) {
1328 b43err(dev->wl, "Radio recalibration timeout\n");
1329 return 0;
1330 }
1331
1332 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1333 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1334 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1335
1336 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1337
1338 return tmp & 0x1f;
1339}
1340
ea7ee14b
RM		 1341static void b43_radio_init2056_pre(struct b43_wldev *dev)
1342{
1343 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1344 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1345 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1346 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1347 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1348 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1349 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1350 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1351 B43_NPHY_RFCTL_CMD_CHIP0PU);
1352}
1353
1354static void b43_radio_init2056_post(struct b43_wldev *dev)
1355{
1356 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1357 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1358 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1359 msleep(1);
1360 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1361 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1362 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
90e569d1 1363 if (dev->phy.do_full_init)
d3d178f0 1364 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 1365}
1366
d817f4e1
RM		 1367/*
1368 * Initialize a Broadcom 2056 N-radio
1369 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1370 */
1371static void b43_radio_init2056(struct b43_wldev *dev)
1372{
ea7ee14b
RM		 1373 b43_radio_init2056_pre(dev);
1374 b2056_upload_inittabs(dev, 0, 0);
1375 b43_radio_init2056_post(dev);
d817f4e1
RM		 1376}
1377
884a5228
RM		 1378/**************************************************
1379 * Radio 0x2055
1380 **************************************************/
1381
1382static void b43_chantab_radio_upload(struct b43_wldev *dev,
1383 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1384{
884a5228
RM		 1385 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1386 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1387 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1388 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1389 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 1390
884a5228
RM		 1391 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1392 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1393 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1394 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1395 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1396
884a5228
RM		 1397 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1398 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1399 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1400 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1401 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1402
884a5228
RM		 1403 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1404 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1405 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1406 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1407 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1408
884a5228
RM		 1409 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1410 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1411 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1412 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1413 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1414
884a5228
RM		 1415 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1416 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 1417}
1418
884a5228
RM		 1419/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1420static void b43_radio_2055_setup(struct b43_wldev *dev,
1421 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1422{
884a5228 1423 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 1424
884a5228
RM		 1425 b43_chantab_radio_upload(dev, e);
1426 udelay(50);
1427 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1428 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1429 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1430 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1431 udelay(300);
95b66bad
MB		 1432}
1433
884a5228 1434static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1435{
884a5228
RM		 1436 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1437 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1438 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1439 B43_NPHY_RFCTL_CMD_CHIP0PU |
1440 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1441 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1442 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1443}
1444
884a5228 1445static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1446{
1447 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1448 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1449 bool workaround = false;
2faa6b83 1450
884a5228
RM		 1451 if (sprom->revision < 4)
1452 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1453 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1454 && dev->dev->board_rev >= 0x41);
2faa6b83 1455 else
884a5228
RM		 1456 workaround =
1457 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1458
884a5228
RM		 1459 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1460 if (workaround) {
1461 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1462 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1463 }
1464 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1465 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1466 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1467 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1468 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1469 msleep(1);
1470 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1471 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1472 b43err(dev->wl, "radio post init timeout\n");
1473 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1474 b43_switch_channel(dev, dev->phy.channel);
1475 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1476 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1477 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1478 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1479 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1480 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1481 if (!nphy->gain_boost) {
1482 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1483 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1484 } else {
1485 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1486 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1487 }
1488 udelay(2);
2faa6b83
RM		 1489}
1490
884a5228
RM		 1491/*
1492 * Initialize a Broadcom 2055 N-radio
1493 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1494 */
1495static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1496{
884a5228
RM		 1497 b43_radio_init2055_pre(dev);
1498 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1499 /* Follow wl, not specs. Do not force uploading all regs */
1500 b2055_upload_inittab(dev, 0, 0);
a67162ab 1501 } else {
884a5228
RM		 1502 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1503 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1504 }
884a5228 1505 b43_radio_init2055_post(dev);
a67162ab
RM		 1506}
1507
8be89535
RM		 1508/**************************************************
1509 * Samples
1510 **************************************************/
026816fc 1511
8be89535
RM		 1512/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1513static int b43_nphy_load_samples(struct b43_wldev *dev,
1514 struct b43_c32 *samples, u16 len) {
1515 struct b43_phy_n *nphy = dev->phy.n;
1516 u16 i;
1517 u32 *data;
1518
1519 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1520 if (!data) {
1521 b43err(dev->wl, "allocation for samples loading failed\n");
1522 return -ENOMEM;
1523 }
1524 if (nphy->hang_avoid)
1525 b43_nphy_stay_in_carrier_search(dev, 1);
1526
1527 for (i = 0; i < len; i++) {
1528 data[i] = (samples[i].i & 0x3FF << 10);
1529 data[i] |= samples[i].q & 0x3FF;
1530 }
1531 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1532
1533 kfree(data);
1534 if (nphy->hang_avoid)
1535 b43_nphy_stay_in_carrier_search(dev, 0);
1536 return 0;
026816fc
RM		 1537}
1538
8be89535
RM		 1539/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1540static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1541 bool test)
026816fc 1542{
8be89535
RM		 1543 int i;
1544 u16 bw, len, rot, angle;
1545 struct b43_c32 *samples;
026816fc 1546
bee6d4b2 1547 bw = b43_is_40mhz(dev) ? 40 : 20;
8be89535 1548 len = bw << 3;
026816fc 1549
8be89535
RM		 1550 if (test) {
1551 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1552 bw = 82;
1553 else
1554 bw = 80;
026816fc 1555
bee6d4b2 1556 if (b43_is_40mhz(dev))
8be89535
RM		 1557 bw <<= 1;
1558
1559 len = bw << 1;
026816fc
RM		 1560 }
1561
8be89535
RM		 1562 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1563 if (!samples) {
1564 b43err(dev->wl, "allocation for samples generation failed\n");
1565 return 0;
1566 }
1567 rot = (((freq * 36) / bw) << 16) / 100;
1568 angle = 0;
026816fc 1569
8be89535
RM		 1570 for (i = 0; i < len; i++) {
1571 samples[i] = b43_cordic(angle);
1572 angle += rot;
1573 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1574 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1575 }
8be89535
RM		 1576
1577 i = b43_nphy_load_samples(dev, samples, len);
1578 kfree(samples);
1579 return (i < 0) ? 0 : len;
026816fc
RM		 1580}
1581
8be89535
RM		 1582/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1583static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
ed03033e
RM		 1584 u16 wait, bool iqmode, bool dac_test,
1585 bool modify_bbmult)
34a56f2c 1586{
303415e2 1587 struct b43_phy *phy = &dev->phy;
8be89535 1588 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1589 int i;
8be89535
RM		 1590 u16 seq_mode;
1591 u32 tmp;
34a56f2c 1592
bc36e994 1593 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1594
303415e2 1595 if (phy->rev >= 7) {
40c68f20
RM		 1596 bool lpf_bw3, lpf_bw4;
1597
1598 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
1599 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
1600
1601 if (lpf_bw3 || lpf_bw4) {
1602 /* TODO */
1603 } else {
1604 u16 value = b43_nphy_read_lpf_ctl(dev, 0);
1605 if (phy->rev >= 19)
1606 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value,
1607 0, false, 1);
1608 else
1609 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value,
1610 0, false, 1);
1611 nphy->lpf_bw_overrode_for_sample_play = true;
1612 }
303415e2
RM		 1613 }
1614
8be89535
RM		 1615 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1616 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1617 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1618 }
34a56f2c 1619
ed03033e
RM		 1620 if (modify_bbmult) {
1621 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747;
1622 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1623 }
34a56f2c 1624
8be89535 1625 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1626
8be89535
RM		 1627 if (loops != 0xFFFF)
1628 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1629 else
1630 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1631
8be89535 1632 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1633
8be89535 1634 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1635
8be89535
RM		 1636 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1637 if (iqmode) {
1638 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1639 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1640 } else {
ed03033e
RM		 1641 tmp = dac_test ? 5 : 1;
1642 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp);
8be89535
RM		 1643 }
1644 for (i = 0; i < 100; i++) {
2c8ac7eb 1645 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1646 i = 0;
1647 break;
34a56f2c 1648 }
8be89535 1649 udelay(10);
34a56f2c 1650 }
8be89535
RM		 1651 if (i)
1652 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1653
8be89535 1654 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
bc36e994
RM		 1655
1656 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c
RM		 1657}
1658
4d9f46ba
RM		 1659/**************************************************
1660 * RSSI
1661 **************************************************/
1662
1663/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1664static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1665 s8 offset, u8 core,
1666 enum n_rail_type rail,
2a2d0589 1667 enum n_rssi_type rssi_type)
09146400 1668{
4d9f46ba
RM		 1669 u16 tmp;
1670 bool core1or5 = (core == 1) || (core == 5);
1671 bool core2or5 = (core == 2) || (core == 5);
09146400 1672
4d9f46ba
RM		 1673 offset = clamp_val(offset, -32, 31);
1674 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1675
e5ab1fd7 1676 switch (rssi_type) {
2a2d0589 1677 case N_RSSI_NB:
e5ab1fd7
RM		 1678 if (core1or5 && rail == N_RAIL_I)
1679 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1680 if (core1or5 && rail == N_RAIL_Q)
1681 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1682 if (core2or5 && rail == N_RAIL_I)
1683 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1684 if (core2or5 && rail == N_RAIL_Q)
1685 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1686 break;
2a2d0589 1687 case N_RSSI_W1:
e5ab1fd7
RM		 1688 if (core1or5 && rail == N_RAIL_I)
1689 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1690 if (core1or5 && rail == N_RAIL_Q)
1691 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1692 if (core2or5 && rail == N_RAIL_I)
1693 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1694 if (core2or5 && rail == N_RAIL_Q)
1695 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1696 break;
2a2d0589 1697 case N_RSSI_W2:
e5ab1fd7
RM		 1698 if (core1or5 && rail == N_RAIL_I)
1699 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1700 if (core1or5 && rail == N_RAIL_Q)
1701 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1702 if (core2or5 && rail == N_RAIL_I)
1703 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1704 if (core2or5 && rail == N_RAIL_Q)
1705 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1706 break;
2a2d0589 1707 case N_RSSI_TBD:
e5ab1fd7
RM		 1708 if (core1or5 && rail == N_RAIL_I)
1709 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1710 if (core1or5 && rail == N_RAIL_Q)
1711 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1712 if (core2or5 && rail == N_RAIL_I)
1713 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1714 if (core2or5 && rail == N_RAIL_Q)
1715 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1716 break;
2a2d0589 1717 case N_RSSI_IQ:
e5ab1fd7
RM		 1718 if (core1or5 && rail == N_RAIL_I)
1719 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1720 if (core1or5 && rail == N_RAIL_Q)
1721 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1722 if (core2or5 && rail == N_RAIL_I)
1723 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1724 if (core2or5 && rail == N_RAIL_Q)
1725 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1726 break;
2a2d0589 1727 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1728 if (core1or5)
1729 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1730 if (core2or5)
1731 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1732 break;
2a2d0589 1733 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1734 if (core1or5)
1735 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1736 if (core2or5)
1737 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1738 break;
1739 }
8987a9e9
RM		 1740}
1741
303415e2
RM		 1742static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code,
1743 enum n_rssi_type rssi_type)
1744{
1745 /* TODO */
1746}
1747
a3764ef7
RM		 1748static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1749 enum n_rssi_type rssi_type)
bbec398c 1750{
4d9f46ba
RM		 1751 u8 i;
1752 u16 reg, val;
bbec398c 1753
4d9f46ba
RM		 1754 if (code == 0) {
1755 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1756 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1757 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1758 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1759 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1760 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1761 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1762 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1763 } else {
1764 for (i = 0; i < 2; i++) {
1765 if ((code == 1 && i == 1) || (code == 2 && !i))
1766 continue;
bbec398c 1767
4d9f46ba
RM		 1768 reg = (i == 0) ?
1769 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1770 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1771
a3764ef7
RM		 1772 if (rssi_type == N_RSSI_W1 ||
1773 rssi_type == N_RSSI_W2 ||
1774 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1775 reg = (i == 0) ?
1776 B43_NPHY_AFECTL_C1 :
1777 B43_NPHY_AFECTL_C2;
1778 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1779
4d9f46ba
RM		 1780 reg = (i == 0) ?
1781 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1782 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1783 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1784
a3764ef7 1785 if (rssi_type == N_RSSI_W1)
4d9f46ba 1786 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1787 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1788 val = 16;
1789 else
1790 val = 32;
1791 b43_phy_set(dev, reg, val);
5c1a140a 1792
4d9f46ba
RM		 1793 reg = (i == 0) ?
1794 B43_NPHY_TXF_40CO_B1S0 :
1795 B43_NPHY_TXF_40CO_B32S1;
1796 b43_phy_set(dev, reg, 0x0020);
1797 } else {
a3764ef7 1798 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1799 val = 0x0100;
a3764ef7 1800 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1801 val = 0x0200;
1802 else
1803 val = 0x0300;
5c1a140a 1804
4d9f46ba
RM		 1805 reg = (i == 0) ?
1806 B43_NPHY_AFECTL_C1 :
1807 B43_NPHY_AFECTL_C2;
53ae8e8c 1808
4d9f46ba
RM		 1809 b43_phy_maskset(dev, reg, 0xFCFF, val);
1810 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1811
a3764ef7
RM		 1812 if (rssi_type != N_RSSI_IQ &&
1813 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1814 enum ieee80211_band band =
1815 b43_current_band(dev->wl);
53ae8e8c 1816
303415e2
RM		 1817 if (dev->phy.rev < 7) {
1818 if (b43_nphy_ipa(dev))
1819 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1820 else
1821 val = 0x11;
1822 reg = (i == 0) ? B2056_TX0 : B2056_TX1;
1823 reg |= B2056_TX_TX_SSI_MUX;
1824 b43_radio_write(dev, reg, val);
1825 }
53ae8e8c 1826
4d9f46ba
RM		 1827 reg = (i == 0) ?
1828 B43_NPHY_AFECTL_OVER1 :
1829 B43_NPHY_AFECTL_OVER;
1830 b43_phy_set(dev, reg, 0x0200);
1831 }
1832 }
1833 }
53ae8e8c 1834 }
53ae8e8c
RM		 1835}
1836
a3764ef7
RM		 1837static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1838 enum n_rssi_type rssi_type)
9442e5b5 1839{
4d9f46ba 1840 u16 val;
a3764ef7 1841 bool rssi_w1_w2_nb = false;
9442e5b5 1842
a3764ef7
RM		 1843 switch (rssi_type) {
1844 case N_RSSI_W1:
1845 case N_RSSI_W2:
1846 case N_RSSI_NB:
4d9f46ba 1847 val = 0;
a3764ef7
RM		 1848 rssi_w1_w2_nb = true;
1849 break;
1850 case N_RSSI_TBD:
4d9f46ba 1851 val = 1;
a3764ef7
RM		 1852 break;
1853 case N_RSSI_IQ:
4d9f46ba 1854 val = 2;
a3764ef7
RM		 1855 break;
1856 default:
4d9f46ba 1857 val = 3;
a3764ef7 1858 }
9442e5b5 1859
4d9f46ba
RM		 1860 val = (val << 12) | (val << 14);
1861 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1862 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1863
a3764ef7 1864 if (rssi_w1_w2_nb) {
4d9f46ba 1865 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1866 (rssi_type + 1) << 4);
4d9f46ba 1867 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1868 (rssi_type + 1) << 4);
9442e5b5
RM		 1869 }
1870
4d9f46ba
RM		 1871 if (code == 0) {
1872 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1873 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1874 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1875 ~(B43_NPHY_RFCTL_CMD_RXEN |
1876 B43_NPHY_RFCTL_CMD_CORESEL));
1877 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1878 ~(0x1 << 12 |
1879 0x1 << 5 |
1880 0x1 << 1 |
1881 0x1));
1882 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1883 ~B43_NPHY_RFCTL_CMD_START);
1884 udelay(20);
1885 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1886 }
1887 } else {
1888 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1889 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1890 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1891 ~(B43_NPHY_RFCTL_CMD_RXEN |
1892 B43_NPHY_RFCTL_CMD_CORESEL),
1893 (B43_NPHY_RFCTL_CMD_RXEN |
1894 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1895 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1896 (0x1 << 12 |
1897 0x1 << 5 |
1898 0x1 << 1 |
1899 0x1));
1900 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1901 B43_NPHY_RFCTL_CMD_START);
1902 udelay(20);
1903 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1904 }
9442e5b5 1905 }
9442e5b5
RM		 1906}
1907
4d9f46ba 1908/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1909static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1910 enum n_rssi_type type)
d24019ad 1911{
303415e2
RM		 1912 if (dev->phy.rev >= 19)
1913 b43_nphy_rssi_select_rev19(dev, code, type);
1914 else if (dev->phy.rev >= 3)
4d9f46ba
RM		 1915 b43_nphy_rev3_rssi_select(dev, code, type);
1916 else
1917 b43_nphy_rev2_rssi_select(dev, code, type);
1918}
d24019ad 1919
5ecab603 1920/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1921static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1922 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1923{
1924 int i;
d24019ad 1925 for (i = 0; i < 2; i++) {
a3764ef7 1926 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1927 if (i == 0) {
1928 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1929 0xFC, buf[0]);
1930 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1931 0xFC, buf[1]);
1932 } else {
1933 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1934 0xFC, buf[2 * i]);
1935 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1936 0xFC, buf[2 * i + 1]);
1937 }
d24019ad 1938 } else {
5ecab603
RM		 1939 if (i == 0)
1940 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1941 0xF3, buf[0] << 2);
1942 else
1943 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1944 0xF3, buf[2 * i + 1] << 2);
d24019ad 1945 }
d24019ad 1946 }
d24019ad
RM		 1947}
1948
5ecab603 1949/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1950static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1951 s32 *buf, u8 nsamp)
ef5127a4 1952{
5ecab603
RM		 1953 int i;
1954 int out;
1955 u16 save_regs_phy[9];
1956 u16 s[2];
ef5127a4 1957
303415e2
RM		 1958 /* TODO: rev7+ is treated like rev3+, what about rev19+? */
1959
ef5127a4 1960 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1961 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1962 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1963 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1964 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1965 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1966 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1967 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1968 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1969 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1970 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1971 save_regs_phy[8] = 0;
ef5127a4 1972 } else {
5ecab603
RM		 1973 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1974 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1975 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1976 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1977 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1978 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1979 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1980 save_regs_phy[7] = 0;
1981 save_regs_phy[8] = 0;
1982 }
ef5127a4 1983
a3764ef7 1984 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1985
5ecab603
RM		 1986 if (dev->phy.rev < 2) {
1987 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1988 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1989 }
ef5127a4 1990
5ecab603
RM		 1991 for (i = 0; i < 4; i++)
1992 buf[i] = 0;
1993
1994 for (i = 0; i < nsamp; i++) {
1995 if (dev->phy.rev < 2) {
1996 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1997 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1998 } else {
5ecab603
RM		 1999 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2000 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 2001 }
2002
5ecab603
RM		 2003 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2004 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2005 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2006 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2007 }
2008 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2009 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 2010
5ecab603
RM		 2011 if (dev->phy.rev < 2)
2012 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 2013
5ecab603 2014 if (dev->phy.rev >= 3) {
3084f3b6
RM		 2015 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2016 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 2017 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 2018 save_regs_phy[2]);
5ecab603 2019 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 2020 save_regs_phy[3]);
5ecab603
RM		 2021 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2022 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2023 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2024 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2025 } else {
2026 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2027 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2028 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2029 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2030 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2031 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2032 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2033 }
ef5127a4 2034
5ecab603
RM		 2035 return out;
2036}
ef5127a4 2037
e0c9a021
RM		 2038/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2039static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2040{
39e971ef 2041 struct b43_phy *phy = &dev->phy;
e0c9a021
RM		 2042 struct b43_phy_n *nphy = dev->phy.n;
2043
2044 u16 saved_regs_phy_rfctl[2];
97e2a1a1
RM		 2045 u16 saved_regs_phy[22];
2046 u16 regs_to_store_rev3[] = {
e0c9a021
RM		 2047 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
2048 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
2049 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
2050 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
2051 B43_NPHY_RFCTL_CMD,
2052 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2053 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
2054 };
97e2a1a1
RM		 2055 u16 regs_to_store_rev7[] = {
2056 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
2057 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
2058 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
40c68f20
RM		 2059 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
2060 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
97e2a1a1
RM		 2061 0x2ff,
2062 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
2063 B43_NPHY_RFCTL_CMD,
2064 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
40c68f20
RM		 2065 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
2066 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
97e2a1a1
RM		 2067 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
2068 };
2069 u16 *regs_to_store;
2070 int regs_amount;
e0c9a021
RM		 2071
2072 u16 class;
2073
2074 u16 clip_state[2];
2075 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2076
2077 u8 vcm_final = 0;
2e1253d6 2078 s32 offset[4];
e0c9a021
RM		 2079 s32 results[8][4] = { };
2080 s32 results_min[4] = { };
2081 s32 poll_results[4] = { };
2082
2083 u16 *rssical_radio_regs = NULL;
2084 u16 *rssical_phy_regs = NULL;
2085
2086 u16 r; /* routing */
2087 u8 rx_core_state;
37859a75 2088 int core, i, j, vcm;
e0c9a021 2089
97e2a1a1
RM		 2090 if (dev->phy.rev >= 7) {
2091 regs_to_store = regs_to_store_rev7;
2092 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
2093 } else {
2094 regs_to_store = regs_to_store_rev3;
2095 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
2096 }
2097 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
2098
e0c9a021
RM		 2099 class = b43_nphy_classifier(dev, 0, 0);
2100 b43_nphy_classifier(dev, 7, 4);
2101 b43_nphy_read_clip_detection(dev, clip_state);
2102 b43_nphy_write_clip_detection(dev, clip_off);
2103
2104 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2105 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
97e2a1a1 2106 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 2107 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
2108
89e43dad
RM		 2109 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
2110 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
97e2a1a1
RM		 2111
2112 if (dev->phy.rev >= 7) {
40c68f20
RM		 2113 b43_nphy_rf_ctl_override_one_to_many(dev,
2114 N_RF_CTL_OVER_CMD_RXRF_PU,
2115 0, 0, false);
2116 b43_nphy_rf_ctl_override_one_to_many(dev,
2117 N_RF_CTL_OVER_CMD_RX_PU,
2118 1, 0, false);
2119 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
2120 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
97e2a1a1 2121 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
40c68f20
RM		 2122 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false,
2123 0);
2124 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false,
2125 0);
97e2a1a1 2126 } else {
40c68f20
RM		 2127 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false,
2128 0);
2129 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false,
2130 0);
97e2a1a1 2131 }
e0c9a021 2132 } else {
97e2a1a1
RM		 2133 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
2134 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
2135 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
2136 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
2137 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2138 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
2139 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
2140 } else {
2141 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
2142 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
2143 }
e0c9a021
RM		 2144 }
2145
2146 rx_core_state = b43_nphy_get_rx_core_state(dev);
2147 for (core = 0; core < 2; core++) {
2148 if (!(rx_core_state & (1 << core)))
2149 continue;
2150 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 2151 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
2152 N_RSSI_NB);
2153 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
2154 N_RSSI_NB);
37859a75
RM		 2155
2156 /* Grab RSSI results for every possible VCM */
2157 for (vcm = 0; vcm < 8; vcm++) {
97e2a1a1 2158 if (dev->phy.rev >= 7)
40c68f20
RM		 2159 b43_radio_maskset(dev,
2160 core ? R2057_NB_MASTER_CORE1 :
2161 R2057_NB_MASTER_CORE0,
2162 ~R2057_VCM_MASK, vcm);
97e2a1a1
RM		 2163 else
2164 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
2165 0xE3, vcm << 2);
a3764ef7 2166 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 2167 }
37859a75
RM		 2168
2169 /* Find out which VCM got the best results */
cddec902 2170 for (i = 0; i < 4; i += 2) {
37859a75 2171 s32 currd;
e67dd874 2172 s32 mind = 0x100000;
e0c9a021
RM		 2173 s32 minpoll = 249;
2174 u8 minvcm = 0;
2175 if (2 * core != i)
2176 continue;
37859a75
RM		 2177 for (vcm = 0; vcm < 8; vcm++) {
2178 currd = results[vcm][i] * results[vcm][i] +
2179 results[vcm][i + 1] * results[vcm][i];
2180 if (currd < mind) {
2181 mind = currd;
2182 minvcm = vcm;
e0c9a021 2183 }
37859a75
RM		 2184 if (results[vcm][i] < minpoll)
2185 minpoll = results[vcm][i];
e0c9a021
RM		 2186 }
2187 vcm_final = minvcm;
2188 results_min[i] = minpoll;
2189 }
37859a75
RM		 2190
2191 /* Select the best VCM */
97e2a1a1 2192 if (dev->phy.rev >= 7)
40c68f20
RM		 2193 b43_radio_maskset(dev,
2194 core ? R2057_NB_MASTER_CORE1 :
2195 R2057_NB_MASTER_CORE0,
2196 ~R2057_VCM_MASK, vcm);
97e2a1a1
RM		 2197 else
2198 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
2199 0xE3, vcm_final << 2);
37859a75 2200
e0c9a021
RM		 2201 for (i = 0; i < 4; i++) {
2202 if (core != i / 2)
2203 continue;
2204 offset[i] = -results[vcm_final][i];
2205 if (offset[i] < 0)
2206 offset[i] = -((abs(offset[i]) + 4) / 8);
2207 else
2208 offset[i] = (offset[i] + 4) / 8;
2209 if (results_min[i] == 248)
2210 offset[i] = -32;
2211 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
2212 (i / 2 == 0) ? 1 : 2,
6aa38725 2213 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 2214 N_RSSI_NB);
e0c9a021
RM		 2215 }
2216 }
37859a75 2217
e0c9a021
RM		 2218 for (core = 0; core < 2; core++) {
2219 if (!(rx_core_state & (1 << core)))
2220 continue;
2221 for (i = 0; i < 2; i++) {
6aa38725
RM		 2222 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2223 N_RAIL_I, i);
2224 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2225 N_RAIL_Q, i);
e0c9a021
RM		 2226 b43_nphy_poll_rssi(dev, i, poll_results, 8);
2227 for (j = 0; j < 4; j++) {
cddec902 2228 if (j / 2 == core) {
e0c9a021 2229 offset[j] = 232 - poll_results[j];
cddec902
RM		 2230 if (offset[j] < 0)
2231 offset[j] = -(abs(offset[j] + 4) / 8);
2232 else
2233 offset[j] = (offset[j] + 4) / 8;
2234 b43_nphy_scale_offset_rssi(dev, 0,
2235 offset[2 * core], core + 1, j % 2, i);
2236 }
e0c9a021
RM		 2237 }
2238 }
2239 }
2240
2241 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
2242 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
2243
2244 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2245
2246 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
2247 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
2248 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
2249
2250 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2251 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
bc36e994 2252 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
e0c9a021 2253
97e2a1a1 2254 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 2255 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
2256
2257 /* Store for future configuration */
2258 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2259 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2260 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2261 } else {
2262 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2263 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2264 }
9a98979e 2265 if (dev->phy.rev >= 7) {
40c68f20
RM		 2266 rssical_radio_regs[0] = b43_radio_read(dev,
2267 R2057_NB_MASTER_CORE0);
2268 rssical_radio_regs[1] = b43_radio_read(dev,
2269 R2057_NB_MASTER_CORE1);
9a98979e
RM		 2270 } else {
2271 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
2272 B2056_RX_RSSI_MISC);
2273 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
2274 B2056_RX_RSSI_MISC);
2275 }
e0c9a021
RM		 2276 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
2277 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
2278 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
2279 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
2280 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
2281 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
2282 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
2283 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
2284 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
2285 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
2286 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
2287 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
2288
2289 /* Remember for which channel we store configuration */
2290 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
39e971ef 2291 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
e0c9a021 2292 else
39e971ef 2293 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
e0c9a021
RM		 2294
2295 /* End of calibration, restore configuration */
2296 b43_nphy_classifier(dev, 7, class);
2297 b43_nphy_write_clip_detection(dev, clip_state);
2298}
2299
5ecab603 2300/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 2301static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 2302{
37859a75 2303 int i, j, vcm;
5ecab603
RM		 2304 u8 state[4];
2305 u8 code, val;
2306 u16 class, override;
2307 u8 regs_save_radio[2];
2308 u16 regs_save_phy[2];
2309
2e1253d6 2310 s32 offset[4];
5ecab603
RM		 2311 u8 core;
2312 u8 rail;
2313
2314 u16 clip_state[2];
2315 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2316 s32 results_min[4] = { };
2317 u8 vcm_final[4] = { };
2318 s32 results[4][4] = { };
2319 s32 miniq[4][2] = { };
2320
a3764ef7 2321 if (type == N_RSSI_NB) {
5ecab603
RM		 2322 code = 0;
2323 val = 6;
a3764ef7 2324 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 2325 code = 25;
2326 val = 4;
2327 } else {
2328 B43_WARN_ON(1);
2329 return;
2330 }
2331
2332 class = b43_nphy_classifier(dev, 0, 0);
2333 b43_nphy_classifier(dev, 7, 4);
2334 b43_nphy_read_clip_detection(dev, clip_state);
2335 b43_nphy_write_clip_detection(dev, clip_off);
2336
2337 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2338 override = 0x140;
2339 else
2340 override = 0x110;
2341
2342 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 2343 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 2344 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 2345 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 2346
2347 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 2348 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 2349 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 2350 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 2351
0c201cfb
RM		 2352 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2353 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 2354 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2355 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 2356 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
2357 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 2358
2359 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 2360 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
2361 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 2362
37859a75 2363 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 2364 u8 tmp[4];
2365 for (j = 0; j < 4; j++)
37859a75 2366 tmp[j] = vcm;
a3764ef7 2367 if (type != N_RSSI_W2)
5ecab603 2368 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 2369 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 2370 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 2371 for (j = 0; j < 2; j++)
37859a75
RM		 2372 miniq[vcm][j] = min(results[vcm][2 * j],
2373 results[vcm][2 * j + 1]);
5ecab603
RM		 2374 }
2375
2376 for (i = 0; i < 4; i++) {
e67dd874 2377 s32 mind = 0x100000;
5ecab603
RM		 2378 u8 minvcm = 0;
2379 s32 minpoll = 249;
37859a75
RM		 2380 s32 currd;
2381 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 2382 if (type == N_RSSI_NB)
542e15f3 2383 currd = abs(results[vcm][i] - code * 8);
5ecab603 2384 else
37859a75 2385 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 2386
37859a75
RM		 2387 if (currd < mind) {
2388 mind = currd;
2389 minvcm = vcm;
5ecab603
RM		 2390 }
2391
37859a75
RM		 2392 if (results[vcm][i] < minpoll)
2393 minpoll = results[vcm][i];
8e60b044 2394 }
5ecab603
RM		 2395 results_min[i] = minpoll;
2396 vcm_final[i] = minvcm;
2397 }
ef5127a4 2398
a3764ef7 2399 if (type != N_RSSI_W2)
5ecab603 2400 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 2401
5ecab603
RM		 2402 for (i = 0; i < 4; i++) {
2403 offset[i] = (code * 8) - results[vcm_final[i]][i];
2404
2405 if (offset[i] < 0)
2406 offset[i] = -((abs(offset[i]) + 4) / 8);
2407 else
2408 offset[i] = (offset[i] + 4) / 8;
2409
2410 if (results_min[i] == 248)
2411 offset[i] = code - 32;
2412
2413 core = (i / 2) ? 2 : 1;
6aa38725 2414 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 2415
2416 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2417 type);
2418 }
2419
2420 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2421 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2422
2423 switch (state[2]) {
2424 case 1:
a3764ef7 2425 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 2426 break;
2427 case 4:
a3764ef7 2428 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 2429 break;
2430 case 2:
a3764ef7 2431 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2432 break;
2433 default:
a3764ef7 2434 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2435 break;
2436 }
2437
2438 switch (state[3]) {
2439 case 1:
a3764ef7 2440 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 2441 break;
2442 case 4:
a3764ef7 2443 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 2444 break;
2445 default:
a3764ef7 2446 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 2447 break;
2448 }
2449
2450 b43_nphy_rssi_select(dev, 0, type);
2451
2452 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 2453 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 2454 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 2455 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 2456
2457 b43_nphy_classifier(dev, 7, class);
2458 b43_nphy_write_clip_detection(dev, clip_state);
2459 /* Specs don't say about reset here, but it makes wl and b43 dumps
2460 identical, it really seems wl performs this */
2461 b43_nphy_reset_cca(dev);
2462}
2463
5ecab603
RM		 2464/*
2465 * RSSI Calibration
2466 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2467 */
2468static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2469{
303415e2
RM		 2470 if (dev->phy.rev >= 19) {
2471 /* TODO */
2472 } else if (dev->phy.rev >= 3) {
5ecab603
RM		 2473 b43_nphy_rev3_rssi_cal(dev);
2474 } else {
2a2d0589
RM		 2475 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2476 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2477 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 2478 }
2479}
2480
64712095
RM		 2481/**************************************************
2482 * Workarounds
2483 **************************************************/
2484
303415e2
RM		 2485static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev)
2486{
2487 /* TODO */
2488}
2489
2490static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev)
2491{
2492 struct b43_phy *phy = &dev->phy;
2493
2494 switch (phy->rev) {
2495 /* TODO */
2496 }
2497}
2498
2499static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev)
64712095
RM		 2500{
2501 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2502
2503 bool ghz5;
2504 bool ext_lna;
2505 u16 rssi_gain;
2506 struct nphy_gain_ctl_workaround_entry *e;
2507 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2508 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2509
2510 /* Prepare values */
2511 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2512 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 2513 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2514 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 2515 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2516 if (ghz5 && dev->phy.rev >= 5)
2517 rssi_gain = 0x90;
2518 else
2519 rssi_gain = 0x50;
2520
2521 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2522
2523 /* Set Clip 2 detect */
04519dc6
RM		 2524 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2525 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 2526
2527 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2528 0x17);
2529 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2530 0x17);
2531 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2532 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2533 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2534 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2535 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2536 rssi_gain);
2537 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2538 rssi_gain);
2539 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2540 0x17);
2541 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2542 0x17);
2543 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2544 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2545
2546 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2547 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2548 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2549 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2550 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2551 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2552 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2553 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2554 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2555 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2556 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2557 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2558
04519dc6
RM		 2559 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2560 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2561
64712095
RM		 2562 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2563 e->rfseq_init);
64712095 2564
04519dc6
RM		 2565 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2566 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2567 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2568 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2569 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2570 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2571
2572 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2573 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2574 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2575 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2576 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2577 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2578 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2579 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2580 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2581 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2582}
2583
2584static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2585{
2586 struct b43_phy_n *nphy = dev->phy.n;
2587
2588 u8 i, j;
2589 u8 code;
2590 u16 tmp;
2591 u8 rfseq_events[3] = { 6, 8, 7 };
2592 u8 rfseq_delays[3] = { 10, 30, 1 };
2593
2594 /* Set Clip 2 detect */
2595 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2596 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2597
2598 /* Set narrowband clip threshold */
2599 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2600 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2601
bee6d4b2 2602 if (!b43_is_40mhz(dev)) {
64712095
RM		 2603 /* Set dwell lengths */
2604 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2605 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2606 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2607 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2608 }
2609
2610 /* Set wideband clip 2 threshold */
2611 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2612 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2613 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2614 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2615
bee6d4b2 2616 if (!b43_is_40mhz(dev)) {
64712095
RM		 2617 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2618 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2619 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2620 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2621 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2622 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2623 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2624 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2625 }
2626
2627 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2628
2629 if (nphy->gain_boost) {
2630 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
bee6d4b2 2631 b43_is_40mhz(dev))
64712095
RM		 2632 code = 4;
2633 else
2634 code = 5;
2635 } else {
bee6d4b2 2636 code = b43_is_40mhz(dev) ? 6 : 7;
64712095
RM		 2637 }
2638
2639 /* Set HPVGA2 index */
2640 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2641 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2642 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2643 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2644
2645 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2646 /* specs say about 2 loops, but wl does 4 */
2647 for (i = 0; i < 4; i++)
2648 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2649
2650 b43_nphy_adjust_lna_gain_table(dev);
2651
2652 if (nphy->elna_gain_config) {
2653 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2654 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2655 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2656 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2657 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2658
2659 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2660 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2661 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2662 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2663 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2664
2665 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2666 /* specs say about 2 loops, but wl does 4 */
2667 for (i = 0; i < 4; i++)
2668 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2669 (code << 8 | 0x74));
2670 }
2671
2672 if (dev->phy.rev == 2) {
2673 for (i = 0; i < 4; i++) {
2674 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2675 (0x0400 * i) + 0x0020);
2676 for (j = 0; j < 21; j++) {
2677 tmp = j * (i < 2 ? 3 : 1);
2678 b43_phy_write(dev,
2679 B43_NPHY_TABLE_DATALO, tmp);
2680 }
2681 }
ef5127a4 2682 }
64712095
RM		 2683
2684 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2685 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2686 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2687 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2688
2689 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2690 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2691}
2692
2693/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2694static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2695{
303415e2
RM		 2696 if (dev->phy.rev >= 19)
2697 b43_nphy_gain_ctl_workarounds_rev19(dev);
2698 else if (dev->phy.rev >= 7)
2699 b43_nphy_gain_ctl_workarounds_rev7(dev);
d11d354b 2700 else if (dev->phy.rev >= 3)
303415e2 2701 b43_nphy_gain_ctl_workarounds_rev3(dev);
64712095
RM		 2702 else
2703 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2704}
2705
d11d354b
RM		 2706static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2707{
2708 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2709 struct b43_phy *phy = &dev->phy;
2710
2711 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2712 0x1F };
2713 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2714
2715 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2716 u8 ntab7_138_146[] = { 0x11, 0x11 };
2717 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2718
2719 u16 lpf_20, lpf_40, lpf_11b;
2720 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2721 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2722 bool rccal_ovrd = false;
2723
2724 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2725 u16 bias, conv, filt;
2726
2727 u32 tmp32;
2728 u8 core;
2729
2730 if (phy->rev == 7) {
2731 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2732 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2733 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2734 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2735 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2736 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2737 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2738 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2739 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2740 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2741 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2742 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2743 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2744 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2745 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2746 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2747 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2748 }
2749 if (phy->rev <= 8) {
04519dc6
RM		 2750 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2751 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2752 }
2753 if (phy->rev >= 8)
2754 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2755
2756 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2757 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2758 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2759 tmp32 &= 0xffffff;
2760 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2761 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2762 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2763
2764 if (b43_nphy_ipa(dev))
2765 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2766 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2767
04519dc6
RM		 2768 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2769 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2770
2771 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2772 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2773 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2774 if (b43_nphy_ipa(dev)) {
bee6d4b2 2775 if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
d11d354b
RM		 2776 phy->radio_rev == 7 || phy->radio_rev == 8) {
2777 bcap_val = b43_radio_read(dev, 0x16b);
2778 scap_val = b43_radio_read(dev, 0x16a);
2779 scap_val_11b = scap_val;
2780 bcap_val_11b = bcap_val;
bee6d4b2 2781 if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
d11d354b
RM		 2782 scap_val_11n_20 = scap_val;
2783 bcap_val_11n_20 = bcap_val;
2784 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2785 rccal_ovrd = true;
2786 } else { /* Rev 7/8 */
2787 lpf_20 = 4;
2788 lpf_11b = 1;
2789 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2790 scap_val_11n_20 = 0xc;
2791 bcap_val_11n_20 = 0xc;
2792 scap_val_11n_40 = 0xa;
2793 bcap_val_11n_40 = 0xa;
2794 } else {
2795 scap_val_11n_20 = 0x14;
2796 bcap_val_11n_20 = 0x14;
2797 scap_val_11n_40 = 0xf;
2798 bcap_val_11n_40 = 0xf;
2799 }
2800 rccal_ovrd = true;
2801 }
2802 }
2803 } else {
2804 if (phy->radio_rev == 5) {
2805 lpf_20 = 1;
2806 lpf_40 = 3;
2807 bcap_val = b43_radio_read(dev, 0x16b);
2808 scap_val = b43_radio_read(dev, 0x16a);
2809 scap_val_11b = scap_val;
2810 bcap_val_11b = bcap_val;
2811 scap_val_11n_20 = 0x11;
2812 scap_val_11n_40 = 0x11;
2813 bcap_val_11n_20 = 0x13;
2814 bcap_val_11n_40 = 0x13;
2815 rccal_ovrd = true;
2816 }
2817 }
2818 if (rccal_ovrd) {
2819 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2820 (scap_val_11b << 3) |
2821 lpf_11b;
2822 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2823 (scap_val_11n_20 << 3) |
2824 lpf_20;
2825 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2826 (scap_val_11n_40 << 3) |
2827 lpf_40;
2828 for (core = 0; core < 2; core++) {
2829 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2830 rx2tx_lut_20_11b);
2831 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2832 rx2tx_lut_20_11n);
2833 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2834 rx2tx_lut_20_11n);
2835 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2836 rx2tx_lut_40_11n);
2837 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2838 rx2tx_lut_40_11n);
2839 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2840 rx2tx_lut_40_11n);
2841 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2842 rx2tx_lut_40_11n);
2843 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2844 rx2tx_lut_40_11n);
2845 }
78ae7532 2846 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2847 }
2848 b43_phy_write(dev, 0x32F, 0x3);
2849 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2850 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2851
2852 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2853 if (sprom->revision &&
2854 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2855 b43_radio_write(dev, 0x5, 0x05);
2856 b43_radio_write(dev, 0x6, 0x30);
2857 b43_radio_write(dev, 0x7, 0x00);
2858 b43_radio_set(dev, 0x4f, 0x1);
2859 b43_radio_set(dev, 0xd4, 0x1);
2860 bias = 0x1f;
2861 conv = 0x6f;
2862 filt = 0xaa;
2863 } else {
2864 bias = 0x2b;
2865 conv = 0x7f;
2866 filt = 0xee;
2867 }
2868 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2869 for (core = 0; core < 2; core++) {
2870 if (core == 0) {
2871 b43_radio_write(dev, 0x5F, bias);
2872 b43_radio_write(dev, 0x64, conv);
2873 b43_radio_write(dev, 0x66, filt);
2874 } else {
2875 b43_radio_write(dev, 0xE8, bias);
2876 b43_radio_write(dev, 0xE9, conv);
2877 b43_radio_write(dev, 0xEB, filt);
2878 }
2879 }
2880 }
2881 }
2882
2883 if (b43_nphy_ipa(dev)) {
2884 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2885 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2886 phy->radio_rev == 6) {
2887 for (core = 0; core < 2; core++) {
2888 if (core == 0)
2889 b43_radio_write(dev, 0x51,
2890 0x7f);
2891 else
2892 b43_radio_write(dev, 0xd6,
2893 0x7f);
2894 }
2895 }
2896 if (phy->radio_rev == 3) {
2897 for (core = 0; core < 2; core++) {
2898 if (core == 0) {
2899 b43_radio_write(dev, 0x64,
2900 0x13);
2901 b43_radio_write(dev, 0x5F,
2902 0x1F);
2903 b43_radio_write(dev, 0x66,
2904 0xEE);
2905 b43_radio_write(dev, 0x59,
2906 0x8A);
2907 b43_radio_write(dev, 0x80,
2908 0x3E);
2909 } else {
2910 b43_radio_write(dev, 0x69,
2911 0x13);
2912 b43_radio_write(dev, 0xE8,
2913 0x1F);
2914 b43_radio_write(dev, 0xEB,
2915 0xEE);
2916 b43_radio_write(dev, 0xDE,
2917 0x8A);
2918 b43_radio_write(dev, 0x105,
2919 0x3E);
2920 }
2921 }
2922 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
bee6d4b2 2923 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2924 b43_radio_write(dev, 0x5F, 0x14);
2925 b43_radio_write(dev, 0xE8, 0x12);
2926 } else {
2927 b43_radio_write(dev, 0x5F, 0x16);
2928 b43_radio_write(dev, 0xE8, 0x16);
2929 }
2930 }
2931 } else {
39e971ef 2932 u16 freq = phy->chandef->chan->center_freq;
d11d354b
RM		 2933 if ((freq >= 5180 && freq <= 5230) ||
2934 (freq >= 5745 && freq <= 5805)) {
2935 b43_radio_write(dev, 0x7D, 0xFF);
2936 b43_radio_write(dev, 0xFE, 0xFF);
2937 }
2938 }
2939 } else {
2940 if (phy->radio_rev != 5) {
2941 for (core = 0; core < 2; core++) {
2942 if (core == 0) {
2943 b43_radio_write(dev, 0x5c, 0x61);
2944 b43_radio_write(dev, 0x51, 0x70);
2945 } else {
2946 b43_radio_write(dev, 0xe1, 0x61);
2947 b43_radio_write(dev, 0xd6, 0x70);
2948 }
2949 }
2950 }
2951 }
2952
2953 if (phy->radio_rev == 4) {
2954 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2955 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2956 for (core = 0; core < 2; core++) {
2957 if (core == 0) {
2958 b43_radio_write(dev, 0x1a1, 0x00);
2959 b43_radio_write(dev, 0x1a2, 0x3f);
2960 b43_radio_write(dev, 0x1a6, 0x3f);
2961 } else {
2962 b43_radio_write(dev, 0x1a7, 0x00);
2963 b43_radio_write(dev, 0x1ab, 0x3f);
2964 b43_radio_write(dev, 0x1ac, 0x3f);
2965 }
2966 }
2967 } else {
2968 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2969 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2970 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2971 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2972
2973 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2974 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2975 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2976 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2977 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2978 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2979
2980 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2981 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2982 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2983 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2984 }
2985
2986 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2987
2988 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2989 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2990 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2991 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2992 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2993 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2994 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2995
bee6d4b2 2996 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2997 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2998 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2999 } else {
3000 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
3001 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
3002 }
3003
3004 b43_nphy_gain_ctl_workarounds(dev);
3005
3006 /* TODO
3007 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
3008 aux_adc_vmid_rev7_core0);
3009 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
3010 aux_adc_vmid_rev7_core1);
3011 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
3012 aux_adc_gain_rev7);
3013 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
3014 aux_adc_gain_rev7);
3015 */
3016}
3017
73d07a39 3018static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 3019{
0eff8fcd 3020 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3021 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 3022
0eff8fcd 3023 /* TX to RX */
c378bb97
RM		 3024 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
3025 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 3026 /* RX to TX */
3027 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
3028 0x1F };
3029 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
3030 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
3031 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
3032
c378bb97
RM		 3033 u16 vmids[5][4] = {
3034 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
3035 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
3036 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
3037 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
3038 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
3039 };
3040 u16 gains[5][4] = {
3041 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
3042 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
3043 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
3044 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
3045 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
3046 };
3047 u16 *vmid, *gain;
3048
3049 u8 pdet_range;
ba9a6214
RM		 3050 u16 tmp16;
3051 u32 tmp32;
3052
04519dc6
RM		 3053 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
3054 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 3055
73d07a39
RM		 3056 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
3057 tmp32 &= 0xffffff;
3058 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 3059
73d07a39
RM		 3060 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
3061 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
3062 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
3063 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
3064 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
3065 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 3066
04519dc6
RM		 3067 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
3068 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 3069
0eff8fcd 3070 /* TX to RX */
c56da252
RM		 3071 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
3072 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 3073
3074 /* RX to TX */
3075 if (b43_nphy_ipa(dev))
c56da252
RM		 3076 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
3077 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 3078 if (nphy->hw_phyrxchain != 3 &&
3079 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
3080 if (b43_nphy_ipa(dev)) {
3081 rx2tx_delays[5] = 59;
3082 rx2tx_delays[6] = 1;
3083 rx2tx_events[7] = 0x1F;
3084 }
fa0f2b38 3085 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 3086 ARRAY_SIZE(rx2tx_events));
0eff8fcd 3087 }
ba9a6214 3088
73d07a39
RM		 3089 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
3090 0x2 : 0x9C40;
3091 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 3092
04519dc6 3093 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 3094
bee6d4b2 3095 if (!b43_is_40mhz(dev)) {
fa0f2b38
RM		 3096 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
3097 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
3098 } else {
3099 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
3100 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
3101 }
ba9a6214 3102
3ccd0957 3103 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 3104
c56da252
RM		 3105 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
3106 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 3107
c378bb97
RM		 3108 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3109 pdet_range = sprom->fem.ghz2.pdet_range;
3110 else
3111 pdet_range = sprom->fem.ghz5.pdet_range;
3112 vmid = vmids[min_t(u16, pdet_range, 4)];
3113 gain = gains[min_t(u16, pdet_range, 4)];
3114 switch (pdet_range) {
3115 case 3:
3116 if (!(dev->phy.rev >= 4 &&
3117 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
3118 break;
3119 /* FALL THROUGH */
3120 case 0:
3121 case 1:
3122 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3123 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3124 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3125 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3126 break;
3127 case 2:
3128 if (dev->phy.rev >= 6) {
3129 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3130 vmid[3] = 0x94;
3131 else
3132 vmid[3] = 0x8e;
3133 gain[3] = 3;
3134 } else if (dev->phy.rev == 5) {
3135 vmid[3] = 0x84;
3136 gain[3] = 2;
3137 }
3138 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3139 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3140 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3141 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3142 break;
3143 case 4:
3144 case 5:
3145 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
3146 if (pdet_range == 4) {
3147 vmid[3] = 0x8e;
3148 tmp16 = 0x96;
3149 gain[3] = 0x2;
3150 } else {
3151 vmid[3] = 0x89;
3152 tmp16 = 0x89;
3153 gain[3] = 0;
3154 }
3155 } else {
3156 if (pdet_range == 4) {
3157 vmid[3] = 0x89;
3158 tmp16 = 0x8b;
3159 gain[3] = 0x2;
3160 } else {
3161 vmid[3] = 0x74;
3162 tmp16 = 0x70;
3163 gain[3] = 0;
3164 }
3165 }
3166 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3167 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3168 vmid[3] = tmp16;
3169 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3170 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3171 break;
3172 }
ba9a6214 3173
73d07a39
RM		 3174 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3175 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3176 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3177 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3178 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3179 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3180 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3181 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 3182 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3183 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 3184 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3185 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3186
3187 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
3188
3189 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
3190 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
3191 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
3192 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
3193 tmp32 = 0x00088888;
3194 else
3195 tmp32 = 0x88888888;
3196 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
3197 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
3198 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
3199
3200 if (dev->phy.rev == 4 &&
fa0f2b38 3201 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 3202 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
3203 0x70);
3204 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
3205 0x70);
3206 }
ba9a6214 3207
fa0f2b38 3208 /* Dropped probably-always-true condition */
04519dc6
RM		 3209 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
3210 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
bc36e994 3211 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
04519dc6
RM		 3212 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
3213 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
3214 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
3215 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
3216 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
3217 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
3218 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
3219 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
3220 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 3221
3222 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
3223 ; /* TODO: 0x0080000000000000 HF */
73d07a39 3224}
ba9a6214 3225
73d07a39
RM		 3226static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
3227{
3228 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3229 struct b43_phy *phy = &dev->phy;
3230 struct b43_phy_n *nphy = phy->n;
ba9a6214 3231
73d07a39
RM		 3232 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
3233 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 3234
73d07a39
RM		 3235 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
3236 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 3237
fa0f2b38 3238 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 3239 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 3240 delays1[0] = 0x1;
3241 delays1[5] = 0x14;
3242 }
3243
73d07a39
RM		 3244 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
3245 nphy->band5g_pwrgain) {
3246 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
3247 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 3248 } else {
73d07a39
RM		 3249 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
3250 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
3251 }
28fd7daa 3252
73d07a39
RM		 3253 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
3254 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 3255 if (dev->phy.rev < 3) {
3256 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
3257 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
3258 }
73d07a39
RM		 3259
3260 if (dev->phy.rev < 2) {
3261 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
3262 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
3263 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
3264 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
3265 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
3266 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
3267 }
28fd7daa 3268
73d07a39
RM		 3269 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3270 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3271 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 3273
73d07a39
RM		 3274 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
3275 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
3276
3ccd0957 3277 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 3278
3279 if (dev->phy.rev < 2) {
3280 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
3281 b43_hf_write(dev, b43_hf_read(dev) |
3282 B43_HF_MLADVW);
3283 } else if (dev->phy.rev == 2) {
3284 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
3285 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
3286 }
28fd7daa 3287
73d07a39
RM		 3288 if (dev->phy.rev < 2)
3289 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
3290 ~B43_NPHY_SCRAM_SIGCTL_SCM);
3291
3292 /* Set phase track alpha and beta */
3293 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
3294 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
3295 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
3296 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
3297 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
3298 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
3299
fa0f2b38
RM		 3300 if (dev->phy.rev < 3) {
3301 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
3302 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
3303 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
3304 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
3305 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
3306 }
73d07a39
RM		 3307
3308 if (dev->phy.rev == 2)
3309 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
3310 B43_NPHY_FINERX2_CGC_DECGC);
3311}
28fd7daa 3312
73d07a39
RM		 3313/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
3314static void b43_nphy_workarounds(struct b43_wldev *dev)
3315{
3316 struct b43_phy *phy = &dev->phy;
3317 struct b43_phy_n *nphy = phy->n;
28fd7daa 3318
73d07a39
RM		 3319 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3320 b43_nphy_classifier(dev, 1, 0);
3321 else
3322 b43_nphy_classifier(dev, 1, 1);
28fd7daa 3323
73d07a39
RM		 3324 if (nphy->hang_avoid)
3325 b43_nphy_stay_in_carrier_search(dev, 1);
3326
3327 b43_phy_set(dev, B43_NPHY_IQFLIP,
3328 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
3329
303415e2 3330 /* TODO: rev19+ */
d11d354b
RM		 3331 if (dev->phy.rev >= 7)
3332 b43_nphy_workarounds_rev7plus(dev);
3333 else if (dev->phy.rev >= 3)
73d07a39
RM		 3334 b43_nphy_workarounds_rev3plus(dev);
3335 else
3336 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 3337
3338 if (nphy->hang_avoid)
3339 b43_nphy_stay_in_carrier_search(dev, 0);
3340}
3341
9dd4d9b9
RM		 3342/**************************************************
3343 * Tx/Rx common
3344 **************************************************/
3345
3346/*
3347 * Transmits a known value for LO calibration
3348 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
3349 */
3350static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
ed03033e 3351 bool iqmode, bool dac_test, bool modify_bbmult)
9dd4d9b9
RM		 3352{
3353 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
3354 if (samp == 0)
3355 return -1;
ed03033e
RM		 3356 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test,
3357 modify_bbmult);
9dd4d9b9
RM		 3358 return 0;
3359}
3360
3361/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
3362static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
3363{
3364 struct b43_phy_n *nphy = dev->phy.n;
3365
3366 bool override = false;
3367 u16 chain = 0x33;
3368
3369 if (nphy->txrx_chain == 0) {
3370 chain = 0x11;
3371 override = true;
3372 } else if (nphy->txrx_chain == 1) {
3373 chain = 0x22;
3374 override = true;
3375 }
3376
3377 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3378 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
3379 chain);
3380
3381 if (override)
3382 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
3383 B43_NPHY_RFSEQMODE_CAOVER);
3384 else
3385 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3386 ~B43_NPHY_RFSEQMODE_CAOVER);
3387}
3388
3389/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
3390static void b43_nphy_stop_playback(struct b43_wldev *dev)
3391{
40c68f20 3392 struct b43_phy *phy = &dev->phy;
9dd4d9b9
RM		 3393 struct b43_phy_n *nphy = dev->phy.n;
3394 u16 tmp;
3395
3396 if (nphy->hang_avoid)
3397 b43_nphy_stay_in_carrier_search(dev, 1);
3398
3399 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
3400 if (tmp & 0x1)
3401 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
3402 else if (tmp & 0x2)
3403 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3404
3405 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3406
3407 if (nphy->bb_mult_save & 0x80000000) {
3408 tmp = nphy->bb_mult_save & 0xFFFF;
3409 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3410 nphy->bb_mult_save = 0;
3411 }
3412
40c68f20
RM		 3413 if (phy->rev >= 7) {
3414 if (phy->rev >= 19)
3415 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true,
3416 1);
3417 else
3418 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1);
3419 nphy->lpf_bw_overrode_for_sample_play = false;
303415e2
RM		 3420 }
3421
9dd4d9b9
RM		 3422 if (nphy->hang_avoid)
3423 b43_nphy_stay_in_carrier_search(dev, 0);
3424}
3425
3426/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3427static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3428 struct nphy_txgains target,
3429 struct nphy_iqcal_params *params)
3430{
303415e2 3431 struct b43_phy *phy = &dev->phy;
9dd4d9b9
RM		 3432 int i, j, indx;
3433 u16 gain;
3434
3435 if (dev->phy.rev >= 3) {
40c68f20 3436 params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */
9dd4d9b9
RM		 3437 params->txgm = target.txgm[core];
3438 params->pga = target.pga[core];
3439 params->pad = target.pad[core];
3440 params->ipa = target.ipa[core];
303415e2
RM		 3441 if (phy->rev >= 19) {
3442 /* TODO */
3443 } else if (phy->rev >= 7) {
40c68f20 3444 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15);
303415e2
RM		 3445 } else {
3446 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa);
3447 }
9dd4d9b9
RM		 3448 for (j = 0; j < 5; j++)
3449 params->ncorr[j] = 0x79;
3450 } else {
3451 gain = (target.pad[core]) | (target.pga[core] << 4) |
3452 (target.txgm[core] << 8);
3453
3454 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3455 1 : 0;
3456 for (i = 0; i < 9; i++)
3457 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3458 break;
3459 i = min(i, 8);
3460
3461 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3462 params->pga = tbl_iqcal_gainparams[indx][i][2];
3463 params->pad = tbl_iqcal_gainparams[indx][i][3];
3464 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3465 (params->pad << 2);
3466 for (j = 0; j < 4; j++)
3467 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3468 }
3469}
3470
884a5228 3471/**************************************************
104cfa88 3472 * Tx and Rx
884a5228 3473 **************************************************/
5f6393ec 3474
884a5228
RM		 3475static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3476{//TODO
3477}
59af099b 3478
884a5228
RM		 3479static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3480 bool ignore_tssi)
3481{//TODO
3482 return B43_TXPWR_RES_DONE;
3483}
59af099b 3484
161d540c
RM		 3485/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3486static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3487{
303415e2 3488 struct b43_phy *phy = &dev->phy;
161d540c
RM		 3489 struct b43_phy_n *nphy = dev->phy.n;
3490 u8 i;
c9c0d9ec
RM		 3491 u16 bmask, val, tmp;
3492 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 3493
161d540c
RM		 3494 if (nphy->hang_avoid)
3495 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 3496
161d540c
RM		 3497 nphy->txpwrctrl = enable;
3498 if (!enable) {
c9c0d9ec
RM		 3499 if (dev->phy.rev >= 3 &&
3500 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3501 (B43_NPHY_TXPCTL_CMD_COEFF |
3502 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3503 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3504 /* We disable enabled TX pwr ctl, save it's state */
3505 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3506 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3507 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3508 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3509 }
59af099b 3510
161d540c
RM		 3511 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3512 for (i = 0; i < 84; i++)
3513 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3514
161d540c
RM		 3515 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3516 for (i = 0; i < 84; i++)
3517 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3518
161d540c
RM		 3519 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3520 if (dev->phy.rev >= 3)
3521 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3522 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 3523
161d540c
RM		 3524 if (dev->phy.rev >= 3) {
3525 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3526 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3527 } else {
3528 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3529 }
10a79873 3530
161d540c
RM		 3531 if (dev->phy.rev == 2)
3532 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3533 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3534 else if (dev->phy.rev < 2)
3535 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3536 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 3537
bee6d4b2 3538 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3539 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 3540 } else {
c9c0d9ec
RM		 3541 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3542 nphy->adj_pwr_tbl);
3543 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3544 nphy->adj_pwr_tbl);
10a79873 3545
c9c0d9ec
RM		 3546 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3547 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3548 /* wl does useless check for "enable" param here */
3549 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3550 if (dev->phy.rev >= 3) {
3551 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3552 if (val)
3553 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3554 }
3555 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3556
c9c0d9ec 3557 if (band == IEEE80211_BAND_5GHZ) {
303415e2
RM		 3558 if (phy->rev >= 19) {
3559 /* TODO */
3560 } else if (phy->rev >= 7) {
40c68f20
RM		 3561 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3562 ~B43_NPHY_TXPCTL_CMD_INIT,
3563 0x32);
3564 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3565 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3566 0x32);
303415e2
RM		 3567 } else {
3568 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3569 ~B43_NPHY_TXPCTL_CMD_INIT,
c9c0d9ec 3570 0x64);
303415e2
RM		 3571 if (phy->rev > 1)
3572 b43_phy_maskset(dev,
3573 B43_NPHY_TXPCTL_INIT,
3574 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3575 0x64);
3576 }
c9c0d9ec 3577 }
10a79873 3578
c9c0d9ec
RM		 3579 if (dev->phy.rev >= 3) {
3580 if (nphy->tx_pwr_idx[0] != 128 &&
3581 nphy->tx_pwr_idx[1] != 128) {
3582 /* Recover TX pwr ctl state */
3583 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3584 ~B43_NPHY_TXPCTL_CMD_INIT,
3585 nphy->tx_pwr_idx[0]);
3586 if (dev->phy.rev > 1)
3587 b43_phy_maskset(dev,
3588 B43_NPHY_TXPCTL_INIT,
3589 ~0xff, nphy->tx_pwr_idx[1]);
3590 }
3591 }
10a79873 3592
303415e2
RM		 3593 if (phy->rev >= 7) {
3594 /* TODO */
3595 }
3596
c9c0d9ec
RM		 3597 if (dev->phy.rev >= 3) {
3598 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3599 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3600 } else {
3601 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3602 }
10a79873 3603
c9c0d9ec
RM		 3604 if (dev->phy.rev == 2)
3605 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3606 else if (dev->phy.rev < 2)
3607 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3608
bee6d4b2 3609 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3610 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3611
c002831a 3612 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3613 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3614 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3615 }
10a79873 3616 }
10a79873 3617
161d540c
RM		 3618 if (nphy->hang_avoid)
3619 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3620}
3621
161d540c 3622/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3623static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91 3624{
39e971ef 3625 struct b43_phy *phy = &dev->phy;
6dcd9d91 3626 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3627 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3628
161d540c
RM		 3629 u8 txpi[2], bbmult, i;
3630 u16 tmp, radio_gain, dac_gain;
39e971ef 3631 u16 freq = phy->chandef->chan->center_freq;
161d540c
RM		 3632 u32 txgain;
3633 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3634
3635 if (nphy->hang_avoid)
161d540c 3636 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3637
303415e2 3638 /* TODO: rev19+ */
dd5f13b8
RM		 3639 if (dev->phy.rev >= 7) {
3640 txpi[0] = txpi[1] = 30;
3641 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3642 txpi[0] = 40;
3643 txpi[1] = 40;
3644 } else if (sprom->revision < 4) {
3645 txpi[0] = 72;
3646 txpi[1] = 72;
3647 } else {
3648 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3649 txpi[0] = sprom->txpid2g[0];
3650 txpi[1] = sprom->txpid2g[1];
3651 } else if (freq >= 4900 && freq < 5100) {
3652 txpi[0] = sprom->txpid5gl[0];
3653 txpi[1] = sprom->txpid5gl[1];
3654 } else if (freq >= 5100 && freq < 5500) {
3655 txpi[0] = sprom->txpid5g[0];
3656 txpi[1] = sprom->txpid5g[1];
3657 } else if (freq >= 5500) {
3658 txpi[0] = sprom->txpid5gh[0];
3659 txpi[1] = sprom->txpid5gh[1];
3660 } else {
3661 txpi[0] = 91;
3662 txpi[1] = 91;
6dcd9d91
RM		 3663 }
3664 }
dd5f13b8 3665 if (dev->phy.rev < 7 &&
9bd28571 3666 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3667 txpi[0] = txpi[1] = 91;
6dcd9d91 3668
161d540c
RM		 3669 /*
3670 for (i = 0; i < 2; i++) {
3671 nphy->txpwrindex[i].index_internal = txpi[i];
3672 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3673 }
161d540c 3674 */
75377b24 3675
161d540c 3676 for (i = 0; i < 2; i++) {
7ef5cd24
RM		 3677 const u32 *table = b43_nphy_get_tx_gain_table(dev);
3678
3679 if (!table)
3680 break;
3681 txgain = *(table + txpi[i]);
aeab5751
RM		 3682
3683 if (dev->phy.rev >= 3)
161d540c 3684 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3685 else
161d540c 3686 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3687
dd5f13b8
RM		 3688 if (dev->phy.rev >= 7)
3689 dac_gain = (txgain >> 8) & 0x7;
3690 else
3691 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3692 bbmult = txgain & 0xFF;
75377b24 3693
161d540c
RM		 3694 if (dev->phy.rev >= 3) {
3695 if (i == 0)
3696 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3697 else
3698 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3699 } else {
3700 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3701 }
75377b24 3702
161d540c
RM		 3703 if (i == 0)
3704 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3705 else
3706 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3707
44f4008b 3708 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3709
44f4008b 3710 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3711 if (i == 0)
3712 tmp = (tmp & 0x00FF) | (bbmult << 8);
3713 else
3714 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3715 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3716
0eff8fcd
RM		 3717 if (b43_nphy_ipa(dev)) {
3718 u32 tmp32;
3719 u16 reg = (i == 0) ?
3720 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3721 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3722 576 + txpi[i]));
0eff8fcd
RM		 3723 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3724 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3725 }
3726 }
75377b24 3727
161d540c 3728 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3729
161d540c
RM		 3730 if (nphy->hang_avoid)
3731 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3732}
67cbc3ed 3733
3dda07b6
RM		 3734static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3735{
3736 struct b43_phy *phy = &dev->phy;
3737
3738 u8 core;
3739 u16 r; /* routing */
3740
303415e2
RM		 3741 if (phy->rev >= 19) {
3742 /* TODO */
3743 } else if (phy->rev >= 7) {
3dda07b6
RM		 3744 for (core = 0; core < 2; core++) {
3745 r = core ? 0x190 : 0x170;
3746 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3747 b43_radio_write(dev, r + 0x5, 0x5);
3748 b43_radio_write(dev, r + 0x9, 0xE);
3749 if (phy->rev != 5)
3750 b43_radio_write(dev, r + 0xA, 0);
3751 if (phy->rev != 7)
3752 b43_radio_write(dev, r + 0xB, 1);
3753 else
3754 b43_radio_write(dev, r + 0xB, 0x31);
3755 } else {
3756 b43_radio_write(dev, r + 0x5, 0x9);
3757 b43_radio_write(dev, r + 0x9, 0xC);
3758 b43_radio_write(dev, r + 0xB, 0x0);
3759 if (phy->rev != 5)
3760 b43_radio_write(dev, r + 0xA, 1);
3761 else
3762 b43_radio_write(dev, r + 0xA, 0x31);
3763 }
3764 b43_radio_write(dev, r + 0x6, 0);
3765 b43_radio_write(dev, r + 0x7, 0);
3766 b43_radio_write(dev, r + 0x8, 3);
3767 b43_radio_write(dev, r + 0xC, 0);
3768 }
3769 } else {
3770 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3771 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3772 else
3773 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3774 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3775 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3776
3777 for (core = 0; core < 2; core++) {
3778 r = core ? B2056_TX1 : B2056_TX0;
3779
3780 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3781 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3782 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3783 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3784 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3785 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3786 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3787 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3788 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3789 0x5);
3790 if (phy->rev != 5)
3791 b43_radio_write(dev, r | B2056_TX_TSSIA,
3792 0x00);
3793 if (phy->rev >= 5)
3794 b43_radio_write(dev, r | B2056_TX_TSSIG,
3795 0x31);
3796 else
3797 b43_radio_write(dev, r | B2056_TX_TSSIG,
3798 0x11);
3799 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3800 0xE);
3801 } else {
3802 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3803 0x9);
3804 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3805 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3806 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3807 0xC);
3808 }
3809 }
3810 }
3811}
3812
3813/*
3814 * Stop radio and transmit known signal. Then check received signal strength to
3815 * get TSSI (Transmit Signal Strength Indicator).
3816 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3817 */
3818static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3819{
3820 struct b43_phy *phy = &dev->phy;
3821 struct b43_phy_n *nphy = dev->phy.n;
3822
3823 u32 tmp;
3824 s32 rssi[4] = { };
3825
3826 /* TODO: check if we can transmit */
3827
3828 if (b43_nphy_ipa(dev))
3829 b43_nphy_ipa_internal_tssi_setup(dev);
3830
303415e2
RM		 3831 if (phy->rev >= 19)
3832 b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, false, 0);
3833 else if (phy->rev >= 7)
78ae7532 3834 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3835 else if (phy->rev >= 3)
78ae7532 3836 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3837
3838 b43_nphy_stop_playback(dev);
ed03033e 3839 b43_nphy_tx_tone(dev, 4000, 0, false, false, false);
3dda07b6 3840 udelay(20);
a3764ef7 3841 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3842 b43_nphy_stop_playback(dev);
303415e2 3843
a3764ef7 3844 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6 3845
303415e2
RM		 3846 if (phy->rev >= 19)
3847 b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, true, 0);
3848 else if (phy->rev >= 7)
78ae7532 3849 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3850 else if (phy->rev >= 3)
78ae7532 3851 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6 3852
303415e2
RM		 3853 if (phy->rev >= 19) {
3854 /* TODO */
3855 return;
3856 } else if (phy->rev >= 3) {
3dda07b6
RM		 3857 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3858 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3859 } else {
3860 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3861 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3862 }
3863 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3864 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3865}
3866
d3fd8bf7
RM		 3867/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3868static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3869{
3870 struct b43_phy_n *nphy = dev->phy.n;
3871
3872 u8 idx, delta;
3873 u8 i, stf_mode;
3874
55757927
RM		 3875 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3876 * 21 groups, each containing 4 entries.
3877 *
3878 * First group has entries for CCK modulation.
3879 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3880 *
3881 * Group 0 is for CCK
3882 * Groups 1..4 use BPSK (group per coding rate)
3883 * Groups 5..8 use QPSK (group per coding rate)
3884 * Groups 9..12 use 16-QAM (group per coding rate)
3885 * Groups 13..16 use 64-QAM (group per coding rate)
3886 * Groups 17..20 are unknown
3887 */
3888
d3fd8bf7
RM		 3889 for (i = 0; i < 4; i++)
3890 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3891
3892 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3893 delta = 0;
3894 switch (stf_mode) {
3895 case 0:
bee6d4b2 3896 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
d3fd8bf7
RM		 3897 idx = 68;
3898 } else {
3899 delta = 1;
bee6d4b2 3900 idx = b43_is_40mhz(dev) ? 52 : 4;
d3fd8bf7
RM		 3901 }
3902 break;
3903 case 1:
bee6d4b2 3904 idx = b43_is_40mhz(dev) ? 76 : 28;
d3fd8bf7
RM		 3905 break;
3906 case 2:
bee6d4b2 3907 idx = b43_is_40mhz(dev) ? 84 : 36;
d3fd8bf7
RM		 3908 break;
3909 case 3:
bee6d4b2 3910 idx = b43_is_40mhz(dev) ? 92 : 44;
d3fd8bf7
RM		 3911 break;
3912 }
3913
3914 for (i = 0; i < 20; i++) {
3915 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3916 nphy->tx_power_offset[idx];
3917 if (i == 0)
3918 idx += delta;
3919 if (i == 14)
3920 idx += 1 - delta;
3921 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3922 i == 13)
3923 idx += 1;
3924 }
3925 }
3926}
3927
3928/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3929static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3930{
39e971ef 3931 struct b43_phy *phy = &dev->phy;
d3fd8bf7
RM		 3932 struct b43_phy_n *nphy = dev->phy.n;
3933 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3934
3935 s16 a1[2], b0[2], b1[2];
3936 u8 idle[2];
3937 s8 target[2];
3938 s32 num, den, pwr;
3939 u32 regval[64];
3940
39e971ef 3941 u16 freq = phy->chandef->chan->center_freq;
d3fd8bf7
RM		 3942 u16 tmp;
3943 u16 r; /* routing */
3944 u8 i, c;
3945
3946 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3947 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3948 b43_read32(dev, B43_MMIO_MACCTL);
3949 udelay(1);
3950 }
3951
3952 if (nphy->hang_avoid)
3953 b43_nphy_stay_in_carrier_search(dev, true);
3954
3955 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3956 if (dev->phy.rev >= 3)
3957 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3958 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3959 else
3960 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3961 B43_NPHY_TXPCTL_CMD_PCTLEN);
3962
3963 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3964 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3965
3966 if (sprom->revision < 4) {
3967 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3968 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3969 target[0] = target[1] = 52;
3970 a1[0] = a1[1] = -424;
3971 b0[0] = b0[1] = 5612;
3972 b1[0] = b1[1] = -1393;
3973 } else {
3974 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3975 for (c = 0; c < 2; c++) {
3976 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3977 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3978 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3979 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3980 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3981 }
3982 } else if (freq >= 4900 && freq < 5100) {
3983 for (c = 0; c < 2; c++) {
3984 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3985 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3986 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3987 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3988 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3989 }
3990 } else if (freq >= 5100 && freq < 5500) {
3991 for (c = 0; c < 2; c++) {
3992 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3993 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3994 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3995 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3996 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3997 }
3998 } else if (freq >= 5500) {
3999 for (c = 0; c < 2; c++) {
4000 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
4001 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
4002 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
4003 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
4004 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
4005 }
4006 } else {
4007 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
4008 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
4009 target[0] = target[1] = 52;
4010 a1[0] = a1[1] = -424;
4011 b0[0] = b0[1] = 5612;
4012 b1[0] = b1[1] = -1393;
4013 }
4014 }
4015 /* target[0] = target[1] = nphy->tx_power_max; */
4016
4017 if (dev->phy.rev >= 3) {
4018 if (sprom->fem.ghz2.tssipos)
4019 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
4020 if (dev->phy.rev >= 7) {
4021 for (c = 0; c < 2; c++) {
4022 r = c ? 0x190 : 0x170;
4023 if (b43_nphy_ipa(dev))
4024 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
4025 }
4026 } else {
4027 if (b43_nphy_ipa(dev)) {
4028 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
4029 b43_radio_write(dev,
4030 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
4031 b43_radio_write(dev,
4032 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
4033 } else {
4034 b43_radio_write(dev,
4035 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
4036 b43_radio_write(dev,
4037 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
4038 }
4039 }
4040 }
4041
4042 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
4043 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
4044 b43_read32(dev, B43_MMIO_MACCTL);
4045 udelay(1);
4046 }
4047
303415e2
RM		 4048 if (phy->rev >= 19) {
4049 /* TODO */
4050 } else if (phy->rev >= 7) {
d3fd8bf7
RM		 4051 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
4052 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
4053 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
4054 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
4055 } else {
4056 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
4057 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
4058 if (dev->phy.rev > 1)
4059 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
4060 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
4061 }
4062
4063 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
4064 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
4065
4066 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
4067 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
4068 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
4069 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
4070 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
4071 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
4072 B43_NPHY_TXPCTL_ITSSI_BINF);
4073 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
4074 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
4075 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
4076
4077 for (c = 0; c < 2; c++) {
4078 for (i = 0; i < 64; i++) {
4079 num = 8 * (16 * b0[c] + b1[c] * i);
4080 den = 32768 + a1[c] * i;
4081 pwr = max((4 * num + den / 2) / den, -8);
4082 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
4083 pwr = max(pwr, target[c] + 1);
4084 regval[i] = pwr;
4085 }
4086 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
4087 }
4088
4089 b43_nphy_tx_prepare_adjusted_power_table(dev);
d3fd8bf7
RM		 4090 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
4091 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
d3fd8bf7
RM		 4092
4093 if (nphy->hang_avoid)
4094 b43_nphy_stay_in_carrier_search(dev, false);
4095}
4096
0eff8fcd
RM		 4097static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
4098{
4099 struct b43_phy *phy = &dev->phy;
67cbc3ed 4100
0eff8fcd 4101 const u32 *table = NULL;
0eff8fcd
RM		 4102 u32 rfpwr_offset;
4103 u8 pga_gain;
4104 int i;
0eff8fcd 4105
aeab5751 4106 table = b43_nphy_get_tx_gain_table(dev);
7ef5cd24
RM		 4107 if (!table)
4108 return;
4109
0eff8fcd
RM		 4110 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
4111 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
4112
303415e2
RM		 4113 if (phy->rev < 3)
4114 return;
4115
0eff8fcd 4116#if 0
303415e2 4117 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 4118#endif
0eff8fcd 4119
303415e2
RM		 4120 for (i = 0; i < 128; i++) {
4121 if (phy->rev >= 19) {
4122 /* TODO */
4123 return;
4124 } else if (phy->rev >= 7) {
4125 /* TODO */
4126 return;
4127 } else {
0eff8fcd
RM		 4128 pga_gain = (table[i] >> 24) & 0xF;
4129 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
303415e2 4130 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 4131 else
303415e2 4132 rfpwr_offset = 0; /* FIXME */
0eff8fcd 4133 }
303415e2
RM		 4134
4135 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset);
4136 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset);
67cbc3ed
RM		 4137 }
4138}
4139
e50cbcf6
RM		 4140/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
4141static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 4142{
e50cbcf6
RM		 4143 struct b43_phy_n *nphy = dev->phy.n;
4144 enum ieee80211_band band;
4145 u16 tmp;
95b66bad 4146
e50cbcf6
RM		 4147 if (!enable) {
4148 nphy->rfctrl_intc1_save = b43_phy_read(dev,
4149 B43_NPHY_RFCTL_INTC1);
4150 nphy->rfctrl_intc2_save = b43_phy_read(dev,
4151 B43_NPHY_RFCTL_INTC2);
4152 band = b43_current_band(dev->wl);
303415e2 4153 if (dev->phy.rev >= 7) {
40c68f20 4154 tmp = 0x1480;
303415e2 4155 } else if (dev->phy.rev >= 3) {
e50cbcf6
RM		 4156 if (band == IEEE80211_BAND_5GHZ)
4157 tmp = 0x600;
4158 else
4159 tmp = 0x480;
4160 } else {
4161 if (band == IEEE80211_BAND_5GHZ)
4162 tmp = 0x180;
4163 else
4164 tmp = 0x120;
4165 }
4166 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4167 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4168 } else {
4169 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
4170 nphy->rfctrl_intc1_save);
4171 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
4172 nphy->rfctrl_intc2_save);
95b66bad 4173 }
95b66bad
MB		 4174}
4175
8ac3a2aa
RM		 4176/*
4177 * TX low-pass filter bandwidth setup
4178 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw
4179 */
4180static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev)
3c95627d
RM		 4181{
4182 u16 tmp;
3c95627d 4183
8ac3a2aa
RM		 4184 if (dev->phy.rev < 3 || dev->phy.rev >= 7)
4185 return;
76b002bd 4186
8ac3a2aa
RM		 4187 if (b43_nphy_ipa(dev))
4188 tmp = b43_is_40mhz(dev) ? 5 : 4;
4189 else
4190 tmp = b43_is_40mhz(dev) ? 3 : 1;
4191 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
4192 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
4193
4194 if (b43_nphy_ipa(dev)) {
4195 tmp = b43_is_40mhz(dev) ? 4 : 1;
fe3e46e8 4196 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
8ac3a2aa 4197 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
fe3e46e8
RM		 4198 }
4199}
76b002bd 4200
2faa6b83
RM		 4201/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
4202static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
4203 u16 samps, u8 time, bool wait)
3c95627d 4204{
2faa6b83
RM		 4205 int i;
4206 u16 tmp;
3c95627d 4207
2faa6b83
RM		 4208 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
4209 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
4210 if (wait)
4211 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 4212 else
2faa6b83 4213 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 4214
2faa6b83 4215 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 4216
2faa6b83
RM		 4217 for (i = 1000; i; i--) {
4218 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
4219 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
4220 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
4221 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
4222 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
4223 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
4224 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
4225 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 4226
2faa6b83
RM		 4227 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
4228 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
4229 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
4230 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
4231 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
4232 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
4233 return;
3c95627d 4234 }
2faa6b83 4235 udelay(10);
3c95627d 4236 }
2faa6b83 4237 memset(est, 0, sizeof(*est));
3c95627d
RM		 4238}
4239
a67162ab
RM		 4240/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
4241static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
4242 struct b43_phy_n_iq_comp *pcomp)
99b82c41 4243{
a67162ab
RM		 4244 if (write) {
4245 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
4246 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
4247 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
4248 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 4249 } else {
a67162ab
RM		 4250 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
4251 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
4252 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
4253 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
4254 }
4255}
6e3b15a9 4256
c7455cf9
RM		 4257#if 0
4258/* Ready but not used anywhere */
026816fc
RM		 4259/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
4260static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
4261{
4262 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 4263
026816fc
RM		 4264 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4265 if (core == 0) {
4266 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
4267 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4268 } else {
4269 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4270 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4271 }
4272 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
4273 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
4274 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
4275 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
4276 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
4277 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
4278 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4279 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4280}
6e3b15a9 4281
026816fc
RM		 4282/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
4283static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
4284{
4285 u8 rxval, txval;
4286 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 4287
026816fc
RM		 4288 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4289 if (core == 0) {
4290 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4291 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4292 } else {
4293 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4294 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4295 }
4296 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4297 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4298 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
4299 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
4300 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
4301 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
4302 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4303 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 4304
026816fc
RM		 4305 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4306 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 4307
acd82aa8
LF		 4308 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4309 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 4310 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4311 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4312 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
4313 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4314 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
4315 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
4316 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 4317
026816fc
RM		 4318 if (core == 0) {
4319 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4320 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4321 } else {
4322 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4323 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4324 }
6e3b15a9 4325
89e43dad 4326 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 4327 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 4328 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 4329
026816fc
RM		 4330 if (core == 0) {
4331 rxval = 1;
4332 txval = 8;
4333 } else {
4334 rxval = 4;
4335 txval = 2;
6e3b15a9 4336 }
89e43dad
RM		 4337 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4338 core + 1);
4339 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4340 2 - core);
99b82c41 4341}
c7455cf9 4342#endif
99b82c41 4343
34a56f2c
RM		 4344/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
4345static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 4346{
4347 int i;
34a56f2c
RM		 4348 s32 iq;
4349 u32 ii;
4350 u32 qq;
4351 int iq_nbits, qq_nbits;
4352 int arsh, brsh;
4353 u16 tmp, a, b;
4354
4355 struct nphy_iq_est est;
4356 struct b43_phy_n_iq_comp old;
4357 struct b43_phy_n_iq_comp new = { };
4358 bool error = false;
4359
4360 if (mask == 0)
4361 return;
4362
4363 b43_nphy_rx_iq_coeffs(dev, false, &old);
4364 b43_nphy_rx_iq_coeffs(dev, true, &new);
4365 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
4366 new = old;
4367
dfb4aa5d 4368 for (i = 0; i < 2; i++) {
34a56f2c
RM		 4369 if (i == 0 && (mask & 1)) {
4370 iq = est.iq0_prod;
4371 ii = est.i0_pwr;
4372 qq = est.q0_pwr;
4373 } else if (i == 1 && (mask & 2)) {
4374 iq = est.iq1_prod;
4375 ii = est.i1_pwr;
4376 qq = est.q1_pwr;
dfb4aa5d 4377 } else {
34a56f2c 4378 continue;
dfb4aa5d 4379 }
dfb4aa5d 4380
34a56f2c
RM		 4381 if (ii + qq < 2) {
4382 error = true;
4383 break;
4384 }
dfb4aa5d 4385
34a56f2c
RM		 4386 iq_nbits = fls(abs(iq));
4387 qq_nbits = fls(qq);
dfb4aa5d 4388
34a56f2c
RM		 4389 arsh = iq_nbits - 20;
4390 if (arsh >= 0) {
4391 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
4392 tmp = ii >> arsh;
4393 } else {
4394 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
4395 tmp = ii << -arsh;
4396 }
4397 if (tmp == 0) {
4398 error = true;
4399 break;
4400 }
4401 a /= tmp;
dfb4aa5d 4402
34a56f2c
RM		 4403 brsh = qq_nbits - 11;
4404 if (brsh >= 0) {
4405 b = (qq << (31 - qq_nbits));
4406 tmp = ii >> brsh;
dfb4aa5d 4407 } else {
34a56f2c
RM		 4408 b = (qq << (31 - qq_nbits));
4409 tmp = ii << -brsh;
4410 }
4411 if (tmp == 0) {
4412 error = true;
4413 break;
dfb4aa5d 4414 }
34a56f2c 4415 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 4416
34a56f2c
RM		 4417 if (i == 0 && (mask & 0x1)) {
4418 if (dev->phy.rev >= 3) {
4419 new.a0 = a & 0x3FF;
4420 new.b0 = b & 0x3FF;
4421 } else {
4422 new.a0 = b & 0x3FF;
4423 new.b0 = a & 0x3FF;
4424 }
4425 } else if (i == 1 && (mask & 0x2)) {
4426 if (dev->phy.rev >= 3) {
4427 new.a1 = a & 0x3FF;
4428 new.b1 = b & 0x3FF;
4429 } else {
4430 new.a1 = b & 0x3FF;
4431 new.b1 = a & 0x3FF;
4432 }
4433 }
dfb4aa5d 4434 }
dfb4aa5d 4435
34a56f2c
RM		 4436 if (error)
4437 new = old;
dfb4aa5d 4438
34a56f2c
RM		 4439 b43_nphy_rx_iq_coeffs(dev, true, &new);
4440}
dfb4aa5d 4441
09146400
RM		 4442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
4443static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
4444{
4445 u16 array[4];
44f4008b 4446 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 4447
4448 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
4449 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
4450 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
4451 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 4452}
4453
9442e5b5
RM		 4454/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
4455static void b43_nphy_spur_workaround(struct b43_wldev *dev)
4456{
4457 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 4458
204a665b 4459 u8 channel = dev->phy.channel;
9442e5b5
RM		 4460 int tone[2] = { 57, 58 };
4461 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 4462
9442e5b5 4463 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 4464
9442e5b5
RM		 4465 if (nphy->hang_avoid)
4466 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 4467
9442e5b5
RM		 4468 if (nphy->gband_spurwar_en) {
4469 /* TODO: N PHY Adjust Analog Pfbw (7) */
bee6d4b2 4470 if (channel == 11 && b43_is_40mhz(dev))
9442e5b5
RM		 4471 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4472 else
4473 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4474 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 4475 }
4476
9442e5b5
RM		 4477 if (nphy->aband_spurwar_en) {
4478 if (channel == 54) {
4479 tone[0] = 0x20;
4480 noise[0] = 0x25F;
4481 } else if (channel == 38 || channel == 102 || channel == 118) {
4482 if (0 /* FIXME */) {
4483 tone[0] = 0x20;
4484 noise[0] = 0x21F;
4485 } else {
4486 tone[0] = 0;
4487 noise[0] = 0;
90b9738d 4488 }
9442e5b5
RM		 4489 } else if (channel == 134) {
4490 tone[0] = 0x20;
4491 noise[0] = 0x21F;
4492 } else if (channel == 151) {
4493 tone[0] = 0x10;
4494 noise[0] = 0x23F;
4495 } else if (channel == 153 || channel == 161) {
4496 tone[0] = 0x30;
4497 noise[0] = 0x23F;
4498 } else {
4499 tone[0] = 0;
4500 noise[0] = 0;
90b9738d 4501 }
90b9738d 4502
9442e5b5
RM		 4503 if (!tone[0] && !noise[0])
4504 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 4505 else
9442e5b5
RM		 4506 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4507 }
90b9738d 4508
9442e5b5
RM		 4509 if (nphy->hang_avoid)
4510 b43_nphy_stay_in_carrier_search(dev, 0);
4511}
90b9738d 4512
5ecab603
RM		 4513/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4514static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4515{
4516 struct b43_phy_n *nphy = dev->phy.n;
4517 int i, j;
4518 u32 tmp;
4519 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 4520
5ecab603 4521 u16 buffer[7];
90b9738d 4522
5ecab603
RM		 4523 if (nphy->hang_avoid)
4524 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 4525
5ecab603 4526 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 4527
5ecab603
RM		 4528 for (i = 0; i < 2; i++) {
4529 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4530 (buffer[i * 2 + 1] & 0x3FF);
4531 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4532 (((i + 26) << 10) | 320));
4533 for (j = 0; j < 128; j++) {
4534 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4535 ((tmp >> 16) & 0xFFFF));
4536 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4537 (tmp & 0xFFFF));
90b9738d 4538 }
90b9738d 4539 }
90b9738d 4540
5ecab603
RM		 4541 for (i = 0; i < 2; i++) {
4542 tmp = buffer[5 + i];
4543 real_part = (tmp >> 8) & 0xFF;
4544 imag_part = (tmp & 0xFF);
4545 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4546 (((i + 26) << 10) | 448));
90b9738d 4547
5ecab603
RM		 4548 if (dev->phy.rev >= 3) {
4549 cur_real = real_part;
4550 cur_imag = imag_part;
4551 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4552 }
4cb99775 4553
5ecab603
RM		 4554 for (j = 0; j < 128; j++) {
4555 if (dev->phy.rev < 3) {
4556 cur_real = (real_part * loscale[j] + 128) >> 8;
4557 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4558 tmp = ((cur_real & 0xFF) << 8) |
4559 (cur_imag & 0xFF);
4560 }
4561 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4562 ((tmp >> 16) & 0xFFFF));
4563 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4564 (tmp & 0xFFFF));
4565 }
90b9738d 4566 }
4cb99775 4567
4cb99775 4568 if (dev->phy.rev >= 3) {
5ecab603
RM		 4569 b43_shm_write16(dev, B43_SHM_SHARED,
4570 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4571 b43_shm_write16(dev, B43_SHM_SHARED,
4572 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 4573 }
90b9738d 4574
5ecab603
RM		 4575 if (nphy->hang_avoid)
4576 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 4577}
4578
42e1547e
RM		 4579/*
4580 * Restore RSSI Calibration
4581 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4582 */
4583static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4584{
4585 struct b43_phy_n *nphy = dev->phy.n;
4586
4587 u16 *rssical_radio_regs = NULL;
4588 u16 *rssical_phy_regs = NULL;
4589
4590 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4591 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 4592 return;
4593 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4594 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4595 } else {
204a665b 4596 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 4597 return;
4598 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4599 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4600 }
4601
303415e2
RM		 4602 if (dev->phy.rev >= 19) {
4603 /* TODO */
4604 } else if (dev->phy.rev >= 7) {
40c68f20
RM		 4605 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK,
4606 rssical_radio_regs[0]);
4607 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK,
4608 rssical_radio_regs[1]);
9a98979e
RM		 4609 } else {
4610 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4611 rssical_radio_regs[0]);
4612 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4613 rssical_radio_regs[1]);
4614 }
42e1547e
RM		 4615
4616 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4617 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4618 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4619 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4620
4621 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4622 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4623 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4624 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4625
4626 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4627 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4628 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4629 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4630}
4631
303415e2
RM		 4632static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev)
4633{
4634 /* TODO */
4635}
4636
4637static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev)
4638{
40c68f20
RM		 4639 struct b43_phy *phy = &dev->phy;
4640 struct b43_phy_n *nphy = dev->phy.n;
4641 u16 *save = nphy->tx_rx_cal_radio_saveregs;
4642 int core, off;
4643 u16 r, tmp;
4644
4645 for (core = 0; core < 2; core++) {
4646 r = core ? 0x20 : 0;
4647 off = core * 11;
4648
4649 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER);
4650 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG);
4651 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC);
4652 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM);
4653 save[off + 4] = 0;
4654 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX);
4655 if (phy->radio_rev != 5)
4656 save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA);
4657 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG);
4658 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1);
4659
4660 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4661 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA);
4662 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4663 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
4664 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);
4665 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0);
4666 if (nphy->use_int_tx_iq_lo_cal) {
4667 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4);
4668 tmp = true ? 0x31 : 0x21; /* TODO */
4669 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp);
4670 }
4671 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00);
4672 } else {
4673 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6);
4674 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4675 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
4676 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);
4677
4678 if (phy->radio_rev != 5)
4679 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0);
4680 if (nphy->use_int_tx_iq_lo_cal) {
4681 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6);
4682 tmp = true ? 0x31 : 0x21; /* TODO */
4683 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp);
4684 }
4685 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0);
4686 }
4687 }
303415e2
RM		 4688}
4689
c4a92003
RM		 4690/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4691static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4692{
303415e2 4693 struct b43_phy *phy = &dev->phy;
c4a92003
RM		 4694 struct b43_phy_n *nphy = dev->phy.n;
4695 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4696 u16 tmp;
4697 u8 offset, i;
c4a92003 4698
303415e2
RM		 4699 if (phy->rev >= 19) {
4700 b43_nphy_tx_cal_radio_setup_rev19(dev);
4701 } else if (phy->rev >= 7) {
4702 b43_nphy_tx_cal_radio_setup_rev7(dev);
4703 } else if (phy->rev >= 3) {
52cb5e97
RM		 4704 for (i = 0; i < 2; i++) {
4705 tmp = (i == 0) ? 0x2000 : 0x3000;
4706 offset = i * 11;
4707
0c201cfb
RM		 4708 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4709 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4710 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4711 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4712 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4713 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4714 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4715 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4716 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4717 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4718 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4719
4720 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4721 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4722 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4723 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4724 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4725 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4726 if (nphy->ipa5g_on) {
0c201cfb
RM		 4727 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4728 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4729 } else {
0c201cfb
RM		 4730 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4731 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4732 }
0c201cfb 4733 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4734 } else {
0c201cfb
RM		 4735 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4736 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4737 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4738 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4739 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4740 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4741 if (nphy->ipa2g_on) {
0c201cfb
RM		 4742 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4743 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4744 (dev->phy.rev < 5) ? 0x11 : 0x01);
4745 } else {
0c201cfb
RM		 4746 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4747 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4748 }
4749 }
0c201cfb
RM		 4750 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4751 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4752 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4753 }
c4a92003 4754 } else {
0c201cfb
RM		 4755 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4756 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4757
0c201cfb
RM		 4758 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4759 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4760
0c201cfb
RM		 4761 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4762 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4763
0c201cfb
RM		 4764 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4765 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4766
0c201cfb
RM		 4767 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4768 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4769
4770 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4771 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4772 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4773 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4774 } else {
0c201cfb
RM		 4775 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4776 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4777 }
4778
4779 if (dev->phy.rev < 2) {
4780 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4781 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4782 } else {
4783 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4784 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4785 }
4786 }
4787}
4788
de7ed0c6
RM		 4789/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4790static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4791{
4792 struct b43_phy_n *nphy = dev->phy.n;
4793 int i;
4794 u16 scale, entry;
4795
4796 u16 tmp = nphy->txcal_bbmult;
4797 if (core == 0)
4798 tmp >>= 8;
4799 tmp &= 0xff;
4800
4801 for (i = 0; i < 18; i++) {
4802 scale = (ladder_lo[i].percent * tmp) / 100;
4803 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4804 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4805
4806 scale = (ladder_iq[i].percent * tmp) / 100;
4807 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4808 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4809 }
4810}
4811
45ca697e
RM		 4812/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4813static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4814{
4815 int i;
4816 for (i = 0; i < 15; i++)
4817 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4818 tbl_tx_filter_coef_rev4[2][i]);
4819}
4820
4821/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4822static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4823{
4824 int i, j;
4825 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4826 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4827
4828 for (i = 0; i < 3; i++)
4829 for (j = 0; j < 15; j++)
4830 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4831 tbl_tx_filter_coef_rev4[i][j]);
4832
bee6d4b2 4833 if (b43_is_40mhz(dev)) {
45ca697e
RM		 4834 for (j = 0; j < 15; j++)
4835 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4836 tbl_tx_filter_coef_rev4[3][j]);
4837 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4838 for (j = 0; j < 15; j++)
4839 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4840 tbl_tx_filter_coef_rev4[5][j]);
4841 }
4842
4843 if (dev->phy.channel == 14)
4844 for (j = 0; j < 15; j++)
4845 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4846 tbl_tx_filter_coef_rev4[6][j]);
4847}
4848
b0022e15
RM		 4849/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4850static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4851{
4852 struct b43_phy_n *nphy = dev->phy.n;
4853
4854 u16 curr_gain[2];
4855 struct nphy_txgains target;
4856 const u32 *table = NULL;
4857
161d540c 4858 if (!nphy->txpwrctrl) {
b0022e15
RM		 4859 int i;
4860
4861 if (nphy->hang_avoid)
4862 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4863 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4864 if (nphy->hang_avoid)
4865 b43_nphy_stay_in_carrier_search(dev, false);
4866
4867 for (i = 0; i < 2; ++i) {
40c68f20
RM		 4868 if (dev->phy.rev >= 7) {
4869 target.ipa[i] = curr_gain[i] & 0x0007;
4870 target.pad[i] = (curr_gain[i] & 0x00F8) >> 3;
4871 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4872 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4873 target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15;
4874 } else if (dev->phy.rev >= 3) {
b0022e15
RM		 4875 target.ipa[i] = curr_gain[i] & 0x000F;
4876 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4877 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4878 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4879 } else {
4880 target.ipa[i] = curr_gain[i] & 0x0003;
4881 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4882 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4883 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4884 }
4885 }
4886 } else {
4887 int i;
4888 u16 index[2];
4889 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4890 B43_NPHY_TXPCTL_STAT_BIDX) >>
4891 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4892 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4893 B43_NPHY_TXPCTL_STAT_BIDX) >>
4894 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4895
4896 for (i = 0; i < 2; ++i) {
aeab5751 4897 table = b43_nphy_get_tx_gain_table(dev);
7ef5cd24
RM		 4898 if (!table)
4899 break;
4900
40c68f20
RM		 4901 if (dev->phy.rev >= 7) {
4902 target.ipa[i] = (table[index[i]] >> 16) & 0x7;
4903 target.pad[i] = (table[index[i]] >> 19) & 0x1F;
4904 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4905 target.txgm[i] = (table[index[i]] >> 28) & 0x7;
4906 target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1;
4907 } else if (dev->phy.rev >= 3) {
b0022e15
RM		 4908 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4909 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4910 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4911 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4912 } else {
b0022e15
RM		 4913 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4914 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4915 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4916 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4917 }
4918 }
4919 }
4920
4921 return target;
4922}
4923
e53de674
RM		 4924/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4925static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4926{
4927 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4928
4929 if (dev->phy.rev >= 3) {
4930 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4931 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4932 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4933 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4934 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4935 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4936 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4937 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4938 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4939 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4940 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4941 b43_nphy_reset_cca(dev);
4942 } else {
4943 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4944 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4945 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4946 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4947 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4948 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4949 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4950 }
4951}
4952
4953/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4954static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4955{
303415e2 4956 struct b43_phy *phy = &dev->phy;
40c68f20 4957 struct b43_phy_n *nphy = dev->phy.n;
e53de674
RM		 4958 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4959 u16 tmp;
4960
4961 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4962 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4963 if (dev->phy.rev >= 3) {
4964 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4965 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4966
4967 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4968 regs[2] = tmp;
4969 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4970
4971 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4972 regs[3] = tmp;
4973 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4974
4975 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4976 b43_phy_mask(dev, B43_NPHY_BBCFG,
4977 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4978
c643a66e 4979 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4980 regs[5] = tmp;
d41a3552 4981 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4982
4983 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4984 regs[6] = tmp;
d41a3552 4985 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4986 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4987 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4988
40c68f20
RM		 4989 if (!nphy->use_int_tx_iq_lo_cal)
4990 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
4991 1, 3);
4992 else
4993 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
4994 0, 3);
89e43dad
RM		 4995 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4996 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4997
4998 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4999 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
5000 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
5001 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
303415e2 5002
40c68f20 5003 tmp = b43_nphy_read_lpf_ctl(dev, 0);
303415e2 5004 if (phy->rev >= 19)
40c68f20
RM		 5005 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false,
5006 1);
303415e2 5007 else if (phy->rev >= 7)
40c68f20
RM		 5008 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false,
5009 1);
303415e2 5010
40c68f20 5011 if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) {
303415e2 5012 if (phy->rev >= 19) {
40c68f20
RM		 5013 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3,
5014 false, 0);
303415e2 5015 } else if (phy->rev >= 8) {
40c68f20
RM		 5016 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3,
5017 false, 0);
303415e2 5018 } else if (phy->rev == 7) {
40c68f20
RM		 5019 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4);
5020 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5021 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0);
5022 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0);
5023 } else {
5024 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0);
5025 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0);
5026 }
303415e2
RM		 5027 }
5028 }
e53de674
RM		 5029 } else {
5030 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
5031 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
5032 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5033 regs[2] = tmp;
5034 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 5035 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 5036 regs[3] = tmp;
5037 tmp |= 0x2000;
d41a3552 5038 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 5039 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 5040 regs[4] = tmp;
5041 tmp |= 0x2000;
d41a3552 5042 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 5043 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
5044 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
5045 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
5046 tmp = 0x0180;
5047 else
5048 tmp = 0x0120;
5049 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
5050 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
5051 }
5052}
5053
bbc6dc12
RM		 5054/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
5055static void b43_nphy_save_cal(struct b43_wldev *dev)
5056{
303415e2 5057 struct b43_phy *phy = &dev->phy;
bbc6dc12
RM		 5058 struct b43_phy_n *nphy = dev->phy.n;
5059
5060 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
5061 u16 *txcal_radio_regs = NULL;
902db91d 5062 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 5063 u16 *table = NULL;
5064
5065 if (nphy->hang_avoid)
5066 b43_nphy_stay_in_carrier_search(dev, 1);
5067
5068 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5069 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
5070 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
5071 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
5072 table = nphy->cal_cache.txcal_coeffs_2G;
5073 } else {
5074 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
5075 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
5076 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
5077 table = nphy->cal_cache.txcal_coeffs_5G;
5078 }
5079
5080 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
5081 /* TODO use some definitions */
303415e2
RM		 5082 if (phy->rev >= 19) {
5083 /* TODO */
5084 } else if (phy->rev >= 7) {
40c68f20
RM		 5085 txcal_radio_regs[0] = b43_radio_read(dev,
5086 R2057_TX0_LOFT_FINE_I);
5087 txcal_radio_regs[1] = b43_radio_read(dev,
5088 R2057_TX0_LOFT_FINE_Q);
5089 txcal_radio_regs[4] = b43_radio_read(dev,
5090 R2057_TX0_LOFT_COARSE_I);
5091 txcal_radio_regs[5] = b43_radio_read(dev,
5092 R2057_TX0_LOFT_COARSE_Q);
5093 txcal_radio_regs[2] = b43_radio_read(dev,
5094 R2057_TX1_LOFT_FINE_I);
5095 txcal_radio_regs[3] = b43_radio_read(dev,
5096 R2057_TX1_LOFT_FINE_Q);
5097 txcal_radio_regs[6] = b43_radio_read(dev,
5098 R2057_TX1_LOFT_COARSE_I);
5099 txcal_radio_regs[7] = b43_radio_read(dev,
5100 R2057_TX1_LOFT_COARSE_Q);
303415e2 5101 } else if (phy->rev >= 3) {
bbc6dc12
RM		 5102 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
5103 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
5104 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
5105 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
5106 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
5107 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
5108 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
5109 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
5110 } else {
5111 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
5112 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
5113 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
5114 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
5115 }
39e971ef 5116 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
427fa00b
RM		 5117 iqcal_chanspec->channel_type =
5118 cfg80211_get_chandef_type(dev->phy.chandef);
5818e989 5119 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 5120
5121 if (nphy->hang_avoid)
5122 b43_nphy_stay_in_carrier_search(dev, 0);
5123}
5124
2f258b74
RM		 5125/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
5126static void b43_nphy_restore_cal(struct b43_wldev *dev)
5127{
303415e2 5128 struct b43_phy *phy = &dev->phy;
2f258b74
RM		 5129 struct b43_phy_n *nphy = dev->phy.n;
5130
5131 u16 coef[4];
5132 u16 *loft = NULL;
5133 u16 *table = NULL;
5134
5135 int i;
5136 u16 *txcal_radio_regs = NULL;
5137 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
5138
5139 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 5140 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 5141 return;
5142 table = nphy->cal_cache.txcal_coeffs_2G;
5143 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
5144 } else {
204a665b 5145 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 5146 return;
5147 table = nphy->cal_cache.txcal_coeffs_5G;
5148 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
5149 }
5150
2581b143 5151 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 5152
5153 for (i = 0; i < 4; i++) {
5154 if (dev->phy.rev >= 3)
5155 table[i] = coef[i];
5156 else
5157 coef[i] = 0;
5158 }
5159
2581b143
RM		 5160 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
5161 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
5162 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 5163
5164 if (dev->phy.rev < 2)
5165 b43_nphy_tx_iq_workaround(dev);
5166
5167 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5168 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
5169 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
5170 } else {
5171 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
5172 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
5173 }
5174
5175 /* TODO use some definitions */
303415e2
RM		 5176 if (phy->rev >= 19) {
5177 /* TODO */
5178 } else if (phy->rev >= 7) {
40c68f20
RM		 5179 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I,
5180 txcal_radio_regs[0]);
5181 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q,
5182 txcal_radio_regs[1]);
5183 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I,
5184 txcal_radio_regs[4]);
5185 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q,
5186 txcal_radio_regs[5]);
5187 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I,
5188 txcal_radio_regs[2]);
5189 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q,
5190 txcal_radio_regs[3]);
5191 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I,
5192 txcal_radio_regs[6]);
5193 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q,
5194 txcal_radio_regs[7]);
303415e2 5195 } else if (phy->rev >= 3) {
2f258b74
RM		 5196 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
5197 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
5198 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
5199 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
5200 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
5201 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
5202 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
5203 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
5204 } else {
5205 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
5206 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
5207 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
5208 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
5209 }
5210 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
5211}
5212
fb43b8e2
RM		 5213/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
5214static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
5215 struct nphy_txgains target,
5216 bool full, bool mphase)
5217{
39e971ef 5218 struct b43_phy *phy = &dev->phy;
fb43b8e2
RM		 5219 struct b43_phy_n *nphy = dev->phy.n;
5220 int i;
5221 int error = 0;
5222 int freq;
5223 bool avoid = false;
5224 u8 length;
fb23d863 5225 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 5226 const u16 *table;
5227 bool phy6or5x;
5228
5229 u16 buffer[11];
5230 u16 diq_start = 0;
5231 u16 save[2];
5232 u16 gain[2];
5233 struct nphy_iqcal_params params[2];
5234 bool updated[2] = { };
5235
5236 b43_nphy_stay_in_carrier_search(dev, true);
5237
5238 if (dev->phy.rev >= 4) {
5239 avoid = nphy->hang_avoid;
3db1cd5c 5240 nphy->hang_avoid = false;
fb43b8e2
RM		 5241 }
5242
9145834e 5243 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 5244
5245 for (i = 0; i < 2; i++) {
5246 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
5247 gain[i] = params[i].cal_gain;
5248 }
2581b143
RM		 5249
5250 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 5251
5252 b43_nphy_tx_cal_radio_setup(dev);
e53de674 5253 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 5254
5255 phy6or5x = dev->phy.rev >= 6 ||
5256 (dev->phy.rev == 5 && nphy->ipa2g_on &&
5257 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
5258 if (phy6or5x) {
bee6d4b2 5259 if (b43_is_40mhz(dev)) {
38bb9029
RM		 5260 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
5261 tbl_tx_iqlo_cal_loft_ladder_40);
5262 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
5263 tbl_tx_iqlo_cal_iqimb_ladder_40);
5264 } else {
5265 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
5266 tbl_tx_iqlo_cal_loft_ladder_20);
5267 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
5268 tbl_tx_iqlo_cal_iqimb_ladder_20);
5269 }
fb43b8e2
RM		 5270 }
5271
303415e2
RM		 5272 if (phy->rev >= 19) {
5273 /* TODO */
5274 } else if (phy->rev >= 7) {
40c68f20 5275 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9);
303415e2
RM		 5276 } else {
5277 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
5278 }
fb43b8e2 5279
bee6d4b2 5280 if (!b43_is_40mhz(dev))
fb43b8e2
RM		 5281 freq = 2500;
5282 else
5283 freq = 5000;
5284
5285 if (nphy->mphase_cal_phase_id > 2)
bee6d4b2 5286 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
ed03033e 5287 0xFFFF, 0, true, false, false);
fb43b8e2 5288 else
ed03033e 5289 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false);
fb43b8e2
RM		 5290
5291 if (error == 0) {
5292 if (nphy->mphase_cal_phase_id > 2) {
5293 table = nphy->mphase_txcal_bestcoeffs;
5294 length = 11;
5295 if (dev->phy.rev < 3)
5296 length -= 2;
5297 } else {
5298 if (!full && nphy->txiqlocal_coeffsvalid) {
5299 table = nphy->txiqlocal_bestc;
5300 length = 11;
5301 if (dev->phy.rev < 3)
5302 length -= 2;
5303 } else {
5304 full = true;
5305 if (dev->phy.rev >= 3) {
5306 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
5307 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
5308 } else {
5309 table = tbl_tx_iqlo_cal_startcoefs;
5310 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
5311 }
5312 }
5313 }
5314
2581b143 5315 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 5316
5317 if (full) {
5318 if (dev->phy.rev >= 3)
5319 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
5320 else
5321 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
5322 } else {
5323 if (dev->phy.rev >= 3)
5324 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
5325 else
5326 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
5327 }
5328
5329 if (mphase) {
5330 count = nphy->mphase_txcal_cmdidx;
5331 numb = min(max,
5332 (u16)(count + nphy->mphase_txcal_numcmds));
5333 } else {
5334 count = 0;
5335 numb = max;
5336 }
5337
5338 for (; count < numb; count++) {
5339 if (full) {
5340 if (dev->phy.rev >= 3)
5341 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
5342 else
5343 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
5344 } else {
5345 if (dev->phy.rev >= 3)
5346 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
5347 else
5348 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
5349 }
5350
5351 core = (cmd & 0x3000) >> 12;
5352 type = (cmd & 0x0F00) >> 8;
5353
5354 if (phy6or5x && updated[core] == 0) {
5355 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 5356 updated[core] = true;
fb43b8e2
RM		 5357 }
5358
5359 tmp = (params[core].ncorr[type] << 8) | 0x66;
5360 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
5361
5362 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 5363 buffer[0] = b43_ntab_read(dev,
5364 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 5365 diq_start = buffer[0];
5366 buffer[0] = 0;
d41a3552
RM		 5367 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
5368 0);
fb43b8e2
RM		 5369 }
5370
5371 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
5372 for (i = 0; i < 2000; i++) {
5373 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
5374 if (tmp & 0xC000)
5375 break;
5376 udelay(10);
5377 }
5378
9145834e
RM		 5379 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5380 buffer);
2581b143
RM		 5381 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
5382 buffer);
fb43b8e2
RM		 5383
5384 if (type == 1 || type == 3 || type == 4)
5385 buffer[0] = diq_start;
5386 }
5387
5388 if (mphase)
5389 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
5390
5391 last = (dev->phy.rev < 3) ? 6 : 7;
5392
5393 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 5394 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 5395 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 5396 if (dev->phy.rev < 3) {
5397 buffer[0] = 0;
5398 buffer[1] = 0;
5399 buffer[2] = 0;
5400 buffer[3] = 0;
5401 }
2581b143
RM		 5402 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5403 buffer);
bc53e512 5404 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 5405 buffer);
5406 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5407 buffer);
5408 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5409 buffer);
fb43b8e2
RM		 5410 length = 11;
5411 if (dev->phy.rev < 3)
5412 length -= 2;
9145834e
RM		 5413 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5414 nphy->txiqlocal_bestc);
fb43b8e2 5415 nphy->txiqlocal_coeffsvalid = true;
204a665b 5416 nphy->txiqlocal_chanspec.center_freq =
39e971ef 5417 phy->chandef->chan->center_freq;
204a665b 5418 nphy->txiqlocal_chanspec.channel_type =
427fa00b 5419 cfg80211_get_chandef_type(phy->chandef);
fb43b8e2
RM		 5420 } else {
5421 length = 11;
5422 if (dev->phy.rev < 3)
5423 length -= 2;
9145834e
RM		 5424 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5425 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 5426 }
5427
53ae8e8c 5428 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 5429 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
5430 }
5431
e53de674 5432 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 5433 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 5434
5435 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
5436 b43_nphy_tx_iq_workaround(dev);
5437
5438 if (dev->phy.rev >= 4)
5439 nphy->hang_avoid = avoid;
5440
5441 b43_nphy_stay_in_carrier_search(dev, false);
5442
5443 return error;
5444}
5445
984ff4ff
RM		 5446/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
5447static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
5448{
5449 struct b43_phy_n *nphy = dev->phy.n;
5450 u8 i;
5451 u16 buffer[7];
5452 bool equal = true;
5453
902db91d 5454 if (!nphy->txiqlocal_coeffsvalid ||
39e971ef 5455 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
427fa00b 5456 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef))
984ff4ff
RM		 5457 return;
5458
5459 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
5460 for (i = 0; i < 4; i++) {
5461 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
5462 equal = false;
5463 break;
5464 }
5465 }
5466
5467 if (!equal) {
5468 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
5469 nphy->txiqlocal_bestc);
5470 for (i = 0; i < 4; i++)
5471 buffer[i] = 0;
5472 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5473 buffer);
5474 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5475 &nphy->txiqlocal_bestc[5]);
5476 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5477 &nphy->txiqlocal_bestc[5]);
5478 }
5479}
5480
15931e31
RM		 5481/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
5482static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
5483 struct nphy_txgains target, u8 type, bool debug)
5484{
5485 struct b43_phy_n *nphy = dev->phy.n;
5486 int i, j, index;
5487 u8 rfctl[2];
5488 u8 afectl_core;
5489 u16 tmp[6];
c7455cf9 5490 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 5491 u32 real, imag;
5492 enum ieee80211_band band;
5493
5494 u8 use;
5495 u16 cur_hpf;
5496 u16 lna[3] = { 3, 3, 1 };
5497 u16 hpf1[3] = { 7, 2, 0 };
5498 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 5499 u32 power[3] = { };
15931e31
RM		 5500 u16 gain_save[2];
5501 u16 cal_gain[2];
5502 struct nphy_iqcal_params cal_params[2];
5503 struct nphy_iq_est est;
5504 int ret = 0;
5505 bool playtone = true;
5506 int desired = 13;
5507
5508 b43_nphy_stay_in_carrier_search(dev, 1);
5509
5510 if (dev->phy.rev < 2)
984ff4ff 5511 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 5512 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5513 for (i = 0; i < 2; i++) {
5514 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
5515 cal_gain[i] = cal_params[i].cal_gain;
5516 }
2581b143 5517 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 5518
5519 for (i = 0; i < 2; i++) {
5520 if (i == 0) {
5521 rfctl[0] = B43_NPHY_RFCTL_INTC1;
5522 rfctl[1] = B43_NPHY_RFCTL_INTC2;
5523 afectl_core = B43_NPHY_AFECTL_C1;
5524 } else {
5525 rfctl[0] = B43_NPHY_RFCTL_INTC2;
5526 rfctl[1] = B43_NPHY_RFCTL_INTC1;
5527 afectl_core = B43_NPHY_AFECTL_C2;
5528 }
5529
5530 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
5531 tmp[2] = b43_phy_read(dev, afectl_core);
5532 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5533 tmp[4] = b43_phy_read(dev, rfctl[0]);
5534 tmp[5] = b43_phy_read(dev, rfctl[1]);
5535
5536 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 5537 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 5538 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
5539 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
5540 (1 - i));
5541 b43_phy_set(dev, afectl_core, 0x0006);
5542 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
5543
5544 band = b43_current_band(dev->wl);
5545
5546 if (nphy->rxcalparams & 0xFF000000) {
5547 if (band == IEEE80211_BAND_5GHZ)
5548 b43_phy_write(dev, rfctl[0], 0x140);
5549 else
5550 b43_phy_write(dev, rfctl[0], 0x110);
5551 } else {
5552 if (band == IEEE80211_BAND_5GHZ)
5553 b43_phy_write(dev, rfctl[0], 0x180);
5554 else
5555 b43_phy_write(dev, rfctl[0], 0x120);
5556 }
5557
5558 if (band == IEEE80211_BAND_5GHZ)
5559 b43_phy_write(dev, rfctl[1], 0x148);
5560 else
5561 b43_phy_write(dev, rfctl[1], 0x114);
5562
5563 if (nphy->rxcalparams & 0x10000) {
5564 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
5565 (i + 1));
5566 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
5567 (2 - i));
5568 }
5569
30115c22 5570 for (j = 0; j < 4; j++) {
15931e31
RM		 5571 if (j < 3) {
5572 cur_lna = lna[j];
5573 cur_hpf1 = hpf1[j];
5574 cur_hpf2 = hpf2[j];
5575 } else {
5576 if (power[1] > 10000) {
5577 use = 1;
5578 cur_hpf = cur_hpf1;
5579 index = 2;
5580 } else {
5581 if (power[0] > 10000) {
5582 use = 1;
5583 cur_hpf = cur_hpf1;
5584 index = 1;
5585 } else {
5586 index = 0;
5587 use = 2;
5588 cur_hpf = cur_hpf2;
5589 }
5590 }
5591 cur_lna = lna[index];
5592 cur_hpf1 = hpf1[index];
5593 cur_hpf2 = hpf2[index];
5594 cur_hpf += desired - hweight32(power[index]);
5595 cur_hpf = clamp_val(cur_hpf, 0, 10);
5596 if (use == 1)
5597 cur_hpf1 = cur_hpf;
5598 else
5599 cur_hpf2 = cur_hpf;
5600 }
5601
5602 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
5603 (cur_lna << 2));
78ae7532 5604 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 5605 false);
de9a47f9 5606 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 5607 b43_nphy_stop_playback(dev);
15931e31
RM		 5608
5609 if (playtone) {
59af099b
RM		 5610 ret = b43_nphy_tx_tone(dev, 4000,
5611 (nphy->rxcalparams & 0xFFFF),
ed03033e 5612 false, false, true);
15931e31
RM		 5613 playtone = false;
5614 } else {
ed03033e
RM		 5615 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false,
5616 false, true);
15931e31
RM		 5617 }
5618
5619 if (ret == 0) {
5620 if (j < 3) {
5621 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
5622 false);
5623 if (i == 0) {
5624 real = est.i0_pwr;
5625 imag = est.q0_pwr;
5626 } else {
5627 real = est.i1_pwr;
5628 imag = est.q1_pwr;
5629 }
5630 power[i] = ((real + imag) / 1024) + 1;
5631 } else {
5632 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
5633 }
53ae8e8c 5634 b43_nphy_stop_playback(dev);
15931e31
RM		 5635 }
5636
5637 if (ret != 0)
5638 break;
5639 }
5640
5641 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5642 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5643 b43_phy_write(dev, rfctl[1], tmp[5]);
5644 b43_phy_write(dev, rfctl[0], tmp[4]);
5645 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5646 b43_phy_write(dev, afectl_core, tmp[2]);
5647 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5648
5649 if (ret != 0)
5650 break;
5651 }
5652
78ae7532 5653 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 5654 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 5655 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5656
5657 b43_nphy_stay_in_carrier_search(dev, 0);
5658
5659 return ret;
5660}
5661
5662static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5663 struct nphy_txgains target, u8 type, bool debug)
5664{
5665 return -1;
5666}
5667
5668/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5669static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5670 struct nphy_txgains target, u8 type, bool debug)
5671{
303415e2
RM		 5672 if (dev->phy.rev >= 7)
5673 type = 0;
5674
15931e31
RM		 5675 if (dev->phy.rev >= 3)
5676 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5677 else
5678 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5679}
5680
4e687b22
GS		 5681/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5682static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5683{
5684 struct b43_phy *phy = &dev->phy;
5685 struct b43_phy_n *nphy = phy->n;
0b81c23d 5686 /* u16 buf[16]; it's rev3+ */
4e687b22 5687
049fbfee
RM		 5688 nphy->phyrxchain = mask;
5689
4e687b22
GS		 5690 if (0 /* FIXME clk */)
5691 return;
5692
5693 b43_mac_suspend(dev);
5694
5695 if (nphy->hang_avoid)
5696 b43_nphy_stay_in_carrier_search(dev, true);
5697
5698 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5699 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5700
049fbfee 5701 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 5702 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5703 if (dev->phy.rev >= 3) {
5704 /* TODO */
5705 }
5706 } else {
5707 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5708 if (dev->phy.rev >= 3) {
5709 /* TODO */
5710 }
5711 }
5712
5713 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5714
5715 if (nphy->hang_avoid)
5716 b43_nphy_stay_in_carrier_search(dev, false);
5717
5718 b43_mac_enable(dev);
5719}
5720
104cfa88
RM		 5721/**************************************************
5722 * N-PHY init
5723 **************************************************/
5724
104cfa88
RM		 5725/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5726static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5727{
5728 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5729
5730 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5731 if (preamble == 1)
5732 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5733 else
5734 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5735
5736 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5737}
5738
5739/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5740static void b43_nphy_bphy_init(struct b43_wldev *dev)
5741{
5742 unsigned int i;
5743 u16 val;
5744
5745 val = 0x1E1F;
5746 for (i = 0; i < 16; i++) {
5747 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5748 val -= 0x202;
5749 }
5750 val = 0x3E3F;
5751 for (i = 0; i < 16; i++) {
5752 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5753 val -= 0x202;
5754 }
5755 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5756}
5757
5758/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5759static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5760{
303415e2
RM		 5761 if (dev->phy.rev >= 7)
5762 return;
5763
104cfa88
RM		 5764 if (dev->phy.rev >= 3) {
5765 if (!init)
5766 return;
5767 if (0 /* FIXME */) {
5768 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5769 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5770 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5771 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5772 }
5773 } else {
5774 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5775 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5776
5777 switch (dev->dev->bus_type) {
5778#ifdef CONFIG_B43_BCMA
5779 case B43_BUS_BCMA:
5780 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5781 0xFC00, 0xFC00);
5782 break;
5783#endif
5784#ifdef CONFIG_B43_SSB
5785 case B43_BUS_SSB:
5786 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5787 0xFC00, 0xFC00);
5788 break;
5789#endif
5790 }
5791
5056635c
RM		 5792 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5793 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5794 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5795 0);
104cfa88
RM		 5796
5797 if (init) {
5798 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5799 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5800 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5801 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5802 }
5803 }
5804}
5805
5806/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5807static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5808{
0581483a 5809 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5810 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5811 struct b43_phy_n *nphy = phy->n;
5812 u8 tx_pwr_state;
5813 struct nphy_txgains target;
95b66bad 5814 u16 tmp;
0988a7a1
RM		 5815 enum ieee80211_band tmp2;
5816 bool do_rssi_cal;
5817
5818 u16 clip[2];
5819 bool do_cal = false;
95b66bad 5820
0988a7a1 5821 if ((dev->phy.rev >= 3) &&
0581483a 5822 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5823 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5824 switch (dev->dev->bus_type) {
42c9a458
RM		 5825#ifdef CONFIG_B43_BCMA
5826 case B43_BUS_BCMA:
5827 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5828 BCMA_CC_CHIPCTL, 0x40);
5829 break;
5830#endif
6cbab0d9
RM		 5831#ifdef CONFIG_B43_SSB
5832 case B43_BUS_SSB:
5833 chipco_set32(&dev->dev->sdev->bus->chipco,
5834 SSB_CHIPCO_CHIPCTL, 0x40);
5835 break;
5836#endif
5837 }
0988a7a1 5838 }
40c68f20
RM		 5839 nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) ||
5840 phy->rev >= 7 ||
5841 (phy->rev >= 5 &&
5842 sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL);
0988a7a1 5843 nphy->deaf_count = 0;
95b66bad 5844 b43_nphy_tables_init(dev);
0988a7a1
RM		 5845 nphy->crsminpwr_adjusted = false;
5846 nphy->noisevars_adjusted = false;
95b66bad
MB		 5847
5848 /* Clear all overrides */
0988a7a1
RM		 5849 if (dev->phy.rev >= 3) {
5850 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5851 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
303415e2 5852 if (phy->rev >= 7) {
40c68f20
RM		 5853 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0);
5854 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0);
5855 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0);
5856 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0);
303415e2
RM		 5857 }
5858 if (phy->rev >= 19) {
5859 /* TODO */
5860 }
5861
0988a7a1
RM		 5862 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5863 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5864 } else {
5865 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5866 }
95b66bad
MB		 5867 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5868 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5869 if (dev->phy.rev < 6) {
5870 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5871 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5872 }
95b66bad
MB		 5873 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5874 ~(B43_NPHY_RFSEQMODE_CAOVER |
5875 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5876 if (dev->phy.rev >= 3)
5877 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5878 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5879
0988a7a1
RM		 5880 if (dev->phy.rev <= 2) {
5881 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5882 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5883 ~B43_NPHY_BPHY_CTL3_SCALE,
5884 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5885 }
95b66bad
MB		 5886 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5887 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5888
0eff8fcd 5889 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5890 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5891 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5892 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5893 else
5894 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5895 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5896 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5897 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5898
303415e2
RM		 5899 if (phy->rev < 8)
5900 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
5901
4f4ab6cd 5902 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5903
5904 if (phy->rev < 2) {
5905 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5906 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5907 }
0988a7a1
RM		 5908
5909 tmp2 = b43_current_band(dev->wl);
c002831a 5910 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5911 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5912 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5913 nphy->papd_epsilon_offset[0] << 7);
5914 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5915 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5916 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5917 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5918 } else if (phy->rev >= 5) {
45ca697e 5919 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5920 }
5921
95b66bad 5922 b43_nphy_workarounds(dev);
95b66bad 5923
0988a7a1 5924 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5925 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5926 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5927 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5928 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5929 b43_phy_force_clock(dev, 0);
0988a7a1 5930
858a1652 5931 b43_mac_phy_clock_set(dev, true);
0988a7a1 5932
303415e2
RM		 5933 if (phy->rev < 7) {
5934 b43_nphy_pa_override(dev, false);
5935 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5936 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5937 b43_nphy_pa_override(dev, true);
5938 }
0988a7a1 5939
bbec398c
RM		 5940 b43_nphy_classifier(dev, 0, 0);
5941 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5942 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5943 b43_nphy_bphy_init(dev);
5944
0988a7a1 5945 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5946 b43_nphy_tx_power_ctrl(dev, false);
5947 b43_nphy_tx_power_fix(dev);
3dda07b6 5948 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5949 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5950 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5951
0988a7a1 5952 if (nphy->phyrxchain != 3)
4e687b22 5953 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5954 if (nphy->mphase_cal_phase_id > 0)
5955 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5956
5957 do_rssi_cal = false;
5958 if (phy->rev >= 3) {
5959 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5960 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5961 else
204a665b 5962 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5963
5964 if (do_rssi_cal)
4cb99775 5965 b43_nphy_rssi_cal(dev);
0988a7a1 5966 else
42e1547e 5967 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5968 } else {
4cb99775 5969 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5970 }
5971
5972 if (!((nphy->measure_hold & 0x6) != 0)) {
5973 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5974 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5975 else
204a665b 5976 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5977
5978 if (nphy->mute)
5979 do_cal = false;
5980
5981 if (do_cal) {
b0022e15 5982 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5983
5984 if (nphy->antsel_type == 2)
8987a9e9 5985 b43_nphy_superswitch_init(dev, true);
0988a7a1 5986 if (nphy->perical != 2) {
90b9738d 5987 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5988 if (phy->rev >= 3) {
5989 nphy->cal_orig_pwr_idx[0] =
5990 nphy->txpwrindex[0].index_internal;
5991 nphy->cal_orig_pwr_idx[1] =
5992 nphy->txpwrindex[1].index_internal;
5993 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5994 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5995 }
e7797bf2
RM		 5996 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5997 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5998 b43_nphy_save_cal(dev);
5999 } else if (nphy->mphase_cal_phase_id == 0)
6000 ;/* N PHY Periodic Calibration with arg 3 */
6001 } else {
6002 b43_nphy_restore_cal(dev);
0988a7a1
RM		 6003 }
6004 }
6005
6dcd9d91 6006 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 6007 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 6008 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
6009 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
6010 if (phy->rev >= 3 && phy->rev <= 6)
bc36e994 6011 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
8ac3a2aa 6012 b43_nphy_tx_lpf_bw(dev);
9442e5b5
RM		 6013 if (phy->rev >= 3)
6014 b43_nphy_spur_workaround(dev);
95b66bad 6015
53a6e234 6016 return 0;
424047e6 6017}
ef1a628d 6018
104cfa88
RM		 6019/**************************************************
6020 * Channel switching ops.
6021 **************************************************/
6022
6023static void b43_chantab_phy_upload(struct b43_wldev *dev,
6024 const struct b43_phy_n_sfo_cfg *e)
6025{
6026 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
6027 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
6028 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
6029 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
6030 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
6031 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
6032}
6033
49d55cef
RM		 6034/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
6035static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
6036{
d66be829
RM		 6037 switch (dev->dev->bus_type) {
6038#ifdef CONFIG_B43_BCMA
6039 case B43_BUS_BCMA:
9b383672
HM		 6040 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
6041 avoid);
d66be829 6042 break;
8b1fdb53 6043#endif
d66be829
RM		 6044#ifdef CONFIG_B43_SSB
6045 case B43_BUS_SSB:
46fc4c90
RM		 6046 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
6047 avoid);
d66be829
RM		 6048 break;
6049#endif
6050 }
49d55cef
RM		 6051}
6052
1b69ec7b 6053/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 6054static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 6055 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 6056 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 6057{
6058 struct b43_phy *phy = &dev->phy;
6059 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 6060 int ch = new_channel->hw_value;
1b69ec7b 6061
087de74a 6062 u16 old_band_5ghz;
12cd43c6 6063 u16 tmp16;
1b69ec7b 6064
087de74a
RM		 6065 old_band_5ghz =
6066 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
6067 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 6068 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
6069 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 6070 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 6071 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 6072 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 6073 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 6074 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 6075 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
6076 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 6077 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 6078 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 6079 }
6080
6081 b43_chantab_phy_upload(dev, e);
6082
a656b6a9 6083 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 6084 b43_nphy_classifier(dev, 2, 0);
6085 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
6086 } else {
6087 b43_nphy_classifier(dev, 2, 2);
a656b6a9 6088 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 6089 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
6090 }
6091
161d540c 6092 if (!nphy->txpwrctrl)
1b69ec7b
RM		 6093 b43_nphy_tx_power_fix(dev);
6094
6095 if (dev->phy.rev < 3)
6096 b43_nphy_adjust_lna_gain_table(dev);
6097
8ac3a2aa 6098 b43_nphy_tx_lpf_bw(dev);
1b69ec7b 6099
49d55cef
RM		 6100 if (dev->phy.rev >= 3 &&
6101 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
6102 bool avoid = false;
6103 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
6104 avoid = true;
427fa00b 6105 } else if (!b43_is_40mhz(dev)) {
49d55cef
RM		 6106 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
6107 avoid = true;
6108 } else { /* 40MHz */
6109 if (nphy->aband_spurwar_en &&
6110 (ch == 38 || ch == 102 || ch == 118))
6111 avoid = dev->dev->chip_id == 0x4716;
6112 }
6113
6114 b43_nphy_pmu_spur_avoid(dev, avoid);
6115
6116 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
6117 dev->dev->chip_id == 43225) {
6118 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
6119 avoid ? 0x5341 : 0x8889);
6120 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
6121 }
6122
6123 if (dev->phy.rev == 3 || dev->phy.rev == 4)
6124 ; /* TODO: reset PLL */
6125
6126 if (avoid)
6127 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
6128 else
6129 b43_phy_mask(dev, B43_NPHY_BBCFG,
6130 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
6131
6132 b43_nphy_reset_cca(dev);
6133
6134 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 6135 }
6136
6137 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
6138
6139 if (phy->rev >= 3)
6140 b43_nphy_spur_workaround(dev);
6141}
6142
eff66c51 6143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 6144static int b43_nphy_set_channel(struct b43_wldev *dev,
6145 struct ieee80211_channel *channel,
6146 enum nl80211_channel_type channel_type)
eff66c51 6147{
a656b6a9 6148 struct b43_phy *phy = &dev->phy;
eff66c51 6149
2eeb6fd0
JL		 6150 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
6151 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
fe255b40
RM		 6152 const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL;
6153 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL;
eff66c51
RM		 6154
6155 u8 tmp;
eff66c51 6156
303415e2
RM		 6157 if (phy->rev >= 19) {
6158 return -ESRCH;
6159 /* TODO */
6160 } else if (phy->rev >= 7) {
fe255b40
RM		 6161 r2057_get_chantabent_rev7(dev, channel->center_freq,
6162 &tabent_r7, &tabent_r7_2g);
6163 if (!tabent_r7 && !tabent_r7_2g)
6164 return -ESRCH;
6165 } else if (phy->rev >= 3) {
f2a6d6a0
RM		 6166 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
6167 channel->center_freq);
f19ebe7d
RM		 6168 if (!tabent_r3)
6169 return -ESRCH;
ffd2d9bd 6170 } else {
a656b6a9
RM		 6171 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
6172 channel->hw_value);
f19ebe7d 6173 if (!tabent_r2)
ffd2d9bd 6174 return -ESRCH;
eff66c51
RM		 6175 }
6176
204a665b
RM		 6177 /* Channel is set later in common code, but we need to set it on our
6178 own to let this function's subcalls work properly. */
6179 phy->channel = channel->hw_value;
eff66c51 6180
427fa00b 6181#if 0
e5c407f9
RM		 6182 if (b43_channel_type_is_40mhz(phy->channel_type) !=
6183 b43_channel_type_is_40mhz(channel_type))
6184 ; /* TODO: BMAC BW Set (channel_type) */
427fa00b 6185#endif
eff66c51 6186
fe255b40
RM		 6187 if (channel_type == NL80211_CHAN_HT40PLUS) {
6188 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20);
6189 if (phy->rev >= 7)
6190 b43_phy_set(dev, 0x310, 0x8000);
6191 } else if (channel_type == NL80211_CHAN_HT40MINUS) {
6192 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20);
6193 if (phy->rev >= 7)
6194 b43_phy_mask(dev, 0x310, (u16)~0x8000);
6195 }
eff66c51 6196
303415e2
RM		 6197 if (phy->rev >= 19) {
6198 /* TODO */
6199 } else if (phy->rev >= 7) {
fe255b40
RM		 6200 const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ?
6201 &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs);
6202
6203 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
6204 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 2 : 0;
6205 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp);
6206 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp);
6207 }
6208
6209 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g);
6210 b43_nphy_channel_setup(dev, phy_regs, channel);
6211 } else if (phy->rev >= 3) {
a656b6a9 6212 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 6213 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 6214 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 6215 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 6216 } else {
a656b6a9 6217 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 6218 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 6219 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 6220 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 6221 }
6222
6223 return 0;
6224}
6225
104cfa88
RM		 6226/**************************************************
6227 * Basic PHY ops.
6228 **************************************************/
6229
ef1a628d
MB		 6230static int b43_nphy_op_allocate(struct b43_wldev *dev)
6231{
6232 struct b43_phy_n *nphy;
6233
6234 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
6235 if (!nphy)
6236 return -ENOMEM;
6237 dev->phy.n = nphy;
6238
ef1a628d
MB		 6239 return 0;
6240}
6241
fb11137a 6242static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 6243{
fb11137a
MB		 6244 struct b43_phy *phy = &dev->phy;
6245 struct b43_phy_n *nphy = phy->n;
c7d64310 6246 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 6247
fb11137a 6248 memset(nphy, 0, sizeof(*nphy));
ef1a628d 6249
aca434d3 6250 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 6251 nphy->spur_avoid = (phy->rev >= 3) ?
6252 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
0b81c23d
RM		 6253 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
6254 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
6255 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 6256 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 6257 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
6258 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
6259 nphy->tx_pwr_idx[0] = 128;
6260 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 6261
6262 /* Hardware TX power control and 5GHz power gain */
6263 nphy->txpwrctrl = false;
6264 nphy->pwg_gain_5ghz = false;
6265 if (dev->phy.rev >= 3 ||
6266 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
6267 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
6268 nphy->txpwrctrl = true;
6269 nphy->pwg_gain_5ghz = true;
6270 } else if (sprom->revision >= 4) {
6271 if (dev->phy.rev >= 2 &&
6272 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
6273 nphy->txpwrctrl = true;
6274#ifdef CONFIG_B43_SSB
6275 if (dev->dev->bus_type == B43_BUS_SSB &&
6276 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
6277 struct pci_dev *pdev =
6278 dev->dev->sdev->bus->host_pci;
6279 if (pdev->device == 0x4328 ||
6280 pdev->device == 0x432a)
6281 nphy->pwg_gain_5ghz = true;
6282 }
6283#endif
6284 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
6285 nphy->pwg_gain_5ghz = true;
6286 }
6287 }
6288
6289 if (dev->phy.rev >= 3) {
6290 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
6291 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
6292 }
ef1a628d
MB		 6293}
6294
fb11137a 6295static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 6296{
fb11137a
MB		 6297 struct b43_phy *phy = &dev->phy;
6298 struct b43_phy_n *nphy = phy->n;
ef1a628d 6299
ef1a628d 6300 kfree(nphy);
fb11137a
MB		 6301 phy->n = NULL;
6302}
6303
6304static int b43_nphy_op_init(struct b43_wldev *dev)
6305{
6306 return b43_phy_initn(dev);
ef1a628d
MB		 6307}
6308
6309static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
6310{
6311#if B43_DEBUG
6312 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
6313 /* OFDM registers are onnly available on A/G-PHYs */
6314 b43err(dev->wl, "Invalid OFDM PHY access at "
6315 "0x%04X on N-PHY\n", offset);
6316 dump_stack();
6317 }
6318 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
6319 /* Ext-G registers are only available on G-PHYs */
6320 b43err(dev->wl, "Invalid EXT-G PHY access at "
6321 "0x%04X on N-PHY\n", offset);
6322 dump_stack();
6323 }
6324#endif /* B43_DEBUG */
6325}
6326
6327static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
6328{
6329 check_phyreg(dev, reg);
6330 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
6331 return b43_read16(dev, B43_MMIO_PHY_DATA);
6332}
6333
6334static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
6335{
6336 check_phyreg(dev, reg);
6337 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
6338 b43_write16(dev, B43_MMIO_PHY_DATA, value);
6339}
6340
755fd183
RM		 6341static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
6342 u16 set)
6343{
6344 check_phyreg(dev, reg);
6345 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 6346 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 6347}
6348
ef1a628d
MB		 6349static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
6350{
6351 /* Register 1 is a 32-bit register. */
0933ecf9 6352 B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
a6aa05d6
RM		 6353
6354 if (dev->phy.rev >= 7)
6355 reg |= 0x200; /* Radio 0x2057 */
6356 else
6357 reg |= 0x100;
ef1a628d
MB		 6358
6359 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
6360 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
6361}
6362
6363static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
6364{
6365 /* Register 1 is a 32-bit register. */
0933ecf9 6366 B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
ef1a628d
MB		 6367
6368 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
6369 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
6370}
6371
c2b7aefd 6372/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 6373static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 6374 bool blocked)
c2b7aefd 6375{
303415e2
RM		 6376 struct b43_phy *phy = &dev->phy;
6377
c2b7aefd
RM		 6378 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
6379 b43err(dev->wl, "MAC not suspended\n");
6380
6381 if (blocked) {
303415e2 6382 if (phy->rev >= 19) {
572d37a4 6383 /* TODO */
40c68f20
RM		 6384 } else if (phy->rev >= 8) {
6385 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
6386 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
303415e2 6387 } else if (phy->rev >= 7) {
40c68f20 6388 /* Nothing needed */
303415e2 6389 } else if (phy->rev >= 3) {
40c68f20
RM		 6390 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
6391 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
6392
c2b7aefd
RM		 6393 b43_radio_mask(dev, 0x09, ~0x2);
6394
6395 b43_radio_write(dev, 0x204D, 0);
6396 b43_radio_write(dev, 0x2053, 0);
6397 b43_radio_write(dev, 0x2058, 0);
6398 b43_radio_write(dev, 0x205E, 0);
6399 b43_radio_mask(dev, 0x2062, ~0xF0);
6400 b43_radio_write(dev, 0x2064, 0);
6401
6402 b43_radio_write(dev, 0x304D, 0);
6403 b43_radio_write(dev, 0x3053, 0);
6404 b43_radio_write(dev, 0x3058, 0);
6405 b43_radio_write(dev, 0x305E, 0);
6406 b43_radio_mask(dev, 0x3062, ~0xF0);
6407 b43_radio_write(dev, 0x3064, 0);
6408 }
6409 } else {
303415e2
RM		 6410 if (phy->rev >= 19) {
6411 /* TODO */
6412 } else if (phy->rev >= 7) {
6fe55143
RM		 6413 if (!dev->phy.radio_on)
6414 b43_radio_2057_init(dev);
572d37a4 6415 b43_switch_channel(dev, dev->phy.channel);
303415e2 6416 } else if (phy->rev >= 3) {
6fe55143
RM		 6417 if (!dev->phy.radio_on)
6418 b43_radio_init2056(dev);
78159788 6419 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 6420 } else {
6421 b43_radio_init2055(dev);
6422 }
6423 }
ef1a628d
MB		 6424}
6425
0f4091b9 6426/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 6427static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
6428{
303415e2 6429 struct b43_phy *phy = &dev->phy;
2a870831
RM		 6430 u16 override = on ? 0x0 : 0x7FFF;
6431 u16 core = on ? 0xD : 0x00FD;
0f4091b9 6432
303415e2
RM		 6433 if (phy->rev >= 19) {
6434 /* TODO */
6435 } else if (phy->rev >= 3) {
2a870831
RM		 6436 if (on) {
6437 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6438 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6439 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6440 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6441 } else {
6442 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6443 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6444 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6445 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6446 }
6447 } else {
6448 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6449 }
cb24f57f
MB		 6450}
6451
ef1a628d
MB		 6452static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
6453 unsigned int new_channel)
6454{
675a0b04
KB		 6455 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
6456 enum nl80211_channel_type channel_type =
6457 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 6458
ef1a628d
MB		 6459 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
6460 if ((new_channel < 1) || (new_channel > 14))
6461 return -EINVAL;
6462 } else {
6463 if (new_channel > 200)
6464 return -EINVAL;
6465 }
6466
a656b6a9 6467 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 6468}
6469
6470static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
6471{
6472 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
6473 return 1;
6474 return 36;
6475}
6476
ef1a628d
MB		 6477const struct b43_phy_operations b43_phyops_n = {
6478 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 6479 .free = b43_nphy_op_free,
6480 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 6481 .init = b43_nphy_op_init,
ef1a628d
MB		 6482 .phy_read = b43_nphy_op_read,
6483 .phy_write = b43_nphy_op_write,
755fd183 6484 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 6485 .radio_read = b43_nphy_op_radio_read,
6486 .radio_write = b43_nphy_op_radio_write,
6487 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 6488 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 6489 .switch_channel = b43_nphy_op_switch_channel,
6490 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 6491 .recalc_txpower = b43_nphy_op_recalc_txpower,
6492 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 6493};
Linux kernel - Deliverables
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