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b43: N-PHY: initialize hardware tables on new devices
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
89e43dad
RM		 72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
2a2d0589
RM		 80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
76b002bd
RM		 88};
89
6aa38725
RM		 90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
76b002bd
RM		 93};
94
c002831a
RM		 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
e0c9a021
RM		 102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
ab499217 109/**************************************************
89e43dad 110 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 111 **************************************************/
18c8adeb 112
ab499217
RM		 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
d1591314 116{
ab499217
RM		 117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 127
ab499217 128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 129
ab499217
RM		 130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
e5255ccc 142
c071b9f6 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
146 u8 override)
c071b9f6
RM		 147{
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
151 };
152 u16 en_addr;
153 u16 en_mask = field;
154 u16 val_addr;
155 u8 i;
156
157 /* Remember: we can get NULL! */
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
159
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
163 return;
164 }
165 en_addr = en_addrs[override][i];
166
8ce9beac
FP		 167 if (e)
168 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 169
170 if (off) {
171 b43_phy_mask(dev, en_addr, ~en_mask);
172 if (e) /* Do it safer, better than wl */
173 b43_phy_mask(dev, val_addr, ~e->val_mask);
174 } else {
175 if (!core || (core & (1 << i))) {
176 b43_phy_set(dev, en_addr, en_mask);
177 if (e)
178 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
179 }
180 }
181 }
182}
183
ab499217 184/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 185static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
186 u16 value, u8 core, bool off)
ab499217
RM		 187{
188 int i;
189 u8 index = fls(field);
190 u8 addr, en_addr, val_addr;
191 /* we expect only one bit set */
192 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 193
ab499217
RM		 194 if (dev->phy.rev >= 3) {
195 const struct nphy_rf_control_override_rev3 *rf_ctrl;
196 for (i = 0; i < 2; i++) {
197 if (index == 0 || index == 16) {
198 b43err(dev->wl,
199 "Unsupported RF Ctrl Override call\n");
200 return;
201 }
e5255ccc 202
ab499217
RM		 203 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
204 en_addr = B43_PHY_N((i == 0) ?
205 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
206 val_addr = B43_PHY_N((i == 0) ?
207 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 208
ab499217
RM		 209 if (off) {
210 b43_phy_mask(dev, en_addr, ~(field));
211 b43_phy_mask(dev, val_addr,
212 ~(rf_ctrl->val_mask));
213 } else {
b97c0718 214 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 215 b43_phy_set(dev, en_addr, field);
216 b43_phy_maskset(dev, val_addr,
217 ~(rf_ctrl->val_mask),
218 (value << rf_ctrl->val_shift));
219 }
220 }
221 }
222 } else {
223 const struct nphy_rf_control_override_rev2 *rf_ctrl;
224 if (off) {
225 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
226 value = 0;
227 } else {
228 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
229 }
d4814e69 230
ab499217
RM		 231 for (i = 0; i < 2; i++) {
232 if (index <= 1 || index == 16) {
233 b43err(dev->wl,
234 "Unsupported RF Ctrl Override call\n");
235 return;
236 }
d4814e69 237
ab499217
RM		 238 if (index == 2 || index == 10 ||
239 (index >= 13 && index <= 15)) {
240 core = 1;
241 }
d4814e69 242
ab499217
RM		 243 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
244 addr = B43_PHY_N((i == 0) ?
245 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 246
b97c0718 247 if ((1 << i) & core)
ab499217
RM		 248 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
249 (value << rf_ctrl->shift));
250
251 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
252 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
253 B43_NPHY_RFCTL_CMD_START);
254 udelay(1);
255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
256 }
257 }
d4814e69
RM		 258}
259
4256ba77
RM		 260static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
261 enum n_intc_override intc_override,
262 u16 value, u8 core_sel)
263{
264 u16 reg, tmp, tmp2, val;
265 int core;
266
267 for (core = 0; core < 2; core++) {
268 if ((core_sel == 1 && core != 0) ||
269 (core_sel == 2 && core != 1))
270 continue;
271
272 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
273
274 switch (intc_override) {
275 case N_INTC_OVERRIDE_OFF:
276 b43_phy_write(dev, reg, 0);
277 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
278 break;
279 case N_INTC_OVERRIDE_TRSW:
280 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
281 b43_phy_set(dev, reg, 0x400);
282
283 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
284 b43_phy_set(dev, 0x2ff, 0x2000);
285 b43_phy_set(dev, 0x2ff, 0x0001);
286 break;
287 case N_INTC_OVERRIDE_PA:
288 tmp = 0x0030;
289 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
290 val = value << 5;
291 else
292 val = value << 4;
293 b43_phy_maskset(dev, reg, ~tmp, val);
294 b43_phy_set(dev, reg, 0x1000);
295 break;
296 case N_INTC_OVERRIDE_EXT_LNA_PU:
297 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
298 tmp = 0x0001;
299 tmp2 = 0x0004;
300 val = value;
301 } else {
302 tmp = 0x0004;
303 tmp2 = 0x0001;
304 val = value << 2;
305 }
306 b43_phy_maskset(dev, reg, ~tmp, val);
307 b43_phy_mask(dev, reg, ~tmp2);
308 break;
309 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
310 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
311 tmp = 0x0002;
312 tmp2 = 0x0008;
313 val = value << 1;
314 } else {
315 tmp = 0x0008;
316 tmp2 = 0x0002;
317 val = value << 3;
318 }
319 b43_phy_maskset(dev, reg, ~tmp, val);
320 b43_phy_mask(dev, reg, ~tmp2);
321 break;
322 }
323 }
324}
325
ab499217 326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 327static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
328 enum n_intc_override intc_override,
329 u16 value, u8 core)
d4814e69 330{
ab499217
RM		 331 u8 i, j;
332 u16 reg, tmp, val;
38646eba 333
4256ba77
RM		 334 if (dev->phy.rev >= 7) {
335 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
336 core);
337 return;
338 }
339
d4814e69
RM		 340 B43_WARN_ON(dev->phy.rev < 3);
341
ab499217
RM		 342 for (i = 0; i < 2; i++) {
343 if ((core == 1 && i == 1) || (core == 2 && !i))
344 continue;
38646eba 345
ab499217
RM		 346 reg = (i == 0) ?
347 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 348 b43_phy_set(dev, reg, 0x400);
38646eba 349
89e43dad
RM		 350 switch (intc_override) {
351 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 352 b43_phy_write(dev, reg, 0);
353 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
354 break;
89e43dad 355 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 356 if (!i) {
357 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
358 0xFC3F, (value << 6));
359 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
360 0xFFFE, 1);
361 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
362 B43_NPHY_RFCTL_CMD_START);
363 for (j = 0; j < 100; j++) {
603431e9 364 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 365 j = 0;
366 break;
367 }
368 udelay(10);
38646eba 369 }
ab499217
RM		 370 if (j)
371 b43err(dev->wl,
372 "intc override timeout\n");
373 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
374 0xFFFE);
38646eba 375 } else {
ab499217
RM		 376 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
377 0xFC3F, (value << 6));
378 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
379 0xFFFE, 1);
380 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
381 B43_NPHY_RFCTL_CMD_RXTX);
382 for (j = 0; j < 100; j++) {
603431e9 383 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 384 j = 0;
385 break;
386 }
387 udelay(10);
388 }
389 if (j)
390 b43err(dev->wl,
391 "intc override timeout\n");
392 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
393 0xFFFE);
38646eba 394 }
ab499217 395 break;
89e43dad 396 case N_INTC_OVERRIDE_PA:
ab499217
RM		 397 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
398 tmp = 0x0020;
399 val = value << 5;
400 } else {
401 tmp = 0x0010;
402 val = value << 4;
403 }
404 b43_phy_maskset(dev, reg, ~tmp, val);
405 break;
89e43dad 406 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 407 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
408 tmp = 0x0001;
409 val = value;
410 } else {
411 tmp = 0x0004;
412 val = value << 2;
413 }
414 b43_phy_maskset(dev, reg, ~tmp, val);
415 break;
89e43dad 416 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 417 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
418 tmp = 0x0002;
419 val = value << 1;
420 } else {
421 tmp = 0x0008;
422 val = value << 3;
423 }
424 b43_phy_maskset(dev, reg, ~tmp, val);
425 break;
38646eba 426 }
38646eba 427 }
ab499217 428}
38646eba 429
ab499217
RM		 430/**************************************************
431 * Various PHY ops
432 **************************************************/
433
434/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
435static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
436 const u16 *clip_st)
437{
438 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
439 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 440}
441
ab499217
RM		 442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
443static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 444{
ab499217
RM		 445 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
446 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 447}
448
ab499217
RM		 449/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
450static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 451{
ab499217 452 u16 tmp;
161d540c 453
ab499217
RM		 454 if (dev->dev->core_rev == 16)
455 b43_mac_suspend(dev);
161d540c 456
ab499217
RM		 457 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
458 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
459 B43_NPHY_CLASSCTL_WAITEDEN);
460 tmp &= ~mask;
461 tmp |= (val & mask);
462 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 463
ab499217
RM		 464 if (dev->dev->core_rev == 16)
465 b43_mac_enable(dev);
161d540c 466
ab499217
RM		 467 return tmp;
468}
161d540c 469
ab499217
RM		 470/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
471static void b43_nphy_reset_cca(struct b43_wldev *dev)
472{
473 u16 bbcfg;
161d540c 474
ab499217
RM		 475 b43_phy_force_clock(dev, 1);
476 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
477 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
478 udelay(1);
479 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
480 b43_phy_force_clock(dev, 0);
481 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
482}
161d540c 483
ab499217
RM		 484/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
485static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
486{
487 struct b43_phy *phy = &dev->phy;
488 struct b43_phy_n *nphy = phy->n;
161d540c 489
ab499217
RM		 490 if (enable) {
491 static const u16 clip[] = { 0xFFFF, 0xFFFF };
492 if (nphy->deaf_count++ == 0) {
493 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
bc36e994
RM		 494 b43_nphy_classifier(dev, 0x7,
495 B43_NPHY_CLASSCTL_WAITEDEN);
ab499217
RM		 496 b43_nphy_read_clip_detection(dev, nphy->clip_state);
497 b43_nphy_write_clip_detection(dev, clip);
498 }
499 b43_nphy_reset_cca(dev);
161d540c 500 } else {
ab499217
RM		 501 if (--nphy->deaf_count == 0) {
502 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
503 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 504 }
161d540c 505 }
161d540c
RM		 506}
507
64712095
RM		 508/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
509static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 510{
161d540c 511 struct b43_phy_n *nphy = dev->phy.n;
161d540c 512
64712095
RM		 513 u8 i;
514 s16 tmp;
515 u16 data[4];
516 s16 gain[2];
517 u16 minmax[2];
518 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 519
520 if (nphy->hang_avoid)
521 b43_nphy_stay_in_carrier_search(dev, 1);
522
64712095 523 if (nphy->gain_boost) {
161d540c 524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 525 gain[0] = 6;
526 gain[1] = 6;
161d540c 527 } else {
64712095
RM		 528 tmp = 40370 - 315 * dev->phy.channel;
529 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
530 tmp = 23242 - 224 * dev->phy.channel;
531 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 532 }
64712095
RM		 533 } else {
534 gain[0] = 0;
535 gain[1] = 0;
161d540c 536 }
161d540c
RM		 537
538 for (i = 0; i < 2; i++) {
64712095
RM		 539 if (nphy->elna_gain_config) {
540 data[0] = 19 + gain[i];
541 data[1] = 25 + gain[i];
542 data[2] = 25 + gain[i];
543 data[3] = 25 + gain[i];
161d540c 544 } else {
64712095
RM		 545 data[0] = lna_gain[0] + gain[i];
546 data[1] = lna_gain[1] + gain[i];
547 data[2] = lna_gain[2] + gain[i];
548 data[3] = lna_gain[3] + gain[i];
161d540c 549 }
64712095 550 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 551
64712095 552 minmax[i] = 23 + gain[i];
161d540c
RM		 553 }
554
64712095
RM		 555 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
556 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
557 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
558 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 559
560 if (nphy->hang_avoid)
561 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 562}
563
ab499217
RM		 564/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
565static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
566 u8 *events, u8 *delays, u8 length)
0eff8fcd 567{
ab499217
RM		 568 struct b43_phy_n *nphy = dev->phy.n;
569 u8 i;
570 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
571 u16 offset1 = cmd << 4;
572 u16 offset2 = offset1 + 0x80;
0eff8fcd 573
ab499217
RM		 574 if (nphy->hang_avoid)
575 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 576
ab499217
RM		 577 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
578 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 579
ab499217
RM		 580 for (i = length; i < 16; i++) {
581 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
582 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 583 }
ab499217
RM		 584
585 if (nphy->hang_avoid)
586 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 587}
7955de0c 588
572d37a4
RM		 589/**************************************************
590 * Radio 0x2057
591 **************************************************/
592
fe255b40
RM		 593static void b43_radio_2057_chantab_upload(struct b43_wldev *dev,
594 const struct b43_nphy_chantabent_rev7 *e_r7,
595 const struct b43_nphy_chantabent_rev7_2g *e_r7_2g)
596{
597 if (e_r7_2g) {
598 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
599 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
600 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
601 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
602 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
603 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
604 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
605 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
606 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
607 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
608 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
609 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
610 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
611 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
612 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
613 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
614 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
615 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);
616
617 } else {
618 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
619 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
620 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
621 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
622 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
623 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
624 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
625 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
626 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
627 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
628 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
629 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
630 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
631 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
632 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
633 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
634 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
635 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
636 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
637 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
638 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
639 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
640 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
641 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
642 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
643 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
644 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
645 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
646 }
647}
648
649static void b43_radio_2057_setup(struct b43_wldev *dev,
650 const struct b43_nphy_chantabent_rev7 *tabent_r7,
651 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g)
652{
653 struct b43_phy *phy = &dev->phy;
654
655 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g);
656
657 switch (phy->radio_rev) {
658 case 0 ... 4:
659 case 6:
660 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
661 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
662 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
663 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
664 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
665 } else {
666 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
667 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
668 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
669 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
670 }
671 break;
672 /* TODO */
673 }
674
675 /* TODO */
676
677 usleep_range(50, 100);
678
679 /* VCO calibration */
680 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01);
681 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
682 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
683 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01);
684 usleep_range(300, 600);
685}
686
e90cf1c7
RM		 687/* Calibrate resistors in LPF of PLL?
688 * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal
689 */
572d37a4
RM		 690static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
691{
692 struct b43_phy *phy = &dev->phy;
693 u16 tmp;
694
695 if (phy->radio_rev == 5) {
696 b43_phy_mask(dev, 0x342, ~0x2);
697 udelay(10);
698 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
699 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
700 }
701
e90cf1c7 702 /* Enable */
572d37a4
RM		 703 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
704 udelay(10);
e90cf1c7
RM		 705
706 /* Start */
707 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2);
708 usleep_range(100, 200);
709
710 /* Stop */
711 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
712
713 /* Wait and check for result */
714 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
572d37a4
RM		 715 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
716 return 0;
717 }
572d37a4 718 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
e90cf1c7
RM		 719
720 /* Disable */
572d37a4
RM		 721 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
722
723 if (phy->radio_rev == 5) {
724 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
725 b43_radio_mask(dev, 0x1ca, ~0x2);
726 }
727 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
728 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
729 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
730 tmp << 2);
731 }
732
733 return tmp & 0x3e;
734}
735
e90cf1c7
RM		 736/* Calibrate the internal RC oscillator?
737 * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal
738 */
572d37a4
RM		 739static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
740{
741 struct b43_phy *phy = &dev->phy;
742 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
743 phy->radio_rev == 6);
744 u16 tmp;
745
e90cf1c7 746 /* Setup cal */
572d37a4
RM		 747 if (special) {
748 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
749 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
750 } else {
e90cf1c7 751 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61);
572d37a4
RM		 752 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
753 }
754 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
e90cf1c7
RM		 755
756 /* Start, wait, stop */
572d37a4 757 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7 758 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4
RM		 759 5000000))
760 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
e90cf1c7 761 usleep_range(35, 70);
572d37a4 762 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 763 usleep_range(70, 140);
764
765 /* Setup cal */
572d37a4
RM		 766 if (special) {
767 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
768 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
769 } else {
e90cf1c7 770 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69);
572d37a4
RM		 771 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
772 }
773 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
e90cf1c7
RM		 774
775 /* Start, wait, stop */
776 usleep_range(35, 70);
572d37a4 777 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7
RM		 778 usleep_range(70, 140);
779 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4 780 5000000))
6c187236 781 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
e90cf1c7 782 usleep_range(35, 70);
572d37a4 783 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 784 usleep_range(70, 140);
785
786 /* Setup cal */
572d37a4
RM		 787 if (special) {
788 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
789 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
790 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
791 } else {
e90cf1c7 792 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73);
572d37a4
RM		 793 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
794 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
795 }
e90cf1c7
RM		 796
797 /* Start, wait, stop */
798 usleep_range(35, 70);
572d37a4 799 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7
RM		 800 usleep_range(70, 140);
801 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4
RM		 802 5000000)) {
803 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
804 return 0;
805 }
806 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
e90cf1c7 807 usleep_range(35, 70);
572d37a4 808 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 809 usleep_range(70, 140);
810
811 if (special)
812 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1);
813 else
814 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1);
815
572d37a4
RM		 816 return tmp;
817}
818
819static void b43_radio_2057_init_pre(struct b43_wldev *dev)
820{
821 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
822 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
823 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
824 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
825 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
826}
827
828static void b43_radio_2057_init_post(struct b43_wldev *dev)
829{
830 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
831
832 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
833 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
834 mdelay(2);
835 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
836 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
837
90e569d1 838 if (dev->phy.do_full_init) {
572d37a4
RM		 839 b43_radio_2057_rcal(dev);
840 b43_radio_2057_rccal(dev);
841 }
842 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
572d37a4
RM		 843}
844
845/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
846static void b43_radio_2057_init(struct b43_wldev *dev)
847{
848 b43_radio_2057_init_pre(dev);
849 r2057_upload_inittabs(dev);
850 b43_radio_2057_init_post(dev);
851}
852
ab499217 853/**************************************************
884a5228 854 * Radio 0x2056
ab499217 855 **************************************************/
7955de0c 856
d4814e69
RM		 857static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
858 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 859{
d4814e69
RM		 860 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
861 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
862 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
863 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
864 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
865 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
866 e->radio_syn_pll_loopfilter1);
867 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
868 e->radio_syn_pll_loopfilter2);
869 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
870 e->radio_syn_pll_loopfilter3);
871 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
872 e->radio_syn_pll_loopfilter4);
873 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
874 e->radio_syn_pll_loopfilter5);
875 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
876 e->radio_syn_reserved_addr27);
877 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
878 e->radio_syn_reserved_addr28);
879 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
880 e->radio_syn_reserved_addr29);
881 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
882 e->radio_syn_logen_vcobuf1);
883 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
884 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
885 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
886
887 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
888 e->radio_rx0_lnaa_tune);
889 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
890 e->radio_rx0_lnag_tune);
891
892 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
893 e->radio_tx0_intpaa_boost_tune);
894 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
895 e->radio_tx0_intpag_boost_tune);
896 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
897 e->radio_tx0_pada_boost_tune);
898 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
899 e->radio_tx0_padg_boost_tune);
900 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
901 e->radio_tx0_pgaa_boost_tune);
902 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
903 e->radio_tx0_pgag_boost_tune);
904 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
905 e->radio_tx0_mixa_boost_tune);
906 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
907 e->radio_tx0_mixg_boost_tune);
908
909 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
910 e->radio_rx1_lnaa_tune);
911 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
912 e->radio_rx1_lnag_tune);
913
914 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
915 e->radio_tx1_intpaa_boost_tune);
916 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
917 e->radio_tx1_intpag_boost_tune);
918 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
919 e->radio_tx1_pada_boost_tune);
920 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
921 e->radio_tx1_padg_boost_tune);
922 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
923 e->radio_tx1_pgaa_boost_tune);
924 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
925 e->radio_tx1_pgag_boost_tune);
926 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
927 e->radio_tx1_mixa_boost_tune);
928 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
929 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 930}
931
d4814e69
RM		 932/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
933static void b43_radio_2056_setup(struct b43_wldev *dev,
934 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 935{
39e971ef 936 struct b43_phy *phy = &dev->phy;
0581483a 937 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 938 enum ieee80211_band band = b43_current_band(dev->wl);
939 u16 offset;
940 u8 i;
d3d178f0
RM		 941 u16 bias, cbias;
942 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
943 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
b88cdde9 944 bool is_pkg_fab_smic;
036cafe4 945
d4814e69 946 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 947
b88cdde9
RM		 948 is_pkg_fab_smic =
949 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
950 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
951 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
952 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
953
d4814e69 954 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 955 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
956
957 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
958 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
959 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
960 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
b88cdde9
RM		 961 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
962 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 963 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
964 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
965 } else {
966 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
967 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 968 }
53a6e234 969 }
b88cdde9
RM		 970 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
971 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
972 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
973 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
974 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
975 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
976 }
38646eba
RM		 977 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
978 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
979 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
980 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
981 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
982 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 983 }
53a6e234 984
38646eba
RM		 985 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
986 for (i = 0; i < 2; i++) {
987 offset = i ? B2056_TX1 : B2056_TX0;
988 if (dev->phy.rev >= 5) {
989 b43_radio_write(dev,
990 offset | B2056_TX_PADG_IDAC, 0xcc);
991
b88cdde9
RM		 992 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
993 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 994 bias = 0x40;
995 cbias = 0x45;
996 pag_boost = 0x5;
997 pgag_boost = 0x33;
998 mixg_boost = 0x55;
999 } else {
1000 bias = 0x25;
1001 cbias = 0x20;
b88cdde9
RM		 1002 if (is_pkg_fab_smic) {
1003 bias = 0x2a;
1004 cbias = 0x38;
1005 }
38646eba
RM		 1006 pag_boost = 0x4;
1007 pgag_boost = 0x03;
1008 mixg_boost = 0x65;
1009 }
1010 padg_boost = 0x77;
1011
1012 b43_radio_write(dev,
1013 offset | B2056_TX_INTPAG_IMAIN_STAT,
1014 bias);
1015 b43_radio_write(dev,
1016 offset | B2056_TX_INTPAG_IAUX_STAT,
1017 bias);
1018 b43_radio_write(dev,
1019 offset | B2056_TX_INTPAG_CASCBIAS,
1020 cbias);
1021 b43_radio_write(dev,
1022 offset | B2056_TX_INTPAG_BOOST_TUNE,
1023 pag_boost);
1024 b43_radio_write(dev,
1025 offset | B2056_TX_PGAG_BOOST_TUNE,
1026 pgag_boost);
1027 b43_radio_write(dev,
1028 offset | B2056_TX_PADG_BOOST_TUNE,
1029 padg_boost);
1030 b43_radio_write(dev,
1031 offset | B2056_TX_MIXG_BOOST_TUNE,
1032 mixg_boost);
1033 } else {
bee6d4b2 1034 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
38646eba
RM		 1035 b43_radio_write(dev,
1036 offset | B2056_TX_INTPAG_IMAIN_STAT,
1037 bias);
1038 b43_radio_write(dev,
1039 offset | B2056_TX_INTPAG_IAUX_STAT,
1040 bias);
1041 b43_radio_write(dev,
1042 offset | B2056_TX_INTPAG_CASCBIAS,
1043 0x30);
1044 }
1045 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
1046 }
1047 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
39e971ef 1048 u16 freq = phy->chandef->chan->center_freq;
d3d178f0
RM		 1049 if (freq < 5100) {
1050 paa_boost = 0xA;
1051 pada_boost = 0x77;
1052 pgaa_boost = 0xF;
1053 mixa_boost = 0xF;
1054 } else if (freq < 5340) {
1055 paa_boost = 0x8;
1056 pada_boost = 0x77;
1057 pgaa_boost = 0xFB;
1058 mixa_boost = 0xF;
1059 } else if (freq < 5650) {
1060 paa_boost = 0x0;
1061 pada_boost = 0x77;
1062 pgaa_boost = 0xB;
1063 mixa_boost = 0xF;
1064 } else {
1065 paa_boost = 0x0;
1066 pada_boost = 0x77;
1067 if (freq != 5825)
1068 pgaa_boost = -(freq - 18) / 36 + 168;
1069 else
1070 pgaa_boost = 6;
1071 mixa_boost = 0xF;
1072 }
1073
b88cdde9
RM		 1074 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
1075
d3d178f0
RM		 1076 for (i = 0; i < 2; i++) {
1077 offset = i ? B2056_TX1 : B2056_TX0;
1078
1079 b43_radio_write(dev,
1080 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
1081 b43_radio_write(dev,
1082 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
1083 b43_radio_write(dev,
1084 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
1085 b43_radio_write(dev,
1086 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
1087 b43_radio_write(dev,
1088 offset | B2056_TX_TXSPARE1, 0x30);
1089 b43_radio_write(dev,
1090 offset | B2056_TX_PA_SPARE2, 0xee);
1091 b43_radio_write(dev,
1092 offset | B2056_TX_PADA_CASCBIAS, 0x03);
1093 b43_radio_write(dev,
b88cdde9 1094 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
d3d178f0 1095 b43_radio_write(dev,
b88cdde9 1096 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
d3d178f0 1097 b43_radio_write(dev,
b88cdde9 1098 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
d3d178f0 1099 }
a2d9bc6f 1100 }
38646eba 1101
d4814e69
RM		 1102 udelay(50);
1103 /* VCO calibration */
1104 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
1105 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1106 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
1107 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1108 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
1109 udelay(300);
53a6e234
MB		 1110}
1111
d3d178f0
RM		 1112static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
1113{
1114 struct b43_phy *phy = &dev->phy;
1115 u16 mast2, tmp;
1116
1117 if (phy->rev != 3)
1118 return 0;
1119
1120 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
1121 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
1122
1123 udelay(10);
1124 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1125 udelay(10);
1126 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
1127
1128 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
1129 1000000)) {
1130 b43err(dev->wl, "Radio recalibration timeout\n");
1131 return 0;
1132 }
1133
1134 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1135 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1136 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1137
1138 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1139
1140 return tmp & 0x1f;
1141}
1142
ea7ee14b
RM		 1143static void b43_radio_init2056_pre(struct b43_wldev *dev)
1144{
1145 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1146 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1147 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1148 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1149 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1150 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1151 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1152 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1153 B43_NPHY_RFCTL_CMD_CHIP0PU);
1154}
1155
1156static void b43_radio_init2056_post(struct b43_wldev *dev)
1157{
1158 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1159 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1160 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1161 msleep(1);
1162 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1163 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1164 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
90e569d1 1165 if (dev->phy.do_full_init)
d3d178f0 1166 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 1167}
1168
d817f4e1
RM		 1169/*
1170 * Initialize a Broadcom 2056 N-radio
1171 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1172 */
1173static void b43_radio_init2056(struct b43_wldev *dev)
1174{
ea7ee14b
RM		 1175 b43_radio_init2056_pre(dev);
1176 b2056_upload_inittabs(dev, 0, 0);
1177 b43_radio_init2056_post(dev);
d817f4e1
RM		 1178}
1179
884a5228
RM		 1180/**************************************************
1181 * Radio 0x2055
1182 **************************************************/
1183
1184static void b43_chantab_radio_upload(struct b43_wldev *dev,
1185 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1186{
884a5228
RM		 1187 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1188 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1189 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1190 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1191 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 1192
884a5228
RM		 1193 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1194 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1195 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1196 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1197 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1198
884a5228
RM		 1199 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1200 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1201 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1202 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1203 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1204
884a5228
RM		 1205 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1206 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1207 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1208 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1209 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1210
884a5228
RM		 1211 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1212 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1213 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1214 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1215 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1216
884a5228
RM		 1217 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1218 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 1219}
1220
884a5228
RM		 1221/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1222static void b43_radio_2055_setup(struct b43_wldev *dev,
1223 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1224{
884a5228 1225 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 1226
884a5228
RM		 1227 b43_chantab_radio_upload(dev, e);
1228 udelay(50);
1229 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1230 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1231 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1232 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1233 udelay(300);
95b66bad
MB		 1234}
1235
884a5228 1236static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1237{
884a5228
RM		 1238 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1239 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1240 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1241 B43_NPHY_RFCTL_CMD_CHIP0PU |
1242 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1243 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1244 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1245}
1246
884a5228 1247static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1248{
1249 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1250 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1251 bool workaround = false;
2faa6b83 1252
884a5228
RM		 1253 if (sprom->revision < 4)
1254 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1255 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1256 && dev->dev->board_rev >= 0x41);
2faa6b83 1257 else
884a5228
RM		 1258 workaround =
1259 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1260
884a5228
RM		 1261 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1262 if (workaround) {
1263 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1264 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1265 }
1266 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1267 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1268 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1269 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1270 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1271 msleep(1);
1272 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1273 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1274 b43err(dev->wl, "radio post init timeout\n");
1275 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1276 b43_switch_channel(dev, dev->phy.channel);
1277 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1278 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1279 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1280 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1281 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1282 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1283 if (!nphy->gain_boost) {
1284 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1285 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1286 } else {
1287 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1288 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1289 }
1290 udelay(2);
2faa6b83
RM		 1291}
1292
884a5228
RM		 1293/*
1294 * Initialize a Broadcom 2055 N-radio
1295 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1296 */
1297static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1298{
884a5228
RM		 1299 b43_radio_init2055_pre(dev);
1300 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1301 /* Follow wl, not specs. Do not force uploading all regs */
1302 b2055_upload_inittab(dev, 0, 0);
a67162ab 1303 } else {
884a5228
RM		 1304 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1305 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1306 }
884a5228 1307 b43_radio_init2055_post(dev);
a67162ab
RM		 1308}
1309
8be89535
RM		 1310/**************************************************
1311 * Samples
1312 **************************************************/
026816fc 1313
8be89535
RM		 1314/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1315static int b43_nphy_load_samples(struct b43_wldev *dev,
1316 struct b43_c32 *samples, u16 len) {
1317 struct b43_phy_n *nphy = dev->phy.n;
1318 u16 i;
1319 u32 *data;
1320
1321 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1322 if (!data) {
1323 b43err(dev->wl, "allocation for samples loading failed\n");
1324 return -ENOMEM;
1325 }
1326 if (nphy->hang_avoid)
1327 b43_nphy_stay_in_carrier_search(dev, 1);
1328
1329 for (i = 0; i < len; i++) {
1330 data[i] = (samples[i].i & 0x3FF << 10);
1331 data[i] |= samples[i].q & 0x3FF;
1332 }
1333 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1334
1335 kfree(data);
1336 if (nphy->hang_avoid)
1337 b43_nphy_stay_in_carrier_search(dev, 0);
1338 return 0;
026816fc
RM		 1339}
1340
8be89535
RM		 1341/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1342static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1343 bool test)
026816fc 1344{
8be89535
RM		 1345 int i;
1346 u16 bw, len, rot, angle;
1347 struct b43_c32 *samples;
026816fc 1348
bee6d4b2 1349 bw = b43_is_40mhz(dev) ? 40 : 20;
8be89535 1350 len = bw << 3;
026816fc 1351
8be89535
RM		 1352 if (test) {
1353 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1354 bw = 82;
1355 else
1356 bw = 80;
026816fc 1357
bee6d4b2 1358 if (b43_is_40mhz(dev))
8be89535
RM		 1359 bw <<= 1;
1360
1361 len = bw << 1;
026816fc
RM		 1362 }
1363
8be89535
RM		 1364 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1365 if (!samples) {
1366 b43err(dev->wl, "allocation for samples generation failed\n");
1367 return 0;
1368 }
1369 rot = (((freq * 36) / bw) << 16) / 100;
1370 angle = 0;
026816fc 1371
8be89535
RM		 1372 for (i = 0; i < len; i++) {
1373 samples[i] = b43_cordic(angle);
1374 angle += rot;
1375 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1376 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1377 }
8be89535
RM		 1378
1379 i = b43_nphy_load_samples(dev, samples, len);
1380 kfree(samples);
1381 return (i < 0) ? 0 : len;
026816fc
RM		 1382}
1383
8be89535
RM		 1384/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1385static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
ed03033e
RM		 1386 u16 wait, bool iqmode, bool dac_test,
1387 bool modify_bbmult)
34a56f2c 1388{
8be89535 1389 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1390 int i;
8be89535
RM		 1391 u16 seq_mode;
1392 u32 tmp;
34a56f2c 1393
bc36e994 1394 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1395
8be89535
RM		 1396 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1397 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1398 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1399 }
34a56f2c 1400
ed03033e
RM		 1401 if (modify_bbmult) {
1402 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747;
1403 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1404 }
34a56f2c 1405
8be89535 1406 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1407
8be89535
RM		 1408 if (loops != 0xFFFF)
1409 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1410 else
1411 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1412
8be89535 1413 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1414
8be89535 1415 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1416
8be89535
RM		 1417 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1418 if (iqmode) {
1419 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1420 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1421 } else {
ed03033e
RM		 1422 tmp = dac_test ? 5 : 1;
1423 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp);
8be89535
RM		 1424 }
1425 for (i = 0; i < 100; i++) {
2c8ac7eb 1426 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1427 i = 0;
1428 break;
34a56f2c 1429 }
8be89535 1430 udelay(10);
34a56f2c 1431 }
8be89535
RM		 1432 if (i)
1433 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1434
8be89535 1435 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
bc36e994
RM		 1436
1437 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c
RM		 1438}
1439
4d9f46ba
RM		 1440/**************************************************
1441 * RSSI
1442 **************************************************/
1443
1444/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1445static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1446 s8 offset, u8 core,
1447 enum n_rail_type rail,
2a2d0589 1448 enum n_rssi_type rssi_type)
09146400 1449{
4d9f46ba
RM		 1450 u16 tmp;
1451 bool core1or5 = (core == 1) || (core == 5);
1452 bool core2or5 = (core == 2) || (core == 5);
09146400 1453
4d9f46ba
RM		 1454 offset = clamp_val(offset, -32, 31);
1455 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1456
e5ab1fd7 1457 switch (rssi_type) {
2a2d0589 1458 case N_RSSI_NB:
e5ab1fd7
RM		 1459 if (core1or5 && rail == N_RAIL_I)
1460 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1461 if (core1or5 && rail == N_RAIL_Q)
1462 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1463 if (core2or5 && rail == N_RAIL_I)
1464 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1465 if (core2or5 && rail == N_RAIL_Q)
1466 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1467 break;
2a2d0589 1468 case N_RSSI_W1:
e5ab1fd7
RM		 1469 if (core1or5 && rail == N_RAIL_I)
1470 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1471 if (core1or5 && rail == N_RAIL_Q)
1472 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1473 if (core2or5 && rail == N_RAIL_I)
1474 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1475 if (core2or5 && rail == N_RAIL_Q)
1476 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1477 break;
2a2d0589 1478 case N_RSSI_W2:
e5ab1fd7
RM		 1479 if (core1or5 && rail == N_RAIL_I)
1480 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1481 if (core1or5 && rail == N_RAIL_Q)
1482 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1483 if (core2or5 && rail == N_RAIL_I)
1484 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1485 if (core2or5 && rail == N_RAIL_Q)
1486 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1487 break;
2a2d0589 1488 case N_RSSI_TBD:
e5ab1fd7
RM		 1489 if (core1or5 && rail == N_RAIL_I)
1490 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1491 if (core1or5 && rail == N_RAIL_Q)
1492 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1493 if (core2or5 && rail == N_RAIL_I)
1494 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1495 if (core2or5 && rail == N_RAIL_Q)
1496 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1497 break;
2a2d0589 1498 case N_RSSI_IQ:
e5ab1fd7
RM		 1499 if (core1or5 && rail == N_RAIL_I)
1500 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1501 if (core1or5 && rail == N_RAIL_Q)
1502 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1503 if (core2or5 && rail == N_RAIL_I)
1504 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1505 if (core2or5 && rail == N_RAIL_Q)
1506 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1507 break;
2a2d0589 1508 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1509 if (core1or5)
1510 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1511 if (core2or5)
1512 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1513 break;
2a2d0589 1514 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1515 if (core1or5)
1516 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1517 if (core2or5)
1518 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1519 break;
1520 }
8987a9e9
RM		 1521}
1522
a3764ef7
RM		 1523static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1524 enum n_rssi_type rssi_type)
bbec398c 1525{
4d9f46ba
RM		 1526 u8 i;
1527 u16 reg, val;
bbec398c 1528
4d9f46ba
RM		 1529 if (code == 0) {
1530 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1531 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1532 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1533 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1534 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1535 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1536 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1537 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1538 } else {
1539 for (i = 0; i < 2; i++) {
1540 if ((code == 1 && i == 1) || (code == 2 && !i))
1541 continue;
bbec398c 1542
4d9f46ba
RM		 1543 reg = (i == 0) ?
1544 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1545 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1546
a3764ef7
RM		 1547 if (rssi_type == N_RSSI_W1 ||
1548 rssi_type == N_RSSI_W2 ||
1549 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1550 reg = (i == 0) ?
1551 B43_NPHY_AFECTL_C1 :
1552 B43_NPHY_AFECTL_C2;
1553 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1554
4d9f46ba
RM		 1555 reg = (i == 0) ?
1556 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1557 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1558 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1559
a3764ef7 1560 if (rssi_type == N_RSSI_W1)
4d9f46ba 1561 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1562 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1563 val = 16;
1564 else
1565 val = 32;
1566 b43_phy_set(dev, reg, val);
5c1a140a 1567
4d9f46ba
RM		 1568 reg = (i == 0) ?
1569 B43_NPHY_TXF_40CO_B1S0 :
1570 B43_NPHY_TXF_40CO_B32S1;
1571 b43_phy_set(dev, reg, 0x0020);
1572 } else {
a3764ef7 1573 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1574 val = 0x0100;
a3764ef7 1575 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1576 val = 0x0200;
1577 else
1578 val = 0x0300;
5c1a140a 1579
4d9f46ba
RM		 1580 reg = (i == 0) ?
1581 B43_NPHY_AFECTL_C1 :
1582 B43_NPHY_AFECTL_C2;
53ae8e8c 1583
4d9f46ba
RM		 1584 b43_phy_maskset(dev, reg, 0xFCFF, val);
1585 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1586
a3764ef7
RM		 1587 if (rssi_type != N_RSSI_IQ &&
1588 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1589 enum ieee80211_band band =
1590 b43_current_band(dev->wl);
53ae8e8c 1591
4d9f46ba
RM		 1592 if (b43_nphy_ipa(dev))
1593 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1594 else
1595 val = 0x11;
1596 reg = (i == 0) ? 0x2000 : 0x3000;
1597 reg |= B2055_PADDRV;
0c201cfb 1598 b43_radio_write(dev, reg, val);
53ae8e8c 1599
4d9f46ba
RM		 1600 reg = (i == 0) ?
1601 B43_NPHY_AFECTL_OVER1 :
1602 B43_NPHY_AFECTL_OVER;
1603 b43_phy_set(dev, reg, 0x0200);
1604 }
1605 }
1606 }
53ae8e8c 1607 }
53ae8e8c
RM		 1608}
1609
a3764ef7
RM		 1610static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1611 enum n_rssi_type rssi_type)
9442e5b5 1612{
4d9f46ba 1613 u16 val;
a3764ef7 1614 bool rssi_w1_w2_nb = false;
9442e5b5 1615
a3764ef7
RM		 1616 switch (rssi_type) {
1617 case N_RSSI_W1:
1618 case N_RSSI_W2:
1619 case N_RSSI_NB:
4d9f46ba 1620 val = 0;
a3764ef7
RM		 1621 rssi_w1_w2_nb = true;
1622 break;
1623 case N_RSSI_TBD:
4d9f46ba 1624 val = 1;
a3764ef7
RM		 1625 break;
1626 case N_RSSI_IQ:
4d9f46ba 1627 val = 2;
a3764ef7
RM		 1628 break;
1629 default:
4d9f46ba 1630 val = 3;
a3764ef7 1631 }
9442e5b5 1632
4d9f46ba
RM		 1633 val = (val << 12) | (val << 14);
1634 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1635 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1636
a3764ef7 1637 if (rssi_w1_w2_nb) {
4d9f46ba 1638 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1639 (rssi_type + 1) << 4);
4d9f46ba 1640 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1641 (rssi_type + 1) << 4);
9442e5b5
RM		 1642 }
1643
4d9f46ba
RM		 1644 if (code == 0) {
1645 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1646 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1647 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1648 ~(B43_NPHY_RFCTL_CMD_RXEN |
1649 B43_NPHY_RFCTL_CMD_CORESEL));
1650 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1651 ~(0x1 << 12 |
1652 0x1 << 5 |
1653 0x1 << 1 |
1654 0x1));
1655 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1656 ~B43_NPHY_RFCTL_CMD_START);
1657 udelay(20);
1658 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1659 }
1660 } else {
1661 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1662 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1663 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1664 ~(B43_NPHY_RFCTL_CMD_RXEN |
1665 B43_NPHY_RFCTL_CMD_CORESEL),
1666 (B43_NPHY_RFCTL_CMD_RXEN |
1667 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1668 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1669 (0x1 << 12 |
1670 0x1 << 5 |
1671 0x1 << 1 |
1672 0x1));
1673 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1674 B43_NPHY_RFCTL_CMD_START);
1675 udelay(20);
1676 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1677 }
9442e5b5 1678 }
9442e5b5
RM		 1679}
1680
4d9f46ba 1681/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1682static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1683 enum n_rssi_type type)
d24019ad 1684{
4d9f46ba
RM		 1685 if (dev->phy.rev >= 3)
1686 b43_nphy_rev3_rssi_select(dev, code, type);
1687 else
1688 b43_nphy_rev2_rssi_select(dev, code, type);
1689}
d24019ad 1690
5ecab603 1691/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1692static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1693 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1694{
1695 int i;
d24019ad 1696 for (i = 0; i < 2; i++) {
a3764ef7 1697 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1698 if (i == 0) {
1699 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1700 0xFC, buf[0]);
1701 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1702 0xFC, buf[1]);
1703 } else {
1704 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1705 0xFC, buf[2 * i]);
1706 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1707 0xFC, buf[2 * i + 1]);
1708 }
d24019ad 1709 } else {
5ecab603
RM		 1710 if (i == 0)
1711 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1712 0xF3, buf[0] << 2);
1713 else
1714 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1715 0xF3, buf[2 * i + 1] << 2);
d24019ad 1716 }
d24019ad 1717 }
d24019ad
RM		 1718}
1719
5ecab603 1720/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1721static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1722 s32 *buf, u8 nsamp)
ef5127a4 1723{
5ecab603
RM		 1724 int i;
1725 int out;
1726 u16 save_regs_phy[9];
1727 u16 s[2];
ef5127a4
RM		 1728
1729 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1730 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1731 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1732 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1733 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1734 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1735 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1736 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1737 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1738 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1739 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1740 save_regs_phy[8] = 0;
ef5127a4 1741 } else {
5ecab603
RM		 1742 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1743 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1744 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1745 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1746 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1747 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1748 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1749 save_regs_phy[7] = 0;
1750 save_regs_phy[8] = 0;
1751 }
ef5127a4 1752
a3764ef7 1753 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1754
5ecab603
RM		 1755 if (dev->phy.rev < 2) {
1756 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1757 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1758 }
ef5127a4 1759
5ecab603
RM		 1760 for (i = 0; i < 4; i++)
1761 buf[i] = 0;
1762
1763 for (i = 0; i < nsamp; i++) {
1764 if (dev->phy.rev < 2) {
1765 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1766 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1767 } else {
5ecab603
RM		 1768 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1769 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1770 }
1771
5ecab603
RM		 1772 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1773 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1774 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1775 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1776 }
1777 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1778 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1779
5ecab603
RM		 1780 if (dev->phy.rev < 2)
1781 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1782
5ecab603 1783 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1784 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1785 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1786 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1787 save_regs_phy[2]);
5ecab603 1788 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1789 save_regs_phy[3]);
5ecab603
RM		 1790 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1791 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1792 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1793 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1794 } else {
1795 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1796 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1797 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1798 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1799 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1800 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1801 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1802 }
ef5127a4 1803
5ecab603
RM		 1804 return out;
1805}
ef5127a4 1806
e0c9a021
RM		 1807/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1808static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1809{
39e971ef 1810 struct b43_phy *phy = &dev->phy;
e0c9a021
RM		 1811 struct b43_phy_n *nphy = dev->phy.n;
1812
1813 u16 saved_regs_phy_rfctl[2];
97e2a1a1
RM		 1814 u16 saved_regs_phy[22];
1815 u16 regs_to_store_rev3[] = {
e0c9a021
RM		 1816 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1817 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1818 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1819 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1820 B43_NPHY_RFCTL_CMD,
1821 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1822 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1823 };
97e2a1a1
RM		 1824 u16 regs_to_store_rev7[] = {
1825 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1826 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1827 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1828 0x342, 0x343, 0x346, 0x347,
1829 0x2ff,
1830 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1831 B43_NPHY_RFCTL_CMD,
1832 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1833 0x340, 0x341, 0x344, 0x345,
1834 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1835 };
1836 u16 *regs_to_store;
1837 int regs_amount;
e0c9a021
RM		 1838
1839 u16 class;
1840
1841 u16 clip_state[2];
1842 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1843
1844 u8 vcm_final = 0;
2e1253d6 1845 s32 offset[4];
e0c9a021
RM		 1846 s32 results[8][4] = { };
1847 s32 results_min[4] = { };
1848 s32 poll_results[4] = { };
1849
1850 u16 *rssical_radio_regs = NULL;
1851 u16 *rssical_phy_regs = NULL;
1852
1853 u16 r; /* routing */
1854 u8 rx_core_state;
37859a75 1855 int core, i, j, vcm;
e0c9a021 1856
97e2a1a1
RM		 1857 if (dev->phy.rev >= 7) {
1858 regs_to_store = regs_to_store_rev7;
1859 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1860 } else {
1861 regs_to_store = regs_to_store_rev3;
1862 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1863 }
1864 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1865
e0c9a021
RM		 1866 class = b43_nphy_classifier(dev, 0, 0);
1867 b43_nphy_classifier(dev, 7, 4);
1868 b43_nphy_read_clip_detection(dev, clip_state);
1869 b43_nphy_write_clip_detection(dev, clip_off);
1870
1871 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1872 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
97e2a1a1 1873 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1874 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1875
89e43dad
RM		 1876 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1877 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
97e2a1a1
RM		 1878
1879 if (dev->phy.rev >= 7) {
1880 /* TODO */
1881 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1882 } else {
1883 }
e0c9a021 1884 } else {
97e2a1a1
RM		 1885 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1886 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1887 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1888 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1889 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1890 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1891 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1892 } else {
1893 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1894 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1895 }
e0c9a021
RM		 1896 }
1897
1898 rx_core_state = b43_nphy_get_rx_core_state(dev);
1899 for (core = 0; core < 2; core++) {
1900 if (!(rx_core_state & (1 << core)))
1901 continue;
1902 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1903 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1904 N_RSSI_NB);
1905 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1906 N_RSSI_NB);
37859a75
RM		 1907
1908 /* Grab RSSI results for every possible VCM */
1909 for (vcm = 0; vcm < 8; vcm++) {
97e2a1a1
RM		 1910 if (dev->phy.rev >= 7)
1911 ;
1912 else
1913 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1914 0xE3, vcm << 2);
a3764ef7 1915 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1916 }
37859a75
RM		 1917
1918 /* Find out which VCM got the best results */
cddec902 1919 for (i = 0; i < 4; i += 2) {
37859a75 1920 s32 currd;
e67dd874 1921 s32 mind = 0x100000;
e0c9a021
RM		 1922 s32 minpoll = 249;
1923 u8 minvcm = 0;
1924 if (2 * core != i)
1925 continue;
37859a75
RM		 1926 for (vcm = 0; vcm < 8; vcm++) {
1927 currd = results[vcm][i] * results[vcm][i] +
1928 results[vcm][i + 1] * results[vcm][i];
1929 if (currd < mind) {
1930 mind = currd;
1931 minvcm = vcm;
e0c9a021 1932 }
37859a75
RM		 1933 if (results[vcm][i] < minpoll)
1934 minpoll = results[vcm][i];
e0c9a021
RM		 1935 }
1936 vcm_final = minvcm;
1937 results_min[i] = minpoll;
1938 }
37859a75
RM		 1939
1940 /* Select the best VCM */
97e2a1a1
RM		 1941 if (dev->phy.rev >= 7)
1942 ;
1943 else
1944 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1945 0xE3, vcm_final << 2);
37859a75 1946
e0c9a021
RM		 1947 for (i = 0; i < 4; i++) {
1948 if (core != i / 2)
1949 continue;
1950 offset[i] = -results[vcm_final][i];
1951 if (offset[i] < 0)
1952 offset[i] = -((abs(offset[i]) + 4) / 8);
1953 else
1954 offset[i] = (offset[i] + 4) / 8;
1955 if (results_min[i] == 248)
1956 offset[i] = -32;
1957 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1958 (i / 2 == 0) ? 1 : 2,
6aa38725 1959 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1960 N_RSSI_NB);
e0c9a021
RM		 1961 }
1962 }
37859a75 1963
e0c9a021
RM		 1964 for (core = 0; core < 2; core++) {
1965 if (!(rx_core_state & (1 << core)))
1966 continue;
1967 for (i = 0; i < 2; i++) {
6aa38725
RM		 1968 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1969 N_RAIL_I, i);
1970 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1971 N_RAIL_Q, i);
e0c9a021
RM		 1972 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1973 for (j = 0; j < 4; j++) {
cddec902 1974 if (j / 2 == core) {
e0c9a021 1975 offset[j] = 232 - poll_results[j];
cddec902
RM		 1976 if (offset[j] < 0)
1977 offset[j] = -(abs(offset[j] + 4) / 8);
1978 else
1979 offset[j] = (offset[j] + 4) / 8;
1980 b43_nphy_scale_offset_rssi(dev, 0,
1981 offset[2 * core], core + 1, j % 2, i);
1982 }
e0c9a021
RM		 1983 }
1984 }
1985 }
1986
1987 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1988 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1989
1990 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1991
1992 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1993 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1994 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1995
1996 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1997 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
bc36e994 1998 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
e0c9a021 1999
97e2a1a1 2000 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 2001 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
2002
2003 /* Store for future configuration */
2004 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2005 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2006 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2007 } else {
2008 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2009 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2010 }
9a98979e
RM		 2011 if (dev->phy.rev >= 7) {
2012 } else {
2013 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
2014 B2056_RX_RSSI_MISC);
2015 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
2016 B2056_RX_RSSI_MISC);
2017 }
e0c9a021
RM		 2018 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
2019 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
2020 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
2021 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
2022 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
2023 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
2024 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
2025 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
2026 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
2027 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
2028 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
2029 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
2030
2031 /* Remember for which channel we store configuration */
2032 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
39e971ef 2033 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
e0c9a021 2034 else
39e971ef 2035 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
e0c9a021
RM		 2036
2037 /* End of calibration, restore configuration */
2038 b43_nphy_classifier(dev, 7, class);
2039 b43_nphy_write_clip_detection(dev, clip_state);
2040}
2041
5ecab603 2042/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 2043static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 2044{
37859a75 2045 int i, j, vcm;
5ecab603
RM		 2046 u8 state[4];
2047 u8 code, val;
2048 u16 class, override;
2049 u8 regs_save_radio[2];
2050 u16 regs_save_phy[2];
2051
2e1253d6 2052 s32 offset[4];
5ecab603
RM		 2053 u8 core;
2054 u8 rail;
2055
2056 u16 clip_state[2];
2057 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2058 s32 results_min[4] = { };
2059 u8 vcm_final[4] = { };
2060 s32 results[4][4] = { };
2061 s32 miniq[4][2] = { };
2062
a3764ef7 2063 if (type == N_RSSI_NB) {
5ecab603
RM		 2064 code = 0;
2065 val = 6;
a3764ef7 2066 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 2067 code = 25;
2068 val = 4;
2069 } else {
2070 B43_WARN_ON(1);
2071 return;
2072 }
2073
2074 class = b43_nphy_classifier(dev, 0, 0);
2075 b43_nphy_classifier(dev, 7, 4);
2076 b43_nphy_read_clip_detection(dev, clip_state);
2077 b43_nphy_write_clip_detection(dev, clip_off);
2078
2079 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2080 override = 0x140;
2081 else
2082 override = 0x110;
2083
2084 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 2085 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 2086 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 2087 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 2088
2089 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 2090 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 2091 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 2092 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 2093
0c201cfb
RM		 2094 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2095 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 2096 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2097 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 2098 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
2099 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 2100
2101 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 2102 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
2103 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 2104
37859a75 2105 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 2106 u8 tmp[4];
2107 for (j = 0; j < 4; j++)
37859a75 2108 tmp[j] = vcm;
a3764ef7 2109 if (type != N_RSSI_W2)
5ecab603 2110 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 2111 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 2112 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 2113 for (j = 0; j < 2; j++)
37859a75
RM		 2114 miniq[vcm][j] = min(results[vcm][2 * j],
2115 results[vcm][2 * j + 1]);
5ecab603
RM		 2116 }
2117
2118 for (i = 0; i < 4; i++) {
e67dd874 2119 s32 mind = 0x100000;
5ecab603
RM		 2120 u8 minvcm = 0;
2121 s32 minpoll = 249;
37859a75
RM		 2122 s32 currd;
2123 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 2124 if (type == N_RSSI_NB)
542e15f3 2125 currd = abs(results[vcm][i] - code * 8);
5ecab603 2126 else
37859a75 2127 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 2128
37859a75
RM		 2129 if (currd < mind) {
2130 mind = currd;
2131 minvcm = vcm;
5ecab603
RM		 2132 }
2133
37859a75
RM		 2134 if (results[vcm][i] < minpoll)
2135 minpoll = results[vcm][i];
8e60b044 2136 }
5ecab603
RM		 2137 results_min[i] = minpoll;
2138 vcm_final[i] = minvcm;
2139 }
ef5127a4 2140
a3764ef7 2141 if (type != N_RSSI_W2)
5ecab603 2142 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 2143
5ecab603
RM		 2144 for (i = 0; i < 4; i++) {
2145 offset[i] = (code * 8) - results[vcm_final[i]][i];
2146
2147 if (offset[i] < 0)
2148 offset[i] = -((abs(offset[i]) + 4) / 8);
2149 else
2150 offset[i] = (offset[i] + 4) / 8;
2151
2152 if (results_min[i] == 248)
2153 offset[i] = code - 32;
2154
2155 core = (i / 2) ? 2 : 1;
6aa38725 2156 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 2157
2158 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2159 type);
2160 }
2161
2162 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2163 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2164
2165 switch (state[2]) {
2166 case 1:
a3764ef7 2167 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 2168 break;
2169 case 4:
a3764ef7 2170 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 2171 break;
2172 case 2:
a3764ef7 2173 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2174 break;
2175 default:
a3764ef7 2176 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2177 break;
2178 }
2179
2180 switch (state[3]) {
2181 case 1:
a3764ef7 2182 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 2183 break;
2184 case 4:
a3764ef7 2185 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 2186 break;
2187 default:
a3764ef7 2188 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 2189 break;
2190 }
2191
2192 b43_nphy_rssi_select(dev, 0, type);
2193
2194 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 2195 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 2196 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 2197 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 2198
2199 b43_nphy_classifier(dev, 7, class);
2200 b43_nphy_write_clip_detection(dev, clip_state);
2201 /* Specs don't say about reset here, but it makes wl and b43 dumps
2202 identical, it really seems wl performs this */
2203 b43_nphy_reset_cca(dev);
2204}
2205
5ecab603
RM		 2206/*
2207 * RSSI Calibration
2208 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2209 */
2210static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2211{
2212 if (dev->phy.rev >= 3) {
2213 b43_nphy_rev3_rssi_cal(dev);
2214 } else {
2a2d0589
RM		 2215 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2216 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2217 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 2218 }
2219}
2220
64712095
RM		 2221/**************************************************
2222 * Workarounds
2223 **************************************************/
2224
2225static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2226{
2227 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2228
2229 bool ghz5;
2230 bool ext_lna;
2231 u16 rssi_gain;
2232 struct nphy_gain_ctl_workaround_entry *e;
2233 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2234 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2235
2236 /* Prepare values */
2237 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2238 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 2239 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2240 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 2241 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2242 if (ghz5 && dev->phy.rev >= 5)
2243 rssi_gain = 0x90;
2244 else
2245 rssi_gain = 0x50;
2246
2247 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2248
2249 /* Set Clip 2 detect */
04519dc6
RM		 2250 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2251 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 2252
2253 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2254 0x17);
2255 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2256 0x17);
2257 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2258 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2259 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2260 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2261 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2262 rssi_gain);
2263 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2264 rssi_gain);
2265 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2266 0x17);
2267 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2268 0x17);
2269 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2270 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2271
2272 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2273 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2274 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2275 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2276 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2277 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2278 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2279 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2280 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2281 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2282 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2283 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2284
04519dc6
RM		 2285 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2286 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2287
64712095
RM		 2288 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2289 e->rfseq_init);
64712095 2290
04519dc6
RM		 2291 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2292 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2293 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2294 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2295 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2296 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2297
2298 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2299 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2300 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2301 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2302 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2303 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2304 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2305 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2306 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2307 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2308}
2309
2310static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2311{
2312 struct b43_phy_n *nphy = dev->phy.n;
2313
2314 u8 i, j;
2315 u8 code;
2316 u16 tmp;
2317 u8 rfseq_events[3] = { 6, 8, 7 };
2318 u8 rfseq_delays[3] = { 10, 30, 1 };
2319
2320 /* Set Clip 2 detect */
2321 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2322 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2323
2324 /* Set narrowband clip threshold */
2325 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2326 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2327
bee6d4b2 2328 if (!b43_is_40mhz(dev)) {
64712095
RM		 2329 /* Set dwell lengths */
2330 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2331 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2332 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2333 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2334 }
2335
2336 /* Set wideband clip 2 threshold */
2337 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2338 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2339 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2340 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2341
bee6d4b2 2342 if (!b43_is_40mhz(dev)) {
64712095
RM		 2343 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2344 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2345 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2346 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2347 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2348 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2349 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2350 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2351 }
2352
2353 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2354
2355 if (nphy->gain_boost) {
2356 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
bee6d4b2 2357 b43_is_40mhz(dev))
64712095
RM		 2358 code = 4;
2359 else
2360 code = 5;
2361 } else {
bee6d4b2 2362 code = b43_is_40mhz(dev) ? 6 : 7;
64712095
RM		 2363 }
2364
2365 /* Set HPVGA2 index */
2366 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2367 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2368 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2369 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2370
2371 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2372 /* specs say about 2 loops, but wl does 4 */
2373 for (i = 0; i < 4; i++)
2374 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2375
2376 b43_nphy_adjust_lna_gain_table(dev);
2377
2378 if (nphy->elna_gain_config) {
2379 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2380 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2381 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2382 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2383 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2384
2385 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2386 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2387 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2388 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2389 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2390
2391 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2392 /* specs say about 2 loops, but wl does 4 */
2393 for (i = 0; i < 4; i++)
2394 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2395 (code << 8 | 0x74));
2396 }
2397
2398 if (dev->phy.rev == 2) {
2399 for (i = 0; i < 4; i++) {
2400 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2401 (0x0400 * i) + 0x0020);
2402 for (j = 0; j < 21; j++) {
2403 tmp = j * (i < 2 ? 3 : 1);
2404 b43_phy_write(dev,
2405 B43_NPHY_TABLE_DATALO, tmp);
2406 }
2407 }
ef5127a4 2408 }
64712095
RM		 2409
2410 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2411 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2412 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2413 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2414
2415 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2416 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2417}
2418
2419/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2420static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2421{
d11d354b
RM		 2422 if (dev->phy.rev >= 7)
2423 ; /* TODO */
2424 else if (dev->phy.rev >= 3)
64712095
RM		 2425 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2426 else
2427 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2428}
2429
d11d354b
RM		 2430/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2431static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2432{
2433 if (!offset)
bee6d4b2 2434 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
d11d354b
RM		 2435 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2436}
2437
2438static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2439{
2440 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2441 struct b43_phy *phy = &dev->phy;
2442
2443 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2444 0x1F };
2445 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2446
2447 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2448 u8 ntab7_138_146[] = { 0x11, 0x11 };
2449 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2450
2451 u16 lpf_20, lpf_40, lpf_11b;
2452 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2453 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2454 bool rccal_ovrd = false;
2455
2456 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2457 u16 bias, conv, filt;
2458
2459 u32 tmp32;
2460 u8 core;
2461
2462 if (phy->rev == 7) {
2463 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2464 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2465 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2466 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2467 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2468 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2469 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2470 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2471 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2472 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2473 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2474 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2475 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2476 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2477 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2478 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2479 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2480 }
2481 if (phy->rev <= 8) {
04519dc6
RM		 2482 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2483 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2484 }
2485 if (phy->rev >= 8)
2486 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2487
2488 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2489 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2490 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2491 tmp32 &= 0xffffff;
2492 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2493 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2494 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2495
2496 if (b43_nphy_ipa(dev))
2497 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2498 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2499
04519dc6
RM		 2500 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2501 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2502
2503 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2504 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2505 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2506 if (b43_nphy_ipa(dev)) {
bee6d4b2 2507 if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
d11d354b
RM		 2508 phy->radio_rev == 7 || phy->radio_rev == 8) {
2509 bcap_val = b43_radio_read(dev, 0x16b);
2510 scap_val = b43_radio_read(dev, 0x16a);
2511 scap_val_11b = scap_val;
2512 bcap_val_11b = bcap_val;
bee6d4b2 2513 if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
d11d354b
RM		 2514 scap_val_11n_20 = scap_val;
2515 bcap_val_11n_20 = bcap_val;
2516 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2517 rccal_ovrd = true;
2518 } else { /* Rev 7/8 */
2519 lpf_20 = 4;
2520 lpf_11b = 1;
2521 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2522 scap_val_11n_20 = 0xc;
2523 bcap_val_11n_20 = 0xc;
2524 scap_val_11n_40 = 0xa;
2525 bcap_val_11n_40 = 0xa;
2526 } else {
2527 scap_val_11n_20 = 0x14;
2528 bcap_val_11n_20 = 0x14;
2529 scap_val_11n_40 = 0xf;
2530 bcap_val_11n_40 = 0xf;
2531 }
2532 rccal_ovrd = true;
2533 }
2534 }
2535 } else {
2536 if (phy->radio_rev == 5) {
2537 lpf_20 = 1;
2538 lpf_40 = 3;
2539 bcap_val = b43_radio_read(dev, 0x16b);
2540 scap_val = b43_radio_read(dev, 0x16a);
2541 scap_val_11b = scap_val;
2542 bcap_val_11b = bcap_val;
2543 scap_val_11n_20 = 0x11;
2544 scap_val_11n_40 = 0x11;
2545 bcap_val_11n_20 = 0x13;
2546 bcap_val_11n_40 = 0x13;
2547 rccal_ovrd = true;
2548 }
2549 }
2550 if (rccal_ovrd) {
2551 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2552 (scap_val_11b << 3) |
2553 lpf_11b;
2554 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2555 (scap_val_11n_20 << 3) |
2556 lpf_20;
2557 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2558 (scap_val_11n_40 << 3) |
2559 lpf_40;
2560 for (core = 0; core < 2; core++) {
2561 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2562 rx2tx_lut_20_11b);
2563 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2564 rx2tx_lut_20_11n);
2565 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2566 rx2tx_lut_20_11n);
2567 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2568 rx2tx_lut_40_11n);
2569 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2570 rx2tx_lut_40_11n);
2571 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2572 rx2tx_lut_40_11n);
2573 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2574 rx2tx_lut_40_11n);
2575 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2576 rx2tx_lut_40_11n);
2577 }
78ae7532 2578 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2579 }
2580 b43_phy_write(dev, 0x32F, 0x3);
2581 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2582 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2583
2584 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2585 if (sprom->revision &&
2586 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2587 b43_radio_write(dev, 0x5, 0x05);
2588 b43_radio_write(dev, 0x6, 0x30);
2589 b43_radio_write(dev, 0x7, 0x00);
2590 b43_radio_set(dev, 0x4f, 0x1);
2591 b43_radio_set(dev, 0xd4, 0x1);
2592 bias = 0x1f;
2593 conv = 0x6f;
2594 filt = 0xaa;
2595 } else {
2596 bias = 0x2b;
2597 conv = 0x7f;
2598 filt = 0xee;
2599 }
2600 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2601 for (core = 0; core < 2; core++) {
2602 if (core == 0) {
2603 b43_radio_write(dev, 0x5F, bias);
2604 b43_radio_write(dev, 0x64, conv);
2605 b43_radio_write(dev, 0x66, filt);
2606 } else {
2607 b43_radio_write(dev, 0xE8, bias);
2608 b43_radio_write(dev, 0xE9, conv);
2609 b43_radio_write(dev, 0xEB, filt);
2610 }
2611 }
2612 }
2613 }
2614
2615 if (b43_nphy_ipa(dev)) {
2616 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2617 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2618 phy->radio_rev == 6) {
2619 for (core = 0; core < 2; core++) {
2620 if (core == 0)
2621 b43_radio_write(dev, 0x51,
2622 0x7f);
2623 else
2624 b43_radio_write(dev, 0xd6,
2625 0x7f);
2626 }
2627 }
2628 if (phy->radio_rev == 3) {
2629 for (core = 0; core < 2; core++) {
2630 if (core == 0) {
2631 b43_radio_write(dev, 0x64,
2632 0x13);
2633 b43_radio_write(dev, 0x5F,
2634 0x1F);
2635 b43_radio_write(dev, 0x66,
2636 0xEE);
2637 b43_radio_write(dev, 0x59,
2638 0x8A);
2639 b43_radio_write(dev, 0x80,
2640 0x3E);
2641 } else {
2642 b43_radio_write(dev, 0x69,
2643 0x13);
2644 b43_radio_write(dev, 0xE8,
2645 0x1F);
2646 b43_radio_write(dev, 0xEB,
2647 0xEE);
2648 b43_radio_write(dev, 0xDE,
2649 0x8A);
2650 b43_radio_write(dev, 0x105,
2651 0x3E);
2652 }
2653 }
2654 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
bee6d4b2 2655 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2656 b43_radio_write(dev, 0x5F, 0x14);
2657 b43_radio_write(dev, 0xE8, 0x12);
2658 } else {
2659 b43_radio_write(dev, 0x5F, 0x16);
2660 b43_radio_write(dev, 0xE8, 0x16);
2661 }
2662 }
2663 } else {
39e971ef 2664 u16 freq = phy->chandef->chan->center_freq;
d11d354b
RM		 2665 if ((freq >= 5180 && freq <= 5230) ||
2666 (freq >= 5745 && freq <= 5805)) {
2667 b43_radio_write(dev, 0x7D, 0xFF);
2668 b43_radio_write(dev, 0xFE, 0xFF);
2669 }
2670 }
2671 } else {
2672 if (phy->radio_rev != 5) {
2673 for (core = 0; core < 2; core++) {
2674 if (core == 0) {
2675 b43_radio_write(dev, 0x5c, 0x61);
2676 b43_radio_write(dev, 0x51, 0x70);
2677 } else {
2678 b43_radio_write(dev, 0xe1, 0x61);
2679 b43_radio_write(dev, 0xd6, 0x70);
2680 }
2681 }
2682 }
2683 }
2684
2685 if (phy->radio_rev == 4) {
2686 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2687 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2688 for (core = 0; core < 2; core++) {
2689 if (core == 0) {
2690 b43_radio_write(dev, 0x1a1, 0x00);
2691 b43_radio_write(dev, 0x1a2, 0x3f);
2692 b43_radio_write(dev, 0x1a6, 0x3f);
2693 } else {
2694 b43_radio_write(dev, 0x1a7, 0x00);
2695 b43_radio_write(dev, 0x1ab, 0x3f);
2696 b43_radio_write(dev, 0x1ac, 0x3f);
2697 }
2698 }
2699 } else {
2700 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2701 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2702 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2703 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2704
2705 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2706 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2707 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2708 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2709 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2710 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2711
2712 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2713 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2714 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2715 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2716 }
2717
2718 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2719
2720 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2721 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2722 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2723 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2724 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2725 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2726 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2727
bee6d4b2 2728 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2729 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2730 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2731 } else {
2732 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2733 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2734 }
2735
2736 b43_nphy_gain_ctl_workarounds(dev);
2737
2738 /* TODO
2739 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2740 aux_adc_vmid_rev7_core0);
2741 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2742 aux_adc_vmid_rev7_core1);
2743 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2744 aux_adc_gain_rev7);
2745 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2746 aux_adc_gain_rev7);
2747 */
2748}
2749
73d07a39 2750static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2751{
0eff8fcd 2752 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2753 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2754
0eff8fcd 2755 /* TX to RX */
c378bb97
RM		 2756 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2757 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 2758 /* RX to TX */
2759 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2760 0x1F };
2761 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2762 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2763 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2764
c378bb97
RM		 2765 u16 vmids[5][4] = {
2766 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2767 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2768 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2769 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2770 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2771 };
2772 u16 gains[5][4] = {
2773 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2774 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2775 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2776 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2777 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2778 };
2779 u16 *vmid, *gain;
2780
2781 u8 pdet_range;
ba9a6214
RM		 2782 u16 tmp16;
2783 u32 tmp32;
2784
04519dc6
RM		 2785 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2786 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2787
73d07a39
RM		 2788 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2789 tmp32 &= 0xffffff;
2790 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2791
73d07a39
RM		 2792 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2793 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2794 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2795 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2796 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2797 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2798
04519dc6
RM		 2799 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2800 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2801
0eff8fcd 2802 /* TX to RX */
c56da252
RM		 2803 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2804 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2805
2806 /* RX to TX */
2807 if (b43_nphy_ipa(dev))
c56da252
RM		 2808 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2809 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2810 if (nphy->hw_phyrxchain != 3 &&
2811 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2812 if (b43_nphy_ipa(dev)) {
2813 rx2tx_delays[5] = 59;
2814 rx2tx_delays[6] = 1;
2815 rx2tx_events[7] = 0x1F;
2816 }
fa0f2b38 2817 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2818 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2819 }
ba9a6214 2820
73d07a39
RM		 2821 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2822 0x2 : 0x9C40;
2823 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2824
04519dc6 2825 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2826
bee6d4b2 2827 if (!b43_is_40mhz(dev)) {
fa0f2b38
RM		 2828 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2829 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2830 } else {
2831 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2832 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2833 }
ba9a6214 2834
3ccd0957 2835 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2836
c56da252
RM		 2837 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2838 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2839
c378bb97
RM		 2840 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2841 pdet_range = sprom->fem.ghz2.pdet_range;
2842 else
2843 pdet_range = sprom->fem.ghz5.pdet_range;
2844 vmid = vmids[min_t(u16, pdet_range, 4)];
2845 gain = gains[min_t(u16, pdet_range, 4)];
2846 switch (pdet_range) {
2847 case 3:
2848 if (!(dev->phy.rev >= 4 &&
2849 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2850 break;
2851 /* FALL THROUGH */
2852 case 0:
2853 case 1:
2854 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2855 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2856 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2857 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2858 break;
2859 case 2:
2860 if (dev->phy.rev >= 6) {
2861 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2862 vmid[3] = 0x94;
2863 else
2864 vmid[3] = 0x8e;
2865 gain[3] = 3;
2866 } else if (dev->phy.rev == 5) {
2867 vmid[3] = 0x84;
2868 gain[3] = 2;
2869 }
2870 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2871 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2872 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2873 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2874 break;
2875 case 4:
2876 case 5:
2877 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2878 if (pdet_range == 4) {
2879 vmid[3] = 0x8e;
2880 tmp16 = 0x96;
2881 gain[3] = 0x2;
2882 } else {
2883 vmid[3] = 0x89;
2884 tmp16 = 0x89;
2885 gain[3] = 0;
2886 }
2887 } else {
2888 if (pdet_range == 4) {
2889 vmid[3] = 0x89;
2890 tmp16 = 0x8b;
2891 gain[3] = 0x2;
2892 } else {
2893 vmid[3] = 0x74;
2894 tmp16 = 0x70;
2895 gain[3] = 0;
2896 }
2897 }
2898 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2899 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2900 vmid[3] = tmp16;
2901 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2902 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2903 break;
2904 }
ba9a6214 2905
73d07a39
RM		 2906 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2907 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2908 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2909 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2910 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2911 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2912 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2913 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2914 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2915 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2916 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2917 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2918
2919 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2920
2921 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2922 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2923 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2924 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2925 tmp32 = 0x00088888;
2926 else
2927 tmp32 = 0x88888888;
2928 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2929 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2930 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2931
2932 if (dev->phy.rev == 4 &&
fa0f2b38 2933 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2934 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2935 0x70);
2936 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2937 0x70);
2938 }
ba9a6214 2939
fa0f2b38 2940 /* Dropped probably-always-true condition */
04519dc6
RM		 2941 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2942 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
bc36e994 2943 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
04519dc6
RM		 2944 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2945 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2946 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2947 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2948 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2949 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2950 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2951 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2952 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 2953
2954 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2955 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2956}
ba9a6214 2957
73d07a39
RM		 2958static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2959{
2960 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2961 struct b43_phy *phy = &dev->phy;
2962 struct b43_phy_n *nphy = phy->n;
ba9a6214 2963
73d07a39
RM		 2964 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2965 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2966
73d07a39
RM		 2967 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2968 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2969
fa0f2b38 2970 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 2971 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 2972 delays1[0] = 0x1;
2973 delays1[5] = 0x14;
2974 }
2975
73d07a39
RM		 2976 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2977 nphy->band5g_pwrgain) {
2978 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2979 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2980 } else {
73d07a39
RM		 2981 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2982 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2983 }
28fd7daa 2984
73d07a39
RM		 2985 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2986 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2987 if (dev->phy.rev < 3) {
2988 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2989 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2990 }
73d07a39
RM		 2991
2992 if (dev->phy.rev < 2) {
2993 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2994 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2995 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2996 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2997 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2998 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2999 }
28fd7daa 3000
73d07a39
RM		 3001 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3002 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3003 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3004 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 3005
73d07a39
RM		 3006 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
3007 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
3008
3ccd0957 3009 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 3010
3011 if (dev->phy.rev < 2) {
3012 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
3013 b43_hf_write(dev, b43_hf_read(dev) |
3014 B43_HF_MLADVW);
3015 } else if (dev->phy.rev == 2) {
3016 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
3017 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
3018 }
28fd7daa 3019
73d07a39
RM		 3020 if (dev->phy.rev < 2)
3021 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
3022 ~B43_NPHY_SCRAM_SIGCTL_SCM);
3023
3024 /* Set phase track alpha and beta */
3025 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
3026 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
3027 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
3028 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
3029 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
3030 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
3031
fa0f2b38
RM		 3032 if (dev->phy.rev < 3) {
3033 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
3034 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
3035 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
3036 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
3037 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
3038 }
73d07a39
RM		 3039
3040 if (dev->phy.rev == 2)
3041 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
3042 B43_NPHY_FINERX2_CGC_DECGC);
3043}
28fd7daa 3044
73d07a39
RM		 3045/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
3046static void b43_nphy_workarounds(struct b43_wldev *dev)
3047{
3048 struct b43_phy *phy = &dev->phy;
3049 struct b43_phy_n *nphy = phy->n;
28fd7daa 3050
73d07a39
RM		 3051 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3052 b43_nphy_classifier(dev, 1, 0);
3053 else
3054 b43_nphy_classifier(dev, 1, 1);
28fd7daa 3055
73d07a39
RM		 3056 if (nphy->hang_avoid)
3057 b43_nphy_stay_in_carrier_search(dev, 1);
3058
3059 b43_phy_set(dev, B43_NPHY_IQFLIP,
3060 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
3061
d11d354b
RM		 3062 if (dev->phy.rev >= 7)
3063 b43_nphy_workarounds_rev7plus(dev);
3064 else if (dev->phy.rev >= 3)
73d07a39
RM		 3065 b43_nphy_workarounds_rev3plus(dev);
3066 else
3067 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 3068
3069 if (nphy->hang_avoid)
3070 b43_nphy_stay_in_carrier_search(dev, 0);
3071}
3072
9dd4d9b9
RM		 3073/**************************************************
3074 * Tx/Rx common
3075 **************************************************/
3076
3077/*
3078 * Transmits a known value for LO calibration
3079 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
3080 */
3081static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
ed03033e 3082 bool iqmode, bool dac_test, bool modify_bbmult)
9dd4d9b9
RM		 3083{
3084 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
3085 if (samp == 0)
3086 return -1;
ed03033e
RM		 3087 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test,
3088 modify_bbmult);
9dd4d9b9
RM		 3089 return 0;
3090}
3091
3092/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
3093static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
3094{
3095 struct b43_phy_n *nphy = dev->phy.n;
3096
3097 bool override = false;
3098 u16 chain = 0x33;
3099
3100 if (nphy->txrx_chain == 0) {
3101 chain = 0x11;
3102 override = true;
3103 } else if (nphy->txrx_chain == 1) {
3104 chain = 0x22;
3105 override = true;
3106 }
3107
3108 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3109 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
3110 chain);
3111
3112 if (override)
3113 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
3114 B43_NPHY_RFSEQMODE_CAOVER);
3115 else
3116 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3117 ~B43_NPHY_RFSEQMODE_CAOVER);
3118}
3119
3120/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
3121static void b43_nphy_stop_playback(struct b43_wldev *dev)
3122{
3123 struct b43_phy_n *nphy = dev->phy.n;
3124 u16 tmp;
3125
3126 if (nphy->hang_avoid)
3127 b43_nphy_stay_in_carrier_search(dev, 1);
3128
3129 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
3130 if (tmp & 0x1)
3131 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
3132 else if (tmp & 0x2)
3133 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3134
3135 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3136
3137 if (nphy->bb_mult_save & 0x80000000) {
3138 tmp = nphy->bb_mult_save & 0xFFFF;
3139 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3140 nphy->bb_mult_save = 0;
3141 }
3142
3143 if (nphy->hang_avoid)
3144 b43_nphy_stay_in_carrier_search(dev, 0);
3145}
3146
3147/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3148static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3149 struct nphy_txgains target,
3150 struct nphy_iqcal_params *params)
3151{
3152 int i, j, indx;
3153 u16 gain;
3154
3155 if (dev->phy.rev >= 3) {
3156 params->txgm = target.txgm[core];
3157 params->pga = target.pga[core];
3158 params->pad = target.pad[core];
3159 params->ipa = target.ipa[core];
3160 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
3161 (params->pad << 4) | (params->ipa);
3162 for (j = 0; j < 5; j++)
3163 params->ncorr[j] = 0x79;
3164 } else {
3165 gain = (target.pad[core]) | (target.pga[core] << 4) |
3166 (target.txgm[core] << 8);
3167
3168 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3169 1 : 0;
3170 for (i = 0; i < 9; i++)
3171 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3172 break;
3173 i = min(i, 8);
3174
3175 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3176 params->pga = tbl_iqcal_gainparams[indx][i][2];
3177 params->pad = tbl_iqcal_gainparams[indx][i][3];
3178 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3179 (params->pad << 2);
3180 for (j = 0; j < 4; j++)
3181 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3182 }
3183}
3184
884a5228 3185/**************************************************
104cfa88 3186 * Tx and Rx
884a5228 3187 **************************************************/
5f6393ec 3188
884a5228
RM		 3189static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3190{//TODO
3191}
59af099b 3192
884a5228
RM		 3193static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3194 bool ignore_tssi)
3195{//TODO
3196 return B43_TXPWR_RES_DONE;
3197}
59af099b 3198
161d540c
RM		 3199/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3200static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3201{
3202 struct b43_phy_n *nphy = dev->phy.n;
3203 u8 i;
c9c0d9ec
RM		 3204 u16 bmask, val, tmp;
3205 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 3206
161d540c
RM		 3207 if (nphy->hang_avoid)
3208 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 3209
161d540c
RM		 3210 nphy->txpwrctrl = enable;
3211 if (!enable) {
c9c0d9ec
RM		 3212 if (dev->phy.rev >= 3 &&
3213 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3214 (B43_NPHY_TXPCTL_CMD_COEFF |
3215 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3216 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3217 /* We disable enabled TX pwr ctl, save it's state */
3218 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3219 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3220 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3221 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3222 }
59af099b 3223
161d540c
RM		 3224 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3225 for (i = 0; i < 84; i++)
3226 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3227
161d540c
RM		 3228 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3229 for (i = 0; i < 84; i++)
3230 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3231
161d540c
RM		 3232 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3233 if (dev->phy.rev >= 3)
3234 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3235 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 3236
161d540c
RM		 3237 if (dev->phy.rev >= 3) {
3238 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3239 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3240 } else {
3241 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3242 }
10a79873 3243
161d540c
RM		 3244 if (dev->phy.rev == 2)
3245 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3246 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3247 else if (dev->phy.rev < 2)
3248 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3249 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 3250
bee6d4b2 3251 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3252 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 3253 } else {
c9c0d9ec
RM		 3254 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3255 nphy->adj_pwr_tbl);
3256 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3257 nphy->adj_pwr_tbl);
10a79873 3258
c9c0d9ec
RM		 3259 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3260 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3261 /* wl does useless check for "enable" param here */
3262 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3263 if (dev->phy.rev >= 3) {
3264 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3265 if (val)
3266 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3267 }
3268 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3269
c9c0d9ec
RM		 3270 if (band == IEEE80211_BAND_5GHZ) {
3271 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3272 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3273 if (dev->phy.rev > 1)
3274 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3275 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3276 0x64);
3277 }
10a79873 3278
c9c0d9ec
RM		 3279 if (dev->phy.rev >= 3) {
3280 if (nphy->tx_pwr_idx[0] != 128 &&
3281 nphy->tx_pwr_idx[1] != 128) {
3282 /* Recover TX pwr ctl state */
3283 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3284 ~B43_NPHY_TXPCTL_CMD_INIT,
3285 nphy->tx_pwr_idx[0]);
3286 if (dev->phy.rev > 1)
3287 b43_phy_maskset(dev,
3288 B43_NPHY_TXPCTL_INIT,
3289 ~0xff, nphy->tx_pwr_idx[1]);
3290 }
3291 }
10a79873 3292
c9c0d9ec
RM		 3293 if (dev->phy.rev >= 3) {
3294 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3295 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3296 } else {
3297 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3298 }
10a79873 3299
c9c0d9ec
RM		 3300 if (dev->phy.rev == 2)
3301 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3302 else if (dev->phy.rev < 2)
3303 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3304
bee6d4b2 3305 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3306 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3307
c002831a 3308 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3309 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3310 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3311 }
10a79873 3312 }
10a79873 3313
161d540c
RM		 3314 if (nphy->hang_avoid)
3315 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3316}
3317
161d540c 3318/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3319static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91 3320{
39e971ef 3321 struct b43_phy *phy = &dev->phy;
6dcd9d91 3322 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3323 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3324
161d540c
RM		 3325 u8 txpi[2], bbmult, i;
3326 u16 tmp, radio_gain, dac_gain;
39e971ef 3327 u16 freq = phy->chandef->chan->center_freq;
161d540c
RM		 3328 u32 txgain;
3329 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3330
3331 if (nphy->hang_avoid)
161d540c 3332 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3333
dd5f13b8
RM		 3334 if (dev->phy.rev >= 7) {
3335 txpi[0] = txpi[1] = 30;
3336 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3337 txpi[0] = 40;
3338 txpi[1] = 40;
3339 } else if (sprom->revision < 4) {
3340 txpi[0] = 72;
3341 txpi[1] = 72;
3342 } else {
3343 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3344 txpi[0] = sprom->txpid2g[0];
3345 txpi[1] = sprom->txpid2g[1];
3346 } else if (freq >= 4900 && freq < 5100) {
3347 txpi[0] = sprom->txpid5gl[0];
3348 txpi[1] = sprom->txpid5gl[1];
3349 } else if (freq >= 5100 && freq < 5500) {
3350 txpi[0] = sprom->txpid5g[0];
3351 txpi[1] = sprom->txpid5g[1];
3352 } else if (freq >= 5500) {
3353 txpi[0] = sprom->txpid5gh[0];
3354 txpi[1] = sprom->txpid5gh[1];
3355 } else {
3356 txpi[0] = 91;
3357 txpi[1] = 91;
6dcd9d91
RM		 3358 }
3359 }
dd5f13b8 3360 if (dev->phy.rev < 7 &&
9bd28571 3361 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3362 txpi[0] = txpi[1] = 91;
6dcd9d91 3363
161d540c
RM		 3364 /*
3365 for (i = 0; i < 2; i++) {
3366 nphy->txpwrindex[i].index_internal = txpi[i];
3367 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3368 }
161d540c 3369 */
75377b24 3370
161d540c 3371 for (i = 0; i < 2; i++) {
aeab5751
RM		 3372 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3373
3374 if (dev->phy.rev >= 3)
161d540c 3375 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3376 else
161d540c 3377 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3378
dd5f13b8
RM		 3379 if (dev->phy.rev >= 7)
3380 dac_gain = (txgain >> 8) & 0x7;
3381 else
3382 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3383 bbmult = txgain & 0xFF;
75377b24 3384
161d540c
RM		 3385 if (dev->phy.rev >= 3) {
3386 if (i == 0)
3387 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3388 else
3389 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3390 } else {
3391 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3392 }
75377b24 3393
161d540c
RM		 3394 if (i == 0)
3395 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3396 else
3397 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3398
44f4008b 3399 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3400
44f4008b 3401 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3402 if (i == 0)
3403 tmp = (tmp & 0x00FF) | (bbmult << 8);
3404 else
3405 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3406 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3407
0eff8fcd
RM		 3408 if (b43_nphy_ipa(dev)) {
3409 u32 tmp32;
3410 u16 reg = (i == 0) ?
3411 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3412 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3413 576 + txpi[i]));
0eff8fcd
RM		 3414 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3415 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3416 }
3417 }
75377b24 3418
161d540c 3419 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3420
161d540c
RM		 3421 if (nphy->hang_avoid)
3422 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3423}
67cbc3ed 3424
3dda07b6
RM		 3425static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3426{
3427 struct b43_phy *phy = &dev->phy;
3428
3429 u8 core;
3430 u16 r; /* routing */
3431
3432 if (phy->rev >= 7) {
3433 for (core = 0; core < 2; core++) {
3434 r = core ? 0x190 : 0x170;
3435 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3436 b43_radio_write(dev, r + 0x5, 0x5);
3437 b43_radio_write(dev, r + 0x9, 0xE);
3438 if (phy->rev != 5)
3439 b43_radio_write(dev, r + 0xA, 0);
3440 if (phy->rev != 7)
3441 b43_radio_write(dev, r + 0xB, 1);
3442 else
3443 b43_radio_write(dev, r + 0xB, 0x31);
3444 } else {
3445 b43_radio_write(dev, r + 0x5, 0x9);
3446 b43_radio_write(dev, r + 0x9, 0xC);
3447 b43_radio_write(dev, r + 0xB, 0x0);
3448 if (phy->rev != 5)
3449 b43_radio_write(dev, r + 0xA, 1);
3450 else
3451 b43_radio_write(dev, r + 0xA, 0x31);
3452 }
3453 b43_radio_write(dev, r + 0x6, 0);
3454 b43_radio_write(dev, r + 0x7, 0);
3455 b43_radio_write(dev, r + 0x8, 3);
3456 b43_radio_write(dev, r + 0xC, 0);
3457 }
3458 } else {
3459 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3460 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3461 else
3462 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3463 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3464 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3465
3466 for (core = 0; core < 2; core++) {
3467 r = core ? B2056_TX1 : B2056_TX0;
3468
3469 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3470 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3471 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3472 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3473 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3474 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3475 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3476 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3477 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3478 0x5);
3479 if (phy->rev != 5)
3480 b43_radio_write(dev, r | B2056_TX_TSSIA,
3481 0x00);
3482 if (phy->rev >= 5)
3483 b43_radio_write(dev, r | B2056_TX_TSSIG,
3484 0x31);
3485 else
3486 b43_radio_write(dev, r | B2056_TX_TSSIG,
3487 0x11);
3488 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3489 0xE);
3490 } else {
3491 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3492 0x9);
3493 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3494 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3495 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3496 0xC);
3497 }
3498 }
3499 }
3500}
3501
3502/*
3503 * Stop radio and transmit known signal. Then check received signal strength to
3504 * get TSSI (Transmit Signal Strength Indicator).
3505 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3506 */
3507static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3508{
3509 struct b43_phy *phy = &dev->phy;
3510 struct b43_phy_n *nphy = dev->phy.n;
3511
3512 u32 tmp;
3513 s32 rssi[4] = { };
3514
3515 /* TODO: check if we can transmit */
3516
3517 if (b43_nphy_ipa(dev))
3518 b43_nphy_ipa_internal_tssi_setup(dev);
3519
3520 if (phy->rev >= 7)
78ae7532 3521 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3522 else if (phy->rev >= 3)
78ae7532 3523 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3524
3525 b43_nphy_stop_playback(dev);
ed03033e 3526 b43_nphy_tx_tone(dev, 4000, 0, false, false, false);
3dda07b6 3527 udelay(20);
a3764ef7 3528 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3529 b43_nphy_stop_playback(dev);
a3764ef7 3530 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6
RM		 3531
3532 if (phy->rev >= 7)
78ae7532 3533 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3534 else if (phy->rev >= 3)
78ae7532 3535 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6
RM		 3536
3537 if (phy->rev >= 3) {
3538 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3539 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3540 } else {
3541 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3542 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3543 }
3544 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3545 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3546}
3547
d3fd8bf7
RM		 3548/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3549static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3550{
3551 struct b43_phy_n *nphy = dev->phy.n;
3552
3553 u8 idx, delta;
3554 u8 i, stf_mode;
3555
55757927
RM		 3556 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3557 * 21 groups, each containing 4 entries.
3558 *
3559 * First group has entries for CCK modulation.
3560 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3561 *
3562 * Group 0 is for CCK
3563 * Groups 1..4 use BPSK (group per coding rate)
3564 * Groups 5..8 use QPSK (group per coding rate)
3565 * Groups 9..12 use 16-QAM (group per coding rate)
3566 * Groups 13..16 use 64-QAM (group per coding rate)
3567 * Groups 17..20 are unknown
3568 */
3569
d3fd8bf7
RM		 3570 for (i = 0; i < 4; i++)
3571 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3572
3573 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3574 delta = 0;
3575 switch (stf_mode) {
3576 case 0:
bee6d4b2 3577 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
d3fd8bf7
RM		 3578 idx = 68;
3579 } else {
3580 delta = 1;
bee6d4b2 3581 idx = b43_is_40mhz(dev) ? 52 : 4;
d3fd8bf7
RM		 3582 }
3583 break;
3584 case 1:
bee6d4b2 3585 idx = b43_is_40mhz(dev) ? 76 : 28;
d3fd8bf7
RM		 3586 break;
3587 case 2:
bee6d4b2 3588 idx = b43_is_40mhz(dev) ? 84 : 36;
d3fd8bf7
RM		 3589 break;
3590 case 3:
bee6d4b2 3591 idx = b43_is_40mhz(dev) ? 92 : 44;
d3fd8bf7
RM		 3592 break;
3593 }
3594
3595 for (i = 0; i < 20; i++) {
3596 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3597 nphy->tx_power_offset[idx];
3598 if (i == 0)
3599 idx += delta;
3600 if (i == 14)
3601 idx += 1 - delta;
3602 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3603 i == 13)
3604 idx += 1;
3605 }
3606 }
3607}
3608
3609/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3610static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3611{
39e971ef 3612 struct b43_phy *phy = &dev->phy;
d3fd8bf7
RM		 3613 struct b43_phy_n *nphy = dev->phy.n;
3614 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3615
3616 s16 a1[2], b0[2], b1[2];
3617 u8 idle[2];
3618 s8 target[2];
3619 s32 num, den, pwr;
3620 u32 regval[64];
3621
39e971ef 3622 u16 freq = phy->chandef->chan->center_freq;
d3fd8bf7
RM		 3623 u16 tmp;
3624 u16 r; /* routing */
3625 u8 i, c;
3626
3627 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3628 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3629 b43_read32(dev, B43_MMIO_MACCTL);
3630 udelay(1);
3631 }
3632
3633 if (nphy->hang_avoid)
3634 b43_nphy_stay_in_carrier_search(dev, true);
3635
3636 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3637 if (dev->phy.rev >= 3)
3638 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3639 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3640 else
3641 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3642 B43_NPHY_TXPCTL_CMD_PCTLEN);
3643
3644 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3645 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3646
3647 if (sprom->revision < 4) {
3648 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3649 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3650 target[0] = target[1] = 52;
3651 a1[0] = a1[1] = -424;
3652 b0[0] = b0[1] = 5612;
3653 b1[0] = b1[1] = -1393;
3654 } else {
3655 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3656 for (c = 0; c < 2; c++) {
3657 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3658 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3659 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3660 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3661 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3662 }
3663 } else if (freq >= 4900 && freq < 5100) {
3664 for (c = 0; c < 2; c++) {
3665 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3666 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3667 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3668 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3669 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3670 }
3671 } else if (freq >= 5100 && freq < 5500) {
3672 for (c = 0; c < 2; c++) {
3673 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3674 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3675 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3676 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3677 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3678 }
3679 } else if (freq >= 5500) {
3680 for (c = 0; c < 2; c++) {
3681 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3682 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3683 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3684 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3685 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3686 }
3687 } else {
3688 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3689 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3690 target[0] = target[1] = 52;
3691 a1[0] = a1[1] = -424;
3692 b0[0] = b0[1] = 5612;
3693 b1[0] = b1[1] = -1393;
3694 }
3695 }
3696 /* target[0] = target[1] = nphy->tx_power_max; */
3697
3698 if (dev->phy.rev >= 3) {
3699 if (sprom->fem.ghz2.tssipos)
3700 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3701 if (dev->phy.rev >= 7) {
3702 for (c = 0; c < 2; c++) {
3703 r = c ? 0x190 : 0x170;
3704 if (b43_nphy_ipa(dev))
3705 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3706 }
3707 } else {
3708 if (b43_nphy_ipa(dev)) {
3709 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3710 b43_radio_write(dev,
3711 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3712 b43_radio_write(dev,
3713 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3714 } else {
3715 b43_radio_write(dev,
3716 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3717 b43_radio_write(dev,
3718 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3719 }
3720 }
3721 }
3722
3723 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3724 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3725 b43_read32(dev, B43_MMIO_MACCTL);
3726 udelay(1);
3727 }
3728
3729 if (dev->phy.rev >= 7) {
3730 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3731 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3732 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3733 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3734 } else {
3735 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3736 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3737 if (dev->phy.rev > 1)
3738 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3739 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3740 }
3741
3742 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3743 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3744
3745 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3746 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3747 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3748 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3749 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3750 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3751 B43_NPHY_TXPCTL_ITSSI_BINF);
3752 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3753 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3754 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3755
3756 for (c = 0; c < 2; c++) {
3757 for (i = 0; i < 64; i++) {
3758 num = 8 * (16 * b0[c] + b1[c] * i);
3759 den = 32768 + a1[c] * i;
3760 pwr = max((4 * num + den / 2) / den, -8);
3761 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3762 pwr = max(pwr, target[c] + 1);
3763 regval[i] = pwr;
3764 }
3765 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3766 }
3767
3768 b43_nphy_tx_prepare_adjusted_power_table(dev);
d3fd8bf7
RM		 3769 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3770 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
d3fd8bf7
RM		 3771
3772 if (nphy->hang_avoid)
3773 b43_nphy_stay_in_carrier_search(dev, false);
3774}
3775
0eff8fcd
RM		 3776static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3777{
3778 struct b43_phy *phy = &dev->phy;
67cbc3ed 3779
0eff8fcd 3780 const u32 *table = NULL;
0eff8fcd
RM		 3781 u32 rfpwr_offset;
3782 u8 pga_gain;
3783 int i;
0eff8fcd 3784
aeab5751 3785 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3786 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3787 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3788
3789 if (phy->rev >= 3) {
3790#if 0
3791 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3792#endif
0eff8fcd
RM		 3793
3794 for (i = 0; i < 128; i++) {
3795 pga_gain = (table[i] >> 24) & 0xF;
3796 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3797 rfpwr_offset =
3798 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3799 else
34c5cf20
RM		 3800 rfpwr_offset =
3801 0; /* FIXME */
0eff8fcd
RM		 3802 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3803 rfpwr_offset);
3804 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3805 rfpwr_offset);
3806 }
67cbc3ed
RM		 3807 }
3808}
3809
e50cbcf6
RM		 3810/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3811static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3812{
e50cbcf6
RM		 3813 struct b43_phy_n *nphy = dev->phy.n;
3814 enum ieee80211_band band;
3815 u16 tmp;
95b66bad 3816
e50cbcf6
RM		 3817 if (!enable) {
3818 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3819 B43_NPHY_RFCTL_INTC1);
3820 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3821 B43_NPHY_RFCTL_INTC2);
3822 band = b43_current_band(dev->wl);
3823 if (dev->phy.rev >= 3) {
3824 if (band == IEEE80211_BAND_5GHZ)
3825 tmp = 0x600;
3826 else
3827 tmp = 0x480;
3828 } else {
3829 if (band == IEEE80211_BAND_5GHZ)
3830 tmp = 0x180;
3831 else
3832 tmp = 0x120;
3833 }
3834 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3835 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3836 } else {
3837 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3838 nphy->rfctrl_intc1_save);
3839 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3840 nphy->rfctrl_intc2_save);
95b66bad 3841 }
95b66bad
MB		 3842}
3843
8ac3a2aa
RM		 3844/*
3845 * TX low-pass filter bandwidth setup
3846 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw
3847 */
3848static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev)
3c95627d
RM		 3849{
3850 u16 tmp;
3c95627d 3851
8ac3a2aa
RM		 3852 if (dev->phy.rev < 3 || dev->phy.rev >= 7)
3853 return;
76b002bd 3854
8ac3a2aa
RM		 3855 if (b43_nphy_ipa(dev))
3856 tmp = b43_is_40mhz(dev) ? 5 : 4;
3857 else
3858 tmp = b43_is_40mhz(dev) ? 3 : 1;
3859 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3860 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
3861
3862 if (b43_nphy_ipa(dev)) {
3863 tmp = b43_is_40mhz(dev) ? 4 : 1;
fe3e46e8 3864 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
8ac3a2aa 3865 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
fe3e46e8
RM		 3866 }
3867}
76b002bd 3868
2faa6b83
RM		 3869/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3870static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3871 u16 samps, u8 time, bool wait)
3c95627d 3872{
2faa6b83
RM		 3873 int i;
3874 u16 tmp;
3c95627d 3875
2faa6b83
RM		 3876 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3877 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3878 if (wait)
3879 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3880 else
2faa6b83 3881 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3882
2faa6b83 3883 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3884
2faa6b83
RM		 3885 for (i = 1000; i; i--) {
3886 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3887 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3888 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3889 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3890 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3891 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3892 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3893 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3894
2faa6b83
RM		 3895 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3896 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3897 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3898 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3899 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3900 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3901 return;
3c95627d 3902 }
2faa6b83 3903 udelay(10);
3c95627d 3904 }
2faa6b83 3905 memset(est, 0, sizeof(*est));
3c95627d
RM		 3906}
3907
a67162ab
RM		 3908/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3909static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3910 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3911{
a67162ab
RM		 3912 if (write) {
3913 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3914 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3915 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3916 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3917 } else {
a67162ab
RM		 3918 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3919 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3920 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3921 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3922 }
3923}
6e3b15a9 3924
c7455cf9
RM		 3925#if 0
3926/* Ready but not used anywhere */
026816fc
RM		 3927/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3928static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3929{
3930 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3931
026816fc
RM		 3932 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3933 if (core == 0) {
3934 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3935 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3936 } else {
3937 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3938 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3939 }
3940 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3941 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3942 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3943 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3944 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3945 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3946 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3947 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3948}
6e3b15a9 3949
026816fc
RM		 3950/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3951static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3952{
3953 u8 rxval, txval;
3954 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3955
026816fc
RM		 3956 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3957 if (core == 0) {
3958 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3959 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3960 } else {
3961 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3962 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3963 }
3964 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3965 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3966 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3967 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3968 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3969 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3970 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3971 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3972
026816fc
RM		 3973 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3974 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3975
acd82aa8
LF		 3976 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3977 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3978 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3979 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3980 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3981 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3982 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3983 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3984 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3985
026816fc
RM		 3986 if (core == 0) {
3987 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3988 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3989 } else {
3990 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3991 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3992 }
6e3b15a9 3993
89e43dad 3994 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 3995 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 3996 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3997
026816fc
RM		 3998 if (core == 0) {
3999 rxval = 1;
4000 txval = 8;
4001 } else {
4002 rxval = 4;
4003 txval = 2;
6e3b15a9 4004 }
89e43dad
RM		 4005 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4006 core + 1);
4007 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4008 2 - core);
99b82c41 4009}
c7455cf9 4010#endif
99b82c41 4011
34a56f2c
RM		 4012/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
4013static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 4014{
4015 int i;
34a56f2c
RM		 4016 s32 iq;
4017 u32 ii;
4018 u32 qq;
4019 int iq_nbits, qq_nbits;
4020 int arsh, brsh;
4021 u16 tmp, a, b;
4022
4023 struct nphy_iq_est est;
4024 struct b43_phy_n_iq_comp old;
4025 struct b43_phy_n_iq_comp new = { };
4026 bool error = false;
4027
4028 if (mask == 0)
4029 return;
4030
4031 b43_nphy_rx_iq_coeffs(dev, false, &old);
4032 b43_nphy_rx_iq_coeffs(dev, true, &new);
4033 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
4034 new = old;
4035
dfb4aa5d 4036 for (i = 0; i < 2; i++) {
34a56f2c
RM		 4037 if (i == 0 && (mask & 1)) {
4038 iq = est.iq0_prod;
4039 ii = est.i0_pwr;
4040 qq = est.q0_pwr;
4041 } else if (i == 1 && (mask & 2)) {
4042 iq = est.iq1_prod;
4043 ii = est.i1_pwr;
4044 qq = est.q1_pwr;
dfb4aa5d 4045 } else {
34a56f2c 4046 continue;
dfb4aa5d 4047 }
dfb4aa5d 4048
34a56f2c
RM		 4049 if (ii + qq < 2) {
4050 error = true;
4051 break;
4052 }
dfb4aa5d 4053
34a56f2c
RM		 4054 iq_nbits = fls(abs(iq));
4055 qq_nbits = fls(qq);
dfb4aa5d 4056
34a56f2c
RM		 4057 arsh = iq_nbits - 20;
4058 if (arsh >= 0) {
4059 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
4060 tmp = ii >> arsh;
4061 } else {
4062 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
4063 tmp = ii << -arsh;
4064 }
4065 if (tmp == 0) {
4066 error = true;
4067 break;
4068 }
4069 a /= tmp;
dfb4aa5d 4070
34a56f2c
RM		 4071 brsh = qq_nbits - 11;
4072 if (brsh >= 0) {
4073 b = (qq << (31 - qq_nbits));
4074 tmp = ii >> brsh;
dfb4aa5d 4075 } else {
34a56f2c
RM		 4076 b = (qq << (31 - qq_nbits));
4077 tmp = ii << -brsh;
4078 }
4079 if (tmp == 0) {
4080 error = true;
4081 break;
dfb4aa5d 4082 }
34a56f2c 4083 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 4084
34a56f2c
RM		 4085 if (i == 0 && (mask & 0x1)) {
4086 if (dev->phy.rev >= 3) {
4087 new.a0 = a & 0x3FF;
4088 new.b0 = b & 0x3FF;
4089 } else {
4090 new.a0 = b & 0x3FF;
4091 new.b0 = a & 0x3FF;
4092 }
4093 } else if (i == 1 && (mask & 0x2)) {
4094 if (dev->phy.rev >= 3) {
4095 new.a1 = a & 0x3FF;
4096 new.b1 = b & 0x3FF;
4097 } else {
4098 new.a1 = b & 0x3FF;
4099 new.b1 = a & 0x3FF;
4100 }
4101 }
dfb4aa5d 4102 }
dfb4aa5d 4103
34a56f2c
RM		 4104 if (error)
4105 new = old;
dfb4aa5d 4106
34a56f2c
RM		 4107 b43_nphy_rx_iq_coeffs(dev, true, &new);
4108}
dfb4aa5d 4109
09146400
RM		 4110/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
4111static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
4112{
4113 u16 array[4];
44f4008b 4114 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 4115
4116 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
4117 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
4118 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
4119 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 4120}
4121
9442e5b5
RM		 4122/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
4123static void b43_nphy_spur_workaround(struct b43_wldev *dev)
4124{
4125 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 4126
204a665b 4127 u8 channel = dev->phy.channel;
9442e5b5
RM		 4128 int tone[2] = { 57, 58 };
4129 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 4130
9442e5b5 4131 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 4132
9442e5b5
RM		 4133 if (nphy->hang_avoid)
4134 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 4135
9442e5b5
RM		 4136 if (nphy->gband_spurwar_en) {
4137 /* TODO: N PHY Adjust Analog Pfbw (7) */
bee6d4b2 4138 if (channel == 11 && b43_is_40mhz(dev))
9442e5b5
RM		 4139 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4140 else
4141 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4142 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 4143 }
4144
9442e5b5
RM		 4145 if (nphy->aband_spurwar_en) {
4146 if (channel == 54) {
4147 tone[0] = 0x20;
4148 noise[0] = 0x25F;
4149 } else if (channel == 38 || channel == 102 || channel == 118) {
4150 if (0 /* FIXME */) {
4151 tone[0] = 0x20;
4152 noise[0] = 0x21F;
4153 } else {
4154 tone[0] = 0;
4155 noise[0] = 0;
90b9738d 4156 }
9442e5b5
RM		 4157 } else if (channel == 134) {
4158 tone[0] = 0x20;
4159 noise[0] = 0x21F;
4160 } else if (channel == 151) {
4161 tone[0] = 0x10;
4162 noise[0] = 0x23F;
4163 } else if (channel == 153 || channel == 161) {
4164 tone[0] = 0x30;
4165 noise[0] = 0x23F;
4166 } else {
4167 tone[0] = 0;
4168 noise[0] = 0;
90b9738d 4169 }
90b9738d 4170
9442e5b5
RM		 4171 if (!tone[0] && !noise[0])
4172 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 4173 else
9442e5b5
RM		 4174 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4175 }
90b9738d 4176
9442e5b5
RM		 4177 if (nphy->hang_avoid)
4178 b43_nphy_stay_in_carrier_search(dev, 0);
4179}
90b9738d 4180
5ecab603
RM		 4181/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4182static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4183{
4184 struct b43_phy_n *nphy = dev->phy.n;
4185 int i, j;
4186 u32 tmp;
4187 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 4188
5ecab603 4189 u16 buffer[7];
90b9738d 4190
5ecab603
RM		 4191 if (nphy->hang_avoid)
4192 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 4193
5ecab603 4194 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 4195
5ecab603
RM		 4196 for (i = 0; i < 2; i++) {
4197 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4198 (buffer[i * 2 + 1] & 0x3FF);
4199 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4200 (((i + 26) << 10) | 320));
4201 for (j = 0; j < 128; j++) {
4202 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4203 ((tmp >> 16) & 0xFFFF));
4204 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4205 (tmp & 0xFFFF));
90b9738d 4206 }
90b9738d 4207 }
90b9738d 4208
5ecab603
RM		 4209 for (i = 0; i < 2; i++) {
4210 tmp = buffer[5 + i];
4211 real_part = (tmp >> 8) & 0xFF;
4212 imag_part = (tmp & 0xFF);
4213 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4214 (((i + 26) << 10) | 448));
90b9738d 4215
5ecab603
RM		 4216 if (dev->phy.rev >= 3) {
4217 cur_real = real_part;
4218 cur_imag = imag_part;
4219 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4220 }
4cb99775 4221
5ecab603
RM		 4222 for (j = 0; j < 128; j++) {
4223 if (dev->phy.rev < 3) {
4224 cur_real = (real_part * loscale[j] + 128) >> 8;
4225 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4226 tmp = ((cur_real & 0xFF) << 8) |
4227 (cur_imag & 0xFF);
4228 }
4229 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4230 ((tmp >> 16) & 0xFFFF));
4231 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4232 (tmp & 0xFFFF));
4233 }
90b9738d 4234 }
4cb99775 4235
4cb99775 4236 if (dev->phy.rev >= 3) {
5ecab603
RM		 4237 b43_shm_write16(dev, B43_SHM_SHARED,
4238 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4239 b43_shm_write16(dev, B43_SHM_SHARED,
4240 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 4241 }
90b9738d 4242
5ecab603
RM		 4243 if (nphy->hang_avoid)
4244 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 4245}
4246
42e1547e
RM		 4247/*
4248 * Restore RSSI Calibration
4249 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4250 */
4251static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4252{
4253 struct b43_phy_n *nphy = dev->phy.n;
4254
4255 u16 *rssical_radio_regs = NULL;
4256 u16 *rssical_phy_regs = NULL;
4257
4258 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4259 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 4260 return;
4261 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4262 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4263 } else {
204a665b 4264 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 4265 return;
4266 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4267 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4268 }
4269
9a98979e
RM		 4270 if (dev->phy.rev >= 7) {
4271 } else {
4272 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4273 rssical_radio_regs[0]);
4274 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4275 rssical_radio_regs[1]);
4276 }
42e1547e
RM		 4277
4278 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4279 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4280 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4281 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4282
4283 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4284 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4285 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4286 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4287
4288 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4289 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4290 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4291 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4292}
4293
c4a92003
RM		 4294/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4295static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4296{
4297 struct b43_phy_n *nphy = dev->phy.n;
4298 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4299 u16 tmp;
4300 u8 offset, i;
c4a92003
RM		 4301
4302 if (dev->phy.rev >= 3) {
52cb5e97
RM		 4303 for (i = 0; i < 2; i++) {
4304 tmp = (i == 0) ? 0x2000 : 0x3000;
4305 offset = i * 11;
4306
0c201cfb
RM		 4307 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4308 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4309 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4310 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4311 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4312 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4313 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4314 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4315 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4316 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4317 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4318
4319 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4320 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4321 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4322 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4323 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4324 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4325 if (nphy->ipa5g_on) {
0c201cfb
RM		 4326 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4327 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4328 } else {
0c201cfb
RM		 4329 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4330 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4331 }
0c201cfb 4332 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4333 } else {
0c201cfb
RM		 4334 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4335 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4336 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4337 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4338 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4339 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4340 if (nphy->ipa2g_on) {
0c201cfb
RM		 4341 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4342 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4343 (dev->phy.rev < 5) ? 0x11 : 0x01);
4344 } else {
0c201cfb
RM		 4345 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4346 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4347 }
4348 }
0c201cfb
RM		 4349 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4350 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4351 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4352 }
c4a92003 4353 } else {
0c201cfb
RM		 4354 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4355 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4356
0c201cfb
RM		 4357 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4358 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4359
0c201cfb
RM		 4360 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4361 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4362
0c201cfb
RM		 4363 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4364 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4365
0c201cfb
RM		 4366 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4367 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4368
4369 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4370 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4371 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4372 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4373 } else {
0c201cfb
RM		 4374 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4375 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4376 }
4377
4378 if (dev->phy.rev < 2) {
4379 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4380 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4381 } else {
4382 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4383 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4384 }
4385 }
4386}
4387
de7ed0c6
RM		 4388/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4389static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4390{
4391 struct b43_phy_n *nphy = dev->phy.n;
4392 int i;
4393 u16 scale, entry;
4394
4395 u16 tmp = nphy->txcal_bbmult;
4396 if (core == 0)
4397 tmp >>= 8;
4398 tmp &= 0xff;
4399
4400 for (i = 0; i < 18; i++) {
4401 scale = (ladder_lo[i].percent * tmp) / 100;
4402 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4403 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4404
4405 scale = (ladder_iq[i].percent * tmp) / 100;
4406 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4407 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4408 }
4409}
4410
45ca697e
RM		 4411/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4412static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4413{
4414 int i;
4415 for (i = 0; i < 15; i++)
4416 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4417 tbl_tx_filter_coef_rev4[2][i]);
4418}
4419
4420/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4421static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4422{
4423 int i, j;
4424 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4425 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4426
4427 for (i = 0; i < 3; i++)
4428 for (j = 0; j < 15; j++)
4429 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4430 tbl_tx_filter_coef_rev4[i][j]);
4431
bee6d4b2 4432 if (b43_is_40mhz(dev)) {
45ca697e
RM		 4433 for (j = 0; j < 15; j++)
4434 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4435 tbl_tx_filter_coef_rev4[3][j]);
4436 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4437 for (j = 0; j < 15; j++)
4438 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4439 tbl_tx_filter_coef_rev4[5][j]);
4440 }
4441
4442 if (dev->phy.channel == 14)
4443 for (j = 0; j < 15; j++)
4444 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4445 tbl_tx_filter_coef_rev4[6][j]);
4446}
4447
b0022e15
RM		 4448/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4449static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4450{
4451 struct b43_phy_n *nphy = dev->phy.n;
4452
4453 u16 curr_gain[2];
4454 struct nphy_txgains target;
4455 const u32 *table = NULL;
4456
161d540c 4457 if (!nphy->txpwrctrl) {
b0022e15
RM		 4458 int i;
4459
4460 if (nphy->hang_avoid)
4461 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4462 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4463 if (nphy->hang_avoid)
4464 b43_nphy_stay_in_carrier_search(dev, false);
4465
4466 for (i = 0; i < 2; ++i) {
4467 if (dev->phy.rev >= 3) {
4468 target.ipa[i] = curr_gain[i] & 0x000F;
4469 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4470 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4471 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4472 } else {
4473 target.ipa[i] = curr_gain[i] & 0x0003;
4474 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4475 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4476 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4477 }
4478 }
4479 } else {
4480 int i;
4481 u16 index[2];
4482 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4483 B43_NPHY_TXPCTL_STAT_BIDX) >>
4484 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4485 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4486 B43_NPHY_TXPCTL_STAT_BIDX) >>
4487 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4488
4489 for (i = 0; i < 2; ++i) {
aeab5751 4490 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4491 if (dev->phy.rev >= 3) {
b0022e15
RM		 4492 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4493 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4494 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4495 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4496 } else {
b0022e15
RM		 4497 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4498 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4499 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4500 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4501 }
4502 }
4503 }
4504
4505 return target;
4506}
4507
e53de674
RM		 4508/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4509static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4510{
4511 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4512
4513 if (dev->phy.rev >= 3) {
4514 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4515 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4516 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4517 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4518 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4519 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4520 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4521 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4522 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4523 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4524 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4525 b43_nphy_reset_cca(dev);
4526 } else {
4527 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4528 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4529 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4530 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4531 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4532 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4533 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4534 }
4535}
4536
4537/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4538static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4539{
4540 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4541 u16 tmp;
4542
4543 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4544 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4545 if (dev->phy.rev >= 3) {
4546 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4547 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4548
4549 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4550 regs[2] = tmp;
4551 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4552
4553 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4554 regs[3] = tmp;
4555 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4556
4557 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4558 b43_phy_mask(dev, B43_NPHY_BBCFG,
4559 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4560
c643a66e 4561 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4562 regs[5] = tmp;
d41a3552 4563 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4564
4565 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4566 regs[6] = tmp;
d41a3552 4567 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4568 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4569 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4570
89e43dad
RM		 4571 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4572 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4573 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4574
4575 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4576 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4577 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4578 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4579 } else {
4580 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4581 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4582 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4583 regs[2] = tmp;
4584 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4585 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4586 regs[3] = tmp;
4587 tmp |= 0x2000;
d41a3552 4588 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4589 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4590 regs[4] = tmp;
4591 tmp |= 0x2000;
d41a3552 4592 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4593 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4594 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4595 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4596 tmp = 0x0180;
4597 else
4598 tmp = 0x0120;
4599 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4600 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4601 }
4602}
4603
bbc6dc12
RM		 4604/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4605static void b43_nphy_save_cal(struct b43_wldev *dev)
4606{
4607 struct b43_phy_n *nphy = dev->phy.n;
4608
4609 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4610 u16 *txcal_radio_regs = NULL;
902db91d 4611 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4612 u16 *table = NULL;
4613
4614 if (nphy->hang_avoid)
4615 b43_nphy_stay_in_carrier_search(dev, 1);
4616
4617 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4618 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4619 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4620 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4621 table = nphy->cal_cache.txcal_coeffs_2G;
4622 } else {
4623 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4624 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4625 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4626 table = nphy->cal_cache.txcal_coeffs_5G;
4627 }
4628
4629 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4630 /* TODO use some definitions */
4631 if (dev->phy.rev >= 3) {
4632 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4633 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4634 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4635 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4636 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4637 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4638 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4639 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4640 } else {
4641 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4642 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4643 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4644 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4645 }
39e971ef 4646 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
427fa00b
RM		 4647 iqcal_chanspec->channel_type =
4648 cfg80211_get_chandef_type(dev->phy.chandef);
5818e989 4649 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4650
4651 if (nphy->hang_avoid)
4652 b43_nphy_stay_in_carrier_search(dev, 0);
4653}
4654
2f258b74
RM		 4655/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4656static void b43_nphy_restore_cal(struct b43_wldev *dev)
4657{
4658 struct b43_phy_n *nphy = dev->phy.n;
4659
4660 u16 coef[4];
4661 u16 *loft = NULL;
4662 u16 *table = NULL;
4663
4664 int i;
4665 u16 *txcal_radio_regs = NULL;
4666 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4667
4668 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4669 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4670 return;
4671 table = nphy->cal_cache.txcal_coeffs_2G;
4672 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4673 } else {
204a665b 4674 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4675 return;
4676 table = nphy->cal_cache.txcal_coeffs_5G;
4677 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4678 }
4679
2581b143 4680 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4681
4682 for (i = 0; i < 4; i++) {
4683 if (dev->phy.rev >= 3)
4684 table[i] = coef[i];
4685 else
4686 coef[i] = 0;
4687 }
4688
2581b143
RM		 4689 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4690 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4691 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4692
4693 if (dev->phy.rev < 2)
4694 b43_nphy_tx_iq_workaround(dev);
4695
4696 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4697 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4698 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4699 } else {
4700 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4701 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4702 }
4703
4704 /* TODO use some definitions */
4705 if (dev->phy.rev >= 3) {
4706 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4707 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4708 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4709 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4710 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4711 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4712 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4713 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4714 } else {
4715 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4716 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4717 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4718 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4719 }
4720 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4721}
4722
fb43b8e2
RM		 4723/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4724static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4725 struct nphy_txgains target,
4726 bool full, bool mphase)
4727{
39e971ef 4728 struct b43_phy *phy = &dev->phy;
fb43b8e2
RM		 4729 struct b43_phy_n *nphy = dev->phy.n;
4730 int i;
4731 int error = 0;
4732 int freq;
4733 bool avoid = false;
4734 u8 length;
fb23d863 4735 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4736 const u16 *table;
4737 bool phy6or5x;
4738
4739 u16 buffer[11];
4740 u16 diq_start = 0;
4741 u16 save[2];
4742 u16 gain[2];
4743 struct nphy_iqcal_params params[2];
4744 bool updated[2] = { };
4745
4746 b43_nphy_stay_in_carrier_search(dev, true);
4747
4748 if (dev->phy.rev >= 4) {
4749 avoid = nphy->hang_avoid;
3db1cd5c 4750 nphy->hang_avoid = false;
fb43b8e2
RM		 4751 }
4752
9145834e 4753 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4754
4755 for (i = 0; i < 2; i++) {
4756 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4757 gain[i] = params[i].cal_gain;
4758 }
2581b143
RM		 4759
4760 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4761
4762 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4763 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4764
4765 phy6or5x = dev->phy.rev >= 6 ||
4766 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4767 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4768 if (phy6or5x) {
bee6d4b2 4769 if (b43_is_40mhz(dev)) {
38bb9029
RM		 4770 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4771 tbl_tx_iqlo_cal_loft_ladder_40);
4772 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4773 tbl_tx_iqlo_cal_iqimb_ladder_40);
4774 } else {
4775 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4776 tbl_tx_iqlo_cal_loft_ladder_20);
4777 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4778 tbl_tx_iqlo_cal_iqimb_ladder_20);
4779 }
fb43b8e2
RM		 4780 }
4781
4782 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4783
bee6d4b2 4784 if (!b43_is_40mhz(dev))
fb43b8e2
RM		 4785 freq = 2500;
4786 else
4787 freq = 5000;
4788
4789 if (nphy->mphase_cal_phase_id > 2)
bee6d4b2 4790 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
ed03033e 4791 0xFFFF, 0, true, false, false);
fb43b8e2 4792 else
ed03033e 4793 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false);
fb43b8e2
RM		 4794
4795 if (error == 0) {
4796 if (nphy->mphase_cal_phase_id > 2) {
4797 table = nphy->mphase_txcal_bestcoeffs;
4798 length = 11;
4799 if (dev->phy.rev < 3)
4800 length -= 2;
4801 } else {
4802 if (!full && nphy->txiqlocal_coeffsvalid) {
4803 table = nphy->txiqlocal_bestc;
4804 length = 11;
4805 if (dev->phy.rev < 3)
4806 length -= 2;
4807 } else {
4808 full = true;
4809 if (dev->phy.rev >= 3) {
4810 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4811 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4812 } else {
4813 table = tbl_tx_iqlo_cal_startcoefs;
4814 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4815 }
4816 }
4817 }
4818
2581b143 4819 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4820
4821 if (full) {
4822 if (dev->phy.rev >= 3)
4823 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4824 else
4825 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4826 } else {
4827 if (dev->phy.rev >= 3)
4828 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4829 else
4830 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4831 }
4832
4833 if (mphase) {
4834 count = nphy->mphase_txcal_cmdidx;
4835 numb = min(max,
4836 (u16)(count + nphy->mphase_txcal_numcmds));
4837 } else {
4838 count = 0;
4839 numb = max;
4840 }
4841
4842 for (; count < numb; count++) {
4843 if (full) {
4844 if (dev->phy.rev >= 3)
4845 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4846 else
4847 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4848 } else {
4849 if (dev->phy.rev >= 3)
4850 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4851 else
4852 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4853 }
4854
4855 core = (cmd & 0x3000) >> 12;
4856 type = (cmd & 0x0F00) >> 8;
4857
4858 if (phy6or5x && updated[core] == 0) {
4859 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4860 updated[core] = true;
fb43b8e2
RM		 4861 }
4862
4863 tmp = (params[core].ncorr[type] << 8) | 0x66;
4864 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4865
4866 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4867 buffer[0] = b43_ntab_read(dev,
4868 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4869 diq_start = buffer[0];
4870 buffer[0] = 0;
d41a3552
RM		 4871 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4872 0);
fb43b8e2
RM		 4873 }
4874
4875 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4876 for (i = 0; i < 2000; i++) {
4877 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4878 if (tmp & 0xC000)
4879 break;
4880 udelay(10);
4881 }
4882
9145834e
RM		 4883 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4884 buffer);
2581b143
RM		 4885 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4886 buffer);
fb43b8e2
RM		 4887
4888 if (type == 1 || type == 3 || type == 4)
4889 buffer[0] = diq_start;
4890 }
4891
4892 if (mphase)
4893 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4894
4895 last = (dev->phy.rev < 3) ? 6 : 7;
4896
4897 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4898 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4899 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4900 if (dev->phy.rev < 3) {
4901 buffer[0] = 0;
4902 buffer[1] = 0;
4903 buffer[2] = 0;
4904 buffer[3] = 0;
4905 }
2581b143
RM		 4906 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4907 buffer);
bc53e512 4908 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4909 buffer);
4910 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4911 buffer);
4912 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4913 buffer);
fb43b8e2
RM		 4914 length = 11;
4915 if (dev->phy.rev < 3)
4916 length -= 2;
9145834e
RM		 4917 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4918 nphy->txiqlocal_bestc);
fb43b8e2 4919 nphy->txiqlocal_coeffsvalid = true;
204a665b 4920 nphy->txiqlocal_chanspec.center_freq =
39e971ef 4921 phy->chandef->chan->center_freq;
204a665b 4922 nphy->txiqlocal_chanspec.channel_type =
427fa00b 4923 cfg80211_get_chandef_type(phy->chandef);
fb43b8e2
RM		 4924 } else {
4925 length = 11;
4926 if (dev->phy.rev < 3)
4927 length -= 2;
9145834e
RM		 4928 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4929 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4930 }
4931
53ae8e8c 4932 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4933 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4934 }
4935
e53de674 4936 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4937 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4938
4939 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4940 b43_nphy_tx_iq_workaround(dev);
4941
4942 if (dev->phy.rev >= 4)
4943 nphy->hang_avoid = avoid;
4944
4945 b43_nphy_stay_in_carrier_search(dev, false);
4946
4947 return error;
4948}
4949
984ff4ff
RM		 4950/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4951static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4952{
4953 struct b43_phy_n *nphy = dev->phy.n;
4954 u8 i;
4955 u16 buffer[7];
4956 bool equal = true;
4957
902db91d 4958 if (!nphy->txiqlocal_coeffsvalid ||
39e971ef 4959 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
427fa00b 4960 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef))
984ff4ff
RM		 4961 return;
4962
4963 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4964 for (i = 0; i < 4; i++) {
4965 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4966 equal = false;
4967 break;
4968 }
4969 }
4970
4971 if (!equal) {
4972 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4973 nphy->txiqlocal_bestc);
4974 for (i = 0; i < 4; i++)
4975 buffer[i] = 0;
4976 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4977 buffer);
4978 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4979 &nphy->txiqlocal_bestc[5]);
4980 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4981 &nphy->txiqlocal_bestc[5]);
4982 }
4983}
4984
15931e31
RM		 4985/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4986static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4987 struct nphy_txgains target, u8 type, bool debug)
4988{
4989 struct b43_phy_n *nphy = dev->phy.n;
4990 int i, j, index;
4991 u8 rfctl[2];
4992 u8 afectl_core;
4993 u16 tmp[6];
c7455cf9 4994 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4995 u32 real, imag;
4996 enum ieee80211_band band;
4997
4998 u8 use;
4999 u16 cur_hpf;
5000 u16 lna[3] = { 3, 3, 1 };
5001 u16 hpf1[3] = { 7, 2, 0 };
5002 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 5003 u32 power[3] = { };
15931e31
RM		 5004 u16 gain_save[2];
5005 u16 cal_gain[2];
5006 struct nphy_iqcal_params cal_params[2];
5007 struct nphy_iq_est est;
5008 int ret = 0;
5009 bool playtone = true;
5010 int desired = 13;
5011
5012 b43_nphy_stay_in_carrier_search(dev, 1);
5013
5014 if (dev->phy.rev < 2)
984ff4ff 5015 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 5016 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5017 for (i = 0; i < 2; i++) {
5018 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
5019 cal_gain[i] = cal_params[i].cal_gain;
5020 }
2581b143 5021 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 5022
5023 for (i = 0; i < 2; i++) {
5024 if (i == 0) {
5025 rfctl[0] = B43_NPHY_RFCTL_INTC1;
5026 rfctl[1] = B43_NPHY_RFCTL_INTC2;
5027 afectl_core = B43_NPHY_AFECTL_C1;
5028 } else {
5029 rfctl[0] = B43_NPHY_RFCTL_INTC2;
5030 rfctl[1] = B43_NPHY_RFCTL_INTC1;
5031 afectl_core = B43_NPHY_AFECTL_C2;
5032 }
5033
5034 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
5035 tmp[2] = b43_phy_read(dev, afectl_core);
5036 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5037 tmp[4] = b43_phy_read(dev, rfctl[0]);
5038 tmp[5] = b43_phy_read(dev, rfctl[1]);
5039
5040 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 5041 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 5042 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
5043 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
5044 (1 - i));
5045 b43_phy_set(dev, afectl_core, 0x0006);
5046 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
5047
5048 band = b43_current_band(dev->wl);
5049
5050 if (nphy->rxcalparams & 0xFF000000) {
5051 if (band == IEEE80211_BAND_5GHZ)
5052 b43_phy_write(dev, rfctl[0], 0x140);
5053 else
5054 b43_phy_write(dev, rfctl[0], 0x110);
5055 } else {
5056 if (band == IEEE80211_BAND_5GHZ)
5057 b43_phy_write(dev, rfctl[0], 0x180);
5058 else
5059 b43_phy_write(dev, rfctl[0], 0x120);
5060 }
5061
5062 if (band == IEEE80211_BAND_5GHZ)
5063 b43_phy_write(dev, rfctl[1], 0x148);
5064 else
5065 b43_phy_write(dev, rfctl[1], 0x114);
5066
5067 if (nphy->rxcalparams & 0x10000) {
5068 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
5069 (i + 1));
5070 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
5071 (2 - i));
5072 }
5073
30115c22 5074 for (j = 0; j < 4; j++) {
15931e31
RM		 5075 if (j < 3) {
5076 cur_lna = lna[j];
5077 cur_hpf1 = hpf1[j];
5078 cur_hpf2 = hpf2[j];
5079 } else {
5080 if (power[1] > 10000) {
5081 use = 1;
5082 cur_hpf = cur_hpf1;
5083 index = 2;
5084 } else {
5085 if (power[0] > 10000) {
5086 use = 1;
5087 cur_hpf = cur_hpf1;
5088 index = 1;
5089 } else {
5090 index = 0;
5091 use = 2;
5092 cur_hpf = cur_hpf2;
5093 }
5094 }
5095 cur_lna = lna[index];
5096 cur_hpf1 = hpf1[index];
5097 cur_hpf2 = hpf2[index];
5098 cur_hpf += desired - hweight32(power[index]);
5099 cur_hpf = clamp_val(cur_hpf, 0, 10);
5100 if (use == 1)
5101 cur_hpf1 = cur_hpf;
5102 else
5103 cur_hpf2 = cur_hpf;
5104 }
5105
5106 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
5107 (cur_lna << 2));
78ae7532 5108 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 5109 false);
de9a47f9 5110 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 5111 b43_nphy_stop_playback(dev);
15931e31
RM		 5112
5113 if (playtone) {
59af099b
RM		 5114 ret = b43_nphy_tx_tone(dev, 4000,
5115 (nphy->rxcalparams & 0xFFFF),
ed03033e 5116 false, false, true);
15931e31
RM		 5117 playtone = false;
5118 } else {
ed03033e
RM		 5119 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false,
5120 false, true);
15931e31
RM		 5121 }
5122
5123 if (ret == 0) {
5124 if (j < 3) {
5125 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
5126 false);
5127 if (i == 0) {
5128 real = est.i0_pwr;
5129 imag = est.q0_pwr;
5130 } else {
5131 real = est.i1_pwr;
5132 imag = est.q1_pwr;
5133 }
5134 power[i] = ((real + imag) / 1024) + 1;
5135 } else {
5136 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
5137 }
53ae8e8c 5138 b43_nphy_stop_playback(dev);
15931e31
RM		 5139 }
5140
5141 if (ret != 0)
5142 break;
5143 }
5144
5145 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5146 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5147 b43_phy_write(dev, rfctl[1], tmp[5]);
5148 b43_phy_write(dev, rfctl[0], tmp[4]);
5149 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5150 b43_phy_write(dev, afectl_core, tmp[2]);
5151 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5152
5153 if (ret != 0)
5154 break;
5155 }
5156
78ae7532 5157 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 5158 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 5159 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5160
5161 b43_nphy_stay_in_carrier_search(dev, 0);
5162
5163 return ret;
5164}
5165
5166static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5167 struct nphy_txgains target, u8 type, bool debug)
5168{
5169 return -1;
5170}
5171
5172/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5173static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5174 struct nphy_txgains target, u8 type, bool debug)
5175{
5176 if (dev->phy.rev >= 3)
5177 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5178 else
5179 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5180}
5181
4e687b22
GS		 5182/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5183static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5184{
5185 struct b43_phy *phy = &dev->phy;
5186 struct b43_phy_n *nphy = phy->n;
0b81c23d 5187 /* u16 buf[16]; it's rev3+ */
4e687b22 5188
049fbfee
RM		 5189 nphy->phyrxchain = mask;
5190
4e687b22
GS		 5191 if (0 /* FIXME clk */)
5192 return;
5193
5194 b43_mac_suspend(dev);
5195
5196 if (nphy->hang_avoid)
5197 b43_nphy_stay_in_carrier_search(dev, true);
5198
5199 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5200 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5201
049fbfee 5202 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 5203 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5204 if (dev->phy.rev >= 3) {
5205 /* TODO */
5206 }
5207 } else {
5208 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5209 if (dev->phy.rev >= 3) {
5210 /* TODO */
5211 }
5212 }
5213
5214 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5215
5216 if (nphy->hang_avoid)
5217 b43_nphy_stay_in_carrier_search(dev, false);
5218
5219 b43_mac_enable(dev);
5220}
5221
104cfa88
RM		 5222/**************************************************
5223 * N-PHY init
5224 **************************************************/
5225
104cfa88
RM		 5226/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5227static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5228{
5229 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5230
5231 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5232 if (preamble == 1)
5233 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5234 else
5235 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5236
5237 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5238}
5239
5240/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5241static void b43_nphy_bphy_init(struct b43_wldev *dev)
5242{
5243 unsigned int i;
5244 u16 val;
5245
5246 val = 0x1E1F;
5247 for (i = 0; i < 16; i++) {
5248 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5249 val -= 0x202;
5250 }
5251 val = 0x3E3F;
5252 for (i = 0; i < 16; i++) {
5253 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5254 val -= 0x202;
5255 }
5256 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5257}
5258
5259/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5260static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5261{
5262 if (dev->phy.rev >= 3) {
5263 if (!init)
5264 return;
5265 if (0 /* FIXME */) {
5266 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5267 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5268 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5269 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5270 }
5271 } else {
5272 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5273 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5274
5275 switch (dev->dev->bus_type) {
5276#ifdef CONFIG_B43_BCMA
5277 case B43_BUS_BCMA:
5278 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5279 0xFC00, 0xFC00);
5280 break;
5281#endif
5282#ifdef CONFIG_B43_SSB
5283 case B43_BUS_SSB:
5284 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5285 0xFC00, 0xFC00);
5286 break;
5287#endif
5288 }
5289
5056635c
RM		 5290 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5291 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5292 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5293 0);
104cfa88
RM		 5294
5295 if (init) {
5296 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5297 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5298 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5299 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5300 }
5301 }
5302}
5303
5304/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5305static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5306{
0581483a 5307 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5308 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5309 struct b43_phy_n *nphy = phy->n;
5310 u8 tx_pwr_state;
5311 struct nphy_txgains target;
95b66bad 5312 u16 tmp;
0988a7a1
RM		 5313 enum ieee80211_band tmp2;
5314 bool do_rssi_cal;
5315
5316 u16 clip[2];
5317 bool do_cal = false;
95b66bad 5318
0988a7a1 5319 if ((dev->phy.rev >= 3) &&
0581483a 5320 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5321 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5322 switch (dev->dev->bus_type) {
42c9a458
RM		 5323#ifdef CONFIG_B43_BCMA
5324 case B43_BUS_BCMA:
5325 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5326 BCMA_CC_CHIPCTL, 0x40);
5327 break;
5328#endif
6cbab0d9
RM		 5329#ifdef CONFIG_B43_SSB
5330 case B43_BUS_SSB:
5331 chipco_set32(&dev->dev->sdev->bus->chipco,
5332 SSB_CHIPCO_CHIPCTL, 0x40);
5333 break;
5334#endif
5335 }
0988a7a1
RM		 5336 }
5337 nphy->deaf_count = 0;
95b66bad 5338 b43_nphy_tables_init(dev);
0988a7a1
RM		 5339 nphy->crsminpwr_adjusted = false;
5340 nphy->noisevars_adjusted = false;
95b66bad
MB		 5341
5342 /* Clear all overrides */
0988a7a1
RM		 5343 if (dev->phy.rev >= 3) {
5344 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5345 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5346 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5347 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5348 } else {
5349 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5350 }
95b66bad
MB		 5351 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5352 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5353 if (dev->phy.rev < 6) {
5354 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5355 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5356 }
95b66bad
MB		 5357 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5358 ~(B43_NPHY_RFSEQMODE_CAOVER |
5359 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5360 if (dev->phy.rev >= 3)
5361 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5362 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5363
0988a7a1
RM		 5364 if (dev->phy.rev <= 2) {
5365 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5366 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5367 ~B43_NPHY_BPHY_CTL3_SCALE,
5368 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5369 }
95b66bad
MB		 5370 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5371 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5372
0eff8fcd 5373 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5374 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5375 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5376 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5377 else
5378 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5379 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5380 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5381 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5382
ad9716e8 5383 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 5384 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5385
5386 if (phy->rev < 2) {
5387 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5388 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5389 }
0988a7a1
RM		 5390
5391 tmp2 = b43_current_band(dev->wl);
c002831a 5392 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5393 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5394 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5395 nphy->papd_epsilon_offset[0] << 7);
5396 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5397 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5398 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5399 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5400 } else if (phy->rev >= 5) {
45ca697e 5401 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5402 }
5403
95b66bad 5404 b43_nphy_workarounds(dev);
95b66bad 5405
0988a7a1 5406 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5407 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5408 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5409 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5410 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5411 b43_phy_force_clock(dev, 0);
0988a7a1 5412
858a1652 5413 b43_mac_phy_clock_set(dev, true);
0988a7a1 5414
e50cbcf6 5415 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5416 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5417 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5418 b43_nphy_pa_override(dev, true);
0988a7a1 5419
bbec398c
RM		 5420 b43_nphy_classifier(dev, 0, 0);
5421 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5422 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5423 b43_nphy_bphy_init(dev);
5424
0988a7a1 5425 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5426 b43_nphy_tx_power_ctrl(dev, false);
5427 b43_nphy_tx_power_fix(dev);
3dda07b6 5428 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5429 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5430 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5431
0988a7a1 5432 if (nphy->phyrxchain != 3)
4e687b22 5433 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5434 if (nphy->mphase_cal_phase_id > 0)
5435 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5436
5437 do_rssi_cal = false;
5438 if (phy->rev >= 3) {
5439 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5440 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5441 else
204a665b 5442 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5443
5444 if (do_rssi_cal)
4cb99775 5445 b43_nphy_rssi_cal(dev);
0988a7a1 5446 else
42e1547e 5447 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5448 } else {
4cb99775 5449 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5450 }
5451
5452 if (!((nphy->measure_hold & 0x6) != 0)) {
5453 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5454 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5455 else
204a665b 5456 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5457
5458 if (nphy->mute)
5459 do_cal = false;
5460
5461 if (do_cal) {
b0022e15 5462 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5463
5464 if (nphy->antsel_type == 2)
8987a9e9 5465 b43_nphy_superswitch_init(dev, true);
0988a7a1 5466 if (nphy->perical != 2) {
90b9738d 5467 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5468 if (phy->rev >= 3) {
5469 nphy->cal_orig_pwr_idx[0] =
5470 nphy->txpwrindex[0].index_internal;
5471 nphy->cal_orig_pwr_idx[1] =
5472 nphy->txpwrindex[1].index_internal;
5473 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5474 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5475 }
e7797bf2
RM		 5476 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5477 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5478 b43_nphy_save_cal(dev);
5479 } else if (nphy->mphase_cal_phase_id == 0)
5480 ;/* N PHY Periodic Calibration with arg 3 */
5481 } else {
5482 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5483 }
5484 }
5485
6dcd9d91 5486 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5487 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5488 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5489 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5490 if (phy->rev >= 3 && phy->rev <= 6)
bc36e994 5491 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
8ac3a2aa 5492 b43_nphy_tx_lpf_bw(dev);
9442e5b5
RM		 5493 if (phy->rev >= 3)
5494 b43_nphy_spur_workaround(dev);
95b66bad 5495
53a6e234 5496 return 0;
424047e6 5497}
ef1a628d 5498
104cfa88
RM		 5499/**************************************************
5500 * Channel switching ops.
5501 **************************************************/
5502
5503static void b43_chantab_phy_upload(struct b43_wldev *dev,
5504 const struct b43_phy_n_sfo_cfg *e)
5505{
5506 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5507 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5508 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5509 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5510 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5511 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5512}
5513
49d55cef
RM		 5514/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5515static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5516{
d66be829
RM		 5517 switch (dev->dev->bus_type) {
5518#ifdef CONFIG_B43_BCMA
5519 case B43_BUS_BCMA:
9b383672
HM		 5520 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5521 avoid);
d66be829 5522 break;
8b1fdb53 5523#endif
d66be829
RM		 5524#ifdef CONFIG_B43_SSB
5525 case B43_BUS_SSB:
46fc4c90
RM		 5526 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5527 avoid);
d66be829
RM		 5528 break;
5529#endif
5530 }
49d55cef
RM		 5531}
5532
1b69ec7b 5533/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5534static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5535 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5536 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5537{
5538 struct b43_phy *phy = &dev->phy;
5539 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5540 int ch = new_channel->hw_value;
1b69ec7b 5541
087de74a 5542 u16 old_band_5ghz;
12cd43c6 5543 u16 tmp16;
1b69ec7b 5544
087de74a
RM		 5545 old_band_5ghz =
5546 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5547 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 5548 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5549 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 5550 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 5551 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 5552 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5553 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 5554 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 5555 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5556 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 5557 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 5558 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 5559 }
5560
5561 b43_chantab_phy_upload(dev, e);
5562
a656b6a9 5563 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5564 b43_nphy_classifier(dev, 2, 0);
5565 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5566 } else {
5567 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5568 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5569 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5570 }
5571
161d540c 5572 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5573 b43_nphy_tx_power_fix(dev);
5574
5575 if (dev->phy.rev < 3)
5576 b43_nphy_adjust_lna_gain_table(dev);
5577
8ac3a2aa 5578 b43_nphy_tx_lpf_bw(dev);
1b69ec7b 5579
49d55cef
RM		 5580 if (dev->phy.rev >= 3 &&
5581 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5582 bool avoid = false;
5583 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5584 avoid = true;
427fa00b 5585 } else if (!b43_is_40mhz(dev)) {
49d55cef
RM		 5586 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5587 avoid = true;
5588 } else { /* 40MHz */
5589 if (nphy->aband_spurwar_en &&
5590 (ch == 38 || ch == 102 || ch == 118))
5591 avoid = dev->dev->chip_id == 0x4716;
5592 }
5593
5594 b43_nphy_pmu_spur_avoid(dev, avoid);
5595
5596 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5597 dev->dev->chip_id == 43225) {
5598 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5599 avoid ? 0x5341 : 0x8889);
5600 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5601 }
5602
5603 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5604 ; /* TODO: reset PLL */
5605
5606 if (avoid)
5607 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5608 else
5609 b43_phy_mask(dev, B43_NPHY_BBCFG,
5610 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5611
5612 b43_nphy_reset_cca(dev);
5613
5614 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5615 }
5616
5617 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5618
5619 if (phy->rev >= 3)
5620 b43_nphy_spur_workaround(dev);
5621}
5622
eff66c51 5623/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5624static int b43_nphy_set_channel(struct b43_wldev *dev,
5625 struct ieee80211_channel *channel,
5626 enum nl80211_channel_type channel_type)
eff66c51 5627{
a656b6a9 5628 struct b43_phy *phy = &dev->phy;
eff66c51 5629
2eeb6fd0
JL		 5630 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5631 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
fe255b40
RM		 5632 const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL;
5633 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL;
eff66c51
RM		 5634
5635 u8 tmp;
eff66c51 5636
fe255b40
RM		 5637 if (phy->rev >= 7) {
5638 r2057_get_chantabent_rev7(dev, channel->center_freq,
5639 &tabent_r7, &tabent_r7_2g);
5640 if (!tabent_r7 && !tabent_r7_2g)
5641 return -ESRCH;
5642 } else if (phy->rev >= 3) {
f2a6d6a0
RM		 5643 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5644 channel->center_freq);
f19ebe7d
RM		 5645 if (!tabent_r3)
5646 return -ESRCH;
ffd2d9bd 5647 } else {
a656b6a9
RM		 5648 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5649 channel->hw_value);
f19ebe7d 5650 if (!tabent_r2)
ffd2d9bd 5651 return -ESRCH;
eff66c51
RM		 5652 }
5653
204a665b
RM		 5654 /* Channel is set later in common code, but we need to set it on our
5655 own to let this function's subcalls work properly. */
5656 phy->channel = channel->hw_value;
eff66c51 5657
427fa00b 5658#if 0
e5c407f9
RM		 5659 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5660 b43_channel_type_is_40mhz(channel_type))
5661 ; /* TODO: BMAC BW Set (channel_type) */
427fa00b 5662#endif
eff66c51 5663
fe255b40
RM		 5664 if (channel_type == NL80211_CHAN_HT40PLUS) {
5665 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20);
5666 if (phy->rev >= 7)
5667 b43_phy_set(dev, 0x310, 0x8000);
5668 } else if (channel_type == NL80211_CHAN_HT40MINUS) {
5669 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20);
5670 if (phy->rev >= 7)
5671 b43_phy_mask(dev, 0x310, (u16)~0x8000);
5672 }
eff66c51 5673
fe255b40
RM		 5674 if (phy->rev >= 7) {
5675 const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ?
5676 &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs);
5677
5678 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
5679 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 2 : 0;
5680 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp);
5681 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp);
5682 }
5683
5684 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g);
5685 b43_nphy_channel_setup(dev, phy_regs, channel);
5686 } else if (phy->rev >= 3) {
a656b6a9 5687 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5688 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5689 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5690 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5691 } else {
a656b6a9 5692 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5693 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5694 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5695 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5696 }
5697
5698 return 0;
5699}
5700
104cfa88
RM		 5701/**************************************************
5702 * Basic PHY ops.
5703 **************************************************/
5704
ef1a628d
MB		 5705static int b43_nphy_op_allocate(struct b43_wldev *dev)
5706{
5707 struct b43_phy_n *nphy;
5708
5709 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5710 if (!nphy)
5711 return -ENOMEM;
5712 dev->phy.n = nphy;
5713
ef1a628d
MB		 5714 return 0;
5715}
5716
fb11137a 5717static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5718{
fb11137a
MB		 5719 struct b43_phy *phy = &dev->phy;
5720 struct b43_phy_n *nphy = phy->n;
c7d64310 5721 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5722
fb11137a 5723 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5724
aca434d3 5725 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5726 nphy->spur_avoid = (phy->rev >= 3) ?
5727 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
0b81c23d
RM		 5728 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5729 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5730 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5731 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5732 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5733 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5734 nphy->tx_pwr_idx[0] = 128;
5735 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5736
5737 /* Hardware TX power control and 5GHz power gain */
5738 nphy->txpwrctrl = false;
5739 nphy->pwg_gain_5ghz = false;
5740 if (dev->phy.rev >= 3 ||
5741 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5742 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5743 nphy->txpwrctrl = true;
5744 nphy->pwg_gain_5ghz = true;
5745 } else if (sprom->revision >= 4) {
5746 if (dev->phy.rev >= 2 &&
5747 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5748 nphy->txpwrctrl = true;
5749#ifdef CONFIG_B43_SSB
5750 if (dev->dev->bus_type == B43_BUS_SSB &&
5751 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5752 struct pci_dev *pdev =
5753 dev->dev->sdev->bus->host_pci;
5754 if (pdev->device == 0x4328 ||
5755 pdev->device == 0x432a)
5756 nphy->pwg_gain_5ghz = true;
5757 }
5758#endif
5759 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5760 nphy->pwg_gain_5ghz = true;
5761 }
5762 }
5763
5764 if (dev->phy.rev >= 3) {
5765 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5766 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5767 }
ef1a628d
MB		 5768}
5769
fb11137a 5770static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5771{
fb11137a
MB		 5772 struct b43_phy *phy = &dev->phy;
5773 struct b43_phy_n *nphy = phy->n;
ef1a628d 5774
ef1a628d 5775 kfree(nphy);
fb11137a
MB		 5776 phy->n = NULL;
5777}
5778
5779static int b43_nphy_op_init(struct b43_wldev *dev)
5780{
5781 return b43_phy_initn(dev);
ef1a628d
MB		 5782}
5783
5784static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5785{
5786#if B43_DEBUG
5787 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5788 /* OFDM registers are onnly available on A/G-PHYs */
5789 b43err(dev->wl, "Invalid OFDM PHY access at "
5790 "0x%04X on N-PHY\n", offset);
5791 dump_stack();
5792 }
5793 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5794 /* Ext-G registers are only available on G-PHYs */
5795 b43err(dev->wl, "Invalid EXT-G PHY access at "
5796 "0x%04X on N-PHY\n", offset);
5797 dump_stack();
5798 }
5799#endif /* B43_DEBUG */
5800}
5801
5802static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5803{
5804 check_phyreg(dev, reg);
5805 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5806 return b43_read16(dev, B43_MMIO_PHY_DATA);
5807}
5808
5809static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5810{
5811 check_phyreg(dev, reg);
5812 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5813 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5814}
5815
755fd183
RM		 5816static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5817 u16 set)
5818{
5819 check_phyreg(dev, reg);
5820 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5821 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5822}
5823
ef1a628d
MB		 5824static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5825{
5826 /* Register 1 is a 32-bit register. */
5827 B43_WARN_ON(reg == 1);
a6aa05d6
RM		 5828
5829 if (dev->phy.rev >= 7)
5830 reg |= 0x200; /* Radio 0x2057 */
5831 else
5832 reg |= 0x100;
ef1a628d
MB		 5833
5834 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5835 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5836}
5837
5838static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5839{
5840 /* Register 1 is a 32-bit register. */
5841 B43_WARN_ON(reg == 1);
5842
5843 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5844 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5845}
5846
c2b7aefd 5847/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5848static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5849 bool blocked)
c2b7aefd
RM		 5850{
5851 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5852 b43err(dev->wl, "MAC not suspended\n");
5853
5854 if (blocked) {
5855 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5856 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5857 if (dev->phy.rev >= 7) {
5858 /* TODO */
5859 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5860 b43_radio_mask(dev, 0x09, ~0x2);
5861
5862 b43_radio_write(dev, 0x204D, 0);
5863 b43_radio_write(dev, 0x2053, 0);
5864 b43_radio_write(dev, 0x2058, 0);
5865 b43_radio_write(dev, 0x205E, 0);
5866 b43_radio_mask(dev, 0x2062, ~0xF0);
5867 b43_radio_write(dev, 0x2064, 0);
5868
5869 b43_radio_write(dev, 0x304D, 0);
5870 b43_radio_write(dev, 0x3053, 0);
5871 b43_radio_write(dev, 0x3058, 0);
5872 b43_radio_write(dev, 0x305E, 0);
5873 b43_radio_mask(dev, 0x3062, ~0xF0);
5874 b43_radio_write(dev, 0x3064, 0);
5875 }
5876 } else {
572d37a4 5877 if (dev->phy.rev >= 7) {
6fe55143
RM		 5878 if (!dev->phy.radio_on)
5879 b43_radio_2057_init(dev);
572d37a4
RM		 5880 b43_switch_channel(dev, dev->phy.channel);
5881 } else if (dev->phy.rev >= 3) {
6fe55143
RM		 5882 if (!dev->phy.radio_on)
5883 b43_radio_init2056(dev);
78159788 5884 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5885 } else {
5886 b43_radio_init2055(dev);
5887 }
5888 }
ef1a628d
MB		 5889}
5890
0f4091b9 5891/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5892static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5893{
2a870831
RM		 5894 u16 override = on ? 0x0 : 0x7FFF;
5895 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5896
2a870831
RM		 5897 if (dev->phy.rev >= 3) {
5898 if (on) {
5899 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5900 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5901 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5902 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5903 } else {
5904 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5905 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5906 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5907 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5908 }
5909 } else {
5910 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5911 }
cb24f57f
MB		 5912}
5913
ef1a628d
MB		 5914static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5915 unsigned int new_channel)
5916{
675a0b04
KB		 5917 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5918 enum nl80211_channel_type channel_type =
5919 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5920
ef1a628d
MB		 5921 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5922 if ((new_channel < 1) || (new_channel > 14))
5923 return -EINVAL;
5924 } else {
5925 if (new_channel > 200)
5926 return -EINVAL;
5927 }
5928
a656b6a9 5929 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5930}
5931
5932static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5933{
5934 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5935 return 1;
5936 return 36;
5937}
5938
ef1a628d
MB		 5939const struct b43_phy_operations b43_phyops_n = {
5940 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5941 .free = b43_nphy_op_free,
5942 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5943 .init = b43_nphy_op_init,
ef1a628d
MB		 5944 .phy_read = b43_nphy_op_read,
5945 .phy_write = b43_nphy_op_write,
755fd183 5946 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5947 .radio_read = b43_nphy_op_radio_read,
5948 .radio_write = b43_nphy_op_radio_write,
5949 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5950 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5951 .switch_channel = b43_nphy_op_switch_channel,
5952 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5953 .recalc_txpower = b43_nphy_op_recalc_txpower,
5954 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5955};
Linux kernel - Deliverables
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