b43: HT-PHY: init: init BPHY and upload 0x1a table
[deliverable/linux.git] / drivers / net / wireless / b43 / pio.c
CommitLineData
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1/*
2
3 Broadcom B43 wireless driver
4
5 PIO data transfer
6
eb032b98 7 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
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8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
26#include "b43.h"
27#include "pio.h"
28#include "dma.h"
29#include "main.h"
30#include "xmit.h"
31
32#include <linux/delay.h>
d43c36dc 33#include <linux/sched.h>
5a0e3ad6 34#include <linux/slab.h>
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35
36
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37static u16 generate_cookie(struct b43_pio_txqueue *q,
38 struct b43_pio_txpacket *pack)
39{
40 u16 cookie;
41
42 /* Use the upper 4 bits of the cookie as
43 * PIO controller ID and store the packet index number
44 * in the lower 12 bits.
45 * Note that the cookie must never be 0, as this
46 * is a special value used in RX path.
47 * It can also not be 0xFFFF because that is special
48 * for multicast frames.
49 */
50 cookie = (((u16)q->index + 1) << 12);
51 cookie |= pack->index;
52
53 return cookie;
54}
55
56static
99da185a
JD
57struct b43_pio_txqueue *parse_cookie(struct b43_wldev *dev,
58 u16 cookie,
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59 struct b43_pio_txpacket **pack)
60{
61 struct b43_pio *pio = &dev->pio;
62 struct b43_pio_txqueue *q = NULL;
63 unsigned int pack_index;
64
65 switch (cookie & 0xF000) {
66 case 0x1000:
67 q = pio->tx_queue_AC_BK;
68 break;
69 case 0x2000:
70 q = pio->tx_queue_AC_BE;
71 break;
72 case 0x3000:
73 q = pio->tx_queue_AC_VI;
74 break;
75 case 0x4000:
76 q = pio->tx_queue_AC_VO;
77 break;
78 case 0x5000:
79 q = pio->tx_queue_mcast;
80 break;
81 }
82 if (B43_WARN_ON(!q))
83 return NULL;
84 pack_index = (cookie & 0x0FFF);
85 if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets)))
86 return NULL;
87 *pack = &q->packets[pack_index];
88
89 return q;
90}
91
92static u16 index_to_pioqueue_base(struct b43_wldev *dev,
93 unsigned int index)
94{
95 static const u16 bases[] = {
96 B43_MMIO_PIO_BASE0,
97 B43_MMIO_PIO_BASE1,
98 B43_MMIO_PIO_BASE2,
99 B43_MMIO_PIO_BASE3,
100 B43_MMIO_PIO_BASE4,
101 B43_MMIO_PIO_BASE5,
102 B43_MMIO_PIO_BASE6,
103 B43_MMIO_PIO_BASE7,
104 };
105 static const u16 bases_rev11[] = {
106 B43_MMIO_PIO11_BASE0,
107 B43_MMIO_PIO11_BASE1,
108 B43_MMIO_PIO11_BASE2,
109 B43_MMIO_PIO11_BASE3,
110 B43_MMIO_PIO11_BASE4,
111 B43_MMIO_PIO11_BASE5,
112 };
113
21d889d4 114 if (dev->dev->core_rev >= 11) {
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115 B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
116 return bases_rev11[index];
117 }
118 B43_WARN_ON(index >= ARRAY_SIZE(bases));
119 return bases[index];
120}
121
122static u16 pio_txqueue_offset(struct b43_wldev *dev)
123{
21d889d4 124 if (dev->dev->core_rev >= 11)
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125 return 0x18;
126 return 0;
127}
128
129static u16 pio_rxqueue_offset(struct b43_wldev *dev)
130{
21d889d4 131 if (dev->dev->core_rev >= 11)
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132 return 0x38;
133 return 8;
134}
135
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136static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
137 unsigned int index)
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138{
139 struct b43_pio_txqueue *q;
140 struct b43_pio_txpacket *p;
141 unsigned int i;
142
143 q = kzalloc(sizeof(*q), GFP_KERNEL);
144 if (!q)
145 return NULL;
5100d5ac 146 q->dev = dev;
21d889d4 147 q->rev = dev->dev->core_rev;
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148 q->mmio_base = index_to_pioqueue_base(dev, index) +
149 pio_txqueue_offset(dev);
150 q->index = index;
151
152 q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS;
153 if (q->rev >= 8) {
154 q->buffer_size = 1920; //FIXME this constant is wrong.
155 } else {
156 q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE);
157 q->buffer_size -= 80;
158 }
159
160 INIT_LIST_HEAD(&q->packets_list);
161 for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
162 p = &(q->packets[i]);
163 INIT_LIST_HEAD(&p->list);
164 p->index = i;
165 p->queue = q;
166 list_add(&p->list, &q->packets_list);
167 }
168
169 return q;
170}
171
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172static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
173 unsigned int index)
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174{
175 struct b43_pio_rxqueue *q;
176
177 q = kzalloc(sizeof(*q), GFP_KERNEL);
178 if (!q)
179 return NULL;
5100d5ac 180 q->dev = dev;
21d889d4 181 q->rev = dev->dev->core_rev;
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182 q->mmio_base = index_to_pioqueue_base(dev, index) +
183 pio_rxqueue_offset(dev);
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184
185 /* Enable Direct FIFO RX (PIO) on the engine. */
186 b43_dma_direct_fifo_rx(dev, index, 1);
187
188 return q;
189}
190
191static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q)
192{
193 struct b43_pio_txpacket *pack;
194 unsigned int i;
195
196 for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
197 pack = &(q->packets[i]);
198 if (pack->skb) {
199 dev_kfree_skb_any(pack->skb);
200 pack->skb = NULL;
201 }
202 }
203}
204
205static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q,
206 const char *name)
207{
208 if (!q)
209 return;
210 b43_pio_cancel_tx_packets(q);
211 kfree(q);
212}
213
214static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q,
215 const char *name)
216{
217 if (!q)
218 return;
219 kfree(q);
220}
221
222#define destroy_queue_tx(pio, queue) do { \
223 b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \
224 (pio)->queue = NULL; \
225 } while (0)
226
227#define destroy_queue_rx(pio, queue) do { \
228 b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \
229 (pio)->queue = NULL; \
230 } while (0)
231
232void b43_pio_free(struct b43_wldev *dev)
233{
234 struct b43_pio *pio;
235
236 if (!b43_using_pio_transfers(dev))
237 return;
238 pio = &dev->pio;
239
240 destroy_queue_rx(pio, rx_queue);
241 destroy_queue_tx(pio, tx_queue_mcast);
242 destroy_queue_tx(pio, tx_queue_AC_VO);
243 destroy_queue_tx(pio, tx_queue_AC_VI);
244 destroy_queue_tx(pio, tx_queue_AC_BE);
245 destroy_queue_tx(pio, tx_queue_AC_BK);
246}
247
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248int b43_pio_init(struct b43_wldev *dev)
249{
250 struct b43_pio *pio = &dev->pio;
251 int err = -ENOMEM;
252
253 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
254 & ~B43_MACCTL_BE);
255 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0);
256
257 pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0);
258 if (!pio->tx_queue_AC_BK)
259 goto out;
260
261 pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1);
262 if (!pio->tx_queue_AC_BE)
263 goto err_destroy_bk;
264
265 pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2);
266 if (!pio->tx_queue_AC_VI)
267 goto err_destroy_be;
268
269 pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3);
270 if (!pio->tx_queue_AC_VO)
271 goto err_destroy_vi;
272
273 pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4);
274 if (!pio->tx_queue_mcast)
275 goto err_destroy_vo;
276
277 pio->rx_queue = b43_setup_pioqueue_rx(dev, 0);
278 if (!pio->rx_queue)
279 goto err_destroy_mcast;
280
281 b43dbg(dev->wl, "PIO initialized\n");
282 err = 0;
283out:
284 return err;
285
286err_destroy_mcast:
287 destroy_queue_tx(pio, tx_queue_mcast);
288err_destroy_vo:
289 destroy_queue_tx(pio, tx_queue_AC_VO);
290err_destroy_vi:
291 destroy_queue_tx(pio, tx_queue_AC_VI);
292err_destroy_be:
293 destroy_queue_tx(pio, tx_queue_AC_BE);
294err_destroy_bk:
295 destroy_queue_tx(pio, tx_queue_AC_BK);
296 return err;
297}
298
299/* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */
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300static struct b43_pio_txqueue *select_queue_by_priority(struct b43_wldev *dev,
301 u8 queue_prio)
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302{
303 struct b43_pio_txqueue *q;
304
403a3a13 305 if (dev->qos_enabled) {
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306 /* 0 = highest priority */
307 switch (queue_prio) {
308 default:
309 B43_WARN_ON(1);
310 /* fallthrough */
311 case 0:
312 q = dev->pio.tx_queue_AC_VO;
313 break;
314 case 1:
315 q = dev->pio.tx_queue_AC_VI;
316 break;
317 case 2:
318 q = dev->pio.tx_queue_AC_BE;
319 break;
320 case 3:
321 q = dev->pio.tx_queue_AC_BK;
322 break;
323 }
324 } else
325 q = dev->pio.tx_queue_AC_BE;
326
327 return q;
328}
329
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330static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q,
331 u16 ctl,
332 const void *_data,
333 unsigned int data_len)
5100d5ac 334{
d8c17e15 335 struct b43_wldev *dev = q->dev;
7e937c63 336 struct b43_wl *wl = dev->wl;
5100d5ac 337 const u8 *data = _data;
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338
339 ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI;
340 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
341
620d785b 342 b43_block_write(dev, data, (data_len & ~1),
d8c17e15
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343 q->mmio_base + B43_PIO_TXDATA,
344 sizeof(u16));
345 if (data_len & 1) {
88499ab3
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346 u8 *tail = wl->pio_tailspace;
347 BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2);
348
d8c17e15
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349 /* Write the last byte. */
350 ctl &= ~B43_PIO_TXCTL_WRITEHI;
351 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
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352 tail[0] = data[data_len - 1];
353 tail[1] = 0;
620d785b 354 b43_block_write(dev, tail, 2,
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355 q->mmio_base + B43_PIO_TXDATA,
356 sizeof(u16));
5100d5ac 357 }
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358
359 return ctl;
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360}
361
362static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack,
363 const u8 *hdr, unsigned int hdrlen)
364{
365 struct b43_pio_txqueue *q = pack->queue;
366 const char *frame = pack->skb->data;
367 unsigned int frame_len = pack->skb->len;
368 u16 ctl;
369
370 ctl = b43_piotx_read16(q, B43_PIO_TXCTL);
371 ctl |= B43_PIO_TXCTL_FREADY;
372 ctl &= ~B43_PIO_TXCTL_EOF;
373
374 /* Transfer the header data. */
d8c17e15 375 ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen);
5100d5ac 376 /* Transfer the frame data. */
d8c17e15 377 ctl = tx_write_2byte_queue(q, ctl, frame, frame_len);
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378
379 ctl |= B43_PIO_TXCTL_EOF;
380 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
381}
382
d8c17e15
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383static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q,
384 u32 ctl,
385 const void *_data,
386 unsigned int data_len)
5100d5ac 387{
d8c17e15 388 struct b43_wldev *dev = q->dev;
7e937c63 389 struct b43_wl *wl = dev->wl;
5100d5ac 390 const u8 *data = _data;
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391
392 ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 |
393 B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31;
394 b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
395
620d785b 396 b43_block_write(dev, data, (data_len & ~3),
d8c17e15
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397 q->mmio_base + B43_PIO8_TXDATA,
398 sizeof(u32));
399 if (data_len & 3) {
88499ab3
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400 u8 *tail = wl->pio_tailspace;
401 BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4);
402
403 memset(tail, 0, 4);
d8c17e15
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404 /* Write the last few bytes. */
405 ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 |
406 B43_PIO8_TXCTL_24_31);
d8c17e15
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407 switch (data_len & 3) {
408 case 3:
b96ab540 409 ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15;
88499ab3
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410 tail[0] = data[data_len - 3];
411 tail[1] = data[data_len - 2];
412 tail[2] = data[data_len - 1];
b96ab540 413 break;
d8c17e15
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414 case 2:
415 ctl |= B43_PIO8_TXCTL_8_15;
88499ab3
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416 tail[0] = data[data_len - 2];
417 tail[1] = data[data_len - 1];
b96ab540 418 break;
d8c17e15 419 case 1:
88499ab3 420 tail[0] = data[data_len - 1];
b96ab540 421 break;
5100d5ac 422 }
d8c17e15 423 b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
620d785b 424 b43_block_write(dev, tail, 4,
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425 q->mmio_base + B43_PIO8_TXDATA,
426 sizeof(u32));
5100d5ac 427 }
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428
429 return ctl;
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430}
431
432static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
433 const u8 *hdr, unsigned int hdrlen)
434{
435 struct b43_pio_txqueue *q = pack->queue;
436 const char *frame = pack->skb->data;
437 unsigned int frame_len = pack->skb->len;
438 u32 ctl;
439
440 ctl = b43_piotx_read32(q, B43_PIO8_TXCTL);
441 ctl |= B43_PIO8_TXCTL_FREADY;
442 ctl &= ~B43_PIO8_TXCTL_EOF;
443
444 /* Transfer the header data. */
d8c17e15 445 ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen);
5100d5ac 446 /* Transfer the frame data. */
d8c17e15 447 ctl = tx_write_4byte_queue(q, ctl, frame, frame_len);
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448
449 ctl |= B43_PIO8_TXCTL_EOF;
450 b43_piotx_write32(q, B43_PIO_TXCTL, ctl);
451}
452
453static int pio_tx_frame(struct b43_pio_txqueue *q,
e039fa4a 454 struct sk_buff *skb)
5100d5ac 455{
7e937c63
AH
456 struct b43_wldev *dev = q->dev;
457 struct b43_wl *wl = dev->wl;
5100d5ac 458 struct b43_pio_txpacket *pack;
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459 u16 cookie;
460 int err;
461 unsigned int hdrlen;
e039fa4a 462 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
88499ab3 463 struct b43_txhdr *txhdr = (struct b43_txhdr *)wl->pio_scratchspace;
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464
465 B43_WARN_ON(list_empty(&q->packets_list));
466 pack = list_entry(q->packets_list.next,
467 struct b43_pio_txpacket, list);
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468
469 cookie = generate_cookie(q, pack);
7e937c63 470 hdrlen = b43_txhdr_size(dev);
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471 BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(struct b43_txhdr));
472 B43_WARN_ON(sizeof(wl->pio_scratchspace) < hdrlen);
473 err = b43_generate_txhdr(dev, (u8 *)txhdr, skb,
035d0243 474 info, cookie);
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475 if (err)
476 return err;
477
e039fa4a 478 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
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479 /* Tell the firmware about the cookie of the last
480 * mcast frame, so it can clear the more-data bit in it. */
7e937c63 481 b43_shm_write16(dev, B43_SHM_SHARED,
5100d5ac
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482 B43_SHM_SH_MCASTCOOKIE, cookie);
483 }
484
485 pack->skb = skb;
486 if (q->rev >= 8)
88499ab3 487 pio_tx_frame_4byte_queue(pack, (const u8 *)txhdr, hdrlen);
5100d5ac 488 else
88499ab3 489 pio_tx_frame_2byte_queue(pack, (const u8 *)txhdr, hdrlen);
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490
491 /* Remove it from the list of available packet slots.
492 * It will be put back when we receive the status report. */
493 list_del(&pack->list);
494
495 /* Update the queue statistics. */
496 q->buffer_used += roundup(skb->len + hdrlen, 4);
497 q->free_packet_slots -= 1;
498
499 return 0;
500}
501
e039fa4a 502int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
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503{
504 struct b43_pio_txqueue *q;
505 struct ieee80211_hdr *hdr;
5100d5ac
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506 unsigned int hdrlen, total_len;
507 int err = 0;
e039fa4a 508 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
5100d5ac
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509
510 hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a
JB
511
512 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
5100d5ac
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513 /* The multicast queue will be sent after the DTIM. */
514 q = dev->pio.tx_queue_mcast;
515 /* Set the frame More-Data bit. Ucode will clear it
516 * for us on the last frame. */
517 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
518 } else {
519 /* Decide by priority where to put this frame. */
e2530083 520 q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
5100d5ac
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521 }
522
5100d5ac
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523 hdrlen = b43_txhdr_size(dev);
524 total_len = roundup(skb->len + hdrlen, 4);
525
526 if (unlikely(total_len > q->buffer_size)) {
527 err = -ENOBUFS;
528 b43dbg(dev->wl, "PIO: TX packet longer than queue.\n");
637dae3f 529 goto out;
5100d5ac
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530 }
531 if (unlikely(q->free_packet_slots == 0)) {
532 err = -ENOBUFS;
533 b43warn(dev->wl, "PIO: TX packet overflow.\n");
637dae3f 534 goto out;
5100d5ac
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535 }
536 B43_WARN_ON(q->buffer_used > q->buffer_size);
537
538 if (total_len > (q->buffer_size - q->buffer_used)) {
539 /* Not enough memory on the queue. */
540 err = -EBUSY;
e2530083 541 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
5100d5ac 542 q->stopped = 1;
637dae3f 543 goto out;
5100d5ac
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544 }
545
546 /* Assign the queue number to the ring (if not already done before)
547 * so TX status handling can use it. The mac80211-queue to b43-queue
548 * mapping is static, so we don't need to store it per frame. */
e2530083 549 q->queue_prio = skb_get_queue_mapping(skb);
5100d5ac 550
e039fa4a 551 err = pio_tx_frame(q, skb);
5100d5ac
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552 if (unlikely(err == -ENOKEY)) {
553 /* Drop this packet, as we don't have the encryption key
554 * anymore and must not transmit it unencrypted. */
555 dev_kfree_skb_any(skb);
556 err = 0;
637dae3f 557 goto out;
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558 }
559 if (unlikely(err)) {
560 b43err(dev->wl, "PIO transmission failure\n");
637dae3f 561 goto out;
5100d5ac 562 }
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563
564 B43_WARN_ON(q->buffer_used > q->buffer_size);
565 if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
566 (q->free_packet_slots == 0)) {
567 /* The queue is full. */
e2530083 568 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
5100d5ac
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569 q->stopped = 1;
570 }
571
637dae3f 572out:
5100d5ac
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573 return err;
574}
575
5100d5ac
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576void b43_pio_handle_txstatus(struct b43_wldev *dev,
577 const struct b43_txstatus *status)
578{
579 struct b43_pio_txqueue *q;
580 struct b43_pio_txpacket *pack = NULL;
581 unsigned int total_len;
e039fa4a 582 struct ieee80211_tx_info *info;
5100d5ac
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583
584 q = parse_cookie(dev, status->cookie, &pack);
585 if (unlikely(!q))
586 return;
587 B43_WARN_ON(!pack);
588
14a7dd6f 589 info = IEEE80211_SKB_CB(pack->skb);
e039fa4a 590
e6a9854b 591 b43_fill_txstatus_report(dev, info, status);
5100d5ac
MB
592
593 total_len = pack->skb->len + b43_txhdr_size(dev);
594 total_len = roundup(total_len, 4);
595 q->buffer_used -= total_len;
596 q->free_packet_slots += 1;
597
ce6c4a13 598 ieee80211_tx_status(dev->wl->hw, pack->skb);
5100d5ac
MB
599 pack->skb = NULL;
600 list_add(&pack->list, &q->packets_list);
601
602 if (q->stopped) {
603 ieee80211_wake_queue(dev->wl->hw, q->queue_prio);
604 q->stopped = 0;
605 }
5100d5ac
MB
606}
607
5100d5ac
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608/* Returns whether we should fetch another frame. */
609static bool pio_rx_frame(struct b43_pio_rxqueue *q)
610{
d8c17e15 611 struct b43_wldev *dev = q->dev;
7e937c63 612 struct b43_wl *wl = dev->wl;
5100d5ac
MB
613 u16 len;
614 u32 macstat;
615 unsigned int i, padding;
616 struct sk_buff *skb;
617 const char *err_msg = NULL;
88499ab3
MB
618 struct b43_rxhdr_fw4 *rxhdr =
619 (struct b43_rxhdr_fw4 *)wl->pio_scratchspace;
5100d5ac 620
88499ab3
MB
621 BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(*rxhdr));
622 memset(rxhdr, 0, sizeof(*rxhdr));
5100d5ac
MB
623
624 /* Check if we have data and wait for it to get ready. */
625 if (q->rev >= 8) {
626 u32 ctl;
627
628 ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
629 if (!(ctl & B43_PIO8_RXCTL_FRAMERDY))
630 return 0;
631 b43_piorx_write32(q, B43_PIO8_RXCTL,
632 B43_PIO8_RXCTL_FRAMERDY);
633 for (i = 0; i < 10; i++) {
634 ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
635 if (ctl & B43_PIO8_RXCTL_DATARDY)
636 goto data_ready;
637 udelay(10);
638 }
639 } else {
640 u16 ctl;
641
642 ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
643 if (!(ctl & B43_PIO_RXCTL_FRAMERDY))
644 return 0;
645 b43_piorx_write16(q, B43_PIO_RXCTL,
646 B43_PIO_RXCTL_FRAMERDY);
647 for (i = 0; i < 10; i++) {
648 ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
649 if (ctl & B43_PIO_RXCTL_DATARDY)
650 goto data_ready;
651 udelay(10);
652 }
653 }
654 b43dbg(q->dev->wl, "PIO RX timed out\n");
655 return 1;
656data_ready:
657
658 /* Get the preamble (RX header) */
659 if (q->rev >= 8) {
620d785b 660 b43_block_read(dev, rxhdr, sizeof(*rxhdr),
d8c17e15
MB
661 q->mmio_base + B43_PIO8_RXDATA,
662 sizeof(u32));
5100d5ac 663 } else {
620d785b 664 b43_block_read(dev, rxhdr, sizeof(*rxhdr),
d8c17e15
MB
665 q->mmio_base + B43_PIO_RXDATA,
666 sizeof(u16));
5100d5ac
MB
667 }
668 /* Sanity checks. */
88499ab3 669 len = le16_to_cpu(rxhdr->frame_len);
5100d5ac
MB
670 if (unlikely(len > 0x700)) {
671 err_msg = "len > 0x700";
672 goto rx_error;
673 }
674 if (unlikely(len == 0)) {
675 err_msg = "len == 0";
676 goto rx_error;
677 }
678
17030f48
RM
679 switch (dev->fw.hdr_format) {
680 case B43_FW_HDR_598:
681 macstat = le32_to_cpu(rxhdr->format_598.mac_status);
682 break;
683 case B43_FW_HDR_410:
684 case B43_FW_HDR_351:
685 macstat = le32_to_cpu(rxhdr->format_351.mac_status);
686 break;
687 }
5100d5ac
MB
688 if (macstat & B43_RX_MAC_FCSERR) {
689 if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) {
690 /* Drop frames with failed FCS. */
691 err_msg = "Frame FCS error";
692 goto rx_error;
693 }
694 }
695
696 /* We always pad 2 bytes, as that's what upstream code expects
697 * due to the RX-header being 30 bytes. In case the frame is
698 * unaligned, we pad another 2 bytes. */
699 padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
700 skb = dev_alloc_skb(len + padding + 2);
701 if (unlikely(!skb)) {
702 err_msg = "Out of memory";
703 goto rx_error;
704 }
705 skb_reserve(skb, 2);
706 skb_put(skb, len + padding);
707 if (q->rev >= 8) {
620d785b 708 b43_block_read(dev, skb->data + padding, (len & ~3),
d8c17e15
MB
709 q->mmio_base + B43_PIO8_RXDATA,
710 sizeof(u32));
711 if (len & 3) {
88499ab3
MB
712 u8 *tail = wl->pio_tailspace;
713 BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4);
714
d8c17e15 715 /* Read the last few bytes. */
620d785b 716 b43_block_read(dev, tail, 4,
b96ab540
MB
717 q->mmio_base + B43_PIO8_RXDATA,
718 sizeof(u32));
d8c17e15
MB
719 switch (len & 3) {
720 case 3:
88499ab3
MB
721 skb->data[len + padding - 3] = tail[0];
722 skb->data[len + padding - 2] = tail[1];
723 skb->data[len + padding - 1] = tail[2];
b96ab540 724 break;
d8c17e15 725 case 2:
88499ab3
MB
726 skb->data[len + padding - 2] = tail[0];
727 skb->data[len + padding - 1] = tail[1];
b96ab540 728 break;
d8c17e15 729 case 1:
88499ab3 730 skb->data[len + padding - 1] = tail[0];
b96ab540 731 break;
d8c17e15 732 }
5100d5ac
MB
733 }
734 } else {
620d785b 735 b43_block_read(dev, skb->data + padding, (len & ~1),
d8c17e15
MB
736 q->mmio_base + B43_PIO_RXDATA,
737 sizeof(u16));
738 if (len & 1) {
88499ab3
MB
739 u8 *tail = wl->pio_tailspace;
740 BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2);
741
d8c17e15 742 /* Read the last byte. */
620d785b 743 b43_block_read(dev, tail, 2,
b96ab540
MB
744 q->mmio_base + B43_PIO_RXDATA,
745 sizeof(u16));
88499ab3 746 skb->data[len + padding - 1] = tail[0];
5100d5ac
MB
747 }
748 }
749
88499ab3 750 b43_rx(q->dev, skb, rxhdr);
5100d5ac
MB
751
752 return 1;
753
754rx_error:
755 if (err_msg)
756 b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg);
c286181d
MB
757 if (q->rev >= 8)
758 b43_piorx_write32(q, B43_PIO8_RXCTL, B43_PIO8_RXCTL_DATARDY);
759 else
760 b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY);
761
5100d5ac
MB
762 return 1;
763}
764
77ca07ff 765void b43_pio_rx(struct b43_pio_rxqueue *q)
5100d5ac 766{
77ca07ff 767 unsigned int count = 0;
5100d5ac
MB
768 bool stop;
769
77ca07ff 770 while (1) {
5100d5ac 771 stop = (pio_rx_frame(q) == 0);
5100d5ac
MB
772 if (stop)
773 break;
77ca07ff
MB
774 cond_resched();
775 if (WARN_ON_ONCE(++count > 10000))
776 break;
777 }
5100d5ac
MB
778}
779
780static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q)
781{
5100d5ac
MB
782 if (q->rev >= 8) {
783 b43_piotx_write32(q, B43_PIO8_TXCTL,
784 b43_piotx_read32(q, B43_PIO8_TXCTL)
785 | B43_PIO8_TXCTL_SUSPREQ);
786 } else {
787 b43_piotx_write16(q, B43_PIO_TXCTL,
788 b43_piotx_read16(q, B43_PIO_TXCTL)
789 | B43_PIO_TXCTL_SUSPREQ);
790 }
5100d5ac
MB
791}
792
793static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q)
794{
5100d5ac
MB
795 if (q->rev >= 8) {
796 b43_piotx_write32(q, B43_PIO8_TXCTL,
797 b43_piotx_read32(q, B43_PIO8_TXCTL)
798 & ~B43_PIO8_TXCTL_SUSPREQ);
799 } else {
800 b43_piotx_write16(q, B43_PIO_TXCTL,
801 b43_piotx_read16(q, B43_PIO_TXCTL)
802 & ~B43_PIO_TXCTL_SUSPREQ);
803 }
5100d5ac
MB
804}
805
806void b43_pio_tx_suspend(struct b43_wldev *dev)
807{
808 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
809 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK);
810 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE);
811 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI);
812 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO);
813 b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast);
814}
815
816void b43_pio_tx_resume(struct b43_wldev *dev)
817{
818 b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast);
819 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO);
820 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI);
821 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE);
822 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK);
823 b43_power_saving_ctl_bits(dev, 0);
824}
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