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75388acd LF |
1 | #ifndef B43legacy_H_ |
2 | #define B43legacy_H_ | |
3 | ||
4 | #include <linux/hw_random.h> | |
5 | #include <linux/kernel.h> | |
6 | #include <linux/spinlock.h> | |
7 | #include <linux/interrupt.h> | |
8 | #include <linux/stringify.h> | |
9 | #include <linux/netdevice.h> | |
10 | #include <linux/pci.h> | |
60063497 | 11 | #include <linux/atomic.h> |
75388acd LF |
12 | #include <linux/io.h> |
13 | ||
14 | #include <linux/ssb/ssb.h> | |
15 | #include <linux/ssb/ssb_driver_chipcommon.h> | |
576d28a7 | 16 | #include <linux/completion.h> |
75388acd | 17 | |
75388acd LF |
18 | #include <net/mac80211.h> |
19 | ||
20 | #include "debugfs.h" | |
21 | #include "leds.h" | |
93bb7f3a | 22 | #include "rfkill.h" |
75388acd LF |
23 | #include "phy.h" |
24 | ||
25 | ||
e78c9d28 | 26 | #define B43legacy_IRQWAIT_MAX_RETRIES 20 |
75388acd | 27 | |
75388acd LF |
28 | /* MMIO offsets */ |
29 | #define B43legacy_MMIO_DMA0_REASON 0x20 | |
30 | #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24 | |
31 | #define B43legacy_MMIO_DMA1_REASON 0x28 | |
32 | #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C | |
33 | #define B43legacy_MMIO_DMA2_REASON 0x30 | |
34 | #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34 | |
35 | #define B43legacy_MMIO_DMA3_REASON 0x38 | |
36 | #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C | |
37 | #define B43legacy_MMIO_DMA4_REASON 0x40 | |
38 | #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44 | |
39 | #define B43legacy_MMIO_DMA5_REASON 0x48 | |
40 | #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C | |
e78c9d28 SB |
41 | #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */ |
42 | #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */ | |
75388acd LF |
43 | #define B43legacy_MMIO_GEN_IRQ_REASON 0x128 |
44 | #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C | |
45 | #define B43legacy_MMIO_RAM_CONTROL 0x130 | |
46 | #define B43legacy_MMIO_RAM_DATA 0x134 | |
47 | #define B43legacy_MMIO_PS_STATUS 0x140 | |
48 | #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158 | |
49 | #define B43legacy_MMIO_SHM_CONTROL 0x160 | |
50 | #define B43legacy_MMIO_SHM_DATA 0x164 | |
51 | #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166 | |
52 | #define B43legacy_MMIO_XMITSTAT_0 0x170 | |
53 | #define B43legacy_MMIO_XMITSTAT_1 0x174 | |
54 | #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ | |
55 | #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ | |
7858e07b LF |
56 | #define B43legacy_MMIO_TSF_CFP_REP 0x188 |
57 | #define B43legacy_MMIO_TSF_CFP_START 0x18C | |
75388acd LF |
58 | /* 32-bit DMA */ |
59 | #define B43legacy_MMIO_DMA32_BASE0 0x200 | |
60 | #define B43legacy_MMIO_DMA32_BASE1 0x220 | |
61 | #define B43legacy_MMIO_DMA32_BASE2 0x240 | |
62 | #define B43legacy_MMIO_DMA32_BASE3 0x260 | |
63 | #define B43legacy_MMIO_DMA32_BASE4 0x280 | |
64 | #define B43legacy_MMIO_DMA32_BASE5 0x2A0 | |
65 | /* 64-bit DMA */ | |
66 | #define B43legacy_MMIO_DMA64_BASE0 0x200 | |
67 | #define B43legacy_MMIO_DMA64_BASE1 0x240 | |
68 | #define B43legacy_MMIO_DMA64_BASE2 0x280 | |
69 | #define B43legacy_MMIO_DMA64_BASE3 0x2C0 | |
70 | #define B43legacy_MMIO_DMA64_BASE4 0x300 | |
71 | #define B43legacy_MMIO_DMA64_BASE5 0x340 | |
72 | /* PIO */ | |
73 | #define B43legacy_MMIO_PIO1_BASE 0x300 | |
74 | #define B43legacy_MMIO_PIO2_BASE 0x310 | |
75 | #define B43legacy_MMIO_PIO3_BASE 0x320 | |
76 | #define B43legacy_MMIO_PIO4_BASE 0x330 | |
77 | ||
78 | #define B43legacy_MMIO_PHY_VER 0x3E0 | |
79 | #define B43legacy_MMIO_PHY_RADIO 0x3E2 | |
80 | #define B43legacy_MMIO_PHY0 0x3E6 | |
81 | #define B43legacy_MMIO_ANTENNA 0x3E8 | |
82 | #define B43legacy_MMIO_CHANNEL 0x3F0 | |
83 | #define B43legacy_MMIO_CHANNEL_EXT 0x3F4 | |
84 | #define B43legacy_MMIO_RADIO_CONTROL 0x3F6 | |
85 | #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8 | |
86 | #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA | |
87 | #define B43legacy_MMIO_PHY_CONTROL 0x3FC | |
88 | #define B43legacy_MMIO_PHY_DATA 0x3FE | |
89 | #define B43legacy_MMIO_MACFILTER_CONTROL 0x420 | |
90 | #define B43legacy_MMIO_MACFILTER_DATA 0x422 | |
91 | #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */ | |
92 | #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A | |
93 | #define B43legacy_MMIO_GPIO_CONTROL 0x49C | |
94 | #define B43legacy_MMIO_GPIO_MASK 0x49E | |
3e2c40ef | 95 | #define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612 |
75388acd LF |
96 | #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */ |
97 | #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */ | |
98 | #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */ | |
99 | #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */ | |
100 | #define B43legacy_MMIO_RNG 0x65A | |
101 | #define B43legacy_MMIO_POWERUP_DELAY 0x6A8 | |
102 | ||
103 | /* SPROM boardflags_lo values */ | |
104 | #define B43legacy_BFL_PACTRL 0x0002 | |
105 | #define B43legacy_BFL_RSSI 0x0008 | |
106 | #define B43legacy_BFL_EXTLNA 0x1000 | |
107 | ||
108 | /* GPIO register offset, in both ChipCommon and PCI core. */ | |
109 | #define B43legacy_GPIO_CONTROL 0x6c | |
110 | ||
111 | /* SHM Routing */ | |
112 | #define B43legacy_SHM_SHARED 0x0001 | |
113 | #define B43legacy_SHM_WIRELESS 0x0002 | |
114 | #define B43legacy_SHM_HW 0x0004 | |
115 | #define B43legacy_SHM_UCODE 0x0300 | |
116 | ||
117 | /* SHM Routing modifiers */ | |
118 | #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */ | |
119 | #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */ | |
120 | #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \ | |
121 | B43legacy_SHM_AUTOINC_W) | |
122 | ||
123 | /* Misc SHM_SHARED offsets */ | |
124 | #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */ | |
125 | #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */ | |
126 | #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */ | |
127 | /* SHM_SHARED crypto engine */ | |
128 | #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */ | |
a297170d SB |
129 | /* SHM_SHARED beacon/AP variables */ |
130 | #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */ | |
131 | #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */ | |
132 | #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */ | |
133 | #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */ | |
134 | #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */ | |
75388acd LF |
135 | #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */ |
136 | /* SHM_SHARED ACK/CTS control */ | |
137 | #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */ | |
138 | /* SHM_SHARED probe response variables */ | |
a297170d | 139 | #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */ |
75388acd | 140 | #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */ |
a297170d | 141 | #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */ |
75388acd | 142 | /* SHM_SHARED rate tables */ |
7f3704e9 JB |
143 | #define B43legacy_SHM_SH_OFDMDIRECT 0x0480 /* Pointer to OFDM direct map */ |
144 | #define B43legacy_SHM_SH_OFDMBASIC 0x04A0 /* Pointer to OFDM basic rate map */ | |
145 | #define B43legacy_SHM_SH_CCKDIRECT 0x04C0 /* Pointer to CCK direct map */ | |
146 | #define B43legacy_SHM_SH_CCKBASIC 0x04E0 /* Pointer to CCK basic rate map */ | |
75388acd LF |
147 | /* SHM_SHARED microcode soft registers */ |
148 | #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */ | |
149 | #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */ | |
150 | #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */ | |
151 | #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */ | |
3e2c40ef SB |
152 | #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */ |
153 | #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */ | |
75388acd LF |
154 | |
155 | #define B43legacy_UCODEFLAGS_OFFSET 0x005E | |
156 | ||
157 | /* Hardware Radio Enable masks */ | |
158 | #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) | |
159 | #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) | |
160 | ||
161 | /* HostFlags. See b43legacy_hf_read/write() */ | |
162 | #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */ | |
163 | #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */ | |
164 | #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */ | |
165 | #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */ | |
166 | ||
167 | /* MacFilter offsets. */ | |
168 | #define B43legacy_MACFILTER_SELF 0x0000 | |
169 | #define B43legacy_MACFILTER_BSSID 0x0003 | |
170 | #define B43legacy_MACFILTER_MAC 0x0010 | |
171 | ||
172 | /* PHYVersioning */ | |
173 | #define B43legacy_PHYTYPE_B 0x01 | |
174 | #define B43legacy_PHYTYPE_G 0x02 | |
175 | ||
176 | /* PHYRegisters */ | |
177 | #define B43legacy_PHY_G_LO_CONTROL 0x0810 | |
178 | #define B43legacy_PHY_ILT_G_CTRL 0x0472 | |
179 | #define B43legacy_PHY_ILT_G_DATA1 0x0473 | |
180 | #define B43legacy_PHY_ILT_G_DATA2 0x0474 | |
181 | #define B43legacy_PHY_G_PCTL 0x0029 | |
182 | #define B43legacy_PHY_RADIO_BITFIELD 0x0401 | |
183 | #define B43legacy_PHY_G_CRS 0x0429 | |
184 | #define B43legacy_PHY_NRSSILT_CTRL 0x0803 | |
185 | #define B43legacy_PHY_NRSSILT_DATA 0x0804 | |
186 | ||
187 | /* RadioRegisters */ | |
188 | #define B43legacy_RADIOCTL_ID 0x01 | |
189 | ||
190 | /* MAC Control bitfield */ | |
e78c9d28 SB |
191 | #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */ |
192 | #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */ | |
193 | #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */ | |
194 | #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */ | |
75388acd | 195 | #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */ |
e78c9d28 | 196 | #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */ |
75388acd LF |
197 | #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */ |
198 | #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */ | |
e78c9d28 | 199 | #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */ |
4150c572 | 200 | #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */ |
75388acd LF |
201 | #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */ |
202 | #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */ | |
203 | #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */ | |
204 | #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */ | |
e78c9d28 SB |
205 | #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */ |
206 | #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */ | |
207 | #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */ | |
75388acd LF |
208 | #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */ |
209 | ||
eed0fd21 SB |
210 | /* MAC Command bitfield */ |
211 | #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */ | |
212 | #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */ | |
213 | #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */ | |
214 | #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */ | |
215 | #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */ | |
216 | ||
75388acd LF |
217 | /* 802.11 core specific TM State Low flags */ |
218 | #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ | |
219 | #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */ | |
220 | #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */ | |
221 | #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */ | |
222 | #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */ | |
223 | ||
224 | /* 802.11 core specific TM State High flags */ | |
225 | #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */ | |
226 | #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */ | |
227 | ||
228 | #define B43legacy_UCODEFLAG_AUTODIV 0x0001 | |
229 | ||
230 | /* Generic-Interrupt reasons. */ | |
231 | #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001 | |
232 | #define B43legacy_IRQ_BEACON 0x00000002 | |
233 | #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */ | |
234 | #define B43legacy_IRQ_BEACON_TX_OK 0x00000008 | |
235 | #define B43legacy_IRQ_BEACON_CANCEL 0x00000010 | |
236 | #define B43legacy_IRQ_ATIM_END 0x00000020 | |
237 | #define B43legacy_IRQ_PMQ 0x00000040 | |
238 | #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100 | |
239 | #define B43legacy_IRQ_MAC_TXERR 0x00000200 | |
240 | #define B43legacy_IRQ_PHY_TXERR 0x00000800 | |
241 | #define B43legacy_IRQ_PMEVENT 0x00001000 | |
242 | #define B43legacy_IRQ_TIMER0 0x00002000 | |
243 | #define B43legacy_IRQ_TIMER1 0x00004000 | |
244 | #define B43legacy_IRQ_DMA 0x00008000 | |
245 | #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000 | |
246 | #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000 | |
247 | #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000 | |
248 | #define B43legacy_IRQ_UCODE_DEBUG 0x08000000 | |
249 | #define B43legacy_IRQ_RFKILL 0x10000000 | |
250 | #define B43legacy_IRQ_TX_OK 0x20000000 | |
251 | #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000 | |
252 | #define B43legacy_IRQ_TIMEOUT 0x80000000 | |
253 | ||
254 | #define B43legacy_IRQ_ALL 0xFFFFFFFF | |
255 | #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \ | |
75388acd LF |
256 | B43legacy_IRQ_TBTT_INDI | \ |
257 | B43legacy_IRQ_ATIM_END | \ | |
258 | B43legacy_IRQ_PMQ | \ | |
259 | B43legacy_IRQ_MAC_TXERR | \ | |
260 | B43legacy_IRQ_PHY_TXERR | \ | |
261 | B43legacy_IRQ_DMA | \ | |
262 | B43legacy_IRQ_TXFIFO_FLUSH_OK | \ | |
263 | B43legacy_IRQ_NOISESAMPLE_OK | \ | |
264 | B43legacy_IRQ_UCODE_DEBUG | \ | |
265 | B43legacy_IRQ_RFKILL | \ | |
266 | B43legacy_IRQ_TX_OK) | |
267 | ||
268 | /* Device specific rate values. | |
269 | * The actual values defined here are (rate_in_mbps * 2). | |
270 | * Some code depends on this. Don't change it. */ | |
271 | #define B43legacy_CCK_RATE_1MB 2 | |
272 | #define B43legacy_CCK_RATE_2MB 4 | |
273 | #define B43legacy_CCK_RATE_5MB 11 | |
274 | #define B43legacy_CCK_RATE_11MB 22 | |
275 | #define B43legacy_OFDM_RATE_6MB 12 | |
276 | #define B43legacy_OFDM_RATE_9MB 18 | |
277 | #define B43legacy_OFDM_RATE_12MB 24 | |
278 | #define B43legacy_OFDM_RATE_18MB 36 | |
279 | #define B43legacy_OFDM_RATE_24MB 48 | |
280 | #define B43legacy_OFDM_RATE_36MB 72 | |
281 | #define B43legacy_OFDM_RATE_48MB 96 | |
282 | #define B43legacy_OFDM_RATE_54MB 108 | |
283 | /* Convert a b43legacy rate value to a rate in 100kbps */ | |
284 | #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2) | |
285 | ||
286 | ||
287 | #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7 | |
288 | #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4 | |
289 | ||
a293ee99 SB |
290 | #define B43legacy_PHY_TX_BADNESS_LIMIT 1000 |
291 | ||
75388acd LF |
292 | /* Max size of a security key */ |
293 | #define B43legacy_SEC_KEYSIZE 16 | |
294 | /* Security algorithms. */ | |
295 | enum { | |
296 | B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ | |
297 | B43legacy_SEC_ALGO_WEP40, | |
298 | B43legacy_SEC_ALGO_TKIP, | |
299 | B43legacy_SEC_ALGO_AES, | |
300 | B43legacy_SEC_ALGO_WEP104, | |
301 | B43legacy_SEC_ALGO_AES_LEGACY, | |
302 | }; | |
303 | ||
304 | /* Core Information Registers */ | |
305 | #define B43legacy_CIR_BASE 0xf00 | |
306 | #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18) | |
307 | #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90) | |
308 | #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94) | |
309 | #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98) | |
310 | #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c) | |
311 | #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8) | |
312 | #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc) | |
313 | ||
314 | /* sbtmstatehigh state flags */ | |
315 | #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001 | |
316 | #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004 | |
317 | #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020 | |
318 | #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000 | |
319 | #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000 | |
320 | #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000 | |
321 | #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000 | |
322 | #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000 | |
323 | #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000 | |
324 | ||
325 | /* sbimstate flags */ | |
326 | #define B43legacy_SBIMSTATE_IB_ERROR 0x20000 | |
327 | #define B43legacy_SBIMSTATE_TIMEOUT 0x40000 | |
328 | ||
329 | #define PFX KBUILD_MODNAME ": " | |
330 | #ifdef assert | |
331 | # undef assert | |
332 | #endif | |
333 | #ifdef CONFIG_B43LEGACY_DEBUG | |
4688be30 | 334 | # define B43legacy_WARN_ON(x) WARN_ON(x) |
75388acd LF |
335 | # define B43legacy_BUG_ON(expr) \ |
336 | do { \ | |
337 | if (unlikely((expr))) { \ | |
338 | printk(KERN_INFO PFX "Test (%s) failed\n", \ | |
339 | #expr); \ | |
340 | BUG_ON(expr); \ | |
341 | } \ | |
342 | } while (0) | |
343 | # define B43legacy_DEBUG 1 | |
344 | #else | |
4688be30 SB |
345 | /* This will evaluate the argument even if debugging is disabled. */ |
346 | static inline bool __b43legacy_warn_on_dummy(bool x) { return x; } | |
8f300ae5 | 347 | # define B43legacy_WARN_ON(x) __b43legacy_warn_on_dummy(unlikely(!!(x))) |
75388acd LF |
348 | # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0) |
349 | # define B43legacy_DEBUG 0 | |
350 | #endif | |
351 | ||
352 | ||
353 | struct net_device; | |
354 | struct pci_dev; | |
355 | struct b43legacy_dmaring; | |
356 | struct b43legacy_pioqueue; | |
357 | ||
358 | /* The firmware file header */ | |
359 | #define B43legacy_FW_TYPE_UCODE 'u' | |
360 | #define B43legacy_FW_TYPE_PCM 'p' | |
361 | #define B43legacy_FW_TYPE_IV 'i' | |
362 | struct b43legacy_fw_header { | |
363 | /* File type */ | |
364 | u8 type; | |
365 | /* File format version */ | |
366 | u8 ver; | |
367 | u8 __padding[2]; | |
368 | /* Size of the data. For ucode and PCM this is in bytes. | |
369 | * For IV this is number-of-ivs. */ | |
370 | __be32 size; | |
ba2d3587 | 371 | } __packed; |
75388acd LF |
372 | |
373 | /* Initial Value file format */ | |
374 | #define B43legacy_IV_OFFSET_MASK 0x7FFF | |
375 | #define B43legacy_IV_32BIT 0x8000 | |
376 | struct b43legacy_iv { | |
377 | __be16 offset_size; | |
378 | union { | |
379 | __be16 d16; | |
380 | __be32 d32; | |
ba2d3587 ED |
381 | } data __packed; |
382 | } __packed; | |
75388acd LF |
383 | |
384 | #define B43legacy_PHYMODE(phytype) (1 << (phytype)) | |
385 | #define B43legacy_PHYMODE_B B43legacy_PHYMODE \ | |
386 | ((B43legacy_PHYTYPE_B)) | |
387 | #define B43legacy_PHYMODE_G B43legacy_PHYMODE \ | |
388 | ((B43legacy_PHYTYPE_G)) | |
389 | ||
390 | /* Value pair to measure the LocalOscillator. */ | |
391 | struct b43legacy_lopair { | |
392 | s8 low; | |
393 | s8 high; | |
394 | u8 used:1; | |
395 | }; | |
396 | #define B43legacy_LO_COUNT (14*4) | |
397 | ||
398 | struct b43legacy_phy { | |
399 | /* Possible PHYMODEs on this PHY */ | |
400 | u8 possible_phymodes; | |
401 | /* GMODE bit enabled in MACCTL? */ | |
402 | bool gmode; | |
75388acd LF |
403 | |
404 | /* Analog Type */ | |
405 | u8 analog; | |
406 | /* B43legacy_PHYTYPE_ */ | |
407 | u8 type; | |
408 | /* PHY revision number. */ | |
409 | u8 rev; | |
410 | ||
411 | u16 antenna_diversity; | |
412 | u16 savedpctlreg; | |
413 | /* Radio versioning */ | |
414 | u16 radio_manuf; /* Radio manufacturer */ | |
415 | u16 radio_ver; /* Radio version */ | |
416 | u8 calibrated:1; | |
417 | u8 radio_rev; /* Radio revision */ | |
418 | ||
75388acd LF |
419 | bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */ |
420 | ||
421 | /* ACI (adjacent channel interference) flags. */ | |
422 | bool aci_enable; | |
423 | bool aci_wlan_automatic; | |
424 | bool aci_hw_rssi; | |
425 | ||
42a9174f LF |
426 | /* Radio switched on/off */ |
427 | bool radio_on; | |
428 | struct { | |
429 | /* Values saved when turning the radio off. | |
430 | * They are needed when turning it on again. */ | |
431 | bool valid; | |
432 | u16 rfover; | |
433 | u16 rfoverval; | |
434 | } radio_off_context; | |
435 | ||
75388acd LF |
436 | u16 minlowsig[2]; |
437 | u16 minlowsigpos[2]; | |
438 | ||
439 | /* LO Measurement Data. | |
440 | * Use b43legacy_get_lopair() to get a value. | |
441 | */ | |
442 | struct b43legacy_lopair *_lo_pairs; | |
443 | /* TSSI to dBm table in use */ | |
444 | const s8 *tssi2dbm; | |
445 | /* idle TSSI value */ | |
446 | s8 idle_tssi; | |
447 | /* Target idle TSSI */ | |
448 | int tgt_idle_tssi; | |
449 | /* Current idle TSSI */ | |
450 | int cur_idle_tssi; | |
451 | ||
452 | /* LocalOscillator control values. */ | |
453 | struct b43legacy_txpower_lo_control *lo_control; | |
454 | /* Values from b43legacy_calc_loopback_gain() */ | |
455 | s16 max_lb_gain; /* Maximum Loopback gain in hdB */ | |
456 | s16 trsw_rx_gain; /* TRSW RX gain in hdB */ | |
457 | s16 lna_lod_gain; /* LNA lod */ | |
458 | s16 lna_gain; /* LNA */ | |
459 | s16 pga_gain; /* PGA */ | |
460 | ||
75388acd LF |
461 | /* Desired TX power level (in dBm). This is set by the user and |
462 | * adjusted in b43legacy_phy_xmitpower(). */ | |
463 | u8 power_level; | |
464 | ||
465 | /* Values from b43legacy_calc_loopback_gain() */ | |
466 | u16 loopback_gain[2]; | |
467 | ||
468 | /* TX Power control values. */ | |
469 | /* B/G PHY */ | |
470 | struct { | |
471 | /* Current Radio Attenuation for TXpower recalculation. */ | |
472 | u16 rfatt; | |
473 | /* Current Baseband Attenuation for TXpower recalculation. */ | |
474 | u16 bbatt; | |
475 | /* Current TXpower control value for TXpower recalculation. */ | |
476 | u16 txctl1; | |
477 | u16 txctl2; | |
478 | }; | |
479 | /* A PHY */ | |
480 | struct { | |
481 | u16 txpwr_offset; | |
482 | }; | |
483 | ||
75388acd LF |
484 | /* Current Interference Mitigation mode */ |
485 | int interfmode; | |
486 | /* Stack of saved values from the Interference Mitigation code. | |
25985edc | 487 | * Each value in the stack is laid out as follows: |
75388acd LF |
488 | * bit 0-11: offset |
489 | * bit 12-15: register ID | |
490 | * bit 16-32: value | |
491 | * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT | |
492 | */ | |
493 | #define B43legacy_INTERFSTACK_SIZE 26 | |
494 | u32 interfstack[B43legacy_INTERFSTACK_SIZE]; | |
495 | ||
496 | /* Saved values from the NRSSI Slope calculation */ | |
497 | s16 nrssi[2]; | |
498 | s32 nrssislope; | |
499 | /* In memory nrssi lookup table. */ | |
500 | s8 nrssi_lt[64]; | |
501 | ||
502 | /* current channel */ | |
503 | u8 channel; | |
504 | ||
505 | u16 lofcal; | |
506 | ||
507 | u16 initval; | |
a293ee99 SB |
508 | |
509 | /* PHY TX errors counter. */ | |
510 | atomic_t txerr_cnt; | |
bfe6a501 MB |
511 | |
512 | #if B43legacy_DEBUG | |
513 | /* Manual TX-power control enabled? */ | |
514 | bool manual_txpower_control; | |
515 | /* PHY registers locked by b43legacy_phy_lock()? */ | |
516 | bool phy_locked; | |
517 | #endif /* B43legacy_DEBUG */ | |
75388acd LF |
518 | }; |
519 | ||
520 | /* Data structures for DMA transmission, per 80211 core. */ | |
521 | struct b43legacy_dma { | |
522 | struct b43legacy_dmaring *tx_ring0; | |
523 | struct b43legacy_dmaring *tx_ring1; | |
524 | struct b43legacy_dmaring *tx_ring2; | |
525 | struct b43legacy_dmaring *tx_ring3; | |
526 | struct b43legacy_dmaring *tx_ring4; | |
527 | struct b43legacy_dmaring *tx_ring5; | |
528 | ||
529 | struct b43legacy_dmaring *rx_ring0; | |
530 | struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */ | |
8c95b74d RM |
531 | |
532 | u32 translation; /* Routing bits */ | |
75388acd LF |
533 | }; |
534 | ||
535 | /* Data structures for PIO transmission, per 80211 core. */ | |
536 | struct b43legacy_pio { | |
537 | struct b43legacy_pioqueue *queue0; | |
538 | struct b43legacy_pioqueue *queue1; | |
539 | struct b43legacy_pioqueue *queue2; | |
540 | struct b43legacy_pioqueue *queue3; | |
541 | }; | |
542 | ||
543 | /* Context information for a noise calculation (Link Quality). */ | |
544 | struct b43legacy_noise_calculation { | |
545 | u8 channel_at_start; | |
546 | bool calculation_running; | |
547 | u8 nr_samples; | |
548 | s8 samples[8][4]; | |
549 | }; | |
550 | ||
551 | struct b43legacy_stats { | |
552 | u8 link_noise; | |
553 | /* Store the last TX/RX times here for updating the leds. */ | |
554 | unsigned long last_tx; | |
555 | unsigned long last_rx; | |
556 | }; | |
557 | ||
558 | struct b43legacy_key { | |
559 | void *keyconf; | |
560 | bool enabled; | |
561 | u8 algorithm; | |
562 | }; | |
563 | ||
5d07a3d6 LF |
564 | #define B43legacy_QOS_QUEUE_NUM 4 |
565 | ||
75388acd LF |
566 | struct b43legacy_wldev; |
567 | ||
5d07a3d6 LF |
568 | /* QOS parameters for a queue. */ |
569 | struct b43legacy_qos_params { | |
570 | /* The QOS parameters */ | |
571 | struct ieee80211_tx_queue_params p; | |
572 | }; | |
573 | ||
75388acd LF |
574 | /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */ |
575 | struct b43legacy_wl { | |
576 | /* Pointer to the active wireless device on this chip */ | |
577 | struct b43legacy_wldev *current_dev; | |
578 | /* Pointer to the ieee80211 hardware data structure */ | |
579 | struct ieee80211_hw *hw; | |
580 | ||
581 | spinlock_t irq_lock; /* locks IRQ */ | |
582 | struct mutex mutex; /* locks wireless core state */ | |
583 | spinlock_t leds_lock; /* lock for leds */ | |
584 | ||
a3ea2c76 LF |
585 | /* firmware loading work */ |
586 | struct work_struct firmware_load; | |
587 | ||
75388acd LF |
588 | /* We can only have one operating interface (802.11 core) |
589 | * at a time. General information about this interface follows. | |
590 | */ | |
591 | ||
32bfd35d | 592 | struct ieee80211_vif *vif; |
75388acd | 593 | /* MAC address (can be NULL). */ |
4150c572 | 594 | u8 mac_addr[ETH_ALEN]; |
75388acd | 595 | /* Current BSSID (can be NULL). */ |
4150c572 | 596 | u8 bssid[ETH_ALEN]; |
75388acd LF |
597 | /* Interface type. (IEEE80211_IF_TYPE_XXX) */ |
598 | int if_type; | |
75388acd LF |
599 | /* Is the card operating in AP, STA or IBSS mode? */ |
600 | bool operating; | |
4150c572 JB |
601 | /* filter flags */ |
602 | unsigned int filter_flags; | |
75388acd LF |
603 | /* Stats about the wireless interface */ |
604 | struct ieee80211_low_level_stats ieee_stats; | |
605 | ||
910cfee3 | 606 | #ifdef CONFIG_B43LEGACY_HWRNG |
75388acd LF |
607 | struct hwrng rng; |
608 | u8 rng_initialized; | |
609 | char rng_name[30 + 1]; | |
910cfee3 | 610 | #endif |
75388acd LF |
611 | |
612 | /* List of all wireless devices on this chip */ | |
613 | struct list_head devlist; | |
614 | u8 nr_devs; | |
5be3bda8 JB |
615 | |
616 | bool radiotap_enabled; | |
fd4973c5 | 617 | bool radio_enabled; |
a297170d SB |
618 | |
619 | /* The beacon we are currently using (AP or IBSS mode). | |
620 | * This beacon stuff is protected by the irq_lock. */ | |
621 | struct sk_buff *current_beacon; | |
622 | bool beacon0_uploaded; | |
623 | bool beacon1_uploaded; | |
2d1f96dd | 624 | bool beacon_templates_virgin; /* Never wrote the templates? */ |
7858e07b | 625 | struct work_struct beacon_update_trigger; |
5d07a3d6 LF |
626 | /* The current QOS parameters for the 4 queues. */ |
627 | struct b43legacy_qos_params qos_params[B43legacy_QOS_QUEUE_NUM]; | |
628 | ||
629 | /* Packet transmit work */ | |
630 | struct work_struct tx_work; | |
631 | ||
632 | /* Queue of packets to be transmitted. */ | |
633 | struct sk_buff_head tx_queue[B43legacy_QOS_QUEUE_NUM]; | |
634 | ||
635 | /* Flag that implement the queues stopping. */ | |
636 | bool tx_queue_stopped[B43legacy_QOS_QUEUE_NUM]; | |
637 | ||
75388acd LF |
638 | }; |
639 | ||
640 | /* Pointers to the firmware data and meta information about it. */ | |
641 | struct b43legacy_firmware { | |
642 | /* Microcode */ | |
643 | const struct firmware *ucode; | |
644 | /* PCM code */ | |
645 | const struct firmware *pcm; | |
646 | /* Initial MMIO values for the firmware */ | |
647 | const struct firmware *initvals; | |
648 | /* Initial MMIO values for the firmware, band-specific */ | |
649 | const struct firmware *initvals_band; | |
650 | /* Firmware revision */ | |
651 | u16 rev; | |
652 | /* Firmware patchlevel */ | |
653 | u16 patch; | |
654 | }; | |
655 | ||
656 | /* Device (802.11 core) initialization status. */ | |
657 | enum { | |
658 | B43legacy_STAT_UNINIT = 0, /* Uninitialized. */ | |
659 | B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */ | |
660 | B43legacy_STAT_STARTED = 2, /* Up and running. */ | |
661 | }; | |
662 | #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status) | |
663 | #define b43legacy_set_status(wldev, stat) do { \ | |
664 | atomic_set(&(wldev)->__init_status, (stat)); \ | |
665 | smp_wmb(); \ | |
666 | } while (0) | |
667 | ||
668 | /* *** --- HOW LOCKING WORKS IN B43legacy --- *** | |
669 | * | |
670 | * You should always acquire both, wl->mutex and wl->irq_lock unless: | |
671 | * - You don't need to acquire wl->irq_lock, if the interface is stopped. | |
672 | * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet | |
673 | * and packet TX path (and _ONLY_ there.) | |
674 | */ | |
675 | ||
676 | /* Data structure for one wireless device (802.11 core) */ | |
677 | struct b43legacy_wldev { | |
678 | struct ssb_device *dev; | |
679 | struct b43legacy_wl *wl; | |
680 | ||
681 | /* The device initialization status. | |
682 | * Use b43legacy_status() to query. */ | |
683 | atomic_t __init_status; | |
684 | /* Saved init status for handling suspend. */ | |
685 | int suspend_init_status; | |
686 | ||
687 | bool __using_pio; /* Using pio rather than dma. */ | |
688 | bool bad_frames_preempt;/* Use "Bad Frames Preemption". */ | |
eed0fd21 | 689 | bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */ |
75388acd | 690 | bool short_preamble; /* TRUE if using short preamble. */ |
75388acd LF |
691 | bool radio_hw_enable; /* State of radio hardware enable bit. */ |
692 | ||
693 | /* PHY/Radio device. */ | |
694 | struct b43legacy_phy phy; | |
695 | union { | |
696 | /* DMA engines. */ | |
697 | struct b43legacy_dma dma; | |
698 | /* PIO engines. */ | |
699 | struct b43legacy_pio pio; | |
700 | }; | |
701 | ||
702 | /* Various statistics about the physical device. */ | |
703 | struct b43legacy_stats stats; | |
704 | ||
ba48f7bb LF |
705 | /* The device LEDs. */ |
706 | struct b43legacy_led led_tx; | |
707 | struct b43legacy_led led_rx; | |
708 | struct b43legacy_led led_assoc; | |
93bb7f3a | 709 | struct b43legacy_led led_radio; |
75388acd LF |
710 | |
711 | /* Reason code of the last interrupt. */ | |
712 | u32 irq_reason; | |
713 | u32 dma_reason[6]; | |
44710bbc SB |
714 | /* The currently active generic-interrupt mask. */ |
715 | u32 irq_mask; | |
75388acd LF |
716 | /* Link Quality calculation context. */ |
717 | struct b43legacy_noise_calculation noisecalc; | |
718 | /* if > 0 MAC is suspended. if == 0 MAC is enabled. */ | |
719 | int mac_suspended; | |
720 | ||
721 | /* Interrupt Service Routine tasklet (bottom-half) */ | |
722 | struct tasklet_struct isr_tasklet; | |
723 | ||
724 | /* Periodic tasks */ | |
725 | struct delayed_work periodic_work; | |
726 | unsigned int periodic_state; | |
727 | ||
728 | struct work_struct restart_work; | |
729 | ||
730 | /* encryption/decryption */ | |
731 | u16 ktp; /* Key table pointer */ | |
732 | u8 max_nr_keys; | |
733 | struct b43legacy_key key[58]; | |
734 | ||
75388acd LF |
735 | /* Firmware data */ |
736 | struct b43legacy_firmware fw; | |
576d28a7 LF |
737 | const struct firmware *fwp; /* needed to pass fw pointer */ |
738 | ||
739 | /* completion struct for firmware loading */ | |
740 | struct completion fw_load_complete; | |
75388acd LF |
741 | |
742 | /* Devicelist in struct b43legacy_wl (all 802.11 cores) */ | |
743 | struct list_head list; | |
744 | ||
745 | /* Debugging stuff follows. */ | |
746 | #ifdef CONFIG_B43LEGACY_DEBUG | |
747 | struct b43legacy_dfsentry *dfsentry; | |
748 | #endif | |
749 | }; | |
750 | ||
751 | ||
752 | static inline | |
753 | struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw) | |
754 | { | |
755 | return hw->priv; | |
756 | } | |
757 | ||
758 | /* Helper function, which returns a boolean. | |
759 | * TRUE, if PIO is used; FALSE, if DMA is used. | |
760 | */ | |
761 | #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO) | |
762 | static inline | |
763 | int b43legacy_using_pio(struct b43legacy_wldev *dev) | |
764 | { | |
765 | return dev->__using_pio; | |
766 | } | |
767 | #elif defined(CONFIG_B43LEGACY_DMA) | |
768 | static inline | |
769 | int b43legacy_using_pio(struct b43legacy_wldev *dev) | |
770 | { | |
771 | return 0; | |
772 | } | |
773 | #elif defined(CONFIG_B43LEGACY_PIO) | |
774 | static inline | |
775 | int b43legacy_using_pio(struct b43legacy_wldev *dev) | |
776 | { | |
777 | return 1; | |
778 | } | |
779 | #else | |
780 | # error "Using neither DMA nor PIO? Confused..." | |
781 | #endif | |
782 | ||
783 | ||
784 | static inline | |
785 | struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev) | |
786 | { | |
787 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
788 | return ssb_get_drvdata(ssb_dev); | |
789 | } | |
790 | ||
791 | /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */ | |
792 | static inline | |
793 | int b43legacy_is_mode(struct b43legacy_wl *wl, int type) | |
794 | { | |
75388acd LF |
795 | return (wl->operating && |
796 | wl->if_type == type); | |
797 | } | |
798 | ||
799 | static inline | |
800 | bool is_bcm_board_vendor(struct b43legacy_wldev *dev) | |
801 | { | |
802 | return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM); | |
803 | } | |
804 | ||
805 | static inline | |
806 | u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset) | |
807 | { | |
808 | return ssb_read16(dev->dev, offset); | |
809 | } | |
810 | ||
811 | static inline | |
812 | void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value) | |
813 | { | |
814 | ssb_write16(dev->dev, offset, value); | |
815 | } | |
816 | ||
817 | static inline | |
818 | u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset) | |
819 | { | |
820 | return ssb_read32(dev->dev, offset); | |
821 | } | |
822 | ||
823 | static inline | |
824 | void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value) | |
825 | { | |
826 | ssb_write32(dev->dev, offset, value); | |
827 | } | |
828 | ||
829 | static inline | |
830 | struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy, | |
831 | u16 radio_attenuation, | |
832 | u16 baseband_attenuation) | |
833 | { | |
834 | return phy->_lo_pairs + (radio_attenuation | |
835 | + 14 * (baseband_attenuation / 2)); | |
836 | } | |
837 | ||
838 | ||
839 | ||
840 | /* Message printing */ | |
b9075fa9 JP |
841 | __printf(2, 3) |
842 | void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...); | |
843 | __printf(2, 3) | |
844 | void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...); | |
845 | __printf(2, 3) | |
846 | void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...); | |
75388acd | 847 | #if B43legacy_DEBUG |
b9075fa9 JP |
848 | __printf(2, 3) |
849 | void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...); | |
75388acd LF |
850 | #else /* DEBUG */ |
851 | # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0) | |
852 | #endif /* DEBUG */ | |
853 | ||
75388acd LF |
854 | /* Macros for printing a value in Q5.2 format */ |
855 | #define Q52_FMT "%u.%u" | |
856 | #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4) | |
857 | ||
858 | #endif /* B43legacy_H_ */ |