projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f222313a JL |
1 | #ifndef BCM43xx_H_ |
| 2 | #define BCM43xx_H_ | |
| 3 | ||
| 4 | #include <linux/version.h> | |
| 5 | #include <linux/kernel.h> | |
| 6 | #include <linux/spinlock.h> | |
| 7 | #include <linux/interrupt.h> | |
| 8 | #include <linux/stringify.h> | |
| 9 | #include <linux/pci.h> | |
| 10 | #include <net/ieee80211.h> | |
| 11 | #include <net/ieee80211softmac.h> | |
| 12 | #include <asm/atomic.h> | |
| 13 | #include <asm/io.h> | |
| 14 | ||
| 15 | ||
| 16 | #include "bcm43xx_debugfs.h" | |
| 17 | #include "bcm43xx_leds.h" | |
| 18 | ||
| 19 | ||
| 65f3f191 | 20 | #define PFX KBUILD_MODNAME ": " |
| f222313a JL |
21 | |
| 22 | #define BCM43xx_SWITCH_CORE_MAX_RETRIES 10 | |
| 23 | #define BCM43xx_IRQWAIT_MAX_RETRIES 50 | |
| f222313a JL |
24 | |
| 25 | #define BCM43xx_IO_SIZE 8192 | |
| 26 | #define BCM43xx_REG_ACTIVE_CORE 0x80 | |
| 27 | ||
| 28 | /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */ | |
| 29 | #define BCM43xx_PCICFG_ICR 0x94 | |
| 30 | /* SPROM control register. */ | |
| 31 | #define BCM43xx_PCICFG_SPROMCTL 0x88 | |
| 32 | ||
| 33 | /* MMIO offsets */ | |
| 34 | #define BCM43xx_MMIO_DMA1_REASON 0x20 | |
| 35 | #define BCM43xx_MMIO_DMA1_IRQ_MASK 0x24 | |
| 36 | #define BCM43xx_MMIO_DMA2_REASON 0x28 | |
| 37 | #define BCM43xx_MMIO_DMA2_IRQ_MASK 0x2C | |
| 38 | #define BCM43xx_MMIO_DMA3_REASON 0x30 | |
| 39 | #define BCM43xx_MMIO_DMA3_IRQ_MASK 0x34 | |
| 40 | #define BCM43xx_MMIO_DMA4_REASON 0x38 | |
| 41 | #define BCM43xx_MMIO_DMA4_IRQ_MASK 0x3C | |
| 42 | #define BCM43xx_MMIO_STATUS_BITFIELD 0x120 | |
| 43 | #define BCM43xx_MMIO_STATUS2_BITFIELD 0x124 | |
| 44 | #define BCM43xx_MMIO_GEN_IRQ_REASON 0x128 | |
| 45 | #define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C | |
| 46 | #define BCM43xx_MMIO_RAM_CONTROL 0x130 | |
| 47 | #define BCM43xx_MMIO_RAM_DATA 0x134 | |
| 48 | #define BCM43xx_MMIO_PS_STATUS 0x140 | |
| 49 | #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158 | |
| 50 | #define BCM43xx_MMIO_SHM_CONTROL 0x160 | |
| 51 | #define BCM43xx_MMIO_SHM_DATA 0x164 | |
| 52 | #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166 | |
| 53 | #define BCM43xx_MMIO_XMITSTAT_0 0x170 | |
| 54 | #define BCM43xx_MMIO_XMITSTAT_1 0x174 | |
| 55 | #define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ | |
| 56 | #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ | |
| 57 | #define BCM43xx_MMIO_DMA1_BASE 0x200 | |
| 58 | #define BCM43xx_MMIO_DMA2_BASE 0x220 | |
| 59 | #define BCM43xx_MMIO_DMA3_BASE 0x240 | |
| 60 | #define BCM43xx_MMIO_DMA4_BASE 0x260 | |
| 61 | #define BCM43xx_MMIO_PIO1_BASE 0x300 | |
| 62 | #define BCM43xx_MMIO_PIO2_BASE 0x310 | |
| 63 | #define BCM43xx_MMIO_PIO3_BASE 0x320 | |
| 64 | #define BCM43xx_MMIO_PIO4_BASE 0x330 | |
| 65 | #define BCM43xx_MMIO_PHY_VER 0x3E0 | |
| 66 | #define BCM43xx_MMIO_PHY_RADIO 0x3E2 | |
| 67 | #define BCM43xx_MMIO_ANTENNA 0x3E8 | |
| 68 | #define BCM43xx_MMIO_CHANNEL 0x3F0 | |
| 69 | #define BCM43xx_MMIO_CHANNEL_EXT 0x3F4 | |
| 70 | #define BCM43xx_MMIO_RADIO_CONTROL 0x3F6 | |
| 71 | #define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8 | |
| 72 | #define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA | |
| 73 | #define BCM43xx_MMIO_PHY_CONTROL 0x3FC | |
| 74 | #define BCM43xx_MMIO_PHY_DATA 0x3FE | |
| 75 | #define BCM43xx_MMIO_MACFILTER_CONTROL 0x420 | |
| 76 | #define BCM43xx_MMIO_MACFILTER_DATA 0x422 | |
| 77 | #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A | |
| 78 | #define BCM43xx_MMIO_GPIO_CONTROL 0x49C | |
| 79 | #define BCM43xx_MMIO_GPIO_MASK 0x49E | |
| 80 | #define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */ | |
| 81 | #define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */ | |
| 82 | #define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */ | |
| 83 | #define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */ | |
| 84 | #define BCM43xx_MMIO_POWERUP_DELAY 0x6A8 | |
| 85 | ||
| 86 | /* SPROM offsets. */ | |
| 87 | #define BCM43xx_SPROM_BASE 0x1000 | |
| 88 | #define BCM43xx_SPROM_BOARDFLAGS2 0x1c | |
| 89 | #define BCM43xx_SPROM_IL0MACADDR 0x24 | |
| 90 | #define BCM43xx_SPROM_ET0MACADDR 0x27 | |
| 91 | #define BCM43xx_SPROM_ET1MACADDR 0x2a | |
| 92 | #define BCM43xx_SPROM_ETHPHY 0x2d | |
| 93 | #define BCM43xx_SPROM_BOARDREV 0x2e | |
| 94 | #define BCM43xx_SPROM_PA0B0 0x2f | |
| 95 | #define BCM43xx_SPROM_PA0B1 0x30 | |
| 96 | #define BCM43xx_SPROM_PA0B2 0x31 | |
| 97 | #define BCM43xx_SPROM_WL0GPIO0 0x32 | |
| 98 | #define BCM43xx_SPROM_WL0GPIO2 0x33 | |
| 99 | #define BCM43xx_SPROM_MAXPWR 0x34 | |
| 100 | #define BCM43xx_SPROM_PA1B0 0x35 | |
| 101 | #define BCM43xx_SPROM_PA1B1 0x36 | |
| 102 | #define BCM43xx_SPROM_PA1B2 0x37 | |
| 103 | #define BCM43xx_SPROM_IDL_TSSI_TGT 0x38 | |
| 104 | #define BCM43xx_SPROM_BOARDFLAGS 0x39 | |
| 105 | #define BCM43xx_SPROM_ANTENNA_GAIN 0x3a | |
| 106 | #define BCM43xx_SPROM_VERSION 0x3f | |
| 107 | ||
| 108 | /* BCM43xx_SPROM_BOARDFLAGS values */ | |
| 109 | #define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ | |
| 110 | #define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ | |
| 111 | #define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ | |
| 112 | #define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ | |
| 113 | #define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ | |
| 114 | #define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ | |
| 115 | #define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ | |
| 116 | #define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */ | |
| 117 | #define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */ | |
| 118 | #define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ | |
| 119 | #define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */ | |
| 120 | #define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */ | |
| 121 | ||
| 122 | /* GPIO register offset, in both ChipCommon and PCI core. */ | |
| 123 | #define BCM43xx_GPIO_CONTROL 0x6c | |
| 124 | ||
| 125 | /* SHM Routing */ | |
| 126 | #define BCM43xx_SHM_SHARED 0x0001 | |
| 127 | #define BCM43xx_SHM_WIRELESS 0x0002 | |
| 128 | #define BCM43xx_SHM_PCM 0x0003 | |
| 129 | #define BCM43xx_SHM_HWMAC 0x0004 | |
| 130 | #define BCM43xx_SHM_UCODE 0x0300 | |
| 131 | ||
| 132 | /* MacFilter offsets. */ | |
| 133 | #define BCM43xx_MACFILTER_SELF 0x0000 | |
| 134 | #define BCM43xx_MACFILTER_ASSOC 0x0003 | |
| 135 | ||
| 136 | /* Chipcommon registers. */ | |
| 137 | #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 | |
| 138 | #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 | |
| 139 | #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 | |
| 140 | #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 | |
| 141 | #define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0 | |
| 142 | ||
| 143 | /* PCI core specific registers. */ | |
| 144 | #define BCM43xx_PCICORE_BCAST_ADDR 0x50 | |
| 145 | #define BCM43xx_PCICORE_BCAST_DATA 0x54 | |
| 146 | #define BCM43xx_PCICORE_SBTOPCI2 0x108 | |
| 147 | ||
| 148 | /* SBTOPCI2 values. */ | |
| 149 | #define BCM43xx_SBTOPCI2_PREFETCH 0x4 | |
| 150 | #define BCM43xx_SBTOPCI2_BURST 0x8 | |
| 151 | ||
| 152 | /* Chipcommon capabilities. */ | |
| 153 | #define BCM43xx_CAPABILITIES_PCTL 0x00040000 | |
| 154 | #define BCM43xx_CAPABILITIES_PLLMASK 0x00030000 | |
| 155 | #define BCM43xx_CAPABILITIES_PLLSHIFT 16 | |
| 156 | #define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700 | |
| 157 | #define BCM43xx_CAPABILITIES_FLASHSHIFT 8 | |
| 158 | #define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040 | |
| 159 | #define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020 | |
| 160 | #define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018 | |
| 161 | #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3 | |
| 162 | #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004 | |
| 163 | #define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003 | |
| 164 | ||
| 165 | /* PowerControl */ | |
| 166 | #define BCM43xx_PCTL_IN 0xB0 | |
| 167 | #define BCM43xx_PCTL_OUT 0xB4 | |
| 168 | #define BCM43xx_PCTL_OUTENABLE 0xB8 | |
| 169 | #define BCM43xx_PCTL_XTAL_POWERUP 0x40 | |
| 170 | #define BCM43xx_PCTL_PLL_POWERDOWN 0x80 | |
| 171 | ||
| 172 | /* PowerControl Clock Modes */ | |
| 173 | #define BCM43xx_PCTL_CLK_FAST 0x00 | |
| 174 | #define BCM43xx_PCTL_CLK_SLOW 0x01 | |
| 175 | #define BCM43xx_PCTL_CLK_DYNAMIC 0x02 | |
| 176 | ||
| 177 | #define BCM43xx_PCTL_FORCE_SLOW 0x0800 | |
| 178 | #define BCM43xx_PCTL_FORCE_PLL 0x1000 | |
| 179 | #define BCM43xx_PCTL_DYN_XTAL 0x2000 | |
| 180 | ||
| 181 | /* COREIDs */ | |
| 182 | #define BCM43xx_COREID_CHIPCOMMON 0x800 | |
| 183 | #define BCM43xx_COREID_ILINE20 0x801 | |
| 184 | #define BCM43xx_COREID_SDRAM 0x803 | |
| 185 | #define BCM43xx_COREID_PCI 0x804 | |
| 186 | #define BCM43xx_COREID_MIPS 0x805 | |
| 187 | #define BCM43xx_COREID_ETHERNET 0x806 | |
| 188 | #define BCM43xx_COREID_V90 0x807 | |
| 189 | #define BCM43xx_COREID_USB11_HOSTDEV 0x80a | |
| 190 | #define BCM43xx_COREID_IPSEC 0x80b | |
| 191 | #define BCM43xx_COREID_PCMCIA 0x80d | |
| 192 | #define BCM43xx_COREID_EXT_IF 0x80f | |
| 193 | #define BCM43xx_COREID_80211 0x812 | |
| 194 | #define BCM43xx_COREID_MIPS_3302 0x816 | |
| 195 | #define BCM43xx_COREID_USB11_HOST 0x817 | |
| 196 | #define BCM43xx_COREID_USB11_DEV 0x818 | |
| 197 | #define BCM43xx_COREID_USB20_HOST 0x819 | |
| 198 | #define BCM43xx_COREID_USB20_DEV 0x81a | |
| 199 | #define BCM43xx_COREID_SDIO_HOST 0x81b | |
| 200 | ||
| 201 | /* Core Information Registers */ | |
| 202 | #define BCM43xx_CIR_BASE 0xf00 | |
| 203 | #define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18) | |
| 204 | #define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90) | |
| 205 | #define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94) | |
| 206 | #define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98) | |
| 207 | #define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c) | |
| 208 | #define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8) | |
| 209 | #define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc) | |
| 210 | ||
| 211 | /* Mask to get the Backplane Flag Number from SBTPSFLAG. */ | |
| 212 | #define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f | |
| 213 | ||
| 214 | /* SBIMCONFIGLOW values/masks. */ | |
| 215 | #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007 | |
| 216 | #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0 | |
| 217 | #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070 | |
| 218 | #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4 | |
| 219 | #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000 | |
| 220 | #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16 | |
| 221 | ||
| 222 | /* sbtmstatelow state flags */ | |
| 223 | #define BCM43xx_SBTMSTATELOW_RESET 0x01 | |
| 224 | #define BCM43xx_SBTMSTATELOW_REJECT 0x02 | |
| 225 | #define BCM43xx_SBTMSTATELOW_CLOCK 0x10000 | |
| 226 | #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000 | |
| 227 | ||
| 228 | /* sbtmstatehigh state flags */ | |
| 229 | #define BCM43xx_SBTMSTATEHIGH_SERROR 0x1 | |
| 230 | #define BCM43xx_SBTMSTATEHIGH_BUSY 0x4 | |
| 231 | ||
| 232 | /* sbimstate flags */ | |
| 233 | #define BCM43xx_SBIMSTATE_IB_ERROR 0x20000 | |
| 234 | #define BCM43xx_SBIMSTATE_TIMEOUT 0x40000 | |
| 235 | ||
| 236 | /* PHYVersioning */ | |
| 237 | #define BCM43xx_PHYTYPE_A 0x00 | |
| 238 | #define BCM43xx_PHYTYPE_B 0x01 | |
| 239 | #define BCM43xx_PHYTYPE_G 0x02 | |
| 240 | ||
| 241 | /* PHYRegisters */ | |
| 242 | #define BCM43xx_PHY_ILT_A_CTRL 0x0072 | |
| 243 | #define BCM43xx_PHY_ILT_A_DATA1 0x0073 | |
| 244 | #define BCM43xx_PHY_ILT_A_DATA2 0x0074 | |
| 245 | #define BCM43xx_PHY_G_LO_CONTROL 0x0810 | |
| 246 | #define BCM43xx_PHY_ILT_G_CTRL 0x0472 | |
| 247 | #define BCM43xx_PHY_ILT_G_DATA1 0x0473 | |
| 248 | #define BCM43xx_PHY_ILT_G_DATA2 0x0474 | |
| 249 | #define BCM43xx_PHY_A_PCTL 0x007B | |
| 250 | #define BCM43xx_PHY_G_PCTL 0x0029 | |
| 251 | #define BCM43xx_PHY_A_CRS 0x0029 | |
| 252 | #define BCM43xx_PHY_RADIO_BITFIELD 0x0401 | |
| 253 | #define BCM43xx_PHY_G_CRS 0x0429 | |
| 254 | #define BCM43xx_PHY_NRSSILT_CTRL 0x0803 | |
| 255 | #define BCM43xx_PHY_NRSSILT_DATA 0x0804 | |
| 256 | ||
| 257 | /* RadioRegisters */ | |
| 258 | #define BCM43xx_RADIOCTL_ID 0x01 | |
| 259 | ||
| 260 | /* StatusBitField */ | |
| 261 | #define BCM43xx_SBF_MAC_ENABLED 0x00000001 | |
| 262 | #define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/ | |
| 263 | #define BCM43xx_SBF_CORE_READY 0x00000004 | |
| 264 | #define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/ | |
| 265 | #define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/ | |
| 266 | #define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/ | |
| 267 | #define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000 | |
| 268 | #define BCM43xx_SBF_MODE_NOTADHOC 0x00020000 | |
| 269 | #define BCM43xx_SBF_MODE_AP 0x00040000 | |
| 270 | #define BCM43xx_SBF_RADIOREG_LOCK 0x00080000 | |
| 271 | #define BCM43xx_SBF_MODE_MONITOR 0x00400000 | |
| 272 | #define BCM43xx_SBF_MODE_PROMISC 0x01000000 | |
| 273 | #define BCM43xx_SBF_PS1 0x02000000 | |
| 274 | #define BCM43xx_SBF_PS2 0x04000000 | |
| 275 | #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000 | |
| 276 | #define BCM43xx_SBF_TIME_UPDATE 0x10000000 | |
| 277 | #define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/ | |
| 278 | ||
| 279 | /* MicrocodeFlagsBitfield (addr + lo-word values?)*/ | |
| 280 | #define BCM43xx_UCODEFLAGS_OFFSET 0x005E | |
| 281 | ||
| 282 | #define BCM43xx_UCODEFLAG_AUTODIV 0x0001 | |
| 283 | #define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002 | |
| 284 | #define BCM43xx_UCODEFLAG_UNKBPHY 0x0004 | |
| 285 | #define BCM43xx_UCODEFLAG_UNKGPHY 0x0020 | |
| 286 | #define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040 | |
| 287 | #define BCM43xx_UCODEFLAG_JAPAN 0x0080 | |
| 288 | ||
| 289 | /* Generic-Interrupt reasons. */ | |
| 290 | #define BCM43xx_IRQ_READY (1 << 0) | |
| 291 | #define BCM43xx_IRQ_BEACON (1 << 1) | |
| 292 | #define BCM43xx_IRQ_PS (1 << 2) | |
| 293 | #define BCM43xx_IRQ_REG124 (1 << 5) | |
| 294 | #define BCM43xx_IRQ_PMQ (1 << 6) | |
| 295 | #define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8) | |
| 296 | #define BCM43xx_IRQ_XMIT_ERROR (1 << 11) | |
| 297 | #define BCM43xx_IRQ_RX (1 << 15) | |
| 298 | #define BCM43xx_IRQ_SCAN (1 << 16) | |
| 299 | #define BCM43xx_IRQ_NOISE (1 << 18) | |
| 300 | #define BCM43xx_IRQ_XMIT_STATUS (1 << 29) | |
| 301 | ||
| 302 | #define BCM43xx_IRQ_ALL 0xffffffff | |
| 303 | #define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \ | |
| 304 | BCM43xx_IRQ_REG124 | \ | |
| 305 | BCM43xx_IRQ_PMQ | \ | |
| 306 | BCM43xx_IRQ_XMIT_ERROR | \ | |
| 307 | BCM43xx_IRQ_RX | \ | |
| 308 | BCM43xx_IRQ_SCAN | \ | |
| 309 | BCM43xx_IRQ_NOISE | \ | |
| 310 | BCM43xx_IRQ_XMIT_STATUS) | |
| 311 | ||
| 312 | ||
| 313 | /* Initial default iw_mode */ | |
| 314 | #define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA | |
| 315 | ||
| 316 | /* Values/Masks for the device TX header */ | |
| 317 | #define BCM43xx_TXHDRFLAG_EXPECTACK 0x0001 | |
| 318 | #define BCM43xx_TXHDRFLAG_FIRSTFRAGMENT 0x0008 | |
| 319 | #define BCM43xx_TXHDRFLAG_DESTPSMODE 0x0020 | |
| 320 | #define BCM43xx_TXHDRFLAG_FALLBACKOFDM 0x0100 | |
| 321 | #define BCM43xx_TXHDRFLAG_FRAMEBURST 0x0800 | |
| 322 | ||
| 323 | #define BCM43xx_TXHDRCTL_OFDM 0x0001 | |
| 324 | #define BCM43xx_TXHDRCTL_SHORT_PREAMBLE 0x0010 | |
| 325 | #define BCM43xx_TXHDRCTL_ANTENNADIV_MASK 0x0030 | |
| 326 | #define BCM43xx_TXHDRCTL_ANTENNADIV_SHIFT 8 | |
| 327 | ||
| 328 | #define BCM43xx_TXHDR_WSEC_KEYINDEX_MASK 0x00F0 | |
| 329 | #define BCM43xx_TXHDR_WSEC_KEYINDEX_SHIFT 4 | |
| 330 | #define BCM43xx_TXHDR_WSEC_ALGO_MASK 0x0003 | |
| 331 | #define BCM43xx_TXHDR_WSEC_ALGO_SHIFT 0 | |
| 332 | ||
| 333 | /* Bus type PCI. */ | |
| 334 | #define BCM43xx_BUSTYPE_PCI 0 | |
| 335 | /* Bus type Silicone Backplane Bus. */ | |
| 336 | #define BCM43xx_BUSTYPE_SB 1 | |
| 337 | /* Bus type PCMCIA. */ | |
| 338 | #define BCM43xx_BUSTYPE_PCMCIA 2 | |
| 339 | ||
| 340 | /* Threshold values. */ | |
| 341 | #define BCM43xx_MIN_RTS_THRESHOLD 1U | |
| 342 | #define BCM43xx_MAX_RTS_THRESHOLD 2304U | |
| 343 | #define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD | |
| 344 | ||
| 345 | #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 | |
| 346 | #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 | |
| 347 | ||
| 348 | /* Max size of a security key */ | |
| 349 | #define BCM43xx_SEC_KEYSIZE 16 | |
| 350 | /* Security algorithms. */ | |
| 351 | enum { | |
| 352 | BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ | |
| 353 | BCM43xx_SEC_ALGO_WEP, | |
| 354 | BCM43xx_SEC_ALGO_UNKNOWN, | |
| 355 | BCM43xx_SEC_ALGO_AES, | |
| 356 | BCM43xx_SEC_ALGO_WEP104, | |
| 357 | BCM43xx_SEC_ALGO_TKIP, | |
| 358 | }; | |
| 359 | ||
| 360 | #ifdef assert | |
| 361 | # undef assert | |
| 362 | #endif | |
| 363 | #ifdef CONFIG_BCM43XX_DEBUG | |
| 364 | #define assert(expr) \ | |
| 365 | do { \ | |
| 366 | if (unlikely(!(expr))) { \ | |
| 367 | printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \ | |
| 368 | #expr, __FILE__, __LINE__, __FUNCTION__); \ | |
| 369 | } \ | |
| 370 | } while (0) | |
| 371 | #else | |
| 372 | #define assert(expr) do { /* nothing */ } while (0) | |
| 373 | #endif | |
| 374 | ||
| 375 | /* rate limited printk(). */ | |
| 376 | #ifdef printkl | |
| 377 | # undef printkl | |
| 378 | #endif | |
| 379 | #define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0) | |
| 380 | /* rate limited printk() for debugging */ | |
| 381 | #ifdef dprintkl | |
| 382 | # undef dprintkl | |
| 383 | #endif | |
| 384 | #ifdef CONFIG_BCM43XX_DEBUG | |
| 385 | # define dprintkl printkl | |
| 386 | #else | |
| 387 | # define dprintkl(f, x...) do { /* nothing */ } while (0) | |
| 388 | #endif | |
| 389 | ||
| 390 | /* Helper macro for if branches. | |
| 391 | * An if branch marked with this macro is only taken in DEBUG mode. | |
| 392 | * Example: | |
| 393 | * if (DEBUG_ONLY(foo == bar)) { | |
| 394 | * do something | |
| 395 | * } | |
| 396 | * In DEBUG mode, the branch will be taken if (foo == bar). | |
| 397 | * In non-DEBUG mode, the branch will never be taken. | |
| 398 | */ | |
| 399 | #ifdef DEBUG_ONLY | |
| 400 | # undef DEBUG_ONLY | |
| 401 | #endif | |
| 402 | #ifdef CONFIG_BCM43XX_DEBUG | |
| 403 | # define DEBUG_ONLY(x) (x) | |
| 404 | #else | |
| 405 | # define DEBUG_ONLY(x) 0 | |
| 406 | #endif | |
| 407 | ||
| 408 | /* debugging printk() */ | |
| 409 | #ifdef dprintk | |
| 410 | # undef dprintk | |
| 411 | #endif | |
| 412 | #ifdef CONFIG_BCM43XX_DEBUG | |
| 413 | # define dprintk(f, x...) do { printk(f ,##x); } while (0) | |
| 414 | #else | |
| 415 | # define dprintk(f, x...) do { /* nothing */ } while (0) | |
| 416 | #endif | |
| 417 | ||
| 418 | ||
| 419 | struct net_device; | |
| 420 | struct pci_dev; | |
| 421 | struct workqueue_struct; | |
| 422 | struct bcm43xx_dmaring; | |
| 423 | struct bcm43xx_pioqueue; | |
| 424 | ||
| 425 | struct bcm43xx_initval { | |
| 426 | u16 offset; | |
| 427 | u16 size; | |
| 428 | u32 value; | |
| 429 | } __attribute__((__packed__)); | |
| 430 | ||
| 431 | /* Values for bcm430x_sprominfo.locale */ | |
| 432 | enum { | |
| 433 | BCM43xx_LOCALE_WORLD = 0, | |
| 434 | BCM43xx_LOCALE_THAILAND, | |
| 435 | BCM43xx_LOCALE_ISRAEL, | |
| 436 | BCM43xx_LOCALE_JORDAN, | |
| 437 | BCM43xx_LOCALE_CHINA, | |
| 438 | BCM43xx_LOCALE_JAPAN, | |
| 439 | BCM43xx_LOCALE_USA_CANADA_ANZ, | |
| 440 | BCM43xx_LOCALE_EUROPE, | |
| 441 | BCM43xx_LOCALE_USA_LOW, | |
| 442 | BCM43xx_LOCALE_JAPAN_HIGH, | |
| 443 | BCM43xx_LOCALE_ALL, | |
| 444 | BCM43xx_LOCALE_NONE, | |
| 445 | }; | |
| 446 | ||
| 447 | #define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */ | |
| 448 | struct bcm43xx_sprominfo { | |
| 449 | u16 boardflags2; | |
| 450 | u8 il0macaddr[6]; | |
| 451 | u8 et0macaddr[6]; | |
| 452 | u8 et1macaddr[6]; | |
| 453 | u8 et0phyaddr:5; | |
| 454 | u8 et1phyaddr:5; | |
| 455 | u8 et0mdcport:1; | |
| 456 | u8 et1mdcport:1; | |
| 457 | u8 boardrev; | |
| 458 | u8 locale:4; | |
| 459 | u8 antennas_aphy:2; | |
| 460 | u8 antennas_bgphy:2; | |
| 461 | u16 pa0b0; | |
| 462 | u16 pa0b1; | |
| 463 | u16 pa0b2; | |
| 464 | u8 wl0gpio0; | |
| 465 | u8 wl0gpio1; | |
| 466 | u8 wl0gpio2; | |
| 467 | u8 wl0gpio3; | |
| 468 | u8 maxpower_aphy; | |
| 469 | u8 maxpower_bgphy; | |
| 470 | u16 pa1b0; | |
| 471 | u16 pa1b1; | |
| 472 | u16 pa1b2; | |
| 473 | u8 idle_tssi_tgt_aphy; | |
| 474 | u8 idle_tssi_tgt_bgphy; | |
| 475 | u16 boardflags; | |
| 476 | u16 antennagain_aphy; | |
| 477 | u16 antennagain_bgphy; | |
| 478 | }; | |
| 479 | ||
| 480 | /* Value pair to measure the LocalOscillator. */ | |
| 481 | struct bcm43xx_lopair { | |
| 482 | s8 low; | |
| 483 | s8 high; | |
| 484 | u8 used:1; | |
| 485 | }; | |
| 486 | #define BCM43xx_LO_COUNT (14*4) | |
| 487 | ||
| 488 | struct bcm43xx_phyinfo { | |
| 489 | /* Hardware Data */ | |
| 490 | u8 version; | |
| 491 | u8 type; | |
| 492 | u8 rev; | |
| 493 | u16 antenna_diversity; | |
| 494 | u16 savedpctlreg; | |
| 495 | u16 minlowsig[2]; | |
| 496 | u16 minlowsigpos[2]; | |
| 497 | u8 connected:1, | |
| 498 | calibrated:1, | |
| 499 | is_locked:1, /* used in bcm43xx_phy_{un}lock() */ | |
| 500 | dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */ | |
| 501 | /* LO Measurement Data. | |
| 502 | * Use bcm43xx_get_lopair() to get a value. | |
| 503 | */ | |
| 504 | struct bcm43xx_lopair *_lo_pairs; | |
| 505 | ||
| 506 | /* TSSI to dBm table in use */ | |
| 507 | const s8 *tssi2dbm; | |
| 508 | /* idle TSSI value */ | |
| 509 | s8 idle_tssi; | |
| 510 | /* PHY lock for core.rev < 3 | |
| 511 | * This lock is only used by bcm43xx_phy_{un}lock() | |
| 512 | */ | |
| 513 | spinlock_t lock; | |
| 514 | }; | |
| 515 | ||
| 516 | ||
| 517 | struct bcm43xx_radioinfo { | |
| 518 | u16 manufact; | |
| 519 | u16 version; | |
| 520 | u8 revision; | |
| 521 | ||
| 522 | /* 0: baseband attenuation, | |
| 523 | * 1: radio attenuation, | |
| 524 | * 2: tx_CTL1 | |
| 525 | * 3: tx_CTL2 | |
| 526 | */ | |
| 527 | u16 txpower[4]; | |
| 393344f6 MB |
528 | /* Desired TX power in dBm Q5.2 */ |
| 529 | u16 txpower_desired; | |
| f222313a JL |
530 | /* Current Interference Mitigation mode */ |
| 531 | int interfmode; | |
| 532 | /* Stack of saved values from the Interference Mitigation code */ | |
| 533 | u16 interfstack[20]; | |
| 534 | /* Saved values from the NRSSI Slope calculation */ | |
| 535 | s16 nrssi[2]; | |
| 536 | s32 nrssislope; | |
| 537 | /* In memory nrssi lookup table. */ | |
| 538 | s8 nrssi_lt[64]; | |
| 539 | ||
| 540 | /* current channel */ | |
| 541 | u8 channel; | |
| 542 | u8 initial_channel; | |
| 543 | ||
| 544 | u16 lofcal; | |
| 545 | ||
| 546 | u16 initval; | |
| 547 | ||
| 548 | u8 enabled:1; | |
| 549 | /* ACI (adjacent channel interference) flags. */ | |
| 550 | u8 aci_enable:1, | |
| 551 | aci_wlan_automatic:1, | |
| 552 | aci_hw_rssi:1; | |
| 553 | }; | |
| 554 | ||
| 555 | /* Data structures for DMA transmission, per 80211 core. */ | |
| 556 | struct bcm43xx_dma { | |
| 557 | struct bcm43xx_dmaring *tx_ring0; | |
| 558 | struct bcm43xx_dmaring *tx_ring1; | |
| 559 | struct bcm43xx_dmaring *tx_ring2; | |
| 560 | struct bcm43xx_dmaring *tx_ring3; | |
| 561 | struct bcm43xx_dmaring *rx_ring0; | |
| 562 | struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */ | |
| 563 | }; | |
| 564 | ||
| 565 | /* Data structures for PIO transmission, per 80211 core. */ | |
| 566 | struct bcm43xx_pio { | |
| 567 | struct bcm43xx_pioqueue *queue0; | |
| 568 | struct bcm43xx_pioqueue *queue1; | |
| 569 | struct bcm43xx_pioqueue *queue2; | |
| 570 | struct bcm43xx_pioqueue *queue3; | |
| 571 | }; | |
| 572 | ||
| 573 | #define BCM43xx_MAX_80211_CORES 2 | |
| 574 | ||
| 575 | #define BCM43xx_COREFLAG_AVAILABLE (1 << 0) | |
| 576 | #define BCM43xx_COREFLAG_ENABLED (1 << 1) | |
| 577 | #define BCM43xx_COREFLAG_INITIALIZED (1 << 2) | |
| 578 | ||
| 579 | #ifdef CONFIG_BCM947XX | |
| 580 | #define core_offset(bcm) (bcm)->current_core_offset | |
| 581 | #else | |
| 582 | #define core_offset(bcm) 0 | |
| 583 | #endif | |
| 584 | ||
| 585 | struct bcm43xx_coreinfo { | |
| 586 | /** Driver internal flags. See BCM43xx_COREFLAG_* */ | |
| 587 | u32 flags; | |
| 588 | /** core_id ID number */ | |
| 589 | u16 id; | |
| 590 | /** core_rev revision number */ | |
| 591 | u8 rev; | |
| 592 | /** Index number for _switch_core() */ | |
| 593 | u8 index; | |
| 594 | /* Pointer to the PHYinfo, which belongs to this core (if 80211 core) */ | |
| 595 | struct bcm43xx_phyinfo *phy; | |
| 596 | /* Pointer to the RadioInfo, which belongs to this core (if 80211 core) */ | |
| 597 | struct bcm43xx_radioinfo *radio; | |
| 598 | /* Pointer to the DMA rings, which belong to this core (if 80211 core) */ | |
| 599 | struct bcm43xx_dma *dma; | |
| 600 | /* Pointer to the PIO queues, which belong to this core (if 80211 core) */ | |
| 601 | struct bcm43xx_pio *pio; | |
| 602 | }; | |
| 603 | ||
| 604 | /* Context information for a noise calculation (Link Quality). */ | |
| 605 | struct bcm43xx_noise_calculation { | |
| 606 | struct bcm43xx_coreinfo *core_at_start; | |
| 607 | u8 channel_at_start; | |
| 608 | u8 calculation_running:1; | |
| 609 | u8 nr_samples; | |
| 610 | s8 samples[8][4]; | |
| 611 | }; | |
| 612 | ||
| 613 | struct bcm43xx_stats { | |
| 614 | u8 link_quality; | |
| 615 | /* Store the last TX/RX times here for updating the leds. */ | |
| 616 | unsigned long last_tx; | |
| 617 | unsigned long last_rx; | |
| 618 | }; | |
| 619 | ||
| 620 | struct bcm43xx_key { | |
| 621 | u8 enabled:1; | |
| 622 | u8 algorithm; | |
| 623 | }; | |
| 624 | ||
| 625 | struct bcm43xx_private { | |
| 626 | struct ieee80211_device *ieee; | |
| 627 | struct ieee80211softmac_device *softmac; | |
| 628 | ||
| 629 | struct net_device *net_dev; | |
| 630 | struct pci_dev *pci_dev; | |
| 631 | unsigned int irq; | |
| 632 | ||
| 633 | void __iomem *mmio_addr; | |
| 634 | unsigned int mmio_len; | |
| 635 | ||
| 636 | spinlock_t lock; | |
| 637 | ||
| 638 | /* Driver status flags. */ | |
| 639 | u32 initialized:1, /* init_board() succeed */ | |
| 640 | was_initialized:1, /* for PCI suspend/resume. */ | |
| 641 | shutting_down:1, /* free_board() in progress */ | |
| 642 | pio_mode:1, /* PIO (if true), or DMA (if false) used. */ | |
| 643 | bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */ | |
| 644 | reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */ | |
| 645 | powersaving:1, /* TRUE if we are in PowerSaving mode. FALSE otherwise. */ | |
| 646 | short_preamble:1, /* TRUE, if short preamble is enabled. */ | |
| 647 | firmware_norelease:1; /* Do not release the firmware. Used on suspend. */ | |
| 648 | ||
| 649 | struct bcm43xx_stats stats; | |
| 650 | ||
| 651 | /* Bus type we are connected to. | |
| 652 | * This is currently always BCM43xx_BUSTYPE_PCI | |
| 653 | */ | |
| 654 | u8 bustype; | |
| 655 | ||
| 656 | u16 board_vendor; | |
| 657 | u16 board_type; | |
| 658 | u16 board_revision; | |
| 659 | ||
| 660 | u16 chip_id; | |
| 661 | u8 chip_rev; | |
| 662 | ||
| 663 | struct bcm43xx_sprominfo sprom; | |
| 664 | #define BCM43xx_NR_LEDS 4 | |
| 665 | struct bcm43xx_led leds[BCM43xx_NR_LEDS]; | |
| 666 | ||
| 667 | /* The currently active core. NULL if not initialized, yet. */ | |
| 668 | struct bcm43xx_coreinfo *current_core; | |
| 669 | #ifdef CONFIG_BCM947XX | |
| 670 | /** current core memory offset */ | |
| 671 | u32 current_core_offset; | |
| 672 | #endif | |
| 673 | struct bcm43xx_coreinfo *active_80211_core; | |
| 674 | /* coreinfo structs for all possible cores follow. | |
| 675 | * Note that a core might not exist. | |
| 676 | * So check the coreinfo flags before using it. | |
| 677 | */ | |
| 678 | struct bcm43xx_coreinfo core_chipcommon; | |
| 679 | struct bcm43xx_coreinfo core_pci; | |
| 680 | struct bcm43xx_coreinfo core_v90; | |
| 681 | struct bcm43xx_coreinfo core_pcmcia; | |
| 682 | struct bcm43xx_coreinfo core_ethernet; | |
| 683 | struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ]; | |
| 684 | /* Info about the PHY for each 80211 core. */ | |
| 685 | struct bcm43xx_phyinfo phy[ BCM43xx_MAX_80211_CORES ]; | |
| 686 | /* Info about the Radio for each 80211 core. */ | |
| 687 | struct bcm43xx_radioinfo radio[ BCM43xx_MAX_80211_CORES ]; | |
| 688 | /* DMA */ | |
| 689 | struct bcm43xx_dma dma[ BCM43xx_MAX_80211_CORES ]; | |
| 690 | /* PIO */ | |
| 691 | struct bcm43xx_pio pio[ BCM43xx_MAX_80211_CORES ]; | |
| 692 | ||
| 693 | u32 chipcommon_capabilities; | |
| 694 | ||
| 695 | /* Reason code of the last interrupt. */ | |
| 696 | u32 irq_reason; | |
| 697 | u32 dma_reason[4]; | |
| 698 | /* saved irq enable/disable state bitfield. */ | |
| 699 | u32 irq_savedstate; | |
| 700 | /* Link Quality calculation context. */ | |
| 701 | struct bcm43xx_noise_calculation noisecalc; | |
| 702 | ||
| 703 | /* Threshold values. */ | |
| 704 | //TODO: The RTS thr has to be _used_. Currently, it is only set via WX. | |
| 705 | u32 rts_threshold; | |
| 706 | ||
| 707 | /* Interrupt Service Routine tasklet (bottom-half) */ | |
| 708 | struct tasklet_struct isr_tasklet; | |
| 709 | /* Custom driver work queue. */ | |
| 710 | struct workqueue_struct *workqueue; | |
| 711 | ||
| 712 | /* Periodic tasks */ | |
| 713 | struct work_struct periodic_work0; | |
| 714 | #define BCM43xx_PERIODIC_0_DELAY (HZ * 15) | |
| 715 | struct work_struct periodic_work1; | |
| 716 | #define BCM43xx_PERIODIC_1_DELAY ((HZ * 60) + HZ / 2) | |
| 717 | struct work_struct periodic_work2; | |
| 718 | #define BCM43xx_PERIODIC_2_DELAY ((HZ * 120) + HZ) | |
| 719 | struct work_struct periodic_work3; | |
| 720 | #define BCM43xx_PERIODIC_3_DELAY ((HZ * 30) + HZ / 5) | |
| 721 | ||
| 722 | struct work_struct restart_work; | |
| 723 | ||
| 724 | /* Informational stuff. */ | |
| 725 | char nick[IW_ESSID_MAX_SIZE + 1]; | |
| 726 | ||
| 727 | /* encryption/decryption */ | |
| 728 | u16 security_offset; | |
| 729 | struct bcm43xx_key key[54]; | |
| 730 | u8 default_key_idx; | |
| 731 | ||
| 732 | /* Firmware. */ | |
| 733 | const struct firmware *ucode; | |
| 734 | const struct firmware *pcm; | |
| 735 | const struct firmware *initvals0; | |
| 736 | const struct firmware *initvals1; | |
| 737 | ||
| 738 | /* Debugging stuff follows. */ | |
| 739 | #ifdef CONFIG_BCM43XX_DEBUG | |
| 740 | struct bcm43xx_dfsentry *dfsentry; | |
| 741 | atomic_t mmio_print_cnt; | |
| 742 | atomic_t pcicfg_print_cnt; | |
| 743 | #endif | |
| 744 | }; | |
| 745 | ||
| 746 | static inline | |
| 747 | struct bcm43xx_private * bcm43xx_priv(struct net_device *dev) | |
| 748 | { | |
| 749 | return ieee80211softmac_priv(dev); | |
| 750 | } | |
| 751 | ||
| 752 | static inline | |
| 753 | int bcm43xx_num_80211_cores(struct bcm43xx_private *bcm) | |
| 754 | { | |
| 755 | int i, cnt = 0; | |
| 756 | ||
| 757 | for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) { | |
| 758 | if (bcm->core_80211[i].flags & BCM43xx_COREFLAG_AVAILABLE) | |
| 759 | cnt++; | |
| 760 | } | |
| 761 | ||
| 762 | return cnt; | |
| 763 | } | |
| 764 | ||
| 765 | /* Are we running in init_board() context? */ | |
| 766 | static inline | |
| 767 | int bcm43xx_is_initializing(struct bcm43xx_private *bcm) | |
| 768 | { | |
| 769 | if (bcm->initialized) | |
| 770 | return 0; | |
| 771 | if (bcm->shutting_down) | |
| 772 | return 0; | |
| 773 | return 1; | |
| 774 | } | |
| 775 | ||
| 776 | static inline | |
| 777 | struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy, | |
| 778 | u16 radio_attenuation, | |
| 779 | u16 baseband_attenuation) | |
| 780 | { | |
| 781 | return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2)); | |
| 782 | } | |
| 783 | ||
| 784 | ||
| 785 | /* MMIO read/write functions. Debug and non-debug variants. */ | |
| 786 | #ifdef CONFIG_BCM43XX_DEBUG | |
| 787 | ||
| 788 | static inline | |
| 789 | u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset) | |
| 790 | { | |
| 791 | u16 value; | |
| 792 | ||
| 793 | value = ioread16(bcm->mmio_addr + core_offset(bcm) + offset); | |
| 794 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
| 795 | printk(KERN_INFO PFX "ioread16 offset: 0x%04x, value: 0x%04x\n", | |
| 796 | offset, value); | |
| 797 | } | |
| 798 | ||
| 799 | return value; | |
| 800 | } | |
| 801 | ||
| 802 | static inline | |
| 803 | void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value) | |
| 804 | { | |
| 805 | iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset); | |
| 806 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
| 807 | printk(KERN_INFO PFX "iowrite16 offset: 0x%04x, value: 0x%04x\n", | |
| 808 | offset, value); | |
| 809 | } | |
| 810 | } | |
| 811 | ||
| 812 | static inline | |
| 813 | u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset) | |
| 814 | { | |
| 815 | u32 value; | |
| 816 | ||
| 817 | value = ioread32(bcm->mmio_addr + core_offset(bcm) + offset); | |
| 818 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
| 819 | printk(KERN_INFO PFX "ioread32 offset: 0x%04x, value: 0x%08x\n", | |
| 820 | offset, value); | |
| 821 | } | |
| 822 | ||
| 823 | return value; | |
| 824 | } | |
| 825 | ||
| 826 | static inline | |
| 827 | void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value) | |
| 828 | { | |
| 829 | iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset); | |
| 830 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
| 831 | printk(KERN_INFO PFX "iowrite32 offset: 0x%04x, value: 0x%08x\n", | |
| 832 | offset, value); | |
| 833 | } | |
| 834 | } | |
| 835 | ||
| 836 | static inline | |
| 837 | int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value) | |
| 838 | { | |
| 839 | int err; | |
| 840 | ||
| 841 | err = pci_read_config_word(bcm->pci_dev, offset, value); | |
| 842 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
| 843 | printk(KERN_INFO PFX "pciread16 offset: 0x%08x, value: 0x%04x, err: %d\n", | |
| 844 | offset, *value, err); | |
| 845 | } | |
| 846 | ||
| 847 | return err; | |
| 848 | } | |
| 849 | ||
| 850 | static inline | |
| 851 | int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value) | |
| 852 | { | |
| 853 | int err; | |
| 854 | ||
| 855 | err = pci_read_config_dword(bcm->pci_dev, offset, value); | |
| 856 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
| 857 | printk(KERN_INFO PFX "pciread32 offset: 0x%08x, value: 0x%08x, err: %d\n", | |
| 858 | offset, *value, err); | |
| 859 | } | |
| 860 | ||
| 861 | return err; | |
| 862 | } | |
| 863 | ||
| 864 | static inline | |
| 865 | int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value) | |
| 866 | { | |
| 867 | int err; | |
| 868 | ||
| 869 | err = pci_write_config_word(bcm->pci_dev, offset, value); | |
| 870 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
| 871 | printk(KERN_INFO PFX "pciwrite16 offset: 0x%08x, value: 0x%04x, err: %d\n", | |
| 872 | offset, value, err); | |
| 873 | } | |
| 874 | ||
| 875 | return err; | |
| 876 | } | |
| 877 | ||
| 878 | static inline | |
| 879 | int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value) | |
| 880 | { | |
| 881 | int err; | |
| 882 | ||
| 883 | err = pci_write_config_dword(bcm->pci_dev, offset, value); | |
| 884 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
| 885 | printk(KERN_INFO PFX "pciwrite32 offset: 0x%08x, value: 0x%08x, err: %d\n", | |
| 886 | offset, value, err); | |
| 887 | } | |
| 888 | ||
| 889 | return err; | |
| 890 | } | |
| 891 | ||
| 892 | #define bcm43xx_mmioprint_initial(bcm, value) atomic_set(&(bcm)->mmio_print_cnt, (value)) | |
| 893 | #define bcm43xx_mmioprint_enable(bcm) atomic_inc(&(bcm)->mmio_print_cnt) | |
| 894 | #define bcm43xx_mmioprint_disable(bcm) atomic_dec(&(bcm)->mmio_print_cnt) | |
| 895 | #define bcm43xx_pciprint_initial(bcm, value) atomic_set(&(bcm)->pcicfg_print_cnt, (value)) | |
| 896 | #define bcm43xx_pciprint_enable(bcm) atomic_inc(&(bcm)->pcicfg_print_cnt) | |
| 897 | #define bcm43xx_pciprint_disable(bcm) atomic_dec(&(bcm)->pcicfg_print_cnt) | |
| 898 | ||
| 899 | #else /* CONFIG_BCM43XX_DEBUG*/ | |
| 900 | ||
| 901 | #define bcm43xx_read16(bcm, offset) ioread16((bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
| 902 | #define bcm43xx_write16(bcm, offset, value) iowrite16((value), (bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
| 903 | #define bcm43xx_read32(bcm, offset) ioread32((bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
| 904 | #define bcm43xx_write32(bcm, offset, value) iowrite32((value), (bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
| 905 | #define bcm43xx_pci_read_config16(bcm, o, v) pci_read_config_word((bcm)->pci_dev, (o), (v)) | |
| 906 | #define bcm43xx_pci_read_config32(bcm, o, v) pci_read_config_dword((bcm)->pci_dev, (o), (v)) | |
| 907 | #define bcm43xx_pci_write_config16(bcm, o, v) pci_write_config_word((bcm)->pci_dev, (o), (v)) | |
| 908 | #define bcm43xx_pci_write_config32(bcm, o, v) pci_write_config_dword((bcm)->pci_dev, (o), (v)) | |
| 909 | ||
| 910 | #define bcm43xx_mmioprint_initial(x, y) do { /* nothing */ } while (0) | |
| 911 | #define bcm43xx_mmioprint_enable(x) do { /* nothing */ } while (0) | |
| 912 | #define bcm43xx_mmioprint_disable(x) do { /* nothing */ } while (0) | |
| 913 | #define bcm43xx_pciprint_initial(bcm, value) do { /* nothing */ } while (0) | |
| 914 | #define bcm43xx_pciprint_enable(bcm) do { /* nothing */ } while (0) | |
| 915 | #define bcm43xx_pciprint_disable(bcm) do { /* nothing */ } while (0) | |
| 916 | ||
| 917 | #endif /* CONFIG_BCM43XX_DEBUG*/ | |
| 918 | ||
| 919 | ||
| 920 | /** Limit a value between two limits */ | |
| 921 | #ifdef limit_value | |
| 922 | # undef limit_value | |
| 923 | #endif | |
| 924 | #define limit_value(value, min, max) \ | |
| 925 | ({ \ | |
| 926 | typeof(value) __value = (value); \ | |
| 927 | typeof(value) __min = (min); \ | |
| 928 | typeof(value) __max = (max); \ | |
| 929 | if (__value < __min) \ | |
| 930 | __value = __min; \ | |
| 931 | else if (__value > __max) \ | |
| 932 | __value = __max; \ | |
| 933 | __value; \ | |
| 934 | }) | |
| 935 | ||
| f222313a | 936 | #endif /* BCM43xx_H_ */ |