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f222313a JL |
1 | #ifndef BCM43xx_H_ |
2 | #define BCM43xx_H_ | |
3 | ||
4 | #include <linux/version.h> | |
5 | #include <linux/kernel.h> | |
6 | #include <linux/spinlock.h> | |
7 | #include <linux/interrupt.h> | |
8 | #include <linux/stringify.h> | |
9 | #include <linux/pci.h> | |
10 | #include <net/ieee80211.h> | |
11 | #include <net/ieee80211softmac.h> | |
12 | #include <asm/atomic.h> | |
13 | #include <asm/io.h> | |
14 | ||
15 | ||
16 | #include "bcm43xx_debugfs.h" | |
17 | #include "bcm43xx_leds.h" | |
18 | ||
19 | ||
65f3f191 | 20 | #define PFX KBUILD_MODNAME ": " |
f222313a JL |
21 | |
22 | #define BCM43xx_SWITCH_CORE_MAX_RETRIES 10 | |
23 | #define BCM43xx_IRQWAIT_MAX_RETRIES 50 | |
f222313a JL |
24 | |
25 | #define BCM43xx_IO_SIZE 8192 | |
26 | #define BCM43xx_REG_ACTIVE_CORE 0x80 | |
27 | ||
28 | /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */ | |
29 | #define BCM43xx_PCICFG_ICR 0x94 | |
30 | /* SPROM control register. */ | |
31 | #define BCM43xx_PCICFG_SPROMCTL 0x88 | |
32 | ||
33 | /* MMIO offsets */ | |
34 | #define BCM43xx_MMIO_DMA1_REASON 0x20 | |
35 | #define BCM43xx_MMIO_DMA1_IRQ_MASK 0x24 | |
36 | #define BCM43xx_MMIO_DMA2_REASON 0x28 | |
37 | #define BCM43xx_MMIO_DMA2_IRQ_MASK 0x2C | |
38 | #define BCM43xx_MMIO_DMA3_REASON 0x30 | |
39 | #define BCM43xx_MMIO_DMA3_IRQ_MASK 0x34 | |
40 | #define BCM43xx_MMIO_DMA4_REASON 0x38 | |
41 | #define BCM43xx_MMIO_DMA4_IRQ_MASK 0x3C | |
42 | #define BCM43xx_MMIO_STATUS_BITFIELD 0x120 | |
43 | #define BCM43xx_MMIO_STATUS2_BITFIELD 0x124 | |
44 | #define BCM43xx_MMIO_GEN_IRQ_REASON 0x128 | |
45 | #define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C | |
46 | #define BCM43xx_MMIO_RAM_CONTROL 0x130 | |
47 | #define BCM43xx_MMIO_RAM_DATA 0x134 | |
48 | #define BCM43xx_MMIO_PS_STATUS 0x140 | |
49 | #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158 | |
50 | #define BCM43xx_MMIO_SHM_CONTROL 0x160 | |
51 | #define BCM43xx_MMIO_SHM_DATA 0x164 | |
52 | #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166 | |
53 | #define BCM43xx_MMIO_XMITSTAT_0 0x170 | |
54 | #define BCM43xx_MMIO_XMITSTAT_1 0x174 | |
55 | #define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ | |
56 | #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ | |
57 | #define BCM43xx_MMIO_DMA1_BASE 0x200 | |
58 | #define BCM43xx_MMIO_DMA2_BASE 0x220 | |
59 | #define BCM43xx_MMIO_DMA3_BASE 0x240 | |
60 | #define BCM43xx_MMIO_DMA4_BASE 0x260 | |
61 | #define BCM43xx_MMIO_PIO1_BASE 0x300 | |
62 | #define BCM43xx_MMIO_PIO2_BASE 0x310 | |
63 | #define BCM43xx_MMIO_PIO3_BASE 0x320 | |
64 | #define BCM43xx_MMIO_PIO4_BASE 0x330 | |
65 | #define BCM43xx_MMIO_PHY_VER 0x3E0 | |
66 | #define BCM43xx_MMIO_PHY_RADIO 0x3E2 | |
67 | #define BCM43xx_MMIO_ANTENNA 0x3E8 | |
68 | #define BCM43xx_MMIO_CHANNEL 0x3F0 | |
69 | #define BCM43xx_MMIO_CHANNEL_EXT 0x3F4 | |
70 | #define BCM43xx_MMIO_RADIO_CONTROL 0x3F6 | |
71 | #define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8 | |
72 | #define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA | |
73 | #define BCM43xx_MMIO_PHY_CONTROL 0x3FC | |
74 | #define BCM43xx_MMIO_PHY_DATA 0x3FE | |
75 | #define BCM43xx_MMIO_MACFILTER_CONTROL 0x420 | |
76 | #define BCM43xx_MMIO_MACFILTER_DATA 0x422 | |
77 | #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A | |
78 | #define BCM43xx_MMIO_GPIO_CONTROL 0x49C | |
79 | #define BCM43xx_MMIO_GPIO_MASK 0x49E | |
80 | #define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */ | |
81 | #define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */ | |
82 | #define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */ | |
83 | #define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */ | |
84 | #define BCM43xx_MMIO_POWERUP_DELAY 0x6A8 | |
85 | ||
86 | /* SPROM offsets. */ | |
87 | #define BCM43xx_SPROM_BASE 0x1000 | |
88 | #define BCM43xx_SPROM_BOARDFLAGS2 0x1c | |
89 | #define BCM43xx_SPROM_IL0MACADDR 0x24 | |
90 | #define BCM43xx_SPROM_ET0MACADDR 0x27 | |
91 | #define BCM43xx_SPROM_ET1MACADDR 0x2a | |
92 | #define BCM43xx_SPROM_ETHPHY 0x2d | |
93 | #define BCM43xx_SPROM_BOARDREV 0x2e | |
94 | #define BCM43xx_SPROM_PA0B0 0x2f | |
95 | #define BCM43xx_SPROM_PA0B1 0x30 | |
96 | #define BCM43xx_SPROM_PA0B2 0x31 | |
97 | #define BCM43xx_SPROM_WL0GPIO0 0x32 | |
98 | #define BCM43xx_SPROM_WL0GPIO2 0x33 | |
99 | #define BCM43xx_SPROM_MAXPWR 0x34 | |
100 | #define BCM43xx_SPROM_PA1B0 0x35 | |
101 | #define BCM43xx_SPROM_PA1B1 0x36 | |
102 | #define BCM43xx_SPROM_PA1B2 0x37 | |
103 | #define BCM43xx_SPROM_IDL_TSSI_TGT 0x38 | |
104 | #define BCM43xx_SPROM_BOARDFLAGS 0x39 | |
105 | #define BCM43xx_SPROM_ANTENNA_GAIN 0x3a | |
106 | #define BCM43xx_SPROM_VERSION 0x3f | |
107 | ||
108 | /* BCM43xx_SPROM_BOARDFLAGS values */ | |
109 | #define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ | |
110 | #define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ | |
111 | #define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ | |
112 | #define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ | |
113 | #define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ | |
114 | #define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ | |
115 | #define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ | |
116 | #define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */ | |
117 | #define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */ | |
118 | #define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ | |
119 | #define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */ | |
120 | #define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */ | |
121 | ||
122 | /* GPIO register offset, in both ChipCommon and PCI core. */ | |
123 | #define BCM43xx_GPIO_CONTROL 0x6c | |
124 | ||
125 | /* SHM Routing */ | |
126 | #define BCM43xx_SHM_SHARED 0x0001 | |
127 | #define BCM43xx_SHM_WIRELESS 0x0002 | |
128 | #define BCM43xx_SHM_PCM 0x0003 | |
129 | #define BCM43xx_SHM_HWMAC 0x0004 | |
130 | #define BCM43xx_SHM_UCODE 0x0300 | |
131 | ||
132 | /* MacFilter offsets. */ | |
133 | #define BCM43xx_MACFILTER_SELF 0x0000 | |
134 | #define BCM43xx_MACFILTER_ASSOC 0x0003 | |
135 | ||
136 | /* Chipcommon registers. */ | |
137 | #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 | |
138 | #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 | |
139 | #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 | |
140 | #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 | |
141 | #define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0 | |
142 | ||
143 | /* PCI core specific registers. */ | |
144 | #define BCM43xx_PCICORE_BCAST_ADDR 0x50 | |
145 | #define BCM43xx_PCICORE_BCAST_DATA 0x54 | |
146 | #define BCM43xx_PCICORE_SBTOPCI2 0x108 | |
147 | ||
148 | /* SBTOPCI2 values. */ | |
149 | #define BCM43xx_SBTOPCI2_PREFETCH 0x4 | |
150 | #define BCM43xx_SBTOPCI2_BURST 0x8 | |
151 | ||
152 | /* Chipcommon capabilities. */ | |
153 | #define BCM43xx_CAPABILITIES_PCTL 0x00040000 | |
154 | #define BCM43xx_CAPABILITIES_PLLMASK 0x00030000 | |
155 | #define BCM43xx_CAPABILITIES_PLLSHIFT 16 | |
156 | #define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700 | |
157 | #define BCM43xx_CAPABILITIES_FLASHSHIFT 8 | |
158 | #define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040 | |
159 | #define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020 | |
160 | #define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018 | |
161 | #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3 | |
162 | #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004 | |
163 | #define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003 | |
164 | ||
165 | /* PowerControl */ | |
166 | #define BCM43xx_PCTL_IN 0xB0 | |
167 | #define BCM43xx_PCTL_OUT 0xB4 | |
168 | #define BCM43xx_PCTL_OUTENABLE 0xB8 | |
169 | #define BCM43xx_PCTL_XTAL_POWERUP 0x40 | |
170 | #define BCM43xx_PCTL_PLL_POWERDOWN 0x80 | |
171 | ||
172 | /* PowerControl Clock Modes */ | |
173 | #define BCM43xx_PCTL_CLK_FAST 0x00 | |
174 | #define BCM43xx_PCTL_CLK_SLOW 0x01 | |
175 | #define BCM43xx_PCTL_CLK_DYNAMIC 0x02 | |
176 | ||
177 | #define BCM43xx_PCTL_FORCE_SLOW 0x0800 | |
178 | #define BCM43xx_PCTL_FORCE_PLL 0x1000 | |
179 | #define BCM43xx_PCTL_DYN_XTAL 0x2000 | |
180 | ||
181 | /* COREIDs */ | |
182 | #define BCM43xx_COREID_CHIPCOMMON 0x800 | |
183 | #define BCM43xx_COREID_ILINE20 0x801 | |
184 | #define BCM43xx_COREID_SDRAM 0x803 | |
185 | #define BCM43xx_COREID_PCI 0x804 | |
186 | #define BCM43xx_COREID_MIPS 0x805 | |
187 | #define BCM43xx_COREID_ETHERNET 0x806 | |
188 | #define BCM43xx_COREID_V90 0x807 | |
189 | #define BCM43xx_COREID_USB11_HOSTDEV 0x80a | |
190 | #define BCM43xx_COREID_IPSEC 0x80b | |
191 | #define BCM43xx_COREID_PCMCIA 0x80d | |
192 | #define BCM43xx_COREID_EXT_IF 0x80f | |
193 | #define BCM43xx_COREID_80211 0x812 | |
194 | #define BCM43xx_COREID_MIPS_3302 0x816 | |
195 | #define BCM43xx_COREID_USB11_HOST 0x817 | |
196 | #define BCM43xx_COREID_USB11_DEV 0x818 | |
197 | #define BCM43xx_COREID_USB20_HOST 0x819 | |
198 | #define BCM43xx_COREID_USB20_DEV 0x81a | |
199 | #define BCM43xx_COREID_SDIO_HOST 0x81b | |
200 | ||
201 | /* Core Information Registers */ | |
202 | #define BCM43xx_CIR_BASE 0xf00 | |
203 | #define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18) | |
204 | #define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90) | |
205 | #define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94) | |
206 | #define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98) | |
207 | #define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c) | |
208 | #define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8) | |
209 | #define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc) | |
210 | ||
211 | /* Mask to get the Backplane Flag Number from SBTPSFLAG. */ | |
212 | #define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f | |
213 | ||
214 | /* SBIMCONFIGLOW values/masks. */ | |
215 | #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007 | |
216 | #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0 | |
217 | #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070 | |
218 | #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4 | |
219 | #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000 | |
220 | #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16 | |
221 | ||
222 | /* sbtmstatelow state flags */ | |
223 | #define BCM43xx_SBTMSTATELOW_RESET 0x01 | |
224 | #define BCM43xx_SBTMSTATELOW_REJECT 0x02 | |
225 | #define BCM43xx_SBTMSTATELOW_CLOCK 0x10000 | |
226 | #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000 | |
227 | ||
228 | /* sbtmstatehigh state flags */ | |
229 | #define BCM43xx_SBTMSTATEHIGH_SERROR 0x1 | |
230 | #define BCM43xx_SBTMSTATEHIGH_BUSY 0x4 | |
231 | ||
232 | /* sbimstate flags */ | |
233 | #define BCM43xx_SBIMSTATE_IB_ERROR 0x20000 | |
234 | #define BCM43xx_SBIMSTATE_TIMEOUT 0x40000 | |
235 | ||
236 | /* PHYVersioning */ | |
237 | #define BCM43xx_PHYTYPE_A 0x00 | |
238 | #define BCM43xx_PHYTYPE_B 0x01 | |
239 | #define BCM43xx_PHYTYPE_G 0x02 | |
240 | ||
241 | /* PHYRegisters */ | |
242 | #define BCM43xx_PHY_ILT_A_CTRL 0x0072 | |
243 | #define BCM43xx_PHY_ILT_A_DATA1 0x0073 | |
244 | #define BCM43xx_PHY_ILT_A_DATA2 0x0074 | |
245 | #define BCM43xx_PHY_G_LO_CONTROL 0x0810 | |
246 | #define BCM43xx_PHY_ILT_G_CTRL 0x0472 | |
247 | #define BCM43xx_PHY_ILT_G_DATA1 0x0473 | |
248 | #define BCM43xx_PHY_ILT_G_DATA2 0x0474 | |
249 | #define BCM43xx_PHY_A_PCTL 0x007B | |
250 | #define BCM43xx_PHY_G_PCTL 0x0029 | |
251 | #define BCM43xx_PHY_A_CRS 0x0029 | |
252 | #define BCM43xx_PHY_RADIO_BITFIELD 0x0401 | |
253 | #define BCM43xx_PHY_G_CRS 0x0429 | |
254 | #define BCM43xx_PHY_NRSSILT_CTRL 0x0803 | |
255 | #define BCM43xx_PHY_NRSSILT_DATA 0x0804 | |
256 | ||
257 | /* RadioRegisters */ | |
258 | #define BCM43xx_RADIOCTL_ID 0x01 | |
259 | ||
260 | /* StatusBitField */ | |
261 | #define BCM43xx_SBF_MAC_ENABLED 0x00000001 | |
262 | #define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/ | |
263 | #define BCM43xx_SBF_CORE_READY 0x00000004 | |
264 | #define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/ | |
265 | #define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/ | |
266 | #define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/ | |
267 | #define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000 | |
268 | #define BCM43xx_SBF_MODE_NOTADHOC 0x00020000 | |
269 | #define BCM43xx_SBF_MODE_AP 0x00040000 | |
270 | #define BCM43xx_SBF_RADIOREG_LOCK 0x00080000 | |
271 | #define BCM43xx_SBF_MODE_MONITOR 0x00400000 | |
272 | #define BCM43xx_SBF_MODE_PROMISC 0x01000000 | |
273 | #define BCM43xx_SBF_PS1 0x02000000 | |
274 | #define BCM43xx_SBF_PS2 0x04000000 | |
275 | #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000 | |
276 | #define BCM43xx_SBF_TIME_UPDATE 0x10000000 | |
277 | #define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/ | |
278 | ||
279 | /* MicrocodeFlagsBitfield (addr + lo-word values?)*/ | |
280 | #define BCM43xx_UCODEFLAGS_OFFSET 0x005E | |
281 | ||
282 | #define BCM43xx_UCODEFLAG_AUTODIV 0x0001 | |
283 | #define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002 | |
284 | #define BCM43xx_UCODEFLAG_UNKBPHY 0x0004 | |
285 | #define BCM43xx_UCODEFLAG_UNKGPHY 0x0020 | |
286 | #define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040 | |
287 | #define BCM43xx_UCODEFLAG_JAPAN 0x0080 | |
288 | ||
289 | /* Generic-Interrupt reasons. */ | |
290 | #define BCM43xx_IRQ_READY (1 << 0) | |
291 | #define BCM43xx_IRQ_BEACON (1 << 1) | |
292 | #define BCM43xx_IRQ_PS (1 << 2) | |
293 | #define BCM43xx_IRQ_REG124 (1 << 5) | |
294 | #define BCM43xx_IRQ_PMQ (1 << 6) | |
295 | #define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8) | |
296 | #define BCM43xx_IRQ_XMIT_ERROR (1 << 11) | |
297 | #define BCM43xx_IRQ_RX (1 << 15) | |
298 | #define BCM43xx_IRQ_SCAN (1 << 16) | |
299 | #define BCM43xx_IRQ_NOISE (1 << 18) | |
300 | #define BCM43xx_IRQ_XMIT_STATUS (1 << 29) | |
301 | ||
302 | #define BCM43xx_IRQ_ALL 0xffffffff | |
303 | #define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \ | |
304 | BCM43xx_IRQ_REG124 | \ | |
305 | BCM43xx_IRQ_PMQ | \ | |
306 | BCM43xx_IRQ_XMIT_ERROR | \ | |
307 | BCM43xx_IRQ_RX | \ | |
308 | BCM43xx_IRQ_SCAN | \ | |
309 | BCM43xx_IRQ_NOISE | \ | |
310 | BCM43xx_IRQ_XMIT_STATUS) | |
311 | ||
312 | ||
313 | /* Initial default iw_mode */ | |
314 | #define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA | |
315 | ||
316 | /* Values/Masks for the device TX header */ | |
317 | #define BCM43xx_TXHDRFLAG_EXPECTACK 0x0001 | |
318 | #define BCM43xx_TXHDRFLAG_FIRSTFRAGMENT 0x0008 | |
319 | #define BCM43xx_TXHDRFLAG_DESTPSMODE 0x0020 | |
320 | #define BCM43xx_TXHDRFLAG_FALLBACKOFDM 0x0100 | |
321 | #define BCM43xx_TXHDRFLAG_FRAMEBURST 0x0800 | |
322 | ||
323 | #define BCM43xx_TXHDRCTL_OFDM 0x0001 | |
324 | #define BCM43xx_TXHDRCTL_SHORT_PREAMBLE 0x0010 | |
325 | #define BCM43xx_TXHDRCTL_ANTENNADIV_MASK 0x0030 | |
326 | #define BCM43xx_TXHDRCTL_ANTENNADIV_SHIFT 8 | |
327 | ||
328 | #define BCM43xx_TXHDR_WSEC_KEYINDEX_MASK 0x00F0 | |
329 | #define BCM43xx_TXHDR_WSEC_KEYINDEX_SHIFT 4 | |
330 | #define BCM43xx_TXHDR_WSEC_ALGO_MASK 0x0003 | |
331 | #define BCM43xx_TXHDR_WSEC_ALGO_SHIFT 0 | |
332 | ||
333 | /* Bus type PCI. */ | |
334 | #define BCM43xx_BUSTYPE_PCI 0 | |
335 | /* Bus type Silicone Backplane Bus. */ | |
336 | #define BCM43xx_BUSTYPE_SB 1 | |
337 | /* Bus type PCMCIA. */ | |
338 | #define BCM43xx_BUSTYPE_PCMCIA 2 | |
339 | ||
340 | /* Threshold values. */ | |
341 | #define BCM43xx_MIN_RTS_THRESHOLD 1U | |
342 | #define BCM43xx_MAX_RTS_THRESHOLD 2304U | |
343 | #define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD | |
344 | ||
345 | #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 | |
346 | #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 | |
347 | ||
348 | /* Max size of a security key */ | |
349 | #define BCM43xx_SEC_KEYSIZE 16 | |
350 | /* Security algorithms. */ | |
351 | enum { | |
352 | BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ | |
353 | BCM43xx_SEC_ALGO_WEP, | |
354 | BCM43xx_SEC_ALGO_UNKNOWN, | |
355 | BCM43xx_SEC_ALGO_AES, | |
356 | BCM43xx_SEC_ALGO_WEP104, | |
357 | BCM43xx_SEC_ALGO_TKIP, | |
358 | }; | |
359 | ||
360 | #ifdef assert | |
361 | # undef assert | |
362 | #endif | |
363 | #ifdef CONFIG_BCM43XX_DEBUG | |
364 | #define assert(expr) \ | |
365 | do { \ | |
366 | if (unlikely(!(expr))) { \ | |
367 | printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \ | |
368 | #expr, __FILE__, __LINE__, __FUNCTION__); \ | |
369 | } \ | |
370 | } while (0) | |
371 | #else | |
372 | #define assert(expr) do { /* nothing */ } while (0) | |
373 | #endif | |
374 | ||
375 | /* rate limited printk(). */ | |
376 | #ifdef printkl | |
377 | # undef printkl | |
378 | #endif | |
379 | #define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0) | |
380 | /* rate limited printk() for debugging */ | |
381 | #ifdef dprintkl | |
382 | # undef dprintkl | |
383 | #endif | |
384 | #ifdef CONFIG_BCM43XX_DEBUG | |
385 | # define dprintkl printkl | |
386 | #else | |
387 | # define dprintkl(f, x...) do { /* nothing */ } while (0) | |
388 | #endif | |
389 | ||
390 | /* Helper macro for if branches. | |
391 | * An if branch marked with this macro is only taken in DEBUG mode. | |
392 | * Example: | |
393 | * if (DEBUG_ONLY(foo == bar)) { | |
394 | * do something | |
395 | * } | |
396 | * In DEBUG mode, the branch will be taken if (foo == bar). | |
397 | * In non-DEBUG mode, the branch will never be taken. | |
398 | */ | |
399 | #ifdef DEBUG_ONLY | |
400 | # undef DEBUG_ONLY | |
401 | #endif | |
402 | #ifdef CONFIG_BCM43XX_DEBUG | |
403 | # define DEBUG_ONLY(x) (x) | |
404 | #else | |
405 | # define DEBUG_ONLY(x) 0 | |
406 | #endif | |
407 | ||
408 | /* debugging printk() */ | |
409 | #ifdef dprintk | |
410 | # undef dprintk | |
411 | #endif | |
412 | #ifdef CONFIG_BCM43XX_DEBUG | |
413 | # define dprintk(f, x...) do { printk(f ,##x); } while (0) | |
414 | #else | |
415 | # define dprintk(f, x...) do { /* nothing */ } while (0) | |
416 | #endif | |
417 | ||
418 | ||
419 | struct net_device; | |
420 | struct pci_dev; | |
f222313a JL |
421 | struct bcm43xx_dmaring; |
422 | struct bcm43xx_pioqueue; | |
423 | ||
424 | struct bcm43xx_initval { | |
425 | u16 offset; | |
426 | u16 size; | |
427 | u32 value; | |
428 | } __attribute__((__packed__)); | |
429 | ||
430 | /* Values for bcm430x_sprominfo.locale */ | |
431 | enum { | |
432 | BCM43xx_LOCALE_WORLD = 0, | |
433 | BCM43xx_LOCALE_THAILAND, | |
434 | BCM43xx_LOCALE_ISRAEL, | |
435 | BCM43xx_LOCALE_JORDAN, | |
436 | BCM43xx_LOCALE_CHINA, | |
437 | BCM43xx_LOCALE_JAPAN, | |
438 | BCM43xx_LOCALE_USA_CANADA_ANZ, | |
439 | BCM43xx_LOCALE_EUROPE, | |
440 | BCM43xx_LOCALE_USA_LOW, | |
441 | BCM43xx_LOCALE_JAPAN_HIGH, | |
442 | BCM43xx_LOCALE_ALL, | |
443 | BCM43xx_LOCALE_NONE, | |
444 | }; | |
445 | ||
446 | #define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */ | |
447 | struct bcm43xx_sprominfo { | |
448 | u16 boardflags2; | |
449 | u8 il0macaddr[6]; | |
450 | u8 et0macaddr[6]; | |
451 | u8 et1macaddr[6]; | |
452 | u8 et0phyaddr:5; | |
453 | u8 et1phyaddr:5; | |
454 | u8 et0mdcport:1; | |
455 | u8 et1mdcport:1; | |
456 | u8 boardrev; | |
457 | u8 locale:4; | |
458 | u8 antennas_aphy:2; | |
459 | u8 antennas_bgphy:2; | |
460 | u16 pa0b0; | |
461 | u16 pa0b1; | |
462 | u16 pa0b2; | |
463 | u8 wl0gpio0; | |
464 | u8 wl0gpio1; | |
465 | u8 wl0gpio2; | |
466 | u8 wl0gpio3; | |
467 | u8 maxpower_aphy; | |
468 | u8 maxpower_bgphy; | |
469 | u16 pa1b0; | |
470 | u16 pa1b1; | |
471 | u16 pa1b2; | |
472 | u8 idle_tssi_tgt_aphy; | |
473 | u8 idle_tssi_tgt_bgphy; | |
474 | u16 boardflags; | |
475 | u16 antennagain_aphy; | |
476 | u16 antennagain_bgphy; | |
477 | }; | |
478 | ||
479 | /* Value pair to measure the LocalOscillator. */ | |
480 | struct bcm43xx_lopair { | |
481 | s8 low; | |
482 | s8 high; | |
483 | u8 used:1; | |
484 | }; | |
485 | #define BCM43xx_LO_COUNT (14*4) | |
486 | ||
487 | struct bcm43xx_phyinfo { | |
488 | /* Hardware Data */ | |
489 | u8 version; | |
490 | u8 type; | |
491 | u8 rev; | |
492 | u16 antenna_diversity; | |
493 | u16 savedpctlreg; | |
494 | u16 minlowsig[2]; | |
495 | u16 minlowsigpos[2]; | |
496 | u8 connected:1, | |
497 | calibrated:1, | |
498 | is_locked:1, /* used in bcm43xx_phy_{un}lock() */ | |
499 | dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */ | |
500 | /* LO Measurement Data. | |
501 | * Use bcm43xx_get_lopair() to get a value. | |
502 | */ | |
503 | struct bcm43xx_lopair *_lo_pairs; | |
504 | ||
505 | /* TSSI to dBm table in use */ | |
506 | const s8 *tssi2dbm; | |
507 | /* idle TSSI value */ | |
508 | s8 idle_tssi; | |
509 | /* PHY lock for core.rev < 3 | |
510 | * This lock is only used by bcm43xx_phy_{un}lock() | |
511 | */ | |
512 | spinlock_t lock; | |
513 | }; | |
514 | ||
515 | ||
516 | struct bcm43xx_radioinfo { | |
517 | u16 manufact; | |
518 | u16 version; | |
519 | u8 revision; | |
520 | ||
521 | /* 0: baseband attenuation, | |
522 | * 1: radio attenuation, | |
523 | * 2: tx_CTL1 | |
524 | * 3: tx_CTL2 | |
525 | */ | |
526 | u16 txpower[4]; | |
393344f6 MB |
527 | /* Desired TX power in dBm Q5.2 */ |
528 | u16 txpower_desired; | |
f222313a JL |
529 | /* Current Interference Mitigation mode */ |
530 | int interfmode; | |
531 | /* Stack of saved values from the Interference Mitigation code */ | |
532 | u16 interfstack[20]; | |
533 | /* Saved values from the NRSSI Slope calculation */ | |
534 | s16 nrssi[2]; | |
535 | s32 nrssislope; | |
536 | /* In memory nrssi lookup table. */ | |
537 | s8 nrssi_lt[64]; | |
538 | ||
539 | /* current channel */ | |
540 | u8 channel; | |
541 | u8 initial_channel; | |
542 | ||
543 | u16 lofcal; | |
544 | ||
545 | u16 initval; | |
546 | ||
547 | u8 enabled:1; | |
548 | /* ACI (adjacent channel interference) flags. */ | |
549 | u8 aci_enable:1, | |
550 | aci_wlan_automatic:1, | |
551 | aci_hw_rssi:1; | |
552 | }; | |
553 | ||
554 | /* Data structures for DMA transmission, per 80211 core. */ | |
555 | struct bcm43xx_dma { | |
556 | struct bcm43xx_dmaring *tx_ring0; | |
557 | struct bcm43xx_dmaring *tx_ring1; | |
558 | struct bcm43xx_dmaring *tx_ring2; | |
559 | struct bcm43xx_dmaring *tx_ring3; | |
560 | struct bcm43xx_dmaring *rx_ring0; | |
561 | struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */ | |
562 | }; | |
563 | ||
564 | /* Data structures for PIO transmission, per 80211 core. */ | |
565 | struct bcm43xx_pio { | |
566 | struct bcm43xx_pioqueue *queue0; | |
567 | struct bcm43xx_pioqueue *queue1; | |
568 | struct bcm43xx_pioqueue *queue2; | |
569 | struct bcm43xx_pioqueue *queue3; | |
570 | }; | |
571 | ||
572 | #define BCM43xx_MAX_80211_CORES 2 | |
573 | ||
574 | #define BCM43xx_COREFLAG_AVAILABLE (1 << 0) | |
575 | #define BCM43xx_COREFLAG_ENABLED (1 << 1) | |
576 | #define BCM43xx_COREFLAG_INITIALIZED (1 << 2) | |
577 | ||
578 | #ifdef CONFIG_BCM947XX | |
579 | #define core_offset(bcm) (bcm)->current_core_offset | |
580 | #else | |
581 | #define core_offset(bcm) 0 | |
582 | #endif | |
583 | ||
584 | struct bcm43xx_coreinfo { | |
585 | /** Driver internal flags. See BCM43xx_COREFLAG_* */ | |
586 | u32 flags; | |
587 | /** core_id ID number */ | |
588 | u16 id; | |
589 | /** core_rev revision number */ | |
590 | u8 rev; | |
591 | /** Index number for _switch_core() */ | |
592 | u8 index; | |
593 | /* Pointer to the PHYinfo, which belongs to this core (if 80211 core) */ | |
594 | struct bcm43xx_phyinfo *phy; | |
595 | /* Pointer to the RadioInfo, which belongs to this core (if 80211 core) */ | |
596 | struct bcm43xx_radioinfo *radio; | |
597 | /* Pointer to the DMA rings, which belong to this core (if 80211 core) */ | |
598 | struct bcm43xx_dma *dma; | |
599 | /* Pointer to the PIO queues, which belong to this core (if 80211 core) */ | |
600 | struct bcm43xx_pio *pio; | |
601 | }; | |
602 | ||
603 | /* Context information for a noise calculation (Link Quality). */ | |
604 | struct bcm43xx_noise_calculation { | |
605 | struct bcm43xx_coreinfo *core_at_start; | |
606 | u8 channel_at_start; | |
607 | u8 calculation_running:1; | |
608 | u8 nr_samples; | |
609 | s8 samples[8][4]; | |
610 | }; | |
611 | ||
612 | struct bcm43xx_stats { | |
613 | u8 link_quality; | |
614 | /* Store the last TX/RX times here for updating the leds. */ | |
615 | unsigned long last_tx; | |
616 | unsigned long last_rx; | |
617 | }; | |
618 | ||
619 | struct bcm43xx_key { | |
620 | u8 enabled:1; | |
621 | u8 algorithm; | |
622 | }; | |
623 | ||
624 | struct bcm43xx_private { | |
625 | struct ieee80211_device *ieee; | |
626 | struct ieee80211softmac_device *softmac; | |
627 | ||
628 | struct net_device *net_dev; | |
629 | struct pci_dev *pci_dev; | |
630 | unsigned int irq; | |
631 | ||
632 | void __iomem *mmio_addr; | |
633 | unsigned int mmio_len; | |
634 | ||
635 | spinlock_t lock; | |
636 | ||
637 | /* Driver status flags. */ | |
638 | u32 initialized:1, /* init_board() succeed */ | |
639 | was_initialized:1, /* for PCI suspend/resume. */ | |
640 | shutting_down:1, /* free_board() in progress */ | |
77db31ea | 641 | __using_pio:1, /* Internal, use bcm43xx_using_pio(). */ |
f222313a JL |
642 | bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */ |
643 | reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */ | |
644 | powersaving:1, /* TRUE if we are in PowerSaving mode. FALSE otherwise. */ | |
645 | short_preamble:1, /* TRUE, if short preamble is enabled. */ | |
646 | firmware_norelease:1; /* Do not release the firmware. Used on suspend. */ | |
647 | ||
648 | struct bcm43xx_stats stats; | |
649 | ||
650 | /* Bus type we are connected to. | |
651 | * This is currently always BCM43xx_BUSTYPE_PCI | |
652 | */ | |
653 | u8 bustype; | |
654 | ||
655 | u16 board_vendor; | |
656 | u16 board_type; | |
657 | u16 board_revision; | |
658 | ||
659 | u16 chip_id; | |
660 | u8 chip_rev; | |
661 | ||
662 | struct bcm43xx_sprominfo sprom; | |
663 | #define BCM43xx_NR_LEDS 4 | |
664 | struct bcm43xx_led leds[BCM43xx_NR_LEDS]; | |
665 | ||
666 | /* The currently active core. NULL if not initialized, yet. */ | |
667 | struct bcm43xx_coreinfo *current_core; | |
668 | #ifdef CONFIG_BCM947XX | |
669 | /** current core memory offset */ | |
670 | u32 current_core_offset; | |
671 | #endif | |
672 | struct bcm43xx_coreinfo *active_80211_core; | |
673 | /* coreinfo structs for all possible cores follow. | |
674 | * Note that a core might not exist. | |
675 | * So check the coreinfo flags before using it. | |
676 | */ | |
677 | struct bcm43xx_coreinfo core_chipcommon; | |
678 | struct bcm43xx_coreinfo core_pci; | |
679 | struct bcm43xx_coreinfo core_v90; | |
680 | struct bcm43xx_coreinfo core_pcmcia; | |
681 | struct bcm43xx_coreinfo core_ethernet; | |
682 | struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ]; | |
683 | /* Info about the PHY for each 80211 core. */ | |
684 | struct bcm43xx_phyinfo phy[ BCM43xx_MAX_80211_CORES ]; | |
685 | /* Info about the Radio for each 80211 core. */ | |
686 | struct bcm43xx_radioinfo radio[ BCM43xx_MAX_80211_CORES ]; | |
687 | /* DMA */ | |
688 | struct bcm43xx_dma dma[ BCM43xx_MAX_80211_CORES ]; | |
689 | /* PIO */ | |
690 | struct bcm43xx_pio pio[ BCM43xx_MAX_80211_CORES ]; | |
691 | ||
692 | u32 chipcommon_capabilities; | |
693 | ||
694 | /* Reason code of the last interrupt. */ | |
695 | u32 irq_reason; | |
696 | u32 dma_reason[4]; | |
697 | /* saved irq enable/disable state bitfield. */ | |
698 | u32 irq_savedstate; | |
699 | /* Link Quality calculation context. */ | |
700 | struct bcm43xx_noise_calculation noisecalc; | |
701 | ||
702 | /* Threshold values. */ | |
703 | //TODO: The RTS thr has to be _used_. Currently, it is only set via WX. | |
704 | u32 rts_threshold; | |
705 | ||
706 | /* Interrupt Service Routine tasklet (bottom-half) */ | |
707 | struct tasklet_struct isr_tasklet; | |
f222313a JL |
708 | |
709 | /* Periodic tasks */ | |
ab4977f8 MB |
710 | struct timer_list periodic_tasks; |
711 | unsigned int periodic_state; | |
f222313a JL |
712 | |
713 | struct work_struct restart_work; | |
714 | ||
715 | /* Informational stuff. */ | |
716 | char nick[IW_ESSID_MAX_SIZE + 1]; | |
717 | ||
718 | /* encryption/decryption */ | |
719 | u16 security_offset; | |
720 | struct bcm43xx_key key[54]; | |
721 | u8 default_key_idx; | |
722 | ||
723 | /* Firmware. */ | |
724 | const struct firmware *ucode; | |
725 | const struct firmware *pcm; | |
726 | const struct firmware *initvals0; | |
727 | const struct firmware *initvals1; | |
728 | ||
729 | /* Debugging stuff follows. */ | |
730 | #ifdef CONFIG_BCM43XX_DEBUG | |
731 | struct bcm43xx_dfsentry *dfsentry; | |
732 | atomic_t mmio_print_cnt; | |
733 | atomic_t pcicfg_print_cnt; | |
734 | #endif | |
735 | }; | |
736 | ||
737 | static inline | |
738 | struct bcm43xx_private * bcm43xx_priv(struct net_device *dev) | |
739 | { | |
740 | return ieee80211softmac_priv(dev); | |
741 | } | |
742 | ||
77db31ea MB |
743 | |
744 | /* Helper function, which returns a boolean. | |
745 | * TRUE, if PIO is used; FALSE, if DMA is used. | |
746 | */ | |
747 | #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO) | |
748 | static inline | |
749 | int bcm43xx_using_pio(struct bcm43xx_private *bcm) | |
750 | { | |
751 | return bcm->__using_pio; | |
752 | } | |
753 | #elif defined(CONFIG_BCM43XX_DMA) | |
754 | static inline | |
755 | int bcm43xx_using_pio(struct bcm43xx_private *bcm) | |
756 | { | |
757 | return 0; | |
758 | } | |
759 | #elif defined(CONFIG_BCM43XX_PIO) | |
760 | static inline | |
761 | int bcm43xx_using_pio(struct bcm43xx_private *bcm) | |
762 | { | |
763 | return 1; | |
764 | } | |
765 | #else | |
766 | # error "Using neither DMA nor PIO? Confused..." | |
767 | #endif | |
768 | ||
769 | ||
f222313a JL |
770 | static inline |
771 | int bcm43xx_num_80211_cores(struct bcm43xx_private *bcm) | |
772 | { | |
773 | int i, cnt = 0; | |
774 | ||
775 | for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) { | |
776 | if (bcm->core_80211[i].flags & BCM43xx_COREFLAG_AVAILABLE) | |
777 | cnt++; | |
778 | } | |
779 | ||
780 | return cnt; | |
781 | } | |
782 | ||
783 | /* Are we running in init_board() context? */ | |
784 | static inline | |
785 | int bcm43xx_is_initializing(struct bcm43xx_private *bcm) | |
786 | { | |
787 | if (bcm->initialized) | |
788 | return 0; | |
789 | if (bcm->shutting_down) | |
790 | return 0; | |
791 | return 1; | |
792 | } | |
793 | ||
794 | static inline | |
795 | struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy, | |
796 | u16 radio_attenuation, | |
797 | u16 baseband_attenuation) | |
798 | { | |
799 | return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2)); | |
800 | } | |
801 | ||
802 | ||
803 | /* MMIO read/write functions. Debug and non-debug variants. */ | |
804 | #ifdef CONFIG_BCM43XX_DEBUG | |
805 | ||
806 | static inline | |
807 | u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset) | |
808 | { | |
809 | u16 value; | |
810 | ||
811 | value = ioread16(bcm->mmio_addr + core_offset(bcm) + offset); | |
812 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
813 | printk(KERN_INFO PFX "ioread16 offset: 0x%04x, value: 0x%04x\n", | |
814 | offset, value); | |
815 | } | |
816 | ||
817 | return value; | |
818 | } | |
819 | ||
820 | static inline | |
821 | void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value) | |
822 | { | |
823 | iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset); | |
824 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
825 | printk(KERN_INFO PFX "iowrite16 offset: 0x%04x, value: 0x%04x\n", | |
826 | offset, value); | |
827 | } | |
828 | } | |
829 | ||
830 | static inline | |
831 | u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset) | |
832 | { | |
833 | u32 value; | |
834 | ||
835 | value = ioread32(bcm->mmio_addr + core_offset(bcm) + offset); | |
836 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
837 | printk(KERN_INFO PFX "ioread32 offset: 0x%04x, value: 0x%08x\n", | |
838 | offset, value); | |
839 | } | |
840 | ||
841 | return value; | |
842 | } | |
843 | ||
844 | static inline | |
845 | void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value) | |
846 | { | |
847 | iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset); | |
848 | if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) { | |
849 | printk(KERN_INFO PFX "iowrite32 offset: 0x%04x, value: 0x%08x\n", | |
850 | offset, value); | |
851 | } | |
852 | } | |
853 | ||
854 | static inline | |
855 | int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value) | |
856 | { | |
857 | int err; | |
858 | ||
859 | err = pci_read_config_word(bcm->pci_dev, offset, value); | |
860 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
861 | printk(KERN_INFO PFX "pciread16 offset: 0x%08x, value: 0x%04x, err: %d\n", | |
862 | offset, *value, err); | |
863 | } | |
864 | ||
865 | return err; | |
866 | } | |
867 | ||
868 | static inline | |
869 | int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value) | |
870 | { | |
871 | int err; | |
872 | ||
873 | err = pci_read_config_dword(bcm->pci_dev, offset, value); | |
874 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
875 | printk(KERN_INFO PFX "pciread32 offset: 0x%08x, value: 0x%08x, err: %d\n", | |
876 | offset, *value, err); | |
877 | } | |
878 | ||
879 | return err; | |
880 | } | |
881 | ||
882 | static inline | |
883 | int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value) | |
884 | { | |
885 | int err; | |
886 | ||
887 | err = pci_write_config_word(bcm->pci_dev, offset, value); | |
888 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
889 | printk(KERN_INFO PFX "pciwrite16 offset: 0x%08x, value: 0x%04x, err: %d\n", | |
890 | offset, value, err); | |
891 | } | |
892 | ||
893 | return err; | |
894 | } | |
895 | ||
896 | static inline | |
897 | int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value) | |
898 | { | |
899 | int err; | |
900 | ||
901 | err = pci_write_config_dword(bcm->pci_dev, offset, value); | |
902 | if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) { | |
903 | printk(KERN_INFO PFX "pciwrite32 offset: 0x%08x, value: 0x%08x, err: %d\n", | |
904 | offset, value, err); | |
905 | } | |
906 | ||
907 | return err; | |
908 | } | |
909 | ||
910 | #define bcm43xx_mmioprint_initial(bcm, value) atomic_set(&(bcm)->mmio_print_cnt, (value)) | |
911 | #define bcm43xx_mmioprint_enable(bcm) atomic_inc(&(bcm)->mmio_print_cnt) | |
912 | #define bcm43xx_mmioprint_disable(bcm) atomic_dec(&(bcm)->mmio_print_cnt) | |
913 | #define bcm43xx_pciprint_initial(bcm, value) atomic_set(&(bcm)->pcicfg_print_cnt, (value)) | |
914 | #define bcm43xx_pciprint_enable(bcm) atomic_inc(&(bcm)->pcicfg_print_cnt) | |
915 | #define bcm43xx_pciprint_disable(bcm) atomic_dec(&(bcm)->pcicfg_print_cnt) | |
916 | ||
917 | #else /* CONFIG_BCM43XX_DEBUG*/ | |
918 | ||
919 | #define bcm43xx_read16(bcm, offset) ioread16((bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
920 | #define bcm43xx_write16(bcm, offset, value) iowrite16((value), (bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
921 | #define bcm43xx_read32(bcm, offset) ioread32((bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
922 | #define bcm43xx_write32(bcm, offset, value) iowrite32((value), (bcm)->mmio_addr + core_offset(bcm) + (offset)) | |
923 | #define bcm43xx_pci_read_config16(bcm, o, v) pci_read_config_word((bcm)->pci_dev, (o), (v)) | |
924 | #define bcm43xx_pci_read_config32(bcm, o, v) pci_read_config_dword((bcm)->pci_dev, (o), (v)) | |
925 | #define bcm43xx_pci_write_config16(bcm, o, v) pci_write_config_word((bcm)->pci_dev, (o), (v)) | |
926 | #define bcm43xx_pci_write_config32(bcm, o, v) pci_write_config_dword((bcm)->pci_dev, (o), (v)) | |
927 | ||
928 | #define bcm43xx_mmioprint_initial(x, y) do { /* nothing */ } while (0) | |
929 | #define bcm43xx_mmioprint_enable(x) do { /* nothing */ } while (0) | |
930 | #define bcm43xx_mmioprint_disable(x) do { /* nothing */ } while (0) | |
931 | #define bcm43xx_pciprint_initial(bcm, value) do { /* nothing */ } while (0) | |
932 | #define bcm43xx_pciprint_enable(bcm) do { /* nothing */ } while (0) | |
933 | #define bcm43xx_pciprint_disable(bcm) do { /* nothing */ } while (0) | |
934 | ||
935 | #endif /* CONFIG_BCM43XX_DEBUG*/ | |
936 | ||
937 | ||
938 | /** Limit a value between two limits */ | |
939 | #ifdef limit_value | |
940 | # undef limit_value | |
941 | #endif | |
942 | #define limit_value(value, min, max) \ | |
943 | ({ \ | |
944 | typeof(value) __value = (value); \ | |
945 | typeof(value) __min = (min); \ | |
946 | typeof(value) __max = (max); \ | |
947 | if (__value < __min) \ | |
948 | __value = __min; \ | |
949 | else if (__value > __max) \ | |
950 | __value = __max; \ | |
951 | __value; \ | |
952 | }) | |
953 | ||
f222313a | 954 | #endif /* BCM43xx_H_ */ |