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Merge tag 'char-misc-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregk...
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / chip.c
CommitLineData
a83369b6 1/*
cb7cf7be 2 * Copyright (c) 2014 Broadcom Corporation
a83369b6
FL		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
cb7cf7be
AS		 16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/list.h>
61213be4 19#include <linux/ssb/ssb_regs.h>
99ba15cd 20#include <linux/bcma/bcma.h>
cb7cf7be 21#include <linux/bcma/bcma_regs.h>
61213be4 22
cb7cf7be
AS		 23#include <defs.h>
24#include <soc.h>
a83369b6 25#include <brcm_hw_ids.h>
a83369b6 26#include <brcmu_utils.h>
cb7cf7be 27#include <chipcommon.h>
a8e8ed34 28#include "debug.h"
20c9c9bc 29#include "chip.h"
a83369b6 30
cb7cf7be
AS		 31/* SOC Interconnect types (aka chip types) */
32#define SOCI_SB 0
33#define SOCI_AI 1
34
4aa2c47c
AS		 35/* PL-368 DMP definitions */
36#define DMP_DESC_TYPE_MSK 0x0000000F
37#define DMP_DESC_EMPTY 0x00000000
38#define DMP_DESC_VALID 0x00000001
39#define DMP_DESC_COMPONENT 0x00000001
40#define DMP_DESC_MASTER_PORT 0x00000003
41#define DMP_DESC_ADDRESS 0x00000005
42#define DMP_DESC_ADDRSIZE_GT32 0x00000008
43#define DMP_DESC_EOT 0x0000000F
44
45#define DMP_COMP_DESIGNER 0xFFF00000
46#define DMP_COMP_DESIGNER_S 20
47#define DMP_COMP_PARTNUM 0x000FFF00
48#define DMP_COMP_PARTNUM_S 8
49#define DMP_COMP_CLASS 0x000000F0
50#define DMP_COMP_CLASS_S 4
51#define DMP_COMP_REVISION 0xFF000000
52#define DMP_COMP_REVISION_S 24
53#define DMP_COMP_NUM_SWRAP 0x00F80000
54#define DMP_COMP_NUM_SWRAP_S 19
55#define DMP_COMP_NUM_MWRAP 0x0007C000
56#define DMP_COMP_NUM_MWRAP_S 14
57#define DMP_COMP_NUM_SPORT 0x00003E00
58#define DMP_COMP_NUM_SPORT_S 9
59#define DMP_COMP_NUM_MPORT 0x000001F0
60#define DMP_COMP_NUM_MPORT_S 4
61
62#define DMP_MASTER_PORT_UID 0x0000FF00
63#define DMP_MASTER_PORT_UID_S 8
64#define DMP_MASTER_PORT_NUM 0x000000F0
65#define DMP_MASTER_PORT_NUM_S 4
66
67#define DMP_SLAVE_ADDR_BASE 0xFFFFF000
68#define DMP_SLAVE_ADDR_BASE_S 12
69#define DMP_SLAVE_PORT_NUM 0x00000F00
70#define DMP_SLAVE_PORT_NUM_S 8
71#define DMP_SLAVE_TYPE 0x000000C0
72#define DMP_SLAVE_TYPE_S 6
73#define DMP_SLAVE_TYPE_SLAVE 0
74#define DMP_SLAVE_TYPE_BRIDGE 1
75#define DMP_SLAVE_TYPE_SWRAP 2
76#define DMP_SLAVE_TYPE_MWRAP 3
77#define DMP_SLAVE_SIZE_TYPE 0x00000030
78#define DMP_SLAVE_SIZE_TYPE_S 4
79#define DMP_SLAVE_SIZE_4K 0
80#define DMP_SLAVE_SIZE_8K 1
81#define DMP_SLAVE_SIZE_16K 2
82#define DMP_SLAVE_SIZE_DESC 3
83
cb7cf7be
AS		 84/* EROM CompIdentB */
85#define CIB_REV_MASK 0xff000000
86#define CIB_REV_SHIFT 24
87
88/* ARM CR4 core specific control flag bits */
89#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
90
91/* D11 core specific control flag bits */
92#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
93#define D11_BCMA_IOCTL_PHYRESET 0x0008
94
a83369b6
FL		 95/* chip core base & ramsize */
96/* bcm4329 */
97/* SDIO device core, ID 0x829 */
98#define BCM4329_CORE_BUS_BASE 0x18011000
99/* internal memory core, ID 0x80e */
100#define BCM4329_CORE_SOCRAM_BASE 0x18003000
101/* ARM Cortex M3 core, ID 0x82a */
102#define BCM4329_CORE_ARM_BASE 0x18002000
103#define BCM4329_RAMSIZE 0x48000
369508c5 104/* bcm43143 */
369508c5
HM		 105#define BCM43143_RAMSIZE 0x70000
106
cb7cf7be
AS		 107#define CORE_SB(base, field) \
108 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
a83369b6 109#define SBCOREREV(sbidh) \
61213be4
FL		 110 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
111 ((sbidh) & SSB_IDHIGH_RCLO))
a83369b6 112
cb7cf7be
AS		 113struct sbconfig {
114 u32 PAD[2];
115 u32 sbipsflag; /* initiator port ocp slave flag */
116 u32 PAD[3];
117 u32 sbtpsflag; /* target port ocp slave flag */
118 u32 PAD[11];
119 u32 sbtmerrloga; /* (sonics >= 2.3) */
120 u32 PAD;
121 u32 sbtmerrlog; /* (sonics >= 2.3) */
122 u32 PAD[3];
123 u32 sbadmatch3; /* address match3 */
124 u32 PAD;
125 u32 sbadmatch2; /* address match2 */
126 u32 PAD;
127 u32 sbadmatch1; /* address match1 */
128 u32 PAD[7];
129 u32 sbimstate; /* initiator agent state */
130 u32 sbintvec; /* interrupt mask */
131 u32 sbtmstatelow; /* target state */
132 u32 sbtmstatehigh; /* target state */
133 u32 sbbwa0; /* bandwidth allocation table0 */
134 u32 PAD;
135 u32 sbimconfiglow; /* initiator configuration */
136 u32 sbimconfighigh; /* initiator configuration */
137 u32 sbadmatch0; /* address match0 */
138 u32 PAD;
139 u32 sbtmconfiglow; /* target configuration */
140 u32 sbtmconfighigh; /* target configuration */
141 u32 sbbconfig; /* broadcast configuration */
142 u32 PAD;
143 u32 sbbstate; /* broadcast state */
144 u32 PAD[3];
145 u32 sbactcnfg; /* activate configuration */
146 u32 PAD[3];
147 u32 sbflagst; /* current sbflags */
148 u32 PAD[3];
149 u32 sbidlow; /* identification */
150 u32 sbidhigh; /* identification */
151};
152
153struct brcmf_core_priv {
154 struct brcmf_core pub;
155 u32 wrapbase;
156 struct list_head list;
157 struct brcmf_chip_priv *chip;
158};
523894f2 159
cb7cf7be
AS		 160struct brcmf_chip_priv {
161 struct brcmf_chip pub;
162 const struct brcmf_buscore_ops *ops;
163 void *ctx;
164 /* assured first core is chipcommon, second core is buscore */
165 struct list_head cores;
166 u16 num_cores;
167
168 bool (*iscoreup)(struct brcmf_core_priv *core);
169 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
170 u32 reset);
171 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
172 u32 postreset);
173};
174
175static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
176 struct brcmf_core *core)
454d2a88
FL		 177{
178 u32 regdata;
523894f2 179
cb7cf7be
AS		 180 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
181 core->rev = SBCOREREV(regdata);
454d2a88
FL		 182}
183
cb7cf7be 184static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
d8f64a42 185{
cb7cf7be 186 struct brcmf_chip_priv *ci;
d8f64a42 187 u32 regdata;
cb7cf7be 188 u32 address;
d8f64a42 189
cb7cf7be
AS		 190 ci = core->chip;
191 address = CORE_SB(core->pub.base, sbtmstatelow);
192 regdata = ci->ops->read32(ci->ctx, address);
61213be4
FL		 193 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
194 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
20c9c9bc 195 return SSB_TMSLOW_CLOCK == regdata;
d8f64a42
FL		 196}
197
cb7cf7be 198static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
6ca687d9 199{
cb7cf7be 200 struct brcmf_chip_priv *ci;
6ca687d9 201 u32 regdata;
6ca687d9
FL		 202 bool ret;
203
cb7cf7be
AS		 204 ci = core->chip;
205 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
6ca687d9
FL		 206 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
207
cb7cf7be 208 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
6ca687d9
FL		 209 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
210
211 return ret;
212}
213
cb7cf7be
AS		 214static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
215 u32 prereset, u32 reset)
2d4a9af1 216{
cb7cf7be
AS		 217 struct brcmf_chip_priv *ci;
218 u32 val, base;
086a2e0a 219
cb7cf7be
AS		 220 ci = core->chip;
221 base = core->pub.base;
222 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
223 if (val & SSB_TMSLOW_RESET)
2d4a9af1
FL		 224 return;
225
cb7cf7be
AS		 226 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
227 if ((val & SSB_TMSLOW_CLOCK) != 0) {
2d4a9af1
FL		 228 /*
229 * set target reject and spin until busy is clear
230 * (preserve core-specific bits)
231 */
cb7cf7be
AS		 232 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
233 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
234 val | SSB_TMSLOW_REJECT);
2d4a9af1 235
cb7cf7be 236 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2d4a9af1 237 udelay(1);
cb7cf7be
AS		 238 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
239 & SSB_TMSHIGH_BUSY), 100000);
240
241 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
242 if (val & SSB_TMSHIGH_BUSY)
5e8149f5 243 brcmf_err("core state still busy\n");
2d4a9af1 244
cb7cf7be
AS		 245 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
246 if (val & SSB_IDLOW_INITIATOR) {
247 val = ci->ops->read32(ci->ctx,
248 CORE_SB(base, sbimstate));
249 val |= SSB_IMSTATE_REJECT;
250 ci->ops->write32(ci->ctx,
251 CORE_SB(base, sbimstate), val);
252 val = ci->ops->read32(ci->ctx,
253 CORE_SB(base, sbimstate));
2d4a9af1 254 udelay(1);
cb7cf7be
AS		 255 SPINWAIT((ci->ops->read32(ci->ctx,
256 CORE_SB(base, sbimstate)) &
a39be27b 257 SSB_IMSTATE_BUSY), 100000);
2d4a9af1
FL		 258 }
259
260 /* set reset and reject while enabling the clocks */
cb7cf7be
AS		 261 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
262 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
263 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
264 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2d4a9af1
FL		 265 udelay(10);
266
267 /* clear the initiator reject bit */
cb7cf7be
AS		 268 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
269 if (val & SSB_IDLOW_INITIATOR) {
270 val = ci->ops->read32(ci->ctx,
271 CORE_SB(base, sbimstate));
272 val &= ~SSB_IMSTATE_REJECT;
273 ci->ops->write32(ci->ctx,
274 CORE_SB(base, sbimstate), val);
2d4a9af1
FL		 275 }
276 }
277
278 /* leave reset and reject asserted */
cb7cf7be
AS		 279 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
280 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
2d4a9af1
FL		 281 udelay(1);
282}
283
cb7cf7be
AS		 284static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
285 u32 prereset, u32 reset)
086a2e0a 286{
cb7cf7be 287 struct brcmf_chip_priv *ci;
086a2e0a 288 u32 regdata;
086a2e0a 289
cb7cf7be 290 ci = core->chip;
53036261 291
ffa216bb 292 /* if core is already in reset, skip reset */
cb7cf7be 293 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
086a2e0a 294 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
ffa216bb 295 goto in_reset_configure;
086a2e0a 296
53036261 297 /* configure reset */
cb7cf7be
AS		 298 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
299 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
300 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
086a2e0a 301
53036261 302 /* put in reset */
cb7cf7be
AS		 303 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
304 BCMA_RESET_CTL_RESET);
1640f28f
FL		 305 usleep_range(10, 20);
306
53036261 307 /* wait till reset is 1 */
cb7cf7be 308 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
53036261
HM		 309 BCMA_RESET_CTL_RESET, 300);
310
ffa216bb 311in_reset_configure:
cb7cf7be
AS		 312 /* in-reset configure */
313 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
314 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
315 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
086a2e0a
FL		 316}
317
cb7cf7be
AS		 318static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
319 u32 reset, u32 postreset)
2bc78e10 320{
cb7cf7be 321 struct brcmf_chip_priv *ci;
2bc78e10 322 u32 regdata;
cb7cf7be 323 u32 base;
2bc78e10 324
cb7cf7be
AS		 325 ci = core->chip;
326 base = core->pub.base;
2bc78e10
FL		 327 /*
328 * Must do the disable sequence first to work for
329 * arbitrary current core state.
330 */
cb7cf7be 331 brcmf_chip_sb_coredisable(core, 0, 0);
2bc78e10
FL		 332
333 /*
334 * Now do the initialization sequence.
335 * set reset while enabling the clock and
336 * forcing them on throughout the core
337 */
cb7cf7be
AS		 338 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
339 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
340 SSB_TMSLOW_RESET);
341 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2bc78e10
FL		 342 udelay(1);
343
d77e70ff 344 /* clear any serror */
cb7cf7be 345 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
61213be4 346 if (regdata & SSB_TMSHIGH_SERR)
cb7cf7be
AS		 347 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
348
349 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
350 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
351 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
352 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
353 }
2bc78e10
FL		 354
355 /* clear reset and allow it to propagate throughout the core */
cb7cf7be
AS		 356 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
357 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
358 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2bc78e10
FL		 359 udelay(1);
360
361 /* leave clock enabled */
cb7cf7be
AS		 362 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
363 SSB_TMSLOW_CLOCK);
364 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
d77e70ff
FL		 365 udelay(1);
366}
367
cb7cf7be
AS		 368static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
369 u32 reset, u32 postreset)
d77e70ff 370{
cb7cf7be
AS		 371 struct brcmf_chip_priv *ci;
372 int count;
d77e70ff 373
cb7cf7be 374 ci = core->chip;
53036261 375
d77e70ff 376 /* must disable first to work for arbitrary current core state */
cb7cf7be 377 brcmf_chip_ai_coredisable(core, prereset, reset);
d77e70ff 378
cb7cf7be
AS		 379 count = 0;
380 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
53036261 381 BCMA_RESET_CTL_RESET) {
cb7cf7be
AS		 382 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
383 count++;
384 if (count > 50)
385 break;
53036261
HM		 386 usleep_range(40, 60);
387 }
d77e70ff 388
cb7cf7be
AS		 389 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
390 postreset | BCMA_IOCTL_CLK);
391 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
392}
393
394static char *brcmf_chip_name(uint chipid, char *buf, uint len)
395{
396 const char *fmt;
397
398 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
399 snprintf(buf, len, fmt, chipid);
400 return buf;
401}
402
403static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
404 u16 coreid, u32 base,
405 u32 wrapbase)
406{
407 struct brcmf_core_priv *core;
408
409 core = kzalloc(sizeof(*core), GFP_KERNEL);
410 if (!core)
411 return ERR_PTR(-ENOMEM);
412
413 core->pub.id = coreid;
414 core->pub.base = base;
415 core->chip = ci;
416 core->wrapbase = wrapbase;
417
418 list_add_tail(&core->list, &ci->cores);
419 return &core->pub;
2bc78e10
FL		 420}
421
1640f28f
FL		 422#ifdef DEBUG
423/* safety check for chipinfo */
cb7cf7be 424static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
1640f28f 425{
cb7cf7be
AS		 426 struct brcmf_core_priv *core;
427 bool need_socram = false;
428 bool has_socram = false;
429 int idx = 1;
430
431 list_for_each_entry(core, &ci->cores, list) {
4aa2c47c
AS		 432 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
433 idx++, core->pub.id, core->pub.rev, core->pub.base,
434 core->wrapbase);
cb7cf7be
AS		 435
436 switch (core->pub.id) {
437 case BCMA_CORE_ARM_CM3:
438 need_socram = true;
439 break;
440 case BCMA_CORE_INTERNAL_MEM:
441 has_socram = true;
442 break;
443 case BCMA_CORE_ARM_CR4:
444 if (ci->pub.rambase == 0) {
445 brcmf_err("RAM base not provided with ARM CR4 core\n");
446 return -ENOMEM;
447 }
448 break;
449 default:
450 break;
1640f28f
FL		 451 }
452 }
453
cb7cf7be
AS		 454 /* check RAM core presence for ARM CM3 core */
455 if (need_socram && !has_socram) {
456 brcmf_err("RAM core not provided with ARM CM3 core\n");
457 return -ENODEV;
1640f28f 458 }
1640f28f
FL		 459 return 0;
460}
461#else /* DEBUG */
cb7cf7be 462static inline int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
1640f28f
FL		 463{
464 return 0;
465}
466#endif
467
cb7cf7be 468static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
a83369b6 469{
cb7cf7be 470 switch (ci->pub.chip) {
5779ae6a 471 case BRCM_CC_4329_CHIP_ID:
cb7cf7be
AS		 472 ci->pub.ramsize = BCM4329_RAMSIZE;
473 break;
5779ae6a 474 case BRCM_CC_43143_CHIP_ID:
cb7cf7be
AS		 475 ci->pub.ramsize = BCM43143_RAMSIZE;
476 break;
5779ae6a 477 case BRCM_CC_43241_CHIP_ID:
cb7cf7be
AS		 478 ci->pub.ramsize = 0x90000;
479 break;
5779ae6a 480 case BRCM_CC_4330_CHIP_ID:
cb7cf7be
AS		 481 ci->pub.ramsize = 0x48000;
482 break;
5779ae6a 483 case BRCM_CC_4334_CHIP_ID:
8b3a38da 484 case BRCM_CC_43340_CHIP_ID:
cb7cf7be
AS		 485 ci->pub.ramsize = 0x80000;
486 break;
5779ae6a 487 case BRCM_CC_4335_CHIP_ID:
cb7cf7be
AS		 488 ci->pub.ramsize = 0xc0000;
489 ci->pub.rambase = 0x180000;
490 break;
5779ae6a 491 case BRCM_CC_43362_CHIP_ID:
cb7cf7be
AS		 492 ci->pub.ramsize = 0x3c000;
493 break;
5779ae6a
HM		 494 case BRCM_CC_4339_CHIP_ID:
495 case BRCM_CC_4354_CHIP_ID:
9e37f045
HM		 496 case BRCM_CC_4356_CHIP_ID:
497 case BRCM_CC_43567_CHIP_ID:
498 case BRCM_CC_43569_CHIP_ID:
499 case BRCM_CC_43570_CHIP_ID:
cb7cf7be
AS		 500 ci->pub.ramsize = 0xc0000;
501 ci->pub.rambase = 0x180000;
502 break;
9e37f045
HM		 503 case BRCM_CC_43602_CHIP_ID:
504 ci->pub.ramsize = 0xf0000;
505 ci->pub.rambase = 0x180000;
506 break;
cb7cf7be
AS		 507 default:
508 brcmf_err("unknown chip: %s\n", ci->pub.name);
509 break;
510 }
511}
512
4aa2c47c
AS		 513static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
514 u8 *type)
515{
516 u32 val;
517
518 /* read next descriptor */
519 val = ci->ops->read32(ci->ctx, *eromaddr);
520 *eromaddr += 4;
521
522 if (!type)
523 return val;
524
525 /* determine descriptor type */
526 *type = (val & DMP_DESC_TYPE_MSK);
527 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
528 *type = DMP_DESC_ADDRESS;
529
530 return val;
531}
532
533static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
534 u32 *regbase, u32 *wrapbase)
535{
536 u8 desc;
537 u32 val;
538 u8 mpnum = 0;
539 u8 stype, sztype, wraptype;
540
541 *regbase = 0;
542 *wrapbase = 0;
543
544 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
545 if (desc == DMP_DESC_MASTER_PORT) {
546 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
547 wraptype = DMP_SLAVE_TYPE_MWRAP;
548 } else if (desc == DMP_DESC_ADDRESS) {
549 /* revert erom address */
550 *eromaddr -= 4;
551 wraptype = DMP_SLAVE_TYPE_SWRAP;
552 } else {
553 *eromaddr -= 4;
554 return -EILSEQ;
555 }
556
557 do {
558 /* locate address descriptor */
559 do {
560 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
561 /* unexpected table end */
562 if (desc == DMP_DESC_EOT) {
563 *eromaddr -= 4;
564 return -EFAULT;
565 }
566 } while (desc != DMP_DESC_ADDRESS);
567
568 /* skip upper 32-bit address descriptor */
569 if (val & DMP_DESC_ADDRSIZE_GT32)
570 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
571
572 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
573
574 /* next size descriptor can be skipped */
575 if (sztype == DMP_SLAVE_SIZE_DESC) {
576 val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
577 /* skip upper size descriptor if present */
578 if (val & DMP_DESC_ADDRSIZE_GT32)
579 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
580 }
581
582 /* only look for 4K register regions */
583 if (sztype != DMP_SLAVE_SIZE_4K)
584 continue;
585
586 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
587
588 /* only regular slave and wrapper */
589 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
590 *regbase = val & DMP_SLAVE_ADDR_BASE;
591 if (*wrapbase == 0 && stype == wraptype)
592 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
593 } while (*regbase == 0 || *wrapbase == 0);
594
595 return 0;
596}
597
598static
599int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
600{
601 struct brcmf_core *core;
602 u32 eromaddr;
603 u8 desc_type = 0;
604 u32 val;
605 u16 id;
606 u8 nmp, nsp, nmw, nsw, rev;
607 u32 base, wrap;
608 int err;
609
610 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
611
612 while (desc_type != DMP_DESC_EOT) {
613 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
614 if (!(val & DMP_DESC_VALID))
615 continue;
616
617 if (desc_type == DMP_DESC_EMPTY)
618 continue;
619
620 /* need a component descriptor */
621 if (desc_type != DMP_DESC_COMPONENT)
622 continue;
623
624 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
625
626 /* next descriptor must be component as well */
627 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
628 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
629 return -EFAULT;
630
631 /* only look at cores with master port(s) */
632 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
633 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
634 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
635 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
636 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
637
638 /* need core with ports */
639 if (nmw + nsw == 0)
640 continue;
641
642 /* try to obtain register address info */
643 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
644 if (err)
645 continue;
646
647 /* finally a core to be added */
648 core = brcmf_chip_add_core(ci, id, base, wrap);
649 if (IS_ERR(core))
650 return PTR_ERR(core);
651
652 core->rev = rev;
653 }
654
655 return 0;
656}
657
cb7cf7be
AS		 658static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
659{
660 struct brcmf_core *core;
a83369b6 661 u32 regdata;
c805eeb7 662 u32 socitype;
a83369b6 663
069eddd9 664 /* Get CC core rev
c805eeb7 665 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
a83369b6
FL		 666 * For different chiptypes or old sdio hosts w/o chipcommon,
667 * other ways of recognition should be added here.
668 */
cb7cf7be
AS		 669 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
670 ci->pub.chip = regdata & CID_ID_MASK;
671 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
c805eeb7 672 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
a83369b6 673
cb7cf7be
AS		 674 brcmf_chip_name(ci->pub.chip, ci->pub.name, sizeof(ci->pub.name));
675 brcmf_dbg(INFO, "found %s chip: BCM%s, rev=%d\n",
676 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name,
677 ci->pub.chiprev);
a83369b6 678
c805eeb7 679 if (socitype == SOCI_SB) {
5779ae6a 680 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
c805eeb7
AS		 681 brcmf_err("SB chip is not supported\n");
682 return -ENODEV;
683 }
cb7cf7be
AS		 684 ci->iscoreup = brcmf_chip_sb_iscoreup;
685 ci->coredisable = brcmf_chip_sb_coredisable;
686 ci->resetcore = brcmf_chip_sb_resetcore;
687
688 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
689 SI_ENUM_BASE, 0);
690 brcmf_chip_sb_corerev(ci, core);
691 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
692 BCM4329_CORE_BUS_BASE, 0);
693 brcmf_chip_sb_corerev(ci, core);
694 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
695 BCM4329_CORE_SOCRAM_BASE, 0);
696 brcmf_chip_sb_corerev(ci, core);
697 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
698 BCM4329_CORE_ARM_BASE, 0);
699 brcmf_chip_sb_corerev(ci, core);
4aa2c47c
AS		 700
701 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
702 brcmf_chip_sb_corerev(ci, core);
c805eeb7 703 } else if (socitype == SOCI_AI) {
cb7cf7be
AS		 704 ci->iscoreup = brcmf_chip_ai_iscoreup;
705 ci->coredisable = brcmf_chip_ai_coredisable;
706 ci->resetcore = brcmf_chip_ai_resetcore;
c805eeb7 707
4aa2c47c 708 brcmf_chip_dmp_erom_scan(ci);
c805eeb7
AS		 709 } else {
710 brcmf_err("chip backplane type %u is not supported\n",
711 socitype);
6ca687d9
FL		 712 return -ENODEV;
713 }
714
cb7cf7be
AS		 715 brcmf_chip_get_raminfo(ci);
716
717 return brcmf_chip_cores_check(ci);
a83369b6
FL		 718}
719
cb7cf7be 720static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
5b45e54e 721{
cb7cf7be
AS		 722 struct brcmf_core *core;
723 struct brcmf_core_priv *cr4;
724 u32 val;
79ae3957 725
cb7cf7be
AS		 726
727 core = brcmf_chip_get_core(&chip->pub, id);
728 if (!core)
729 return;
730
731 switch (id) {
732 case BCMA_CORE_ARM_CM3:
733 brcmf_chip_coredisable(core, 0, 0);
734 break;
735 case BCMA_CORE_ARM_CR4:
736 cr4 = container_of(core, struct brcmf_core_priv, pub);
737
738 /* clear all IOCTL bits except HALT bit */
739 val = chip->ops->read32(chip->ctx, cr4->wrapbase + BCMA_IOCTL);
740 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
741 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
742 ARMCR4_BCMA_IOCTL_CPUHALT);
743 break;
744 default:
745 brcmf_err("unknown id: %u\n", id);
746 break;
747 }
748}
749
750static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
751{
752 struct brcmf_chip *pub;
753 struct brcmf_core_priv *cc;
cb7cf7be
AS		 754 u32 base;
755 u32 val;
756 int ret = 0;
757
758 pub = &chip->pub;
759 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
760 base = cc->pub.base;
5b45e54e
FL		 761
762 /* get chipcommon capabilites */
cb7cf7be
AS		 763 pub->cc_caps = chip->ops->read32(chip->ctx,
764 CORE_CC_REG(base, capabilities));
5b45e54e
FL		 765
766 /* get pmu caps & rev */
cb7cf7be
AS		 767 if (pub->cc_caps & CC_CAP_PMU) {
768 val = chip->ops->read32(chip->ctx,
769 CORE_CC_REG(base, pmucapabilities));
770 pub->pmurev = val & PCAP_REV_MASK;
771 pub->pmucaps = val;
5b45e54e
FL		 772 }
773
4aa2c47c
AS		 774 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
775 cc->pub.rev, pub->pmurev, pub->pmucaps);
cb7cf7be
AS		 776
777 /* execute bus core specific setup */
778 if (chip->ops->setup)
779 ret = chip->ops->setup(chip->ctx, pub);
966414da
FL		 780
781 /*
782 * Make sure any on-chip ARM is off (in case strapping is wrong),
783 * or downloaded code was already running.
784 */
cb7cf7be
AS		 785 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
786 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
787 return ret;
5b45e54e
FL		 788}
789
cb7cf7be
AS		 790struct brcmf_chip *brcmf_chip_attach(void *ctx,
791 const struct brcmf_buscore_ops *ops)
a83369b6 792{
cb7cf7be
AS		 793 struct brcmf_chip_priv *chip;
794 int err = 0;
795
796 if (WARN_ON(!ops->read32))
797 err = -EINVAL;
798 if (WARN_ON(!ops->write32))
799 err = -EINVAL;
800 if (WARN_ON(!ops->prepare))
801 err = -EINVAL;
802 if (WARN_ON(!ops->exit_dl))
803 err = -EINVAL;
804 if (err < 0)
805 return ERR_PTR(-EINVAL);
806
807 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
808 if (!chip)
809 return ERR_PTR(-ENOMEM);
810
811 INIT_LIST_HEAD(&chip->cores);
812 chip->num_cores = 0;
813 chip->ops = ops;
814 chip->ctx = ctx;
815
816 err = ops->prepare(ctx);
817 if (err < 0)
818 goto fail;
819
820 err = brcmf_chip_recognition(chip);
821 if (err < 0)
822 goto fail;
823
824 err = brcmf_chip_setup(chip);
825 if (err < 0)
826 goto fail;
827
828 return &chip->pub;
829
830fail:
831 brcmf_chip_detach(&chip->pub);
832 return ERR_PTR(err);
833}
a97e4fc5 834
cb7cf7be
AS		 835void brcmf_chip_detach(struct brcmf_chip *pub)
836{
837 struct brcmf_chip_priv *chip;
838 struct brcmf_core_priv *core;
839 struct brcmf_core_priv *tmp;
840
841 chip = container_of(pub, struct brcmf_chip_priv, pub);
842 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
843 list_del(&core->list);
844 kfree(core);
845 }
846 kfree(chip);
847}
a97e4fc5 848
cb7cf7be
AS		 849struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
850{
851 struct brcmf_chip_priv *chip;
852 struct brcmf_core_priv *core;
a83369b6 853
cb7cf7be
AS		 854 chip = container_of(pub, struct brcmf_chip_priv, pub);
855 list_for_each_entry(core, &chip->cores, list)
856 if (core->pub.id == coreid)
857 return &core->pub;
e63ac6b8 858
cb7cf7be
AS		 859 return NULL;
860}
a83369b6 861
cb7cf7be
AS		 862struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
863{
864 struct brcmf_chip_priv *chip;
865 struct brcmf_core_priv *cc;
866
867 chip = container_of(pub, struct brcmf_chip_priv, pub);
868 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
869 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
870 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
871 return &cc->pub;
872}
5b45e54e 873
cb7cf7be
AS		 874bool brcmf_chip_iscoreup(struct brcmf_core *pub)
875{
876 struct brcmf_core_priv *core;
960908dc 877
cb7cf7be
AS		 878 core = container_of(pub, struct brcmf_core_priv, pub);
879 return core->chip->iscoreup(core);
880}
a97e4fc5 881
cb7cf7be
AS		 882void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
883{
884 struct brcmf_core_priv *core;
885
886 core = container_of(pub, struct brcmf_core_priv, pub);
887 core->chip->coredisable(core, prereset, reset);
a83369b6 888}
a8a6c045 889
cb7cf7be
AS		 890void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
891 u32 postreset)
a8a6c045 892{
cb7cf7be 893 struct brcmf_core_priv *core;
a8a6c045 894
cb7cf7be
AS		 895 core = container_of(pub, struct brcmf_core_priv, pub);
896 core->chip->resetcore(core, prereset, reset, postreset);
a8a6c045 897}
e12afb6c 898
069eddd9 899static void
cb7cf7be 900brcmf_chip_cm3_enterdl(struct brcmf_chip_priv *chip)
069eddd9 901{
cb7cf7be
AS		 902 struct brcmf_core *core;
903
904 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
905 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
906 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
907 D11_BCMA_IOCTL_PHYCLOCKEN,
908 D11_BCMA_IOCTL_PHYCLOCKEN,
909 D11_BCMA_IOCTL_PHYCLOCKEN);
910 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
911 brcmf_chip_resetcore(core, 0, 0, 0);
069eddd9
FL		 912}
913
cb7cf7be 914static bool brcmf_chip_cm3_exitdl(struct brcmf_chip_priv *chip)
069eddd9 915{
cb7cf7be 916 struct brcmf_core *core;
069eddd9 917
cb7cf7be
AS		 918 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
919 if (!brcmf_chip_iscoreup(core)) {
069eddd9
FL		 920 brcmf_err("SOCRAM core is down after reset?\n");
921 return false;
922 }
923
cb7cf7be 924 chip->ops->exit_dl(chip->ctx, &chip->pub, 0);
069eddd9 925
cb7cf7be
AS		 926 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
927 brcmf_chip_resetcore(core, 0, 0, 0);
1640f28f
FL		 928
929 return true;
930}
931
932static inline void
cb7cf7be 933brcmf_chip_cr4_enterdl(struct brcmf_chip_priv *chip)
1640f28f 934{
cb7cf7be 935 struct brcmf_core *core;
53036261 936
cb7cf7be 937 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
53036261 938
cb7cf7be
AS		 939 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
940 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
941 D11_BCMA_IOCTL_PHYCLOCKEN,
942 D11_BCMA_IOCTL_PHYCLOCKEN,
943 D11_BCMA_IOCTL_PHYCLOCKEN);
1640f28f
FL		 944}
945
cb7cf7be 946static bool brcmf_chip_cr4_exitdl(struct brcmf_chip_priv *chip, u32 rstvec)
1640f28f 947{
cb7cf7be 948 struct brcmf_core *core;
1640f28f 949
cb7cf7be 950 chip->ops->exit_dl(chip->ctx, &chip->pub, rstvec);
1640f28f
FL		 951
952 /* restore ARM */
cb7cf7be
AS		 953 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
954 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
069eddd9
FL		 955
956 return true;
957}
958
cb7cf7be 959void brcmf_chip_enter_download(struct brcmf_chip *pub)
069eddd9 960{
cb7cf7be
AS		 961 struct brcmf_chip_priv *chip;
962 struct brcmf_core *arm;
963
964 brcmf_dbg(TRACE, "Enter\n");
1640f28f 965
cb7cf7be 966 chip = container_of(pub, struct brcmf_chip_priv, pub);
2da5cb29 967 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
cb7cf7be 968 if (arm) {
2da5cb29 969 brcmf_chip_cr4_enterdl(chip);
1640f28f
FL		 970 return;
971 }
972
2da5cb29 973 brcmf_chip_cm3_enterdl(chip);
cb7cf7be
AS		 974}
975
976bool brcmf_chip_exit_download(struct brcmf_chip *pub, u32 rstvec)
977{
978 struct brcmf_chip_priv *chip;
979 struct brcmf_core *arm;
980
981 brcmf_dbg(TRACE, "Enter\n");
982
983 chip = container_of(pub, struct brcmf_chip_priv, pub);
2da5cb29 984 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
cb7cf7be 985 if (arm)
2da5cb29 986 return brcmf_chip_cr4_exitdl(chip, rstvec);
cb7cf7be 987
2da5cb29 988 return brcmf_chip_cm3_exitdl(chip);
069eddd9
FL		 989}
990
cb7cf7be 991bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
069eddd9 992{
cb7cf7be
AS		 993 u32 base, addr, reg, pmu_cc3_mask = ~0;
994 struct brcmf_chip_priv *chip;
1640f28f 995
cb7cf7be
AS		 996 brcmf_dbg(TRACE, "Enter\n");
997
998 /* old chips with PMU version less than 17 don't support save restore */
999 if (pub->pmurev < 17)
1000 return false;
1640f28f 1001
cb7cf7be
AS		 1002 base = brcmf_chip_get_chipcommon(pub)->base;
1003 chip = container_of(pub, struct brcmf_chip_priv, pub);
1004
1005 switch (pub->chip) {
5779ae6a 1006 case BRCM_CC_4354_CHIP_ID:
a797ca1e
FL		 1007 /* explicitly check SR engine enable bit */
1008 pmu_cc3_mask = BIT(2);
1009 /* fall-through */
5779ae6a
HM		 1010 case BRCM_CC_43241_CHIP_ID:
1011 case BRCM_CC_4335_CHIP_ID:
1012 case BRCM_CC_4339_CHIP_ID:
cb7cf7be
AS		 1013 /* read PMU chipcontrol register 3 */
1014 addr = CORE_CC_REG(base, chipcontrol_addr);
1015 chip->ops->write32(chip->ctx, addr, 3);
1016 addr = CORE_CC_REG(base, chipcontrol_data);
1017 reg = chip->ops->read32(chip->ctx, addr);
1018 return (reg & pmu_cc3_mask) != 0;
1019 default:
1020 addr = CORE_CC_REG(base, pmucapabilities_ext);
1021 reg = chip->ops->read32(chip->ctx, addr);
1022 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1023 return false;
1024
1025 addr = CORE_CC_REG(base, retention_ctl);
1026 reg = chip->ops->read32(chip->ctx, addr);
1027 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1028 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1029 }
069eddd9 1030}
Linux kernel - Deliverables
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