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brcmfmac: Adding PCIe bus layer support.
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / chip.c
CommitLineData
a83369b6 1/*
cb7cf7be 2 * Copyright (c) 2014 Broadcom Corporation
a83369b6
FL		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
cb7cf7be
AS		 16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/list.h>
61213be4 19#include <linux/ssb/ssb_regs.h>
99ba15cd 20#include <linux/bcma/bcma.h>
cb7cf7be 21#include <linux/bcma/bcma_regs.h>
61213be4 22
cb7cf7be
AS		 23#include <defs.h>
24#include <soc.h>
a83369b6 25#include <brcm_hw_ids.h>
a83369b6 26#include <brcmu_utils.h>
cb7cf7be 27#include <chipcommon.h>
a83369b6 28#include "dhd_dbg.h"
20c9c9bc 29#include "chip.h"
a83369b6 30
cb7cf7be
AS		 31/* SOC Interconnect types (aka chip types) */
32#define SOCI_SB 0
33#define SOCI_AI 1
34
4aa2c47c
AS		 35/* PL-368 DMP definitions */
36#define DMP_DESC_TYPE_MSK 0x0000000F
37#define DMP_DESC_EMPTY 0x00000000
38#define DMP_DESC_VALID 0x00000001
39#define DMP_DESC_COMPONENT 0x00000001
40#define DMP_DESC_MASTER_PORT 0x00000003
41#define DMP_DESC_ADDRESS 0x00000005
42#define DMP_DESC_ADDRSIZE_GT32 0x00000008
43#define DMP_DESC_EOT 0x0000000F
44
45#define DMP_COMP_DESIGNER 0xFFF00000
46#define DMP_COMP_DESIGNER_S 20
47#define DMP_COMP_PARTNUM 0x000FFF00
48#define DMP_COMP_PARTNUM_S 8
49#define DMP_COMP_CLASS 0x000000F0
50#define DMP_COMP_CLASS_S 4
51#define DMP_COMP_REVISION 0xFF000000
52#define DMP_COMP_REVISION_S 24
53#define DMP_COMP_NUM_SWRAP 0x00F80000
54#define DMP_COMP_NUM_SWRAP_S 19
55#define DMP_COMP_NUM_MWRAP 0x0007C000
56#define DMP_COMP_NUM_MWRAP_S 14
57#define DMP_COMP_NUM_SPORT 0x00003E00
58#define DMP_COMP_NUM_SPORT_S 9
59#define DMP_COMP_NUM_MPORT 0x000001F0
60#define DMP_COMP_NUM_MPORT_S 4
61
62#define DMP_MASTER_PORT_UID 0x0000FF00
63#define DMP_MASTER_PORT_UID_S 8
64#define DMP_MASTER_PORT_NUM 0x000000F0
65#define DMP_MASTER_PORT_NUM_S 4
66
67#define DMP_SLAVE_ADDR_BASE 0xFFFFF000
68#define DMP_SLAVE_ADDR_BASE_S 12
69#define DMP_SLAVE_PORT_NUM 0x00000F00
70#define DMP_SLAVE_PORT_NUM_S 8
71#define DMP_SLAVE_TYPE 0x000000C0
72#define DMP_SLAVE_TYPE_S 6
73#define DMP_SLAVE_TYPE_SLAVE 0
74#define DMP_SLAVE_TYPE_BRIDGE 1
75#define DMP_SLAVE_TYPE_SWRAP 2
76#define DMP_SLAVE_TYPE_MWRAP 3
77#define DMP_SLAVE_SIZE_TYPE 0x00000030
78#define DMP_SLAVE_SIZE_TYPE_S 4
79#define DMP_SLAVE_SIZE_4K 0
80#define DMP_SLAVE_SIZE_8K 1
81#define DMP_SLAVE_SIZE_16K 2
82#define DMP_SLAVE_SIZE_DESC 3
83
cb7cf7be
AS		 84/* EROM CompIdentB */
85#define CIB_REV_MASK 0xff000000
86#define CIB_REV_SHIFT 24
87
88/* ARM CR4 core specific control flag bits */
89#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
90
91/* D11 core specific control flag bits */
92#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
93#define D11_BCMA_IOCTL_PHYRESET 0x0008
94
a83369b6
FL		 95/* chip core base & ramsize */
96/* bcm4329 */
97/* SDIO device core, ID 0x829 */
98#define BCM4329_CORE_BUS_BASE 0x18011000
99/* internal memory core, ID 0x80e */
100#define BCM4329_CORE_SOCRAM_BASE 0x18003000
101/* ARM Cortex M3 core, ID 0x82a */
102#define BCM4329_CORE_ARM_BASE 0x18002000
103#define BCM4329_RAMSIZE 0x48000
104
369508c5
HM		 105/* bcm43143 */
106/* SDIO device core */
107#define BCM43143_CORE_BUS_BASE 0x18002000
108/* internal memory core */
109#define BCM43143_CORE_SOCRAM_BASE 0x18004000
110/* ARM Cortex M3 core, ID 0x82a */
111#define BCM43143_CORE_ARM_BASE 0x18003000
112#define BCM43143_RAMSIZE 0x70000
113
cb7cf7be
AS		 114#define CORE_SB(base, field) \
115 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
a83369b6 116#define SBCOREREV(sbidh) \
61213be4
FL		 117 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
118 ((sbidh) & SSB_IDHIGH_RCLO))
a83369b6 119
cb7cf7be
AS		 120struct sbconfig {
121 u32 PAD[2];
122 u32 sbipsflag; /* initiator port ocp slave flag */
123 u32 PAD[3];
124 u32 sbtpsflag; /* target port ocp slave flag */
125 u32 PAD[11];
126 u32 sbtmerrloga; /* (sonics >= 2.3) */
127 u32 PAD;
128 u32 sbtmerrlog; /* (sonics >= 2.3) */
129 u32 PAD[3];
130 u32 sbadmatch3; /* address match3 */
131 u32 PAD;
132 u32 sbadmatch2; /* address match2 */
133 u32 PAD;
134 u32 sbadmatch1; /* address match1 */
135 u32 PAD[7];
136 u32 sbimstate; /* initiator agent state */
137 u32 sbintvec; /* interrupt mask */
138 u32 sbtmstatelow; /* target state */
139 u32 sbtmstatehigh; /* target state */
140 u32 sbbwa0; /* bandwidth allocation table0 */
141 u32 PAD;
142 u32 sbimconfiglow; /* initiator configuration */
143 u32 sbimconfighigh; /* initiator configuration */
144 u32 sbadmatch0; /* address match0 */
145 u32 PAD;
146 u32 sbtmconfiglow; /* target configuration */
147 u32 sbtmconfighigh; /* target configuration */
148 u32 sbbconfig; /* broadcast configuration */
149 u32 PAD;
150 u32 sbbstate; /* broadcast state */
151 u32 PAD[3];
152 u32 sbactcnfg; /* activate configuration */
153 u32 PAD[3];
154 u32 sbflagst; /* current sbflags */
155 u32 PAD[3];
156 u32 sbidlow; /* identification */
157 u32 sbidhigh; /* identification */
158};
159
160struct brcmf_core_priv {
161 struct brcmf_core pub;
162 u32 wrapbase;
163 struct list_head list;
164 struct brcmf_chip_priv *chip;
165};
523894f2 166
1640f28f
FL		 167/* ARM CR4 core specific control flag bits */
168#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
169
53036261
HM		 170/* D11 core specific control flag bits */
171#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
172#define D11_BCMA_IOCTL_PHYRESET 0x0008
173
cb7cf7be
AS		 174struct brcmf_chip_priv {
175 struct brcmf_chip pub;
176 const struct brcmf_buscore_ops *ops;
177 void *ctx;
178 /* assured first core is chipcommon, second core is buscore */
179 struct list_head cores;
180 u16 num_cores;
181
182 bool (*iscoreup)(struct brcmf_core_priv *core);
183 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
184 u32 reset);
185 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
186 u32 postreset);
187};
188
189static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
190 struct brcmf_core *core)
454d2a88
FL		 191{
192 u32 regdata;
523894f2 193
cb7cf7be
AS		 194 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
195 core->rev = SBCOREREV(regdata);
454d2a88
FL		 196}
197
cb7cf7be 198static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
d8f64a42 199{
cb7cf7be 200 struct brcmf_chip_priv *ci;
d8f64a42 201 u32 regdata;
cb7cf7be 202 u32 address;
d8f64a42 203
cb7cf7be
AS		 204 ci = core->chip;
205 address = CORE_SB(core->pub.base, sbtmstatelow);
206 regdata = ci->ops->read32(ci->ctx, address);
61213be4
FL		 207 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
208 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
20c9c9bc 209 return SSB_TMSLOW_CLOCK == regdata;
d8f64a42
FL		 210}
211
cb7cf7be 212static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
6ca687d9 213{
cb7cf7be 214 struct brcmf_chip_priv *ci;
6ca687d9 215 u32 regdata;
6ca687d9
FL		 216 bool ret;
217
cb7cf7be
AS		 218 ci = core->chip;
219 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
6ca687d9
FL		 220 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
221
cb7cf7be 222 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
6ca687d9
FL		 223 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
224
225 return ret;
226}
227
cb7cf7be
AS		 228static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
229 u32 prereset, u32 reset)
2d4a9af1 230{
cb7cf7be
AS		 231 struct brcmf_chip_priv *ci;
232 u32 val, base;
086a2e0a 233
cb7cf7be
AS		 234 ci = core->chip;
235 base = core->pub.base;
236 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
237 if (val & SSB_TMSLOW_RESET)
2d4a9af1
FL		 238 return;
239
cb7cf7be
AS		 240 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
241 if ((val & SSB_TMSLOW_CLOCK) != 0) {
2d4a9af1
FL		 242 /*
243 * set target reject and spin until busy is clear
244 * (preserve core-specific bits)
245 */
cb7cf7be
AS		 246 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
247 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
248 val | SSB_TMSLOW_REJECT);
2d4a9af1 249
cb7cf7be 250 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2d4a9af1 251 udelay(1);
cb7cf7be
AS		 252 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
253 & SSB_TMSHIGH_BUSY), 100000);
254
255 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
256 if (val & SSB_TMSHIGH_BUSY)
5e8149f5 257 brcmf_err("core state still busy\n");
2d4a9af1 258
cb7cf7be
AS		 259 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
260 if (val & SSB_IDLOW_INITIATOR) {
261 val = ci->ops->read32(ci->ctx,
262 CORE_SB(base, sbimstate));
263 val |= SSB_IMSTATE_REJECT;
264 ci->ops->write32(ci->ctx,
265 CORE_SB(base, sbimstate), val);
266 val = ci->ops->read32(ci->ctx,
267 CORE_SB(base, sbimstate));
2d4a9af1 268 udelay(1);
cb7cf7be
AS		 269 SPINWAIT((ci->ops->read32(ci->ctx,
270 CORE_SB(base, sbimstate)) &
a39be27b 271 SSB_IMSTATE_BUSY), 100000);
2d4a9af1
FL		 272 }
273
274 /* set reset and reject while enabling the clocks */
cb7cf7be
AS		 275 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
276 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
277 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
278 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2d4a9af1
FL		 279 udelay(10);
280
281 /* clear the initiator reject bit */
cb7cf7be
AS		 282 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
283 if (val & SSB_IDLOW_INITIATOR) {
284 val = ci->ops->read32(ci->ctx,
285 CORE_SB(base, sbimstate));
286 val &= ~SSB_IMSTATE_REJECT;
287 ci->ops->write32(ci->ctx,
288 CORE_SB(base, sbimstate), val);
2d4a9af1
FL		 289 }
290 }
291
292 /* leave reset and reject asserted */
cb7cf7be
AS		 293 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
294 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
2d4a9af1
FL		 295 udelay(1);
296}
297
cb7cf7be
AS		 298static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
299 u32 prereset, u32 reset)
086a2e0a 300{
cb7cf7be 301 struct brcmf_chip_priv *ci;
086a2e0a 302 u32 regdata;
086a2e0a 303
cb7cf7be 304 ci = core->chip;
53036261 305
ffa216bb 306 /* if core is already in reset, skip reset */
cb7cf7be 307 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
086a2e0a 308 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
ffa216bb 309 goto in_reset_configure;
086a2e0a 310
53036261 311 /* configure reset */
cb7cf7be
AS		 312 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
313 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
314 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
086a2e0a 315
53036261 316 /* put in reset */
cb7cf7be
AS		 317 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
318 BCMA_RESET_CTL_RESET);
1640f28f
FL		 319 usleep_range(10, 20);
320
53036261 321 /* wait till reset is 1 */
cb7cf7be 322 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
53036261
HM		 323 BCMA_RESET_CTL_RESET, 300);
324
ffa216bb 325in_reset_configure:
cb7cf7be
AS		 326 /* in-reset configure */
327 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
328 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
329 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
086a2e0a
FL		 330}
331
cb7cf7be
AS		 332static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
333 u32 reset, u32 postreset)
2bc78e10 334{
cb7cf7be 335 struct brcmf_chip_priv *ci;
2bc78e10 336 u32 regdata;
cb7cf7be 337 u32 base;
2bc78e10 338
cb7cf7be
AS		 339 ci = core->chip;
340 base = core->pub.base;
2bc78e10
FL		 341 /*
342 * Must do the disable sequence first to work for
343 * arbitrary current core state.
344 */
cb7cf7be 345 brcmf_chip_sb_coredisable(core, 0, 0);
2bc78e10
FL		 346
347 /*
348 * Now do the initialization sequence.
349 * set reset while enabling the clock and
350 * forcing them on throughout the core
351 */
cb7cf7be
AS		 352 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
353 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
354 SSB_TMSLOW_RESET);
355 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2bc78e10
FL		 356 udelay(1);
357
d77e70ff 358 /* clear any serror */
cb7cf7be 359 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
61213be4 360 if (regdata & SSB_TMSHIGH_SERR)
cb7cf7be
AS		 361 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
362
363 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
364 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
365 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
366 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
367 }
2bc78e10
FL		 368
369 /* clear reset and allow it to propagate throughout the core */
cb7cf7be
AS		 370 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
371 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
372 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2bc78e10
FL		 373 udelay(1);
374
375 /* leave clock enabled */
cb7cf7be
AS		 376 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
377 SSB_TMSLOW_CLOCK);
378 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
d77e70ff
FL		 379 udelay(1);
380}
381
cb7cf7be
AS		 382static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
383 u32 reset, u32 postreset)
d77e70ff 384{
cb7cf7be
AS		 385 struct brcmf_chip_priv *ci;
386 int count;
d77e70ff 387
cb7cf7be 388 ci = core->chip;
53036261 389
d77e70ff 390 /* must disable first to work for arbitrary current core state */
cb7cf7be 391 brcmf_chip_ai_coredisable(core, prereset, reset);
d77e70ff 392
cb7cf7be
AS		 393 count = 0;
394 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
53036261 395 BCMA_RESET_CTL_RESET) {
cb7cf7be
AS		 396 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
397 count++;
398 if (count > 50)
399 break;
53036261
HM		 400 usleep_range(40, 60);
401 }
d77e70ff 402
cb7cf7be
AS		 403 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
404 postreset | BCMA_IOCTL_CLK);
405 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
406}
407
408static char *brcmf_chip_name(uint chipid, char *buf, uint len)
409{
410 const char *fmt;
411
412 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
413 snprintf(buf, len, fmt, chipid);
414 return buf;
415}
416
417static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
418 u16 coreid, u32 base,
419 u32 wrapbase)
420{
421 struct brcmf_core_priv *core;
422
423 core = kzalloc(sizeof(*core), GFP_KERNEL);
424 if (!core)
425 return ERR_PTR(-ENOMEM);
426
427 core->pub.id = coreid;
428 core->pub.base = base;
429 core->chip = ci;
430 core->wrapbase = wrapbase;
431
432 list_add_tail(&core->list, &ci->cores);
433 return &core->pub;
2bc78e10
FL		 434}
435
1640f28f
FL		 436#ifdef DEBUG
437/* safety check for chipinfo */
cb7cf7be 438static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
1640f28f 439{
cb7cf7be
AS		 440 struct brcmf_core_priv *core;
441 bool need_socram = false;
442 bool has_socram = false;
443 int idx = 1;
444
445 list_for_each_entry(core, &ci->cores, list) {
4aa2c47c
AS		 446 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
447 idx++, core->pub.id, core->pub.rev, core->pub.base,
448 core->wrapbase);
cb7cf7be
AS		 449
450 switch (core->pub.id) {
451 case BCMA_CORE_ARM_CM3:
452 need_socram = true;
453 break;
454 case BCMA_CORE_INTERNAL_MEM:
455 has_socram = true;
456 break;
457 case BCMA_CORE_ARM_CR4:
458 if (ci->pub.rambase == 0) {
459 brcmf_err("RAM base not provided with ARM CR4 core\n");
460 return -ENOMEM;
461 }
462 break;
463 default:
464 break;
1640f28f
FL		 465 }
466 }
467
cb7cf7be
AS		 468 /* check RAM core presence for ARM CM3 core */
469 if (need_socram && !has_socram) {
470 brcmf_err("RAM core not provided with ARM CM3 core\n");
471 return -ENODEV;
1640f28f 472 }
1640f28f
FL		 473 return 0;
474}
475#else /* DEBUG */
cb7cf7be 476static inline int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
1640f28f
FL		 477{
478 return 0;
479}
480#endif
481
cb7cf7be 482static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
a83369b6 483{
cb7cf7be 484 switch (ci->pub.chip) {
5779ae6a 485 case BRCM_CC_4329_CHIP_ID:
cb7cf7be
AS		 486 ci->pub.ramsize = BCM4329_RAMSIZE;
487 break;
5779ae6a 488 case BRCM_CC_43143_CHIP_ID:
cb7cf7be
AS		 489 ci->pub.ramsize = BCM43143_RAMSIZE;
490 break;
5779ae6a 491 case BRCM_CC_43241_CHIP_ID:
cb7cf7be
AS		 492 ci->pub.ramsize = 0x90000;
493 break;
5779ae6a 494 case BRCM_CC_4330_CHIP_ID:
cb7cf7be
AS		 495 ci->pub.ramsize = 0x48000;
496 break;
5779ae6a 497 case BRCM_CC_4334_CHIP_ID:
cb7cf7be
AS		 498 ci->pub.ramsize = 0x80000;
499 break;
5779ae6a 500 case BRCM_CC_4335_CHIP_ID:
cb7cf7be
AS		 501 ci->pub.ramsize = 0xc0000;
502 ci->pub.rambase = 0x180000;
503 break;
5779ae6a 504 case BRCM_CC_43362_CHIP_ID:
cb7cf7be
AS		 505 ci->pub.ramsize = 0x3c000;
506 break;
5779ae6a
HM		 507 case BRCM_CC_4339_CHIP_ID:
508 case BRCM_CC_4354_CHIP_ID:
9e37f045
HM		 509 case BRCM_CC_4356_CHIP_ID:
510 case BRCM_CC_43567_CHIP_ID:
511 case BRCM_CC_43569_CHIP_ID:
512 case BRCM_CC_43570_CHIP_ID:
cb7cf7be
AS		 513 ci->pub.ramsize = 0xc0000;
514 ci->pub.rambase = 0x180000;
515 break;
9e37f045
HM		 516 case BRCM_CC_43602_CHIP_ID:
517 ci->pub.ramsize = 0xf0000;
518 ci->pub.rambase = 0x180000;
519 break;
cb7cf7be
AS		 520 default:
521 brcmf_err("unknown chip: %s\n", ci->pub.name);
522 break;
523 }
524}
525
4aa2c47c
AS		 526static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
527 u8 *type)
528{
529 u32 val;
530
531 /* read next descriptor */
532 val = ci->ops->read32(ci->ctx, *eromaddr);
533 *eromaddr += 4;
534
535 if (!type)
536 return val;
537
538 /* determine descriptor type */
539 *type = (val & DMP_DESC_TYPE_MSK);
540 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
541 *type = DMP_DESC_ADDRESS;
542
543 return val;
544}
545
546static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
547 u32 *regbase, u32 *wrapbase)
548{
549 u8 desc;
550 u32 val;
551 u8 mpnum = 0;
552 u8 stype, sztype, wraptype;
553
554 *regbase = 0;
555 *wrapbase = 0;
556
557 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
558 if (desc == DMP_DESC_MASTER_PORT) {
559 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
560 wraptype = DMP_SLAVE_TYPE_MWRAP;
561 } else if (desc == DMP_DESC_ADDRESS) {
562 /* revert erom address */
563 *eromaddr -= 4;
564 wraptype = DMP_SLAVE_TYPE_SWRAP;
565 } else {
566 *eromaddr -= 4;
567 return -EILSEQ;
568 }
569
570 do {
571 /* locate address descriptor */
572 do {
573 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
574 /* unexpected table end */
575 if (desc == DMP_DESC_EOT) {
576 *eromaddr -= 4;
577 return -EFAULT;
578 }
579 } while (desc != DMP_DESC_ADDRESS);
580
581 /* skip upper 32-bit address descriptor */
582 if (val & DMP_DESC_ADDRSIZE_GT32)
583 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
584
585 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
586
587 /* next size descriptor can be skipped */
588 if (sztype == DMP_SLAVE_SIZE_DESC) {
589 val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
590 /* skip upper size descriptor if present */
591 if (val & DMP_DESC_ADDRSIZE_GT32)
592 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
593 }
594
595 /* only look for 4K register regions */
596 if (sztype != DMP_SLAVE_SIZE_4K)
597 continue;
598
599 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
600
601 /* only regular slave and wrapper */
602 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
603 *regbase = val & DMP_SLAVE_ADDR_BASE;
604 if (*wrapbase == 0 && stype == wraptype)
605 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
606 } while (*regbase == 0 || *wrapbase == 0);
607
608 return 0;
609}
610
611static
612int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
613{
614 struct brcmf_core *core;
615 u32 eromaddr;
616 u8 desc_type = 0;
617 u32 val;
618 u16 id;
619 u8 nmp, nsp, nmw, nsw, rev;
620 u32 base, wrap;
621 int err;
622
623 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
624
625 while (desc_type != DMP_DESC_EOT) {
626 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
627 if (!(val & DMP_DESC_VALID))
628 continue;
629
630 if (desc_type == DMP_DESC_EMPTY)
631 continue;
632
633 /* need a component descriptor */
634 if (desc_type != DMP_DESC_COMPONENT)
635 continue;
636
637 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
638
639 /* next descriptor must be component as well */
640 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
641 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
642 return -EFAULT;
643
644 /* only look at cores with master port(s) */
645 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
646 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
647 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
648 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
649 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
650
651 /* need core with ports */
652 if (nmw + nsw == 0)
653 continue;
654
655 /* try to obtain register address info */
656 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
657 if (err)
658 continue;
659
660 /* finally a core to be added */
661 core = brcmf_chip_add_core(ci, id, base, wrap);
662 if (IS_ERR(core))
663 return PTR_ERR(core);
664
665 core->rev = rev;
666 }
667
668 return 0;
669}
670
cb7cf7be
AS		 671static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
672{
673 struct brcmf_core *core;
a83369b6 674 u32 regdata;
c805eeb7 675 u32 socitype;
a83369b6 676
069eddd9 677 /* Get CC core rev
c805eeb7 678 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
a83369b6
FL		 679 * For different chiptypes or old sdio hosts w/o chipcommon,
680 * other ways of recognition should be added here.
681 */
cb7cf7be
AS		 682 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
683 ci->pub.chip = regdata & CID_ID_MASK;
684 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
c805eeb7 685 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
a83369b6 686
cb7cf7be
AS		 687 brcmf_chip_name(ci->pub.chip, ci->pub.name, sizeof(ci->pub.name));
688 brcmf_dbg(INFO, "found %s chip: BCM%s, rev=%d\n",
689 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name,
690 ci->pub.chiprev);
a83369b6 691
c805eeb7 692 if (socitype == SOCI_SB) {
5779ae6a 693 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
c805eeb7
AS		 694 brcmf_err("SB chip is not supported\n");
695 return -ENODEV;
696 }
cb7cf7be
AS		 697 ci->iscoreup = brcmf_chip_sb_iscoreup;
698 ci->coredisable = brcmf_chip_sb_coredisable;
699 ci->resetcore = brcmf_chip_sb_resetcore;
700
701 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
702 SI_ENUM_BASE, 0);
703 brcmf_chip_sb_corerev(ci, core);
704 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
705 BCM4329_CORE_BUS_BASE, 0);
706 brcmf_chip_sb_corerev(ci, core);
707 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
708 BCM4329_CORE_SOCRAM_BASE, 0);
709 brcmf_chip_sb_corerev(ci, core);
710 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
711 BCM4329_CORE_ARM_BASE, 0);
712 brcmf_chip_sb_corerev(ci, core);
4aa2c47c
AS		 713
714 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
715 brcmf_chip_sb_corerev(ci, core);
c805eeb7 716 } else if (socitype == SOCI_AI) {
cb7cf7be
AS		 717 ci->iscoreup = brcmf_chip_ai_iscoreup;
718 ci->coredisable = brcmf_chip_ai_coredisable;
719 ci->resetcore = brcmf_chip_ai_resetcore;
c805eeb7 720
4aa2c47c 721 brcmf_chip_dmp_erom_scan(ci);
c805eeb7
AS		 722 } else {
723 brcmf_err("chip backplane type %u is not supported\n",
724 socitype);
6ca687d9
FL		 725 return -ENODEV;
726 }
727
cb7cf7be
AS		 728 brcmf_chip_get_raminfo(ci);
729
730 return brcmf_chip_cores_check(ci);
a83369b6
FL		 731}
732
cb7cf7be 733static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
5b45e54e 734{
cb7cf7be
AS		 735 struct brcmf_core *core;
736 struct brcmf_core_priv *cr4;
737 u32 val;
79ae3957 738
cb7cf7be
AS		 739
740 core = brcmf_chip_get_core(&chip->pub, id);
741 if (!core)
742 return;
743
744 switch (id) {
745 case BCMA_CORE_ARM_CM3:
746 brcmf_chip_coredisable(core, 0, 0);
747 break;
748 case BCMA_CORE_ARM_CR4:
749 cr4 = container_of(core, struct brcmf_core_priv, pub);
750
751 /* clear all IOCTL bits except HALT bit */
752 val = chip->ops->read32(chip->ctx, cr4->wrapbase + BCMA_IOCTL);
753 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
754 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
755 ARMCR4_BCMA_IOCTL_CPUHALT);
756 break;
757 default:
758 brcmf_err("unknown id: %u\n", id);
759 break;
760 }
761}
762
763static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
764{
765 struct brcmf_chip *pub;
766 struct brcmf_core_priv *cc;
cb7cf7be
AS		 767 u32 base;
768 u32 val;
769 int ret = 0;
770
771 pub = &chip->pub;
772 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
773 base = cc->pub.base;
5b45e54e
FL		 774
775 /* get chipcommon capabilites */
cb7cf7be
AS		 776 pub->cc_caps = chip->ops->read32(chip->ctx,
777 CORE_CC_REG(base, capabilities));
5b45e54e
FL		 778
779 /* get pmu caps & rev */
cb7cf7be
AS		 780 if (pub->cc_caps & CC_CAP_PMU) {
781 val = chip->ops->read32(chip->ctx,
782 CORE_CC_REG(base, pmucapabilities));
783 pub->pmurev = val & PCAP_REV_MASK;
784 pub->pmucaps = val;
5b45e54e
FL		 785 }
786
4aa2c47c
AS		 787 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
788 cc->pub.rev, pub->pmurev, pub->pmucaps);
cb7cf7be
AS		 789
790 /* execute bus core specific setup */
791 if (chip->ops->setup)
792 ret = chip->ops->setup(chip->ctx, pub);
966414da
FL		 793
794 /*
795 * Make sure any on-chip ARM is off (in case strapping is wrong),
796 * or downloaded code was already running.
797 */
cb7cf7be
AS		 798 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
799 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
800 return ret;
5b45e54e
FL		 801}
802
cb7cf7be
AS		 803struct brcmf_chip *brcmf_chip_attach(void *ctx,
804 const struct brcmf_buscore_ops *ops)
a83369b6 805{
cb7cf7be
AS		 806 struct brcmf_chip_priv *chip;
807 int err = 0;
808
809 if (WARN_ON(!ops->read32))
810 err = -EINVAL;
811 if (WARN_ON(!ops->write32))
812 err = -EINVAL;
813 if (WARN_ON(!ops->prepare))
814 err = -EINVAL;
815 if (WARN_ON(!ops->exit_dl))
816 err = -EINVAL;
817 if (err < 0)
818 return ERR_PTR(-EINVAL);
819
820 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
821 if (!chip)
822 return ERR_PTR(-ENOMEM);
823
824 INIT_LIST_HEAD(&chip->cores);
825 chip->num_cores = 0;
826 chip->ops = ops;
827 chip->ctx = ctx;
828
829 err = ops->prepare(ctx);
830 if (err < 0)
831 goto fail;
832
833 err = brcmf_chip_recognition(chip);
834 if (err < 0)
835 goto fail;
836
837 err = brcmf_chip_setup(chip);
838 if (err < 0)
839 goto fail;
840
841 return &chip->pub;
842
843fail:
844 brcmf_chip_detach(&chip->pub);
845 return ERR_PTR(err);
846}
a97e4fc5 847
cb7cf7be
AS		 848void brcmf_chip_detach(struct brcmf_chip *pub)
849{
850 struct brcmf_chip_priv *chip;
851 struct brcmf_core_priv *core;
852 struct brcmf_core_priv *tmp;
853
854 chip = container_of(pub, struct brcmf_chip_priv, pub);
855 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
856 list_del(&core->list);
857 kfree(core);
858 }
859 kfree(chip);
860}
a97e4fc5 861
cb7cf7be
AS		 862struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
863{
864 struct brcmf_chip_priv *chip;
865 struct brcmf_core_priv *core;
a83369b6 866
cb7cf7be
AS		 867 chip = container_of(pub, struct brcmf_chip_priv, pub);
868 list_for_each_entry(core, &chip->cores, list)
869 if (core->pub.id == coreid)
870 return &core->pub;
e63ac6b8 871
cb7cf7be
AS		 872 return NULL;
873}
a83369b6 874
cb7cf7be
AS		 875struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
876{
877 struct brcmf_chip_priv *chip;
878 struct brcmf_core_priv *cc;
879
880 chip = container_of(pub, struct brcmf_chip_priv, pub);
881 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
882 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
883 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
884 return &cc->pub;
885}
5b45e54e 886
cb7cf7be
AS		 887bool brcmf_chip_iscoreup(struct brcmf_core *pub)
888{
889 struct brcmf_core_priv *core;
960908dc 890
cb7cf7be
AS		 891 core = container_of(pub, struct brcmf_core_priv, pub);
892 return core->chip->iscoreup(core);
893}
a97e4fc5 894
cb7cf7be
AS		 895void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
896{
897 struct brcmf_core_priv *core;
898
899 core = container_of(pub, struct brcmf_core_priv, pub);
900 core->chip->coredisable(core, prereset, reset);
a83369b6 901}
a8a6c045 902
cb7cf7be
AS		 903void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
904 u32 postreset)
a8a6c045 905{
cb7cf7be 906 struct brcmf_core_priv *core;
a8a6c045 907
cb7cf7be
AS		 908 core = container_of(pub, struct brcmf_core_priv, pub);
909 core->chip->resetcore(core, prereset, reset, postreset);
a8a6c045 910}
e12afb6c 911
069eddd9 912static void
cb7cf7be 913brcmf_chip_cm3_enterdl(struct brcmf_chip_priv *chip)
069eddd9 914{
cb7cf7be
AS		 915 struct brcmf_core *core;
916
917 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
918 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
919 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
920 D11_BCMA_IOCTL_PHYCLOCKEN,
921 D11_BCMA_IOCTL_PHYCLOCKEN,
922 D11_BCMA_IOCTL_PHYCLOCKEN);
923 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
924 brcmf_chip_resetcore(core, 0, 0, 0);
069eddd9
FL		 925}
926
cb7cf7be 927static bool brcmf_chip_cm3_exitdl(struct brcmf_chip_priv *chip)
069eddd9 928{
cb7cf7be 929 struct brcmf_core *core;
069eddd9 930
cb7cf7be
AS		 931 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
932 if (!brcmf_chip_iscoreup(core)) {
069eddd9
FL		 933 brcmf_err("SOCRAM core is down after reset?\n");
934 return false;
935 }
936
cb7cf7be 937 chip->ops->exit_dl(chip->ctx, &chip->pub, 0);
069eddd9 938
cb7cf7be
AS		 939 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
940 brcmf_chip_resetcore(core, 0, 0, 0);
1640f28f
FL		 941
942 return true;
943}
944
945static inline void
cb7cf7be 946brcmf_chip_cr4_enterdl(struct brcmf_chip_priv *chip)
1640f28f 947{
cb7cf7be 948 struct brcmf_core *core;
53036261 949
cb7cf7be 950 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
53036261 951
cb7cf7be
AS		 952 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
953 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
954 D11_BCMA_IOCTL_PHYCLOCKEN,
955 D11_BCMA_IOCTL_PHYCLOCKEN,
956 D11_BCMA_IOCTL_PHYCLOCKEN);
1640f28f
FL		 957}
958
cb7cf7be 959static bool brcmf_chip_cr4_exitdl(struct brcmf_chip_priv *chip, u32 rstvec)
1640f28f 960{
cb7cf7be 961 struct brcmf_core *core;
1640f28f 962
cb7cf7be 963 chip->ops->exit_dl(chip->ctx, &chip->pub, rstvec);
1640f28f
FL		 964
965 /* restore ARM */
cb7cf7be
AS		 966 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
967 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
069eddd9
FL		 968
969 return true;
970}
971
cb7cf7be 972void brcmf_chip_enter_download(struct brcmf_chip *pub)
069eddd9 973{
cb7cf7be
AS		 974 struct brcmf_chip_priv *chip;
975 struct brcmf_core *arm;
976
977 brcmf_dbg(TRACE, "Enter\n");
1640f28f 978
cb7cf7be 979 chip = container_of(pub, struct brcmf_chip_priv, pub);
2da5cb29 980 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
cb7cf7be 981 if (arm) {
2da5cb29 982 brcmf_chip_cr4_enterdl(chip);
1640f28f
FL		 983 return;
984 }
985
2da5cb29 986 brcmf_chip_cm3_enterdl(chip);
cb7cf7be
AS		 987}
988
989bool brcmf_chip_exit_download(struct brcmf_chip *pub, u32 rstvec)
990{
991 struct brcmf_chip_priv *chip;
992 struct brcmf_core *arm;
993
994 brcmf_dbg(TRACE, "Enter\n");
995
996 chip = container_of(pub, struct brcmf_chip_priv, pub);
2da5cb29 997 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
cb7cf7be 998 if (arm)
2da5cb29 999 return brcmf_chip_cr4_exitdl(chip, rstvec);
cb7cf7be 1000
2da5cb29 1001 return brcmf_chip_cm3_exitdl(chip);
069eddd9
FL		 1002}
1003
cb7cf7be 1004bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
069eddd9 1005{
cb7cf7be
AS		 1006 u32 base, addr, reg, pmu_cc3_mask = ~0;
1007 struct brcmf_chip_priv *chip;
1640f28f 1008
cb7cf7be
AS		 1009 brcmf_dbg(TRACE, "Enter\n");
1010
1011 /* old chips with PMU version less than 17 don't support save restore */
1012 if (pub->pmurev < 17)
1013 return false;
1640f28f 1014
cb7cf7be
AS		 1015 base = brcmf_chip_get_chipcommon(pub)->base;
1016 chip = container_of(pub, struct brcmf_chip_priv, pub);
1017
1018 switch (pub->chip) {
5779ae6a 1019 case BRCM_CC_4354_CHIP_ID:
a797ca1e
FL		 1020 /* explicitly check SR engine enable bit */
1021 pmu_cc3_mask = BIT(2);
1022 /* fall-through */
5779ae6a
HM		 1023 case BRCM_CC_43241_CHIP_ID:
1024 case BRCM_CC_4335_CHIP_ID:
1025 case BRCM_CC_4339_CHIP_ID:
cb7cf7be
AS		 1026 /* read PMU chipcontrol register 3 */
1027 addr = CORE_CC_REG(base, chipcontrol_addr);
1028 chip->ops->write32(chip->ctx, addr, 3);
1029 addr = CORE_CC_REG(base, chipcontrol_data);
1030 reg = chip->ops->read32(chip->ctx, addr);
1031 return (reg & pmu_cc3_mask) != 0;
1032 default:
1033 addr = CORE_CC_REG(base, pmucapabilities_ext);
1034 reg = chip->ops->read32(chip->ctx, addr);
1035 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1036 return false;
1037
1038 addr = CORE_CC_REG(base, retention_ctl);
1039 reg = chip->ops->read32(chip->ctx, addr);
1040 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1041 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1042 }
069eddd9 1043}
Linux kernel - Deliverables
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