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brcmfmac: remove unintended error logging
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / chip.c
CommitLineData
a83369b6 1/*
cb7cf7be 2 * Copyright (c) 2014 Broadcom Corporation
a83369b6
FL		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
cb7cf7be
AS		 16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/list.h>
61213be4 19#include <linux/ssb/ssb_regs.h>
99ba15cd 20#include <linux/bcma/bcma.h>
cb7cf7be 21#include <linux/bcma/bcma_regs.h>
61213be4 22
cb7cf7be
AS		 23#include <defs.h>
24#include <soc.h>
a83369b6 25#include <brcm_hw_ids.h>
a83369b6 26#include <brcmu_utils.h>
cb7cf7be 27#include <chipcommon.h>
a83369b6 28#include "dhd_dbg.h"
20c9c9bc 29#include "chip.h"
a83369b6 30
cb7cf7be
AS		 31/* SOC Interconnect types (aka chip types) */
32#define SOCI_SB 0
33#define SOCI_AI 1
34
35/* EROM CompIdentB */
36#define CIB_REV_MASK 0xff000000
37#define CIB_REV_SHIFT 24
38
39/* ARM CR4 core specific control flag bits */
40#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
41
42/* D11 core specific control flag bits */
43#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
44#define D11_BCMA_IOCTL_PHYRESET 0x0008
45
a83369b6
FL		 46/* chip core base & ramsize */
47/* bcm4329 */
48/* SDIO device core, ID 0x829 */
49#define BCM4329_CORE_BUS_BASE 0x18011000
50/* internal memory core, ID 0x80e */
51#define BCM4329_CORE_SOCRAM_BASE 0x18003000
52/* ARM Cortex M3 core, ID 0x82a */
53#define BCM4329_CORE_ARM_BASE 0x18002000
54#define BCM4329_RAMSIZE 0x48000
55
369508c5
HM		 56/* bcm43143 */
57/* SDIO device core */
58#define BCM43143_CORE_BUS_BASE 0x18002000
59/* internal memory core */
60#define BCM43143_CORE_SOCRAM_BASE 0x18004000
61/* ARM Cortex M3 core, ID 0x82a */
62#define BCM43143_CORE_ARM_BASE 0x18003000
63#define BCM43143_RAMSIZE 0x70000
64
cb7cf7be
AS		 65#define CORE_SB(base, field) \
66 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
a83369b6 67#define SBCOREREV(sbidh) \
61213be4
FL		 68 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
69 ((sbidh) & SSB_IDHIGH_RCLO))
a83369b6 70
cb7cf7be
AS		 71struct sbconfig {
72 u32 PAD[2];
73 u32 sbipsflag; /* initiator port ocp slave flag */
74 u32 PAD[3];
75 u32 sbtpsflag; /* target port ocp slave flag */
76 u32 PAD[11];
77 u32 sbtmerrloga; /* (sonics >= 2.3) */
78 u32 PAD;
79 u32 sbtmerrlog; /* (sonics >= 2.3) */
80 u32 PAD[3];
81 u32 sbadmatch3; /* address match3 */
82 u32 PAD;
83 u32 sbadmatch2; /* address match2 */
84 u32 PAD;
85 u32 sbadmatch1; /* address match1 */
86 u32 PAD[7];
87 u32 sbimstate; /* initiator agent state */
88 u32 sbintvec; /* interrupt mask */
89 u32 sbtmstatelow; /* target state */
90 u32 sbtmstatehigh; /* target state */
91 u32 sbbwa0; /* bandwidth allocation table0 */
92 u32 PAD;
93 u32 sbimconfiglow; /* initiator configuration */
94 u32 sbimconfighigh; /* initiator configuration */
95 u32 sbadmatch0; /* address match0 */
96 u32 PAD;
97 u32 sbtmconfiglow; /* target configuration */
98 u32 sbtmconfighigh; /* target configuration */
99 u32 sbbconfig; /* broadcast configuration */
100 u32 PAD;
101 u32 sbbstate; /* broadcast state */
102 u32 PAD[3];
103 u32 sbactcnfg; /* activate configuration */
104 u32 PAD[3];
105 u32 sbflagst; /* current sbflags */
106 u32 PAD[3];
107 u32 sbidlow; /* identification */
108 u32 sbidhigh; /* identification */
109};
110
111struct brcmf_core_priv {
112 struct brcmf_core pub;
113 u32 wrapbase;
114 struct list_head list;
115 struct brcmf_chip_priv *chip;
116};
523894f2 117
1640f28f
FL		 118/* ARM CR4 core specific control flag bits */
119#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
120
53036261
HM		 121/* D11 core specific control flag bits */
122#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
123#define D11_BCMA_IOCTL_PHYRESET 0x0008
124
cb7cf7be
AS		 125struct brcmf_chip_priv {
126 struct brcmf_chip pub;
127 const struct brcmf_buscore_ops *ops;
128 void *ctx;
129 /* assured first core is chipcommon, second core is buscore */
130 struct list_head cores;
131 u16 num_cores;
132
133 bool (*iscoreup)(struct brcmf_core_priv *core);
134 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
135 u32 reset);
136 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
137 u32 postreset);
138};
139
140static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
141 struct brcmf_core *core)
454d2a88
FL		 142{
143 u32 regdata;
523894f2 144
cb7cf7be
AS		 145 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
146 core->rev = SBCOREREV(regdata);
454d2a88
FL		 147}
148
cb7cf7be 149static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
d8f64a42 150{
cb7cf7be 151 struct brcmf_chip_priv *ci;
d8f64a42 152 u32 regdata;
cb7cf7be 153 u32 address;
d8f64a42 154
cb7cf7be
AS		 155 ci = core->chip;
156 address = CORE_SB(core->pub.base, sbtmstatelow);
157 regdata = ci->ops->read32(ci->ctx, address);
61213be4
FL		 158 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
159 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
20c9c9bc 160 return SSB_TMSLOW_CLOCK == regdata;
d8f64a42
FL		 161}
162
cb7cf7be 163static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
6ca687d9 164{
cb7cf7be 165 struct brcmf_chip_priv *ci;
6ca687d9 166 u32 regdata;
6ca687d9
FL		 167 bool ret;
168
cb7cf7be
AS		 169 ci = core->chip;
170 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
6ca687d9
FL		 171 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
172
cb7cf7be 173 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
6ca687d9
FL		 174 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
175
176 return ret;
177}
178
cb7cf7be
AS		 179static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
180 u32 prereset, u32 reset)
2d4a9af1 181{
cb7cf7be
AS		 182 struct brcmf_chip_priv *ci;
183 u32 val, base;
086a2e0a 184
cb7cf7be
AS		 185 ci = core->chip;
186 base = core->pub.base;
187 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
188 if (val & SSB_TMSLOW_RESET)
2d4a9af1
FL		 189 return;
190
cb7cf7be
AS		 191 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
192 if ((val & SSB_TMSLOW_CLOCK) != 0) {
2d4a9af1
FL		 193 /*
194 * set target reject and spin until busy is clear
195 * (preserve core-specific bits)
196 */
cb7cf7be
AS		 197 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
198 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
199 val | SSB_TMSLOW_REJECT);
2d4a9af1 200
cb7cf7be 201 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2d4a9af1 202 udelay(1);
cb7cf7be
AS		 203 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
204 & SSB_TMSHIGH_BUSY), 100000);
205
206 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
207 if (val & SSB_TMSHIGH_BUSY)
5e8149f5 208 brcmf_err("core state still busy\n");
2d4a9af1 209
cb7cf7be
AS		 210 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
211 if (val & SSB_IDLOW_INITIATOR) {
212 val = ci->ops->read32(ci->ctx,
213 CORE_SB(base, sbimstate));
214 val |= SSB_IMSTATE_REJECT;
215 ci->ops->write32(ci->ctx,
216 CORE_SB(base, sbimstate), val);
217 val = ci->ops->read32(ci->ctx,
218 CORE_SB(base, sbimstate));
2d4a9af1 219 udelay(1);
cb7cf7be
AS		 220 SPINWAIT((ci->ops->read32(ci->ctx,
221 CORE_SB(base, sbimstate)) &
a39be27b 222 SSB_IMSTATE_BUSY), 100000);
2d4a9af1
FL		 223 }
224
225 /* set reset and reject while enabling the clocks */
cb7cf7be
AS		 226 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
227 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
228 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
229 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2d4a9af1
FL		 230 udelay(10);
231
232 /* clear the initiator reject bit */
cb7cf7be
AS		 233 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
234 if (val & SSB_IDLOW_INITIATOR) {
235 val = ci->ops->read32(ci->ctx,
236 CORE_SB(base, sbimstate));
237 val &= ~SSB_IMSTATE_REJECT;
238 ci->ops->write32(ci->ctx,
239 CORE_SB(base, sbimstate), val);
2d4a9af1
FL		 240 }
241 }
242
243 /* leave reset and reject asserted */
cb7cf7be
AS		 244 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
245 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
2d4a9af1
FL		 246 udelay(1);
247}
248
cb7cf7be
AS		 249static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
250 u32 prereset, u32 reset)
086a2e0a 251{
cb7cf7be 252 struct brcmf_chip_priv *ci;
086a2e0a 253 u32 regdata;
086a2e0a 254
cb7cf7be 255 ci = core->chip;
53036261 256
086a2e0a 257 /* if core is already in reset, just return */
cb7cf7be 258 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
086a2e0a
FL		 259 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
260 return;
261
53036261 262 /* configure reset */
cb7cf7be
AS		 263 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
264 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
265 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
086a2e0a 266
53036261 267 /* put in reset */
cb7cf7be
AS		 268 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
269 BCMA_RESET_CTL_RESET);
1640f28f
FL		 270 usleep_range(10, 20);
271
53036261 272 /* wait till reset is 1 */
cb7cf7be 273 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
53036261
HM		 274 BCMA_RESET_CTL_RESET, 300);
275
cb7cf7be
AS		 276 /* in-reset configure */
277 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
278 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
279 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
086a2e0a
FL		 280}
281
cb7cf7be
AS		 282static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
283 u32 reset, u32 postreset)
2bc78e10 284{
cb7cf7be 285 struct brcmf_chip_priv *ci;
2bc78e10 286 u32 regdata;
cb7cf7be 287 u32 base;
2bc78e10 288
cb7cf7be
AS		 289 ci = core->chip;
290 base = core->pub.base;
2bc78e10
FL		 291 /*
292 * Must do the disable sequence first to work for
293 * arbitrary current core state.
294 */
cb7cf7be 295 brcmf_chip_sb_coredisable(core, 0, 0);
2bc78e10
FL		 296
297 /*
298 * Now do the initialization sequence.
299 * set reset while enabling the clock and
300 * forcing them on throughout the core
301 */
cb7cf7be
AS		 302 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
303 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
304 SSB_TMSLOW_RESET);
305 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2bc78e10
FL		 306 udelay(1);
307
d77e70ff 308 /* clear any serror */
cb7cf7be 309 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
61213be4 310 if (regdata & SSB_TMSHIGH_SERR)
cb7cf7be
AS		 311 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
312
313 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
314 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
315 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
316 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
317 }
2bc78e10
FL		 318
319 /* clear reset and allow it to propagate throughout the core */
cb7cf7be
AS		 320 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
321 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
322 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
2bc78e10
FL		 323 udelay(1);
324
325 /* leave clock enabled */
cb7cf7be
AS		 326 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
327 SSB_TMSLOW_CLOCK);
328 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
d77e70ff
FL		 329 udelay(1);
330}
331
cb7cf7be
AS		 332static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
333 u32 reset, u32 postreset)
d77e70ff 334{
cb7cf7be
AS		 335 struct brcmf_chip_priv *ci;
336 int count;
d77e70ff 337
cb7cf7be 338 ci = core->chip;
53036261 339
d77e70ff 340 /* must disable first to work for arbitrary current core state */
cb7cf7be 341 brcmf_chip_ai_coredisable(core, prereset, reset);
d77e70ff 342
cb7cf7be
AS		 343 count = 0;
344 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
53036261 345 BCMA_RESET_CTL_RESET) {
cb7cf7be
AS		 346 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
347 count++;
348 if (count > 50)
349 break;
53036261
HM		 350 usleep_range(40, 60);
351 }
d77e70ff 352
cb7cf7be
AS		 353 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
354 postreset | BCMA_IOCTL_CLK);
355 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
356}
357
358static char *brcmf_chip_name(uint chipid, char *buf, uint len)
359{
360 const char *fmt;
361
362 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
363 snprintf(buf, len, fmt, chipid);
364 return buf;
365}
366
367static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
368 u16 coreid, u32 base,
369 u32 wrapbase)
370{
371 struct brcmf_core_priv *core;
372
373 core = kzalloc(sizeof(*core), GFP_KERNEL);
374 if (!core)
375 return ERR_PTR(-ENOMEM);
376
377 core->pub.id = coreid;
378 core->pub.base = base;
379 core->chip = ci;
380 core->wrapbase = wrapbase;
381
382 list_add_tail(&core->list, &ci->cores);
383 return &core->pub;
2bc78e10
FL		 384}
385
1640f28f
FL		 386#ifdef DEBUG
387/* safety check for chipinfo */
cb7cf7be 388static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
1640f28f 389{
cb7cf7be
AS		 390 struct brcmf_core_priv *core;
391 bool need_socram = false;
392 bool has_socram = false;
393 int idx = 1;
394
395 list_for_each_entry(core, &ci->cores, list) {
396 brcmf_dbg(INFO, " [%-2d] core 0x%x rev %-2d base 0x%08x\n",
397 idx++, core->pub.id, core->pub.rev, core->pub.base);
398
399 switch (core->pub.id) {
400 case BCMA_CORE_ARM_CM3:
401 need_socram = true;
402 break;
403 case BCMA_CORE_INTERNAL_MEM:
404 has_socram = true;
405 break;
406 case BCMA_CORE_ARM_CR4:
407 if (ci->pub.rambase == 0) {
408 brcmf_err("RAM base not provided with ARM CR4 core\n");
409 return -ENOMEM;
410 }
411 break;
412 default:
413 break;
1640f28f
FL		 414 }
415 }
416
cb7cf7be
AS		 417 /* check RAM core presence for ARM CM3 core */
418 if (need_socram && !has_socram) {
419 brcmf_err("RAM core not provided with ARM CM3 core\n");
420 return -ENODEV;
1640f28f 421 }
1640f28f
FL		 422 return 0;
423}
424#else /* DEBUG */
cb7cf7be 425static inline int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
1640f28f
FL		 426{
427 return 0;
428}
429#endif
430
cb7cf7be 431static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
a83369b6 432{
cb7cf7be
AS		 433 switch (ci->pub.chip) {
434 case BCM4329_CHIP_ID:
435 ci->pub.ramsize = BCM4329_RAMSIZE;
436 break;
437 case BCM43143_CHIP_ID:
438 ci->pub.ramsize = BCM43143_RAMSIZE;
439 break;
440 case BCM43241_CHIP_ID:
441 ci->pub.ramsize = 0x90000;
442 break;
443 case BCM4330_CHIP_ID:
444 ci->pub.ramsize = 0x48000;
445 break;
446 case BCM4334_CHIP_ID:
447 ci->pub.ramsize = 0x80000;
448 break;
449 case BCM4335_CHIP_ID:
450 ci->pub.ramsize = 0xc0000;
451 ci->pub.rambase = 0x180000;
452 break;
453 case BCM43362_CHIP_ID:
454 ci->pub.ramsize = 0x3c000;
455 break;
456 case BCM4339_CHIP_ID:
457 ci->pub.ramsize = 0xc0000;
458 ci->pub.rambase = 0x180000;
459 break;
460 default:
461 brcmf_err("unknown chip: %s\n", ci->pub.name);
462 break;
463 }
464}
465
466static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
467{
468 struct brcmf_core *core;
a83369b6 469 u32 regdata;
c805eeb7 470 u32 socitype;
a83369b6 471
069eddd9 472 /* Get CC core rev
c805eeb7 473 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
a83369b6
FL		 474 * For different chiptypes or old sdio hosts w/o chipcommon,
475 * other ways of recognition should be added here.
476 */
cb7cf7be
AS		 477 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
478 ci->pub.chip = regdata & CID_ID_MASK;
479 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
c805eeb7 480 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
a83369b6 481
cb7cf7be
AS		 482 brcmf_chip_name(ci->pub.chip, ci->pub.name, sizeof(ci->pub.name));
483 brcmf_dbg(INFO, "found %s chip: BCM%s, rev=%d\n",
484 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name,
485 ci->pub.chiprev);
a83369b6 486
c805eeb7 487 if (socitype == SOCI_SB) {
cb7cf7be 488 if (ci->pub.chip != BCM4329_CHIP_ID) {
c805eeb7
AS		 489 brcmf_err("SB chip is not supported\n");
490 return -ENODEV;
491 }
cb7cf7be
AS		 492 ci->iscoreup = brcmf_chip_sb_iscoreup;
493 ci->coredisable = brcmf_chip_sb_coredisable;
494 ci->resetcore = brcmf_chip_sb_resetcore;
495
496 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
497 SI_ENUM_BASE, 0);
498 brcmf_chip_sb_corerev(ci, core);
499 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
500 BCM4329_CORE_BUS_BASE, 0);
501 brcmf_chip_sb_corerev(ci, core);
502 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
503 BCM4329_CORE_SOCRAM_BASE, 0);
504 brcmf_chip_sb_corerev(ci, core);
505 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
506 BCM4329_CORE_ARM_BASE, 0);
507 brcmf_chip_sb_corerev(ci, core);
c805eeb7 508 } else if (socitype == SOCI_AI) {
cb7cf7be
AS		 509 ci->iscoreup = brcmf_chip_ai_iscoreup;
510 ci->coredisable = brcmf_chip_ai_coredisable;
511 ci->resetcore = brcmf_chip_ai_resetcore;
c805eeb7 512
cb7cf7be
AS		 513 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
514 SI_ENUM_BASE,
515 SI_ENUM_BASE + 0x100000);
c805eeb7
AS		 516
517 /* Address of cores for new chips should be added here */
cb7cf7be 518 switch (ci->pub.chip) {
c805eeb7 519 case BCM43143_CHIP_ID:
cb7cf7be
AS		 520 core->rev = 43;
521 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
522 BCM43143_CORE_BUS_BASE,
523 BCM43143_CORE_BUS_BASE +
524 0x100000);
525 core->rev = 24;
526 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
527 BCM43143_CORE_SOCRAM_BASE,
528 BCM43143_CORE_SOCRAM_BASE +
529 0x100000);
530 core->rev = 20;
531 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
532 BCM43143_CORE_ARM_BASE,
533 BCM43143_CORE_ARM_BASE +
534 0x100000);
535 core->rev = 7;
c805eeb7
AS		 536 break;
537 case BCM43241_CHIP_ID:
cb7cf7be
AS		 538 core->rev = 42;
539 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
540 0x18002000, 0x18102000);
541 core->rev = 14;
542 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
543 0x18004000, 0x18104000);
544 core->rev = 20;
545 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
546 0x18003000, 0x18103000);
547 core->rev = 7;
c805eeb7
AS		 548 break;
549 case BCM4330_CHIP_ID:
cb7cf7be
AS		 550 core->rev = 39;
551 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
552 0x18002000, 0x18102000);
553 core->rev = 7;
554 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
555 0x18004000, 0x18104000);
556 core->rev = 13;
557 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
558 0x18003000, 0x18103000);
559 core->rev = 3;
c805eeb7
AS		 560 break;
561 case BCM4334_CHIP_ID:
cb7cf7be
AS		 562 core->rev = 41;
563 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
564 0x18002000, 0x18102000);
565 core->rev = 13;
566 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
567 0x18004000, 0x18104000);
568 core->rev = 19;
569 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
570 0x18003000, 0x18103000);
571 core->rev = 7;
c805eeb7
AS		 572 break;
573 case BCM4335_CHIP_ID:
cb7cf7be
AS		 574 core->rev = 43;
575 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
576 0x18005000, 0x18105000);
577 core->rev = 15;
578 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CR4,
579 0x18002000, 0x18102000);
580 core->rev = 1;
c805eeb7
AS		 581 break;
582 case BCM43362_CHIP_ID:
cb7cf7be
AS		 583 core->rev = 39;
584 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
585 0x18002000, 0x18102000);
586 core->rev = 10;
587 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
588 0x18004000, 0x18104000);
589 core->rev = 8;
590 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
591 0x18003000, 0x18103000);
592 core->rev = 3;
c805eeb7
AS		 593 break;
594 case BCM4339_CHIP_ID:
cb7cf7be
AS		 595 core->rev = 46;
596 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
597 0x18005000, 0x18105000);
598 core->rev = 21;
599 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CR4,
600 0x18002000, 0x18102000);
601 core->rev = 4;
c805eeb7
AS		 602 break;
603 default:
604 brcmf_err("AXI chip is not supported\n");
605 return -ENODEV;
606 }
607 } else {
608 brcmf_err("chip backplane type %u is not supported\n",
609 socitype);
6ca687d9
FL		 610 return -ENODEV;
611 }
612
cb7cf7be
AS		 613 /* add 802.11 core for all chips on same backplane address */
614 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0x18101000);
615
616 brcmf_chip_get_raminfo(ci);
617
618 return brcmf_chip_cores_check(ci);
a83369b6
FL		 619}
620
cb7cf7be 621static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
5b45e54e 622{
cb7cf7be
AS		 623 struct brcmf_core *core;
624 struct brcmf_core_priv *cr4;
625 u32 val;
79ae3957 626
cb7cf7be
AS		 627
628 core = brcmf_chip_get_core(&chip->pub, id);
629 if (!core)
630 return;
631
632 switch (id) {
633 case BCMA_CORE_ARM_CM3:
634 brcmf_chip_coredisable(core, 0, 0);
635 break;
636 case BCMA_CORE_ARM_CR4:
637 cr4 = container_of(core, struct brcmf_core_priv, pub);
638
639 /* clear all IOCTL bits except HALT bit */
640 val = chip->ops->read32(chip->ctx, cr4->wrapbase + BCMA_IOCTL);
641 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
642 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
643 ARMCR4_BCMA_IOCTL_CPUHALT);
644 break;
645 default:
646 brcmf_err("unknown id: %u\n", id);
647 break;
648 }
649}
650
651static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
652{
653 struct brcmf_chip *pub;
654 struct brcmf_core_priv *cc;
655 struct brcmf_core_priv *bus;
656 u32 base;
657 u32 val;
658 int ret = 0;
659
660 pub = &chip->pub;
661 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
662 base = cc->pub.base;
5b45e54e
FL		 663
664 /* get chipcommon capabilites */
cb7cf7be
AS		 665 pub->cc_caps = chip->ops->read32(chip->ctx,
666 CORE_CC_REG(base, capabilities));
5b45e54e
FL		 667
668 /* get pmu caps & rev */
cb7cf7be
AS		 669 if (pub->cc_caps & CC_CAP_PMU) {
670 val = chip->ops->read32(chip->ctx,
671 CORE_CC_REG(base, pmucapabilities));
672 pub->pmurev = val & PCAP_REV_MASK;
673 pub->pmucaps = val;
5b45e54e
FL		 674 }
675
cb7cf7be 676 bus = list_next_entry(cc, list);
5b45e54e
FL		 677
678 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
cb7cf7be
AS		 679 cc->pub.rev, pub->pmurev, bus->pub.rev, bus->pub.id);
680
681 /* execute bus core specific setup */
682 if (chip->ops->setup)
683 ret = chip->ops->setup(chip->ctx, pub);
966414da
FL		 684
685 /*
686 * Make sure any on-chip ARM is off (in case strapping is wrong),
687 * or downloaded code was already running.
688 */
cb7cf7be
AS		 689 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
690 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
691 return ret;
5b45e54e
FL		 692}
693
cb7cf7be
AS		 694struct brcmf_chip *brcmf_chip_attach(void *ctx,
695 const struct brcmf_buscore_ops *ops)
a83369b6 696{
cb7cf7be
AS		 697 struct brcmf_chip_priv *chip;
698 int err = 0;
699
700 if (WARN_ON(!ops->read32))
701 err = -EINVAL;
702 if (WARN_ON(!ops->write32))
703 err = -EINVAL;
704 if (WARN_ON(!ops->prepare))
705 err = -EINVAL;
706 if (WARN_ON(!ops->exit_dl))
707 err = -EINVAL;
708 if (err < 0)
709 return ERR_PTR(-EINVAL);
710
711 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
712 if (!chip)
713 return ERR_PTR(-ENOMEM);
714
715 INIT_LIST_HEAD(&chip->cores);
716 chip->num_cores = 0;
717 chip->ops = ops;
718 chip->ctx = ctx;
719
720 err = ops->prepare(ctx);
721 if (err < 0)
722 goto fail;
723
724 err = brcmf_chip_recognition(chip);
725 if (err < 0)
726 goto fail;
727
728 err = brcmf_chip_setup(chip);
729 if (err < 0)
730 goto fail;
731
732 return &chip->pub;
733
734fail:
735 brcmf_chip_detach(&chip->pub);
736 return ERR_PTR(err);
737}
a97e4fc5 738
cb7cf7be
AS		 739void brcmf_chip_detach(struct brcmf_chip *pub)
740{
741 struct brcmf_chip_priv *chip;
742 struct brcmf_core_priv *core;
743 struct brcmf_core_priv *tmp;
744
745 chip = container_of(pub, struct brcmf_chip_priv, pub);
746 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
747 list_del(&core->list);
748 kfree(core);
749 }
750 kfree(chip);
751}
a97e4fc5 752
cb7cf7be
AS		 753struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
754{
755 struct brcmf_chip_priv *chip;
756 struct brcmf_core_priv *core;
a83369b6 757
cb7cf7be
AS		 758 chip = container_of(pub, struct brcmf_chip_priv, pub);
759 list_for_each_entry(core, &chip->cores, list)
760 if (core->pub.id == coreid)
761 return &core->pub;
e63ac6b8 762
cb7cf7be
AS		 763 return NULL;
764}
a83369b6 765
cb7cf7be
AS		 766struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
767{
768 struct brcmf_chip_priv *chip;
769 struct brcmf_core_priv *cc;
770
771 chip = container_of(pub, struct brcmf_chip_priv, pub);
772 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
773 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
774 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
775 return &cc->pub;
776}
5b45e54e 777
cb7cf7be
AS		 778bool brcmf_chip_iscoreup(struct brcmf_core *pub)
779{
780 struct brcmf_core_priv *core;
960908dc 781
cb7cf7be
AS		 782 core = container_of(pub, struct brcmf_core_priv, pub);
783 return core->chip->iscoreup(core);
784}
a97e4fc5 785
cb7cf7be
AS		 786void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
787{
788 struct brcmf_core_priv *core;
789
790 core = container_of(pub, struct brcmf_core_priv, pub);
791 core->chip->coredisable(core, prereset, reset);
a83369b6 792}
a8a6c045 793
cb7cf7be
AS		 794void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
795 u32 postreset)
a8a6c045 796{
cb7cf7be 797 struct brcmf_core_priv *core;
a8a6c045 798
cb7cf7be
AS		 799 core = container_of(pub, struct brcmf_core_priv, pub);
800 core->chip->resetcore(core, prereset, reset, postreset);
a8a6c045 801}
e12afb6c 802
069eddd9 803static void
cb7cf7be 804brcmf_chip_cm3_enterdl(struct brcmf_chip_priv *chip)
069eddd9 805{
cb7cf7be
AS		 806 struct brcmf_core *core;
807
808 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
809 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
810 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
811 D11_BCMA_IOCTL_PHYCLOCKEN,
812 D11_BCMA_IOCTL_PHYCLOCKEN,
813 D11_BCMA_IOCTL_PHYCLOCKEN);
814 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
815 brcmf_chip_resetcore(core, 0, 0, 0);
069eddd9
FL		 816}
817
cb7cf7be 818static bool brcmf_chip_cm3_exitdl(struct brcmf_chip_priv *chip)
069eddd9 819{
cb7cf7be 820 struct brcmf_core *core;
069eddd9 821
cb7cf7be
AS		 822 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
823 if (!brcmf_chip_iscoreup(core)) {
069eddd9
FL		 824 brcmf_err("SOCRAM core is down after reset?\n");
825 return false;
826 }
827
cb7cf7be 828 chip->ops->exit_dl(chip->ctx, &chip->pub, 0);
069eddd9 829
cb7cf7be
AS		 830 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
831 brcmf_chip_resetcore(core, 0, 0, 0);
1640f28f
FL		 832
833 return true;
834}
835
836static inline void
cb7cf7be 837brcmf_chip_cr4_enterdl(struct brcmf_chip_priv *chip)
1640f28f 838{
cb7cf7be 839 struct brcmf_core *core;
53036261 840
cb7cf7be 841 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
53036261 842
cb7cf7be
AS		 843 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
844 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
845 D11_BCMA_IOCTL_PHYCLOCKEN,
846 D11_BCMA_IOCTL_PHYCLOCKEN,
847 D11_BCMA_IOCTL_PHYCLOCKEN);
1640f28f
FL		 848}
849
cb7cf7be 850static bool brcmf_chip_cr4_exitdl(struct brcmf_chip_priv *chip, u32 rstvec)
1640f28f 851{
cb7cf7be 852 struct brcmf_core *core;
1640f28f 853
cb7cf7be 854 chip->ops->exit_dl(chip->ctx, &chip->pub, rstvec);
1640f28f
FL		 855
856 /* restore ARM */
cb7cf7be
AS		 857 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
858 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
069eddd9
FL		 859
860 return true;
861}
862
cb7cf7be 863void brcmf_chip_enter_download(struct brcmf_chip *pub)
069eddd9 864{
cb7cf7be
AS		 865 struct brcmf_chip_priv *chip;
866 struct brcmf_core *arm;
867
868 brcmf_dbg(TRACE, "Enter\n");
1640f28f 869
cb7cf7be
AS		 870 chip = container_of(pub, struct brcmf_chip_priv, pub);
871 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
872 if (arm) {
873 brcmf_chip_cm3_enterdl(chip);
1640f28f
FL		 874 return;
875 }
876
cb7cf7be
AS		 877 brcmf_chip_cr4_enterdl(chip);
878}
879
880bool brcmf_chip_exit_download(struct brcmf_chip *pub, u32 rstvec)
881{
882 struct brcmf_chip_priv *chip;
883 struct brcmf_core *arm;
884
885 brcmf_dbg(TRACE, "Enter\n");
886
887 chip = container_of(pub, struct brcmf_chip_priv, pub);
888 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
889 if (arm)
890 return brcmf_chip_cm3_exitdl(chip);
891
892 return brcmf_chip_cr4_exitdl(chip, rstvec);
069eddd9
FL		 893}
894
cb7cf7be 895bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
069eddd9 896{
cb7cf7be
AS		 897 u32 base, addr, reg, pmu_cc3_mask = ~0;
898 struct brcmf_chip_priv *chip;
1640f28f 899
cb7cf7be
AS		 900 brcmf_dbg(TRACE, "Enter\n");
901
902 /* old chips with PMU version less than 17 don't support save restore */
903 if (pub->pmurev < 17)
904 return false;
1640f28f 905
cb7cf7be
AS		 906 base = brcmf_chip_get_chipcommon(pub)->base;
907 chip = container_of(pub, struct brcmf_chip_priv, pub);
908
909 switch (pub->chip) {
910 case BCM43241_CHIP_ID:
911 case BCM4335_CHIP_ID:
912 case BCM4339_CHIP_ID:
913 /* read PMU chipcontrol register 3 */
914 addr = CORE_CC_REG(base, chipcontrol_addr);
915 chip->ops->write32(chip->ctx, addr, 3);
916 addr = CORE_CC_REG(base, chipcontrol_data);
917 reg = chip->ops->read32(chip->ctx, addr);
918 return (reg & pmu_cc3_mask) != 0;
919 default:
920 addr = CORE_CC_REG(base, pmucapabilities_ext);
921 reg = chip->ops->read32(chip->ctx, addr);
922 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
923 return false;
924
925 addr = CORE_CC_REG(base, retention_ctl);
926 reg = chip->ops->read32(chip->ctx, addr);
927 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
928 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
929 }
069eddd9 930}
Linux kernel - Deliverables
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