brcm80211: fmac: change function proto_hdrpull parameter
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
CommitLineData
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1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/kthread.h>
20#include <linux/printk.h>
21#include <linux/pci_ids.h>
22#include <linux/netdevice.h>
23#include <linux/interrupt.h>
24#include <linux/sched.h>
25#include <linux/mmc/sdio.h>
26#include <linux/mmc/sdio_func.h>
27#include <linux/mmc/card.h>
28#include <linux/semaphore.h>
29#include <linux/firmware.h>
b7a57e76 30#include <linux/module.h>
99ba15cd 31#include <linux/bcma/bcma.h>
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32#include <asm/unaligned.h>
33#include <defs.h>
34#include <brcmu_wifi.h>
35#include <brcmu_utils.h>
36#include <brcm_hw_ids.h>
37#include <soc.h>
38#include "sdio_host.h"
a83369b6 39#include "sdio_chip.h"
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40
41#define DCMD_RESP_TIMEOUT 2000 /* In milli second */
42
43#ifdef BCMDBG
44
45#define BRCMF_TRAP_INFO_SIZE 80
46
47#define CBUF_LEN (128)
48
49struct rte_log_le {
50 __le32 buf; /* Can't be pointer on (64-bit) hosts */
51 __le32 buf_size;
52 __le32 idx;
53 char *_buf_compat; /* Redundant pointer for backward compat. */
54};
55
56struct rte_console {
57 /* Virtual UART
58 * When there is no UART (e.g. Quickturn),
59 * the host should write a complete
60 * input line directly into cbuf and then write
61 * the length into vcons_in.
62 * This may also be used when there is a real UART
63 * (at risk of conflicting with
64 * the real UART). vcons_out is currently unused.
65 */
66 uint vcons_in;
67 uint vcons_out;
68
69 /* Output (logging) buffer
70 * Console output is written to a ring buffer log_buf at index log_idx.
71 * The host may read the output when it sees log_idx advance.
72 * Output will be lost if the output wraps around faster than the host
73 * polls.
74 */
75 struct rte_log_le log_le;
76
77 /* Console input line buffer
78 * Characters are read one at a time into cbuf
79 * until <CR> is received, then
80 * the buffer is processed as a command line.
81 * Also used for virtual UART.
82 */
83 uint cbuf_idx;
84 char cbuf[CBUF_LEN];
85};
86
87#endif /* BCMDBG */
88#include <chipcommon.h>
89
90#include "dhd.h"
91#include "dhd_bus.h"
92#include "dhd_proto.h"
93#include "dhd_dbg.h"
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94
95#define TXQLEN 2048 /* bulk tx queue length */
96#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
97#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
98#define PRIOMASK 7
99
100#define TXRETRIES 2 /* # of retries for tx frames */
101
102#define BRCMF_RXBOUND 50 /* Default for max rx frames in
103 one scheduling */
104
105#define BRCMF_TXBOUND 20 /* Default for max tx frames in
106 one scheduling */
107
108#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
109
110#define MEMBLOCK 2048 /* Block size used for downloading
111 of dongle image */
112#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
113 biggest possible glom */
114
115#define BRCMF_FIRSTREAD (1 << 6)
116
117
118/* SBSDIO_DEVICE_CTL */
119
120/* 1: device will assert busy signal when receiving CMD53 */
121#define SBSDIO_DEVCTL_SETBUSY 0x01
122/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
123#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
124/* 1: mask all interrupts to host except the chipActive (rev 8) */
125#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
126/* 1: isolate internal sdio signals, put external pads in tri-state; requires
127 * sdio bus power cycle to clear (rev 9) */
128#define SBSDIO_DEVCTL_PADS_ISO 0x08
129/* Force SD->SB reset mapping (rev 11) */
130#define SBSDIO_DEVCTL_SB_RST_CTL 0x30
131/* Determined by CoreControl bit */
132#define SBSDIO_DEVCTL_RST_CORECTL 0x00
133/* Force backplane reset */
134#define SBSDIO_DEVCTL_RST_BPRESET 0x10
135/* Force no backplane reset */
136#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
137
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138/* direct(mapped) cis space */
139
140/* MAPPED common CIS address */
141#define SBSDIO_CIS_BASE_COMMON 0x1000
142/* maximum bytes in one CIS */
143#define SBSDIO_CIS_SIZE_LIMIT 0x200
144/* cis offset addr is < 17 bits */
145#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
146
147/* manfid tuple length, include tuple, link bytes */
148#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
149
150/* intstatus */
151#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
152#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
153#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
154#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
155#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
156#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
157#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
158#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
159#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
160#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
161#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
162#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
163#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
164#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
165#define I_PC (1 << 10) /* descriptor error */
166#define I_PD (1 << 11) /* data error */
167#define I_DE (1 << 12) /* Descriptor protocol Error */
168#define I_RU (1 << 13) /* Receive descriptor Underflow */
169#define I_RO (1 << 14) /* Receive fifo Overflow */
170#define I_XU (1 << 15) /* Transmit fifo Underflow */
171#define I_RI (1 << 16) /* Receive Interrupt */
172#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
173#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
174#define I_XI (1 << 24) /* Transmit Interrupt */
175#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
176#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
177#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
178#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
179#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
180#define I_SRESET (1 << 30) /* CCCR RES interrupt */
181#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
182#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
183#define I_DMA (I_RI | I_XI | I_ERRORS)
184
185/* corecontrol */
186#define CC_CISRDY (1 << 0) /* CIS Ready */
187#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
188#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
189#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
190#define CC_XMTDATAAVAIL_MODE (1 << 4)
191#define CC_XMTDATAAVAIL_CTRL (1 << 5)
192
193/* SDA_FRAMECTRL */
194#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
195#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
196#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
197#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
198
199/* HW frame tag */
200#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
201
202/* Total length of frame header for dongle protocol */
203#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
204#define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
205
206/*
207 * Software allocation of To SB Mailbox resources
208 */
209
210/* tosbmailbox bits corresponding to intstatus bits */
211#define SMB_NAK (1 << 0) /* Frame NAK */
212#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
213#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
214#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
215
216/* tosbmailboxdata */
217#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
218
219/*
220 * Software allocation of To Host Mailbox resources
221 */
222
223/* intstatus bits */
224#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
225#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
226#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
227#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
228
229/* tohostmailboxdata */
230#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
231#define HMB_DATA_DEVREADY 2 /* talk to host after enable */
232#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
233#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
234
235#define HMB_DATA_FCDATA_MASK 0xff000000
236#define HMB_DATA_FCDATA_SHIFT 24
237
238#define HMB_DATA_VERSION_MASK 0x00ff0000
239#define HMB_DATA_VERSION_SHIFT 16
240
241/*
242 * Software-defined protocol header
243 */
244
245/* Current protocol version */
246#define SDPCM_PROT_VERSION 4
247
248/* SW frame header */
249#define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
250
251#define SDPCM_CHANNEL_MASK 0x00000f00
252#define SDPCM_CHANNEL_SHIFT 8
253#define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
254
255#define SDPCM_NEXTLEN_OFFSET 2
256
257/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
258#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
259#define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
260#define SDPCM_DOFFSET_MASK 0xff000000
261#define SDPCM_DOFFSET_SHIFT 24
262#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
263#define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
264#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
265#define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
266
267#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
268
269/* logical channel numbers */
270#define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
271#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
272#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
273#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
274#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
275
276#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
277
278#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
279
280/*
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
283 */
284#define SDPCM_SHARED_VERSION 0x0002
285#define SDPCM_SHARED_VERSION_MASK 0x00FF
286#define SDPCM_SHARED_ASSERT_BUILT 0x0100
287#define SDPCM_SHARED_ASSERT 0x0200
288#define SDPCM_SHARED_TRAP 0x0400
289
290/* Space for header read, limit for data packets */
291#define MAX_HDR_READ (1 << 6)
292#define MAX_RX_DATASZ 2048
293
294/* Maximum milliseconds to wait for F2 to come up */
295#define BRCMF_WAIT_F2RDY 3000
296
297/* Bump up limit on waiting for HT to account for first startup;
298 * if the image is doing a CRC calculation before programming the PMU
299 * for HT availability, it could take a couple hundred ms more, so
300 * max out at a 1 second (1000000us).
301 */
302#undef PMU_MAX_TRANSITION_DLY
303#define PMU_MAX_TRANSITION_DLY 1000000
304
305/* Value for ChipClockCSR during initial setup */
306#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
307 SBSDIO_ALP_AVAIL_REQ)
308
309/* Flags for SDH calls */
310#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
311
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312#define BRCMFMAC_FW_NAME "brcm/brcmfmac.bin"
313#define BRCMFMAC_NV_NAME "brcm/brcmfmac.txt"
314MODULE_FIRMWARE(BRCMFMAC_FW_NAME);
315MODULE_FIRMWARE(BRCMFMAC_NV_NAME);
316
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317/*
318 * Conversion of 802.1D priority to precedence level
319 */
320static uint prio2prec(u32 prio)
321{
322 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
323 (prio^2) : prio;
324}
325
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326/* core registers */
327struct sdpcmd_regs {
328 u32 corecontrol; /* 0x00, rev8 */
329 u32 corestatus; /* rev8 */
330 u32 PAD[1];
331 u32 biststatus; /* rev8 */
332
333 /* PCMCIA access */
334 u16 pcmciamesportaladdr; /* 0x010, rev8 */
335 u16 PAD[1];
336 u16 pcmciamesportalmask; /* rev8 */
337 u16 PAD[1];
338 u16 pcmciawrframebc; /* rev8 */
339 u16 PAD[1];
340 u16 pcmciaunderflowtimer; /* rev8 */
341 u16 PAD[1];
342
343 /* interrupt */
344 u32 intstatus; /* 0x020, rev8 */
345 u32 hostintmask; /* rev8 */
346 u32 intmask; /* rev8 */
347 u32 sbintstatus; /* rev8 */
348 u32 sbintmask; /* rev8 */
349 u32 funcintmask; /* rev4 */
350 u32 PAD[2];
351 u32 tosbmailbox; /* 0x040, rev8 */
352 u32 tohostmailbox; /* rev8 */
353 u32 tosbmailboxdata; /* rev8 */
354 u32 tohostmailboxdata; /* rev8 */
355
356 /* synchronized access to registers in SDIO clock domain */
357 u32 sdioaccess; /* 0x050, rev8 */
358 u32 PAD[3];
359
360 /* PCMCIA frame control */
361 u8 pcmciaframectrl; /* 0x060, rev8 */
362 u8 PAD[3];
363 u8 pcmciawatermark; /* rev8 */
364 u8 PAD[155];
365
366 /* interrupt batching control */
367 u32 intrcvlazy; /* 0x100, rev8 */
368 u32 PAD[3];
369
370 /* counters */
371 u32 cmd52rd; /* 0x110, rev8 */
372 u32 cmd52wr; /* rev8 */
373 u32 cmd53rd; /* rev8 */
374 u32 cmd53wr; /* rev8 */
375 u32 abort; /* rev8 */
376 u32 datacrcerror; /* rev8 */
377 u32 rdoutofsync; /* rev8 */
378 u32 wroutofsync; /* rev8 */
379 u32 writebusy; /* rev8 */
380 u32 readwait; /* rev8 */
381 u32 readterm; /* rev8 */
382 u32 writeterm; /* rev8 */
383 u32 PAD[40];
384 u32 clockctlstatus; /* rev8 */
385 u32 PAD[7];
386
387 u32 PAD[128]; /* DMA engines */
388
389 /* SDIO/PCMCIA CIS region */
390 char cis[512]; /* 0x400-0x5ff, rev6 */
391
392 /* PCMCIA function control registers */
393 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
394 u16 PAD[55];
395
396 /* PCMCIA backplane access */
397 u16 backplanecsr; /* 0x76E, rev6 */
398 u16 backplaneaddr0; /* rev6 */
399 u16 backplaneaddr1; /* rev6 */
400 u16 backplaneaddr2; /* rev6 */
401 u16 backplaneaddr3; /* rev6 */
402 u16 backplanedata0; /* rev6 */
403 u16 backplanedata1; /* rev6 */
404 u16 backplanedata2; /* rev6 */
405 u16 backplanedata3; /* rev6 */
406 u16 PAD[31];
407
408 /* sprom "size" & "blank" info */
409 u16 spromstatus; /* 0x7BE, rev2 */
410 u32 PAD[464];
411
412 u16 PAD[0x80];
413};
414
415#ifdef BCMDBG
416/* Device console log buffer state */
417struct brcmf_console {
418 uint count; /* Poll interval msec counter */
419 uint log_addr; /* Log struct address (fixed) */
420 struct rte_log_le log_le; /* Log struct (host copy) */
421 uint bufsize; /* Size of log buffer */
422 u8 *buf; /* Log buffer (host copy) */
423 uint last; /* Last buffer read index */
424};
425#endif /* BCMDBG */
426
427struct sdpcm_shared {
428 u32 flags;
429 u32 trap_addr;
430 u32 assert_exp_addr;
431 u32 assert_file_addr;
432 u32 assert_line;
433 u32 console_addr; /* Address of struct rte_console */
434 u32 msgtrace_addr;
435 u8 tag[32];
436};
437
438struct sdpcm_shared_le {
439 __le32 flags;
440 __le32 trap_addr;
441 __le32 assert_exp_addr;
442 __le32 assert_file_addr;
443 __le32 assert_line;
444 __le32 console_addr; /* Address of struct rte_console */
445 __le32 msgtrace_addr;
446 u8 tag[32];
447};
448
449
450/* misc chip info needed by some of the routines */
5b435de0 451/* Private data for SDIO bus interaction */
e92eedf4 452struct brcmf_sdio {
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453 struct brcmf_pub *drvr;
454
455 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
456 struct chip_info *ci; /* Chip info struct */
457 char *vars; /* Variables (from CIS and/or other) */
458 uint varsz; /* Size of variables buffer */
459
460 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
461
462 u32 hostintmask; /* Copy of Host Interrupt Mask */
463 u32 intstatus; /* Intstatus bits (events) pending */
464 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
465 bool fcstate; /* State of dongle flow-control */
466
467 uint blocksize; /* Block size of SDIO transfers */
468 uint roundup; /* Max roundup limit */
469
470 struct pktq txq; /* Queue length used for flow-control */
471 u8 flowcontrol; /* per prio flow control bitmask */
472 u8 tx_seq; /* Transmit sequence number (next) */
473 u8 tx_max; /* Maximum transmit sequence allowed */
474
475 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
476 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
477 u16 nextlen; /* Next Read Len from last header */
478 u8 rx_seq; /* Receive sequence number (expected) */
479 bool rxskip; /* Skip receive (awaiting NAK ACK) */
480
481 uint rxbound; /* Rx frames to read before resched */
482 uint txbound; /* Tx frames to send before resched */
483 uint txminmax;
484
485 struct sk_buff *glomd; /* Packet containing glomming descriptor */
b83db862 486 struct sk_buff_head glom; /* Packet list for glommed superframe */
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487 uint glomerr; /* Glom packet read errors */
488
489 u8 *rxbuf; /* Buffer for receiving control packets */
490 uint rxblen; /* Allocated length of rxbuf */
491 u8 *rxctl; /* Aligned pointer into rxbuf */
492 u8 *databuf; /* Buffer for receiving big glom packet */
493 u8 *dataptr; /* Aligned pointer into databuf */
494 uint rxlen; /* Length of valid data in buffer */
495
496 u8 sdpcm_ver; /* Bus protocol reported by dongle */
497
498 bool intr; /* Use interrupts */
499 bool poll; /* Use polling */
500 bool ipend; /* Device interrupt is pending */
501 uint intrcount; /* Count of device interrupt callbacks */
502 uint lastintrs; /* Count as of last watchdog timer */
503 uint spurious; /* Count of spurious interrupts */
504 uint pollrate; /* Ticks between device polls */
505 uint polltick; /* Tick counter */
506 uint pollcnt; /* Count of active polls */
507
508#ifdef BCMDBG
509 uint console_interval;
510 struct brcmf_console console; /* Console output polling support */
511 uint console_addr; /* Console address from shared struct */
512#endif /* BCMDBG */
513
514 uint regfails; /* Count of R_REG failures */
515
516 uint clkstate; /* State of sd and backplane clock(s) */
517 bool activity; /* Activity flag for clock down */
518 s32 idletime; /* Control for activity timeout */
519 s32 idlecount; /* Activity timeout counter */
520 s32 idleclock; /* How to set bus driver when idle */
521 s32 sd_rxchain;
522 bool use_rxchain; /* If brcmf should use PKT chains */
523 bool sleeping; /* Is SDIO bus sleeping? */
524 bool rxflow_mode; /* Rx flow control mode */
525 bool rxflow; /* Is rx flow control on */
526 bool alp_only; /* Don't use HT clock (ALP only) */
527/* Field to decide if rx of control frames happen in rxbuf or lb-pool */
528 bool usebufpool;
529
530 /* Some additional counters */
531 uint tx_sderrs; /* Count of tx attempts with sd errors */
532 uint fcqueued; /* Tx packets that got queued */
533 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
534 uint rx_toolong; /* Receive frames too long to receive */
535 uint rxc_errors; /* SDIO errors when reading control frames */
536 uint rx_hdrfail; /* SDIO errors on header reads */
537 uint rx_badhdr; /* Bad received headers (roosync?) */
538 uint rx_badseq; /* Mismatched rx sequence number */
539 uint fc_rcvd; /* Number of flow-control events received */
540 uint fc_xoff; /* Number which turned on flow-control */
541 uint fc_xon; /* Number which turned off flow-control */
542 uint rxglomfail; /* Failed deglom attempts */
543 uint rxglomframes; /* Number of glom frames (superframes) */
544 uint rxglompkts; /* Number of packets from glom frames */
545 uint f2rxhdrs; /* Number of header reads */
546 uint f2rxdata; /* Number of frame data reads */
547 uint f2txdata; /* Number of f2 frame writes */
548 uint f1regdata; /* Number of f1 register accesses */
549
550 u8 *ctrl_frame_buf;
551 u32 ctrl_frame_len;
552 bool ctrl_frame_stat;
553
554 spinlock_t txqlock;
555 wait_queue_head_t ctrl_wait;
556 wait_queue_head_t dcmd_resp_wait;
557
558 struct timer_list timer;
559 struct completion watchdog_wait;
560 struct task_struct *watchdog_tsk;
561 bool wd_timer_valid;
562 uint save_ms;
563
564 struct task_struct *dpc_tsk;
565 struct completion dpc_wait;
566
567 struct semaphore sdsem;
568
5b435de0 569 const struct firmware *firmware;
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570 u32 fw_ptr;
571};
572
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573/* clkstate */
574#define CLK_NONE 0
575#define CLK_SDONLY 1
576#define CLK_PENDING 2 /* Not used yet */
577#define CLK_AVAIL 3
578
579#ifdef BCMDBG
580static int qcount[NUMPRIO];
581static int tx_packets[NUMPRIO];
582#endif /* BCMDBG */
583
584#define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
585
586#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
587
588/* Retry count for register access failures */
589static const uint retry_limit = 2;
590
591/* Limit on rounding up frames */
592static const uint max_roundup = 512;
593
594#define ALIGNMENT 4
595
596static void pkt_align(struct sk_buff *p, int len, int align)
597{
598 uint datalign;
599 datalign = (unsigned long)(p->data);
600 datalign = roundup(datalign, (align)) - datalign;
601 if (datalign)
602 skb_pull(p, datalign);
603 __skb_trim(p, len);
604}
605
606/* To check if there's window offered */
e92eedf4 607static bool data_ok(struct brcmf_sdio *bus)
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AS
608{
609 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
610 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
611}
612
613/*
614 * Reads a register in the SDIO hardware block. This block occupies a series of
615 * adresses on the 32 bit backplane bus.
616 */
617static void
e92eedf4 618r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
5b435de0 619{
99ba15cd 620 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
5b435de0
AS
621 *retryvar = 0;
622 do {
623 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
99ba15cd
FL
624 bus->ci->c_inf[idx].base + reg_offset,
625 sizeof(u32));
5b435de0
AS
626 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
627 (++(*retryvar) <= retry_limit));
628 if (*retryvar) {
629 bus->regfails += (*retryvar-1);
630 if (*retryvar > retry_limit) {
631 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
632 *regvar = 0;
633 }
634 }
635}
636
637static void
e92eedf4 638w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset, u32 *retryvar)
5b435de0 639{
99ba15cd 640 u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
5b435de0
AS
641 *retryvar = 0;
642 do {
643 brcmf_sdcard_reg_write(bus->sdiodev,
99ba15cd 644 bus->ci->c_inf[idx].base + reg_offset,
5b435de0
AS
645 sizeof(u32), regval);
646 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
647 (++(*retryvar) <= retry_limit));
648 if (*retryvar) {
649 bus->regfails += (*retryvar-1);
650 if (*retryvar > retry_limit)
651 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
652 reg_offset);
653 }
654}
655
656#define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
657
658#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
659
660/* Packet free applicable unconditionally for sdio and sdspi.
661 * Conditional if bufpool was present for gspi bus.
662 */
e92eedf4 663static void brcmf_sdbrcm_pktfree2(struct brcmf_sdio *bus, struct sk_buff *pkt)
5b435de0
AS
664{
665 if (bus->usebufpool)
666 brcmu_pkt_buf_free_skb(pkt);
667}
668
669/* Turn backplane clock on or off */
e92eedf4 670static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
5b435de0
AS
671{
672 int err;
673 u8 clkctl, clkreq, devctl;
674 unsigned long timeout;
675
676 brcmf_dbg(TRACE, "Enter\n");
677
678 clkctl = 0;
679
680 if (on) {
681 /* Request HT Avail */
682 clkreq =
683 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
684
5b435de0
AS
685 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
686 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
687 if (err) {
688 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
689 return -EBADE;
690 }
691
5b435de0
AS
692 /* Check current status */
693 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
694 SBSDIO_FUNC1_CHIPCLKCSR, &err);
695 if (err) {
696 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
697 return -EBADE;
698 }
699
700 /* Go to pending and await interrupt if appropriate */
701 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
702 /* Allow only clock-available interrupt */
703 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
704 SDIO_FUNC_1,
705 SBSDIO_DEVICE_CTL, &err);
706 if (err) {
707 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
708 err);
709 return -EBADE;
710 }
711
712 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
713 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
714 SBSDIO_DEVICE_CTL, devctl, &err);
715 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
716 bus->clkstate = CLK_PENDING;
717
718 return 0;
719 } else if (bus->clkstate == CLK_PENDING) {
720 /* Cancel CA-only interrupt filter */
721 devctl =
722 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
723 SBSDIO_DEVICE_CTL, &err);
724 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
725 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
726 SBSDIO_DEVICE_CTL, devctl, &err);
727 }
728
729 /* Otherwise, wait here (polling) for HT Avail */
730 timeout = jiffies +
731 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
732 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
733 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
734 SDIO_FUNC_1,
735 SBSDIO_FUNC1_CHIPCLKCSR,
736 &err);
737 if (time_after(jiffies, timeout))
738 break;
739 else
740 usleep_range(5000, 10000);
741 }
742 if (err) {
743 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
744 return -EBADE;
745 }
746 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
747 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
748 PMU_MAX_TRANSITION_DLY, clkctl);
749 return -EBADE;
750 }
751
752 /* Mark clock available */
753 bus->clkstate = CLK_AVAIL;
754 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
755
756#if defined(BCMDBG)
757 if (bus->alp_only != true) {
758 if (SBSDIO_ALPONLY(clkctl))
759 brcmf_dbg(ERROR, "HT Clock should be on\n");
760 }
761#endif /* defined (BCMDBG) */
762
763 bus->activity = true;
764 } else {
765 clkreq = 0;
766
767 if (bus->clkstate == CLK_PENDING) {
768 /* Cancel CA-only interrupt filter */
769 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
770 SDIO_FUNC_1,
771 SBSDIO_DEVICE_CTL, &err);
772 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
773 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
774 SBSDIO_DEVICE_CTL, devctl, &err);
775 }
776
777 bus->clkstate = CLK_SDONLY;
778 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
779 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
780 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
781 if (err) {
782 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
783 err);
784 return -EBADE;
785 }
786 }
787 return 0;
788}
789
790/* Change idle/active SD state */
e92eedf4 791static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
5b435de0
AS
792{
793 brcmf_dbg(TRACE, "Enter\n");
794
795 if (on)
796 bus->clkstate = CLK_SDONLY;
797 else
798 bus->clkstate = CLK_NONE;
799
800 return 0;
801}
802
803/* Transition SD and backplane clock readiness */
e92eedf4 804static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
5b435de0
AS
805{
806#ifdef BCMDBG
807 uint oldstate = bus->clkstate;
808#endif /* BCMDBG */
809
810 brcmf_dbg(TRACE, "Enter\n");
811
812 /* Early exit if we're already there */
813 if (bus->clkstate == target) {
814 if (target == CLK_AVAIL) {
815 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
816 bus->activity = true;
817 }
818 return 0;
819 }
820
821 switch (target) {
822 case CLK_AVAIL:
823 /* Make sure SD clock is available */
824 if (bus->clkstate == CLK_NONE)
825 brcmf_sdbrcm_sdclk(bus, true);
826 /* Now request HT Avail on the backplane */
827 brcmf_sdbrcm_htclk(bus, true, pendok);
828 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
829 bus->activity = true;
830 break;
831
832 case CLK_SDONLY:
833 /* Remove HT request, or bring up SD clock */
834 if (bus->clkstate == CLK_NONE)
835 brcmf_sdbrcm_sdclk(bus, true);
836 else if (bus->clkstate == CLK_AVAIL)
837 brcmf_sdbrcm_htclk(bus, false, false);
838 else
839 brcmf_dbg(ERROR, "request for %d -> %d\n",
840 bus->clkstate, target);
841 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
842 break;
843
844 case CLK_NONE:
845 /* Make sure to remove HT request */
846 if (bus->clkstate == CLK_AVAIL)
847 brcmf_sdbrcm_htclk(bus, false, false);
848 /* Now remove the SD clock */
849 brcmf_sdbrcm_sdclk(bus, false);
850 brcmf_sdbrcm_wd_timer(bus, 0);
851 break;
852 }
853#ifdef BCMDBG
854 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
855#endif /* BCMDBG */
856
857 return 0;
858}
859
e92eedf4 860static int brcmf_sdbrcm_bussleep(struct brcmf_sdio *bus, bool sleep)
5b435de0
AS
861{
862 uint retries = 0;
863
864 brcmf_dbg(INFO, "request %s (currently %s)\n",
865 sleep ? "SLEEP" : "WAKE",
866 bus->sleeping ? "SLEEP" : "WAKE");
867
868 /* Done if we're already in the requested state */
869 if (sleep == bus->sleeping)
870 return 0;
871
872 /* Going to sleep: set the alarm and turn off the lights... */
873 if (sleep) {
874 /* Don't sleep if something is pending */
875 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
876 return -EBUSY;
877
878 /* Make sure the controller has the bus up */
879 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
880
881 /* Tell device to start using OOB wakeup */
882 w_sdreg32(bus, SMB_USE_OOB,
883 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
884 if (retries > retry_limit)
885 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
886
887 /* Turn off our contribution to the HT clock request */
888 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
889
890 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
891 SBSDIO_FUNC1_CHIPCLKCSR,
892 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
893
894 /* Isolate the bus */
718897eb
FL
895 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
896 SBSDIO_DEVICE_CTL,
897 SBSDIO_DEVCTL_PADS_ISO, NULL);
5b435de0
AS
898
899 /* Change state */
900 bus->sleeping = true;
901
902 } else {
903 /* Waking up: bus power up is ok, set local state */
904
905 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
906 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
907
5b435de0
AS
908 /* Make sure the controller has the bus up */
909 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
910
911 /* Send misc interrupt to indicate OOB not needed */
912 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
913 &retries);
914 if (retries <= retry_limit)
915 w_sdreg32(bus, SMB_DEV_INT,
916 offsetof(struct sdpcmd_regs, tosbmailbox),
917 &retries);
918
919 if (retries > retry_limit)
920 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
921
922 /* Make sure we have SD bus access */
923 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
924
925 /* Change state */
926 bus->sleeping = false;
927 }
928
929 return 0;
930}
931
e92eedf4 932static void bus_wake(struct brcmf_sdio *bus)
5b435de0
AS
933{
934 if (bus->sleeping)
935 brcmf_sdbrcm_bussleep(bus, false);
936}
937
e92eedf4 938static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus)
5b435de0
AS
939{
940 u32 intstatus = 0;
941 u32 hmb_data;
942 u8 fcbits;
943 uint retries = 0;
944
945 brcmf_dbg(TRACE, "Enter\n");
946
947 /* Read mailbox data and ack that we did so */
948 r_sdreg32(bus, &hmb_data,
949 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
950
951 if (retries <= retry_limit)
952 w_sdreg32(bus, SMB_INT_ACK,
953 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
954 bus->f1regdata += 2;
955
956 /* Dongle recomposed rx frames, accept them again */
957 if (hmb_data & HMB_DATA_NAKHANDLED) {
958 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
959 bus->rx_seq);
960 if (!bus->rxskip)
961 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
962
963 bus->rxskip = false;
964 intstatus |= I_HMB_FRAME_IND;
965 }
966
967 /*
968 * DEVREADY does not occur with gSPI.
969 */
970 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
971 bus->sdpcm_ver =
972 (hmb_data & HMB_DATA_VERSION_MASK) >>
973 HMB_DATA_VERSION_SHIFT;
974 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
975 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
976 "expecting %d\n",
977 bus->sdpcm_ver, SDPCM_PROT_VERSION);
978 else
979 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
980 bus->sdpcm_ver);
981 }
982
983 /*
984 * Flow Control has been moved into the RX headers and this out of band
985 * method isn't used any more.
986 * remaining backward compatible with older dongles.
987 */
988 if (hmb_data & HMB_DATA_FC) {
989 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
990 HMB_DATA_FCDATA_SHIFT;
991
992 if (fcbits & ~bus->flowcontrol)
993 bus->fc_xoff++;
994
995 if (bus->flowcontrol & ~fcbits)
996 bus->fc_xon++;
997
998 bus->fc_rcvd++;
999 bus->flowcontrol = fcbits;
1000 }
1001
1002 /* Shouldn't be any others */
1003 if (hmb_data & ~(HMB_DATA_DEVREADY |
1004 HMB_DATA_NAKHANDLED |
1005 HMB_DATA_FC |
1006 HMB_DATA_FWREADY |
1007 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1008 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1009 hmb_data);
1010
1011 return intstatus;
1012}
1013
e92eedf4 1014static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
5b435de0
AS
1015{
1016 uint retries = 0;
1017 u16 lastrbc;
1018 u8 hi, lo;
1019 int err;
1020
1021 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1022 abort ? "abort command, " : "",
1023 rtx ? ", send NAK" : "");
1024
1025 if (abort)
1026 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1027
1028 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1029 SBSDIO_FUNC1_FRAMECTRL,
1030 SFC_RF_TERM, &err);
1031 bus->f1regdata++;
1032
1033 /* Wait until the packet has been flushed (device/FIFO stable) */
1034 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1035 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1036 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1037 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1038 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1039 bus->f1regdata += 2;
1040
1041 if ((hi == 0) && (lo == 0))
1042 break;
1043
1044 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1045 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1046 lastrbc, (hi << 8) + lo);
1047 }
1048 lastrbc = (hi << 8) + lo;
1049 }
1050
1051 if (!retries)
1052 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1053 else
1054 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1055
1056 if (rtx) {
1057 bus->rxrtx++;
1058 w_sdreg32(bus, SMB_NAK,
1059 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1060
1061 bus->f1regdata++;
1062 if (retries <= retry_limit)
1063 bus->rxskip = true;
1064 }
1065
1066 /* Clear partial in any case */
1067 bus->nextlen = 0;
1068
1069 /* If we can't reach the device, signal failure */
1070 if (err || brcmf_sdcard_regfail(bus->sdiodev))
8d169aa0 1071 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
1072}
1073
20e5ca16 1074/* copy a buffer into a pkt buffer chain */
e92eedf4 1075static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_sdio *bus, uint len)
20e5ca16
AS
1076{
1077 uint n, ret = 0;
1078 struct sk_buff *p;
1079 u8 *buf;
1080
20e5ca16
AS
1081 buf = bus->dataptr;
1082
1083 /* copy the data */
b83db862 1084 skb_queue_walk(&bus->glom, p) {
20e5ca16
AS
1085 n = min_t(uint, p->len, len);
1086 memcpy(p->data, buf, n);
1087 buf += n;
1088 len -= n;
1089 ret += n;
b83db862
AS
1090 if (!len)
1091 break;
20e5ca16
AS
1092 }
1093
1094 return ret;
1095}
1096
9a95e60e 1097/* return total length of buffer chain */
e92eedf4 1098static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus)
9a95e60e
AS
1099{
1100 struct sk_buff *p;
1101 uint total;
1102
1103 total = 0;
1104 skb_queue_walk(&bus->glom, p)
1105 total += p->len;
1106 return total;
1107}
1108
e92eedf4 1109static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus)
046808da
AS
1110{
1111 struct sk_buff *cur, *next;
1112
1113 skb_queue_walk_safe(&bus->glom, cur, next) {
1114 skb_unlink(cur, &bus->glom);
1115 brcmu_pkt_buf_free_skb(cur);
1116 }
1117}
1118
e92eedf4 1119static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
5b435de0
AS
1120{
1121 u16 dlen, totlen;
1122 u8 *dptr, num = 0;
1123
1124 u16 sublen, check;
0b45bf74 1125 struct sk_buff *pfirst, *pnext;
5b435de0
AS
1126
1127 int errcode;
1128 u8 chan, seq, doff, sfdoff;
1129 u8 txmax;
1130
1131 int ifidx = 0;
1132 bool usechain = bus->use_rxchain;
1133
1134 /* If packets, issue read(s) and send up packet chain */
1135 /* Return sequence numbers consumed? */
1136
b83db862
AS
1137 brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
1138 bus->glomd, skb_peek(&bus->glom));
5b435de0
AS
1139
1140 /* If there's a descriptor, generate the packet chain */
1141 if (bus->glomd) {
0b45bf74 1142 pfirst = pnext = NULL;
5b435de0
AS
1143 dlen = (u16) (bus->glomd->len);
1144 dptr = bus->glomd->data;
1145 if (!dlen || (dlen & 1)) {
1146 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1147 dlen);
1148 dlen = 0;
1149 }
1150
1151 for (totlen = num = 0; dlen; num++) {
1152 /* Get (and move past) next length */
1153 sublen = get_unaligned_le16(dptr);
1154 dlen -= sizeof(u16);
1155 dptr += sizeof(u16);
1156 if ((sublen < SDPCM_HDRLEN) ||
1157 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1158 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1159 num, sublen);
1160 pnext = NULL;
1161 break;
1162 }
1163 if (sublen % BRCMF_SDALIGN) {
1164 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1165 sublen, BRCMF_SDALIGN);
1166 usechain = false;
1167 }
1168 totlen += sublen;
1169
1170 /* For last frame, adjust read len so total
1171 is a block multiple */
1172 if (!dlen) {
1173 sublen +=
1174 (roundup(totlen, bus->blocksize) - totlen);
1175 totlen = roundup(totlen, bus->blocksize);
1176 }
1177
1178 /* Allocate/chain packet for next subframe */
1179 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1180 if (pnext == NULL) {
1181 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1182 num, sublen);
1183 break;
1184 }
b83db862 1185 skb_queue_tail(&bus->glom, pnext);
5b435de0
AS
1186
1187 /* Adhere to start alignment requirements */
1188 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1189 }
1190
1191 /* If all allocations succeeded, save packet chain
1192 in bus structure */
1193 if (pnext) {
1194 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1195 totlen, num);
1196 if (BRCMF_GLOM_ON() && bus->nextlen &&
1197 totlen != bus->nextlen) {
1198 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1199 bus->nextlen, totlen, rxseq);
1200 }
5b435de0
AS
1201 pfirst = pnext = NULL;
1202 } else {
046808da 1203 brcmf_sdbrcm_free_glom(bus);
5b435de0
AS
1204 num = 0;
1205 }
1206
1207 /* Done with descriptor packet */
1208 brcmu_pkt_buf_free_skb(bus->glomd);
1209 bus->glomd = NULL;
1210 bus->nextlen = 0;
1211 }
1212
1213 /* Ok -- either we just generated a packet chain,
1214 or had one from before */
b83db862 1215 if (!skb_queue_empty(&bus->glom)) {
5b435de0
AS
1216 if (BRCMF_GLOM_ON()) {
1217 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
b83db862 1218 skb_queue_walk(&bus->glom, pnext) {
5b435de0
AS
1219 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1220 pnext, (u8 *) (pnext->data),
1221 pnext->len, pnext->len);
1222 }
1223 }
1224
b83db862 1225 pfirst = skb_peek(&bus->glom);
9a95e60e 1226 dlen = (u16) brcmf_sdbrcm_glom_len(bus);
5b435de0
AS
1227
1228 /* Do an SDIO read for the superframe. Configurable iovar to
1229 * read directly into the chained packet, or allocate a large
1230 * packet and and copy into the chain.
1231 */
1232 if (usechain) {
5adfeb63 1233 errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
5b435de0 1234 bus->sdiodev->sbwad,
5adfeb63 1235 SDIO_FUNC_2, F2SYNC, &bus->glom);
5b435de0
AS
1236 } else if (bus->dataptr) {
1237 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1238 bus->sdiodev->sbwad,
5adfeb63
AS
1239 SDIO_FUNC_2, F2SYNC,
1240 bus->dataptr, dlen);
20e5ca16 1241 sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
5b435de0
AS
1242 if (sublen != dlen) {
1243 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1244 dlen, sublen);
1245 errcode = -1;
1246 }
1247 pnext = NULL;
1248 } else {
1249 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1250 dlen);
1251 errcode = -1;
1252 }
1253 bus->f2rxdata++;
1254
1255 /* On failure, kill the superframe, allow a couple retries */
1256 if (errcode < 0) {
1257 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1258 dlen, errcode);
1259 bus->drvr->rx_errors++;
1260
1261 if (bus->glomerr++ < 3) {
1262 brcmf_sdbrcm_rxfail(bus, true, true);
1263 } else {
1264 bus->glomerr = 0;
1265 brcmf_sdbrcm_rxfail(bus, true, false);
5b435de0 1266 bus->rxglomfail++;
046808da 1267 brcmf_sdbrcm_free_glom(bus);
5b435de0
AS
1268 }
1269 return 0;
1270 }
1271#ifdef BCMDBG
1272 if (BRCMF_GLOM_ON()) {
1273 printk(KERN_DEBUG "SUPERFRAME:\n");
1274 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1275 pfirst->data, min_t(int, pfirst->len, 48));
1276 }
1277#endif
1278
1279 /* Validate the superframe header */
1280 dptr = (u8 *) (pfirst->data);
1281 sublen = get_unaligned_le16(dptr);
1282 check = get_unaligned_le16(dptr + sizeof(u16));
1283
1284 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1285 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1286 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1287 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1288 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1289 bus->nextlen, seq);
1290 bus->nextlen = 0;
1291 }
1292 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1293 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1294
1295 errcode = 0;
1296 if ((u16)~(sublen ^ check)) {
1297 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1298 sublen, check);
1299 errcode = -1;
1300 } else if (roundup(sublen, bus->blocksize) != dlen) {
1301 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1302 sublen, roundup(sublen, bus->blocksize),
1303 dlen);
1304 errcode = -1;
1305 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1306 SDPCM_GLOM_CHANNEL) {
1307 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1308 SDPCM_PACKET_CHANNEL(
1309 &dptr[SDPCM_FRAMETAG_LEN]));
1310 errcode = -1;
1311 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1312 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1313 errcode = -1;
1314 } else if ((doff < SDPCM_HDRLEN) ||
1315 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1316 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1317 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1318 errcode = -1;
1319 }
1320
1321 /* Check sequence number of superframe SW header */
1322 if (rxseq != seq) {
1323 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1324 seq, rxseq);
1325 bus->rx_badseq++;
1326 rxseq = seq;
1327 }
1328
1329 /* Check window for sanity */
1330 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1331 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1332 txmax, bus->tx_seq);
1333 txmax = bus->tx_seq + 2;
1334 }
1335 bus->tx_max = txmax;
1336
1337 /* Remove superframe header, remember offset */
1338 skb_pull(pfirst, doff);
1339 sfdoff = doff;
0b45bf74 1340 num = 0;
5b435de0
AS
1341
1342 /* Validate all the subframe headers */
0b45bf74
AS
1343 skb_queue_walk(&bus->glom, pnext) {
1344 /* leave when invalid subframe is found */
1345 if (errcode)
1346 break;
1347
5b435de0
AS
1348 dptr = (u8 *) (pnext->data);
1349 dlen = (u16) (pnext->len);
1350 sublen = get_unaligned_le16(dptr);
1351 check = get_unaligned_le16(dptr + sizeof(u16));
1352 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1353 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1354#ifdef BCMDBG
1355 if (BRCMF_GLOM_ON()) {
1356 printk(KERN_DEBUG "subframe:\n");
1357 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1358 dptr, 32);
1359 }
1360#endif
1361
1362 if ((u16)~(sublen ^ check)) {
1363 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1364 num, sublen, check);
1365 errcode = -1;
1366 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1367 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1368 num, sublen, dlen);
1369 errcode = -1;
1370 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1371 (chan != SDPCM_EVENT_CHANNEL)) {
1372 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1373 num, chan);
1374 errcode = -1;
1375 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1376 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1377 num, doff, sublen, SDPCM_HDRLEN);
1378 errcode = -1;
1379 }
0b45bf74
AS
1380 /* increase the subframe count */
1381 num++;
5b435de0
AS
1382 }
1383
1384 if (errcode) {
1385 /* Terminate frame on error, request
1386 a couple retries */
1387 if (bus->glomerr++ < 3) {
1388 /* Restore superframe header space */
1389 skb_push(pfirst, sfdoff);
1390 brcmf_sdbrcm_rxfail(bus, true, true);
1391 } else {
1392 bus->glomerr = 0;
1393 brcmf_sdbrcm_rxfail(bus, true, false);
5b435de0 1394 bus->rxglomfail++;
046808da 1395 brcmf_sdbrcm_free_glom(bus);
5b435de0
AS
1396 }
1397 bus->nextlen = 0;
1398 return 0;
1399 }
1400
1401 /* Basic SD framing looks ok - process each packet (header) */
5b435de0 1402
0b45bf74 1403 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
5b435de0
AS
1404 dptr = (u8 *) (pfirst->data);
1405 sublen = get_unaligned_le16(dptr);
1406 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1407 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1408 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1409
1410 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1411 num, pfirst, pfirst->data,
1412 pfirst->len, sublen, chan, seq);
1413
1414 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1415 chan == SDPCM_EVENT_CHANNEL */
1416
1417 if (rxseq != seq) {
1418 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1419 seq, rxseq);
1420 bus->rx_badseq++;
1421 rxseq = seq;
1422 }
0b45bf74
AS
1423 rxseq++;
1424
5b435de0
AS
1425#ifdef BCMDBG
1426 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1427 printk(KERN_DEBUG "Rx Subframe Data:\n");
1428 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1429 dptr, dlen);
1430 }
1431#endif
1432
1433 __skb_trim(pfirst, sublen);
1434 skb_pull(pfirst, doff);
1435
1436 if (pfirst->len == 0) {
0b45bf74 1437 skb_unlink(pfirst, &bus->glom);
5b435de0 1438 brcmu_pkt_buf_free_skb(pfirst);
5b435de0 1439 continue;
d5625ee6
FL
1440 } else if (brcmf_proto_hdrpull(bus->sdiodev->dev,
1441 &ifidx, pfirst) != 0) {
5b435de0
AS
1442 brcmf_dbg(ERROR, "rx protocol error\n");
1443 bus->drvr->rx_errors++;
0b45bf74 1444 skb_unlink(pfirst, &bus->glom);
5b435de0 1445 brcmu_pkt_buf_free_skb(pfirst);
5b435de0
AS
1446 continue;
1447 }
1448
5b435de0
AS
1449#ifdef BCMDBG
1450 if (BRCMF_GLOM_ON()) {
1451 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
0b45bf74 1452 bus->glom.qlen, pfirst, pfirst->data,
5b435de0
AS
1453 pfirst->len, pfirst->next,
1454 pfirst->prev);
1455 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1456 pfirst->data,
1457 min_t(int, pfirst->len, 32));
1458 }
1459#endif /* BCMDBG */
1460 }
0b45bf74
AS
1461 /* sent any remaining packets up */
1462 if (bus->glom.qlen) {
5b435de0 1463 up(&bus->sdsem);
228bb43d 1464 brcmf_rx_frame(bus->sdiodev->dev, ifidx, &bus->glom);
5b435de0
AS
1465 down(&bus->sdsem);
1466 }
1467
1468 bus->rxglomframes++;
0b45bf74 1469 bus->rxglompkts += bus->glom.qlen;
5b435de0
AS
1470 }
1471 return num;
1472}
1473
e92eedf4 1474static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
5b435de0
AS
1475 bool *pending)
1476{
1477 DECLARE_WAITQUEUE(wait, current);
1478 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1479
1480 /* Wait until control frame is available */
1481 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1482 set_current_state(TASK_INTERRUPTIBLE);
1483
1484 while (!(*condition) && (!signal_pending(current) && timeout))
1485 timeout = schedule_timeout(timeout);
1486
1487 if (signal_pending(current))
1488 *pending = true;
1489
1490 set_current_state(TASK_RUNNING);
1491 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1492
1493 return timeout;
1494}
1495
e92eedf4 1496static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus)
5b435de0
AS
1497{
1498 if (waitqueue_active(&bus->dcmd_resp_wait))
1499 wake_up_interruptible(&bus->dcmd_resp_wait);
1500
1501 return 0;
1502}
1503static void
e92eedf4 1504brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
5b435de0
AS
1505{
1506 uint rdlen, pad;
1507
1508 int sdret;
1509
1510 brcmf_dbg(TRACE, "Enter\n");
1511
1512 /* Set rxctl for frame (w/optional alignment) */
1513 bus->rxctl = bus->rxbuf;
1514 bus->rxctl += BRCMF_FIRSTREAD;
1515 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1516 if (pad)
1517 bus->rxctl += (BRCMF_SDALIGN - pad);
1518 bus->rxctl -= BRCMF_FIRSTREAD;
1519
1520 /* Copy the already-read portion over */
1521 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1522 if (len <= BRCMF_FIRSTREAD)
1523 goto gotpkt;
1524
1525 /* Raise rdlen to next SDIO block to avoid tail command */
1526 rdlen = len - BRCMF_FIRSTREAD;
1527 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1528 pad = bus->blocksize - (rdlen % bus->blocksize);
1529 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1530 ((len + pad) < bus->drvr->maxctl))
1531 rdlen += pad;
1532 } else if (rdlen % BRCMF_SDALIGN) {
1533 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1534 }
1535
1536 /* Satisfy length-alignment requirements */
1537 if (rdlen & (ALIGNMENT - 1))
1538 rdlen = roundup(rdlen, ALIGNMENT);
1539
1540 /* Drop if the read is too big or it exceeds our maximum */
1541 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1542 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1543 rdlen, bus->drvr->maxctl);
1544 bus->drvr->rx_errors++;
1545 brcmf_sdbrcm_rxfail(bus, false, false);
1546 goto done;
1547 }
1548
1549 if ((len - doff) > bus->drvr->maxctl) {
1550 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1551 len, len - doff, bus->drvr->maxctl);
1552 bus->drvr->rx_errors++;
1553 bus->rx_toolong++;
1554 brcmf_sdbrcm_rxfail(bus, false, false);
1555 goto done;
1556 }
1557
1558 /* Read remainder of frame body into the rxctl buffer */
1559 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1560 bus->sdiodev->sbwad,
1561 SDIO_FUNC_2,
5adfeb63 1562 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen);
5b435de0
AS
1563 bus->f2rxdata++;
1564
1565 /* Control frame failures need retransmission */
1566 if (sdret < 0) {
1567 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1568 rdlen, sdret);
1569 bus->rxc_errors++;
1570 brcmf_sdbrcm_rxfail(bus, true, true);
1571 goto done;
1572 }
1573
1574gotpkt:
1575
1576#ifdef BCMDBG
1577 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1578 printk(KERN_DEBUG "RxCtrl:\n");
1579 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1580 }
1581#endif
1582
1583 /* Point to valid data and indicate its length */
1584 bus->rxctl += doff;
1585 bus->rxlen = len - doff;
1586
1587done:
1588 /* Awake any waiters */
1589 brcmf_sdbrcm_dcmd_resp_wake(bus);
1590}
1591
1592/* Pad read to blocksize for efficiency */
e92eedf4 1593static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
5b435de0
AS
1594{
1595 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1596 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1597 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1598 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1599 *rdlen += *pad;
1600 } else if (*rdlen % BRCMF_SDALIGN) {
1601 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1602 }
1603}
1604
1605static void
e92eedf4 1606brcmf_alloc_pkt_and_read(struct brcmf_sdio *bus, u16 rdlen,
5b435de0
AS
1607 struct sk_buff **pkt, u8 **rxbuf)
1608{
1609 int sdret; /* Return code from calls */
1610
1611 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1612 if (*pkt == NULL)
1613 return;
1614
1615 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1616 *rxbuf = (u8 *) ((*pkt)->data);
1617 /* Read the entire frame */
5adfeb63
AS
1618 sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
1619 SDIO_FUNC_2, F2SYNC, *pkt);
5b435de0
AS
1620 bus->f2rxdata++;
1621
1622 if (sdret < 0) {
1623 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1624 rdlen, sdret);
1625 brcmu_pkt_buf_free_skb(*pkt);
1626 bus->drvr->rx_errors++;
1627 /* Force retry w/normal header read.
1628 * Don't attempt NAK for
1629 * gSPI
1630 */
1631 brcmf_sdbrcm_rxfail(bus, true, true);
1632 *pkt = NULL;
1633 }
1634}
1635
1636/* Checks the header */
1637static int
e92eedf4 1638brcmf_check_rxbuf(struct brcmf_sdio *bus, struct sk_buff *pkt, u8 *rxbuf,
5b435de0
AS
1639 u8 rxseq, u16 nextlen, u16 *len)
1640{
1641 u16 check;
1642 bool len_consistent; /* Result of comparing readahead len and
1643 len from hw-hdr */
1644
1645 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1646
1647 /* Extract hardware header fields */
1648 *len = get_unaligned_le16(bus->rxhdr);
1649 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1650
1651 /* All zeros means readahead info was bad */
1652 if (!(*len | check)) {
1653 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1654 goto fail;
1655 }
1656
1657 /* Validate check bytes */
1658 if ((u16)~(*len ^ check)) {
1659 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1660 nextlen, *len, check);
1661 bus->rx_badhdr++;
1662 brcmf_sdbrcm_rxfail(bus, false, false);
1663 goto fail;
1664 }
1665
1666 /* Validate frame length */
1667 if (*len < SDPCM_HDRLEN) {
1668 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1669 *len);
1670 goto fail;
1671 }
1672
1673 /* Check for consistency with readahead info */
1674 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1675 if (len_consistent) {
1676 /* Mismatch, force retry w/normal
1677 header (may be >4K) */
1678 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1679 nextlen, *len, roundup(*len, 16),
1680 rxseq);
1681 brcmf_sdbrcm_rxfail(bus, true, true);
1682 goto fail;
1683 }
1684
1685 return 0;
1686
1687fail:
1688 brcmf_sdbrcm_pktfree2(bus, pkt);
1689 return -EINVAL;
1690}
1691
1692/* Return true if there may be more frames to read */
1693static uint
e92eedf4 1694brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished)
5b435de0
AS
1695{
1696 u16 len, check; /* Extracted hardware header fields */
1697 u8 chan, seq, doff; /* Extracted software header fields */
1698 u8 fcbits; /* Extracted fcbits from software header */
1699
1700 struct sk_buff *pkt; /* Packet for event or data frames */
1701 u16 pad; /* Number of pad bytes to read */
1702 u16 rdlen; /* Total number of bytes to read */
1703 u8 rxseq; /* Next sequence number to expect */
1704 uint rxleft = 0; /* Remaining number of frames allowed */
1705 int sdret; /* Return code from calls */
1706 u8 txmax; /* Maximum tx sequence offered */
1707 u8 *rxbuf;
1708 int ifidx = 0;
1709 uint rxcount = 0; /* Total frames read */
1710
1711 brcmf_dbg(TRACE, "Enter\n");
1712
1713 /* Not finished unless we encounter no more frames indication */
1714 *finished = false;
1715
1716 for (rxseq = bus->rx_seq, rxleft = maxframes;
8d169aa0
FL
1717 !bus->rxskip && rxleft &&
1718 bus->drvr->bus_if->state != BRCMF_BUS_DOWN;
5b435de0
AS
1719 rxseq++, rxleft--) {
1720
1721 /* Handle glomming separately */
b83db862 1722 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
5b435de0
AS
1723 u8 cnt;
1724 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
b83db862 1725 bus->glomd, skb_peek(&bus->glom));
5b435de0
AS
1726 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1727 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1728 rxseq += cnt - 1;
1729 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1730 continue;
1731 }
1732
1733 /* Try doing single read if we can */
1734 if (bus->nextlen) {
1735 u16 nextlen = bus->nextlen;
1736 bus->nextlen = 0;
1737
1738 rdlen = len = nextlen << 4;
1739 brcmf_pad(bus, &pad, &rdlen);
1740
1741 /*
1742 * After the frame is received we have to
1743 * distinguish whether it is data
1744 * or non-data frame.
1745 */
1746 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1747 if (pkt == NULL) {
1748 /* Give up on data, request rtx of events */
1749 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1750 len, rdlen, rxseq);
1751 continue;
1752 }
1753
1754 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1755 &len) < 0)
1756 continue;
1757
1758 /* Extract software header fields */
1759 chan = SDPCM_PACKET_CHANNEL(
1760 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1761 seq = SDPCM_PACKET_SEQUENCE(
1762 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1763 doff = SDPCM_DOFFSET_VALUE(
1764 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1765 txmax = SDPCM_WINDOW_VALUE(
1766 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1767
1768 bus->nextlen =
1769 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1770 SDPCM_NEXTLEN_OFFSET];
1771 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1772 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1773 bus->nextlen, seq);
1774 bus->nextlen = 0;
1775 }
1776
1777 bus->drvr->rx_readahead_cnt++;
1778
1779 /* Handle Flow Control */
1780 fcbits = SDPCM_FCMASK_VALUE(
1781 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1782
1783 if (bus->flowcontrol != fcbits) {
1784 if (~bus->flowcontrol & fcbits)
1785 bus->fc_xoff++;
1786
1787 if (bus->flowcontrol & ~fcbits)
1788 bus->fc_xon++;
1789
1790 bus->fc_rcvd++;
1791 bus->flowcontrol = fcbits;
1792 }
1793
1794 /* Check and update sequence number */
1795 if (rxseq != seq) {
1796 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1797 seq, rxseq);
1798 bus->rx_badseq++;
1799 rxseq = seq;
1800 }
1801
1802 /* Check window for sanity */
1803 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1804 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1805 txmax, bus->tx_seq);
1806 txmax = bus->tx_seq + 2;
1807 }
1808 bus->tx_max = txmax;
1809
1810#ifdef BCMDBG
1811 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1812 printk(KERN_DEBUG "Rx Data:\n");
1813 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1814 rxbuf, len);
1815 } else if (BRCMF_HDRS_ON()) {
1816 printk(KERN_DEBUG "RxHdr:\n");
1817 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1818 bus->rxhdr, SDPCM_HDRLEN);
1819 }
1820#endif
1821
1822 if (chan == SDPCM_CONTROL_CHANNEL) {
1823 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1824 seq);
1825 /* Force retry w/normal header read */
1826 bus->nextlen = 0;
1827 brcmf_sdbrcm_rxfail(bus, false, true);
1828 brcmf_sdbrcm_pktfree2(bus, pkt);
1829 continue;
1830 }
1831
1832 /* Validate data offset */
1833 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1834 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1835 doff, len, SDPCM_HDRLEN);
1836 brcmf_sdbrcm_rxfail(bus, false, false);
1837 brcmf_sdbrcm_pktfree2(bus, pkt);
1838 continue;
1839 }
1840
1841 /* All done with this one -- now deliver the packet */
1842 goto deliver;
1843 }
1844
1845 /* Read frame header (hardware and software) */
1846 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1847 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
5adfeb63 1848 BRCMF_FIRSTREAD);
5b435de0
AS
1849 bus->f2rxhdrs++;
1850
1851 if (sdret < 0) {
1852 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
1853 bus->rx_hdrfail++;
1854 brcmf_sdbrcm_rxfail(bus, true, true);
1855 continue;
1856 }
1857#ifdef BCMDBG
1858 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1859 printk(KERN_DEBUG "RxHdr:\n");
1860 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1861 bus->rxhdr, SDPCM_HDRLEN);
1862 }
1863#endif
1864
1865 /* Extract hardware header fields */
1866 len = get_unaligned_le16(bus->rxhdr);
1867 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1868
1869 /* All zeros means no more frames */
1870 if (!(len | check)) {
1871 *finished = true;
1872 break;
1873 }
1874
1875 /* Validate check bytes */
1876 if ((u16) ~(len ^ check)) {
1877 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
1878 len, check);
1879 bus->rx_badhdr++;
1880 brcmf_sdbrcm_rxfail(bus, false, false);
1881 continue;
1882 }
1883
1884 /* Validate frame length */
1885 if (len < SDPCM_HDRLEN) {
1886 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
1887 continue;
1888 }
1889
1890 /* Extract software header fields */
1891 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1892 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1893 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1894 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1895
1896 /* Validate data offset */
1897 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1898 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
1899 doff, len, SDPCM_HDRLEN, seq);
1900 bus->rx_badhdr++;
1901 brcmf_sdbrcm_rxfail(bus, false, false);
1902 continue;
1903 }
1904
1905 /* Save the readahead length if there is one */
1906 bus->nextlen =
1907 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1908 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1909 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1910 bus->nextlen, seq);
1911 bus->nextlen = 0;
1912 }
1913
1914 /* Handle Flow Control */
1915 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1916
1917 if (bus->flowcontrol != fcbits) {
1918 if (~bus->flowcontrol & fcbits)
1919 bus->fc_xoff++;
1920
1921 if (bus->flowcontrol & ~fcbits)
1922 bus->fc_xon++;
1923
1924 bus->fc_rcvd++;
1925 bus->flowcontrol = fcbits;
1926 }
1927
1928 /* Check and update sequence number */
1929 if (rxseq != seq) {
1930 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
1931 bus->rx_badseq++;
1932 rxseq = seq;
1933 }
1934
1935 /* Check window for sanity */
1936 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1937 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1938 txmax, bus->tx_seq);
1939 txmax = bus->tx_seq + 2;
1940 }
1941 bus->tx_max = txmax;
1942
1943 /* Call a separate function for control frames */
1944 if (chan == SDPCM_CONTROL_CHANNEL) {
1945 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
1946 continue;
1947 }
1948
1949 /* precondition: chan is either SDPCM_DATA_CHANNEL,
1950 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
1951 SDPCM_GLOM_CHANNEL */
1952
1953 /* Length to read */
1954 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
1955
1956 /* May pad read to blocksize for efficiency */
1957 if (bus->roundup && bus->blocksize &&
1958 (rdlen > bus->blocksize)) {
1959 pad = bus->blocksize - (rdlen % bus->blocksize);
1960 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1961 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
1962 rdlen += pad;
1963 } else if (rdlen % BRCMF_SDALIGN) {
1964 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1965 }
1966
1967 /* Satisfy length-alignment requirements */
1968 if (rdlen & (ALIGNMENT - 1))
1969 rdlen = roundup(rdlen, ALIGNMENT);
1970
1971 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
1972 /* Too long -- skip this frame */
1973 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
1974 len, rdlen);
1975 bus->drvr->rx_errors++;
1976 bus->rx_toolong++;
1977 brcmf_sdbrcm_rxfail(bus, false, false);
1978 continue;
1979 }
1980
1981 pkt = brcmu_pkt_buf_get_skb(rdlen +
1982 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
1983 if (!pkt) {
1984 /* Give up on data, request rtx of events */
1985 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
1986 rdlen, chan);
1987 bus->drvr->rx_dropped++;
1988 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
1989 continue;
1990 }
1991
1992 /* Leave room for what we already read, and align remainder */
1993 skb_pull(pkt, BRCMF_FIRSTREAD);
1994 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
1995
1996 /* Read the remaining frame data */
5adfeb63
AS
1997 sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
1998 SDIO_FUNC_2, F2SYNC, pkt);
5b435de0
AS
1999 bus->f2rxdata++;
2000
2001 if (sdret < 0) {
2002 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2003 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2004 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2005 : "test")), sdret);
2006 brcmu_pkt_buf_free_skb(pkt);
2007 bus->drvr->rx_errors++;
2008 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2009 continue;
2010 }
2011
2012 /* Copy the already-read portion */
2013 skb_push(pkt, BRCMF_FIRSTREAD);
2014 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2015
2016#ifdef BCMDBG
2017 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2018 printk(KERN_DEBUG "Rx Data:\n");
2019 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2020 pkt->data, len);
2021 }
2022#endif
2023
2024deliver:
2025 /* Save superframe descriptor and allocate packet frame */
2026 if (chan == SDPCM_GLOM_CHANNEL) {
2027 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2028 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2029 len);
2030#ifdef BCMDBG
2031 if (BRCMF_GLOM_ON()) {
2032 printk(KERN_DEBUG "Glom Data:\n");
2033 print_hex_dump_bytes("",
2034 DUMP_PREFIX_OFFSET,
2035 pkt->data, len);
2036 }
2037#endif
2038 __skb_trim(pkt, len);
2039 skb_pull(pkt, SDPCM_HDRLEN);
2040 bus->glomd = pkt;
2041 } else {
2042 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2043 "descriptor!\n", __func__);
2044 brcmf_sdbrcm_rxfail(bus, false, false);
2045 }
2046 continue;
2047 }
2048
2049 /* Fill in packet len and prio, deliver upward */
2050 __skb_trim(pkt, len);
2051 skb_pull(pkt, doff);
2052
2053 if (pkt->len == 0) {
2054 brcmu_pkt_buf_free_skb(pkt);
2055 continue;
d5625ee6
FL
2056 } else if (brcmf_proto_hdrpull(bus->sdiodev->dev, &ifidx,
2057 pkt) != 0) {
5b435de0
AS
2058 brcmf_dbg(ERROR, "rx protocol error\n");
2059 brcmu_pkt_buf_free_skb(pkt);
2060 bus->drvr->rx_errors++;
2061 continue;
2062 }
2063
2064 /* Unlock during rx call */
2065 up(&bus->sdsem);
228bb43d 2066 brcmf_rx_packet(bus->sdiodev->dev, ifidx, pkt);
5b435de0
AS
2067 down(&bus->sdsem);
2068 }
2069 rxcount = maxframes - rxleft;
2070#ifdef BCMDBG
2071 /* Message if we hit the limit */
2072 if (!rxleft)
2073 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2074 maxframes);
2075 else
2076#endif /* BCMDBG */
2077 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2078 /* Back off rxseq if awaiting rtx, update rx_seq */
2079 if (bus->rxskip)
2080 rxseq--;
2081 bus->rx_seq = rxseq;
2082
2083 return rxcount;
2084}
2085
5b435de0 2086static void
e92eedf4 2087brcmf_sdbrcm_wait_for_event(struct brcmf_sdio *bus, bool *lockvar)
5b435de0
AS
2088{
2089 up(&bus->sdsem);
2090 wait_event_interruptible_timeout(bus->ctrl_wait,
2091 (*lockvar == false), HZ * 2);
2092 down(&bus->sdsem);
2093 return;
2094}
2095
2096static void
e92eedf4 2097brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus)
5b435de0
AS
2098{
2099 if (waitqueue_active(&bus->ctrl_wait))
2100 wake_up_interruptible(&bus->ctrl_wait);
2101 return;
2102}
2103
2104/* Writes a HW/SW header into the packet and sends it. */
2105/* Assumes: (a) header space already there, (b) caller holds lock */
e92eedf4 2106static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt,
5b435de0
AS
2107 uint chan, bool free_pkt)
2108{
2109 int ret;
2110 u8 *frame;
2111 u16 len, pad = 0;
2112 u32 swheader;
2113 struct sk_buff *new;
2114 int i;
2115
2116 brcmf_dbg(TRACE, "Enter\n");
2117
2118 frame = (u8 *) (pkt->data);
2119
2120 /* Add alignment padding, allocate new packet if needed */
2121 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2122 if (pad) {
2123 if (skb_headroom(pkt) < pad) {
2124 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2125 skb_headroom(pkt), pad);
2126 bus->drvr->tx_realloc++;
2127 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2128 if (!new) {
2129 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2130 pkt->len + BRCMF_SDALIGN);
2131 ret = -ENOMEM;
2132 goto done;
2133 }
2134
2135 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2136 memcpy(new->data, pkt->data, pkt->len);
2137 if (free_pkt)
2138 brcmu_pkt_buf_free_skb(pkt);
2139 /* free the pkt if canned one is not used */
2140 free_pkt = true;
2141 pkt = new;
2142 frame = (u8 *) (pkt->data);
2143 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2144 pad = 0;
2145 } else {
2146 skb_push(pkt, pad);
2147 frame = (u8 *) (pkt->data);
2148 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2149 memset(frame, 0, pad + SDPCM_HDRLEN);
2150 }
2151 }
2152 /* precondition: pad < BRCMF_SDALIGN */
2153
2154 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2155 len = (u16) (pkt->len);
2156 *(__le16 *) frame = cpu_to_le16(len);
2157 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2158
2159 /* Software tag: channel, sequence number, data offset */
2160 swheader =
2161 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2162 (((pad +
2163 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2164
2165 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2166 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2167
2168#ifdef BCMDBG
2169 tx_packets[pkt->priority]++;
2170 if (BRCMF_BYTES_ON() &&
2171 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2172 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2173 printk(KERN_DEBUG "Tx Frame:\n");
2174 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2175 } else if (BRCMF_HDRS_ON()) {
2176 printk(KERN_DEBUG "TxHdr:\n");
2177 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2178 frame, min_t(u16, len, 16));
2179 }
2180#endif
2181
2182 /* Raise len to next SDIO block to eliminate tail command */
2183 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2184 u16 pad = bus->blocksize - (len % bus->blocksize);
2185 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2186 len += pad;
2187 } else if (len % BRCMF_SDALIGN) {
2188 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2189 }
2190
2191 /* Some controllers have trouble with odd bytes -- round to even */
2192 if (len & (ALIGNMENT - 1))
2193 len = roundup(len, ALIGNMENT);
2194
5adfeb63
AS
2195 ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
2196 SDIO_FUNC_2, F2SYNC, pkt);
5b435de0
AS
2197 bus->f2txdata++;
2198
2199 if (ret < 0) {
2200 /* On failure, abort the command and terminate the frame */
2201 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2202 ret);
2203 bus->tx_sderrs++;
2204
2205 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2206 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2207 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2208 NULL);
2209 bus->f1regdata++;
2210
2211 for (i = 0; i < 3; i++) {
2212 u8 hi, lo;
2213 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2214 SDIO_FUNC_1,
2215 SBSDIO_FUNC1_WFRAMEBCHI,
2216 NULL);
2217 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2218 SDIO_FUNC_1,
2219 SBSDIO_FUNC1_WFRAMEBCLO,
2220 NULL);
2221 bus->f1regdata += 2;
2222 if ((hi == 0) && (lo == 0))
2223 break;
2224 }
2225
2226 }
2227 if (ret == 0)
2228 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2229
2230done:
2231 /* restore pkt buffer pointer before calling tx complete routine */
2232 skb_pull(pkt, SDPCM_HDRLEN + pad);
2233 up(&bus->sdsem);
c995788f 2234 brcmf_txcomplete(bus->sdiodev->dev, pkt, ret != 0);
5b435de0
AS
2235 down(&bus->sdsem);
2236
2237 if (free_pkt)
2238 brcmu_pkt_buf_free_skb(pkt);
2239
2240 return ret;
2241}
2242
e92eedf4 2243static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes)
5b435de0
AS
2244{
2245 struct sk_buff *pkt;
2246 u32 intstatus = 0;
2247 uint retries = 0;
2248 int ret = 0, prec_out;
2249 uint cnt = 0;
2250 uint datalen;
2251 u8 tx_prec_map;
2252
2253 struct brcmf_pub *drvr = bus->drvr;
2254
2255 brcmf_dbg(TRACE, "Enter\n");
2256
2257 tx_prec_map = ~bus->flowcontrol;
2258
2259 /* Send frames until the limit or some other event */
2260 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2261 spin_lock_bh(&bus->txqlock);
2262 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2263 if (pkt == NULL) {
2264 spin_unlock_bh(&bus->txqlock);
2265 break;
2266 }
2267 spin_unlock_bh(&bus->txqlock);
2268 datalen = pkt->len - SDPCM_HDRLEN;
2269
2270 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2271 if (ret)
2272 bus->drvr->tx_errors++;
2273 else
2274 bus->drvr->dstats.tx_bytes += datalen;
2275
2276 /* In poll mode, need to check for other events */
2277 if (!bus->intr && cnt) {
2278 /* Check device status, signal pending interrupt */
2279 r_sdreg32(bus, &intstatus,
2280 offsetof(struct sdpcmd_regs, intstatus),
2281 &retries);
2282 bus->f2txdata++;
2283 if (brcmf_sdcard_regfail(bus->sdiodev))
2284 break;
2285 if (intstatus & bus->hostintmask)
2286 bus->ipend = true;
2287 }
2288 }
2289
2290 /* Deflow-control stack if needed */
8d169aa0 2291 if (drvr->up && (drvr->bus_if->state == BRCMF_BUS_DATA) &&
5b435de0 2292 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2b459056 2293 brcmf_txflowcontrol(bus->sdiodev->dev, 0, OFF);
5b435de0
AS
2294
2295 return cnt;
2296}
2297
e92eedf4 2298static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
5b435de0
AS
2299{
2300 u32 intstatus, newstatus = 0;
2301 uint retries = 0;
2302 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2303 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2304 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2305 bool rxdone = true; /* Flag for no more read data */
2306 bool resched = false; /* Flag indicating resched wanted */
2307
2308 brcmf_dbg(TRACE, "Enter\n");
2309
2310 /* Start with leftover status bits */
2311 intstatus = bus->intstatus;
2312
2313 down(&bus->sdsem);
2314
2315 /* If waiting for HTAVAIL, check status */
2316 if (bus->clkstate == CLK_PENDING) {
2317 int err;
2318 u8 clkctl, devctl = 0;
2319
2320#ifdef BCMDBG
2321 /* Check for inconsistent device control */
2322 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2323 SBSDIO_DEVICE_CTL, &err);
2324 if (err) {
2325 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
8d169aa0 2326 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
2327 }
2328#endif /* BCMDBG */
2329
2330 /* Read CSR, if clock on switch to AVAIL, else ignore */
2331 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2332 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2333 if (err) {
2334 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2335 err);
8d169aa0 2336 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
2337 }
2338
2339 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2340 devctl, clkctl);
2341
2342 if (SBSDIO_HTAV(clkctl)) {
2343 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2344 SDIO_FUNC_1,
2345 SBSDIO_DEVICE_CTL, &err);
2346 if (err) {
2347 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2348 err);
8d169aa0 2349 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
2350 }
2351 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2352 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2353 SBSDIO_DEVICE_CTL, devctl, &err);
2354 if (err) {
2355 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2356 err);
8d169aa0 2357 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
2358 }
2359 bus->clkstate = CLK_AVAIL;
2360 } else {
2361 goto clkwait;
2362 }
2363 }
2364
2365 bus_wake(bus);
2366
2367 /* Make sure backplane clock is on */
2368 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2369 if (bus->clkstate == CLK_PENDING)
2370 goto clkwait;
2371
2372 /* Pending interrupt indicates new device status */
2373 if (bus->ipend) {
2374 bus->ipend = false;
2375 r_sdreg32(bus, &newstatus,
2376 offsetof(struct sdpcmd_regs, intstatus), &retries);
2377 bus->f1regdata++;
2378 if (brcmf_sdcard_regfail(bus->sdiodev))
2379 newstatus = 0;
2380 newstatus &= bus->hostintmask;
2381 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2382 if (newstatus) {
2383 w_sdreg32(bus, newstatus,
2384 offsetof(struct sdpcmd_regs, intstatus),
2385 &retries);
2386 bus->f1regdata++;
2387 }
2388 }
2389
2390 /* Merge new bits with previous */
2391 intstatus |= newstatus;
2392 bus->intstatus = 0;
2393
2394 /* Handle flow-control change: read new state in case our ack
2395 * crossed another change interrupt. If change still set, assume
2396 * FC ON for safety, let next loop through do the debounce.
2397 */
2398 if (intstatus & I_HMB_FC_CHANGE) {
2399 intstatus &= ~I_HMB_FC_CHANGE;
2400 w_sdreg32(bus, I_HMB_FC_CHANGE,
2401 offsetof(struct sdpcmd_regs, intstatus), &retries);
2402
2403 r_sdreg32(bus, &newstatus,
2404 offsetof(struct sdpcmd_regs, intstatus), &retries);
2405 bus->f1regdata += 2;
2406 bus->fcstate =
2407 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2408 intstatus |= (newstatus & bus->hostintmask);
2409 }
2410
2411 /* Handle host mailbox indication */
2412 if (intstatus & I_HMB_HOST_INT) {
2413 intstatus &= ~I_HMB_HOST_INT;
2414 intstatus |= brcmf_sdbrcm_hostmail(bus);
2415 }
2416
2417 /* Generally don't ask for these, can get CRC errors... */
2418 if (intstatus & I_WR_OOSYNC) {
2419 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2420 intstatus &= ~I_WR_OOSYNC;
2421 }
2422
2423 if (intstatus & I_RD_OOSYNC) {
2424 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2425 intstatus &= ~I_RD_OOSYNC;
2426 }
2427
2428 if (intstatus & I_SBINT) {
2429 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2430 intstatus &= ~I_SBINT;
2431 }
2432
2433 /* Would be active due to wake-wlan in gSPI */
2434 if (intstatus & I_CHIPACTIVE) {
2435 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2436 intstatus &= ~I_CHIPACTIVE;
2437 }
2438
2439 /* Ignore frame indications if rxskip is set */
2440 if (bus->rxskip)
2441 intstatus &= ~I_HMB_FRAME_IND;
2442
2443 /* On frame indication, read available frames */
2444 if (PKT_AVAILABLE()) {
2445 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2446 if (rxdone || bus->rxskip)
2447 intstatus &= ~I_HMB_FRAME_IND;
2448 rxlimit -= min(framecnt, rxlimit);
2449 }
2450
2451 /* Keep still-pending events for next scheduling */
2452 bus->intstatus = intstatus;
2453
2454clkwait:
2455 if (data_ok(bus) && bus->ctrl_frame_stat &&
2456 (bus->clkstate == CLK_AVAIL)) {
2457 int ret, i;
2458
5adfeb63 2459 ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
5b435de0 2460 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
5adfeb63 2461 (u32) bus->ctrl_frame_len);
5b435de0
AS
2462
2463 if (ret < 0) {
2464 /* On failure, abort the command and
2465 terminate the frame */
2466 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2467 ret);
2468 bus->tx_sderrs++;
2469
2470 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2471
2472 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2473 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2474 NULL);
2475 bus->f1regdata++;
2476
2477 for (i = 0; i < 3; i++) {
2478 u8 hi, lo;
2479 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2480 SDIO_FUNC_1,
2481 SBSDIO_FUNC1_WFRAMEBCHI,
2482 NULL);
2483 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2484 SDIO_FUNC_1,
2485 SBSDIO_FUNC1_WFRAMEBCLO,
2486 NULL);
2487 bus->f1regdata += 2;
2488 if ((hi == 0) && (lo == 0))
2489 break;
2490 }
2491
2492 }
2493 if (ret == 0)
2494 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2495
2496 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2497 bus->ctrl_frame_stat = false;
2498 brcmf_sdbrcm_wait_event_wakeup(bus);
2499 }
2500 /* Send queued frames (limit 1 if rx may still be pending) */
2501 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2502 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2503 && data_ok(bus)) {
2504 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2505 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2506 txlimit -= framecnt;
2507 }
2508
2509 /* Resched if events or tx frames are pending,
2510 else await next interrupt */
2511 /* On failed register access, all bets are off:
2512 no resched or interrupts */
8d169aa0 2513 if ((bus->drvr->bus_if->state == BRCMF_BUS_DOWN) ||
5b435de0
AS
2514 brcmf_sdcard_regfail(bus->sdiodev)) {
2515 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2516 brcmf_sdcard_regfail(bus->sdiodev));
8d169aa0 2517 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
2518 bus->intstatus = 0;
2519 } else if (bus->clkstate == CLK_PENDING) {
2520 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2521 resched = true;
2522 } else if (bus->intstatus || bus->ipend ||
2523 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2524 && data_ok(bus)) || PKT_AVAILABLE()) {
2525 resched = true;
2526 }
2527
2528 bus->dpc_sched = resched;
2529
2530 /* If we're done for now, turn off clock request. */
2531 if ((bus->clkstate != CLK_PENDING)
2532 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2533 bus->activity = false;
2534 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2535 }
2536
2537 up(&bus->sdsem);
2538
2539 return resched;
2540}
2541
2542static int brcmf_sdbrcm_dpc_thread(void *data)
2543{
e92eedf4 2544 struct brcmf_sdio *bus = (struct brcmf_sdio *) data;
5b435de0
AS
2545
2546 allow_signal(SIGTERM);
2547 /* Run until signal received */
2548 while (1) {
2549 if (kthread_should_stop())
2550 break;
2551 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2552 /* Call bus dpc unless it indicated down
2553 (then clean stop) */
8d169aa0 2554 if (bus->drvr->bus_if->state != BRCMF_BUS_DOWN) {
5b435de0
AS
2555 if (brcmf_sdbrcm_dpc(bus))
2556 complete(&bus->dpc_wait);
2557 } else {
2558 /* after stopping the bus, exit thread */
94c2fb82 2559 brcmf_sdbrcm_bus_stop(bus->sdiodev->dev);
5b435de0
AS
2560 bus->dpc_tsk = NULL;
2561 break;
2562 }
2563 } else
2564 break;
2565 }
2566 return 0;
2567}
2568
bf347bb9 2569int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
5b435de0
AS
2570{
2571 int ret = -EBADE;
2572 uint datalen, prec;
bf347bb9
FL
2573 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2574 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
2575 struct brcmf_sdio *bus = sdiodev->bus;
5b435de0
AS
2576
2577 brcmf_dbg(TRACE, "Enter\n");
2578
2579 datalen = pkt->len;
2580
2581 /* Add space for the header */
2582 skb_push(pkt, SDPCM_HDRLEN);
2583 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2584
2585 prec = prio2prec((pkt->priority & PRIOMASK));
2586
2587 /* Check for existing queue, current flow-control,
2588 pending event, or pending clock */
2589 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2590 bus->fcqueued++;
2591
2592 /* Priority based enq */
2593 spin_lock_bh(&bus->txqlock);
b63487ed
FL
2594 if (brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec) ==
2595 false) {
5b435de0 2596 skb_pull(pkt, SDPCM_HDRLEN);
c995788f 2597 brcmf_txcomplete(bus->sdiodev->dev, pkt, false);
5b435de0
AS
2598 brcmu_pkt_buf_free_skb(pkt);
2599 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2600 ret = -ENOSR;
2601 } else {
2602 ret = 0;
2603 }
2604 spin_unlock_bh(&bus->txqlock);
2605
2606 if (pktq_len(&bus->txq) >= TXHI)
2b459056 2607 brcmf_txflowcontrol(bus->sdiodev->dev, 0, ON);
5b435de0
AS
2608
2609#ifdef BCMDBG
2610 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2611 qcount[prec] = pktq_plen(&bus->txq, prec);
2612#endif
2613 /* Schedule DPC if needed to send queued packet(s) */
2614 if (!bus->dpc_sched) {
2615 bus->dpc_sched = true;
2616 if (bus->dpc_tsk)
2617 complete(&bus->dpc_wait);
2618 }
2619
2620 return ret;
2621}
2622
2623static int
e92eedf4 2624brcmf_sdbrcm_membytes(struct brcmf_sdio *bus, bool write, u32 address, u8 *data,
5b435de0
AS
2625 uint size)
2626{
2627 int bcmerror = 0;
2628 u32 sdaddr;
2629 uint dsize;
2630
2631 /* Determine initial transfer parameters */
2632 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2633 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2634 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2635 else
2636 dsize = size;
2637
2638 /* Set the backplane window to include the start address */
2639 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2640 if (bcmerror) {
2641 brcmf_dbg(ERROR, "window change failed\n");
2642 goto xfer_done;
2643 }
2644
2645 /* Do the transfer(s) */
2646 while (size) {
2647 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2648 write ? "write" : "read", dsize,
2649 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2650 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2651 sdaddr, data, dsize);
2652 if (bcmerror) {
2653 brcmf_dbg(ERROR, "membytes transfer failed\n");
2654 break;
2655 }
2656
2657 /* Adjust for next transfer (if any) */
2658 size -= dsize;
2659 if (size) {
2660 data += dsize;
2661 address += dsize;
2662 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2663 address);
2664 if (bcmerror) {
2665 brcmf_dbg(ERROR, "window change failed\n");
2666 break;
2667 }
2668 sdaddr = 0;
2669 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2670 }
2671 }
2672
2673xfer_done:
2674 /* Return the window to backplane enumeration space for core access */
2675 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2676 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2677 bus->sdiodev->sbwad);
2678
2679 return bcmerror;
2680}
2681
2682#ifdef BCMDBG
2683#define CONSOLE_LINE_MAX 192
2684
e92eedf4 2685static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
5b435de0
AS
2686{
2687 struct brcmf_console *c = &bus->console;
2688 u8 line[CONSOLE_LINE_MAX], ch;
2689 u32 n, idx, addr;
2690 int rv;
2691
2692 /* Don't do anything until FWREADY updates console address */
2693 if (bus->console_addr == 0)
2694 return 0;
2695
2696 /* Read console log struct */
2697 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2698 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2699 sizeof(c->log_le));
2700 if (rv < 0)
2701 return rv;
2702
2703 /* Allocate console buffer (one time only) */
2704 if (c->buf == NULL) {
2705 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2706 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2707 if (c->buf == NULL)
2708 return -ENOMEM;
2709 }
2710
2711 idx = le32_to_cpu(c->log_le.idx);
2712
2713 /* Protect against corrupt value */
2714 if (idx > c->bufsize)
2715 return -EBADE;
2716
2717 /* Skip reading the console buffer if the index pointer
2718 has not moved */
2719 if (idx == c->last)
2720 return 0;
2721
2722 /* Read the console buffer */
2723 addr = le32_to_cpu(c->log_le.buf);
2724 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2725 if (rv < 0)
2726 return rv;
2727
2728 while (c->last != idx) {
2729 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2730 if (c->last == idx) {
2731 /* This would output a partial line.
2732 * Instead, back up
2733 * the buffer pointer and output this
2734 * line next time around.
2735 */
2736 if (c->last >= n)
2737 c->last -= n;
2738 else
2739 c->last = c->bufsize - n;
2740 goto break2;
2741 }
2742 ch = c->buf[c->last];
2743 c->last = (c->last + 1) % c->bufsize;
2744 if (ch == '\n')
2745 break;
2746 line[n] = ch;
2747 }
2748
2749 if (n > 0) {
2750 if (line[n - 1] == '\r')
2751 n--;
2752 line[n] = 0;
2753 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2754 }
2755 }
2756break2:
2757
2758 return 0;
2759}
2760#endif /* BCMDBG */
2761
e92eedf4 2762static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
5b435de0
AS
2763{
2764 int i;
2765 int ret;
2766
2767 bus->ctrl_frame_stat = false;
5adfeb63
AS
2768 ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
2769 SDIO_FUNC_2, F2SYNC, frame, len);
5b435de0
AS
2770
2771 if (ret < 0) {
2772 /* On failure, abort the command and terminate the frame */
2773 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2774 ret);
2775 bus->tx_sderrs++;
2776
2777 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2778
2779 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2780 SBSDIO_FUNC1_FRAMECTRL,
2781 SFC_WF_TERM, NULL);
2782 bus->f1regdata++;
2783
2784 for (i = 0; i < 3; i++) {
2785 u8 hi, lo;
2786 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2787 SBSDIO_FUNC1_WFRAMEBCHI,
2788 NULL);
2789 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2790 SBSDIO_FUNC1_WFRAMEBCLO,
2791 NULL);
2792 bus->f1regdata += 2;
2793 if (hi == 0 && lo == 0)
2794 break;
2795 }
2796 return ret;
2797 }
2798
2799 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2800
2801 return ret;
2802}
2803
2804int
47a1ce78 2805brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
5b435de0
AS
2806{
2807 u8 *frame;
2808 u16 len;
2809 u32 swheader;
2810 uint retries = 0;
2811 u8 doff = 0;
2812 int ret = -1;
47a1ce78
FL
2813 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2814 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
2815 struct brcmf_sdio *bus = sdiodev->bus;
5b435de0
AS
2816
2817 brcmf_dbg(TRACE, "Enter\n");
2818
2819 /* Back the pointer to make a room for bus header */
2820 frame = msg - SDPCM_HDRLEN;
2821 len = (msglen += SDPCM_HDRLEN);
2822
2823 /* Add alignment padding (optional for ctl frames) */
2824 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2825 if (doff) {
2826 frame -= doff;
2827 len += doff;
2828 msglen += doff;
2829 memset(frame, 0, doff + SDPCM_HDRLEN);
2830 }
2831 /* precondition: doff < BRCMF_SDALIGN */
2832 doff += SDPCM_HDRLEN;
2833
2834 /* Round send length to next SDIO block */
2835 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2836 u16 pad = bus->blocksize - (len % bus->blocksize);
2837 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2838 len += pad;
2839 } else if (len % BRCMF_SDALIGN) {
2840 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2841 }
2842
2843 /* Satisfy length-alignment requirements */
2844 if (len & (ALIGNMENT - 1))
2845 len = roundup(len, ALIGNMENT);
2846
2847 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2848
2849 /* Need to lock here to protect txseq and SDIO tx calls */
2850 down(&bus->sdsem);
2851
2852 bus_wake(bus);
2853
2854 /* Make sure backplane clock is on */
2855 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2856
2857 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2858 *(__le16 *) frame = cpu_to_le16((u16) msglen);
2859 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2860
2861 /* Software tag: channel, sequence number, data offset */
2862 swheader =
2863 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2864 SDPCM_CHANNEL_MASK)
2865 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2866 SDPCM_DOFFSET_MASK);
2867 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2868 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2869
2870 if (!data_ok(bus)) {
2871 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
2872 bus->tx_max, bus->tx_seq);
2873 bus->ctrl_frame_stat = true;
2874 /* Send from dpc */
2875 bus->ctrl_frame_buf = frame;
2876 bus->ctrl_frame_len = len;
2877
2878 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
2879
2880 if (bus->ctrl_frame_stat == false) {
2881 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
2882 ret = 0;
2883 } else {
2884 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
2885 ret = -1;
2886 }
2887 }
2888
2889 if (ret == -1) {
2890#ifdef BCMDBG
2891 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
2892 printk(KERN_DEBUG "Tx Frame:\n");
2893 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2894 frame, len);
2895 } else if (BRCMF_HDRS_ON()) {
2896 printk(KERN_DEBUG "TxHdr:\n");
2897 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2898 frame, min_t(u16, len, 16));
2899 }
2900#endif
2901
2902 do {
2903 ret = brcmf_tx_frame(bus, frame, len);
2904 } while (ret < 0 && retries++ < TXRETRIES);
2905 }
2906
2907 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2908 bus->activity = false;
2909 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2910 }
2911
2912 up(&bus->sdsem);
2913
2914 if (ret)
2915 bus->drvr->tx_ctlerrs++;
2916 else
2917 bus->drvr->tx_ctlpkts++;
2918
2919 return ret ? -EIO : 0;
2920}
2921
2922int
532cdd3b 2923brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
5b435de0
AS
2924{
2925 int timeleft;
2926 uint rxlen = 0;
2927 bool pending;
532cdd3b
FL
2928 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2929 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
2930 struct brcmf_sdio *bus = sdiodev->bus;
5b435de0
AS
2931
2932 brcmf_dbg(TRACE, "Enter\n");
2933
2934 /* Wait until control frame is available */
2935 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
2936
2937 down(&bus->sdsem);
2938 rxlen = bus->rxlen;
2939 memcpy(msg, bus->rxctl, min(msglen, rxlen));
2940 bus->rxlen = 0;
2941 up(&bus->sdsem);
2942
2943 if (rxlen) {
2944 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
2945 rxlen, msglen);
2946 } else if (timeleft == 0) {
2947 brcmf_dbg(ERROR, "resumed on timeout\n");
2948 } else if (pending == true) {
2949 brcmf_dbg(CTL, "cancelled\n");
2950 return -ERESTARTSYS;
2951 } else {
2952 brcmf_dbg(CTL, "resumed for unknown reason?\n");
2953 }
2954
2955 if (rxlen)
2956 bus->drvr->rx_ctlpkts++;
2957 else
2958 bus->drvr->rx_ctlerrs++;
2959
2960 return rxlen ? (int)rxlen : -ETIMEDOUT;
2961}
2962
e92eedf4 2963static int brcmf_sdbrcm_downloadvars(struct brcmf_sdio *bus, void *arg, int len)
5b435de0
AS
2964{
2965 int bcmerror = 0;
2966
2967 brcmf_dbg(TRACE, "Enter\n");
2968
2969 /* Basic sanity checks */
2970 if (bus->drvr->up) {
2971 bcmerror = -EISCONN;
2972 goto err;
2973 }
2974 if (!len) {
2975 bcmerror = -EOVERFLOW;
2976 goto err;
2977 }
2978
2979 /* Free the old ones and replace with passed variables */
2980 kfree(bus->vars);
2981
2982 bus->vars = kmalloc(len, GFP_ATOMIC);
2983 bus->varsz = bus->vars ? len : 0;
2984 if (bus->vars == NULL) {
2985 bcmerror = -ENOMEM;
2986 goto err;
2987 }
2988
2989 /* Copy the passed variables, which should include the
2990 terminating double-null */
2991 memcpy(bus->vars, arg, bus->varsz);
2992err:
2993 return bcmerror;
2994}
2995
e92eedf4 2996static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
5b435de0
AS
2997{
2998 int bcmerror = 0;
2999 u32 varsize;
3000 u32 varaddr;
3001 u8 *vbuffer;
3002 u32 varsizew;
3003 __le32 varsizew_le;
3004#ifdef BCMDBG
3005 char *nvram_ularray;
3006#endif /* BCMDBG */
3007
3008 /* Even if there are no vars are to be written, we still
3009 need to set the ramsize. */
3010 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3011 varaddr = (bus->ramsize - 4) - varsize;
3012
3013 if (bus->vars) {
3014 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3015 if (!vbuffer)
3016 return -ENOMEM;
3017
3018 memcpy(vbuffer, bus->vars, bus->varsz);
3019
3020 /* Write the vars list */
3021 bcmerror =
3022 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3023#ifdef BCMDBG
3024 /* Verify NVRAM bytes */
3025 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3026 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3027 if (!nvram_ularray)
3028 return -ENOMEM;
3029
3030 /* Upload image to verify downloaded contents. */
3031 memset(nvram_ularray, 0xaa, varsize);
3032
3033 /* Read the vars list to temp buffer for comparison */
3034 bcmerror =
3035 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3036 varsize);
3037 if (bcmerror) {
3038 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3039 bcmerror, varsize, varaddr);
3040 }
3041 /* Compare the org NVRAM with the one read from RAM */
3042 if (memcmp(vbuffer, nvram_ularray, varsize))
3043 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3044 else
3045 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3046
3047 kfree(nvram_ularray);
3048#endif /* BCMDBG */
3049
3050 kfree(vbuffer);
3051 }
3052
3053 /* adjust to the user specified RAM */
3054 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3055 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3056 varaddr, varsize);
3057 varsize = ((bus->ramsize - 4) - varaddr);
3058
3059 /*
3060 * Determine the length token:
3061 * Varsize, converted to words, in lower 16-bits, checksum
3062 * in upper 16-bits.
3063 */
3064 if (bcmerror) {
3065 varsizew = 0;
3066 varsizew_le = cpu_to_le32(0);
3067 } else {
3068 varsizew = varsize / 4;
3069 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3070 varsizew_le = cpu_to_le32(varsizew);
3071 }
3072
3073 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3074 varsize, varsizew);
3075
3076 /* Write the length token to the last word */
3077 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3078 (u8 *)&varsizew_le, 4);
3079
3080 return bcmerror;
3081}
3082
e92eedf4 3083static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
5b435de0
AS
3084{
3085 uint retries;
5b435de0 3086 int bcmerror = 0;
99ba15cd 3087 struct chip_info *ci = bus->ci;
5b435de0
AS
3088
3089 /* To enter download state, disable ARM and reset SOCRAM.
3090 * To exit download state, simply reset ARM (default is RAM boot).
3091 */
3092 if (enter) {
3093 bus->alp_only = true;
3094
086a2e0a 3095 ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
5b435de0 3096
d77e70ff 3097 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
5b435de0
AS
3098
3099 /* Clear the top bit of memory */
3100 if (bus->ramsize) {
3101 u32 zeros = 0;
3102 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3103 (u8 *)&zeros, 4);
3104 }
3105 } else {
6ca687d9 3106 if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
5b435de0
AS
3107 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3108 bcmerror = -EBADE;
3109 goto fail;
3110 }
3111
3112 bcmerror = brcmf_sdbrcm_write_vars(bus);
3113 if (bcmerror) {
3114 brcmf_dbg(ERROR, "no vars written to RAM\n");
3115 bcmerror = 0;
3116 }
3117
3118 w_sdreg32(bus, 0xFFFFFFFF,
3119 offsetof(struct sdpcmd_regs, intstatus), &retries);
3120
d77e70ff 3121 ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
5b435de0
AS
3122
3123 /* Allow HT Clock now that the ARM is running. */
3124 bus->alp_only = false;
3125
8d169aa0 3126 bus->drvr->bus_if->state = BRCMF_BUS_LOAD;
5b435de0
AS
3127 }
3128fail:
3129 return bcmerror;
3130}
3131
e92eedf4 3132static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus)
5b435de0
AS
3133{
3134 if (bus->firmware->size < bus->fw_ptr + len)
3135 len = bus->firmware->size - bus->fw_ptr;
3136
3137 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3138 bus->fw_ptr += len;
3139 return len;
3140}
3141
e92eedf4 3142static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus)
5b435de0
AS
3143{
3144 int offset = 0;
3145 uint len;
3146 u8 *memblock = NULL, *memptr;
3147 int ret;
3148
3149 brcmf_dbg(INFO, "Enter\n");
3150
8dd939ca 3151 ret = request_firmware(&bus->firmware, BRCMFMAC_FW_NAME,
5b435de0
AS
3152 &bus->sdiodev->func[2]->dev);
3153 if (ret) {
3154 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3155 return ret;
3156 }
3157 bus->fw_ptr = 0;
3158
3159 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3160 if (memblock == NULL) {
3161 ret = -ENOMEM;
3162 goto err;
3163 }
3164 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3165 memptr += (BRCMF_SDALIGN -
3166 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3167
3168 /* Download image */
3169 while ((len =
3170 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3171 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3172 if (ret) {
3173 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3174 ret, MEMBLOCK, offset);
3175 goto err;
3176 }
3177
3178 offset += MEMBLOCK;
3179 }
3180
3181err:
3182 kfree(memblock);
3183
3184 release_firmware(bus->firmware);
3185 bus->fw_ptr = 0;
3186
3187 return ret;
3188}
3189
3190/*
3191 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3192 * and ending in a NUL.
3193 * Removes carriage returns, empty lines, comment lines, and converts
3194 * newlines to NULs.
3195 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3196 * by two NULs.
3197*/
3198
3199static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3200{
3201 char *dp;
3202 bool findNewline;
3203 int column;
3204 uint buf_len, n;
3205
3206 dp = varbuf;
3207
3208 findNewline = false;
3209 column = 0;
3210
3211 for (n = 0; n < len; n++) {
3212 if (varbuf[n] == 0)
3213 break;
3214 if (varbuf[n] == '\r')
3215 continue;
3216 if (findNewline && varbuf[n] != '\n')
3217 continue;
3218 findNewline = false;
3219 if (varbuf[n] == '#') {
3220 findNewline = true;
3221 continue;
3222 }
3223 if (varbuf[n] == '\n') {
3224 if (column == 0)
3225 continue;
3226 *dp++ = 0;
3227 column = 0;
3228 continue;
3229 }
3230 *dp++ = varbuf[n];
3231 column++;
3232 }
3233 buf_len = dp - varbuf;
3234
3235 while (dp < varbuf + n)
3236 *dp++ = 0;
3237
3238 return buf_len;
3239}
3240
e92eedf4 3241static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
5b435de0
AS
3242{
3243 uint len;
3244 char *memblock = NULL;
3245 char *bufp;
3246 int ret;
3247
8dd939ca 3248 ret = request_firmware(&bus->firmware, BRCMFMAC_NV_NAME,
5b435de0
AS
3249 &bus->sdiodev->func[2]->dev);
3250 if (ret) {
3251 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3252 return ret;
3253 }
3254 bus->fw_ptr = 0;
3255
3256 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3257 if (memblock == NULL) {
3258 ret = -ENOMEM;
3259 goto err;
3260 }
3261
3262 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3263
3264 if (len > 0 && len < MEMBLOCK) {
3265 bufp = (char *)memblock;
3266 bufp[len] = 0;
3267 len = brcmf_process_nvram_vars(bufp, len);
3268 bufp += len;
3269 *bufp++ = 0;
3270 if (len)
3271 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3272 if (ret)
3273 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3274 } else {
3275 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3276 ret = -EIO;
3277 }
3278
3279err:
3280 kfree(memblock);
3281
3282 release_firmware(bus->firmware);
3283 bus->fw_ptr = 0;
3284
3285 return ret;
3286}
3287
e92eedf4 3288static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
5b435de0
AS
3289{
3290 int bcmerror = -1;
3291
3292 /* Keep arm in reset */
3293 if (brcmf_sdbrcm_download_state(bus, true)) {
3294 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3295 goto err;
3296 }
3297
3298 /* External image takes precedence if specified */
3299 if (brcmf_sdbrcm_download_code_file(bus)) {
3300 brcmf_dbg(ERROR, "dongle image file download failed\n");
3301 goto err;
3302 }
3303
3304 /* External nvram takes precedence if specified */
3305 if (brcmf_sdbrcm_download_nvram(bus))
3306 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3307
3308 /* Take arm out of reset */
3309 if (brcmf_sdbrcm_download_state(bus, false)) {
3310 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3311 goto err;
3312 }
3313
3314 bcmerror = 0;
3315
3316err:
3317 return bcmerror;
3318}
3319
3320static bool
e92eedf4 3321brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
5b435de0
AS
3322{
3323 bool ret;
3324
3325 /* Download the firmware */
3326 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3327
3328 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3329
3330 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3331
3332 return ret;
3333}
3334
94c2fb82 3335void brcmf_sdbrcm_bus_stop(struct device *dev)
5b435de0
AS
3336{
3337 u32 local_hostintmask;
3338 u8 saveclk;
3339 uint retries;
3340 int err;
94c2fb82
FL
3341 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3342 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
3343 struct brcmf_sdio *bus = sdiodev->bus;
5b435de0
AS
3344
3345 brcmf_dbg(TRACE, "Enter\n");
3346
3347 if (bus->watchdog_tsk) {
3348 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3349 kthread_stop(bus->watchdog_tsk);
3350 bus->watchdog_tsk = NULL;
3351 }
3352
3353 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3354 send_sig(SIGTERM, bus->dpc_tsk, 1);
3355 kthread_stop(bus->dpc_tsk);
3356 bus->dpc_tsk = NULL;
3357 }
3358
3359 down(&bus->sdsem);
3360
3361 bus_wake(bus);
3362
3363 /* Enable clock for device interrupts */
3364 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3365
3366 /* Disable and clear interrupts at the chip level also */
3367 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3368 local_hostintmask = bus->hostintmask;
3369 bus->hostintmask = 0;
3370
3371 /* Change our idea of bus state */
8d169aa0 3372 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
3373
3374 /* Force clocks on backplane to be sure F2 interrupt propagates */
3375 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3376 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3377 if (!err) {
3378 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3379 SBSDIO_FUNC1_CHIPCLKCSR,
3380 (saveclk | SBSDIO_FORCE_HT), &err);
3381 }
3382 if (err)
3383 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3384
3385 /* Turn off the bus (F2), free any pending packets */
3386 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3387 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3388 SDIO_FUNC_ENABLE_1, NULL);
3389
3390 /* Clear any pending interrupts now that F2 is disabled */
3391 w_sdreg32(bus, local_hostintmask,
3392 offsetof(struct sdpcmd_regs, intstatus), &retries);
3393
3394 /* Turn off the backplane clock (only) */
3395 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3396
3397 /* Clear the data packet queues */
3398 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3399
3400 /* Clear any held glomming stuff */
3401 if (bus->glomd)
3402 brcmu_pkt_buf_free_skb(bus->glomd);
046808da 3403 brcmf_sdbrcm_free_glom(bus);
5b435de0
AS
3404
3405 /* Clear rx control and wake any waiters */
3406 bus->rxlen = 0;
3407 brcmf_sdbrcm_dcmd_resp_wake(bus);
3408
3409 /* Reset some F2 state stuff */
3410 bus->rxskip = false;
3411 bus->tx_seq = bus->rx_seq = 0;
3412
3413 up(&bus->sdsem);
3414}
3415
fa20b911 3416int brcmf_sdbrcm_bus_init(struct device *dev)
5b435de0 3417{
fa20b911
FL
3418 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3419 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
3420 struct brcmf_sdio *bus = sdiodev->bus;
5b435de0
AS
3421 unsigned long timeout;
3422 uint retries = 0;
3423 u8 ready, enable;
3424 int err, ret = 0;
3425 u8 saveclk;
3426
3427 brcmf_dbg(TRACE, "Enter\n");
3428
3429 /* try to download image and nvram to the dongle */
fa20b911 3430 if (bus_if->state == BRCMF_BUS_DOWN) {
5b435de0
AS
3431 if (!(brcmf_sdbrcm_download_firmware(bus)))
3432 return -1;
3433 }
3434
3435 if (!bus->drvr)
3436 return 0;
3437
3438 /* Start the watchdog timer */
3439 bus->drvr->tickcnt = 0;
3440 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3441
3442 down(&bus->sdsem);
3443
3444 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3445 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3446 if (bus->clkstate != CLK_AVAIL)
3447 goto exit;
3448
3449 /* Force clocks on backplane to be sure F2 interrupt propagates */
3450 saveclk =
3451 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3452 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3453 if (!err) {
3454 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3455 SBSDIO_FUNC1_CHIPCLKCSR,
3456 (saveclk | SBSDIO_FORCE_HT), &err);
3457 }
3458 if (err) {
3459 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3460 goto exit;
3461 }
3462
3463 /* Enable function 2 (frame transfers) */
3464 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3465 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3466 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3467
3468 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3469 enable, NULL);
3470
3471 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3472 ready = 0;
3473 while (enable != ready) {
3474 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3475 SDIO_CCCR_IORx, NULL);
3476 if (time_after(jiffies, timeout))
3477 break;
3478 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3479 /* prevent busy waiting if it takes too long */
3480 msleep_interruptible(20);
3481 }
3482
3483 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3484
3485 /* If F2 successfully enabled, set core and enable interrupts */
3486 if (ready == enable) {
3487 /* Set up the interrupt mask and enable interrupts */
3488 bus->hostintmask = HOSTINTMASK;
3489 w_sdreg32(bus, bus->hostintmask,
3490 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3491
3492 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3493 SBSDIO_WATERMARK, 8, &err);
3494
3495 /* Set bus state according to enable result */
fa20b911 3496 bus_if->state = BRCMF_BUS_DATA;
5b435de0
AS
3497 }
3498
3499 else {
3500 /* Disable F2 again */
3501 enable = SDIO_FUNC_ENABLE_1;
3502 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3503 SDIO_CCCR_IOEx, enable, NULL);
3504 }
3505
3506 /* Restore previous clock setting */
3507 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3508 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3509
3510 /* If we didn't come up, turn off backplane clock */
fa20b911 3511 if (bus_if->state != BRCMF_BUS_DATA)
5b435de0
AS
3512 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3513
3514exit:
3515 up(&bus->sdsem);
3516
3517 return ret;
3518}
3519
3520void brcmf_sdbrcm_isr(void *arg)
3521{
e92eedf4 3522 struct brcmf_sdio *bus = (struct brcmf_sdio *) arg;
5b435de0
AS
3523
3524 brcmf_dbg(TRACE, "Enter\n");
3525
3526 if (!bus) {
3527 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3528 return;
3529 }
3530
8d169aa0 3531 if (bus->drvr->bus_if->state == BRCMF_BUS_DOWN) {
5b435de0
AS
3532 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3533 return;
3534 }
3535 /* Count the interrupt call */
3536 bus->intrcount++;
3537 bus->ipend = true;
3538
3539 /* Shouldn't get this interrupt if we're sleeping? */
3540 if (bus->sleeping) {
3541 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3542 return;
3543 }
3544
3545 /* Disable additional interrupts (is this needed now)? */
3546 if (!bus->intr)
3547 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3548
3549 bus->dpc_sched = true;
3550 if (bus->dpc_tsk)
3551 complete(&bus->dpc_wait);
3552}
3553
cad2b26b 3554static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
5b435de0 3555{
cad2b26b
FL
3556#ifdef BCMDBG
3557 struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
3558#endif /* BCMDBG */
5b435de0
AS
3559
3560 brcmf_dbg(TIMER, "Enter\n");
3561
5b435de0
AS
3562 /* Ignore the timer if simulating bus down */
3563 if (bus->sleeping)
3564 return false;
3565
3566 down(&bus->sdsem);
3567
3568 /* Poll period: check device if appropriate. */
3569 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3570 u32 intstatus = 0;
3571
3572 /* Reset poll tick */
3573 bus->polltick = 0;
3574
3575 /* Check device if no interrupts */
3576 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3577
3578 if (!bus->dpc_sched) {
3579 u8 devpend;
3580 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3581 SDIO_FUNC_0, SDIO_CCCR_INTx,
3582 NULL);
3583 intstatus =
3584 devpend & (INTR_STATUS_FUNC1 |
3585 INTR_STATUS_FUNC2);
3586 }
3587
3588 /* If there is something, make like the ISR and
3589 schedule the DPC */
3590 if (intstatus) {
3591 bus->pollcnt++;
3592 bus->ipend = true;
3593
3594 bus->dpc_sched = true;
3595 if (bus->dpc_tsk)
3596 complete(&bus->dpc_wait);
3597 }
3598 }
3599
3600 /* Update interrupt tracking */
3601 bus->lastintrs = bus->intrcount;
3602 }
3603#ifdef BCMDBG
3604 /* Poll for console output periodically */
cad2b26b 3605 if (bus_if->state == BRCMF_BUS_DATA &&
8d169aa0 3606 bus->console_interval != 0) {
5b435de0
AS
3607 bus->console.count += BRCMF_WD_POLL_MS;
3608 if (bus->console.count >= bus->console_interval) {
3609 bus->console.count -= bus->console_interval;
3610 /* Make sure backplane clock is on */
3611 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3612 if (brcmf_sdbrcm_readconsole(bus) < 0)
3613 /* stop on error */
3614 bus->console_interval = 0;
3615 }
3616 }
3617#endif /* BCMDBG */
3618
3619 /* On idle timeout clear activity flag and/or turn off clock */
3620 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3621 if (++bus->idlecount >= bus->idletime) {
3622 bus->idlecount = 0;
3623 if (bus->activity) {
3624 bus->activity = false;
3625 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3626 } else {
3627 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3628 }
3629 }
3630 }
3631
3632 up(&bus->sdsem);
3633
3634 return bus->ipend;
3635}
3636
3637static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3638{
3639 if (chipid == BCM4329_CHIP_ID)
3640 return true;
ce2d7d7e
FL
3641 if (chipid == BCM4330_CHIP_ID)
3642 return true;
5b435de0
AS
3643 return false;
3644}
3645
e92eedf4 3646static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus)
5b435de0
AS
3647{
3648 brcmf_dbg(TRACE, "Enter\n");
3649
3650 kfree(bus->rxbuf);
3651 bus->rxctl = bus->rxbuf = NULL;
3652 bus->rxlen = 0;
3653
3654 kfree(bus->databuf);
3655 bus->databuf = NULL;
3656}
3657
e92eedf4 3658static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus)
5b435de0
AS
3659{
3660 brcmf_dbg(TRACE, "Enter\n");
3661
3662 if (bus->drvr->maxctl) {
3663 bus->rxblen =
3664 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3665 ALIGNMENT) + BRCMF_SDALIGN;
3666 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3667 if (!(bus->rxbuf))
3668 goto fail;
3669 }
3670
3671 /* Allocate buffer to receive glomed packet */
3672 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3673 if (!(bus->databuf)) {
3674 /* release rxbuf which was already located as above */
3675 if (!bus->rxblen)
3676 kfree(bus->rxbuf);
3677 goto fail;
3678 }
3679
3680 /* Align the buffer */
3681 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3682 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3683 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3684 else
3685 bus->dataptr = bus->databuf;
3686
3687 return true;
3688
3689fail:
3690 return false;
3691}
3692
5b435de0 3693static bool
e92eedf4 3694brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
5b435de0
AS
3695{
3696 u8 clkctl = 0;
3697 int err = 0;
3698 int reg_addr;
3699 u32 reg_val;
99ba15cd 3700 u8 idx;
5b435de0
AS
3701
3702 bus->alp_only = true;
3703
3704 /* Return the window to backplane enumeration space for core access */
3705 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
3706 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
3707
3708#ifdef BCMDBG
3709 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
3710 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
3711
3712#endif /* BCMDBG */
3713
3714 /*
a97e4fc5 3715 * Force PLL off until brcmf_sdio_chip_attach()
5b435de0
AS
3716 * programs PLL control regs
3717 */
3718
3719 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3720 SBSDIO_FUNC1_CHIPCLKCSR,
3721 BRCMF_INIT_CLKCTL1, &err);
3722 if (!err)
3723 clkctl =
3724 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3725 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3726
3727 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3728 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3729 err, BRCMF_INIT_CLKCTL1, clkctl);
3730 goto fail;
3731 }
3732
a97e4fc5
FL
3733 if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
3734 brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
5b435de0
AS
3735 goto fail;
3736 }
3737
3738 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
3739 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
3740 goto fail;
3741 }
3742
e12afb6c
FL
3743 brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci,
3744 SDIO_DRIVE_STRENGTH);
5b435de0 3745
454d2a88 3746 /* Get info on the SOCRAM cores... */
5b435de0
AS
3747 bus->ramsize = bus->ci->ramsize;
3748 if (!(bus->ramsize)) {
3749 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
3750 goto fail;
3751 }
3752
3753 /* Set core control so an SDIO reset does a backplane reset */
99ba15cd
FL
3754 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
3755 reg_addr = bus->ci->c_inf[idx].base +
5b435de0
AS
3756 offsetof(struct sdpcmd_regs, corecontrol);
3757 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
3758 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
3759 reg_val | CC_BPRESEN);
3760
3761 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3762
3763 /* Locate an appropriately-aligned portion of hdrbuf */
3764 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3765 BRCMF_SDALIGN);
3766
3767 /* Set the poll and/or interrupt flags */
3768 bus->intr = true;
3769 bus->poll = false;
3770 if (bus->poll)
3771 bus->pollrate = 1;
3772
3773 return true;
3774
3775fail:
3776 return false;
3777}
3778
e92eedf4 3779static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus)
5b435de0
AS
3780{
3781 brcmf_dbg(TRACE, "Enter\n");
3782
3783 /* Disable F2 to clear any intermediate frame state on the dongle */
3784 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3785 SDIO_FUNC_ENABLE_1, NULL);
3786
8d169aa0 3787 bus->drvr->bus_if->state = BRCMF_BUS_DOWN;
5b435de0
AS
3788 bus->sleeping = false;
3789 bus->rxflow = false;
3790
3791 /* Done with backplane-dependent accesses, can drop clock... */
3792 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3793 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
3794
3795 /* ...and initialize clock/power states */
3796 bus->clkstate = CLK_SDONLY;
3797 bus->idletime = BRCMF_IDLE_INTERVAL;
3798 bus->idleclock = BRCMF_IDLE_ACTIVE;
3799
3800 /* Query the F2 block size, set roundup accordingly */
3801 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
3802 bus->roundup = min(max_roundup, bus->blocksize);
3803
3804 /* bus module does not support packet chaining */
3805 bus->use_rxchain = false;
3806 bus->sd_rxchain = false;
3807
3808 return true;
3809}
3810
3811static int
3812brcmf_sdbrcm_watchdog_thread(void *data)
3813{
e92eedf4 3814 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
5b435de0
AS
3815
3816 allow_signal(SIGTERM);
3817 /* Run until signal received */
3818 while (1) {
3819 if (kthread_should_stop())
3820 break;
3821 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
cad2b26b 3822 brcmf_sdbrcm_bus_watchdog(bus);
5b435de0
AS
3823 /* Count the tick for reference */
3824 bus->drvr->tickcnt++;
3825 } else
3826 break;
3827 }
3828 return 0;
3829}
3830
3831static void
3832brcmf_sdbrcm_watchdog(unsigned long data)
3833{
e92eedf4 3834 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
5b435de0
AS
3835
3836 if (bus->watchdog_tsk) {
3837 complete(&bus->watchdog_wait);
3838 /* Reschedule the watchdog */
3839 if (bus->wd_timer_valid)
3840 mod_timer(&bus->timer,
3841 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
3842 }
3843}
3844
e92eedf4 3845static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
5b435de0
AS
3846{
3847 brcmf_dbg(TRACE, "Enter\n");
3848
3849 if (bus->ci) {
3850 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3851 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
a8a6c045 3852 brcmf_sdio_chip_detach(&bus->ci);
5b435de0
AS
3853 if (bus->vars && bus->varsz)
3854 kfree(bus->vars);
3855 bus->vars = NULL;
3856 }
3857
3858 brcmf_dbg(TRACE, "Disconnected\n");
3859}
3860
3861/* Detach and free everything */
e92eedf4 3862static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
5b435de0
AS
3863{
3864 brcmf_dbg(TRACE, "Enter\n");
3865
3866 if (bus) {
3867 /* De-register interrupt handler */
3868 brcmf_sdcard_intr_dereg(bus->sdiodev);
3869
5f947ad9
FL
3870 if (bus->sdiodev->bus_if->drvr) {
3871 brcmf_detach(bus->sdiodev->dev);
5b435de0
AS
3872 brcmf_sdbrcm_release_dongle(bus);
3873 bus->drvr = NULL;
3874 }
3875
3876 brcmf_sdbrcm_release_malloc(bus);
3877
3878 kfree(bus);
3879 }
3880
3881 brcmf_dbg(TRACE, "Disconnected\n");
3882}
3883
4175b88b 3884void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
5b435de0
AS
3885{
3886 int ret;
e92eedf4 3887 struct brcmf_sdio *bus;
5b435de0 3888
5b435de0
AS
3889 brcmf_dbg(TRACE, "Enter\n");
3890
3891 /* We make an assumption about address window mappings:
3892 * regsva == SI_ENUM_BASE*/
3893
3894 /* Allocate private bus interface state */
e92eedf4 3895 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
5b435de0
AS
3896 if (!bus)
3897 goto fail;
3898
3899 bus->sdiodev = sdiodev;
3900 sdiodev->bus = bus;
b83db862 3901 skb_queue_head_init(&bus->glom);
5b435de0
AS
3902 bus->txbound = BRCMF_TXBOUND;
3903 bus->rxbound = BRCMF_RXBOUND;
3904 bus->txminmax = BRCMF_TXMINMAX;
3905 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
3906 bus->usebufpool = false; /* Use bufpool if allocated,
3907 else use locally malloced rxbuf */
3908
3909 /* attempt to attach to the dongle */
3910 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
3911 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
3912 goto fail;
3913 }
3914
3915 spin_lock_init(&bus->txqlock);
3916 init_waitqueue_head(&bus->ctrl_wait);
3917 init_waitqueue_head(&bus->dcmd_resp_wait);
3918
3919 /* Set up the watchdog timer */
3920 init_timer(&bus->timer);
3921 bus->timer.data = (unsigned long)bus;
3922 bus->timer.function = brcmf_sdbrcm_watchdog;
3923
3924 /* Initialize thread based operation and lock */
3925 sema_init(&bus->sdsem, 1);
3926
3927 /* Initialize watchdog thread */
3928 init_completion(&bus->watchdog_wait);
3929 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
3930 bus, "brcmf_watchdog");
3931 if (IS_ERR(bus->watchdog_tsk)) {
3932 printk(KERN_WARNING
3933 "brcmf_watchdog thread failed to start\n");
3934 bus->watchdog_tsk = NULL;
3935 }
3936 /* Initialize DPC thread */
3937 init_completion(&bus->dpc_wait);
3938 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
3939 bus, "brcmf_dpc");
3940 if (IS_ERR(bus->dpc_tsk)) {
3941 printk(KERN_WARNING
3942 "brcmf_dpc thread failed to start\n");
3943 bus->dpc_tsk = NULL;
3944 }
3945
3946 /* Attach to the brcmf/OS/network interface */
8d169aa0 3947 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE, bus->sdiodev->dev);
5b435de0
AS
3948 if (!bus->drvr) {
3949 brcmf_dbg(ERROR, "brcmf_attach failed\n");
3950 goto fail;
3951 }
3952
3953 /* Allocate buffers */
3954 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
3955 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
3956 goto fail;
3957 }
3958
3959 if (!(brcmf_sdbrcm_probe_init(bus))) {
3960 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
3961 goto fail;
3962 }
3963
3964 /* Register interrupt callback, but mask it (not operational yet). */
3965 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
3966 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
3967 if (ret != 0) {
3968 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
3969 goto fail;
3970 }
3971 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
3972
3973 brcmf_dbg(INFO, "completed!!\n");
3974
3975 /* if firmware path present try to download and bring up bus */
ed683c98 3976 ret = brcmf_bus_start(bus->sdiodev->dev);
5b435de0
AS
3977 if (ret != 0) {
3978 if (ret == -ENOLINK) {
3979 brcmf_dbg(ERROR, "dongle is not responding\n");
3980 goto fail;
3981 }
3982 }
15d45b6f
FL
3983
3984 /* add interface and open for business */
55a63bcc 3985 if (brcmf_add_if(bus->sdiodev->dev, 0, "wlan%d", NULL)) {
15d45b6f 3986 brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
5b435de0
AS
3987 goto fail;
3988 }
3989
3990 return bus;
3991
3992fail:
3993 brcmf_sdbrcm_release(bus);
3994 return NULL;
3995}
3996
3997void brcmf_sdbrcm_disconnect(void *ptr)
3998{
e92eedf4 3999 struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr;
5b435de0
AS
4000
4001 brcmf_dbg(TRACE, "Enter\n");
4002
4003 if (bus)
4004 brcmf_sdbrcm_release(bus);
4005
4006 brcmf_dbg(TRACE, "Disconnected\n");
4007}
4008
5b435de0 4009void
e92eedf4 4010brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick)
5b435de0 4011{
5b435de0
AS
4012 /* Totally stop the timer */
4013 if (!wdtick && bus->wd_timer_valid == true) {
4014 del_timer_sync(&bus->timer);
4015 bus->wd_timer_valid = false;
4016 bus->save_ms = wdtick;
4017 return;
4018 }
4019
ece960ea 4020 /* don't start the wd until fw is loaded */
8d169aa0 4021 if (bus->drvr->bus_if->state == BRCMF_BUS_DOWN)
ece960ea
FL
4022 return;
4023
5b435de0
AS
4024 if (wdtick) {
4025 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4026 if (bus->wd_timer_valid == true)
4027 /* Stop timer and restart at new value */
4028 del_timer_sync(&bus->timer);
4029
4030 /* Create timer again when watchdog period is
4031 dynamically changed or in the first instance
4032 */
4033 bus->timer.expires =
4034 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4035 add_timer(&bus->timer);
4036
4037 } else {
4038 /* Re arm the timer, at last watchdog period */
4039 mod_timer(&bus->timer,
4040 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4041 }
4042
4043 bus->wd_timer_valid = true;
4044 bus->save_ms = wdtick;
4045 }
4046}
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