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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
02f77195 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
5b435de0 AS |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/kthread.h> | |
22 | #include <linux/printk.h> | |
23 | #include <linux/pci_ids.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/mmc/sdio.h> | |
28 | #include <linux/mmc/sdio_func.h> | |
29 | #include <linux/mmc/card.h> | |
30 | #include <linux/semaphore.h> | |
31 | #include <linux/firmware.h> | |
b7a57e76 | 32 | #include <linux/module.h> |
99ba15cd | 33 | #include <linux/bcma/bcma.h> |
5b435de0 AS |
34 | #include <asm/unaligned.h> |
35 | #include <defs.h> | |
36 | #include <brcmu_wifi.h> | |
37 | #include <brcmu_utils.h> | |
38 | #include <brcm_hw_ids.h> | |
39 | #include <soc.h> | |
40 | #include "sdio_host.h" | |
a83369b6 | 41 | #include "sdio_chip.h" |
5b435de0 AS |
42 | |
43 | #define DCMD_RESP_TIMEOUT 2000 /* In milli second */ | |
44 | ||
8ae74654 | 45 | #ifdef DEBUG |
5b435de0 AS |
46 | |
47 | #define BRCMF_TRAP_INFO_SIZE 80 | |
48 | ||
49 | #define CBUF_LEN (128) | |
50 | ||
51 | struct rte_log_le { | |
52 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
53 | __le32 buf_size; | |
54 | __le32 idx; | |
55 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
56 | }; | |
57 | ||
58 | struct rte_console { | |
59 | /* Virtual UART | |
60 | * When there is no UART (e.g. Quickturn), | |
61 | * the host should write a complete | |
62 | * input line directly into cbuf and then write | |
63 | * the length into vcons_in. | |
64 | * This may also be used when there is a real UART | |
65 | * (at risk of conflicting with | |
66 | * the real UART). vcons_out is currently unused. | |
67 | */ | |
68 | uint vcons_in; | |
69 | uint vcons_out; | |
70 | ||
71 | /* Output (logging) buffer | |
72 | * Console output is written to a ring buffer log_buf at index log_idx. | |
73 | * The host may read the output when it sees log_idx advance. | |
74 | * Output will be lost if the output wraps around faster than the host | |
75 | * polls. | |
76 | */ | |
77 | struct rte_log_le log_le; | |
78 | ||
79 | /* Console input line buffer | |
80 | * Characters are read one at a time into cbuf | |
81 | * until <CR> is received, then | |
82 | * the buffer is processed as a command line. | |
83 | * Also used for virtual UART. | |
84 | */ | |
85 | uint cbuf_idx; | |
86 | char cbuf[CBUF_LEN]; | |
87 | }; | |
88 | ||
8ae74654 | 89 | #endif /* DEBUG */ |
5b435de0 AS |
90 | #include <chipcommon.h> |
91 | ||
5b435de0 | 92 | #include "dhd_bus.h" |
5b435de0 | 93 | #include "dhd_dbg.h" |
5b435de0 AS |
94 | |
95 | #define TXQLEN 2048 /* bulk tx queue length */ | |
96 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
97 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
98 | #define PRIOMASK 7 | |
99 | ||
100 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
101 | ||
102 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
103 | one scheduling */ | |
104 | ||
105 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
106 | one scheduling */ | |
107 | ||
108 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
109 | ||
110 | #define MEMBLOCK 2048 /* Block size used for downloading | |
111 | of dongle image */ | |
112 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
113 | biggest possible glom */ | |
114 | ||
115 | #define BRCMF_FIRSTREAD (1 << 6) | |
116 | ||
117 | ||
118 | /* SBSDIO_DEVICE_CTL */ | |
119 | ||
120 | /* 1: device will assert busy signal when receiving CMD53 */ | |
121 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
122 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
123 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
124 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
125 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
126 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
127 | * sdio bus power cycle to clear (rev 9) */ | |
128 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
129 | /* Force SD->SB reset mapping (rev 11) */ | |
130 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
131 | /* Determined by CoreControl bit */ | |
132 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
133 | /* Force backplane reset */ | |
134 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
135 | /* Force no backplane reset */ | |
136 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
137 | ||
5b435de0 AS |
138 | /* direct(mapped) cis space */ |
139 | ||
140 | /* MAPPED common CIS address */ | |
141 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
142 | /* maximum bytes in one CIS */ | |
143 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
144 | /* cis offset addr is < 17 bits */ | |
145 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
146 | ||
147 | /* manfid tuple length, include tuple, link bytes */ | |
148 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
149 | ||
150 | /* intstatus */ | |
151 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
152 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
153 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
154 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
155 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
156 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
157 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
158 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
159 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
160 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
161 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
162 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
163 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
164 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
165 | #define I_PC (1 << 10) /* descriptor error */ | |
166 | #define I_PD (1 << 11) /* data error */ | |
167 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
168 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
169 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
170 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
171 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
172 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
173 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
174 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
175 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
176 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
177 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
178 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
179 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
180 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
181 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
182 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
183 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
184 | ||
185 | /* corecontrol */ | |
186 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
187 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
188 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
189 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
190 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
191 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
192 | ||
193 | /* SDA_FRAMECTRL */ | |
194 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
195 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
196 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
197 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
198 | ||
199 | /* HW frame tag */ | |
200 | #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */ | |
201 | ||
202 | /* Total length of frame header for dongle protocol */ | |
203 | #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN) | |
204 | #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN) | |
205 | ||
206 | /* | |
207 | * Software allocation of To SB Mailbox resources | |
208 | */ | |
209 | ||
210 | /* tosbmailbox bits corresponding to intstatus bits */ | |
211 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
212 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
213 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
214 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
215 | ||
216 | /* tosbmailboxdata */ | |
217 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
218 | ||
219 | /* | |
220 | * Software allocation of To Host Mailbox resources | |
221 | */ | |
222 | ||
223 | /* intstatus bits */ | |
224 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
225 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
226 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
227 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
228 | ||
229 | /* tohostmailboxdata */ | |
230 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
231 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
232 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
233 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
234 | ||
235 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
236 | #define HMB_DATA_FCDATA_SHIFT 24 | |
237 | ||
238 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
239 | #define HMB_DATA_VERSION_SHIFT 16 | |
240 | ||
241 | /* | |
242 | * Software-defined protocol header | |
243 | */ | |
244 | ||
245 | /* Current protocol version */ | |
246 | #define SDPCM_PROT_VERSION 4 | |
247 | ||
248 | /* SW frame header */ | |
249 | #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff) | |
250 | ||
251 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
252 | #define SDPCM_CHANNEL_SHIFT 8 | |
253 | #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f) | |
254 | ||
255 | #define SDPCM_NEXTLEN_OFFSET 2 | |
256 | ||
257 | /* Data Offset from SOF (HW Tag, SW Tag, Pad) */ | |
258 | #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ | |
259 | #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) | |
260 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
261 | #define SDPCM_DOFFSET_SHIFT 24 | |
262 | #define SDPCM_FCMASK_OFFSET 4 /* Flow control */ | |
263 | #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff) | |
264 | #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ | |
265 | #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) | |
266 | ||
267 | #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ | |
268 | ||
269 | /* logical channel numbers */ | |
270 | #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */ | |
271 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ | |
272 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ | |
273 | #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */ | |
274 | #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ | |
275 | ||
276 | #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */ | |
277 | ||
278 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
279 | ||
280 | /* | |
281 | * Shared structure between dongle and the host. | |
282 | * The structure contains pointers to trap or assert information. | |
283 | */ | |
284 | #define SDPCM_SHARED_VERSION 0x0002 | |
285 | #define SDPCM_SHARED_VERSION_MASK 0x00FF | |
286 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
287 | #define SDPCM_SHARED_ASSERT 0x0200 | |
288 | #define SDPCM_SHARED_TRAP 0x0400 | |
289 | ||
290 | /* Space for header read, limit for data packets */ | |
291 | #define MAX_HDR_READ (1 << 6) | |
292 | #define MAX_RX_DATASZ 2048 | |
293 | ||
294 | /* Maximum milliseconds to wait for F2 to come up */ | |
295 | #define BRCMF_WAIT_F2RDY 3000 | |
296 | ||
297 | /* Bump up limit on waiting for HT to account for first startup; | |
298 | * if the image is doing a CRC calculation before programming the PMU | |
299 | * for HT availability, it could take a couple hundred ms more, so | |
300 | * max out at a 1 second (1000000us). | |
301 | */ | |
302 | #undef PMU_MAX_TRANSITION_DLY | |
303 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
304 | ||
305 | /* Value for ChipClockCSR during initial setup */ | |
306 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
307 | SBSDIO_ALP_AVAIL_REQ) | |
308 | ||
309 | /* Flags for SDH calls */ | |
310 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
311 | ||
52e1409f AS |
312 | #define BRCMF_SDIO_FW_NAME "brcm/brcmfmac-sdio.bin" |
313 | #define BRCMF_SDIO_NV_NAME "brcm/brcmfmac-sdio.txt" | |
314 | MODULE_FIRMWARE(BRCMF_SDIO_FW_NAME); | |
315 | MODULE_FIRMWARE(BRCMF_SDIO_NV_NAME); | |
8dd939ca | 316 | |
382a9e0f FL |
317 | #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */ |
318 | #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change | |
319 | * when idle | |
320 | */ | |
321 | #define BRCMF_IDLE_INTERVAL 1 | |
322 | ||
5b435de0 AS |
323 | /* |
324 | * Conversion of 802.1D priority to precedence level | |
325 | */ | |
326 | static uint prio2prec(u32 prio) | |
327 | { | |
328 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
329 | (prio^2) : prio; | |
330 | } | |
331 | ||
5b435de0 AS |
332 | /* core registers */ |
333 | struct sdpcmd_regs { | |
334 | u32 corecontrol; /* 0x00, rev8 */ | |
335 | u32 corestatus; /* rev8 */ | |
336 | u32 PAD[1]; | |
337 | u32 biststatus; /* rev8 */ | |
338 | ||
339 | /* PCMCIA access */ | |
340 | u16 pcmciamesportaladdr; /* 0x010, rev8 */ | |
341 | u16 PAD[1]; | |
342 | u16 pcmciamesportalmask; /* rev8 */ | |
343 | u16 PAD[1]; | |
344 | u16 pcmciawrframebc; /* rev8 */ | |
345 | u16 PAD[1]; | |
346 | u16 pcmciaunderflowtimer; /* rev8 */ | |
347 | u16 PAD[1]; | |
348 | ||
349 | /* interrupt */ | |
350 | u32 intstatus; /* 0x020, rev8 */ | |
351 | u32 hostintmask; /* rev8 */ | |
352 | u32 intmask; /* rev8 */ | |
353 | u32 sbintstatus; /* rev8 */ | |
354 | u32 sbintmask; /* rev8 */ | |
355 | u32 funcintmask; /* rev4 */ | |
356 | u32 PAD[2]; | |
357 | u32 tosbmailbox; /* 0x040, rev8 */ | |
358 | u32 tohostmailbox; /* rev8 */ | |
359 | u32 tosbmailboxdata; /* rev8 */ | |
360 | u32 tohostmailboxdata; /* rev8 */ | |
361 | ||
362 | /* synchronized access to registers in SDIO clock domain */ | |
363 | u32 sdioaccess; /* 0x050, rev8 */ | |
364 | u32 PAD[3]; | |
365 | ||
366 | /* PCMCIA frame control */ | |
367 | u8 pcmciaframectrl; /* 0x060, rev8 */ | |
368 | u8 PAD[3]; | |
369 | u8 pcmciawatermark; /* rev8 */ | |
370 | u8 PAD[155]; | |
371 | ||
372 | /* interrupt batching control */ | |
373 | u32 intrcvlazy; /* 0x100, rev8 */ | |
374 | u32 PAD[3]; | |
375 | ||
376 | /* counters */ | |
377 | u32 cmd52rd; /* 0x110, rev8 */ | |
378 | u32 cmd52wr; /* rev8 */ | |
379 | u32 cmd53rd; /* rev8 */ | |
380 | u32 cmd53wr; /* rev8 */ | |
381 | u32 abort; /* rev8 */ | |
382 | u32 datacrcerror; /* rev8 */ | |
383 | u32 rdoutofsync; /* rev8 */ | |
384 | u32 wroutofsync; /* rev8 */ | |
385 | u32 writebusy; /* rev8 */ | |
386 | u32 readwait; /* rev8 */ | |
387 | u32 readterm; /* rev8 */ | |
388 | u32 writeterm; /* rev8 */ | |
389 | u32 PAD[40]; | |
390 | u32 clockctlstatus; /* rev8 */ | |
391 | u32 PAD[7]; | |
392 | ||
393 | u32 PAD[128]; /* DMA engines */ | |
394 | ||
395 | /* SDIO/PCMCIA CIS region */ | |
396 | char cis[512]; /* 0x400-0x5ff, rev6 */ | |
397 | ||
398 | /* PCMCIA function control registers */ | |
399 | char pcmciafcr[256]; /* 0x600-6ff, rev6 */ | |
400 | u16 PAD[55]; | |
401 | ||
402 | /* PCMCIA backplane access */ | |
403 | u16 backplanecsr; /* 0x76E, rev6 */ | |
404 | u16 backplaneaddr0; /* rev6 */ | |
405 | u16 backplaneaddr1; /* rev6 */ | |
406 | u16 backplaneaddr2; /* rev6 */ | |
407 | u16 backplaneaddr3; /* rev6 */ | |
408 | u16 backplanedata0; /* rev6 */ | |
409 | u16 backplanedata1; /* rev6 */ | |
410 | u16 backplanedata2; /* rev6 */ | |
411 | u16 backplanedata3; /* rev6 */ | |
412 | u16 PAD[31]; | |
413 | ||
414 | /* sprom "size" & "blank" info */ | |
415 | u16 spromstatus; /* 0x7BE, rev2 */ | |
416 | u32 PAD[464]; | |
417 | ||
418 | u16 PAD[0x80]; | |
419 | }; | |
420 | ||
8ae74654 | 421 | #ifdef DEBUG |
5b435de0 AS |
422 | /* Device console log buffer state */ |
423 | struct brcmf_console { | |
424 | uint count; /* Poll interval msec counter */ | |
425 | uint log_addr; /* Log struct address (fixed) */ | |
426 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
427 | uint bufsize; /* Size of log buffer */ | |
428 | u8 *buf; /* Log buffer (host copy) */ | |
429 | uint last; /* Last buffer read index */ | |
430 | }; | |
8ae74654 | 431 | #endif /* DEBUG */ |
5b435de0 AS |
432 | |
433 | struct sdpcm_shared { | |
434 | u32 flags; | |
435 | u32 trap_addr; | |
436 | u32 assert_exp_addr; | |
437 | u32 assert_file_addr; | |
438 | u32 assert_line; | |
439 | u32 console_addr; /* Address of struct rte_console */ | |
440 | u32 msgtrace_addr; | |
441 | u8 tag[32]; | |
442 | }; | |
443 | ||
444 | struct sdpcm_shared_le { | |
445 | __le32 flags; | |
446 | __le32 trap_addr; | |
447 | __le32 assert_exp_addr; | |
448 | __le32 assert_file_addr; | |
449 | __le32 assert_line; | |
450 | __le32 console_addr; /* Address of struct rte_console */ | |
451 | __le32 msgtrace_addr; | |
452 | u8 tag[32]; | |
453 | }; | |
454 | ||
455 | ||
456 | /* misc chip info needed by some of the routines */ | |
5b435de0 | 457 | /* Private data for SDIO bus interaction */ |
e92eedf4 | 458 | struct brcmf_sdio { |
5b435de0 AS |
459 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ |
460 | struct chip_info *ci; /* Chip info struct */ | |
461 | char *vars; /* Variables (from CIS and/or other) */ | |
462 | uint varsz; /* Size of variables buffer */ | |
463 | ||
464 | u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
465 | ||
466 | u32 hostintmask; /* Copy of Host Interrupt Mask */ | |
467 | u32 intstatus; /* Intstatus bits (events) pending */ | |
468 | bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ | |
469 | bool fcstate; /* State of dongle flow-control */ | |
470 | ||
471 | uint blocksize; /* Block size of SDIO transfers */ | |
472 | uint roundup; /* Max roundup limit */ | |
473 | ||
474 | struct pktq txq; /* Queue length used for flow-control */ | |
475 | u8 flowcontrol; /* per prio flow control bitmask */ | |
476 | u8 tx_seq; /* Transmit sequence number (next) */ | |
477 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
478 | ||
479 | u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN]; | |
480 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ | |
481 | u16 nextlen; /* Next Read Len from last header */ | |
482 | u8 rx_seq; /* Receive sequence number (expected) */ | |
483 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ | |
484 | ||
485 | uint rxbound; /* Rx frames to read before resched */ | |
486 | uint txbound; /* Tx frames to send before resched */ | |
487 | uint txminmax; | |
488 | ||
489 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
b83db862 | 490 | struct sk_buff_head glom; /* Packet list for glommed superframe */ |
5b435de0 AS |
491 | uint glomerr; /* Glom packet read errors */ |
492 | ||
493 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
494 | uint rxblen; /* Allocated length of rxbuf */ | |
495 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
496 | u8 *databuf; /* Buffer for receiving big glom packet */ | |
497 | u8 *dataptr; /* Aligned pointer into databuf */ | |
498 | uint rxlen; /* Length of valid data in buffer */ | |
499 | ||
500 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
501 | ||
502 | bool intr; /* Use interrupts */ | |
503 | bool poll; /* Use polling */ | |
504 | bool ipend; /* Device interrupt is pending */ | |
505 | uint intrcount; /* Count of device interrupt callbacks */ | |
506 | uint lastintrs; /* Count as of last watchdog timer */ | |
507 | uint spurious; /* Count of spurious interrupts */ | |
508 | uint pollrate; /* Ticks between device polls */ | |
509 | uint polltick; /* Tick counter */ | |
510 | uint pollcnt; /* Count of active polls */ | |
511 | ||
8ae74654 | 512 | #ifdef DEBUG |
5b435de0 AS |
513 | uint console_interval; |
514 | struct brcmf_console console; /* Console output polling support */ | |
515 | uint console_addr; /* Console address from shared struct */ | |
8ae74654 | 516 | #endif /* DEBUG */ |
5b435de0 AS |
517 | |
518 | uint regfails; /* Count of R_REG failures */ | |
519 | ||
520 | uint clkstate; /* State of sd and backplane clock(s) */ | |
521 | bool activity; /* Activity flag for clock down */ | |
522 | s32 idletime; /* Control for activity timeout */ | |
523 | s32 idlecount; /* Activity timeout counter */ | |
524 | s32 idleclock; /* How to set bus driver when idle */ | |
525 | s32 sd_rxchain; | |
526 | bool use_rxchain; /* If brcmf should use PKT chains */ | |
527 | bool sleeping; /* Is SDIO bus sleeping? */ | |
528 | bool rxflow_mode; /* Rx flow control mode */ | |
529 | bool rxflow; /* Is rx flow control on */ | |
530 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
531 | /* Field to decide if rx of control frames happen in rxbuf or lb-pool */ | |
532 | bool usebufpool; | |
533 | ||
534 | /* Some additional counters */ | |
535 | uint tx_sderrs; /* Count of tx attempts with sd errors */ | |
536 | uint fcqueued; /* Tx packets that got queued */ | |
537 | uint rxrtx; /* Count of rtx requests (NAK to dongle) */ | |
538 | uint rx_toolong; /* Receive frames too long to receive */ | |
539 | uint rxc_errors; /* SDIO errors when reading control frames */ | |
540 | uint rx_hdrfail; /* SDIO errors on header reads */ | |
541 | uint rx_badhdr; /* Bad received headers (roosync?) */ | |
542 | uint rx_badseq; /* Mismatched rx sequence number */ | |
543 | uint fc_rcvd; /* Number of flow-control events received */ | |
544 | uint fc_xoff; /* Number which turned on flow-control */ | |
545 | uint fc_xon; /* Number which turned off flow-control */ | |
546 | uint rxglomfail; /* Failed deglom attempts */ | |
547 | uint rxglomframes; /* Number of glom frames (superframes) */ | |
548 | uint rxglompkts; /* Number of packets from glom frames */ | |
549 | uint f2rxhdrs; /* Number of header reads */ | |
550 | uint f2rxdata; /* Number of frame data reads */ | |
551 | uint f2txdata; /* Number of f2 frame writes */ | |
552 | uint f1regdata; /* Number of f1 register accesses */ | |
28a1a3bd FL |
553 | uint tickcnt; /* Number of watchdog been schedule */ |
554 | unsigned long tx_ctlerrs; /* Err of sending ctrl frames */ | |
555 | unsigned long tx_ctlpkts; /* Ctrl frames sent to dongle */ | |
556 | unsigned long rx_ctlerrs; /* Err of processing rx ctrl frames */ | |
557 | unsigned long rx_ctlpkts; /* Ctrl frames processed from dongle */ | |
558 | unsigned long rx_readahead_cnt; /* Number of packets where header | |
559 | * read-ahead was used. */ | |
5b435de0 AS |
560 | |
561 | u8 *ctrl_frame_buf; | |
562 | u32 ctrl_frame_len; | |
563 | bool ctrl_frame_stat; | |
564 | ||
565 | spinlock_t txqlock; | |
566 | wait_queue_head_t ctrl_wait; | |
567 | wait_queue_head_t dcmd_resp_wait; | |
568 | ||
569 | struct timer_list timer; | |
570 | struct completion watchdog_wait; | |
571 | struct task_struct *watchdog_tsk; | |
572 | bool wd_timer_valid; | |
573 | uint save_ms; | |
574 | ||
575 | struct task_struct *dpc_tsk; | |
576 | struct completion dpc_wait; | |
b948a85c FL |
577 | struct list_head dpc_tsklst; |
578 | spinlock_t dpc_tl_lock; | |
5b435de0 AS |
579 | |
580 | struct semaphore sdsem; | |
581 | ||
5b435de0 | 582 | const struct firmware *firmware; |
5b435de0 | 583 | u32 fw_ptr; |
c8bf3484 FL |
584 | |
585 | bool txoff; /* Transmit flow-controlled */ | |
5b435de0 AS |
586 | }; |
587 | ||
5b435de0 AS |
588 | /* clkstate */ |
589 | #define CLK_NONE 0 | |
590 | #define CLK_SDONLY 1 | |
591 | #define CLK_PENDING 2 /* Not used yet */ | |
592 | #define CLK_AVAIL 3 | |
593 | ||
8ae74654 | 594 | #ifdef DEBUG |
5b435de0 AS |
595 | static int qcount[NUMPRIO]; |
596 | static int tx_packets[NUMPRIO]; | |
8ae74654 | 597 | #endif /* DEBUG */ |
5b435de0 AS |
598 | |
599 | #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */ | |
600 | ||
601 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
602 | ||
603 | /* Retry count for register access failures */ | |
604 | static const uint retry_limit = 2; | |
605 | ||
606 | /* Limit on rounding up frames */ | |
607 | static const uint max_roundup = 512; | |
608 | ||
609 | #define ALIGNMENT 4 | |
610 | ||
611 | static void pkt_align(struct sk_buff *p, int len, int align) | |
612 | { | |
613 | uint datalign; | |
614 | datalign = (unsigned long)(p->data); | |
615 | datalign = roundup(datalign, (align)) - datalign; | |
616 | if (datalign) | |
617 | skb_pull(p, datalign); | |
618 | __skb_trim(p, len); | |
619 | } | |
620 | ||
621 | /* To check if there's window offered */ | |
e92eedf4 | 622 | static bool data_ok(struct brcmf_sdio *bus) |
5b435de0 AS |
623 | { |
624 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
625 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
626 | } | |
627 | ||
628 | /* | |
629 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
630 | * adresses on the 32 bit backplane bus. | |
631 | */ | |
632 | static void | |
e92eedf4 | 633 | r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 reg_offset, u32 *retryvar) |
5b435de0 | 634 | { |
99ba15cd | 635 | u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
5b435de0 AS |
636 | *retryvar = 0; |
637 | do { | |
638 | *regvar = brcmf_sdcard_reg_read(bus->sdiodev, | |
abb7fbb4 | 639 | bus->ci->c_inf[idx].base + reg_offset); |
5b435de0 AS |
640 | } while (brcmf_sdcard_regfail(bus->sdiodev) && |
641 | (++(*retryvar) <= retry_limit)); | |
642 | if (*retryvar) { | |
643 | bus->regfails += (*retryvar-1); | |
644 | if (*retryvar > retry_limit) { | |
645 | brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset); | |
646 | *regvar = 0; | |
647 | } | |
648 | } | |
649 | } | |
650 | ||
651 | static void | |
e92eedf4 | 652 | w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset, u32 *retryvar) |
5b435de0 | 653 | { |
99ba15cd | 654 | u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
5b435de0 AS |
655 | *retryvar = 0; |
656 | do { | |
657 | brcmf_sdcard_reg_write(bus->sdiodev, | |
99ba15cd | 658 | bus->ci->c_inf[idx].base + reg_offset, |
ce454e88 | 659 | regval); |
5b435de0 AS |
660 | } while (brcmf_sdcard_regfail(bus->sdiodev) && |
661 | (++(*retryvar) <= retry_limit)); | |
662 | if (*retryvar) { | |
663 | bus->regfails += (*retryvar-1); | |
664 | if (*retryvar > retry_limit) | |
665 | brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n", | |
666 | reg_offset); | |
667 | } | |
668 | } | |
669 | ||
670 | #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND) | |
671 | ||
672 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) | |
673 | ||
674 | /* Packet free applicable unconditionally for sdio and sdspi. | |
675 | * Conditional if bufpool was present for gspi bus. | |
676 | */ | |
e92eedf4 | 677 | static void brcmf_sdbrcm_pktfree2(struct brcmf_sdio *bus, struct sk_buff *pkt) |
5b435de0 AS |
678 | { |
679 | if (bus->usebufpool) | |
680 | brcmu_pkt_buf_free_skb(pkt); | |
681 | } | |
682 | ||
683 | /* Turn backplane clock on or off */ | |
e92eedf4 | 684 | static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok) |
5b435de0 AS |
685 | { |
686 | int err; | |
687 | u8 clkctl, clkreq, devctl; | |
688 | unsigned long timeout; | |
689 | ||
690 | brcmf_dbg(TRACE, "Enter\n"); | |
691 | ||
692 | clkctl = 0; | |
693 | ||
694 | if (on) { | |
695 | /* Request HT Avail */ | |
696 | clkreq = | |
697 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
698 | ||
5b435de0 AS |
699 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, |
700 | SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); | |
701 | if (err) { | |
702 | brcmf_dbg(ERROR, "HT Avail request error: %d\n", err); | |
703 | return -EBADE; | |
704 | } | |
705 | ||
5b435de0 AS |
706 | /* Check current status */ |
707 | clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
708 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
709 | if (err) { | |
710 | brcmf_dbg(ERROR, "HT Avail read error: %d\n", err); | |
711 | return -EBADE; | |
712 | } | |
713 | ||
714 | /* Go to pending and await interrupt if appropriate */ | |
715 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
716 | /* Allow only clock-available interrupt */ | |
717 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
718 | SDIO_FUNC_1, | |
719 | SBSDIO_DEVICE_CTL, &err); | |
720 | if (err) { | |
721 | brcmf_dbg(ERROR, "Devctl error setting CA: %d\n", | |
722 | err); | |
723 | return -EBADE; | |
724 | } | |
725 | ||
726 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
727 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
728 | SBSDIO_DEVICE_CTL, devctl, &err); | |
729 | brcmf_dbg(INFO, "CLKCTL: set PENDING\n"); | |
730 | bus->clkstate = CLK_PENDING; | |
731 | ||
732 | return 0; | |
733 | } else if (bus->clkstate == CLK_PENDING) { | |
734 | /* Cancel CA-only interrupt filter */ | |
735 | devctl = | |
736 | brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
737 | SBSDIO_DEVICE_CTL, &err); | |
738 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
739 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
740 | SBSDIO_DEVICE_CTL, devctl, &err); | |
741 | } | |
742 | ||
743 | /* Otherwise, wait here (polling) for HT Avail */ | |
744 | timeout = jiffies + | |
745 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
746 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
747 | clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
748 | SDIO_FUNC_1, | |
749 | SBSDIO_FUNC1_CHIPCLKCSR, | |
750 | &err); | |
751 | if (time_after(jiffies, timeout)) | |
752 | break; | |
753 | else | |
754 | usleep_range(5000, 10000); | |
755 | } | |
756 | if (err) { | |
757 | brcmf_dbg(ERROR, "HT Avail request error: %d\n", err); | |
758 | return -EBADE; | |
759 | } | |
760 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
761 | brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n", | |
762 | PMU_MAX_TRANSITION_DLY, clkctl); | |
763 | return -EBADE; | |
764 | } | |
765 | ||
766 | /* Mark clock available */ | |
767 | bus->clkstate = CLK_AVAIL; | |
768 | brcmf_dbg(INFO, "CLKCTL: turned ON\n"); | |
769 | ||
8ae74654 | 770 | #if defined(DEBUG) |
23677ce3 | 771 | if (!bus->alp_only) { |
5b435de0 AS |
772 | if (SBSDIO_ALPONLY(clkctl)) |
773 | brcmf_dbg(ERROR, "HT Clock should be on\n"); | |
774 | } | |
8ae74654 | 775 | #endif /* defined (DEBUG) */ |
5b435de0 AS |
776 | |
777 | bus->activity = true; | |
778 | } else { | |
779 | clkreq = 0; | |
780 | ||
781 | if (bus->clkstate == CLK_PENDING) { | |
782 | /* Cancel CA-only interrupt filter */ | |
783 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
784 | SDIO_FUNC_1, | |
785 | SBSDIO_DEVICE_CTL, &err); | |
786 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
787 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
788 | SBSDIO_DEVICE_CTL, devctl, &err); | |
789 | } | |
790 | ||
791 | bus->clkstate = CLK_SDONLY; | |
792 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
793 | SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); | |
794 | brcmf_dbg(INFO, "CLKCTL: turned OFF\n"); | |
795 | if (err) { | |
796 | brcmf_dbg(ERROR, "Failed access turning clock off: %d\n", | |
797 | err); | |
798 | return -EBADE; | |
799 | } | |
800 | } | |
801 | return 0; | |
802 | } | |
803 | ||
804 | /* Change idle/active SD state */ | |
e92eedf4 | 805 | static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on) |
5b435de0 AS |
806 | { |
807 | brcmf_dbg(TRACE, "Enter\n"); | |
808 | ||
809 | if (on) | |
810 | bus->clkstate = CLK_SDONLY; | |
811 | else | |
812 | bus->clkstate = CLK_NONE; | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | /* Transition SD and backplane clock readiness */ | |
e92eedf4 | 818 | static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) |
5b435de0 | 819 | { |
8ae74654 | 820 | #ifdef DEBUG |
5b435de0 | 821 | uint oldstate = bus->clkstate; |
8ae74654 | 822 | #endif /* DEBUG */ |
5b435de0 AS |
823 | |
824 | brcmf_dbg(TRACE, "Enter\n"); | |
825 | ||
826 | /* Early exit if we're already there */ | |
827 | if (bus->clkstate == target) { | |
828 | if (target == CLK_AVAIL) { | |
829 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
830 | bus->activity = true; | |
831 | } | |
832 | return 0; | |
833 | } | |
834 | ||
835 | switch (target) { | |
836 | case CLK_AVAIL: | |
837 | /* Make sure SD clock is available */ | |
838 | if (bus->clkstate == CLK_NONE) | |
839 | brcmf_sdbrcm_sdclk(bus, true); | |
840 | /* Now request HT Avail on the backplane */ | |
841 | brcmf_sdbrcm_htclk(bus, true, pendok); | |
842 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
843 | bus->activity = true; | |
844 | break; | |
845 | ||
846 | case CLK_SDONLY: | |
847 | /* Remove HT request, or bring up SD clock */ | |
848 | if (bus->clkstate == CLK_NONE) | |
849 | brcmf_sdbrcm_sdclk(bus, true); | |
850 | else if (bus->clkstate == CLK_AVAIL) | |
851 | brcmf_sdbrcm_htclk(bus, false, false); | |
852 | else | |
853 | brcmf_dbg(ERROR, "request for %d -> %d\n", | |
854 | bus->clkstate, target); | |
855 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
856 | break; | |
857 | ||
858 | case CLK_NONE: | |
859 | /* Make sure to remove HT request */ | |
860 | if (bus->clkstate == CLK_AVAIL) | |
861 | brcmf_sdbrcm_htclk(bus, false, false); | |
862 | /* Now remove the SD clock */ | |
863 | brcmf_sdbrcm_sdclk(bus, false); | |
864 | brcmf_sdbrcm_wd_timer(bus, 0); | |
865 | break; | |
866 | } | |
8ae74654 | 867 | #ifdef DEBUG |
5b435de0 | 868 | brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate); |
8ae74654 | 869 | #endif /* DEBUG */ |
5b435de0 AS |
870 | |
871 | return 0; | |
872 | } | |
873 | ||
e92eedf4 | 874 | static int brcmf_sdbrcm_bussleep(struct brcmf_sdio *bus, bool sleep) |
5b435de0 AS |
875 | { |
876 | uint retries = 0; | |
877 | ||
878 | brcmf_dbg(INFO, "request %s (currently %s)\n", | |
879 | sleep ? "SLEEP" : "WAKE", | |
880 | bus->sleeping ? "SLEEP" : "WAKE"); | |
881 | ||
882 | /* Done if we're already in the requested state */ | |
883 | if (sleep == bus->sleeping) | |
884 | return 0; | |
885 | ||
886 | /* Going to sleep: set the alarm and turn off the lights... */ | |
887 | if (sleep) { | |
888 | /* Don't sleep if something is pending */ | |
889 | if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq)) | |
890 | return -EBUSY; | |
891 | ||
892 | /* Make sure the controller has the bus up */ | |
893 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
894 | ||
895 | /* Tell device to start using OOB wakeup */ | |
896 | w_sdreg32(bus, SMB_USE_OOB, | |
897 | offsetof(struct sdpcmd_regs, tosbmailbox), &retries); | |
898 | if (retries > retry_limit) | |
899 | brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"); | |
900 | ||
901 | /* Turn off our contribution to the HT clock request */ | |
902 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
903 | ||
904 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
905 | SBSDIO_FUNC1_CHIPCLKCSR, | |
906 | SBSDIO_FORCE_HW_CLKREQ_OFF, NULL); | |
907 | ||
908 | /* Isolate the bus */ | |
718897eb FL |
909 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, |
910 | SBSDIO_DEVICE_CTL, | |
911 | SBSDIO_DEVCTL_PADS_ISO, NULL); | |
5b435de0 AS |
912 | |
913 | /* Change state */ | |
914 | bus->sleeping = true; | |
915 | ||
916 | } else { | |
917 | /* Waking up: bus power up is ok, set local state */ | |
918 | ||
919 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
920 | SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
921 | ||
5b435de0 AS |
922 | /* Make sure the controller has the bus up */ |
923 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
924 | ||
925 | /* Send misc interrupt to indicate OOB not needed */ | |
926 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata), | |
927 | &retries); | |
928 | if (retries <= retry_limit) | |
929 | w_sdreg32(bus, SMB_DEV_INT, | |
930 | offsetof(struct sdpcmd_regs, tosbmailbox), | |
931 | &retries); | |
932 | ||
933 | if (retries > retry_limit) | |
934 | brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"); | |
935 | ||
936 | /* Make sure we have SD bus access */ | |
937 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
938 | ||
939 | /* Change state */ | |
940 | bus->sleeping = false; | |
941 | } | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
e92eedf4 | 946 | static void bus_wake(struct brcmf_sdio *bus) |
5b435de0 AS |
947 | { |
948 | if (bus->sleeping) | |
949 | brcmf_sdbrcm_bussleep(bus, false); | |
950 | } | |
951 | ||
e92eedf4 | 952 | static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus) |
5b435de0 AS |
953 | { |
954 | u32 intstatus = 0; | |
955 | u32 hmb_data; | |
956 | u8 fcbits; | |
957 | uint retries = 0; | |
958 | ||
959 | brcmf_dbg(TRACE, "Enter\n"); | |
960 | ||
961 | /* Read mailbox data and ack that we did so */ | |
962 | r_sdreg32(bus, &hmb_data, | |
963 | offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries); | |
964 | ||
965 | if (retries <= retry_limit) | |
966 | w_sdreg32(bus, SMB_INT_ACK, | |
967 | offsetof(struct sdpcmd_regs, tosbmailbox), &retries); | |
968 | bus->f1regdata += 2; | |
969 | ||
970 | /* Dongle recomposed rx frames, accept them again */ | |
971 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
972 | brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n", | |
973 | bus->rx_seq); | |
974 | if (!bus->rxskip) | |
975 | brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n"); | |
976 | ||
977 | bus->rxskip = false; | |
978 | intstatus |= I_HMB_FRAME_IND; | |
979 | } | |
980 | ||
981 | /* | |
982 | * DEVREADY does not occur with gSPI. | |
983 | */ | |
984 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
985 | bus->sdpcm_ver = | |
986 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
987 | HMB_DATA_VERSION_SHIFT; | |
988 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
989 | brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, " | |
990 | "expecting %d\n", | |
991 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
992 | else | |
993 | brcmf_dbg(INFO, "Dongle ready, protocol version %d\n", | |
994 | bus->sdpcm_ver); | |
995 | } | |
996 | ||
997 | /* | |
998 | * Flow Control has been moved into the RX headers and this out of band | |
999 | * method isn't used any more. | |
1000 | * remaining backward compatible with older dongles. | |
1001 | */ | |
1002 | if (hmb_data & HMB_DATA_FC) { | |
1003 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
1004 | HMB_DATA_FCDATA_SHIFT; | |
1005 | ||
1006 | if (fcbits & ~bus->flowcontrol) | |
1007 | bus->fc_xoff++; | |
1008 | ||
1009 | if (bus->flowcontrol & ~fcbits) | |
1010 | bus->fc_xon++; | |
1011 | ||
1012 | bus->fc_rcvd++; | |
1013 | bus->flowcontrol = fcbits; | |
1014 | } | |
1015 | ||
1016 | /* Shouldn't be any others */ | |
1017 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1018 | HMB_DATA_NAKHANDLED | | |
1019 | HMB_DATA_FC | | |
1020 | HMB_DATA_FWREADY | | |
1021 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
1022 | brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n", | |
1023 | hmb_data); | |
1024 | ||
1025 | return intstatus; | |
1026 | } | |
1027 | ||
e92eedf4 | 1028 | static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) |
5b435de0 AS |
1029 | { |
1030 | uint retries = 0; | |
1031 | u16 lastrbc; | |
1032 | u8 hi, lo; | |
1033 | int err; | |
1034 | ||
1035 | brcmf_dbg(ERROR, "%sterminate frame%s\n", | |
1036 | abort ? "abort command, " : "", | |
1037 | rtx ? ", send NAK" : ""); | |
1038 | ||
1039 | if (abort) | |
1040 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
1041 | ||
1042 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
1043 | SBSDIO_FUNC1_FRAMECTRL, | |
1044 | SFC_RF_TERM, &err); | |
1045 | bus->f1regdata++; | |
1046 | ||
1047 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1048 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
1049 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
1050 | SBSDIO_FUNC1_RFRAMEBCHI, NULL); | |
1051 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
1052 | SBSDIO_FUNC1_RFRAMEBCLO, NULL); | |
1053 | bus->f1regdata += 2; | |
1054 | ||
1055 | if ((hi == 0) && (lo == 0)) | |
1056 | break; | |
1057 | ||
1058 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
1059 | brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n", | |
1060 | lastrbc, (hi << 8) + lo); | |
1061 | } | |
1062 | lastrbc = (hi << 8) + lo; | |
1063 | } | |
1064 | ||
1065 | if (!retries) | |
1066 | brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc); | |
1067 | else | |
1068 | brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries); | |
1069 | ||
1070 | if (rtx) { | |
1071 | bus->rxrtx++; | |
1072 | w_sdreg32(bus, SMB_NAK, | |
1073 | offsetof(struct sdpcmd_regs, tosbmailbox), &retries); | |
1074 | ||
1075 | bus->f1regdata++; | |
1076 | if (retries <= retry_limit) | |
1077 | bus->rxskip = true; | |
1078 | } | |
1079 | ||
1080 | /* Clear partial in any case */ | |
1081 | bus->nextlen = 0; | |
1082 | ||
1083 | /* If we can't reach the device, signal failure */ | |
1084 | if (err || brcmf_sdcard_regfail(bus->sdiodev)) | |
712ac5b3 | 1085 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
1086 | } |
1087 | ||
20e5ca16 | 1088 | /* copy a buffer into a pkt buffer chain */ |
e92eedf4 | 1089 | static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_sdio *bus, uint len) |
20e5ca16 AS |
1090 | { |
1091 | uint n, ret = 0; | |
1092 | struct sk_buff *p; | |
1093 | u8 *buf; | |
1094 | ||
20e5ca16 AS |
1095 | buf = bus->dataptr; |
1096 | ||
1097 | /* copy the data */ | |
b83db862 | 1098 | skb_queue_walk(&bus->glom, p) { |
20e5ca16 AS |
1099 | n = min_t(uint, p->len, len); |
1100 | memcpy(p->data, buf, n); | |
1101 | buf += n; | |
1102 | len -= n; | |
1103 | ret += n; | |
b83db862 AS |
1104 | if (!len) |
1105 | break; | |
20e5ca16 AS |
1106 | } |
1107 | ||
1108 | return ret; | |
1109 | } | |
1110 | ||
9a95e60e | 1111 | /* return total length of buffer chain */ |
e92eedf4 | 1112 | static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus) |
9a95e60e AS |
1113 | { |
1114 | struct sk_buff *p; | |
1115 | uint total; | |
1116 | ||
1117 | total = 0; | |
1118 | skb_queue_walk(&bus->glom, p) | |
1119 | total += p->len; | |
1120 | return total; | |
1121 | } | |
1122 | ||
e92eedf4 | 1123 | static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus) |
046808da AS |
1124 | { |
1125 | struct sk_buff *cur, *next; | |
1126 | ||
1127 | skb_queue_walk_safe(&bus->glom, cur, next) { | |
1128 | skb_unlink(cur, &bus->glom); | |
1129 | brcmu_pkt_buf_free_skb(cur); | |
1130 | } | |
1131 | } | |
1132 | ||
e92eedf4 | 1133 | static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq) |
5b435de0 AS |
1134 | { |
1135 | u16 dlen, totlen; | |
1136 | u8 *dptr, num = 0; | |
1137 | ||
1138 | u16 sublen, check; | |
0b45bf74 | 1139 | struct sk_buff *pfirst, *pnext; |
5b435de0 AS |
1140 | |
1141 | int errcode; | |
1142 | u8 chan, seq, doff, sfdoff; | |
1143 | u8 txmax; | |
1144 | ||
1145 | int ifidx = 0; | |
1146 | bool usechain = bus->use_rxchain; | |
1147 | ||
1148 | /* If packets, issue read(s) and send up packet chain */ | |
1149 | /* Return sequence numbers consumed? */ | |
1150 | ||
b83db862 AS |
1151 | brcmf_dbg(TRACE, "start: glomd %p glom %p\n", |
1152 | bus->glomd, skb_peek(&bus->glom)); | |
5b435de0 AS |
1153 | |
1154 | /* If there's a descriptor, generate the packet chain */ | |
1155 | if (bus->glomd) { | |
0b45bf74 | 1156 | pfirst = pnext = NULL; |
5b435de0 AS |
1157 | dlen = (u16) (bus->glomd->len); |
1158 | dptr = bus->glomd->data; | |
1159 | if (!dlen || (dlen & 1)) { | |
1160 | brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n", | |
1161 | dlen); | |
1162 | dlen = 0; | |
1163 | } | |
1164 | ||
1165 | for (totlen = num = 0; dlen; num++) { | |
1166 | /* Get (and move past) next length */ | |
1167 | sublen = get_unaligned_le16(dptr); | |
1168 | dlen -= sizeof(u16); | |
1169 | dptr += sizeof(u16); | |
1170 | if ((sublen < SDPCM_HDRLEN) || | |
1171 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
1172 | brcmf_dbg(ERROR, "descriptor len %d bad: %d\n", | |
1173 | num, sublen); | |
1174 | pnext = NULL; | |
1175 | break; | |
1176 | } | |
1177 | if (sublen % BRCMF_SDALIGN) { | |
1178 | brcmf_dbg(ERROR, "sublen %d not multiple of %d\n", | |
1179 | sublen, BRCMF_SDALIGN); | |
1180 | usechain = false; | |
1181 | } | |
1182 | totlen += sublen; | |
1183 | ||
1184 | /* For last frame, adjust read len so total | |
1185 | is a block multiple */ | |
1186 | if (!dlen) { | |
1187 | sublen += | |
1188 | (roundup(totlen, bus->blocksize) - totlen); | |
1189 | totlen = roundup(totlen, bus->blocksize); | |
1190 | } | |
1191 | ||
1192 | /* Allocate/chain packet for next subframe */ | |
1193 | pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN); | |
1194 | if (pnext == NULL) { | |
1195 | brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n", | |
1196 | num, sublen); | |
1197 | break; | |
1198 | } | |
b83db862 | 1199 | skb_queue_tail(&bus->glom, pnext); |
5b435de0 AS |
1200 | |
1201 | /* Adhere to start alignment requirements */ | |
1202 | pkt_align(pnext, sublen, BRCMF_SDALIGN); | |
1203 | } | |
1204 | ||
1205 | /* If all allocations succeeded, save packet chain | |
1206 | in bus structure */ | |
1207 | if (pnext) { | |
1208 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1209 | totlen, num); | |
1210 | if (BRCMF_GLOM_ON() && bus->nextlen && | |
1211 | totlen != bus->nextlen) { | |
1212 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", | |
1213 | bus->nextlen, totlen, rxseq); | |
1214 | } | |
5b435de0 AS |
1215 | pfirst = pnext = NULL; |
1216 | } else { | |
046808da | 1217 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 AS |
1218 | num = 0; |
1219 | } | |
1220 | ||
1221 | /* Done with descriptor packet */ | |
1222 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1223 | bus->glomd = NULL; | |
1224 | bus->nextlen = 0; | |
1225 | } | |
1226 | ||
1227 | /* Ok -- either we just generated a packet chain, | |
1228 | or had one from before */ | |
b83db862 | 1229 | if (!skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1230 | if (BRCMF_GLOM_ON()) { |
1231 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
b83db862 | 1232 | skb_queue_walk(&bus->glom, pnext) { |
5b435de0 AS |
1233 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", |
1234 | pnext, (u8 *) (pnext->data), | |
1235 | pnext->len, pnext->len); | |
1236 | } | |
1237 | } | |
1238 | ||
b83db862 | 1239 | pfirst = skb_peek(&bus->glom); |
9a95e60e | 1240 | dlen = (u16) brcmf_sdbrcm_glom_len(bus); |
5b435de0 AS |
1241 | |
1242 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1243 | * read directly into the chained packet, or allocate a large | |
1244 | * packet and and copy into the chain. | |
1245 | */ | |
1246 | if (usechain) { | |
5adfeb63 | 1247 | errcode = brcmf_sdcard_recv_chain(bus->sdiodev, |
5b435de0 | 1248 | bus->sdiodev->sbwad, |
5adfeb63 | 1249 | SDIO_FUNC_2, F2SYNC, &bus->glom); |
5b435de0 AS |
1250 | } else if (bus->dataptr) { |
1251 | errcode = brcmf_sdcard_recv_buf(bus->sdiodev, | |
1252 | bus->sdiodev->sbwad, | |
5adfeb63 AS |
1253 | SDIO_FUNC_2, F2SYNC, |
1254 | bus->dataptr, dlen); | |
20e5ca16 | 1255 | sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen); |
5b435de0 AS |
1256 | if (sublen != dlen) { |
1257 | brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n", | |
1258 | dlen, sublen); | |
1259 | errcode = -1; | |
1260 | } | |
1261 | pnext = NULL; | |
1262 | } else { | |
1263 | brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n", | |
1264 | dlen); | |
1265 | errcode = -1; | |
1266 | } | |
1267 | bus->f2rxdata++; | |
1268 | ||
1269 | /* On failure, kill the superframe, allow a couple retries */ | |
1270 | if (errcode < 0) { | |
1271 | brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n", | |
1272 | dlen, errcode); | |
719f2733 | 1273 | bus->sdiodev->bus_if->dstats.rx_errors++; |
5b435de0 AS |
1274 | |
1275 | if (bus->glomerr++ < 3) { | |
1276 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1277 | } else { | |
1278 | bus->glomerr = 0; | |
1279 | brcmf_sdbrcm_rxfail(bus, true, false); | |
5b435de0 | 1280 | bus->rxglomfail++; |
046808da | 1281 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 AS |
1282 | } |
1283 | return 0; | |
1284 | } | |
1e023829 JP |
1285 | |
1286 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), | |
1287 | pfirst->data, min_t(int, pfirst->len, 48), | |
1288 | "SUPERFRAME:\n"); | |
5b435de0 AS |
1289 | |
1290 | /* Validate the superframe header */ | |
1291 | dptr = (u8 *) (pfirst->data); | |
1292 | sublen = get_unaligned_le16(dptr); | |
1293 | check = get_unaligned_le16(dptr + sizeof(u16)); | |
1294 | ||
1295 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
1296 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1297 | bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET]; | |
1298 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
1299 | brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n", | |
1300 | bus->nextlen, seq); | |
1301 | bus->nextlen = 0; | |
1302 | } | |
1303 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1304 | txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1305 | ||
1306 | errcode = 0; | |
1307 | if ((u16)~(sublen ^ check)) { | |
1308 | brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n", | |
1309 | sublen, check); | |
1310 | errcode = -1; | |
1311 | } else if (roundup(sublen, bus->blocksize) != dlen) { | |
1312 | brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n", | |
1313 | sublen, roundup(sublen, bus->blocksize), | |
1314 | dlen); | |
1315 | errcode = -1; | |
1316 | } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) != | |
1317 | SDPCM_GLOM_CHANNEL) { | |
1318 | brcmf_dbg(ERROR, "(superframe): bad channel %d\n", | |
1319 | SDPCM_PACKET_CHANNEL( | |
1320 | &dptr[SDPCM_FRAMETAG_LEN])); | |
1321 | errcode = -1; | |
1322 | } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) { | |
1323 | brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n"); | |
1324 | errcode = -1; | |
1325 | } else if ((doff < SDPCM_HDRLEN) || | |
1326 | (doff > (pfirst->len - SDPCM_HDRLEN))) { | |
1327 | brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n", | |
1328 | doff, sublen, pfirst->len, SDPCM_HDRLEN); | |
1329 | errcode = -1; | |
1330 | } | |
1331 | ||
1332 | /* Check sequence number of superframe SW header */ | |
1333 | if (rxseq != seq) { | |
1334 | brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n", | |
1335 | seq, rxseq); | |
1336 | bus->rx_badseq++; | |
1337 | rxseq = seq; | |
1338 | } | |
1339 | ||
1340 | /* Check window for sanity */ | |
1341 | if ((u8) (txmax - bus->tx_seq) > 0x40) { | |
1342 | brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n", | |
1343 | txmax, bus->tx_seq); | |
1344 | txmax = bus->tx_seq + 2; | |
1345 | } | |
1346 | bus->tx_max = txmax; | |
1347 | ||
1348 | /* Remove superframe header, remember offset */ | |
1349 | skb_pull(pfirst, doff); | |
1350 | sfdoff = doff; | |
0b45bf74 | 1351 | num = 0; |
5b435de0 AS |
1352 | |
1353 | /* Validate all the subframe headers */ | |
0b45bf74 AS |
1354 | skb_queue_walk(&bus->glom, pnext) { |
1355 | /* leave when invalid subframe is found */ | |
1356 | if (errcode) | |
1357 | break; | |
1358 | ||
5b435de0 AS |
1359 | dptr = (u8 *) (pnext->data); |
1360 | dlen = (u16) (pnext->len); | |
1361 | sublen = get_unaligned_le16(dptr); | |
1362 | check = get_unaligned_le16(dptr + sizeof(u16)); | |
1363 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
1364 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1e023829 JP |
1365 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1366 | dptr, 32, "subframe:\n"); | |
5b435de0 AS |
1367 | |
1368 | if ((u16)~(sublen ^ check)) { | |
1369 | brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n", | |
1370 | num, sublen, check); | |
1371 | errcode = -1; | |
1372 | } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) { | |
1373 | brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n", | |
1374 | num, sublen, dlen); | |
1375 | errcode = -1; | |
1376 | } else if ((chan != SDPCM_DATA_CHANNEL) && | |
1377 | (chan != SDPCM_EVENT_CHANNEL)) { | |
1378 | brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n", | |
1379 | num, chan); | |
1380 | errcode = -1; | |
1381 | } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) { | |
1382 | brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n", | |
1383 | num, doff, sublen, SDPCM_HDRLEN); | |
1384 | errcode = -1; | |
1385 | } | |
0b45bf74 AS |
1386 | /* increase the subframe count */ |
1387 | num++; | |
5b435de0 AS |
1388 | } |
1389 | ||
1390 | if (errcode) { | |
1391 | /* Terminate frame on error, request | |
1392 | a couple retries */ | |
1393 | if (bus->glomerr++ < 3) { | |
1394 | /* Restore superframe header space */ | |
1395 | skb_push(pfirst, sfdoff); | |
1396 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1397 | } else { | |
1398 | bus->glomerr = 0; | |
1399 | brcmf_sdbrcm_rxfail(bus, true, false); | |
5b435de0 | 1400 | bus->rxglomfail++; |
046808da | 1401 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 AS |
1402 | } |
1403 | bus->nextlen = 0; | |
1404 | return 0; | |
1405 | } | |
1406 | ||
1407 | /* Basic SD framing looks ok - process each packet (header) */ | |
5b435de0 | 1408 | |
0b45bf74 | 1409 | skb_queue_walk_safe(&bus->glom, pfirst, pnext) { |
5b435de0 AS |
1410 | dptr = (u8 *) (pfirst->data); |
1411 | sublen = get_unaligned_le16(dptr); | |
1412 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
1413 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1414 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
1415 | ||
1416 | brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n", | |
1417 | num, pfirst, pfirst->data, | |
1418 | pfirst->len, sublen, chan, seq); | |
1419 | ||
1420 | /* precondition: chan == SDPCM_DATA_CHANNEL || | |
1421 | chan == SDPCM_EVENT_CHANNEL */ | |
1422 | ||
1423 | if (rxseq != seq) { | |
1424 | brcmf_dbg(GLOM, "rx_seq %d, expected %d\n", | |
1425 | seq, rxseq); | |
1426 | bus->rx_badseq++; | |
1427 | rxseq = seq; | |
1428 | } | |
0b45bf74 AS |
1429 | rxseq++; |
1430 | ||
1e023829 JP |
1431 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
1432 | dptr, dlen, "Rx Subframe Data:\n"); | |
5b435de0 AS |
1433 | |
1434 | __skb_trim(pfirst, sublen); | |
1435 | skb_pull(pfirst, doff); | |
1436 | ||
1437 | if (pfirst->len == 0) { | |
0b45bf74 | 1438 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1439 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 | 1440 | continue; |
d5625ee6 FL |
1441 | } else if (brcmf_proto_hdrpull(bus->sdiodev->dev, |
1442 | &ifidx, pfirst) != 0) { | |
5b435de0 | 1443 | brcmf_dbg(ERROR, "rx protocol error\n"); |
719f2733 | 1444 | bus->sdiodev->bus_if->dstats.rx_errors++; |
0b45bf74 | 1445 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1446 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 AS |
1447 | continue; |
1448 | } | |
1449 | ||
1e023829 JP |
1450 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1451 | pfirst->data, | |
1452 | min_t(int, pfirst->len, 32), | |
1453 | "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1454 | bus->glom.qlen, pfirst, pfirst->data, | |
1455 | pfirst->len, pfirst->next, | |
1456 | pfirst->prev); | |
5b435de0 | 1457 | } |
0b45bf74 AS |
1458 | /* sent any remaining packets up */ |
1459 | if (bus->glom.qlen) { | |
5b435de0 | 1460 | up(&bus->sdsem); |
228bb43d | 1461 | brcmf_rx_frame(bus->sdiodev->dev, ifidx, &bus->glom); |
5b435de0 AS |
1462 | down(&bus->sdsem); |
1463 | } | |
1464 | ||
1465 | bus->rxglomframes++; | |
0b45bf74 | 1466 | bus->rxglompkts += bus->glom.qlen; |
5b435de0 AS |
1467 | } |
1468 | return num; | |
1469 | } | |
1470 | ||
e92eedf4 | 1471 | static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, |
5b435de0 AS |
1472 | bool *pending) |
1473 | { | |
1474 | DECLARE_WAITQUEUE(wait, current); | |
1475 | int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); | |
1476 | ||
1477 | /* Wait until control frame is available */ | |
1478 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1479 | set_current_state(TASK_INTERRUPTIBLE); | |
1480 | ||
1481 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1482 | timeout = schedule_timeout(timeout); | |
1483 | ||
1484 | if (signal_pending(current)) | |
1485 | *pending = true; | |
1486 | ||
1487 | set_current_state(TASK_RUNNING); | |
1488 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1489 | ||
1490 | return timeout; | |
1491 | } | |
1492 | ||
e92eedf4 | 1493 | static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus) |
5b435de0 AS |
1494 | { |
1495 | if (waitqueue_active(&bus->dcmd_resp_wait)) | |
1496 | wake_up_interruptible(&bus->dcmd_resp_wait); | |
1497 | ||
1498 | return 0; | |
1499 | } | |
1500 | static void | |
e92eedf4 | 1501 | brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) |
5b435de0 AS |
1502 | { |
1503 | uint rdlen, pad; | |
1504 | ||
1505 | int sdret; | |
1506 | ||
1507 | brcmf_dbg(TRACE, "Enter\n"); | |
1508 | ||
1509 | /* Set rxctl for frame (w/optional alignment) */ | |
1510 | bus->rxctl = bus->rxbuf; | |
1511 | bus->rxctl += BRCMF_FIRSTREAD; | |
1512 | pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN); | |
1513 | if (pad) | |
1514 | bus->rxctl += (BRCMF_SDALIGN - pad); | |
1515 | bus->rxctl -= BRCMF_FIRSTREAD; | |
1516 | ||
1517 | /* Copy the already-read portion over */ | |
1518 | memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD); | |
1519 | if (len <= BRCMF_FIRSTREAD) | |
1520 | goto gotpkt; | |
1521 | ||
1522 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1523 | rdlen = len - BRCMF_FIRSTREAD; | |
1524 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1525 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1526 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
b01a6b3c | 1527 | ((len + pad) < bus->sdiodev->bus_if->maxctl)) |
5b435de0 AS |
1528 | rdlen += pad; |
1529 | } else if (rdlen % BRCMF_SDALIGN) { | |
1530 | rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN); | |
1531 | } | |
1532 | ||
1533 | /* Satisfy length-alignment requirements */ | |
1534 | if (rdlen & (ALIGNMENT - 1)) | |
1535 | rdlen = roundup(rdlen, ALIGNMENT); | |
1536 | ||
1537 | /* Drop if the read is too big or it exceeds our maximum */ | |
b01a6b3c | 1538 | if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { |
5b435de0 | 1539 | brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n", |
b01a6b3c | 1540 | rdlen, bus->sdiodev->bus_if->maxctl); |
719f2733 | 1541 | bus->sdiodev->bus_if->dstats.rx_errors++; |
5b435de0 AS |
1542 | brcmf_sdbrcm_rxfail(bus, false, false); |
1543 | goto done; | |
1544 | } | |
1545 | ||
b01a6b3c | 1546 | if ((len - doff) > bus->sdiodev->bus_if->maxctl) { |
5b435de0 | 1547 | brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", |
b01a6b3c | 1548 | len, len - doff, bus->sdiodev->bus_if->maxctl); |
719f2733 | 1549 | bus->sdiodev->bus_if->dstats.rx_errors++; |
5b435de0 AS |
1550 | bus->rx_toolong++; |
1551 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1552 | goto done; | |
1553 | } | |
1554 | ||
1555 | /* Read remainder of frame body into the rxctl buffer */ | |
1556 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, | |
1557 | bus->sdiodev->sbwad, | |
1558 | SDIO_FUNC_2, | |
5adfeb63 | 1559 | F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen); |
5b435de0 AS |
1560 | bus->f2rxdata++; |
1561 | ||
1562 | /* Control frame failures need retransmission */ | |
1563 | if (sdret < 0) { | |
1564 | brcmf_dbg(ERROR, "read %d control bytes failed: %d\n", | |
1565 | rdlen, sdret); | |
1566 | bus->rxc_errors++; | |
1567 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1568 | goto done; | |
1569 | } | |
1570 | ||
1571 | gotpkt: | |
1572 | ||
1e023829 JP |
1573 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
1574 | bus->rxctl, len, "RxCtrl:\n"); | |
5b435de0 AS |
1575 | |
1576 | /* Point to valid data and indicate its length */ | |
1577 | bus->rxctl += doff; | |
1578 | bus->rxlen = len - doff; | |
1579 | ||
1580 | done: | |
1581 | /* Awake any waiters */ | |
1582 | brcmf_sdbrcm_dcmd_resp_wake(bus); | |
1583 | } | |
1584 | ||
1585 | /* Pad read to blocksize for efficiency */ | |
e92eedf4 | 1586 | static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) |
5b435de0 AS |
1587 | { |
1588 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1589 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1590 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1591 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1592 | *rdlen += *pad; | |
1593 | } else if (*rdlen % BRCMF_SDALIGN) { | |
1594 | *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN); | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | static void | |
e92eedf4 | 1599 | brcmf_alloc_pkt_and_read(struct brcmf_sdio *bus, u16 rdlen, |
5b435de0 AS |
1600 | struct sk_buff **pkt, u8 **rxbuf) |
1601 | { | |
1602 | int sdret; /* Return code from calls */ | |
1603 | ||
1604 | *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN); | |
1605 | if (*pkt == NULL) | |
1606 | return; | |
1607 | ||
1608 | pkt_align(*pkt, rdlen, BRCMF_SDALIGN); | |
1609 | *rxbuf = (u8 *) ((*pkt)->data); | |
1610 | /* Read the entire frame */ | |
5adfeb63 AS |
1611 | sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad, |
1612 | SDIO_FUNC_2, F2SYNC, *pkt); | |
5b435de0 AS |
1613 | bus->f2rxdata++; |
1614 | ||
1615 | if (sdret < 0) { | |
1616 | brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n", | |
1617 | rdlen, sdret); | |
1618 | brcmu_pkt_buf_free_skb(*pkt); | |
719f2733 | 1619 | bus->sdiodev->bus_if->dstats.rx_errors++; |
5b435de0 AS |
1620 | /* Force retry w/normal header read. |
1621 | * Don't attempt NAK for | |
1622 | * gSPI | |
1623 | */ | |
1624 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1625 | *pkt = NULL; | |
1626 | } | |
1627 | } | |
1628 | ||
1629 | /* Checks the header */ | |
1630 | static int | |
e92eedf4 | 1631 | brcmf_check_rxbuf(struct brcmf_sdio *bus, struct sk_buff *pkt, u8 *rxbuf, |
5b435de0 AS |
1632 | u8 rxseq, u16 nextlen, u16 *len) |
1633 | { | |
1634 | u16 check; | |
1635 | bool len_consistent; /* Result of comparing readahead len and | |
1636 | len from hw-hdr */ | |
1637 | ||
1638 | memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN); | |
1639 | ||
1640 | /* Extract hardware header fields */ | |
1641 | *len = get_unaligned_le16(bus->rxhdr); | |
1642 | check = get_unaligned_le16(bus->rxhdr + sizeof(u16)); | |
1643 | ||
1644 | /* All zeros means readahead info was bad */ | |
1645 | if (!(*len | check)) { | |
1646 | brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n"); | |
1647 | goto fail; | |
1648 | } | |
1649 | ||
1650 | /* Validate check bytes */ | |
1651 | if ((u16)~(*len ^ check)) { | |
1652 | brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n", | |
1653 | nextlen, *len, check); | |
1654 | bus->rx_badhdr++; | |
1655 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1656 | goto fail; | |
1657 | } | |
1658 | ||
1659 | /* Validate frame length */ | |
1660 | if (*len < SDPCM_HDRLEN) { | |
1661 | brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n", | |
1662 | *len); | |
1663 | goto fail; | |
1664 | } | |
1665 | ||
1666 | /* Check for consistency with readahead info */ | |
1667 | len_consistent = (nextlen != (roundup(*len, 16) >> 4)); | |
1668 | if (len_consistent) { | |
1669 | /* Mismatch, force retry w/normal | |
1670 | header (may be >4K) */ | |
1671 | brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n", | |
1672 | nextlen, *len, roundup(*len, 16), | |
1673 | rxseq); | |
1674 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1675 | goto fail; | |
1676 | } | |
1677 | ||
1678 | return 0; | |
1679 | ||
1680 | fail: | |
1681 | brcmf_sdbrcm_pktfree2(bus, pkt); | |
1682 | return -EINVAL; | |
1683 | } | |
1684 | ||
1685 | /* Return true if there may be more frames to read */ | |
1686 | static uint | |
e92eedf4 | 1687 | brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished) |
5b435de0 AS |
1688 | { |
1689 | u16 len, check; /* Extracted hardware header fields */ | |
1690 | u8 chan, seq, doff; /* Extracted software header fields */ | |
1691 | u8 fcbits; /* Extracted fcbits from software header */ | |
1692 | ||
1693 | struct sk_buff *pkt; /* Packet for event or data frames */ | |
1694 | u16 pad; /* Number of pad bytes to read */ | |
1695 | u16 rdlen; /* Total number of bytes to read */ | |
1696 | u8 rxseq; /* Next sequence number to expect */ | |
1697 | uint rxleft = 0; /* Remaining number of frames allowed */ | |
1698 | int sdret; /* Return code from calls */ | |
1699 | u8 txmax; /* Maximum tx sequence offered */ | |
1700 | u8 *rxbuf; | |
1701 | int ifidx = 0; | |
1702 | uint rxcount = 0; /* Total frames read */ | |
1703 | ||
1704 | brcmf_dbg(TRACE, "Enter\n"); | |
1705 | ||
1706 | /* Not finished unless we encounter no more frames indication */ | |
1707 | *finished = false; | |
1708 | ||
1709 | for (rxseq = bus->rx_seq, rxleft = maxframes; | |
8d169aa0 | 1710 | !bus->rxskip && rxleft && |
712ac5b3 | 1711 | bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN; |
5b435de0 AS |
1712 | rxseq++, rxleft--) { |
1713 | ||
1714 | /* Handle glomming separately */ | |
b83db862 | 1715 | if (bus->glomd || !skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1716 | u8 cnt; |
1717 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
b83db862 | 1718 | bus->glomd, skb_peek(&bus->glom)); |
5b435de0 AS |
1719 | cnt = brcmf_sdbrcm_rxglom(bus, rxseq); |
1720 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); | |
1721 | rxseq += cnt - 1; | |
1722 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; | |
1723 | continue; | |
1724 | } | |
1725 | ||
1726 | /* Try doing single read if we can */ | |
1727 | if (bus->nextlen) { | |
1728 | u16 nextlen = bus->nextlen; | |
1729 | bus->nextlen = 0; | |
1730 | ||
1731 | rdlen = len = nextlen << 4; | |
1732 | brcmf_pad(bus, &pad, &rdlen); | |
1733 | ||
1734 | /* | |
1735 | * After the frame is received we have to | |
1736 | * distinguish whether it is data | |
1737 | * or non-data frame. | |
1738 | */ | |
1739 | brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf); | |
1740 | if (pkt == NULL) { | |
1741 | /* Give up on data, request rtx of events */ | |
1742 | brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n", | |
1743 | len, rdlen, rxseq); | |
1744 | continue; | |
1745 | } | |
1746 | ||
1747 | if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen, | |
1748 | &len) < 0) | |
1749 | continue; | |
1750 | ||
1751 | /* Extract software header fields */ | |
1752 | chan = SDPCM_PACKET_CHANNEL( | |
1753 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1754 | seq = SDPCM_PACKET_SEQUENCE( | |
1755 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1756 | doff = SDPCM_DOFFSET_VALUE( | |
1757 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1758 | txmax = SDPCM_WINDOW_VALUE( | |
1759 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1760 | ||
1761 | bus->nextlen = | |
1762 | bus->rxhdr[SDPCM_FRAMETAG_LEN + | |
1763 | SDPCM_NEXTLEN_OFFSET]; | |
1764 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
1765 | brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n", | |
1766 | bus->nextlen, seq); | |
1767 | bus->nextlen = 0; | |
1768 | } | |
1769 | ||
28a1a3bd | 1770 | bus->rx_readahead_cnt++; |
5b435de0 AS |
1771 | |
1772 | /* Handle Flow Control */ | |
1773 | fcbits = SDPCM_FCMASK_VALUE( | |
1774 | &bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1775 | ||
1776 | if (bus->flowcontrol != fcbits) { | |
1777 | if (~bus->flowcontrol & fcbits) | |
1778 | bus->fc_xoff++; | |
1779 | ||
1780 | if (bus->flowcontrol & ~fcbits) | |
1781 | bus->fc_xon++; | |
1782 | ||
1783 | bus->fc_rcvd++; | |
1784 | bus->flowcontrol = fcbits; | |
1785 | } | |
1786 | ||
1787 | /* Check and update sequence number */ | |
1788 | if (rxseq != seq) { | |
1789 | brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n", | |
1790 | seq, rxseq); | |
1791 | bus->rx_badseq++; | |
1792 | rxseq = seq; | |
1793 | } | |
1794 | ||
1795 | /* Check window for sanity */ | |
1796 | if ((u8) (txmax - bus->tx_seq) > 0x40) { | |
1797 | brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n", | |
1798 | txmax, bus->tx_seq); | |
1799 | txmax = bus->tx_seq + 2; | |
1800 | } | |
1801 | bus->tx_max = txmax; | |
1802 | ||
1e023829 JP |
1803 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
1804 | rxbuf, len, "Rx Data:\n"); | |
1805 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
1806 | BRCMF_DATA_ON()) && | |
1807 | BRCMF_HDRS_ON(), | |
1808 | bus->rxhdr, SDPCM_HDRLEN, | |
1809 | "RxHdr:\n"); | |
5b435de0 AS |
1810 | |
1811 | if (chan == SDPCM_CONTROL_CHANNEL) { | |
1812 | brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n", | |
1813 | seq); | |
1814 | /* Force retry w/normal header read */ | |
1815 | bus->nextlen = 0; | |
1816 | brcmf_sdbrcm_rxfail(bus, false, true); | |
1817 | brcmf_sdbrcm_pktfree2(bus, pkt); | |
1818 | continue; | |
1819 | } | |
1820 | ||
1821 | /* Validate data offset */ | |
1822 | if ((doff < SDPCM_HDRLEN) || (doff > len)) { | |
1823 | brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n", | |
1824 | doff, len, SDPCM_HDRLEN); | |
1825 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1826 | brcmf_sdbrcm_pktfree2(bus, pkt); | |
1827 | continue; | |
1828 | } | |
1829 | ||
1830 | /* All done with this one -- now deliver the packet */ | |
1831 | goto deliver; | |
1832 | } | |
1833 | ||
1834 | /* Read frame header (hardware and software) */ | |
1835 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad, | |
1836 | SDIO_FUNC_2, F2SYNC, bus->rxhdr, | |
5adfeb63 | 1837 | BRCMF_FIRSTREAD); |
5b435de0 AS |
1838 | bus->f2rxhdrs++; |
1839 | ||
1840 | if (sdret < 0) { | |
1841 | brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret); | |
1842 | bus->rx_hdrfail++; | |
1843 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1844 | continue; | |
1845 | } | |
1e023829 JP |
1846 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), |
1847 | bus->rxhdr, SDPCM_HDRLEN, "RxHdr:\n"); | |
1848 | ||
5b435de0 AS |
1849 | |
1850 | /* Extract hardware header fields */ | |
1851 | len = get_unaligned_le16(bus->rxhdr); | |
1852 | check = get_unaligned_le16(bus->rxhdr + sizeof(u16)); | |
1853 | ||
1854 | /* All zeros means no more frames */ | |
1855 | if (!(len | check)) { | |
1856 | *finished = true; | |
1857 | break; | |
1858 | } | |
1859 | ||
1860 | /* Validate check bytes */ | |
1861 | if ((u16) ~(len ^ check)) { | |
1862 | brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n", | |
1863 | len, check); | |
1864 | bus->rx_badhdr++; | |
1865 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1866 | continue; | |
1867 | } | |
1868 | ||
1869 | /* Validate frame length */ | |
1870 | if (len < SDPCM_HDRLEN) { | |
1871 | brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len); | |
1872 | continue; | |
1873 | } | |
1874 | ||
1875 | /* Extract software header fields */ | |
1876 | chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1877 | seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1878 | doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1879 | txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1880 | ||
1881 | /* Validate data offset */ | |
1882 | if ((doff < SDPCM_HDRLEN) || (doff > len)) { | |
1883 | brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n", | |
1884 | doff, len, SDPCM_HDRLEN, seq); | |
1885 | bus->rx_badhdr++; | |
1886 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1887 | continue; | |
1888 | } | |
1889 | ||
1890 | /* Save the readahead length if there is one */ | |
1891 | bus->nextlen = | |
1892 | bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET]; | |
1893 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
1894 | brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n", | |
1895 | bus->nextlen, seq); | |
1896 | bus->nextlen = 0; | |
1897 | } | |
1898 | ||
1899 | /* Handle Flow Control */ | |
1900 | fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
1901 | ||
1902 | if (bus->flowcontrol != fcbits) { | |
1903 | if (~bus->flowcontrol & fcbits) | |
1904 | bus->fc_xoff++; | |
1905 | ||
1906 | if (bus->flowcontrol & ~fcbits) | |
1907 | bus->fc_xon++; | |
1908 | ||
1909 | bus->fc_rcvd++; | |
1910 | bus->flowcontrol = fcbits; | |
1911 | } | |
1912 | ||
1913 | /* Check and update sequence number */ | |
1914 | if (rxseq != seq) { | |
1915 | brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq); | |
1916 | bus->rx_badseq++; | |
1917 | rxseq = seq; | |
1918 | } | |
1919 | ||
1920 | /* Check window for sanity */ | |
1921 | if ((u8) (txmax - bus->tx_seq) > 0x40) { | |
1922 | brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n", | |
1923 | txmax, bus->tx_seq); | |
1924 | txmax = bus->tx_seq + 2; | |
1925 | } | |
1926 | bus->tx_max = txmax; | |
1927 | ||
1928 | /* Call a separate function for control frames */ | |
1929 | if (chan == SDPCM_CONTROL_CHANNEL) { | |
1930 | brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff); | |
1931 | continue; | |
1932 | } | |
1933 | ||
1934 | /* precondition: chan is either SDPCM_DATA_CHANNEL, | |
1935 | SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or | |
1936 | SDPCM_GLOM_CHANNEL */ | |
1937 | ||
1938 | /* Length to read */ | |
1939 | rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0; | |
1940 | ||
1941 | /* May pad read to blocksize for efficiency */ | |
1942 | if (bus->roundup && bus->blocksize && | |
1943 | (rdlen > bus->blocksize)) { | |
1944 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1945 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
1946 | ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ)) | |
1947 | rdlen += pad; | |
1948 | } else if (rdlen % BRCMF_SDALIGN) { | |
1949 | rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN); | |
1950 | } | |
1951 | ||
1952 | /* Satisfy length-alignment requirements */ | |
1953 | if (rdlen & (ALIGNMENT - 1)) | |
1954 | rdlen = roundup(rdlen, ALIGNMENT); | |
1955 | ||
1956 | if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) { | |
1957 | /* Too long -- skip this frame */ | |
1958 | brcmf_dbg(ERROR, "too long: len %d rdlen %d\n", | |
1959 | len, rdlen); | |
719f2733 | 1960 | bus->sdiodev->bus_if->dstats.rx_errors++; |
5b435de0 AS |
1961 | bus->rx_toolong++; |
1962 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1963 | continue; | |
1964 | } | |
1965 | ||
1966 | pkt = brcmu_pkt_buf_get_skb(rdlen + | |
1967 | BRCMF_FIRSTREAD + BRCMF_SDALIGN); | |
1968 | if (!pkt) { | |
1969 | /* Give up on data, request rtx of events */ | |
1970 | brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n", | |
1971 | rdlen, chan); | |
719f2733 | 1972 | bus->sdiodev->bus_if->dstats.rx_dropped++; |
5b435de0 AS |
1973 | brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan)); |
1974 | continue; | |
1975 | } | |
1976 | ||
1977 | /* Leave room for what we already read, and align remainder */ | |
1978 | skb_pull(pkt, BRCMF_FIRSTREAD); | |
1979 | pkt_align(pkt, rdlen, BRCMF_SDALIGN); | |
1980 | ||
1981 | /* Read the remaining frame data */ | |
5adfeb63 AS |
1982 | sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad, |
1983 | SDIO_FUNC_2, F2SYNC, pkt); | |
5b435de0 AS |
1984 | bus->f2rxdata++; |
1985 | ||
1986 | if (sdret < 0) { | |
1987 | brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen, | |
1988 | ((chan == SDPCM_EVENT_CHANNEL) ? "event" | |
1989 | : ((chan == SDPCM_DATA_CHANNEL) ? "data" | |
1990 | : "test")), sdret); | |
1991 | brcmu_pkt_buf_free_skb(pkt); | |
719f2733 | 1992 | bus->sdiodev->bus_if->dstats.rx_errors++; |
5b435de0 AS |
1993 | brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan)); |
1994 | continue; | |
1995 | } | |
1996 | ||
1997 | /* Copy the already-read portion */ | |
1998 | skb_push(pkt, BRCMF_FIRSTREAD); | |
1999 | memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD); | |
2000 | ||
1e023829 JP |
2001 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
2002 | pkt->data, len, "Rx Data:\n"); | |
5b435de0 AS |
2003 | |
2004 | deliver: | |
2005 | /* Save superframe descriptor and allocate packet frame */ | |
2006 | if (chan == SDPCM_GLOM_CHANNEL) { | |
2007 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) { | |
2008 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", | |
2009 | len); | |
1e023829 JP |
2010 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
2011 | pkt->data, len, | |
2012 | "Glom Data:\n"); | |
5b435de0 AS |
2013 | __skb_trim(pkt, len); |
2014 | skb_pull(pkt, SDPCM_HDRLEN); | |
2015 | bus->glomd = pkt; | |
2016 | } else { | |
2017 | brcmf_dbg(ERROR, "%s: glom superframe w/o " | |
2018 | "descriptor!\n", __func__); | |
2019 | brcmf_sdbrcm_rxfail(bus, false, false); | |
2020 | } | |
2021 | continue; | |
2022 | } | |
2023 | ||
2024 | /* Fill in packet len and prio, deliver upward */ | |
2025 | __skb_trim(pkt, len); | |
2026 | skb_pull(pkt, doff); | |
2027 | ||
2028 | if (pkt->len == 0) { | |
2029 | brcmu_pkt_buf_free_skb(pkt); | |
2030 | continue; | |
d5625ee6 FL |
2031 | } else if (brcmf_proto_hdrpull(bus->sdiodev->dev, &ifidx, |
2032 | pkt) != 0) { | |
5b435de0 AS |
2033 | brcmf_dbg(ERROR, "rx protocol error\n"); |
2034 | brcmu_pkt_buf_free_skb(pkt); | |
719f2733 | 2035 | bus->sdiodev->bus_if->dstats.rx_errors++; |
5b435de0 AS |
2036 | continue; |
2037 | } | |
2038 | ||
2039 | /* Unlock during rx call */ | |
2040 | up(&bus->sdsem); | |
228bb43d | 2041 | brcmf_rx_packet(bus->sdiodev->dev, ifidx, pkt); |
5b435de0 AS |
2042 | down(&bus->sdsem); |
2043 | } | |
2044 | rxcount = maxframes - rxleft; | |
5b435de0 AS |
2045 | /* Message if we hit the limit */ |
2046 | if (!rxleft) | |
2047 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", | |
2048 | maxframes); | |
2049 | else | |
5b435de0 AS |
2050 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); |
2051 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
2052 | if (bus->rxskip) | |
2053 | rxseq--; | |
2054 | bus->rx_seq = rxseq; | |
2055 | ||
2056 | return rxcount; | |
2057 | } | |
2058 | ||
5b435de0 | 2059 | static void |
e92eedf4 | 2060 | brcmf_sdbrcm_wait_for_event(struct brcmf_sdio *bus, bool *lockvar) |
5b435de0 AS |
2061 | { |
2062 | up(&bus->sdsem); | |
23677ce3 | 2063 | wait_event_interruptible_timeout(bus->ctrl_wait, !*lockvar, HZ * 2); |
5b435de0 AS |
2064 | down(&bus->sdsem); |
2065 | return; | |
2066 | } | |
2067 | ||
2068 | static void | |
e92eedf4 | 2069 | brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus) |
5b435de0 AS |
2070 | { |
2071 | if (waitqueue_active(&bus->ctrl_wait)) | |
2072 | wake_up_interruptible(&bus->ctrl_wait); | |
2073 | return; | |
2074 | } | |
2075 | ||
2076 | /* Writes a HW/SW header into the packet and sends it. */ | |
2077 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
e92eedf4 | 2078 | static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt, |
5b435de0 AS |
2079 | uint chan, bool free_pkt) |
2080 | { | |
2081 | int ret; | |
2082 | u8 *frame; | |
2083 | u16 len, pad = 0; | |
2084 | u32 swheader; | |
2085 | struct sk_buff *new; | |
2086 | int i; | |
2087 | ||
2088 | brcmf_dbg(TRACE, "Enter\n"); | |
2089 | ||
2090 | frame = (u8 *) (pkt->data); | |
2091 | ||
2092 | /* Add alignment padding, allocate new packet if needed */ | |
2093 | pad = ((unsigned long)frame % BRCMF_SDALIGN); | |
2094 | if (pad) { | |
2095 | if (skb_headroom(pkt) < pad) { | |
2096 | brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n", | |
2097 | skb_headroom(pkt), pad); | |
9c1a043a | 2098 | bus->sdiodev->bus_if->tx_realloc++; |
5b435de0 AS |
2099 | new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN); |
2100 | if (!new) { | |
2101 | brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n", | |
2102 | pkt->len + BRCMF_SDALIGN); | |
2103 | ret = -ENOMEM; | |
2104 | goto done; | |
2105 | } | |
2106 | ||
2107 | pkt_align(new, pkt->len, BRCMF_SDALIGN); | |
2108 | memcpy(new->data, pkt->data, pkt->len); | |
2109 | if (free_pkt) | |
2110 | brcmu_pkt_buf_free_skb(pkt); | |
2111 | /* free the pkt if canned one is not used */ | |
2112 | free_pkt = true; | |
2113 | pkt = new; | |
2114 | frame = (u8 *) (pkt->data); | |
2115 | /* precondition: (frame % BRCMF_SDALIGN) == 0) */ | |
2116 | pad = 0; | |
2117 | } else { | |
2118 | skb_push(pkt, pad); | |
2119 | frame = (u8 *) (pkt->data); | |
2120 | /* precondition: pad + SDPCM_HDRLEN <= pkt->len */ | |
2121 | memset(frame, 0, pad + SDPCM_HDRLEN); | |
2122 | } | |
2123 | } | |
2124 | /* precondition: pad < BRCMF_SDALIGN */ | |
2125 | ||
2126 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ | |
2127 | len = (u16) (pkt->len); | |
2128 | *(__le16 *) frame = cpu_to_le16(len); | |
2129 | *(((__le16 *) frame) + 1) = cpu_to_le16(~len); | |
2130 | ||
2131 | /* Software tag: channel, sequence number, data offset */ | |
2132 | swheader = | |
2133 | ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq | | |
2134 | (((pad + | |
2135 | SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK); | |
2136 | ||
2137 | put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN); | |
2138 | put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader)); | |
2139 | ||
8ae74654 | 2140 | #ifdef DEBUG |
5b435de0 | 2141 | tx_packets[pkt->priority]++; |
18aad4f8 | 2142 | #endif |
1e023829 JP |
2143 | |
2144 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && | |
2145 | ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || | |
2146 | (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)), | |
2147 | frame, len, "Tx Frame:\n"); | |
2148 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
2149 | ((BRCMF_CTL_ON() && | |
2150 | chan == SDPCM_CONTROL_CHANNEL) || | |
2151 | (BRCMF_DATA_ON() && | |
2152 | chan != SDPCM_CONTROL_CHANNEL))) && | |
2153 | BRCMF_HDRS_ON(), | |
2154 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
5b435de0 AS |
2155 | |
2156 | /* Raise len to next SDIO block to eliminate tail command */ | |
2157 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2158 | u16 pad = bus->blocksize - (len % bus->blocksize); | |
2159 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | |
2160 | len += pad; | |
2161 | } else if (len % BRCMF_SDALIGN) { | |
2162 | len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN); | |
2163 | } | |
2164 | ||
2165 | /* Some controllers have trouble with odd bytes -- round to even */ | |
2166 | if (len & (ALIGNMENT - 1)) | |
2167 | len = roundup(len, ALIGNMENT); | |
2168 | ||
5adfeb63 AS |
2169 | ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad, |
2170 | SDIO_FUNC_2, F2SYNC, pkt); | |
5b435de0 AS |
2171 | bus->f2txdata++; |
2172 | ||
2173 | if (ret < 0) { | |
2174 | /* On failure, abort the command and terminate the frame */ | |
2175 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2176 | ret); | |
2177 | bus->tx_sderrs++; | |
2178 | ||
2179 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2180 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2181 | SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, | |
2182 | NULL); | |
2183 | bus->f1regdata++; | |
2184 | ||
2185 | for (i = 0; i < 3; i++) { | |
2186 | u8 hi, lo; | |
2187 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2188 | SDIO_FUNC_1, | |
2189 | SBSDIO_FUNC1_WFRAMEBCHI, | |
2190 | NULL); | |
2191 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2192 | SDIO_FUNC_1, | |
2193 | SBSDIO_FUNC1_WFRAMEBCLO, | |
2194 | NULL); | |
2195 | bus->f1regdata += 2; | |
2196 | if ((hi == 0) && (lo == 0)) | |
2197 | break; | |
2198 | } | |
2199 | ||
2200 | } | |
2201 | if (ret == 0) | |
2202 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
2203 | ||
2204 | done: | |
2205 | /* restore pkt buffer pointer before calling tx complete routine */ | |
2206 | skb_pull(pkt, SDPCM_HDRLEN + pad); | |
2207 | up(&bus->sdsem); | |
c995788f | 2208 | brcmf_txcomplete(bus->sdiodev->dev, pkt, ret != 0); |
5b435de0 AS |
2209 | down(&bus->sdsem); |
2210 | ||
2211 | if (free_pkt) | |
2212 | brcmu_pkt_buf_free_skb(pkt); | |
2213 | ||
2214 | return ret; | |
2215 | } | |
2216 | ||
e92eedf4 | 2217 | static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 AS |
2218 | { |
2219 | struct sk_buff *pkt; | |
2220 | u32 intstatus = 0; | |
2221 | uint retries = 0; | |
2222 | int ret = 0, prec_out; | |
2223 | uint cnt = 0; | |
2224 | uint datalen; | |
2225 | u8 tx_prec_map; | |
2226 | ||
5b435de0 AS |
2227 | brcmf_dbg(TRACE, "Enter\n"); |
2228 | ||
2229 | tx_prec_map = ~bus->flowcontrol; | |
2230 | ||
2231 | /* Send frames until the limit or some other event */ | |
2232 | for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) { | |
2233 | spin_lock_bh(&bus->txqlock); | |
2234 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out); | |
2235 | if (pkt == NULL) { | |
2236 | spin_unlock_bh(&bus->txqlock); | |
2237 | break; | |
2238 | } | |
2239 | spin_unlock_bh(&bus->txqlock); | |
2240 | datalen = pkt->len - SDPCM_HDRLEN; | |
2241 | ||
2242 | ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true); | |
2243 | if (ret) | |
719f2733 | 2244 | bus->sdiodev->bus_if->dstats.tx_errors++; |
5b435de0 | 2245 | else |
719f2733 | 2246 | bus->sdiodev->bus_if->dstats.tx_bytes += datalen; |
5b435de0 AS |
2247 | |
2248 | /* In poll mode, need to check for other events */ | |
2249 | if (!bus->intr && cnt) { | |
2250 | /* Check device status, signal pending interrupt */ | |
2251 | r_sdreg32(bus, &intstatus, | |
2252 | offsetof(struct sdpcmd_regs, intstatus), | |
2253 | &retries); | |
2254 | bus->f2txdata++; | |
2255 | if (brcmf_sdcard_regfail(bus->sdiodev)) | |
2256 | break; | |
2257 | if (intstatus & bus->hostintmask) | |
2258 | bus->ipend = true; | |
2259 | } | |
2260 | } | |
2261 | ||
2262 | /* Deflow-control stack if needed */ | |
712ac5b3 FL |
2263 | if (bus->sdiodev->bus_if->drvr_up && |
2264 | (bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) && | |
c8bf3484 FL |
2265 | bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { |
2266 | bus->txoff = OFF; | |
2b459056 | 2267 | brcmf_txflowcontrol(bus->sdiodev->dev, 0, OFF); |
c8bf3484 | 2268 | } |
5b435de0 AS |
2269 | |
2270 | return cnt; | |
2271 | } | |
2272 | ||
a9ffda88 FL |
2273 | static void brcmf_sdbrcm_bus_stop(struct device *dev) |
2274 | { | |
2275 | u32 local_hostintmask; | |
2276 | u8 saveclk; | |
2277 | uint retries; | |
2278 | int err; | |
2279 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
0a332e46 | 2280 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
a9ffda88 FL |
2281 | struct brcmf_sdio *bus = sdiodev->bus; |
2282 | ||
2283 | brcmf_dbg(TRACE, "Enter\n"); | |
2284 | ||
2285 | if (bus->watchdog_tsk) { | |
2286 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
2287 | kthread_stop(bus->watchdog_tsk); | |
2288 | bus->watchdog_tsk = NULL; | |
2289 | } | |
2290 | ||
2291 | if (bus->dpc_tsk && bus->dpc_tsk != current) { | |
2292 | send_sig(SIGTERM, bus->dpc_tsk, 1); | |
2293 | kthread_stop(bus->dpc_tsk); | |
2294 | bus->dpc_tsk = NULL; | |
2295 | } | |
2296 | ||
2297 | down(&bus->sdsem); | |
2298 | ||
2299 | bus_wake(bus); | |
2300 | ||
2301 | /* Enable clock for device interrupts */ | |
2302 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
2303 | ||
2304 | /* Disable and clear interrupts at the chip level also */ | |
2305 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries); | |
2306 | local_hostintmask = bus->hostintmask; | |
2307 | bus->hostintmask = 0; | |
2308 | ||
2309 | /* Change our idea of bus state */ | |
2310 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; | |
2311 | ||
2312 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
2313 | saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2314 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
2315 | if (!err) { | |
2316 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2317 | SBSDIO_FUNC1_CHIPCLKCSR, | |
2318 | (saveclk | SBSDIO_FORCE_HT), &err); | |
2319 | } | |
2320 | if (err) | |
2321 | brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err); | |
2322 | ||
2323 | /* Turn off the bus (F2), free any pending packets */ | |
2324 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
2325 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx, | |
2326 | SDIO_FUNC_ENABLE_1, NULL); | |
2327 | ||
2328 | /* Clear any pending interrupts now that F2 is disabled */ | |
2329 | w_sdreg32(bus, local_hostintmask, | |
2330 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
2331 | ||
2332 | /* Turn off the backplane clock (only) */ | |
2333 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
2334 | ||
2335 | /* Clear the data packet queues */ | |
2336 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
2337 | ||
2338 | /* Clear any held glomming stuff */ | |
2339 | if (bus->glomd) | |
2340 | brcmu_pkt_buf_free_skb(bus->glomd); | |
2341 | brcmf_sdbrcm_free_glom(bus); | |
2342 | ||
2343 | /* Clear rx control and wake any waiters */ | |
2344 | bus->rxlen = 0; | |
2345 | brcmf_sdbrcm_dcmd_resp_wake(bus); | |
2346 | ||
2347 | /* Reset some F2 state stuff */ | |
2348 | bus->rxskip = false; | |
2349 | bus->tx_seq = bus->rx_seq = 0; | |
2350 | ||
2351 | up(&bus->sdsem); | |
2352 | } | |
2353 | ||
ba89bf19 FL |
2354 | #ifdef CONFIG_BRCMFMAC_SDIO_OOB |
2355 | static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus) | |
2356 | { | |
2357 | unsigned long flags; | |
2358 | ||
2359 | spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags); | |
2360 | if (!bus->sdiodev->irq_en && !bus->ipend) { | |
2361 | enable_irq(bus->sdiodev->irq); | |
2362 | bus->sdiodev->irq_en = true; | |
2363 | } | |
2364 | spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags); | |
2365 | } | |
2366 | #else | |
2367 | static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus) | |
2368 | { | |
2369 | } | |
2370 | #endif /* CONFIG_BRCMFMAC_SDIO_OOB */ | |
2371 | ||
e92eedf4 | 2372 | static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus) |
5b435de0 AS |
2373 | { |
2374 | u32 intstatus, newstatus = 0; | |
2375 | uint retries = 0; | |
2376 | uint rxlimit = bus->rxbound; /* Rx frames to read before resched */ | |
2377 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ | |
2378 | uint framecnt = 0; /* Temporary counter of tx/rx frames */ | |
2379 | bool rxdone = true; /* Flag for no more read data */ | |
2380 | bool resched = false; /* Flag indicating resched wanted */ | |
2381 | ||
2382 | brcmf_dbg(TRACE, "Enter\n"); | |
2383 | ||
2384 | /* Start with leftover status bits */ | |
2385 | intstatus = bus->intstatus; | |
2386 | ||
2387 | down(&bus->sdsem); | |
2388 | ||
2389 | /* If waiting for HTAVAIL, check status */ | |
2390 | if (bus->clkstate == CLK_PENDING) { | |
2391 | int err; | |
2392 | u8 clkctl, devctl = 0; | |
2393 | ||
8ae74654 | 2394 | #ifdef DEBUG |
5b435de0 AS |
2395 | /* Check for inconsistent device control */ |
2396 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2397 | SBSDIO_DEVICE_CTL, &err); | |
2398 | if (err) { | |
2399 | brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err); | |
712ac5b3 | 2400 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 | 2401 | } |
8ae74654 | 2402 | #endif /* DEBUG */ |
5b435de0 AS |
2403 | |
2404 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
2405 | clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2406 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
2407 | if (err) { | |
2408 | brcmf_dbg(ERROR, "error reading CSR: %d\n", | |
2409 | err); | |
712ac5b3 | 2410 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2411 | } |
2412 | ||
2413 | brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", | |
2414 | devctl, clkctl); | |
2415 | ||
2416 | if (SBSDIO_HTAV(clkctl)) { | |
2417 | devctl = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2418 | SDIO_FUNC_1, | |
2419 | SBSDIO_DEVICE_CTL, &err); | |
2420 | if (err) { | |
2421 | brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", | |
2422 | err); | |
712ac5b3 | 2423 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2424 | } |
2425 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
2426 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2427 | SBSDIO_DEVICE_CTL, devctl, &err); | |
2428 | if (err) { | |
2429 | brcmf_dbg(ERROR, "error writing DEVCTL: %d\n", | |
2430 | err); | |
712ac5b3 | 2431 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2432 | } |
2433 | bus->clkstate = CLK_AVAIL; | |
2434 | } else { | |
2435 | goto clkwait; | |
2436 | } | |
2437 | } | |
2438 | ||
2439 | bus_wake(bus); | |
2440 | ||
2441 | /* Make sure backplane clock is on */ | |
2442 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true); | |
2443 | if (bus->clkstate == CLK_PENDING) | |
2444 | goto clkwait; | |
2445 | ||
2446 | /* Pending interrupt indicates new device status */ | |
2447 | if (bus->ipend) { | |
2448 | bus->ipend = false; | |
2449 | r_sdreg32(bus, &newstatus, | |
2450 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
2451 | bus->f1regdata++; | |
2452 | if (brcmf_sdcard_regfail(bus->sdiodev)) | |
2453 | newstatus = 0; | |
2454 | newstatus &= bus->hostintmask; | |
2455 | bus->fcstate = !!(newstatus & I_HMB_FC_STATE); | |
2456 | if (newstatus) { | |
2457 | w_sdreg32(bus, newstatus, | |
2458 | offsetof(struct sdpcmd_regs, intstatus), | |
2459 | &retries); | |
2460 | bus->f1regdata++; | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | /* Merge new bits with previous */ | |
2465 | intstatus |= newstatus; | |
2466 | bus->intstatus = 0; | |
2467 | ||
2468 | /* Handle flow-control change: read new state in case our ack | |
2469 | * crossed another change interrupt. If change still set, assume | |
2470 | * FC ON for safety, let next loop through do the debounce. | |
2471 | */ | |
2472 | if (intstatus & I_HMB_FC_CHANGE) { | |
2473 | intstatus &= ~I_HMB_FC_CHANGE; | |
2474 | w_sdreg32(bus, I_HMB_FC_CHANGE, | |
2475 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
2476 | ||
2477 | r_sdreg32(bus, &newstatus, | |
2478 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
2479 | bus->f1regdata += 2; | |
2480 | bus->fcstate = | |
2481 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)); | |
2482 | intstatus |= (newstatus & bus->hostintmask); | |
2483 | } | |
2484 | ||
2485 | /* Handle host mailbox indication */ | |
2486 | if (intstatus & I_HMB_HOST_INT) { | |
2487 | intstatus &= ~I_HMB_HOST_INT; | |
2488 | intstatus |= brcmf_sdbrcm_hostmail(bus); | |
2489 | } | |
2490 | ||
2491 | /* Generally don't ask for these, can get CRC errors... */ | |
2492 | if (intstatus & I_WR_OOSYNC) { | |
2493 | brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n"); | |
2494 | intstatus &= ~I_WR_OOSYNC; | |
2495 | } | |
2496 | ||
2497 | if (intstatus & I_RD_OOSYNC) { | |
2498 | brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n"); | |
2499 | intstatus &= ~I_RD_OOSYNC; | |
2500 | } | |
2501 | ||
2502 | if (intstatus & I_SBINT) { | |
2503 | brcmf_dbg(ERROR, "Dongle reports SBINT\n"); | |
2504 | intstatus &= ~I_SBINT; | |
2505 | } | |
2506 | ||
2507 | /* Would be active due to wake-wlan in gSPI */ | |
2508 | if (intstatus & I_CHIPACTIVE) { | |
2509 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2510 | intstatus &= ~I_CHIPACTIVE; | |
2511 | } | |
2512 | ||
2513 | /* Ignore frame indications if rxskip is set */ | |
2514 | if (bus->rxskip) | |
2515 | intstatus &= ~I_HMB_FRAME_IND; | |
2516 | ||
2517 | /* On frame indication, read available frames */ | |
2518 | if (PKT_AVAILABLE()) { | |
2519 | framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone); | |
2520 | if (rxdone || bus->rxskip) | |
2521 | intstatus &= ~I_HMB_FRAME_IND; | |
2522 | rxlimit -= min(framecnt, rxlimit); | |
2523 | } | |
2524 | ||
2525 | /* Keep still-pending events for next scheduling */ | |
2526 | bus->intstatus = intstatus; | |
2527 | ||
2528 | clkwait: | |
ba89bf19 FL |
2529 | brcmf_sdbrcm_clrintr(bus); |
2530 | ||
5b435de0 AS |
2531 | if (data_ok(bus) && bus->ctrl_frame_stat && |
2532 | (bus->clkstate == CLK_AVAIL)) { | |
2533 | int ret, i; | |
2534 | ||
5adfeb63 | 2535 | ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad, |
5b435de0 | 2536 | SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf, |
5adfeb63 | 2537 | (u32) bus->ctrl_frame_len); |
5b435de0 AS |
2538 | |
2539 | if (ret < 0) { | |
2540 | /* On failure, abort the command and | |
2541 | terminate the frame */ | |
2542 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2543 | ret); | |
2544 | bus->tx_sderrs++; | |
2545 | ||
2546 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2547 | ||
2548 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2549 | SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, | |
2550 | NULL); | |
2551 | bus->f1regdata++; | |
2552 | ||
2553 | for (i = 0; i < 3; i++) { | |
2554 | u8 hi, lo; | |
2555 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2556 | SDIO_FUNC_1, | |
2557 | SBSDIO_FUNC1_WFRAMEBCHI, | |
2558 | NULL); | |
2559 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, | |
2560 | SDIO_FUNC_1, | |
2561 | SBSDIO_FUNC1_WFRAMEBCLO, | |
2562 | NULL); | |
2563 | bus->f1regdata += 2; | |
2564 | if ((hi == 0) && (lo == 0)) | |
2565 | break; | |
2566 | } | |
2567 | ||
2568 | } | |
2569 | if (ret == 0) | |
2570 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
2571 | ||
2572 | brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret); | |
2573 | bus->ctrl_frame_stat = false; | |
2574 | brcmf_sdbrcm_wait_event_wakeup(bus); | |
2575 | } | |
2576 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
2577 | else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate && | |
2578 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit | |
2579 | && data_ok(bus)) { | |
2580 | framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax); | |
2581 | framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt); | |
2582 | txlimit -= framecnt; | |
2583 | } | |
2584 | ||
2585 | /* Resched if events or tx frames are pending, | |
2586 | else await next interrupt */ | |
2587 | /* On failed register access, all bets are off: | |
2588 | no resched or interrupts */ | |
712ac5b3 | 2589 | if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) || |
5b435de0 AS |
2590 | brcmf_sdcard_regfail(bus->sdiodev)) { |
2591 | brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n", | |
2592 | brcmf_sdcard_regfail(bus->sdiodev)); | |
712ac5b3 | 2593 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2594 | bus->intstatus = 0; |
2595 | } else if (bus->clkstate == CLK_PENDING) { | |
2596 | brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n"); | |
2597 | resched = true; | |
2598 | } else if (bus->intstatus || bus->ipend || | |
2599 | (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) | |
2600 | && data_ok(bus)) || PKT_AVAILABLE()) { | |
2601 | resched = true; | |
2602 | } | |
2603 | ||
2604 | bus->dpc_sched = resched; | |
2605 | ||
2606 | /* If we're done for now, turn off clock request. */ | |
2607 | if ((bus->clkstate != CLK_PENDING) | |
2608 | && bus->idletime == BRCMF_IDLE_IMMEDIATE) { | |
2609 | bus->activity = false; | |
2610 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
2611 | } | |
2612 | ||
2613 | up(&bus->sdsem); | |
2614 | ||
2615 | return resched; | |
2616 | } | |
2617 | ||
b948a85c FL |
2618 | static inline void brcmf_sdbrcm_adddpctsk(struct brcmf_sdio *bus) |
2619 | { | |
2620 | struct list_head *new_hd; | |
2621 | unsigned long flags; | |
2622 | ||
2623 | if (in_interrupt()) | |
2624 | new_hd = kzalloc(sizeof(struct list_head), GFP_ATOMIC); | |
2625 | else | |
2626 | new_hd = kzalloc(sizeof(struct list_head), GFP_KERNEL); | |
2627 | if (new_hd == NULL) | |
2628 | return; | |
2629 | ||
2630 | spin_lock_irqsave(&bus->dpc_tl_lock, flags); | |
2631 | list_add_tail(new_hd, &bus->dpc_tsklst); | |
2632 | spin_unlock_irqrestore(&bus->dpc_tl_lock, flags); | |
2633 | } | |
2634 | ||
5b435de0 AS |
2635 | static int brcmf_sdbrcm_dpc_thread(void *data) |
2636 | { | |
e92eedf4 | 2637 | struct brcmf_sdio *bus = (struct brcmf_sdio *) data; |
b948a85c FL |
2638 | struct list_head *cur_hd, *tmp_hd; |
2639 | unsigned long flags; | |
5b435de0 AS |
2640 | |
2641 | allow_signal(SIGTERM); | |
2642 | /* Run until signal received */ | |
2643 | while (1) { | |
2644 | if (kthread_should_stop()) | |
2645 | break; | |
b948a85c FL |
2646 | |
2647 | if (list_empty(&bus->dpc_tsklst)) | |
2648 | if (wait_for_completion_interruptible(&bus->dpc_wait)) | |
2649 | break; | |
2650 | ||
2651 | spin_lock_irqsave(&bus->dpc_tl_lock, flags); | |
2652 | list_for_each_safe(cur_hd, tmp_hd, &bus->dpc_tsklst) { | |
2653 | spin_unlock_irqrestore(&bus->dpc_tl_lock, flags); | |
2654 | ||
2655 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) { | |
5b435de0 | 2656 | /* after stopping the bus, exit thread */ |
94c2fb82 | 2657 | brcmf_sdbrcm_bus_stop(bus->sdiodev->dev); |
5b435de0 | 2658 | bus->dpc_tsk = NULL; |
cf043172 | 2659 | spin_lock_irqsave(&bus->dpc_tl_lock, flags); |
5b435de0 AS |
2660 | break; |
2661 | } | |
b948a85c FL |
2662 | |
2663 | if (brcmf_sdbrcm_dpc(bus)) | |
2664 | brcmf_sdbrcm_adddpctsk(bus); | |
2665 | ||
2666 | spin_lock_irqsave(&bus->dpc_tl_lock, flags); | |
2667 | list_del(cur_hd); | |
2668 | kfree(cur_hd); | |
2669 | } | |
2670 | spin_unlock_irqrestore(&bus->dpc_tl_lock, flags); | |
5b435de0 AS |
2671 | } |
2672 | return 0; | |
2673 | } | |
2674 | ||
b9692d17 | 2675 | static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt) |
5b435de0 AS |
2676 | { |
2677 | int ret = -EBADE; | |
2678 | uint datalen, prec; | |
bf347bb9 | 2679 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2680 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
bf347bb9 | 2681 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
2682 | |
2683 | brcmf_dbg(TRACE, "Enter\n"); | |
2684 | ||
2685 | datalen = pkt->len; | |
2686 | ||
2687 | /* Add space for the header */ | |
2688 | skb_push(pkt, SDPCM_HDRLEN); | |
2689 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ | |
2690 | ||
2691 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2692 | ||
2693 | /* Check for existing queue, current flow-control, | |
2694 | pending event, or pending clock */ | |
2695 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
2696 | bus->fcqueued++; | |
2697 | ||
2698 | /* Priority based enq */ | |
2699 | spin_lock_bh(&bus->txqlock); | |
23677ce3 | 2700 | if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) { |
5b435de0 | 2701 | skb_pull(pkt, SDPCM_HDRLEN); |
c995788f | 2702 | brcmf_txcomplete(bus->sdiodev->dev, pkt, false); |
5b435de0 AS |
2703 | brcmu_pkt_buf_free_skb(pkt); |
2704 | brcmf_dbg(ERROR, "out of bus->txq !!!\n"); | |
2705 | ret = -ENOSR; | |
2706 | } else { | |
2707 | ret = 0; | |
2708 | } | |
2709 | spin_unlock_bh(&bus->txqlock); | |
2710 | ||
c8bf3484 FL |
2711 | if (pktq_len(&bus->txq) >= TXHI) { |
2712 | bus->txoff = ON; | |
2b459056 | 2713 | brcmf_txflowcontrol(bus->sdiodev->dev, 0, ON); |
c8bf3484 | 2714 | } |
5b435de0 | 2715 | |
8ae74654 | 2716 | #ifdef DEBUG |
5b435de0 AS |
2717 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) |
2718 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2719 | #endif | |
2720 | /* Schedule DPC if needed to send queued packet(s) */ | |
2721 | if (!bus->dpc_sched) { | |
2722 | bus->dpc_sched = true; | |
b948a85c FL |
2723 | if (bus->dpc_tsk) { |
2724 | brcmf_sdbrcm_adddpctsk(bus); | |
5b435de0 | 2725 | complete(&bus->dpc_wait); |
b948a85c | 2726 | } |
5b435de0 AS |
2727 | } |
2728 | ||
2729 | return ret; | |
2730 | } | |
2731 | ||
2732 | static int | |
e92eedf4 | 2733 | brcmf_sdbrcm_membytes(struct brcmf_sdio *bus, bool write, u32 address, u8 *data, |
5b435de0 AS |
2734 | uint size) |
2735 | { | |
2736 | int bcmerror = 0; | |
2737 | u32 sdaddr; | |
2738 | uint dsize; | |
2739 | ||
2740 | /* Determine initial transfer parameters */ | |
2741 | sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK; | |
2742 | if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK) | |
2743 | dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr); | |
2744 | else | |
2745 | dsize = size; | |
2746 | ||
2747 | /* Set the backplane window to include the start address */ | |
2748 | bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address); | |
2749 | if (bcmerror) { | |
2750 | brcmf_dbg(ERROR, "window change failed\n"); | |
2751 | goto xfer_done; | |
2752 | } | |
2753 | ||
2754 | /* Do the transfer(s) */ | |
2755 | while (size) { | |
2756 | brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n", | |
2757 | write ? "write" : "read", dsize, | |
2758 | sdaddr, address & SBSDIO_SBWINDOW_MASK); | |
2759 | bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write, | |
2760 | sdaddr, data, dsize); | |
2761 | if (bcmerror) { | |
2762 | brcmf_dbg(ERROR, "membytes transfer failed\n"); | |
2763 | break; | |
2764 | } | |
2765 | ||
2766 | /* Adjust for next transfer (if any) */ | |
2767 | size -= dsize; | |
2768 | if (size) { | |
2769 | data += dsize; | |
2770 | address += dsize; | |
2771 | bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, | |
2772 | address); | |
2773 | if (bcmerror) { | |
2774 | brcmf_dbg(ERROR, "window change failed\n"); | |
2775 | break; | |
2776 | } | |
2777 | sdaddr = 0; | |
2778 | dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size); | |
2779 | } | |
2780 | } | |
2781 | ||
2782 | xfer_done: | |
2783 | /* Return the window to backplane enumeration space for core access */ | |
2784 | if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad)) | |
2785 | brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n", | |
2786 | bus->sdiodev->sbwad); | |
2787 | ||
2788 | return bcmerror; | |
2789 | } | |
2790 | ||
8ae74654 | 2791 | #ifdef DEBUG |
5b435de0 AS |
2792 | #define CONSOLE_LINE_MAX 192 |
2793 | ||
e92eedf4 | 2794 | static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus) |
5b435de0 AS |
2795 | { |
2796 | struct brcmf_console *c = &bus->console; | |
2797 | u8 line[CONSOLE_LINE_MAX], ch; | |
2798 | u32 n, idx, addr; | |
2799 | int rv; | |
2800 | ||
2801 | /* Don't do anything until FWREADY updates console address */ | |
2802 | if (bus->console_addr == 0) | |
2803 | return 0; | |
2804 | ||
2805 | /* Read console log struct */ | |
2806 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
2807 | rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le, | |
2808 | sizeof(c->log_le)); | |
2809 | if (rv < 0) | |
2810 | return rv; | |
2811 | ||
2812 | /* Allocate console buffer (one time only) */ | |
2813 | if (c->buf == NULL) { | |
2814 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2815 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2816 | if (c->buf == NULL) | |
2817 | return -ENOMEM; | |
2818 | } | |
2819 | ||
2820 | idx = le32_to_cpu(c->log_le.idx); | |
2821 | ||
2822 | /* Protect against corrupt value */ | |
2823 | if (idx > c->bufsize) | |
2824 | return -EBADE; | |
2825 | ||
2826 | /* Skip reading the console buffer if the index pointer | |
2827 | has not moved */ | |
2828 | if (idx == c->last) | |
2829 | return 0; | |
2830 | ||
2831 | /* Read the console buffer */ | |
2832 | addr = le32_to_cpu(c->log_le.buf); | |
2833 | rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize); | |
2834 | if (rv < 0) | |
2835 | return rv; | |
2836 | ||
2837 | while (c->last != idx) { | |
2838 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2839 | if (c->last == idx) { | |
2840 | /* This would output a partial line. | |
2841 | * Instead, back up | |
2842 | * the buffer pointer and output this | |
2843 | * line next time around. | |
2844 | */ | |
2845 | if (c->last >= n) | |
2846 | c->last -= n; | |
2847 | else | |
2848 | c->last = c->bufsize - n; | |
2849 | goto break2; | |
2850 | } | |
2851 | ch = c->buf[c->last]; | |
2852 | c->last = (c->last + 1) % c->bufsize; | |
2853 | if (ch == '\n') | |
2854 | break; | |
2855 | line[n] = ch; | |
2856 | } | |
2857 | ||
2858 | if (n > 0) { | |
2859 | if (line[n - 1] == '\r') | |
2860 | n--; | |
2861 | line[n] = 0; | |
18aad4f8 | 2862 | pr_debug("CONSOLE: %s\n", line); |
5b435de0 AS |
2863 | } |
2864 | } | |
2865 | break2: | |
2866 | ||
2867 | return 0; | |
2868 | } | |
8ae74654 | 2869 | #endif /* DEBUG */ |
5b435de0 | 2870 | |
e92eedf4 | 2871 | static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len) |
5b435de0 AS |
2872 | { |
2873 | int i; | |
2874 | int ret; | |
2875 | ||
2876 | bus->ctrl_frame_stat = false; | |
5adfeb63 AS |
2877 | ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad, |
2878 | SDIO_FUNC_2, F2SYNC, frame, len); | |
5b435de0 AS |
2879 | |
2880 | if (ret < 0) { | |
2881 | /* On failure, abort the command and terminate the frame */ | |
2882 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2883 | ret); | |
2884 | bus->tx_sderrs++; | |
2885 | ||
2886 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2887 | ||
2888 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
2889 | SBSDIO_FUNC1_FRAMECTRL, | |
2890 | SFC_WF_TERM, NULL); | |
2891 | bus->f1regdata++; | |
2892 | ||
2893 | for (i = 0; i < 3; i++) { | |
2894 | u8 hi, lo; | |
2895 | hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2896 | SBSDIO_FUNC1_WFRAMEBCHI, | |
2897 | NULL); | |
2898 | lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
2899 | SBSDIO_FUNC1_WFRAMEBCLO, | |
2900 | NULL); | |
2901 | bus->f1regdata += 2; | |
2902 | if (hi == 0 && lo == 0) | |
2903 | break; | |
2904 | } | |
2905 | return ret; | |
2906 | } | |
2907 | ||
2908 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
2909 | ||
2910 | return ret; | |
2911 | } | |
2912 | ||
fcf094f4 | 2913 | static int |
47a1ce78 | 2914 | brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
2915 | { |
2916 | u8 *frame; | |
2917 | u16 len; | |
2918 | u32 swheader; | |
2919 | uint retries = 0; | |
2920 | u8 doff = 0; | |
2921 | int ret = -1; | |
47a1ce78 | 2922 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2923 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
47a1ce78 | 2924 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
2925 | |
2926 | brcmf_dbg(TRACE, "Enter\n"); | |
2927 | ||
2928 | /* Back the pointer to make a room for bus header */ | |
2929 | frame = msg - SDPCM_HDRLEN; | |
2930 | len = (msglen += SDPCM_HDRLEN); | |
2931 | ||
2932 | /* Add alignment padding (optional for ctl frames) */ | |
2933 | doff = ((unsigned long)frame % BRCMF_SDALIGN); | |
2934 | if (doff) { | |
2935 | frame -= doff; | |
2936 | len += doff; | |
2937 | msglen += doff; | |
2938 | memset(frame, 0, doff + SDPCM_HDRLEN); | |
2939 | } | |
2940 | /* precondition: doff < BRCMF_SDALIGN */ | |
2941 | doff += SDPCM_HDRLEN; | |
2942 | ||
2943 | /* Round send length to next SDIO block */ | |
2944 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2945 | u16 pad = bus->blocksize - (len % bus->blocksize); | |
2946 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | |
2947 | len += pad; | |
2948 | } else if (len % BRCMF_SDALIGN) { | |
2949 | len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN); | |
2950 | } | |
2951 | ||
2952 | /* Satisfy length-alignment requirements */ | |
2953 | if (len & (ALIGNMENT - 1)) | |
2954 | len = roundup(len, ALIGNMENT); | |
2955 | ||
2956 | /* precondition: IS_ALIGNED((unsigned long)frame, 2) */ | |
2957 | ||
2958 | /* Need to lock here to protect txseq and SDIO tx calls */ | |
2959 | down(&bus->sdsem); | |
2960 | ||
2961 | bus_wake(bus); | |
2962 | ||
2963 | /* Make sure backplane clock is on */ | |
2964 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
2965 | ||
2966 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ | |
2967 | *(__le16 *) frame = cpu_to_le16((u16) msglen); | |
2968 | *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen); | |
2969 | ||
2970 | /* Software tag: channel, sequence number, data offset */ | |
2971 | swheader = | |
2972 | ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & | |
2973 | SDPCM_CHANNEL_MASK) | |
2974 | | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) & | |
2975 | SDPCM_DOFFSET_MASK); | |
2976 | put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN); | |
2977 | put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader)); | |
2978 | ||
2979 | if (!data_ok(bus)) { | |
2980 | brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n", | |
2981 | bus->tx_max, bus->tx_seq); | |
2982 | bus->ctrl_frame_stat = true; | |
2983 | /* Send from dpc */ | |
2984 | bus->ctrl_frame_buf = frame; | |
2985 | bus->ctrl_frame_len = len; | |
2986 | ||
2987 | brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat); | |
2988 | ||
23677ce3 | 2989 | if (!bus->ctrl_frame_stat) { |
5b435de0 AS |
2990 | brcmf_dbg(INFO, "ctrl_frame_stat == false\n"); |
2991 | ret = 0; | |
2992 | } else { | |
2993 | brcmf_dbg(INFO, "ctrl_frame_stat == true\n"); | |
2994 | ret = -1; | |
2995 | } | |
2996 | } | |
2997 | ||
2998 | if (ret == -1) { | |
1e023829 JP |
2999 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
3000 | frame, len, "Tx Frame:\n"); | |
3001 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && | |
3002 | BRCMF_HDRS_ON(), | |
3003 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
5b435de0 AS |
3004 | |
3005 | do { | |
3006 | ret = brcmf_tx_frame(bus, frame, len); | |
3007 | } while (ret < 0 && retries++ < TXRETRIES); | |
3008 | } | |
3009 | ||
3010 | if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) { | |
3011 | bus->activity = false; | |
3012 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, true); | |
3013 | } | |
3014 | ||
3015 | up(&bus->sdsem); | |
3016 | ||
3017 | if (ret) | |
28a1a3bd | 3018 | bus->tx_ctlerrs++; |
5b435de0 | 3019 | else |
28a1a3bd | 3020 | bus->tx_ctlpkts++; |
5b435de0 AS |
3021 | |
3022 | return ret ? -EIO : 0; | |
3023 | } | |
3024 | ||
fcf094f4 | 3025 | static int |
532cdd3b | 3026 | brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
3027 | { |
3028 | int timeleft; | |
3029 | uint rxlen = 0; | |
3030 | bool pending; | |
532cdd3b | 3031 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3032 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
532cdd3b | 3033 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3034 | |
3035 | brcmf_dbg(TRACE, "Enter\n"); | |
3036 | ||
3037 | /* Wait until control frame is available */ | |
3038 | timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending); | |
3039 | ||
3040 | down(&bus->sdsem); | |
3041 | rxlen = bus->rxlen; | |
3042 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
3043 | bus->rxlen = 0; | |
3044 | up(&bus->sdsem); | |
3045 | ||
3046 | if (rxlen) { | |
3047 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3048 | rxlen, msglen); | |
3049 | } else if (timeleft == 0) { | |
3050 | brcmf_dbg(ERROR, "resumed on timeout\n"); | |
23677ce3 | 3051 | } else if (pending) { |
5b435de0 AS |
3052 | brcmf_dbg(CTL, "cancelled\n"); |
3053 | return -ERESTARTSYS; | |
3054 | } else { | |
3055 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
3056 | } | |
3057 | ||
3058 | if (rxlen) | |
28a1a3bd | 3059 | bus->rx_ctlpkts++; |
5b435de0 | 3060 | else |
28a1a3bd | 3061 | bus->rx_ctlerrs++; |
5b435de0 AS |
3062 | |
3063 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3064 | } | |
3065 | ||
e92eedf4 | 3066 | static int brcmf_sdbrcm_downloadvars(struct brcmf_sdio *bus, void *arg, int len) |
5b435de0 AS |
3067 | { |
3068 | int bcmerror = 0; | |
3069 | ||
3070 | brcmf_dbg(TRACE, "Enter\n"); | |
3071 | ||
3072 | /* Basic sanity checks */ | |
3fb1d8d2 | 3073 | if (bus->sdiodev->bus_if->drvr_up) { |
5b435de0 AS |
3074 | bcmerror = -EISCONN; |
3075 | goto err; | |
3076 | } | |
3077 | if (!len) { | |
3078 | bcmerror = -EOVERFLOW; | |
3079 | goto err; | |
3080 | } | |
3081 | ||
3082 | /* Free the old ones and replace with passed variables */ | |
3083 | kfree(bus->vars); | |
3084 | ||
3085 | bus->vars = kmalloc(len, GFP_ATOMIC); | |
3086 | bus->varsz = bus->vars ? len : 0; | |
3087 | if (bus->vars == NULL) { | |
3088 | bcmerror = -ENOMEM; | |
3089 | goto err; | |
3090 | } | |
3091 | ||
3092 | /* Copy the passed variables, which should include the | |
3093 | terminating double-null */ | |
3094 | memcpy(bus->vars, arg, bus->varsz); | |
3095 | err: | |
3096 | return bcmerror; | |
3097 | } | |
3098 | ||
e92eedf4 | 3099 | static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus) |
5b435de0 AS |
3100 | { |
3101 | int bcmerror = 0; | |
3102 | u32 varsize; | |
3103 | u32 varaddr; | |
3104 | u8 *vbuffer; | |
3105 | u32 varsizew; | |
3106 | __le32 varsizew_le; | |
8ae74654 | 3107 | #ifdef DEBUG |
5b435de0 | 3108 | char *nvram_ularray; |
8ae74654 | 3109 | #endif /* DEBUG */ |
5b435de0 AS |
3110 | |
3111 | /* Even if there are no vars are to be written, we still | |
3112 | need to set the ramsize. */ | |
3113 | varsize = bus->varsz ? roundup(bus->varsz, 4) : 0; | |
3114 | varaddr = (bus->ramsize - 4) - varsize; | |
3115 | ||
3116 | if (bus->vars) { | |
3117 | vbuffer = kzalloc(varsize, GFP_ATOMIC); | |
3118 | if (!vbuffer) | |
3119 | return -ENOMEM; | |
3120 | ||
3121 | memcpy(vbuffer, bus->vars, bus->varsz); | |
3122 | ||
3123 | /* Write the vars list */ | |
3124 | bcmerror = | |
3125 | brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize); | |
8ae74654 | 3126 | #ifdef DEBUG |
5b435de0 AS |
3127 | /* Verify NVRAM bytes */ |
3128 | brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize); | |
3129 | nvram_ularray = kmalloc(varsize, GFP_ATOMIC); | |
c40701ea JJ |
3130 | if (!nvram_ularray) { |
3131 | kfree(vbuffer); | |
5b435de0 | 3132 | return -ENOMEM; |
c40701ea | 3133 | } |
5b435de0 AS |
3134 | |
3135 | /* Upload image to verify downloaded contents. */ | |
3136 | memset(nvram_ularray, 0xaa, varsize); | |
3137 | ||
3138 | /* Read the vars list to temp buffer for comparison */ | |
3139 | bcmerror = | |
3140 | brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray, | |
3141 | varsize); | |
3142 | if (bcmerror) { | |
3143 | brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n", | |
3144 | bcmerror, varsize, varaddr); | |
3145 | } | |
3146 | /* Compare the org NVRAM with the one read from RAM */ | |
3147 | if (memcmp(vbuffer, nvram_ularray, varsize)) | |
3148 | brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n"); | |
3149 | else | |
3150 | brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n"); | |
3151 | ||
3152 | kfree(nvram_ularray); | |
8ae74654 | 3153 | #endif /* DEBUG */ |
5b435de0 AS |
3154 | |
3155 | kfree(vbuffer); | |
3156 | } | |
3157 | ||
3158 | /* adjust to the user specified RAM */ | |
3159 | brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize); | |
3160 | brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n", | |
3161 | varaddr, varsize); | |
3162 | varsize = ((bus->ramsize - 4) - varaddr); | |
3163 | ||
3164 | /* | |
3165 | * Determine the length token: | |
3166 | * Varsize, converted to words, in lower 16-bits, checksum | |
3167 | * in upper 16-bits. | |
3168 | */ | |
3169 | if (bcmerror) { | |
3170 | varsizew = 0; | |
3171 | varsizew_le = cpu_to_le32(0); | |
3172 | } else { | |
3173 | varsizew = varsize / 4; | |
3174 | varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF); | |
3175 | varsizew_le = cpu_to_le32(varsizew); | |
3176 | } | |
3177 | ||
3178 | brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n", | |
3179 | varsize, varsizew); | |
3180 | ||
3181 | /* Write the length token to the last word */ | |
3182 | bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4), | |
3183 | (u8 *)&varsizew_le, 4); | |
3184 | ||
3185 | return bcmerror; | |
3186 | } | |
3187 | ||
e92eedf4 | 3188 | static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter) |
5b435de0 AS |
3189 | { |
3190 | uint retries; | |
5b435de0 | 3191 | int bcmerror = 0; |
99ba15cd | 3192 | struct chip_info *ci = bus->ci; |
5b435de0 AS |
3193 | |
3194 | /* To enter download state, disable ARM and reset SOCRAM. | |
3195 | * To exit download state, simply reset ARM (default is RAM boot). | |
3196 | */ | |
3197 | if (enter) { | |
3198 | bus->alp_only = true; | |
3199 | ||
086a2e0a | 3200 | ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3); |
5b435de0 | 3201 | |
d77e70ff | 3202 | ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM); |
5b435de0 AS |
3203 | |
3204 | /* Clear the top bit of memory */ | |
3205 | if (bus->ramsize) { | |
3206 | u32 zeros = 0; | |
3207 | brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4, | |
3208 | (u8 *)&zeros, 4); | |
3209 | } | |
3210 | } else { | |
6ca687d9 | 3211 | if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) { |
5b435de0 AS |
3212 | brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n"); |
3213 | bcmerror = -EBADE; | |
3214 | goto fail; | |
3215 | } | |
3216 | ||
3217 | bcmerror = brcmf_sdbrcm_write_vars(bus); | |
3218 | if (bcmerror) { | |
3219 | brcmf_dbg(ERROR, "no vars written to RAM\n"); | |
3220 | bcmerror = 0; | |
3221 | } | |
3222 | ||
3223 | w_sdreg32(bus, 0xFFFFFFFF, | |
3224 | offsetof(struct sdpcmd_regs, intstatus), &retries); | |
3225 | ||
d77e70ff | 3226 | ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3); |
5b435de0 AS |
3227 | |
3228 | /* Allow HT Clock now that the ARM is running. */ | |
3229 | bus->alp_only = false; | |
3230 | ||
712ac5b3 | 3231 | bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD; |
5b435de0 AS |
3232 | } |
3233 | fail: | |
3234 | return bcmerror; | |
3235 | } | |
3236 | ||
e92eedf4 | 3237 | static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus) |
5b435de0 AS |
3238 | { |
3239 | if (bus->firmware->size < bus->fw_ptr + len) | |
3240 | len = bus->firmware->size - bus->fw_ptr; | |
3241 | ||
3242 | memcpy(buf, &bus->firmware->data[bus->fw_ptr], len); | |
3243 | bus->fw_ptr += len; | |
3244 | return len; | |
3245 | } | |
3246 | ||
e92eedf4 | 3247 | static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus) |
5b435de0 AS |
3248 | { |
3249 | int offset = 0; | |
3250 | uint len; | |
3251 | u8 *memblock = NULL, *memptr; | |
3252 | int ret; | |
3253 | ||
3254 | brcmf_dbg(INFO, "Enter\n"); | |
3255 | ||
52e1409f | 3256 | ret = request_firmware(&bus->firmware, BRCMF_SDIO_FW_NAME, |
5b435de0 AS |
3257 | &bus->sdiodev->func[2]->dev); |
3258 | if (ret) { | |
3259 | brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret); | |
3260 | return ret; | |
3261 | } | |
3262 | bus->fw_ptr = 0; | |
3263 | ||
3264 | memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC); | |
3265 | if (memblock == NULL) { | |
3266 | ret = -ENOMEM; | |
3267 | goto err; | |
3268 | } | |
3269 | if ((u32)(unsigned long)memblock % BRCMF_SDALIGN) | |
3270 | memptr += (BRCMF_SDALIGN - | |
3271 | ((u32)(unsigned long)memblock % BRCMF_SDALIGN)); | |
3272 | ||
3273 | /* Download image */ | |
3274 | while ((len = | |
3275 | brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) { | |
3276 | ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len); | |
3277 | if (ret) { | |
3278 | brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n", | |
3279 | ret, MEMBLOCK, offset); | |
3280 | goto err; | |
3281 | } | |
3282 | ||
3283 | offset += MEMBLOCK; | |
3284 | } | |
3285 | ||
3286 | err: | |
3287 | kfree(memblock); | |
3288 | ||
3289 | release_firmware(bus->firmware); | |
3290 | bus->fw_ptr = 0; | |
3291 | ||
3292 | return ret; | |
3293 | } | |
3294 | ||
3295 | /* | |
3296 | * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file | |
3297 | * and ending in a NUL. | |
3298 | * Removes carriage returns, empty lines, comment lines, and converts | |
3299 | * newlines to NULs. | |
3300 | * Shortens buffer as needed and pads with NULs. End of buffer is marked | |
3301 | * by two NULs. | |
3302 | */ | |
3303 | ||
3304 | static uint brcmf_process_nvram_vars(char *varbuf, uint len) | |
3305 | { | |
3306 | char *dp; | |
3307 | bool findNewline; | |
3308 | int column; | |
3309 | uint buf_len, n; | |
3310 | ||
3311 | dp = varbuf; | |
3312 | ||
3313 | findNewline = false; | |
3314 | column = 0; | |
3315 | ||
3316 | for (n = 0; n < len; n++) { | |
3317 | if (varbuf[n] == 0) | |
3318 | break; | |
3319 | if (varbuf[n] == '\r') | |
3320 | continue; | |
3321 | if (findNewline && varbuf[n] != '\n') | |
3322 | continue; | |
3323 | findNewline = false; | |
3324 | if (varbuf[n] == '#') { | |
3325 | findNewline = true; | |
3326 | continue; | |
3327 | } | |
3328 | if (varbuf[n] == '\n') { | |
3329 | if (column == 0) | |
3330 | continue; | |
3331 | *dp++ = 0; | |
3332 | column = 0; | |
3333 | continue; | |
3334 | } | |
3335 | *dp++ = varbuf[n]; | |
3336 | column++; | |
3337 | } | |
3338 | buf_len = dp - varbuf; | |
3339 | ||
3340 | while (dp < varbuf + n) | |
3341 | *dp++ = 0; | |
3342 | ||
3343 | return buf_len; | |
3344 | } | |
3345 | ||
e92eedf4 | 3346 | static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus) |
5b435de0 AS |
3347 | { |
3348 | uint len; | |
3349 | char *memblock = NULL; | |
3350 | char *bufp; | |
3351 | int ret; | |
3352 | ||
52e1409f | 3353 | ret = request_firmware(&bus->firmware, BRCMF_SDIO_NV_NAME, |
5b435de0 AS |
3354 | &bus->sdiodev->func[2]->dev); |
3355 | if (ret) { | |
3356 | brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret); | |
3357 | return ret; | |
3358 | } | |
3359 | bus->fw_ptr = 0; | |
3360 | ||
3361 | memblock = kmalloc(MEMBLOCK, GFP_ATOMIC); | |
3362 | if (memblock == NULL) { | |
3363 | ret = -ENOMEM; | |
3364 | goto err; | |
3365 | } | |
3366 | ||
3367 | len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus); | |
3368 | ||
3369 | if (len > 0 && len < MEMBLOCK) { | |
3370 | bufp = (char *)memblock; | |
3371 | bufp[len] = 0; | |
3372 | len = brcmf_process_nvram_vars(bufp, len); | |
3373 | bufp += len; | |
3374 | *bufp++ = 0; | |
3375 | if (len) | |
3376 | ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1); | |
3377 | if (ret) | |
3378 | brcmf_dbg(ERROR, "error downloading vars: %d\n", ret); | |
3379 | } else { | |
3380 | brcmf_dbg(ERROR, "error reading nvram file: %d\n", len); | |
3381 | ret = -EIO; | |
3382 | } | |
3383 | ||
3384 | err: | |
3385 | kfree(memblock); | |
3386 | ||
3387 | release_firmware(bus->firmware); | |
3388 | bus->fw_ptr = 0; | |
3389 | ||
3390 | return ret; | |
3391 | } | |
3392 | ||
e92eedf4 | 3393 | static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus) |
5b435de0 AS |
3394 | { |
3395 | int bcmerror = -1; | |
3396 | ||
3397 | /* Keep arm in reset */ | |
3398 | if (brcmf_sdbrcm_download_state(bus, true)) { | |
3399 | brcmf_dbg(ERROR, "error placing ARM core in reset\n"); | |
3400 | goto err; | |
3401 | } | |
3402 | ||
3403 | /* External image takes precedence if specified */ | |
3404 | if (brcmf_sdbrcm_download_code_file(bus)) { | |
3405 | brcmf_dbg(ERROR, "dongle image file download failed\n"); | |
3406 | goto err; | |
3407 | } | |
3408 | ||
3409 | /* External nvram takes precedence if specified */ | |
3410 | if (brcmf_sdbrcm_download_nvram(bus)) | |
3411 | brcmf_dbg(ERROR, "dongle nvram file download failed\n"); | |
3412 | ||
3413 | /* Take arm out of reset */ | |
3414 | if (brcmf_sdbrcm_download_state(bus, false)) { | |
3415 | brcmf_dbg(ERROR, "error getting out of ARM core reset\n"); | |
3416 | goto err; | |
3417 | } | |
3418 | ||
3419 | bcmerror = 0; | |
3420 | ||
3421 | err: | |
3422 | return bcmerror; | |
3423 | } | |
3424 | ||
3425 | static bool | |
e92eedf4 | 3426 | brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus) |
5b435de0 AS |
3427 | { |
3428 | bool ret; | |
3429 | ||
3430 | /* Download the firmware */ | |
3431 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3432 | ||
3433 | ret = _brcmf_sdbrcm_download_firmware(bus) == 0; | |
3434 | ||
3435 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
3436 | ||
3437 | return ret; | |
3438 | } | |
3439 | ||
99a0b8ff | 3440 | static int brcmf_sdbrcm_bus_init(struct device *dev) |
5b435de0 | 3441 | { |
fa20b911 | 3442 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3443 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
fa20b911 | 3444 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3445 | unsigned long timeout; |
3446 | uint retries = 0; | |
3447 | u8 ready, enable; | |
3448 | int err, ret = 0; | |
3449 | u8 saveclk; | |
3450 | ||
3451 | brcmf_dbg(TRACE, "Enter\n"); | |
3452 | ||
3453 | /* try to download image and nvram to the dongle */ | |
fa20b911 | 3454 | if (bus_if->state == BRCMF_BUS_DOWN) { |
5b435de0 AS |
3455 | if (!(brcmf_sdbrcm_download_firmware(bus))) |
3456 | return -1; | |
3457 | } | |
3458 | ||
712ac5b3 | 3459 | if (!bus->sdiodev->bus_if->drvr) |
5b435de0 AS |
3460 | return 0; |
3461 | ||
3462 | /* Start the watchdog timer */ | |
28a1a3bd | 3463 | bus->tickcnt = 0; |
5b435de0 AS |
3464 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); |
3465 | ||
3466 | down(&bus->sdsem); | |
3467 | ||
3468 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
3469 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3470 | if (bus->clkstate != CLK_AVAIL) | |
3471 | goto exit; | |
3472 | ||
3473 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
3474 | saveclk = | |
3475 | brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
3476 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
3477 | if (!err) { | |
3478 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3479 | SBSDIO_FUNC1_CHIPCLKCSR, | |
3480 | (saveclk | SBSDIO_FORCE_HT), &err); | |
3481 | } | |
3482 | if (err) { | |
3483 | brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err); | |
3484 | goto exit; | |
3485 | } | |
3486 | ||
3487 | /* Enable function 2 (frame transfers) */ | |
3488 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
3489 | offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries); | |
3490 | enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2); | |
3491 | ||
3492 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx, | |
3493 | enable, NULL); | |
3494 | ||
3495 | timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY); | |
3496 | ready = 0; | |
3497 | while (enable != ready) { | |
3498 | ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0, | |
3499 | SDIO_CCCR_IORx, NULL); | |
3500 | if (time_after(jiffies, timeout)) | |
3501 | break; | |
3502 | else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50)) | |
3503 | /* prevent busy waiting if it takes too long */ | |
3504 | msleep_interruptible(20); | |
3505 | } | |
3506 | ||
3507 | brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready); | |
3508 | ||
3509 | /* If F2 successfully enabled, set core and enable interrupts */ | |
3510 | if (ready == enable) { | |
3511 | /* Set up the interrupt mask and enable interrupts */ | |
3512 | bus->hostintmask = HOSTINTMASK; | |
3513 | w_sdreg32(bus, bus->hostintmask, | |
3514 | offsetof(struct sdpcmd_regs, hostintmask), &retries); | |
3515 | ||
3516 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3517 | SBSDIO_WATERMARK, 8, &err); | |
c0e89f08 | 3518 | } else { |
5b435de0 AS |
3519 | /* Disable F2 again */ |
3520 | enable = SDIO_FUNC_ENABLE_1; | |
3521 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, | |
3522 | SDIO_CCCR_IOEx, enable, NULL); | |
c0e89f08 | 3523 | ret = -ENODEV; |
5b435de0 AS |
3524 | } |
3525 | ||
3526 | /* Restore previous clock setting */ | |
3527 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3528 | SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err); | |
3529 | ||
e2f93cc3 | 3530 | if (ret == 0) { |
ba89bf19 | 3531 | ret = brcmf_sdio_intr_register(bus->sdiodev); |
e2f93cc3 FL |
3532 | if (ret != 0) |
3533 | brcmf_dbg(ERROR, "intr register failed:%d\n", ret); | |
3534 | } | |
3535 | ||
5b435de0 | 3536 | /* If we didn't come up, turn off backplane clock */ |
d9126e0c | 3537 | if (bus_if->state != BRCMF_BUS_DATA) |
5b435de0 AS |
3538 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); |
3539 | ||
3540 | exit: | |
3541 | up(&bus->sdsem); | |
3542 | ||
3543 | return ret; | |
3544 | } | |
3545 | ||
3546 | void brcmf_sdbrcm_isr(void *arg) | |
3547 | { | |
e92eedf4 | 3548 | struct brcmf_sdio *bus = (struct brcmf_sdio *) arg; |
5b435de0 AS |
3549 | |
3550 | brcmf_dbg(TRACE, "Enter\n"); | |
3551 | ||
3552 | if (!bus) { | |
3553 | brcmf_dbg(ERROR, "bus is null pointer, exiting\n"); | |
3554 | return; | |
3555 | } | |
3556 | ||
712ac5b3 | 3557 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) { |
5b435de0 AS |
3558 | brcmf_dbg(ERROR, "bus is down. we have nothing to do\n"); |
3559 | return; | |
3560 | } | |
3561 | /* Count the interrupt call */ | |
3562 | bus->intrcount++; | |
3563 | bus->ipend = true; | |
3564 | ||
3565 | /* Shouldn't get this interrupt if we're sleeping? */ | |
3566 | if (bus->sleeping) { | |
3567 | brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n"); | |
3568 | return; | |
3569 | } | |
3570 | ||
3571 | /* Disable additional interrupts (is this needed now)? */ | |
3572 | if (!bus->intr) | |
3573 | brcmf_dbg(ERROR, "isr w/o interrupt configured!\n"); | |
3574 | ||
3575 | bus->dpc_sched = true; | |
b948a85c FL |
3576 | if (bus->dpc_tsk) { |
3577 | brcmf_sdbrcm_adddpctsk(bus); | |
5b435de0 | 3578 | complete(&bus->dpc_wait); |
b948a85c | 3579 | } |
5b435de0 AS |
3580 | } |
3581 | ||
cad2b26b | 3582 | static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus) |
5b435de0 | 3583 | { |
8ae74654 | 3584 | #ifdef DEBUG |
cad2b26b | 3585 | struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev); |
8ae74654 | 3586 | #endif /* DEBUG */ |
5b435de0 AS |
3587 | |
3588 | brcmf_dbg(TIMER, "Enter\n"); | |
3589 | ||
5b435de0 AS |
3590 | /* Ignore the timer if simulating bus down */ |
3591 | if (bus->sleeping) | |
3592 | return false; | |
3593 | ||
3594 | down(&bus->sdsem); | |
3595 | ||
3596 | /* Poll period: check device if appropriate. */ | |
3597 | if (bus->poll && (++bus->polltick >= bus->pollrate)) { | |
3598 | u32 intstatus = 0; | |
3599 | ||
3600 | /* Reset poll tick */ | |
3601 | bus->polltick = 0; | |
3602 | ||
3603 | /* Check device if no interrupts */ | |
3604 | if (!bus->intr || (bus->intrcount == bus->lastintrs)) { | |
3605 | ||
3606 | if (!bus->dpc_sched) { | |
3607 | u8 devpend; | |
3608 | devpend = brcmf_sdcard_cfg_read(bus->sdiodev, | |
3609 | SDIO_FUNC_0, SDIO_CCCR_INTx, | |
3610 | NULL); | |
3611 | intstatus = | |
3612 | devpend & (INTR_STATUS_FUNC1 | | |
3613 | INTR_STATUS_FUNC2); | |
3614 | } | |
3615 | ||
3616 | /* If there is something, make like the ISR and | |
3617 | schedule the DPC */ | |
3618 | if (intstatus) { | |
3619 | bus->pollcnt++; | |
3620 | bus->ipend = true; | |
3621 | ||
3622 | bus->dpc_sched = true; | |
b948a85c FL |
3623 | if (bus->dpc_tsk) { |
3624 | brcmf_sdbrcm_adddpctsk(bus); | |
5b435de0 | 3625 | complete(&bus->dpc_wait); |
b948a85c | 3626 | } |
5b435de0 AS |
3627 | } |
3628 | } | |
3629 | ||
3630 | /* Update interrupt tracking */ | |
3631 | bus->lastintrs = bus->intrcount; | |
3632 | } | |
8ae74654 | 3633 | #ifdef DEBUG |
5b435de0 | 3634 | /* Poll for console output periodically */ |
cad2b26b | 3635 | if (bus_if->state == BRCMF_BUS_DATA && |
8d169aa0 | 3636 | bus->console_interval != 0) { |
5b435de0 AS |
3637 | bus->console.count += BRCMF_WD_POLL_MS; |
3638 | if (bus->console.count >= bus->console_interval) { | |
3639 | bus->console.count -= bus->console_interval; | |
3640 | /* Make sure backplane clock is on */ | |
3641 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3642 | if (brcmf_sdbrcm_readconsole(bus) < 0) | |
3643 | /* stop on error */ | |
3644 | bus->console_interval = 0; | |
3645 | } | |
3646 | } | |
8ae74654 | 3647 | #endif /* DEBUG */ |
5b435de0 AS |
3648 | |
3649 | /* On idle timeout clear activity flag and/or turn off clock */ | |
3650 | if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) { | |
3651 | if (++bus->idlecount >= bus->idletime) { | |
3652 | bus->idlecount = 0; | |
3653 | if (bus->activity) { | |
3654 | bus->activity = false; | |
3655 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
3656 | } else { | |
3657 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
3658 | } | |
3659 | } | |
3660 | } | |
3661 | ||
3662 | up(&bus->sdsem); | |
3663 | ||
3664 | return bus->ipend; | |
3665 | } | |
3666 | ||
3667 | static bool brcmf_sdbrcm_chipmatch(u16 chipid) | |
3668 | { | |
3669 | if (chipid == BCM4329_CHIP_ID) | |
3670 | return true; | |
ce2d7d7e FL |
3671 | if (chipid == BCM4330_CHIP_ID) |
3672 | return true; | |
5b435de0 AS |
3673 | return false; |
3674 | } | |
3675 | ||
e92eedf4 | 3676 | static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus) |
5b435de0 AS |
3677 | { |
3678 | brcmf_dbg(TRACE, "Enter\n"); | |
3679 | ||
3680 | kfree(bus->rxbuf); | |
3681 | bus->rxctl = bus->rxbuf = NULL; | |
3682 | bus->rxlen = 0; | |
3683 | ||
3684 | kfree(bus->databuf); | |
3685 | bus->databuf = NULL; | |
3686 | } | |
3687 | ||
e92eedf4 | 3688 | static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus) |
5b435de0 AS |
3689 | { |
3690 | brcmf_dbg(TRACE, "Enter\n"); | |
3691 | ||
b01a6b3c | 3692 | if (bus->sdiodev->bus_if->maxctl) { |
5b435de0 | 3693 | bus->rxblen = |
b01a6b3c | 3694 | roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), |
5b435de0 AS |
3695 | ALIGNMENT) + BRCMF_SDALIGN; |
3696 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
3697 | if (!(bus->rxbuf)) | |
3698 | goto fail; | |
3699 | } | |
3700 | ||
3701 | /* Allocate buffer to receive glomed packet */ | |
3702 | bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC); | |
3703 | if (!(bus->databuf)) { | |
3704 | /* release rxbuf which was already located as above */ | |
3705 | if (!bus->rxblen) | |
3706 | kfree(bus->rxbuf); | |
3707 | goto fail; | |
3708 | } | |
3709 | ||
3710 | /* Align the buffer */ | |
3711 | if ((unsigned long)bus->databuf % BRCMF_SDALIGN) | |
3712 | bus->dataptr = bus->databuf + (BRCMF_SDALIGN - | |
3713 | ((unsigned long)bus->databuf % BRCMF_SDALIGN)); | |
3714 | else | |
3715 | bus->dataptr = bus->databuf; | |
3716 | ||
3717 | return true; | |
3718 | ||
3719 | fail: | |
3720 | return false; | |
3721 | } | |
3722 | ||
5b435de0 | 3723 | static bool |
e92eedf4 | 3724 | brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva) |
5b435de0 AS |
3725 | { |
3726 | u8 clkctl = 0; | |
3727 | int err = 0; | |
3728 | int reg_addr; | |
3729 | u32 reg_val; | |
99ba15cd | 3730 | u8 idx; |
5b435de0 AS |
3731 | |
3732 | bus->alp_only = true; | |
3733 | ||
3734 | /* Return the window to backplane enumeration space for core access */ | |
3735 | if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE)) | |
3736 | brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n"); | |
3737 | ||
18aad4f8 | 3738 | pr_debug("F1 signature read @0x18000000=0x%4x\n", |
abb7fbb4 | 3739 | brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE)); |
5b435de0 AS |
3740 | |
3741 | /* | |
a97e4fc5 | 3742 | * Force PLL off until brcmf_sdio_chip_attach() |
5b435de0 AS |
3743 | * programs PLL control regs |
3744 | */ | |
3745 | ||
3746 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3747 | SBSDIO_FUNC1_CHIPCLKCSR, | |
3748 | BRCMF_INIT_CLKCTL1, &err); | |
3749 | if (!err) | |
3750 | clkctl = | |
3751 | brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1, | |
3752 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
3753 | ||
3754 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
3755 | brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", | |
3756 | err, BRCMF_INIT_CLKCTL1, clkctl); | |
3757 | goto fail; | |
3758 | } | |
3759 | ||
a97e4fc5 FL |
3760 | if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) { |
3761 | brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n"); | |
5b435de0 AS |
3762 | goto fail; |
3763 | } | |
3764 | ||
3765 | if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) { | |
3766 | brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip); | |
3767 | goto fail; | |
3768 | } | |
3769 | ||
e12afb6c FL |
3770 | brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci, |
3771 | SDIO_DRIVE_STRENGTH); | |
5b435de0 | 3772 | |
454d2a88 | 3773 | /* Get info on the SOCRAM cores... */ |
5b435de0 AS |
3774 | bus->ramsize = bus->ci->ramsize; |
3775 | if (!(bus->ramsize)) { | |
3776 | brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n"); | |
3777 | goto fail; | |
3778 | } | |
3779 | ||
3780 | /* Set core control so an SDIO reset does a backplane reset */ | |
99ba15cd FL |
3781 | idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
3782 | reg_addr = bus->ci->c_inf[idx].base + | |
5b435de0 | 3783 | offsetof(struct sdpcmd_regs, corecontrol); |
abb7fbb4 | 3784 | reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr); |
ce454e88 | 3785 | brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, reg_val | CC_BPRESEN); |
5b435de0 AS |
3786 | |
3787 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); | |
3788 | ||
3789 | /* Locate an appropriately-aligned portion of hdrbuf */ | |
3790 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
3791 | BRCMF_SDALIGN); | |
3792 | ||
3793 | /* Set the poll and/or interrupt flags */ | |
3794 | bus->intr = true; | |
3795 | bus->poll = false; | |
3796 | if (bus->poll) | |
3797 | bus->pollrate = 1; | |
3798 | ||
3799 | return true; | |
3800 | ||
3801 | fail: | |
3802 | return false; | |
3803 | } | |
3804 | ||
e92eedf4 | 3805 | static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus) |
5b435de0 AS |
3806 | { |
3807 | brcmf_dbg(TRACE, "Enter\n"); | |
3808 | ||
3809 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
3810 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx, | |
3811 | SDIO_FUNC_ENABLE_1, NULL); | |
3812 | ||
712ac5b3 | 3813 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
3814 | bus->sleeping = false; |
3815 | bus->rxflow = false; | |
3816 | ||
3817 | /* Done with backplane-dependent accesses, can drop clock... */ | |
3818 | brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1, | |
3819 | SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
3820 | ||
3821 | /* ...and initialize clock/power states */ | |
3822 | bus->clkstate = CLK_SDONLY; | |
3823 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
3824 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
3825 | ||
3826 | /* Query the F2 block size, set roundup accordingly */ | |
3827 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
3828 | bus->roundup = min(max_roundup, bus->blocksize); | |
3829 | ||
3830 | /* bus module does not support packet chaining */ | |
3831 | bus->use_rxchain = false; | |
3832 | bus->sd_rxchain = false; | |
3833 | ||
3834 | return true; | |
3835 | } | |
3836 | ||
3837 | static int | |
3838 | brcmf_sdbrcm_watchdog_thread(void *data) | |
3839 | { | |
e92eedf4 | 3840 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3841 | |
3842 | allow_signal(SIGTERM); | |
3843 | /* Run until signal received */ | |
3844 | while (1) { | |
3845 | if (kthread_should_stop()) | |
3846 | break; | |
3847 | if (!wait_for_completion_interruptible(&bus->watchdog_wait)) { | |
cad2b26b | 3848 | brcmf_sdbrcm_bus_watchdog(bus); |
5b435de0 | 3849 | /* Count the tick for reference */ |
28a1a3bd | 3850 | bus->tickcnt++; |
5b435de0 AS |
3851 | } else |
3852 | break; | |
3853 | } | |
3854 | return 0; | |
3855 | } | |
3856 | ||
3857 | static void | |
3858 | brcmf_sdbrcm_watchdog(unsigned long data) | |
3859 | { | |
e92eedf4 | 3860 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3861 | |
3862 | if (bus->watchdog_tsk) { | |
3863 | complete(&bus->watchdog_wait); | |
3864 | /* Reschedule the watchdog */ | |
3865 | if (bus->wd_timer_valid) | |
3866 | mod_timer(&bus->timer, | |
3867 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
3868 | } | |
3869 | } | |
3870 | ||
e92eedf4 | 3871 | static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus) |
5b435de0 AS |
3872 | { |
3873 | brcmf_dbg(TRACE, "Enter\n"); | |
3874 | ||
3875 | if (bus->ci) { | |
3876 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3877 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
a8a6c045 | 3878 | brcmf_sdio_chip_detach(&bus->ci); |
5b435de0 AS |
3879 | if (bus->vars && bus->varsz) |
3880 | kfree(bus->vars); | |
3881 | bus->vars = NULL; | |
3882 | } | |
3883 | ||
3884 | brcmf_dbg(TRACE, "Disconnected\n"); | |
3885 | } | |
3886 | ||
3887 | /* Detach and free everything */ | |
e92eedf4 | 3888 | static void brcmf_sdbrcm_release(struct brcmf_sdio *bus) |
5b435de0 AS |
3889 | { |
3890 | brcmf_dbg(TRACE, "Enter\n"); | |
3891 | ||
3892 | if (bus) { | |
3893 | /* De-register interrupt handler */ | |
ba89bf19 | 3894 | brcmf_sdio_intr_unregister(bus->sdiodev); |
5b435de0 | 3895 | |
5f947ad9 FL |
3896 | if (bus->sdiodev->bus_if->drvr) { |
3897 | brcmf_detach(bus->sdiodev->dev); | |
5b435de0 | 3898 | brcmf_sdbrcm_release_dongle(bus); |
5b435de0 AS |
3899 | } |
3900 | ||
3901 | brcmf_sdbrcm_release_malloc(bus); | |
3902 | ||
3903 | kfree(bus); | |
3904 | } | |
3905 | ||
3906 | brcmf_dbg(TRACE, "Disconnected\n"); | |
3907 | } | |
3908 | ||
4175b88b | 3909 | void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev) |
5b435de0 AS |
3910 | { |
3911 | int ret; | |
e92eedf4 | 3912 | struct brcmf_sdio *bus; |
5b435de0 | 3913 | |
5b435de0 AS |
3914 | brcmf_dbg(TRACE, "Enter\n"); |
3915 | ||
3916 | /* We make an assumption about address window mappings: | |
3917 | * regsva == SI_ENUM_BASE*/ | |
3918 | ||
3919 | /* Allocate private bus interface state */ | |
e92eedf4 | 3920 | bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); |
5b435de0 AS |
3921 | if (!bus) |
3922 | goto fail; | |
3923 | ||
3924 | bus->sdiodev = sdiodev; | |
3925 | sdiodev->bus = bus; | |
b83db862 | 3926 | skb_queue_head_init(&bus->glom); |
5b435de0 AS |
3927 | bus->txbound = BRCMF_TXBOUND; |
3928 | bus->rxbound = BRCMF_RXBOUND; | |
3929 | bus->txminmax = BRCMF_TXMINMAX; | |
3930 | bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1; | |
3931 | bus->usebufpool = false; /* Use bufpool if allocated, | |
3932 | else use locally malloced rxbuf */ | |
3933 | ||
3934 | /* attempt to attach to the dongle */ | |
3935 | if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) { | |
3936 | brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n"); | |
3937 | goto fail; | |
3938 | } | |
3939 | ||
3940 | spin_lock_init(&bus->txqlock); | |
3941 | init_waitqueue_head(&bus->ctrl_wait); | |
3942 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
3943 | ||
3944 | /* Set up the watchdog timer */ | |
3945 | init_timer(&bus->timer); | |
3946 | bus->timer.data = (unsigned long)bus; | |
3947 | bus->timer.function = brcmf_sdbrcm_watchdog; | |
3948 | ||
3949 | /* Initialize thread based operation and lock */ | |
3950 | sema_init(&bus->sdsem, 1); | |
3951 | ||
3952 | /* Initialize watchdog thread */ | |
3953 | init_completion(&bus->watchdog_wait); | |
3954 | bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread, | |
3955 | bus, "brcmf_watchdog"); | |
3956 | if (IS_ERR(bus->watchdog_tsk)) { | |
02f77195 | 3957 | pr_warn("brcmf_watchdog thread failed to start\n"); |
5b435de0 AS |
3958 | bus->watchdog_tsk = NULL; |
3959 | } | |
3960 | /* Initialize DPC thread */ | |
3961 | init_completion(&bus->dpc_wait); | |
b948a85c FL |
3962 | INIT_LIST_HEAD(&bus->dpc_tsklst); |
3963 | spin_lock_init(&bus->dpc_tl_lock); | |
5b435de0 AS |
3964 | bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread, |
3965 | bus, "brcmf_dpc"); | |
3966 | if (IS_ERR(bus->dpc_tsk)) { | |
02f77195 | 3967 | pr_warn("brcmf_dpc thread failed to start\n"); |
5b435de0 AS |
3968 | bus->dpc_tsk = NULL; |
3969 | } | |
3970 | ||
a9ffda88 FL |
3971 | /* Assign bus interface call back */ |
3972 | bus->sdiodev->bus_if->brcmf_bus_stop = brcmf_sdbrcm_bus_stop; | |
99a0b8ff | 3973 | bus->sdiodev->bus_if->brcmf_bus_init = brcmf_sdbrcm_bus_init; |
b9692d17 | 3974 | bus->sdiodev->bus_if->brcmf_bus_txdata = brcmf_sdbrcm_bus_txdata; |
fcf094f4 FL |
3975 | bus->sdiodev->bus_if->brcmf_bus_txctl = brcmf_sdbrcm_bus_txctl; |
3976 | bus->sdiodev->bus_if->brcmf_bus_rxctl = brcmf_sdbrcm_bus_rxctl; | |
5b435de0 | 3977 | /* Attach to the brcmf/OS/network interface */ |
2447ffb0 | 3978 | ret = brcmf_attach(SDPCM_RESERVE, bus->sdiodev->dev); |
712ac5b3 | 3979 | if (ret != 0) { |
5b435de0 AS |
3980 | brcmf_dbg(ERROR, "brcmf_attach failed\n"); |
3981 | goto fail; | |
3982 | } | |
3983 | ||
3984 | /* Allocate buffers */ | |
3985 | if (!(brcmf_sdbrcm_probe_malloc(bus))) { | |
3986 | brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n"); | |
3987 | goto fail; | |
3988 | } | |
3989 | ||
3990 | if (!(brcmf_sdbrcm_probe_init(bus))) { | |
3991 | brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n"); | |
3992 | goto fail; | |
3993 | } | |
3994 | ||
5b435de0 AS |
3995 | brcmf_dbg(INFO, "completed!!\n"); |
3996 | ||
3997 | /* if firmware path present try to download and bring up bus */ | |
ed683c98 | 3998 | ret = brcmf_bus_start(bus->sdiodev->dev); |
5b435de0 AS |
3999 | if (ret != 0) { |
4000 | if (ret == -ENOLINK) { | |
4001 | brcmf_dbg(ERROR, "dongle is not responding\n"); | |
4002 | goto fail; | |
4003 | } | |
4004 | } | |
15d45b6f | 4005 | |
5b435de0 AS |
4006 | return bus; |
4007 | ||
4008 | fail: | |
4009 | brcmf_sdbrcm_release(bus); | |
4010 | return NULL; | |
4011 | } | |
4012 | ||
4013 | void brcmf_sdbrcm_disconnect(void *ptr) | |
4014 | { | |
e92eedf4 | 4015 | struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr; |
5b435de0 AS |
4016 | |
4017 | brcmf_dbg(TRACE, "Enter\n"); | |
4018 | ||
4019 | if (bus) | |
4020 | brcmf_sdbrcm_release(bus); | |
4021 | ||
4022 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4023 | } | |
4024 | ||
5b435de0 | 4025 | void |
e92eedf4 | 4026 | brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick) |
5b435de0 | 4027 | { |
5b435de0 | 4028 | /* Totally stop the timer */ |
23677ce3 | 4029 | if (!wdtick && bus->wd_timer_valid) { |
5b435de0 AS |
4030 | del_timer_sync(&bus->timer); |
4031 | bus->wd_timer_valid = false; | |
4032 | bus->save_ms = wdtick; | |
4033 | return; | |
4034 | } | |
4035 | ||
ece960ea | 4036 | /* don't start the wd until fw is loaded */ |
712ac5b3 | 4037 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) |
ece960ea FL |
4038 | return; |
4039 | ||
5b435de0 AS |
4040 | if (wdtick) { |
4041 | if (bus->save_ms != BRCMF_WD_POLL_MS) { | |
23677ce3 | 4042 | if (bus->wd_timer_valid) |
5b435de0 AS |
4043 | /* Stop timer and restart at new value */ |
4044 | del_timer_sync(&bus->timer); | |
4045 | ||
4046 | /* Create timer again when watchdog period is | |
4047 | dynamically changed or in the first instance | |
4048 | */ | |
4049 | bus->timer.expires = | |
4050 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000; | |
4051 | add_timer(&bus->timer); | |
4052 | ||
4053 | } else { | |
4054 | /* Re arm the timer, at last watchdog period */ | |
4055 | mod_timer(&bus->timer, | |
4056 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
4057 | } | |
4058 | ||
4059 | bus->wd_timer_valid = true; | |
4060 | bus->save_ms = wdtick; | |
4061 | } | |
4062 | } |