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brcmfmac: remove dummy cache flush/invalidate function
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / pcie.c
CommitLineData
9e37f045
HM		 1/* Copyright (c) 2014 Broadcom Corporation
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/firmware.h>
19#include <linux/pci.h>
20#include <linux/vmalloc.h>
21#include <linux/delay.h>
9e37f045
HM		 22#include <linux/interrupt.h>
23#include <linux/bcma/bcma.h>
24#include <linux/sched.h>
a1d69c60 25#include <asm/unaligned.h>
9e37f045
HM		 26
27#include <soc.h>
28#include <chipcommon.h>
29#include <brcmu_utils.h>
30#include <brcmu_wifi.h>
31#include <brcm_hw_ids.h>
32
a8e8ed34 33#include "debug.h"
d14f78b9 34#include "bus.h"
9e37f045
HM		 35#include "commonring.h"
36#include "msgbuf.h"
37#include "pcie.h"
38#include "firmware.h"
39#include "chip.h"
40
41
42enum brcmf_pcie_state {
43 BRCMFMAC_PCIE_STATE_DOWN,
44 BRCMFMAC_PCIE_STATE_UP
45};
46
47
48#define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin"
49#define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt"
9e37f045
HM		 50#define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin"
51#define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt"
52#define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin"
53#define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt"
67f3b6a3
AS		 54#define BRCMF_PCIE_4358_FW_NAME "brcm/brcmfmac4358-pcie.bin"
55#define BRCMF_PCIE_4358_NVRAM_NAME "brcm/brcmfmac4358-pcie.txt"
9e37f045
HM		 56
57#define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */
58
59#define BRCMF_PCIE_TCM_MAP_SIZE (4096 * 1024)
60#define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
61
62/* backplane addres space accessed by BAR0 */
63#define BRCMF_PCIE_BAR0_WINDOW 0x80
64#define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
65#define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
66
67#define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
68#define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
69
70#define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
71#define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
72
73#define BRCMF_PCIE_REG_INTSTATUS 0x90
74#define BRCMF_PCIE_REG_INTMASK 0x94
75#define BRCMF_PCIE_REG_SBMBX 0x98
76
77#define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
78#define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
79#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
80#define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
81#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
82#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
83
84#define BRCMF_PCIE_GENREV1 1
85#define BRCMF_PCIE_GENREV2 2
86
87#define BRCMF_PCIE2_INTA 0x01
88#define BRCMF_PCIE2_INTB 0x02
89
90#define BRCMF_PCIE_INT_0 0x01
91#define BRCMF_PCIE_INT_1 0x02
92#define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
93 BRCMF_PCIE_INT_1)
94
95#define BRCMF_PCIE_MB_INT_FN0_0 0x0100
96#define BRCMF_PCIE_MB_INT_FN0_1 0x0200
97#define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
98#define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
99#define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
100#define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
101#define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
102#define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
103#define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
104#define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
105
106#define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
107 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
108 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
109 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
110 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
111 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
112 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
113 BRCMF_PCIE_MB_INT_D2H3_DB1)
114
fd5e8cb8 115#define BRCMF_PCIE_MIN_SHARED_VERSION 5
9e37f045
HM		 116#define BRCMF_PCIE_MAX_SHARED_VERSION 5
117#define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
9e37f045
HM		 118
119#define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
120#define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
121
122#define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
123#define BRCMF_SHARED_RING_BASE_OFFSET 52
124#define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
125#define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
126#define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
127#define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
128#define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
129#define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
130#define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
131#define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
132#define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
133
134#define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
135#define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
136#define BRCMF_RING_H2D_RING_MEM_OFFSET 4
137#define BRCMF_RING_H2D_RING_STATE_OFFSET 8
138
139#define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
140#define BRCMF_RING_MAX_ITEM_OFFSET 4
141#define BRCMF_RING_LEN_ITEMS_OFFSET 6
142#define BRCMF_RING_MEM_SZ 16
143#define BRCMF_RING_STATE_SZ 8
144
145#define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4
146#define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
147#define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
148#define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
149#define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
150#define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
151
152#define BRCMF_DEF_MAX_RXBUFPOST 255
153
154#define BRCMF_CONSOLE_BUFADDR_OFFSET 8
155#define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
156#define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
157
158#define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
159#define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
160
161#define BRCMF_D2H_DEV_D3_ACK 0x00000001
162#define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
163#define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
164
165#define BRCMF_H2D_HOST_D3_INFORM 0x00000001
166#define BRCMF_H2D_HOST_DS_ACK 0x00000002
4eb3af7c
HM		 167#define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
168#define BRCMF_H2D_HOST_D0_INFORM 0x00000010
9e37f045
HM		 169
170#define BRCMF_PCIE_MBDATA_TIMEOUT 2000
171
bd4f82e3
HM		 172#define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
173#define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
174#define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
175#define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
176#define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
177#define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
178#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
179#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
180#define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
181#define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
182#define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
183#define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
184#define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
185
9e37f045
HM		 186
187MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
188MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
7fca40eb
AS		 189MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME);
190MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME);
9e37f045
HM		 191MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
192MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
67f3b6a3
AS		 193MODULE_FIRMWARE(BRCMF_PCIE_4358_FW_NAME);
194MODULE_FIRMWARE(BRCMF_PCIE_4358_NVRAM_NAME);
9e37f045
HM		 195
196
197struct brcmf_pcie_console {
198 u32 base_addr;
199 u32 buf_addr;
200 u32 bufsize;
201 u32 read_idx;
202 u8 log_str[256];
203 u8 log_idx;
204};
205
206struct brcmf_pcie_shared_info {
207 u32 tcm_base_address;
208 u32 flags;
209 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
210 struct brcmf_pcie_ringbuf *flowrings;
211 u16 max_rxbufpost;
212 u32 nrof_flowrings;
213 u32 rx_dataoffset;
214 u32 htod_mb_data_addr;
215 u32 dtoh_mb_data_addr;
216 u32 ring_info_addr;
217 struct brcmf_pcie_console console;
218 void *scratch;
219 dma_addr_t scratch_dmahandle;
220 void *ringupd;
221 dma_addr_t ringupd_dmahandle;
222};
223
224struct brcmf_pcie_core_info {
225 u32 base;
226 u32 wrapbase;
227};
228
229struct brcmf_pciedev_info {
230 enum brcmf_pcie_state state;
231 bool in_irq;
232 bool irq_requested;
233 struct pci_dev *pdev;
234 char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
235 char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
236 void __iomem *regs;
237 void __iomem *tcm;
238 u32 tcm_size;
239 u32 ram_base;
240 u32 ram_size;
241 struct brcmf_chip *ci;
242 u32 coreid;
243 u32 generic_corerev;
244 struct brcmf_pcie_shared_info shared;
245 void (*ringbell)(struct brcmf_pciedev_info *devinfo);
246 wait_queue_head_t mbdata_resp_wait;
247 bool mbdata_completed;
248 bool irq_allocated;
4eb3af7c 249 bool wowl_enabled;
9e37f045
HM		 250};
251
252struct brcmf_pcie_ringbuf {
253 struct brcmf_commonring commonring;
254 dma_addr_t dma_handle;
255 u32 w_idx_addr;
256 u32 r_idx_addr;
257 struct brcmf_pciedev_info *devinfo;
258 u8 id;
259};
260
261
262static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
263 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
264 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
265 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
266 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
267 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
268};
269
270static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
271 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
272 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
273 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
274 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
275 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
276};
277
278
9e37f045
HM		 279static u32
280brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
281{
282 void __iomem *address = devinfo->regs + reg_offset;
283
284 return (ioread32(address));
285}
286
287
288static void
289brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
290 u32 value)
291{
292 void __iomem *address = devinfo->regs + reg_offset;
293
294 iowrite32(value, address);
295}
296
297
298static u8
299brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
300{
301 void __iomem *address = devinfo->tcm + mem_offset;
302
303 return (ioread8(address));
304}
305
306
307static u16
308brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
309{
310 void __iomem *address = devinfo->tcm + mem_offset;
311
312 return (ioread16(address));
313}
314
315
316static void
317brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
318 u16 value)
319{
320 void __iomem *address = devinfo->tcm + mem_offset;
321
322 iowrite16(value, address);
323}
324
325
326static u32
327brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
328{
329 void __iomem *address = devinfo->tcm + mem_offset;
330
331 return (ioread32(address));
332}
333
334
335static void
336brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
337 u32 value)
338{
339 void __iomem *address = devinfo->tcm + mem_offset;
340
341 iowrite32(value, address);
342}
343
344
345static u32
346brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
347{
348 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
349
350 return (ioread32(addr));
351}
352
353
354static void
355brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
356 u32 value)
357{
358 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
359
360 iowrite32(value, addr);
361}
362
363
364static void
365brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
366 void *srcaddr, u32 len)
367{
368 void __iomem *address = devinfo->tcm + mem_offset;
369 __le32 *src32;
370 __le16 *src16;
371 u8 *src8;
372
373 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
374 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
375 src8 = (u8 *)srcaddr;
376 while (len) {
377 iowrite8(*src8, address);
378 address++;
379 src8++;
380 len--;
381 }
382 } else {
383 len = len / 2;
384 src16 = (__le16 *)srcaddr;
385 while (len) {
386 iowrite16(le16_to_cpu(*src16), address);
387 address += 2;
388 src16++;
389 len--;
390 }
391 }
392 } else {
393 len = len / 4;
394 src32 = (__le32 *)srcaddr;
395 while (len) {
396 iowrite32(le32_to_cpu(*src32), address);
397 address += 4;
398 src32++;
399 len--;
400 }
401 }
402}
403
404
405#define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
406 CHIPCREGOFFS(reg), value)
407
408
409static void
410brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
411{
412 const struct pci_dev *pdev = devinfo->pdev;
413 struct brcmf_core *core;
414 u32 bar0_win;
415
416 core = brcmf_chip_get_core(devinfo->ci, coreid);
417 if (core) {
418 bar0_win = core->base;
419 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
420 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
421 &bar0_win) == 0) {
422 if (bar0_win != core->base) {
423 bar0_win = core->base;
424 pci_write_config_dword(pdev,
425 BRCMF_PCIE_BAR0_WINDOW,
426 bar0_win);
427 }
428 }
429 } else {
430 brcmf_err("Unsupported core selected %x\n", coreid);
431 }
432}
433
434
bd4f82e3 435static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
9e37f045 436{
bd4f82e3
HM		 437 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
438 BRCMF_PCIE_CFGREG_PM_CSR,
439 BRCMF_PCIE_CFGREG_MSI_CAP,
440 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
441 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
442 BRCMF_PCIE_CFGREG_MSI_DATA,
443 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
444 BRCMF_PCIE_CFGREG_RBAR_CTRL,
445 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
446 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
447 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
9e37f045
HM		 448 u32 i;
449 u32 val;
bd4f82e3 450 u32 lsc;
9e37f045
HM		 451
452 if (!devinfo->ci)
453 return;
454
bd4f82e3
HM		 455 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
456 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
457 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
458 lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
459 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
460 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
9e37f045 461
bd4f82e3
HM		 462 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
463 WRITECC32(devinfo, watchdog, 4);
9e37f045
HM		 464 msleep(100);
465
bd4f82e3
HM		 466 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
467 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
468 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
469 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
470
9e37f045
HM		 471 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
472 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
473 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
474 cfg_offset[i]);
475 val = brcmf_pcie_read_reg32(devinfo,
476 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
477 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
478 cfg_offset[i], val);
479 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
480 val);
481 }
482}
483
484
485static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
486{
487 u32 config;
488
489 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
490 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
bd4f82e3 491 brcmf_pcie_reset_device(devinfo);
9e37f045
HM		 492 /* BAR1 window may not be sized properly */
493 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
494 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
495 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
496 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
497
498 device_wakeup_enable(&devinfo->pdev->dev);
499}
500
501
502static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
503{
9e37f045
HM		 504 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
505 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
506 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
507 5);
508 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
509 0);
510 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
511 7);
512 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
513 0);
514 }
515 return 0;
516}
517
518
519static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
520 u32 resetintr)
521{
522 struct brcmf_core *core;
523
524 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
525 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
526 brcmf_chip_resetcore(core, 0, 0, 0);
527 }
528
d380ebc9 529 return !brcmf_chip_set_active(devinfo->ci, resetintr);
9e37f045
HM		 530}
531
532
4eb3af7c 533static int
9e37f045
HM		 534brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
535{
536 struct brcmf_pcie_shared_info *shared;
537 u32 addr;
538 u32 cur_htod_mb_data;
539 u32 i;
540
541 shared = &devinfo->shared;
542 addr = shared->htod_mb_data_addr;
543 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
544
545 if (cur_htod_mb_data != 0)
546 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
547 cur_htod_mb_data);
548
549 i = 0;
550 while (cur_htod_mb_data != 0) {
551 msleep(10);
552 i++;
553 if (i > 100)
4eb3af7c 554 return -EIO;
9e37f045
HM		 555 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
556 }
557
558 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
559 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
560 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
4eb3af7c
HM		 561
562 return 0;
9e37f045
HM		 563}
564
565
566static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
567{
568 struct brcmf_pcie_shared_info *shared;
569 u32 addr;
570 u32 dtoh_mb_data;
571
572 shared = &devinfo->shared;
573 addr = shared->dtoh_mb_data_addr;
574 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
575
576 if (!dtoh_mb_data)
577 return;
578
579 brcmf_pcie_write_tcm32(devinfo, addr, 0);
580
581 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
582 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
583 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
584 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
585 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
586 }
587 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
588 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
ebcc2f51 589 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
9e37f045
HM		 590 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
591 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
592 devinfo->mbdata_completed = true;
593 wake_up(&devinfo->mbdata_resp_wait);
594 }
ebcc2f51 595 }
9e37f045
HM		 596}
597
598
599static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
600{
601 struct brcmf_pcie_shared_info *shared;
602 struct brcmf_pcie_console *console;
603 u32 addr;
604
605 shared = &devinfo->shared;
606 console = &shared->console;
607 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
608 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
609
610 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
611 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
612 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
613 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
614
615 brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
616 console->base_addr, console->buf_addr, console->bufsize);
617}
618
619
620static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
621{
622 struct brcmf_pcie_console *console;
623 u32 addr;
624 u8 ch;
625 u32 newidx;
626
627 console = &devinfo->shared.console;
628 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
629 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
630 while (newidx != console->read_idx) {
631 addr = console->buf_addr + console->read_idx;
632 ch = brcmf_pcie_read_tcm8(devinfo, addr);
633 console->read_idx++;
634 if (console->read_idx == console->bufsize)
635 console->read_idx = 0;
636 if (ch == '\r')
637 continue;
638 console->log_str[console->log_idx] = ch;
639 console->log_idx++;
640 if ((ch != '\n') &&
641 (console->log_idx == (sizeof(console->log_str) - 2))) {
642 ch = '\n';
643 console->log_str[console->log_idx] = ch;
644 console->log_idx++;
645 }
9e37f045
HM		 646 if (ch == '\n') {
647 console->log_str[console->log_idx] = 0;
ef5671d2 648 brcmf_dbg(PCIE, "CONSOLE: %s", console->log_str);
9e37f045
HM		 649 console->log_idx = 0;
650 }
651 }
652}
653
654
655static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
656{
657 u32 reg_value;
658
659 brcmf_dbg(PCIE, "RING !\n");
660 reg_value = brcmf_pcie_read_reg32(devinfo,
661 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
662 reg_value |= BRCMF_PCIE2_INTB;
663 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
664 reg_value);
665}
666
667
668static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
669{
670 brcmf_dbg(PCIE, "RING !\n");
671 /* Any arbitrary value will do, lets use 1 */
672 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
673}
674
675
676static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
677{
678 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
679 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
680 0);
681 else
682 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
683 0);
684}
685
686
687static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
688{
689 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
690 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
691 BRCMF_PCIE_INT_DEF);
692 else
693 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
694 BRCMF_PCIE_MB_INT_D2H_DB |
695 BRCMF_PCIE_MB_INT_FN0_0 |
696 BRCMF_PCIE_MB_INT_FN0_1);
697}
698
699
700static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
701{
702 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
703 u32 status;
704
705 status = 0;
706 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
707 if (status) {
708 brcmf_pcie_intr_disable(devinfo);
709 brcmf_dbg(PCIE, "Enter\n");
710 return IRQ_WAKE_THREAD;
711 }
712 return IRQ_NONE;
713}
714
715
716static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
717{
718 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
719
720 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
721 brcmf_pcie_intr_disable(devinfo);
722 brcmf_dbg(PCIE, "Enter\n");
723 return IRQ_WAKE_THREAD;
724 }
725 return IRQ_NONE;
726}
727
728
729static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
730{
731 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
732 const struct pci_dev *pdev = devinfo->pdev;
733 u32 status;
734
735 devinfo->in_irq = true;
736 status = 0;
737 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
738 brcmf_dbg(PCIE, "Enter %x\n", status);
739 if (status) {
740 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
741 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
742 brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
743 }
744 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
745 brcmf_pcie_intr_enable(devinfo);
746 devinfo->in_irq = false;
747 return IRQ_HANDLED;
748}
749
750
751static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
752{
753 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
754 u32 status;
755
756 devinfo->in_irq = true;
757 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
758 brcmf_dbg(PCIE, "Enter %x\n", status);
759 if (status) {
760 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
761 status);
762 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
763 BRCMF_PCIE_MB_INT_FN0_1))
764 brcmf_pcie_handle_mb_data(devinfo);
765 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
766 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
767 brcmf_proto_msgbuf_rx_trigger(
768 &devinfo->pdev->dev);
769 }
770 }
771 brcmf_pcie_bus_console_read(devinfo);
772 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
773 brcmf_pcie_intr_enable(devinfo);
774 devinfo->in_irq = false;
775 return IRQ_HANDLED;
776}
777
778
779static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
780{
781 struct pci_dev *pdev;
782
783 pdev = devinfo->pdev;
784
785 brcmf_pcie_intr_disable(devinfo);
786
787 brcmf_dbg(PCIE, "Enter\n");
788 /* is it a v1 or v2 implementation */
789 devinfo->irq_requested = false;
e9efa340 790 pci_enable_msi(pdev);
9e37f045
HM		 791 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
792 if (request_threaded_irq(pdev->irq,
793 brcmf_pcie_quick_check_isr_v1,
794 brcmf_pcie_isr_thread_v1,
795 IRQF_SHARED, "brcmf_pcie_intr",
796 devinfo)) {
e9efa340 797 pci_disable_msi(pdev);
9e37f045
HM		 798 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
799 return -EIO;
800 }
801 } else {
802 if (request_threaded_irq(pdev->irq,
803 brcmf_pcie_quick_check_isr_v2,
804 brcmf_pcie_isr_thread_v2,
805 IRQF_SHARED, "brcmf_pcie_intr",
806 devinfo)) {
e9efa340 807 pci_disable_msi(pdev);
9e37f045
HM		 808 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
809 return -EIO;
810 }
811 }
812 devinfo->irq_requested = true;
813 devinfo->irq_allocated = true;
814 return 0;
815}
816
817
818static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
819{
820 struct pci_dev *pdev;
821 u32 status;
822 u32 count;
823
824 if (!devinfo->irq_allocated)
825 return;
826
827 pdev = devinfo->pdev;
828
829 brcmf_pcie_intr_disable(devinfo);
830 if (!devinfo->irq_requested)
831 return;
832 devinfo->irq_requested = false;
833 free_irq(pdev->irq, devinfo);
e9efa340 834 pci_disable_msi(pdev);
9e37f045
HM		 835
836 msleep(50);
837 count = 0;
838 while ((devinfo->in_irq) && (count < 20)) {
839 msleep(50);
840 count++;
841 }
842 if (devinfo->in_irq)
843 brcmf_err("Still in IRQ (processing) !!!\n");
844
845 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
846 status = 0;
847 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
848 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
849 } else {
850 status = brcmf_pcie_read_reg32(devinfo,
851 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
852 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
853 status);
854 }
855 devinfo->irq_allocated = false;
856}
857
858
859static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
860{
861 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
862 struct brcmf_pciedev_info *devinfo = ring->devinfo;
863 struct brcmf_commonring *commonring = &ring->commonring;
864
865 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
866 return -EIO;
867
868 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
869 commonring->w_ptr, ring->id);
870
871 brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
872
873 return 0;
874}
875
876
877static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
878{
879 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
880 struct brcmf_pciedev_info *devinfo = ring->devinfo;
881 struct brcmf_commonring *commonring = &ring->commonring;
882
883 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
884 return -EIO;
885
886 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
887 commonring->r_ptr, ring->id);
888
889 brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
890
891 return 0;
892}
893
894
895static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
896{
897 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
898 struct brcmf_pciedev_info *devinfo = ring->devinfo;
899
900 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
901 return -EIO;
902
903 devinfo->ringbell(devinfo);
904
905 return 0;
906}
907
908
909static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
910{
911 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
912 struct brcmf_pciedev_info *devinfo = ring->devinfo;
913 struct brcmf_commonring *commonring = &ring->commonring;
914
915 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
916 return -EIO;
917
918 commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
919
920 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
921 commonring->w_ptr, ring->id);
922
923 return 0;
924}
925
926
927static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
928{
929 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
930 struct brcmf_pciedev_info *devinfo = ring->devinfo;
931 struct brcmf_commonring *commonring = &ring->commonring;
932
933 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
934 return -EIO;
935
936 commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
937
938 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
939 commonring->r_ptr, ring->id);
940
941 return 0;
942}
943
944
945static void *
946brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
947 u32 size, u32 tcm_dma_phys_addr,
948 dma_addr_t *dma_handle)
949{
950 void *ring;
83297aaa 951 u64 address;
9e37f045
HM		 952
953 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
954 GFP_KERNEL);
955 if (!ring)
956 return NULL;
957
83297aaa 958 address = (u64)*dma_handle;
9e37f045
HM		 959 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
960 address & 0xffffffff);
961 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
962
963 memset(ring, 0, size);
964
965 return (ring);
966}
967
968
969static struct brcmf_pcie_ringbuf *
970brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
971 u32 tcm_ring_phys_addr)
972{
973 void *dma_buf;
974 dma_addr_t dma_handle;
975 struct brcmf_pcie_ringbuf *ring;
976 u32 size;
977 u32 addr;
978
979 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
980 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
981 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
982 &dma_handle);
983 if (!dma_buf)
984 return NULL;
985
986 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
987 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
988 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
989 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
990
991 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
992 if (!ring) {
993 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
994 dma_handle);
995 return NULL;
996 }
997 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
998 brcmf_ring_itemsize[ring_id], dma_buf);
999 ring->dma_handle = dma_handle;
1000 ring->devinfo = devinfo;
1001 brcmf_commonring_register_cb(&ring->commonring,
1002 brcmf_pcie_ring_mb_ring_bell,
1003 brcmf_pcie_ring_mb_update_rptr,
1004 brcmf_pcie_ring_mb_update_wptr,
1005 brcmf_pcie_ring_mb_write_rptr,
1006 brcmf_pcie_ring_mb_write_wptr, ring);
1007
1008 return (ring);
1009}
1010
1011
1012static void brcmf_pcie_release_ringbuffer(struct device *dev,
1013 struct brcmf_pcie_ringbuf *ring)
1014{
1015 void *dma_buf;
1016 u32 size;
1017
1018 if (!ring)
1019 return;
1020
1021 dma_buf = ring->commonring.buf_addr;
1022 if (dma_buf) {
1023 size = ring->commonring.depth * ring->commonring.item_len;
1024 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1025 }
1026 kfree(ring);
1027}
1028
1029
1030static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1031{
1032 u32 i;
1033
1034 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1035 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1036 devinfo->shared.commonrings[i]);
1037 devinfo->shared.commonrings[i] = NULL;
1038 }
1039 kfree(devinfo->shared.flowrings);
1040 devinfo->shared.flowrings = NULL;
1041}
1042
1043
1044static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1045{
1046 struct brcmf_pcie_ringbuf *ring;
1047 struct brcmf_pcie_ringbuf *rings;
1048 u32 ring_addr;
1049 u32 d2h_w_idx_ptr;
1050 u32 d2h_r_idx_ptr;
1051 u32 h2d_w_idx_ptr;
1052 u32 h2d_r_idx_ptr;
1053 u32 addr;
1054 u32 ring_mem_ptr;
1055 u32 i;
1056 u16 max_sub_queues;
1057
1058 ring_addr = devinfo->shared.ring_info_addr;
1059 brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1060
1061 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1062 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1063 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1064 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1065 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1066 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1067 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1068 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1069
1070 addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1071 ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1072
1073 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1074 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1075 if (!ring)
1076 goto fail;
1077 ring->w_idx_addr = h2d_w_idx_ptr;
1078 ring->r_idx_addr = h2d_r_idx_ptr;
1079 ring->id = i;
1080 devinfo->shared.commonrings[i] = ring;
1081
1082 h2d_w_idx_ptr += sizeof(u32);
1083 h2d_r_idx_ptr += sizeof(u32);
1084 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1085 }
1086
1087 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1088 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1089 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1090 if (!ring)
1091 goto fail;
1092 ring->w_idx_addr = d2h_w_idx_ptr;
1093 ring->r_idx_addr = d2h_r_idx_ptr;
1094 ring->id = i;
1095 devinfo->shared.commonrings[i] = ring;
1096
1097 d2h_w_idx_ptr += sizeof(u32);
1098 d2h_r_idx_ptr += sizeof(u32);
1099 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1100 }
1101
1102 addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1103 max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1104 devinfo->shared.nrof_flowrings =
1105 max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1106 rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1107 GFP_KERNEL);
1108 if (!rings)
1109 goto fail;
1110
1111 brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1112 devinfo->shared.nrof_flowrings);
1113
1114 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1115 ring = &rings[i];
1116 ring->devinfo = devinfo;
1117 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1118 brcmf_commonring_register_cb(&ring->commonring,
1119 brcmf_pcie_ring_mb_ring_bell,
1120 brcmf_pcie_ring_mb_update_rptr,
1121 brcmf_pcie_ring_mb_update_wptr,
1122 brcmf_pcie_ring_mb_write_rptr,
1123 brcmf_pcie_ring_mb_write_wptr,
1124 ring);
1125 ring->w_idx_addr = h2d_w_idx_ptr;
1126 ring->r_idx_addr = h2d_r_idx_ptr;
1127 h2d_w_idx_ptr += sizeof(u32);
1128 h2d_r_idx_ptr += sizeof(u32);
1129 }
1130 devinfo->shared.flowrings = rings;
1131
1132 return 0;
1133
1134fail:
1135 brcmf_err("Allocating commonring buffers failed\n");
1136 brcmf_pcie_release_ringbuffers(devinfo);
1137 return -ENOMEM;
1138}
1139
1140
1141static void
1142brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1143{
1144 if (devinfo->shared.scratch)
1145 dma_free_coherent(&devinfo->pdev->dev,
1146 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1147 devinfo->shared.scratch,
1148 devinfo->shared.scratch_dmahandle);
1149 if (devinfo->shared.ringupd)
1150 dma_free_coherent(&devinfo->pdev->dev,
1151 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1152 devinfo->shared.ringupd,
1153 devinfo->shared.ringupd_dmahandle);
1154}
1155
1156static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1157{
83297aaa 1158 u64 address;
9e37f045
HM		 1159 u32 addr;
1160
1161 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1162 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1163 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1164 if (!devinfo->shared.scratch)
1165 goto fail;
1166
1167 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
9e37f045
HM		 1168
1169 addr = devinfo->shared.tcm_base_address +
1170 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
83297aaa 1171 address = (u64)devinfo->shared.scratch_dmahandle;
9e37f045
HM		 1172 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1173 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1174 addr = devinfo->shared.tcm_base_address +
1175 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1176 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1177
1178 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1179 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1180 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1181 if (!devinfo->shared.ringupd)
1182 goto fail;
1183
1184 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
9e37f045
HM		 1185
1186 addr = devinfo->shared.tcm_base_address +
1187 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
83297aaa 1188 address = (u64)devinfo->shared.ringupd_dmahandle;
9e37f045
HM		 1189 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1190 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1191 addr = devinfo->shared.tcm_base_address +
1192 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1193 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1194 return 0;
1195
1196fail:
1197 brcmf_err("Allocating scratch buffers failed\n");
1198 brcmf_pcie_release_scratchbuffers(devinfo);
1199 return -ENOMEM;
1200}
1201
1202
1203static void brcmf_pcie_down(struct device *dev)
1204{
1205}
1206
1207
1208static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1209{
1210 return 0;
1211}
1212
1213
1214static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1215 uint len)
1216{
1217 return 0;
1218}
1219
1220
1221static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1222 uint len)
1223{
1224 return 0;
1225}
1226
1227
4eb3af7c
HM		 1228static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1229{
1230 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1231 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1232 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1233
1234 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1235 devinfo->wowl_enabled = enabled;
1236 if (enabled)
1237 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1238 else
1239 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1240}
1241
1242
9e37f045
HM		 1243static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1244 .txdata = brcmf_pcie_tx,
1245 .stop = brcmf_pcie_down,
1246 .txctl = brcmf_pcie_tx_ctlpkt,
1247 .rxctl = brcmf_pcie_rx_ctlpkt,
4eb3af7c 1248 .wowl_config = brcmf_pcie_wowl_config,
9e37f045
HM		 1249};
1250
1251
1252static int
1253brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1254 u32 sharedram_addr)
1255{
1256 struct brcmf_pcie_shared_info *shared;
1257 u32 addr;
1258 u32 version;
1259
1260 shared = &devinfo->shared;
1261 shared->tcm_base_address = sharedram_addr;
1262
1263 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1264 version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1265 brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1266 if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1267 (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1268 brcmf_err("Unsupported PCIE version %d\n", version);
1269 return -EINVAL;
1270 }
9e37f045
HM		 1271
1272 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1273 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1274 if (shared->max_rxbufpost == 0)
1275 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1276
1277 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1278 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1279
1280 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1281 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1282
1283 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1284 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1285
1286 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1287 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1288
1289 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1290 shared->max_rxbufpost, shared->rx_dataoffset);
1291
1292 brcmf_pcie_bus_console_init(devinfo);
1293
1294 return 0;
1295}
1296
1297
1298static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1299{
1300 char *fw_name;
1301 char *nvram_name;
1302 uint fw_len, nv_len;
1303 char end;
1304
1305 brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1306 devinfo->ci->chiprev);
1307
1308 switch (devinfo->ci->chip) {
1309 case BRCM_CC_43602_CHIP_ID:
1310 fw_name = BRCMF_PCIE_43602_FW_NAME;
1311 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1312 break;
9e37f045
HM		 1313 case BRCM_CC_4356_CHIP_ID:
1314 fw_name = BRCMF_PCIE_4356_FW_NAME;
1315 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1316 break;
1317 case BRCM_CC_43567_CHIP_ID:
1318 case BRCM_CC_43569_CHIP_ID:
1319 case BRCM_CC_43570_CHIP_ID:
1320 fw_name = BRCMF_PCIE_43570_FW_NAME;
1321 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1322 break;
67f3b6a3
AS		 1323 case BRCM_CC_4358_CHIP_ID:
1324 fw_name = BRCMF_PCIE_4358_FW_NAME;
1325 nvram_name = BRCMF_PCIE_4358_NVRAM_NAME;
1326 break;
9e37f045
HM		 1327 default:
1328 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1329 return -ENODEV;
1330 }
1331
1332 fw_len = sizeof(devinfo->fw_name) - 1;
1333 nv_len = sizeof(devinfo->nvram_name) - 1;
1334 /* check if firmware path is provided by module parameter */
1335 if (brcmf_firmware_path[0] != '\0') {
1336 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1337 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1338 fw_len -= strlen(devinfo->fw_name);
1339 nv_len -= strlen(devinfo->nvram_name);
1340
1341 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1342 if (end != '/') {
1343 strncat(devinfo->fw_name, "/", fw_len);
1344 strncat(devinfo->nvram_name, "/", nv_len);
1345 fw_len--;
1346 nv_len--;
1347 }
1348 }
1349 strncat(devinfo->fw_name, fw_name, fw_len);
1350 strncat(devinfo->nvram_name, nvram_name, nv_len);
1351
1352 return 0;
1353}
1354
1355
1356static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1357 const struct firmware *fw, void *nvram,
1358 u32 nvram_len)
1359{
1360 u32 sharedram_addr;
1361 u32 sharedram_addr_written;
1362 u32 loop_counter;
1363 int err;
1364 u32 address;
1365 u32 resetintr;
1366
1367 devinfo->ringbell = brcmf_pcie_ringbell_v2;
1368 devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1369
1370 brcmf_dbg(PCIE, "Halt ARM.\n");
1371 err = brcmf_pcie_enter_download_state(devinfo);
1372 if (err)
1373 return err;
1374
1375 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1376 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1377 (void *)fw->data, fw->size);
1378
1379 resetintr = get_unaligned_le32(fw->data);
1380 release_firmware(fw);
1381
1382 /* reset last 4 bytes of RAM address. to be used for shared
1383 * area. This identifies when FW is running
1384 */
1385 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1386
1387 if (nvram) {
1388 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1389 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1390 nvram_len;
1391 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1392 brcmf_fw_nvram_free(nvram);
1393 } else {
1394 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1395 devinfo->nvram_name);
1396 }
1397
1398 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1399 devinfo->ci->ramsize -
1400 4);
1401 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1402 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1403 if (err)
1404 return err;
1405
1406 brcmf_dbg(PCIE, "Wait for FW init\n");
1407 sharedram_addr = sharedram_addr_written;
1408 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1409 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1410 msleep(50);
1411 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1412 devinfo->ci->ramsize -
1413 4);
1414 loop_counter--;
1415 }
1416 if (sharedram_addr == sharedram_addr_written) {
1417 brcmf_err("FW failed to initialize\n");
1418 return -ENODEV;
1419 }
1420 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1421
1422 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1423}
1424
1425
1426static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1427{
1428 struct pci_dev *pdev;
1429 int err;
1430 phys_addr_t bar0_addr, bar1_addr;
1431 ulong bar1_size;
1432
1433 pdev = devinfo->pdev;
1434
1435 err = pci_enable_device(pdev);
1436 if (err) {
1437 brcmf_err("pci_enable_device failed err=%d\n", err);
1438 return err;
1439 }
1440
1441 pci_set_master(pdev);
1442
1443 /* Bar-0 mapped address */
1444 bar0_addr = pci_resource_start(pdev, 0);
1445 /* Bar-1 mapped address */
1446 bar1_addr = pci_resource_start(pdev, 2);
1447 /* read Bar-1 mapped memory range */
1448 bar1_size = pci_resource_len(pdev, 2);
1449 if ((bar1_size == 0) || (bar1_addr == 0)) {
1450 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1451 bar1_size, (unsigned long long)bar1_addr);
1452 return -EINVAL;
1453 }
1454
1455 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1456 devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1457 devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1458
1459 if (!devinfo->regs || !devinfo->tcm) {
1460 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1461 devinfo->tcm);
1462 return -EINVAL;
1463 }
1464 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1465 devinfo->regs, (unsigned long long)bar0_addr);
1466 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1467 devinfo->tcm, (unsigned long long)bar1_addr);
1468
1469 return 0;
1470}
1471
1472
1473static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1474{
1475 if (devinfo->tcm)
1476 iounmap(devinfo->tcm);
1477 if (devinfo->regs)
1478 iounmap(devinfo->regs);
1479
1480 pci_disable_device(devinfo->pdev);
1481}
1482
1483
1484static int brcmf_pcie_attach_bus(struct device *dev)
1485{
1486 int ret;
1487
1488 /* Attach to the common driver interface */
1489 ret = brcmf_attach(dev);
1490 if (ret) {
1491 brcmf_err("brcmf_attach failed\n");
1492 } else {
1493 ret = brcmf_bus_start(dev);
1494 if (ret)
1495 brcmf_err("dongle is not responding\n");
1496 }
1497
1498 return ret;
1499}
1500
1501
1502static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1503{
1504 u32 ret_addr;
1505
1506 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1507 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1508 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1509
1510 return ret_addr;
1511}
1512
1513
1514static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1515{
1516 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1517
1518 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1519 return brcmf_pcie_read_reg32(devinfo, addr);
1520}
1521
1522
1523static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1524{
1525 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1526
1527 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1528 brcmf_pcie_write_reg32(devinfo, addr, value);
1529}
1530
1531
1532static int brcmf_pcie_buscoreprep(void *ctx)
1533{
1534 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1535 int err;
1536
1537 err = brcmf_pcie_get_resource(devinfo);
1538 if (err == 0) {
1539 /* Set CC watchdog to reset all the cores on the chip to bring
1540 * back dongle to a sane state.
1541 */
1542 brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE,
1543 watchdog), 4);
1544 msleep(100);
1545 }
1546
1547 return err;
1548}
1549
1550
d380ebc9
AS		 1551static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1552 u32 rstvec)
9e37f045
HM		 1553{
1554 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1555
1556 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1557}
1558
1559
1560static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1561 .prepare = brcmf_pcie_buscoreprep,
d380ebc9 1562 .activate = brcmf_pcie_buscore_activate,
9e37f045
HM		 1563 .read32 = brcmf_pcie_buscore_read32,
1564 .write32 = brcmf_pcie_buscore_write32,
1565};
1566
1567static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1568 void *nvram, u32 nvram_len)
1569{
1570 struct brcmf_bus *bus = dev_get_drvdata(dev);
1571 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1572 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1573 struct brcmf_commonring **flowrings;
1574 int ret;
1575 u32 i;
1576
1577 brcmf_pcie_attach(devinfo);
1578
1579 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1580 if (ret)
1581 goto fail;
1582
1583 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1584
1585 ret = brcmf_pcie_init_ringbuffers(devinfo);
1586 if (ret)
1587 goto fail;
1588
1589 ret = brcmf_pcie_init_scratchbuffers(devinfo);
1590 if (ret)
1591 goto fail;
1592
1593 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1594 ret = brcmf_pcie_request_irq(devinfo);
1595 if (ret)
1596 goto fail;
1597
1598 /* hook the commonrings in the bus structure. */
1599 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1600 bus->msgbuf->commonrings[i] =
1601 &devinfo->shared.commonrings[i]->commonring;
1602
d5c5181c 1603 flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
9e37f045
HM		 1604 GFP_KERNEL);
1605 if (!flowrings)
1606 goto fail;
1607
1608 for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1609 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1610 bus->msgbuf->flowrings = flowrings;
1611
1612 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1613 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1614 bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1615
1616 init_waitqueue_head(&devinfo->mbdata_resp_wait);
1617
1618 brcmf_pcie_intr_enable(devinfo);
1619 if (brcmf_pcie_attach_bus(bus->dev) == 0)
1620 return;
1621
1622 brcmf_pcie_bus_console_read(devinfo);
1623
1624fail:
1625 device_release_driver(dev);
1626}
1627
1628static int
1629brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1630{
1631 int ret;
1632 struct brcmf_pciedev_info *devinfo;
1633 struct brcmf_pciedev *pcie_bus_dev;
1634 struct brcmf_bus *bus;
c4365534
HM		 1635 u16 domain_nr;
1636 u16 bus_nr;
9e37f045 1637
c4365534
HM		 1638 domain_nr = pci_domain_nr(pdev->bus) + 1;
1639 bus_nr = pdev->bus->number;
1640 brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1641 domain_nr, bus_nr);
9e37f045
HM		 1642
1643 ret = -ENOMEM;
1644 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1645 if (devinfo == NULL)
1646 return ret;
1647
1648 devinfo->pdev = pdev;
1649 pcie_bus_dev = NULL;
1650 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1651 if (IS_ERR(devinfo->ci)) {
1652 ret = PTR_ERR(devinfo->ci);
1653 devinfo->ci = NULL;
1654 goto fail;
1655 }
1656
1657 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1658 if (pcie_bus_dev == NULL) {
1659 ret = -ENOMEM;
1660 goto fail;
1661 }
1662
1663 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1664 if (!bus) {
1665 ret = -ENOMEM;
1666 goto fail;
1667 }
1668 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1669 if (!bus->msgbuf) {
1670 ret = -ENOMEM;
1671 kfree(bus);
1672 goto fail;
1673 }
1674
1675 /* hook it all together. */
1676 pcie_bus_dev->devinfo = devinfo;
1677 pcie_bus_dev->bus = bus;
1678 bus->dev = &pdev->dev;
1679 bus->bus_priv.pcie = pcie_bus_dev;
1680 bus->ops = &brcmf_pcie_bus_ops;
1681 bus->proto_type = BRCMF_PROTO_MSGBUF;
1682 bus->chip = devinfo->coreid;
4eb3af7c 1683 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
9e37f045
HM		 1684 dev_set_drvdata(&pdev->dev, bus);
1685
1686 ret = brcmf_pcie_get_fwnames(devinfo);
1687 if (ret)
1688 goto fail_bus;
1689
c4365534
HM		 1690 ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1691 BRCMF_FW_REQ_NV_OPTIONAL,
1692 devinfo->fw_name, devinfo->nvram_name,
1693 brcmf_pcie_setup, domain_nr, bus_nr);
9e37f045
HM		 1694 if (ret == 0)
1695 return 0;
1696fail_bus:
1697 kfree(bus->msgbuf);
1698 kfree(bus);
1699fail:
1700 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1701 brcmf_pcie_release_resource(devinfo);
1702 if (devinfo->ci)
1703 brcmf_chip_detach(devinfo->ci);
1704 kfree(pcie_bus_dev);
1705 kfree(devinfo);
1706 return ret;
1707}
1708
1709
1710static void
1711brcmf_pcie_remove(struct pci_dev *pdev)
1712{
1713 struct brcmf_pciedev_info *devinfo;
1714 struct brcmf_bus *bus;
1715
1716 brcmf_dbg(PCIE, "Enter\n");
1717
1718 bus = dev_get_drvdata(&pdev->dev);
1719 if (bus == NULL)
1720 return;
1721
1722 devinfo = bus->bus_priv.pcie->devinfo;
1723
1724 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1725 if (devinfo->ci)
1726 brcmf_pcie_intr_disable(devinfo);
1727
1728 brcmf_detach(&pdev->dev);
1729
1730 kfree(bus->bus_priv.pcie);
1731 kfree(bus->msgbuf->flowrings);
1732 kfree(bus->msgbuf);
1733 kfree(bus);
1734
1735 brcmf_pcie_release_irq(devinfo);
1736 brcmf_pcie_release_scratchbuffers(devinfo);
1737 brcmf_pcie_release_ringbuffers(devinfo);
bd4f82e3 1738 brcmf_pcie_reset_device(devinfo);
9e37f045
HM		 1739 brcmf_pcie_release_resource(devinfo);
1740
1741 if (devinfo->ci)
1742 brcmf_chip_detach(devinfo->ci);
1743
1744 kfree(devinfo);
1745 dev_set_drvdata(&pdev->dev, NULL);
1746}
1747
1748
1749#ifdef CONFIG_PM
1750
1751
1752static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1753{
1754 struct brcmf_pciedev_info *devinfo;
1755 struct brcmf_bus *bus;
1756 int err;
1757
1758 brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1759
1760 bus = dev_get_drvdata(&pdev->dev);
1761 devinfo = bus->bus_priv.pcie->devinfo;
1762
1763 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1764
1765 devinfo->mbdata_completed = false;
1766 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1767
1768 wait_event_timeout(devinfo->mbdata_resp_wait,
1769 devinfo->mbdata_completed,
1770 msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1771 if (!devinfo->mbdata_completed) {
1772 brcmf_err("Timeout on response for entering D3 substate\n");
1773 return -EIO;
1774 }
4eb3af7c 1775 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
9e37f045
HM		 1776
1777 err = pci_save_state(pdev);
4eb3af7c 1778 if (err)
9e37f045 1779 brcmf_err("pci_save_state failed, err=%d\n", err);
4eb3af7c
HM		 1780 if ((err) || (!devinfo->wowl_enabled)) {
1781 brcmf_chip_detach(devinfo->ci);
1782 devinfo->ci = NULL;
1783 brcmf_pcie_remove(pdev);
1784 return 0;
9e37f045
HM		 1785 }
1786
9e37f045
HM		 1787 return pci_prepare_to_sleep(pdev);
1788}
1789
9e37f045
HM		 1790static int brcmf_pcie_resume(struct pci_dev *pdev)
1791{
4eb3af7c
HM		 1792 struct brcmf_pciedev_info *devinfo;
1793 struct brcmf_bus *bus;
9e37f045
HM		 1794 int err;
1795
4eb3af7c
HM		 1796 bus = dev_get_drvdata(&pdev->dev);
1797 brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
9e37f045
HM		 1798
1799 err = pci_set_power_state(pdev, PCI_D0);
1800 if (err) {
1801 brcmf_err("pci_set_power_state failed, err=%d\n", err);
4eb3af7c 1802 goto cleanup;
9e37f045
HM		 1803 }
1804 pci_restore_state(pdev);
4eb3af7c
HM		 1805 pci_enable_wake(pdev, PCI_D3hot, false);
1806 pci_enable_wake(pdev, PCI_D3cold, false);
1807
1808 /* Check if device is still up and running, if so we are ready */
1809 if (bus) {
1810 devinfo = bus->bus_priv.pcie->devinfo;
1811 if (brcmf_pcie_read_reg32(devinfo,
1812 BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1813 if (brcmf_pcie_send_mb_data(devinfo,
1814 BRCMF_H2D_HOST_D0_INFORM))
1815 goto cleanup;
1816 brcmf_dbg(PCIE, "Hot resume, continue....\n");
1817 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
a1cee865 1818 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
4eb3af7c
HM		 1819 brcmf_pcie_intr_enable(devinfo);
1820 return 0;
1821 }
1822 }
9e37f045 1823
4eb3af7c
HM		 1824cleanup:
1825 if (bus) {
1826 devinfo = bus->bus_priv.pcie->devinfo;
1827 brcmf_chip_detach(devinfo->ci);
1828 devinfo->ci = NULL;
1829 brcmf_pcie_remove(pdev);
1830 }
9e37f045
HM		 1831 err = brcmf_pcie_probe(pdev, NULL);
1832 if (err)
1833 brcmf_err("probe after resume failed, err=%d\n", err);
1834
1835 return err;
1836}
1837
1838
1839#endif /* CONFIG_PM */
1840
1841
1842#define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1843 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1844
1845static struct pci_device_id brcmf_pcie_devid_table[] = {
9e37f045
HM		 1846 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1847 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1848 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
67f3b6a3 1849 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
9e37f045 1850 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
48fd818f
HM		 1851 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1852 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
27aace2d 1853 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
9e37f045
HM		 1854 { /* end: all zeroes */ }
1855};
1856
1857
1858MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1859
1860
1861static struct pci_driver brcmf_pciedrvr = {
1862 .node = {},
1863 .name = KBUILD_MODNAME,
1864 .id_table = brcmf_pcie_devid_table,
1865 .probe = brcmf_pcie_probe,
1866 .remove = brcmf_pcie_remove,
1867#ifdef CONFIG_PM
1868 .suspend = brcmf_pcie_suspend,
1869 .resume = brcmf_pcie_resume
1870#endif /* CONFIG_PM */
1871};
1872
1873
1874void brcmf_pcie_register(void)
1875{
1876 int err;
1877
1878 brcmf_dbg(PCIE, "Enter\n");
1879 err = pci_register_driver(&brcmf_pciedrvr);
1880 if (err)
1881 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1882}
1883
1884
1885void brcmf_pcie_exit(void)
1886{
1887 brcmf_dbg(PCIE, "Enter\n");
1888 pci_unregister_driver(&brcmf_pciedrvr);
1889}
Linux kernel - Deliverables
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