[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / sdio.h

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	BRCMFMAC_SDIO_H
#define	BRCMFMAC_SDIO_H

#include <linux/skbuff.h>
#include <linux/firmware.h>
#include "firmware.h"

#define SDIO_FUNC_0		0
#define SDIO_FUNC_1		1
#define SDIO_FUNC_2		2

#define SDIOD_FBR_SIZE		0x100

/* io_en */
#define SDIO_FUNC_ENABLE_1	0x02
#define SDIO_FUNC_ENABLE_2	0x04

/* io_rdys */
#define SDIO_FUNC_READY_1	0x02
#define SDIO_FUNC_READY_2	0x04

/* intr_status */
#define INTR_STATUS_FUNC1	0x2
#define INTR_STATUS_FUNC2	0x4

/* Maximum number of I/O funcs */
#define SDIOD_MAX_IOFUNCS	7

/* mask of register map */
#define REG_F0_REG_MASK		0x7FF
#define REG_F1_MISC_MASK	0x1FFFF

/* as of sdiod rev 0, supports 3 functions */
#define SBSDIO_NUM_FUNCTION		3

/* function 0 vendor specific CCCR registers */
#define SDIO_CCCR_BRCM_CARDCAP			0xf0
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT	0x02
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT	0x04
#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC	0x08
#define SDIO_CCCR_BRCM_CARDCTRL		0xf1
#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET	0x02
#define SDIO_CCCR_BRCM_SEPINT			0xf2

#define  SDIO_SEPINT_MASK		0x01
#define  SDIO_SEPINT_OE			0x02
#define  SDIO_SEPINT_ACT_HI		0x04

/* function 1 miscellaneous registers */

/* sprom command and status */
#define SBSDIO_SPROM_CS			0x10000
/* sprom info register */
#define SBSDIO_SPROM_INFO		0x10001
/* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_LOW		0x10002
/* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_DATA_HIGH		0x10003
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_LOW		0x10004
/* gpio select */
#define SBSDIO_GPIO_SELECT		0x10005
/* gpio output */
#define SBSDIO_GPIO_OUT			0x10006
/* gpio enable */
#define SBSDIO_GPIO_EN			0x10007
/* rev < 7, watermark for sdio device */
#define SBSDIO_WATERMARK		0x10008
/* control busy signal generation */
#define SBSDIO_DEVICE_CTL		0x10009

/* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRLOW		0x1000A
/* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRMID		0x1000B
/* SB Address Window High (b31:b24)    */
#define SBSDIO_FUNC1_SBADDRHIGH		0x1000C
/* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_FRAMECTRL		0x1000D
/* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_CHIPCLKCSR		0x1000E
/* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_SDIOPULLUP		0x1000F
/* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCLO		0x10019
/* Write Frame Byte Count High */
#define SBSDIO_FUNC1_WFRAMEBCHI		0x1001A
/* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCLO		0x1001B
/* Read Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCHI		0x1001C
/* MesBusyCtl (rev 11) */
#define SBSDIO_FUNC1_MESBUSYCTRL	0x1001D
/* Sdio Core Rev 12 */
#define SBSDIO_FUNC1_WAKEUPCTRL		0x1001E
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK		0x1
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT	0
#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK		0x2
#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT		1
#define SBSDIO_FUNC1_SLEEPCSR		0x1001F
#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK		0x1
#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT		0
#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN		1
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK	0x2
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT	1

#define SBSDIO_FUNC1_MISC_REG_START	0x10000	/* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT	0x1001F	/* f1 misc register end */

/* function 1 OCP space */

/* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_MASK		0x07FFF
#define SBSDIO_SB_OFT_ADDR_LIMIT	0x08000
/* with b15, maps to 32-bit SB access */
#define SBSDIO_SB_ACCESS_2_4B_FLAG	0x08000

/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */

#define SBSDIO_SBADDRLOW_MASK		0x80	/* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK		0xff	/* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK		0xffU	/* Valid bits in SBADDRHIGH */
/* Address bits from SBADDR regs */
#define SBSDIO_SBWINDOW_MASK		0xffff8000

#define SDIOH_READ              0	/* Read request */
#define SDIOH_WRITE             1	/* Write request */

#define SDIOH_DATA_FIX          0	/* Fixed addressing */
#define SDIOH_DATA_INC          1	/* Incremental addressing */

/* internal return code */
#define SUCCESS	0
#define ERROR	1

/* Packet alignment for most efficient SDIO (can change based on platform) */
#define BRCMF_SDALIGN	(1 << 6)

/* watchdog polling interval in ms */
#define BRCMF_WD_POLL_MS	10

/* The state of the bus */
enum brcmf_sdio_state {
	BRCMF_STATE_DOWN,	/* Device available, still initialising */
	BRCMF_STATE_DATA,	/* Ready for data transfers, DPC enabled */
	BRCMF_STATE_NOMEDIUM	/* No medium access to dongle possible */
};

struct brcmf_sdreg {
	int func;
	int offset;
	int value;
};

struct brcmf_sdio;

struct brcmf_sdio_dev {
	struct sdio_func *func[SDIO_MAX_FUNCS];
	u8 num_funcs;			/* Supported funcs on client */
	u32 sbwad;			/* Save backplane window address */
	struct brcmf_sdio *bus;
	atomic_t suspend;		/* suspend flag */
	bool sleeping;
	wait_queue_head_t idle_wait;
	struct device *dev;
	struct brcmf_bus *bus_if;
	struct brcmfmac_sdio_platform_data *pdata;
	bool oob_irq_requested;
	bool irq_en;			/* irq enable flags */
	spinlock_t irq_en_lock;
	bool irq_wake;			/* irq wake enable flags */
	bool sg_support;
	uint max_request_size;
	ushort max_segment_count;
	uint max_segment_size;
	uint txglomsz;
	struct sg_table sgtable;
	char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
	char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
	bool wowl_enabled;
	enum brcmf_sdio_state state;
};

/* sdio core registers */
struct sdpcmd_regs {
	u32 corecontrol;		/* 0x00, rev8 */
	u32 corestatus;			/* rev8 */
	u32 PAD[1];
	u32 biststatus;			/* rev8 */

	/* PCMCIA access */
	u16 pcmciamesportaladdr;	/* 0x010, rev8 */
	u16 PAD[1];
	u16 pcmciamesportalmask;	/* rev8 */
	u16 PAD[1];
	u16 pcmciawrframebc;		/* rev8 */
	u16 PAD[1];
	u16 pcmciaunderflowtimer;	/* rev8 */
	u16 PAD[1];

	/* interrupt */
	u32 intstatus;			/* 0x020, rev8 */
	u32 hostintmask;		/* rev8 */
	u32 intmask;			/* rev8 */
	u32 sbintstatus;		/* rev8 */
	u32 sbintmask;			/* rev8 */
	u32 funcintmask;		/* rev4 */
	u32 PAD[2];
	u32 tosbmailbox;		/* 0x040, rev8 */
	u32 tohostmailbox;		/* rev8 */
	u32 tosbmailboxdata;		/* rev8 */
	u32 tohostmailboxdata;		/* rev8 */

	/* synchronized access to registers in SDIO clock domain */
	u32 sdioaccess;			/* 0x050, rev8 */
	u32 PAD[3];

	/* PCMCIA frame control */
	u8 pcmciaframectrl;		/* 0x060, rev8 */
	u8 PAD[3];
	u8 pcmciawatermark;		/* rev8 */
	u8 PAD[155];

	/* interrupt batching control */
	u32 intrcvlazy;			/* 0x100, rev8 */
	u32 PAD[3];

	/* counters */
	u32 cmd52rd;			/* 0x110, rev8 */
	u32 cmd52wr;			/* rev8 */
	u32 cmd53rd;			/* rev8 */
	u32 cmd53wr;			/* rev8 */
	u32 abort;			/* rev8 */
	u32 datacrcerror;		/* rev8 */
	u32 rdoutofsync;		/* rev8 */
	u32 wroutofsync;		/* rev8 */
	u32 writebusy;			/* rev8 */
	u32 readwait;			/* rev8 */
	u32 readterm;			/* rev8 */
	u32 writeterm;			/* rev8 */
	u32 PAD[40];
	u32 clockctlstatus;		/* rev8 */
	u32 PAD[7];

	u32 PAD[128];			/* DMA engines */

	/* SDIO/PCMCIA CIS region */
	char cis[512];			/* 0x400-0x5ff, rev6 */

	/* PCMCIA function control registers */
	char pcmciafcr[256];		/* 0x600-6ff, rev6 */
	u16 PAD[55];

	/* PCMCIA backplane access */
	u16 backplanecsr;		/* 0x76E, rev6 */
	u16 backplaneaddr0;		/* rev6 */
	u16 backplaneaddr1;		/* rev6 */
	u16 backplaneaddr2;		/* rev6 */
	u16 backplaneaddr3;		/* rev6 */
	u16 backplanedata0;		/* rev6 */
	u16 backplanedata1;		/* rev6 */
	u16 backplanedata2;		/* rev6 */
	u16 backplanedata3;		/* rev6 */
	u16 PAD[31];

	/* sprom "size" & "blank" info */
	u16 spromstatus;		/* 0x7BE, rev2 */
	u32 PAD[464];

	u16 PAD[0x80];
};

/* Register/deregister interrupt handler. */
int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);

/* sdio device register access interface */
u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
		       int *ret);
void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
		       int *ret);

/* Buffer transfer to/from device (client) core via cmd53.
 *   fn:       function number
 *   flags:    backplane width, address increment, sync/async
 *   buf:      pointer to memory data buffer
 *   nbytes:   number of bytes to transfer to/from buf
 *   pkt:      pointer to packet associated with buf (if any)
 *   complete: callback function for command completion (async only)
 *   handle:   handle for completion callback (first arg in callback)
 * Returns 0 or error code.
 * NOTE: Async operation is not currently supported.
 */
int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
			 struct sk_buff_head *pktq);
int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);

int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
			   struct sk_buff_head *pktq, uint totlen);

/* Flags bits */

/* Four-byte target (backplane) width (vs. two-byte) */
#define SDIO_REQ_4BYTE	0x1
/* Fixed address (FIFO) (vs. incrementing address) */
#define SDIO_REQ_FIXED	0x2

/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
 *   rw:       read or write (0/1)
 *   addr:     direct SDIO address
 *   buf:      pointer to memory data buffer
 *   nbytes:   number of bytes to transfer to/from buf
 * Returns 0 or error code.
 */
int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
		      u8 *data, uint size);

/* Issue an abort to the specified function */
int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn);

struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
void brcmf_sdio_remove(struct brcmf_sdio *bus);
void brcmf_sdio_isr(struct brcmf_sdio *bus);

void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick);
void brcmf_sdio_wowl_config(struct device *dev, bool enabled);

#endif /* BRCMFMAC_SDIO_H */
Commit	Line	Data
5b435de0 AS	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
888bf76e HM	17	#ifndef BRCMFMAC_SDIO_H
888bf76e HM	18	#define BRCMFMAC_SDIO_H
5b435de0 AS	19
5b435de0 AS	20	#include <linux/skbuff.h>
c1b20532 DK	21	#include <linux/firmware.h>
c1b20532 DK	22	#include "firmware.h"
5b435de0 AS	23
	24	#define SDIO_FUNC_0 0
	25	#define SDIO_FUNC_1 1
	26	#define SDIO_FUNC_2 2
	27
	28	#define SDIOD_FBR_SIZE 0x100
	29
	30	/* io_en */
	31	#define SDIO_FUNC_ENABLE_1 0x02
	32	#define SDIO_FUNC_ENABLE_2 0x04
	33
	34	/* io_rdys */
	35	#define SDIO_FUNC_READY_1 0x02
	36	#define SDIO_FUNC_READY_2 0x04
	37
	38	/* intr_status */
	39	#define INTR_STATUS_FUNC1 0x2
	40	#define INTR_STATUS_FUNC2 0x4
	41
	42	/* Maximum number of I/O funcs */
	43	#define SDIOD_MAX_IOFUNCS 7
	44
e9b8d91d	45	/* mask of register map */
d8b3fc59	46	#define REG_F0_REG_MASK 0x7FF
e9b8d91d FL	47	#define REG_F1_MISC_MASK 0x1FFFF
e9b8d91d FL	48
5b435de0 AS	49	/* as of sdiod rev 0, supports 3 functions */
	50	#define SBSDIO_NUM_FUNCTION 3
	51
ba89bf19	52	/* function 0 vendor specific CCCR registers */
4a3da990 PH	53	#define SDIO_CCCR_BRCM_CARDCAP 0xf0
	54	#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
	55	#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
	56	#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
1e9ab4dd PH	57	#define SDIO_CCCR_BRCM_CARDCTRL 0xf1
1e9ab4dd PH	58	#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
4a3da990	59	#define SDIO_CCCR_BRCM_SEPINT 0xf2
ba89bf19 FL	60
	61	#define SDIO_SEPINT_MASK 0x01
	62	#define SDIO_SEPINT_OE 0x02
	63	#define SDIO_SEPINT_ACT_HI 0x04
	64
5b435de0 AS	65	/* function 1 miscellaneous registers */
	66
	67	/* sprom command and status */
	68	#define SBSDIO_SPROM_CS 0x10000
	69	/* sprom info register */
	70	#define SBSDIO_SPROM_INFO 0x10001
	71	/* sprom indirect access data byte 0 */
	72	#define SBSDIO_SPROM_DATA_LOW 0x10002
	73	/* sprom indirect access data byte 1 */
	74	#define SBSDIO_SPROM_DATA_HIGH 0x10003
	75	/* sprom indirect access addr byte 0 */
	76	#define SBSDIO_SPROM_ADDR_LOW 0x10004
3cdf0a81 HG	77	/* gpio select */
	78	#define SBSDIO_GPIO_SELECT 0x10005
	79	/* gpio output */
	80	#define SBSDIO_GPIO_OUT 0x10006
	81	/* gpio enable */
	82	#define SBSDIO_GPIO_EN 0x10007
5b435de0 AS	83	/* rev < 7, watermark for sdio device */
	84	#define SBSDIO_WATERMARK 0x10008
	85	/* control busy signal generation */
	86	#define SBSDIO_DEVICE_CTL 0x10009
	87
	88	/* SB Address Window Low (b15) */
	89	#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
	90	/* SB Address Window Mid (b23:b16) */
	91	#define SBSDIO_FUNC1_SBADDRMID 0x1000B
	92	/* SB Address Window High (b31:b24) */
	93	#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
	94	/* Frame Control (frame term/abort) */
	95	#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
	96	/* ChipClockCSR (ALP/HT ctl/status) */
	97	#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
	98	/* SdioPullUp (on cmd, d0-d2) */
	99	#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
	100	/* Write Frame Byte Count Low */
	101	#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
	102	/* Write Frame Byte Count High */
	103	#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
	104	/* Read Frame Byte Count Low */
	105	#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
	106	/* Read Frame Byte Count High */
	107	#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
4a3da990 PH	108	/* MesBusyCtl (rev 11) */
	109	#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
	110	/* Sdio Core Rev 12 */
	111	#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
	112	#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
	113	#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
	114	#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
	115	#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
	116	#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
	117	#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
	118	#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
	119	#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
	120	#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
	121	#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
5b435de0 AS	122
5b435de0 AS	123	#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
4a3da990	124	#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
5b435de0 AS	125
	126	/* function 1 OCP space */
	127
	128	/* sb offset addr is <= 15 bits, 32k */
	129	#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
	130	#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
	131	/* with b15, maps to 32-bit SB access */
	132	#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
	133
	134	/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
	135
	136	#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
	137	#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
	138	#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
	139	/* Address bits from SBADDR regs */
	140	#define SBSDIO_SBWINDOW_MASK 0xffff8000
	141
	142	#define SDIOH_READ 0 /* Read request */
	143	#define SDIOH_WRITE 1 /* Write request */
	144
	145	#define SDIOH_DATA_FIX 0 /* Fixed addressing */
	146	#define SDIOH_DATA_INC 1 /* Incremental addressing */
	147
	148	/* internal return code */
	149	#define SUCCESS 0
	150	#define ERROR 1
	151
6e3c7128 FL	152	/* Packet alignment for most efficient SDIO (can change based on platform) */
	153	#define BRCMF_SDALIGN (1 << 6)
	154
	155	/* watchdog polling interval in ms */
	156	#define BRCMF_WD_POLL_MS 10
	157
a1cee865 HM	158	/* The state of the bus */
	159	enum brcmf_sdio_state {
	160	BRCMF_STATE_DOWN, /* Device available, still initialising */
	161	BRCMF_STATE_DATA, /* Ready for data transfers, DPC enabled */
	162	BRCMF_STATE_NOMEDIUM /* No medium access to dongle possible */
	163	};
	164
5b435de0 AS	165	struct brcmf_sdreg {
	166	int func;
	167	int offset;
	168	int value;
	169	};
	170
2447ffb0 FL	171	struct brcmf_sdio;
2447ffb0 FL	172
5b435de0 AS	173	struct brcmf_sdio_dev {
	174	struct sdio_func *func[SDIO_MAX_FUNCS];
	175	u8 num_funcs; /* Supported funcs on client */
5b435de0	176	u32 sbwad; /* Save backplane window address */
964ec1cf	177	struct brcmf_sdio *bus;
5b435de0	178	atomic_t suspend; /* suspend flag */
8982cd40 AS	179	bool sleeping;
8982cd40 AS	180	wait_queue_head_t idle_wait;
655713be	181	struct device *dev;
d76d1c8c	182	struct brcmf_bus *bus_if;
668761ac HM	183	struct brcmfmac_sdio_platform_data *pdata;
668761ac HM	184	bool oob_irq_requested;
ba89bf19 FL	185	bool irq_en; /* irq enable flags */
	186	spinlock_t irq_en_lock;
	187	bool irq_wake; /* irq wake enable flags */
71201496 AS	188	bool sg_support;
	189	uint max_request_size;
	190	ushort max_segment_count;
	191	uint max_segment_size;
af1fa210 AS	192	uint txglomsz;
af1fa210 AS	193	struct sg_table sgtable;
c1b20532 DK	194	char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
c1b20532 DK	195	char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
330b4e4b	196	bool wowl_enabled;
a1cee865	197	enum brcmf_sdio_state state;
5b435de0 AS	198	};
5b435de0 AS	199
cb7cf7be AS	200	/* sdio core registers */
	201	struct sdpcmd_regs {
	202	u32 corecontrol; /* 0x00, rev8 */
	203	u32 corestatus; /* rev8 */
	204	u32 PAD[1];
	205	u32 biststatus; /* rev8 */
	206
	207	/* PCMCIA access */
	208	u16 pcmciamesportaladdr; /* 0x010, rev8 */
	209	u16 PAD[1];
	210	u16 pcmciamesportalmask; /* rev8 */
	211	u16 PAD[1];
	212	u16 pcmciawrframebc; /* rev8 */
	213	u16 PAD[1];
	214	u16 pcmciaunderflowtimer; /* rev8 */
	215	u16 PAD[1];
	216
	217	/* interrupt */
	218	u32 intstatus; /* 0x020, rev8 */
	219	u32 hostintmask; /* rev8 */
	220	u32 intmask; /* rev8 */
	221	u32 sbintstatus; /* rev8 */
	222	u32 sbintmask; /* rev8 */
	223	u32 funcintmask; /* rev4 */
	224	u32 PAD[2];
	225	u32 tosbmailbox; /* 0x040, rev8 */
	226	u32 tohostmailbox; /* rev8 */
	227	u32 tosbmailboxdata; /* rev8 */
	228	u32 tohostmailboxdata; /* rev8 */
	229
	230	/* synchronized access to registers in SDIO clock domain */
	231	u32 sdioaccess; /* 0x050, rev8 */
	232	u32 PAD[3];
	233
	234	/* PCMCIA frame control */
	235	u8 pcmciaframectrl; /* 0x060, rev8 */
	236	u8 PAD[3];
	237	u8 pcmciawatermark; /* rev8 */
	238	u8 PAD[155];
	239
	240	/* interrupt batching control */
	241	u32 intrcvlazy; /* 0x100, rev8 */
	242	u32 PAD[3];
	243
	244	/* counters */
	245	u32 cmd52rd; /* 0x110, rev8 */
	246	u32 cmd52wr; /* rev8 */
	247	u32 cmd53rd; /* rev8 */
	248	u32 cmd53wr; /* rev8 */
	249	u32 abort; /* rev8 */
	250	u32 datacrcerror; /* rev8 */
	251	u32 rdoutofsync; /* rev8 */
	252	u32 wroutofsync; /* rev8 */
	253	u32 writebusy; /* rev8 */
	254	u32 readwait; /* rev8 */
	255	u32 readterm; /* rev8 */
	256	u32 writeterm; /* rev8 */
	257	u32 PAD[40];
	258	u32 clockctlstatus; /* rev8 */
	259	u32 PAD[7];
	260
	261	u32 PAD[128]; /* DMA engines */
	262
	263	/* SDIO/PCMCIA CIS region */
264	char cis[512]; /* 0x400-0x5ff, rev6 */
265
266	/* PCMCIA function control registers */
267	char pcmciafcr[256]; /* 0x600-6ff, rev6 */
268	u16 PAD[55];
269
270	/* PCMCIA backplane access */
271	u16 backplanecsr; /* 0x76E, rev6 */
272	u16 backplaneaddr0; /* rev6 */
273	u16 backplaneaddr1; /* rev6 */
274	u16 backplaneaddr2; /* rev6 */
275	u16 backplaneaddr3; /* rev6 */
276	u16 backplanedata0; /* rev6 */
277	u16 backplanedata1; /* rev6 */
278	u16 backplanedata2; /* rev6 */
279	u16 backplanedata3; /* rev6 */
280	u16 PAD[31];
281
282	/* sprom "size" & "blank" info */
283	u16 spromstatus; /* 0x7BE, rev2 */
284	u32 PAD[464];
285
286	u16 PAD[0x80];
287	};
288
ba89bf19	289	/* Register/deregister interrupt handler. */
a39be27b AS	290	int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
a39be27b AS	291	int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
5b435de0	292
e9b8d91d	293	/* sdio device register access interface */
a39be27b AS	294	u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev sdiodev, u32 addr, int ret);
	295	u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev sdiodev, u32 addr, int ret);
	296	void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
	297	int *ret);
	298	void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
	299	int *ret);
e9b8d91d	300
5b435de0 AS	301	/* Buffer transfer to/from device (client) core via cmd53.
5b435de0 AS	302	* fn: function number
5b435de0 AS	303	* flags: backplane width, address increment, sync/async
	304	* buf: pointer to memory data buffer
	305	* nbytes: number of bytes to transfer to/from buf
	306	* pkt: pointer to packet associated with buf (if any)
	307	* complete: callback function for command completion (async only)
	308	* handle: handle for completion callback (first arg in callback)
	309	* Returns 0 or error code.
	310	* NOTE: Async operation is not currently supported.
	311	*/
a7cdd821 AS	312	int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
	313	struct sk_buff_head *pktq);
	314	int brcmf_sdiod_send_buf(struct brcmf_sdio_dev sdiodev, u8 buf, uint nbytes);
	315
	316	int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev sdiodev, struct sk_buff pkt);
	317	int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev sdiodev, u8 buf, uint nbytes);
	318	int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
	319	struct sk_buff_head *pktq, uint totlen);
5b435de0 AS	320
	321	/* Flags bits */
	322
	323	/* Four-byte target (backplane) width (vs. two-byte) */
	324	#define SDIO_REQ_4BYTE 0x1
	325	/* Fixed address (FIFO) (vs. incrementing address) */
	326	#define SDIO_REQ_FIXED 0x2
5b435de0 AS	327
	328	/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
	329	* rw: read or write (0/1)
	330	* addr: direct SDIO address
	331	* buf: pointer to memory data buffer
	332	* nbytes: number of bytes to transfer to/from buf
	333	* Returns 0 or error code.
	334	*/
a39be27b AS	335	int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
a39be27b AS	336	u8 *data, uint size);
5b435de0 AS	337
5b435de0 AS	338	/* Issue an abort to the specified function */
a39be27b	339	int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
5b435de0	340
82d7f3c1	341	struct brcmf_sdio brcmf_sdio_probe(struct brcmf_sdio_dev sdiodev);
9fbe2a6d	342	void brcmf_sdio_remove(struct brcmf_sdio *bus);
82d7f3c1 AS	343	void brcmf_sdio_isr(struct brcmf_sdio *bus);
	344
	345	void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick);
330b4e4b	346	void brcmf_sdio_wowl_config(struct device *dev, bool enabled);
78b3f1c5	347
888bf76e	348	#endif /* BRCMFMAC_SDIO_H */