[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmfmac / sdio_chip.c

/*
 * Copyright (c) 2011 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
/* ***** SDIO interface chip backplane handle functions ***** */

#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/mmc/card.h>
#include <chipcommon.h>
#include <brcm_hw_ids.h>
#include <brcmu_wifi.h>
#include <brcmu_utils.h>
#include <soc.h>
#include "dhd.h"
#include "dhd_dbg.h"
#include "sdio_host.h"
#include "sdio_chip.h"

/* chip core base & ramsize */
/* bcm4329 */
/* SDIO device core, ID 0x829 */
#define BCM4329_CORE_BUS_BASE		0x18011000
/* internal memory core, ID 0x80e */
#define BCM4329_CORE_SOCRAM_BASE	0x18003000
/* ARM Cortex M3 core, ID 0x82a */
#define BCM4329_CORE_ARM_BASE		0x18002000
#define BCM4329_RAMSIZE			0x48000


/* SB regs */
/* sbidhigh */
#define	SBIDH_RC_MASK		0x000f	/* revision code */
#define	SBIDH_RCE_MASK		0x7000	/* revision code extension field */
#define	SBIDH_RCE_SHIFT		8
#define	SBCOREREV(sbidh) \
	((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
	  ((sbidh) & SBIDH_RC_MASK))
#define	SBIDH_CC_MASK		0x8ff0	/* core code */
#define	SBIDH_CC_SHIFT		4
#define	SBIDH_VC_MASK		0xffff0000	/* vendor code */
#define	SBIDH_VC_SHIFT		16

static u32
brcmf_sdio_chip_corerev(struct brcmf_sdio_dev *sdiodev,
			u32 corebase)
{
	u32 regdata;

	regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbidhigh), 4);
	return SBCOREREV(regdata);
}

bool
brcmf_sdio_chip_iscoreup(struct brcmf_sdio_dev *sdiodev,
			 u32 corebase)
{
	u32 regdata;

	regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbtmstatelow), 4);
	regdata &= (SBTML_RESET | SBTML_REJ_MASK |
			(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
	return ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) == regdata);
}

void
brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
{
	u32 regdata;

	regdata = brcmf_sdcard_reg_read(sdiodev,
		CORE_SB(corebase, sbtmstatelow), 4);
	if (regdata & SBTML_RESET)
		return;

	regdata = brcmf_sdcard_reg_read(sdiodev,
		CORE_SB(corebase, sbtmstatelow), 4);
	if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
		/*
		 * set target reject and spin until busy is clear
		 * (preserve core-specific bits)
		 */
		regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbtmstatelow), 4);
		brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
				       4, regdata | SBTML_REJ);

		regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbtmstatelow), 4);
		udelay(1);
		SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbtmstatehigh), 4) &
			SBTMH_BUSY), 100000);

		regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbtmstatehigh), 4);
		if (regdata & SBTMH_BUSY)
			brcmf_dbg(ERROR, "core state still busy\n");

		regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbidlow), 4);
		if (regdata & SBIDL_INIT) {
			regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(corebase, sbimstate), 4) |
				SBIM_RJ;
			brcmf_sdcard_reg_write(sdiodev,
				CORE_SB(corebase, sbimstate), 4,
				regdata);
			regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(corebase, sbimstate), 4);
			udelay(1);
			SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(corebase, sbimstate), 4) &
				SBIM_BY), 100000);
		}

		/* set reset and reject while enabling the clocks */
		brcmf_sdcard_reg_write(sdiodev,
			CORE_SB(corebase, sbtmstatelow), 4,
			(((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
			SBTML_REJ | SBTML_RESET));
		regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbtmstatelow), 4);
		udelay(10);

		/* clear the initiator reject bit */
		regdata = brcmf_sdcard_reg_read(sdiodev,
			CORE_SB(corebase, sbidlow), 4);
		if (regdata & SBIDL_INIT) {
			regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_SB(corebase, sbimstate), 4) &
				~SBIM_RJ;
			brcmf_sdcard_reg_write(sdiodev,
				CORE_SB(corebase, sbimstate), 4,
				regdata);
		}
	}

	/* leave reset and reject asserted */
	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
		(SBTML_REJ | SBTML_RESET));
	udelay(1);
}

void
brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
{
	u32 regdata;

	/*
	 * Must do the disable sequence first to work for
	 * arbitrary current core state.
	 */
	brcmf_sdio_chip_coredisable(sdiodev, corebase);

	/*
	 * Now do the initialization sequence.
	 * set reset while enabling the clock and
	 * forcing them on throughout the core
	 */
	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
		((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
		SBTML_RESET);
	udelay(1);

	regdata = brcmf_sdcard_reg_read(sdiodev,
					CORE_SB(corebase, sbtmstatehigh), 4);
	if (regdata & SBTMH_SERR)
		brcmf_sdcard_reg_write(sdiodev,
				       CORE_SB(corebase, sbtmstatehigh), 4, 0);

	regdata = brcmf_sdcard_reg_read(sdiodev,
					CORE_SB(corebase, sbimstate), 4);
	if (regdata & (SBIM_IBE | SBIM_TO))
		brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
			regdata & ~(SBIM_IBE | SBIM_TO));

	/* clear reset and allow it to propagate throughout the core */
	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
		(SICF_FGC << SBTML_SICF_SHIFT) |
		(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
	udelay(1);

	/* leave clock enabled */
	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
		(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
	udelay(1);
}

static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
				       struct chip_info *ci, u32 regs)
{
	u32 regdata;

	/*
	 * Get CC core rev
	 * Chipid is assume to be at offset 0 from regs arg
	 * For different chiptypes or old sdio hosts w/o chipcommon,
	 * other ways of recognition should be added here.
	 */
	ci->cccorebase = regs;
	regdata = brcmf_sdcard_reg_read(sdiodev,
				CORE_CC_REG(ci->cccorebase, chipid), 4);
	ci->chip = regdata & CID_ID_MASK;
	ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;

	brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);

	/* Address of cores for new chips should be added here */
	switch (ci->chip) {
	case BCM4329_CHIP_ID:
		ci->buscorebase = BCM4329_CORE_BUS_BASE;
		ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
		ci->armcorebase	= BCM4329_CORE_ARM_BASE;
		ci->ramsize = BCM4329_RAMSIZE;
		break;
	default:
		brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
		return -ENODEV;
	}

	return 0;
}

static int
brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev)
{
	int err = 0;
	u8 clkval, clkset;

	/* Try forcing SDIO core to do ALPAvail request only */
	clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
	brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
			       SBSDIO_FUNC1_CHIPCLKCSR,	clkset, &err);
	if (err) {
		brcmf_dbg(ERROR, "error writing for HT off\n");
		return err;
	}

	/* If register supported, wait for ALPAvail and then force ALP */
	/* This may take up to 15 milliseconds */
	clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
				       SBSDIO_FUNC1_CHIPCLKCSR, NULL);

	if ((clkval & ~SBSDIO_AVBITS) != clkset) {
		brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
			  clkset, clkval);
		return -EACCES;
	}

	SPINWAIT(((clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
				SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
			!SBSDIO_ALPAV(clkval)),
			PMU_MAX_TRANSITION_DLY);
	if (!SBSDIO_ALPAV(clkval)) {
		brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
			  clkval);
		return -EBUSY;
	}

	clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
	brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
			       SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
	udelay(65);

	/* Also, disable the extra SDIO pull-ups */
	brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
			       SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);

	return 0;
}

static void
brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
			     struct chip_info *ci)
{
	u32 regdata;

	/* get chipcommon rev */
	ci->ccrev = brcmf_sdio_chip_corerev(sdiodev, ci->cccorebase);

	/* get chipcommon capabilites */
	ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
		CORE_CC_REG(ci->cccorebase, capabilities), 4);

	/* get pmu caps & rev */
	if (ci->cccaps & CC_CAP_PMU) {
		ci->pmucaps = brcmf_sdcard_reg_read(sdiodev,
			CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
		ci->pmurev = ci->pmucaps & PCAP_REV_MASK;
	}


	ci->buscorerev = brcmf_sdio_chip_corerev(sdiodev, ci->buscorebase);
	regdata = brcmf_sdcard_reg_read(sdiodev,
					CORE_SB(ci->buscorebase, sbidhigh), 4);
	ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;

	brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
		  ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);

	/*
	 * Make sure any on-chip ARM is off (in case strapping is wrong),
	 * or downloaded code was already running.
	 */
	brcmf_sdio_chip_coredisable(sdiodev, ci->armcorebase);
}

int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
			   struct chip_info **ci_ptr, u32 regs)
{
	int ret;
	struct chip_info *ci;

	brcmf_dbg(TRACE, "Enter\n");

	/* alloc chip_info_t */
	ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
	if (!ci)
		return -ENOMEM;

	ret = brcmf_sdio_chip_buscoreprep(sdiodev);
	if (ret != 0)
		goto err;

	ret = brcmf_sdio_chip_recognition(sdiodev, ci, regs);
	if (ret != 0)
		goto err;

	brcmf_sdio_chip_buscoresetup(sdiodev, ci);

	brcmf_sdcard_reg_write(sdiodev,
		CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
	brcmf_sdcard_reg_write(sdiodev,
		CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);

	*ci_ptr = ci;
	return 0;

err:
	kfree(ci);
	return ret;
}
Commit	Line	Data
a83369b6 FL	1	/*
	2	* Copyright (c) 2011 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16	/* *** SDIO interface chip backplane handle functions *** */
	17
	18	#include <linux/types.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/mmc/card.h>
	21	#include <chipcommon.h>
	22	#include <brcm_hw_ids.h>
	23	#include <brcmu_wifi.h>
	24	#include <brcmu_utils.h>
2d4a9af1	25	#include <soc.h>
a83369b6 FL	26	#include "dhd.h"
	27	#include "dhd_dbg.h"
	28	#include "sdio_host.h"
	29	#include "sdio_chip.h"
	30
	31	/* chip core base & ramsize */
	32	/* bcm4329 */
	33	/* SDIO device core, ID 0x829 */
	34	#define BCM4329_CORE_BUS_BASE 0x18011000
	35	/* internal memory core, ID 0x80e */
	36	#define BCM4329_CORE_SOCRAM_BASE 0x18003000
	37	/* ARM Cortex M3 core, ID 0x82a */
	38	#define BCM4329_CORE_ARM_BASE 0x18002000
	39	#define BCM4329_RAMSIZE 0x48000
	40
	41
	42	/* SB regs */
	43	/* sbidhigh */
	44	#define SBIDH_RC_MASK 0x000f /* revision code */
	45	#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
	46	#define SBIDH_RCE_SHIFT 8
	47	#define SBCOREREV(sbidh) \
	48	((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) \| \
	49	((sbidh) & SBIDH_RC_MASK))
	50	#define SBIDH_CC_MASK 0x8ff0 /* core code */
	51	#define SBIDH_CC_SHIFT 4
	52	#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
	53	#define SBIDH_VC_SHIFT 16
	54
454d2a88 FL	55	static u32
	56	brcmf_sdio_chip_corerev(struct brcmf_sdio_dev *sdiodev,
	57	u32 corebase)
	58	{
	59	u32 regdata;
	60
	61	regdata = brcmf_sdcard_reg_read(sdiodev,
	62	CORE_SB(corebase, sbidhigh), 4);
	63	return SBCOREREV(regdata);
	64	}
	65
d8f64a42 FL	66	bool
	67	brcmf_sdio_chip_iscoreup(struct brcmf_sdio_dev *sdiodev,
	68	u32 corebase)
	69	{
	70	u32 regdata;
	71
	72	regdata = brcmf_sdcard_reg_read(sdiodev,
	73	CORE_SB(corebase, sbtmstatelow), 4);
	74	regdata &= (SBTML_RESET \| SBTML_REJ_MASK \|
	75	(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
	76	return ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) == regdata);
	77	}
	78
2d4a9af1 FL	79	void
	80	brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
	81	{
	82	u32 regdata;
	83
	84	regdata = brcmf_sdcard_reg_read(sdiodev,
	85	CORE_SB(corebase, sbtmstatelow), 4);
	86	if (regdata & SBTML_RESET)
	87	return;
	88
	89	regdata = brcmf_sdcard_reg_read(sdiodev,
	90	CORE_SB(corebase, sbtmstatelow), 4);
	91	if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
	92	/*
	93	* set target reject and spin until busy is clear
	94	* (preserve core-specific bits)
	95	*/
	96	regdata = brcmf_sdcard_reg_read(sdiodev,
	97	CORE_SB(corebase, sbtmstatelow), 4);
	98	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
	99	4, regdata \| SBTML_REJ);
	100
	101	regdata = brcmf_sdcard_reg_read(sdiodev,
	102	CORE_SB(corebase, sbtmstatelow), 4);
	103	udelay(1);
	104	SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
	105	CORE_SB(corebase, sbtmstatehigh), 4) &
	106	SBTMH_BUSY), 100000);
	107
	108	regdata = brcmf_sdcard_reg_read(sdiodev,
	109	CORE_SB(corebase, sbtmstatehigh), 4);
	110	if (regdata & SBTMH_BUSY)
	111	brcmf_dbg(ERROR, "core state still busy\n");
	112
	113	regdata = brcmf_sdcard_reg_read(sdiodev,
	114	CORE_SB(corebase, sbidlow), 4);
	115	if (regdata & SBIDL_INIT) {
	116	regdata = brcmf_sdcard_reg_read(sdiodev,
	117	CORE_SB(corebase, sbimstate), 4) \|
	118	SBIM_RJ;
	119	brcmf_sdcard_reg_write(sdiodev,
	120	CORE_SB(corebase, sbimstate), 4,
	121	regdata);
	122	regdata = brcmf_sdcard_reg_read(sdiodev,
	123	CORE_SB(corebase, sbimstate), 4);
	124	udelay(1);
	125	SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
	126	CORE_SB(corebase, sbimstate), 4) &
	127	SBIM_BY), 100000);
	128	}
	129
	130	/* set reset and reject while enabling the clocks */
	131	brcmf_sdcard_reg_write(sdiodev,
	132	CORE_SB(corebase, sbtmstatelow), 4,
	133	(((SICF_FGC \| SICF_CLOCK_EN) << SBTML_SICF_SHIFT) \|
	134	SBTML_REJ \| SBTML_RESET));
	135	regdata = brcmf_sdcard_reg_read(sdiodev,
	136	CORE_SB(corebase, sbtmstatelow), 4);
	137	udelay(10);
	138
	139	/* clear the initiator reject bit */
	140	regdata = brcmf_sdcard_reg_read(sdiodev,
	141	CORE_SB(corebase, sbidlow), 4);
	142	if (regdata & SBIDL_INIT) {
143	regdata = brcmf_sdcard_reg_read(sdiodev,
144	CORE_SB(corebase, sbimstate), 4) &
145	~SBIM_RJ;
146	brcmf_sdcard_reg_write(sdiodev,
147	CORE_SB(corebase, sbimstate), 4,
148	regdata);
149	}
150	}
151
152	/* leave reset and reject asserted */
153	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
154	(SBTML_REJ \| SBTML_RESET));
155	udelay(1);
156	}
157
2bc78e10 FL	158	void
	159	brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
	160	{
	161	u32 regdata;
	162
	163	/*
	164	* Must do the disable sequence first to work for
	165	* arbitrary current core state.
	166	*/
	167	brcmf_sdio_chip_coredisable(sdiodev, corebase);
	168
	169	/*
	170	* Now do the initialization sequence.
	171	* set reset while enabling the clock and
	172	* forcing them on throughout the core
	173	*/
	174	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
	175	((SICF_FGC \| SICF_CLOCK_EN) << SBTML_SICF_SHIFT) \|
	176	SBTML_RESET);
	177	udelay(1);
	178
	179	regdata = brcmf_sdcard_reg_read(sdiodev,
	180	CORE_SB(corebase, sbtmstatehigh), 4);
	181	if (regdata & SBTMH_SERR)
	182	brcmf_sdcard_reg_write(sdiodev,
	183	CORE_SB(corebase, sbtmstatehigh), 4, 0);
	184
	185	regdata = brcmf_sdcard_reg_read(sdiodev,
	186	CORE_SB(corebase, sbimstate), 4);
	187	if (regdata & (SBIM_IBE \| SBIM_TO))
	188	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
	189	regdata & ~(SBIM_IBE \| SBIM_TO));
	190
	191	/* clear reset and allow it to propagate throughout the core */
	192	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
	193	(SICF_FGC << SBTML_SICF_SHIFT) \|
	194	(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
	195	udelay(1);
	196
	197	/* leave clock enabled */
	198	brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
	199	(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
	200	udelay(1);
	201	}
	202
a83369b6 FL	203	static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
	204	struct chip_info *ci, u32 regs)
	205	{
	206	u32 regdata;
	207
	208	/*
	209	* Get CC core rev
	210	* Chipid is assume to be at offset 0 from regs arg
	211	* For different chiptypes or old sdio hosts w/o chipcommon,
	212	* other ways of recognition should be added here.
	213	*/
	214	ci->cccorebase = regs;
	215	regdata = brcmf_sdcard_reg_read(sdiodev,
	216	CORE_CC_REG(ci->cccorebase, chipid), 4);
	217	ci->chip = regdata & CID_ID_MASK;
	218	ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
	219
	220	brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
	221
	222	/* Address of cores for new chips should be added here */
	223	switch (ci->chip) {
	224	case BCM4329_CHIP_ID:
	225	ci->buscorebase = BCM4329_CORE_BUS_BASE;
	226	ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
	227	ci->armcorebase = BCM4329_CORE_ARM_BASE;
	228	ci->ramsize = BCM4329_RAMSIZE;
	229	break;
	230	default:
	231	brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
	232	return -ENODEV;
	233	}
	234
a83369b6 FL	235	return 0;
	236	}
	237
e63ac6b8 FL	238	static int
	239	brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev)
	240	{
	241	int err = 0;
	242	u8 clkval, clkset;
	243
	244	/* Try forcing SDIO core to do ALPAvail request only */
	245	clkset = SBSDIO_FORCE_HW_CLKREQ_OFF \| SBSDIO_ALP_AVAIL_REQ;
	246	brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
	247	SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
	248	if (err) {
	249	brcmf_dbg(ERROR, "error writing for HT off\n");
	250	return err;
	251	}
	252
	253	/* If register supported, wait for ALPAvail and then force ALP */
	254	/* This may take up to 15 milliseconds */
	255	clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
	256	SBSDIO_FUNC1_CHIPCLKCSR, NULL);
	257
	258	if ((clkval & ~SBSDIO_AVBITS) != clkset) {
	259	brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
	260	clkset, clkval);
	261	return -EACCES;
	262	}
	263
	264	SPINWAIT(((clkval = brcmf_sdcard_cfg_read(sdiodev, SDIO_FUNC_1,
	265	SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
	266	!SBSDIO_ALPAV(clkval)),
	267	PMU_MAX_TRANSITION_DLY);
	268	if (!SBSDIO_ALPAV(clkval)) {
	269	brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
	270	clkval);
	271	return -EBUSY;
	272	}
	273
	274	clkset = SBSDIO_FORCE_HW_CLKREQ_OFF \| SBSDIO_FORCE_ALP;
	275	brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
	276	SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
	277	udelay(65);
	278
	279	/* Also, disable the extra SDIO pull-ups */
	280	brcmf_sdcard_cfg_write(sdiodev, SDIO_FUNC_1,
	281	SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
	282
	283	return 0;
	284	}
	285
5b45e54e FL	286	static void
	287	brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
	288	struct chip_info *ci)
	289	{
	290	u32 regdata;
	291
	292	/* get chipcommon rev */
454d2a88	293	ci->ccrev = brcmf_sdio_chip_corerev(sdiodev, ci->cccorebase);
5b45e54e FL	294
	295	/* get chipcommon capabilites */
	296	ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
	297	CORE_CC_REG(ci->cccorebase, capabilities), 4);
	298
	299	/* get pmu caps & rev */
	300	if (ci->cccaps & CC_CAP_PMU) {
	301	ci->pmucaps = brcmf_sdcard_reg_read(sdiodev,
	302	CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
	303	ci->pmurev = ci->pmucaps & PCAP_REV_MASK;
	304	}
	305
454d2a88 FL	306
454d2a88 FL	307	ci->buscorerev = brcmf_sdio_chip_corerev(sdiodev, ci->buscorebase);
5b45e54e FL	308	regdata = brcmf_sdcard_reg_read(sdiodev,
5b45e54e FL	309	CORE_SB(ci->buscorebase, sbidhigh), 4);
5b45e54e FL	310	ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
	311
	312	brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
	313	ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
966414da FL	314
	315	/*
	316	* Make sure any on-chip ARM is off (in case strapping is wrong),
	317	* or downloaded code was already running.
	318	*/
	319	brcmf_sdio_chip_coredisable(sdiodev, ci->armcorebase);
5b45e54e FL	320	}
5b45e54e FL	321
a83369b6	322	int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
a97e4fc5	323	struct chip_info **ci_ptr, u32 regs)
a83369b6	324	{
a97e4fc5 FL	325	int ret;
	326	struct chip_info *ci;
	327
	328	brcmf_dbg(TRACE, "Enter\n");
	329
	330	/* alloc chip_info_t */
	331	ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
	332	if (!ci)
	333	return -ENOMEM;
a83369b6	334
e63ac6b8 FL	335	ret = brcmf_sdio_chip_buscoreprep(sdiodev);
e63ac6b8 FL	336	if (ret != 0)
a97e4fc5	337	goto err;
e63ac6b8	338
a83369b6 FL	339	ret = brcmf_sdio_chip_recognition(sdiodev, ci, regs);
a83369b6 FL	340	if (ret != 0)
a97e4fc5	341	goto err;
a83369b6	342
5b45e54e FL	343	brcmf_sdio_chip_buscoresetup(sdiodev, ci);
5b45e54e FL	344
960908dc FL	345	brcmf_sdcard_reg_write(sdiodev,
	346	CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
	347	brcmf_sdcard_reg_write(sdiodev,
	348	CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
	349
a97e4fc5 FL	350	*ci_ptr = ci;
	351	return 0;
	352
	353	err:
	354	kfree(ci);
a83369b6 FL	355	return ret;
a83369b6 FL	356	}