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a83369b6 FL |
1 | /* |
2 | * Copyright (c) 2011 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef _BRCMFMAC_SDIO_CHIP_H_ | |
18 | #define _BRCMFMAC_SDIO_CHIP_H_ | |
19 | ||
20 | /* | |
21 | * Core reg address translation. | |
22 | * Both macro's returns a 32 bits byte address on the backplane bus. | |
23 | */ | |
24 | #define CORE_CC_REG(base, field) \ | |
25 | (base + offsetof(struct chipcregs, field)) | |
26 | #define CORE_BUS_REG(base, field) \ | |
27 | (base + offsetof(struct sdpcmd_regs, field)) | |
28 | #define CORE_SB(base, field) \ | |
29 | (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) | |
30 | ||
e63ac6b8 FL |
31 | /* SDIO function 1 register CHIPCLKCSR */ |
32 | /* Force ALP request to backplane */ | |
33 | #define SBSDIO_FORCE_ALP 0x01 | |
34 | /* Force HT request to backplane */ | |
35 | #define SBSDIO_FORCE_HT 0x02 | |
36 | /* Force ILP request to backplane */ | |
37 | #define SBSDIO_FORCE_ILP 0x04 | |
38 | /* Make ALP ready (power up xtal) */ | |
39 | #define SBSDIO_ALP_AVAIL_REQ 0x08 | |
40 | /* Make HT ready (power up PLL) */ | |
41 | #define SBSDIO_HT_AVAIL_REQ 0x10 | |
42 | /* Squelch clock requests from HW */ | |
43 | #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 | |
44 | /* Status: ALP is ready */ | |
45 | #define SBSDIO_ALP_AVAIL 0x40 | |
46 | /* Status: HT is ready */ | |
47 | #define SBSDIO_HT_AVAIL 0x80 | |
48 | #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) | |
49 | #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) | |
50 | #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) | |
51 | #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) | |
52 | #define SBSDIO_CLKAV(regval, alponly) \ | |
53 | (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) | |
2d4a9af1 | 54 | |
99ba15cd FL |
55 | #define BRCMF_MAX_CORENUM 6 |
56 | ||
57 | struct chip_core_info { | |
58 | u16 id; | |
59 | u16 rev; | |
60 | u32 base; | |
61 | u32 wrapbase; | |
62 | u32 caps; | |
523894f2 | 63 | u32 cib; |
99ba15cd FL |
64 | }; |
65 | ||
a83369b6 FL |
66 | struct chip_info { |
67 | u32 chip; | |
68 | u32 chiprev; | |
6ca687d9 | 69 | u32 socitype; |
99ba15cd FL |
70 | /* core info */ |
71 | /* always put chipcommon core at 0, bus core at 1 */ | |
72 | struct chip_core_info c_inf[BRCMF_MAX_CORENUM]; | |
a83369b6 | 73 | u32 pmurev; |
5b45e54e | 74 | u32 pmucaps; |
a83369b6 | 75 | u32 ramsize; |
6ca687d9 FL |
76 | |
77 | bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci, | |
78 | u16 coreid); | |
523894f2 FL |
79 | u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci, |
80 | u16 coreid); | |
a83369b6 FL |
81 | }; |
82 | ||
83 | struct sbconfig { | |
84 | u32 PAD[2]; | |
85 | u32 sbipsflag; /* initiator port ocp slave flag */ | |
86 | u32 PAD[3]; | |
87 | u32 sbtpsflag; /* target port ocp slave flag */ | |
88 | u32 PAD[11]; | |
89 | u32 sbtmerrloga; /* (sonics >= 2.3) */ | |
90 | u32 PAD; | |
91 | u32 sbtmerrlog; /* (sonics >= 2.3) */ | |
92 | u32 PAD[3]; | |
93 | u32 sbadmatch3; /* address match3 */ | |
94 | u32 PAD; | |
95 | u32 sbadmatch2; /* address match2 */ | |
96 | u32 PAD; | |
97 | u32 sbadmatch1; /* address match1 */ | |
98 | u32 PAD[7]; | |
99 | u32 sbimstate; /* initiator agent state */ | |
100 | u32 sbintvec; /* interrupt mask */ | |
101 | u32 sbtmstatelow; /* target state */ | |
102 | u32 sbtmstatehigh; /* target state */ | |
103 | u32 sbbwa0; /* bandwidth allocation table0 */ | |
104 | u32 PAD; | |
105 | u32 sbimconfiglow; /* initiator configuration */ | |
106 | u32 sbimconfighigh; /* initiator configuration */ | |
107 | u32 sbadmatch0; /* address match0 */ | |
108 | u32 PAD; | |
109 | u32 sbtmconfiglow; /* target configuration */ | |
110 | u32 sbtmconfighigh; /* target configuration */ | |
111 | u32 sbbconfig; /* broadcast configuration */ | |
112 | u32 PAD; | |
113 | u32 sbbstate; /* broadcast state */ | |
114 | u32 PAD[3]; | |
115 | u32 sbactcnfg; /* activate configuration */ | |
116 | u32 PAD[3]; | |
117 | u32 sbflagst; /* current sbflags */ | |
118 | u32 PAD[3]; | |
119 | u32 sbidlow; /* identification */ | |
120 | u32 sbidhigh; /* identification */ | |
121 | }; | |
122 | ||
2bc78e10 FL |
123 | extern void brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev, |
124 | u32 corebase); | |
2d4a9af1 FL |
125 | extern void brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, |
126 | u32 corebase); | |
a83369b6 | 127 | extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev, |
a97e4fc5 | 128 | struct chip_info **ci_ptr, u32 regs); |
a8a6c045 | 129 | extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr); |
e12afb6c FL |
130 | extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, |
131 | struct chip_info *ci, | |
132 | u32 drivestrength); | |
99ba15cd FL |
133 | extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid); |
134 | ||
a83369b6 FL |
135 | |
136 | #endif /* _BRCMFMAC_SDIO_CHIP_H_ */ |