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brcmsmac: remove ai_get_buscore{type,rev}()
[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmsmac / aiutils.c
CommitLineData
5b435de0
AS		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * File contents: support functions for PCI/PCIe
17 */
18
8505a7e6
JP		 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
5b435de0 21#include <linux/delay.h>
5b435de0
AS		 22
23#include <defs.h>
24#include <chipcommon.h>
25#include <brcmu_utils.h>
26#include <brcm_hw_ids.h>
27#include <soc.h>
28#include "types.h"
29#include "pub.h"
30#include "pmu.h"
5b435de0
AS		 31#include "aiutils.h"
32
33/* slow_clk_ctl */
34 /* slow clock source mask */
35#define SCC_SS_MASK 0x00000007
36 /* source of slow clock is LPO */
37#define SCC_SS_LPO 0x00000000
38 /* source of slow clock is crystal */
39#define SCC_SS_XTAL 0x00000001
40 /* source of slow clock is PCI */
41#define SCC_SS_PCI 0x00000002
42 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
43#define SCC_LF 0x00000200
44 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
45#define SCC_LP 0x00000400
46 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
47#define SCC_FS 0x00000800
48 /* IgnorePllOffReq, 1/0:
49 * power logic ignores/honors PLL clock disable requests from core
50 */
51#define SCC_IP 0x00001000
52 /* XtalControlEn, 1/0:
53 * power logic does/doesn't disable crystal when appropriate
54 */
55#define SCC_XC 0x00002000
56 /* XtalPU (RO), 1/0: crystal running/disabled */
57#define SCC_XP 0x00004000
58 /* ClockDivider (SlowClk = 1/(4+divisor)) */
59#define SCC_CD_MASK 0xffff0000
60#define SCC_CD_SHIFT 16
61
62/* system_clk_ctl */
63 /* ILPen: Enable Idle Low Power */
64#define SYCC_IE 0x00000001
65 /* ALPen: Enable Active Low Power */
66#define SYCC_AE 0x00000002
67 /* ForcePLLOn */
68#define SYCC_FP 0x00000004
69 /* Force ALP (or HT if ALPen is not set */
70#define SYCC_AR 0x00000008
71 /* Force HT */
72#define SYCC_HR 0x00000010
73 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
74#define SYCC_CD_MASK 0xffff0000
75#define SYCC_CD_SHIFT 16
76
77#define CST4329_SPROM_OTP_SEL_MASK 0x00000003
78 /* OTP is powered up, use def. CIS, no SPROM */
79#define CST4329_DEFCIS_SEL 0
80 /* OTP is powered up, SPROM is present */
81#define CST4329_SPROM_SEL 1
82 /* OTP is powered up, no SPROM */
83#define CST4329_OTP_SEL 2
84 /* OTP is powered down, SPROM is present */
85#define CST4329_OTP_PWRDN 3
86
87#define CST4329_SPI_SDIO_MODE_MASK 0x00000004
88#define CST4329_SPI_SDIO_MODE_SHIFT 2
89
90/* 43224 chip-specific ChipControl register bits */
91#define CCTRL43224_GPIO_TOGGLE 0x8000
92 /* 12 mA drive strength */
93#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0
94 /* 12 mA drive strength for later 43224s */
95#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0
96
97/* 43236 Chip specific ChipStatus register bits */
98#define CST43236_SFLASH_MASK 0x00000040
99#define CST43236_OTP_MASK 0x00000080
100#define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
101#define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
102#define CST43236_BOOT_MASK 0x00001800
103#define CST43236_BOOT_SHIFT 11
104#define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
105#define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
106#define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
107#define CST43236_BOOT_FROM_INVALID 3
108
109/* 4331 chip-specific ChipControl register bits */
110 /* 0 disable */
111#define CCTRL4331_BT_COEXIST (1<<0)
112 /* 0 SECI is disabled (JTAG functional) */
113#define CCTRL4331_SECI (1<<1)
114 /* 0 disable */
115#define CCTRL4331_EXT_LNA (1<<2)
116 /* sprom/gpio13-15 mux */
117#define CCTRL4331_SPROM_GPIO13_15 (1<<3)
118 /* 0 ext pa disable, 1 ext pa enabled */
119#define CCTRL4331_EXTPA_EN (1<<4)
120 /* set drive out GPIO_CLK on sprom_cs pin */
121#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5)
122 /* use sprom_cs pin as PCIE mdio interface */
123#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6)
124 /* aband extpa will be at gpio2/5 and sprom_dout */
125#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7)
126 /* override core control on pipe_AuxClkEnable */
127#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8)
128 /* override core control on pipe_AuxPowerDown */
129#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9)
130 /* pcie_auxclkenable */
131#define CCTRL4331_PCIE_AUXCLKEN (1<<10)
132 /* pcie_pipe_pllpowerdown */
133#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11)
134 /* enable bt_shd0 at gpio4 */
135#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16)
136 /* enable bt_shd1 at gpio5 */
137#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17)
138
139/* 4331 Chip specific ChipStatus register bits */
140 /* crystal frequency 20/40Mhz */
141#define CST4331_XTAL_FREQ 0x00000001
142#define CST4331_SPROM_PRESENT 0x00000002
143#define CST4331_OTP_PRESENT 0x00000004
144#define CST4331_LDO_RF 0x00000008
145#define CST4331_LDO_PAR 0x00000010
146
147/* 4319 chip-specific ChipStatus register bits */
148#define CST4319_SPI_CPULESSUSB 0x00000001
149#define CST4319_SPI_CLK_POL 0x00000002
150#define CST4319_SPI_CLK_PH 0x00000008
151 /* gpio [7:6], SDIO CIS selection */
152#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0
153#define CST4319_SPROM_OTP_SEL_SHIFT 6
154 /* use default CIS, OTP is powered up */
155#define CST4319_DEFCIS_SEL 0x00000000
156 /* use SPROM, OTP is powered up */
157#define CST4319_SPROM_SEL 0x00000040
158 /* use OTP, OTP is powered up */
159#define CST4319_OTP_SEL 0x00000080
160 /* use SPROM, OTP is powered down */
161#define CST4319_OTP_PWRDN 0x000000c0
162 /* gpio [8], sdio/usb mode */
163#define CST4319_SDIO_USB_MODE 0x00000100
164#define CST4319_REMAP_SEL_MASK 0x00000600
165#define CST4319_ILPDIV_EN 0x00000800
166#define CST4319_XTAL_PD_POL 0x00001000
167#define CST4319_LPO_SEL 0x00002000
168#define CST4319_RES_INIT_MODE 0x0000c000
169 /* PALDO is configured with external PNP */
170#define CST4319_PALDO_EXTPNP 0x00010000
171#define CST4319_CBUCK_MODE_MASK 0x00060000
172#define CST4319_CBUCK_MODE_BURST 0x00020000
173#define CST4319_CBUCK_MODE_LPBURST 0x00060000
174#define CST4319_RCAL_VALID 0x01000000
175#define CST4319_RCAL_VALUE_MASK 0x3e000000
176#define CST4319_RCAL_VALUE_SHIFT 25
177
178/* 4336 chip-specific ChipStatus register bits */
179#define CST4336_SPI_MODE_MASK 0x00000001
180#define CST4336_SPROM_PRESENT 0x00000002
181#define CST4336_OTP_PRESENT 0x00000004
182#define CST4336_ARMREMAP_0 0x00000008
183#define CST4336_ILPDIV_EN_MASK 0x00000010
184#define CST4336_ILPDIV_EN_SHIFT 4
185#define CST4336_XTAL_PD_POL_MASK 0x00000020
186#define CST4336_XTAL_PD_POL_SHIFT 5
187#define CST4336_LPO_SEL_MASK 0x00000040
188#define CST4336_LPO_SEL_SHIFT 6
189#define CST4336_RES_INIT_MODE_MASK 0x00000180
190#define CST4336_RES_INIT_MODE_SHIFT 7
191#define CST4336_CBUCK_MODE_MASK 0x00000600
192#define CST4336_CBUCK_MODE_SHIFT 9
193
194/* 4313 chip-specific ChipStatus register bits */
195#define CST4313_SPROM_PRESENT 1
196#define CST4313_OTP_PRESENT 2
197#define CST4313_SPROM_OTP_SEL_MASK 0x00000002
198#define CST4313_SPROM_OTP_SEL_SHIFT 0
199
200/* 4313 Chip specific ChipControl register bits */
201 /* 12 mA drive strengh for later 4313 */
202#define CCTRL_4313_12MA_LED_DRIVE 0x00000007
203
204/* Manufacturer Ids */
205#define MFGID_ARM 0x43b
206#define MFGID_BRCM 0x4bf
207#define MFGID_MIPS 0x4a7
208
209/* Enumeration ROM registers */
210#define ER_EROMENTRY 0x000
211#define ER_REMAPCONTROL 0xe00
212#define ER_REMAPSELECT 0xe04
213#define ER_MASTERSELECT 0xe10
214#define ER_ITCR 0xf00
215#define ER_ITIP 0xf04
216
217/* Erom entries */
218#define ER_TAG 0xe
219#define ER_TAG1 0x6
220#define ER_VALID 1
221#define ER_CI 0
222#define ER_MP 2
223#define ER_ADD 4
224#define ER_END 0xe
225#define ER_BAD 0xffffffff
226
227/* EROM CompIdentA */
228#define CIA_MFG_MASK 0xfff00000
229#define CIA_MFG_SHIFT 20
230#define CIA_CID_MASK 0x000fff00
231#define CIA_CID_SHIFT 8
232#define CIA_CCL_MASK 0x000000f0
233#define CIA_CCL_SHIFT 4
234
235/* EROM CompIdentB */
236#define CIB_REV_MASK 0xff000000
237#define CIB_REV_SHIFT 24
238#define CIB_NSW_MASK 0x00f80000
239#define CIB_NSW_SHIFT 19
240#define CIB_NMW_MASK 0x0007c000
241#define CIB_NMW_SHIFT 14
242#define CIB_NSP_MASK 0x00003e00
243#define CIB_NSP_SHIFT 9
244#define CIB_NMP_MASK 0x000001f0
245#define CIB_NMP_SHIFT 4
246
247/* EROM AddrDesc */
248#define AD_ADDR_MASK 0xfffff000
249#define AD_SP_MASK 0x00000f00
250#define AD_SP_SHIFT 8
251#define AD_ST_MASK 0x000000c0
252#define AD_ST_SHIFT 6
253#define AD_ST_SLAVE 0x00000000
254#define AD_ST_BRIDGE 0x00000040
255#define AD_ST_SWRAP 0x00000080
256#define AD_ST_MWRAP 0x000000c0
257#define AD_SZ_MASK 0x00000030
258#define AD_SZ_SHIFT 4
259#define AD_SZ_4K 0x00000000
260#define AD_SZ_8K 0x00000010
261#define AD_SZ_16K 0x00000020
262#define AD_SZ_SZD 0x00000030
263#define AD_AG32 0x00000008
264#define AD_ADDR_ALIGN 0x00000fff
265#define AD_SZ_BASE 0x00001000 /* 4KB */
266
267/* EROM SizeDesc */
268#define SD_SZ_MASK 0xfffff000
269#define SD_SG32 0x00000008
270#define SD_SZ_ALIGN 0x00000fff
271
272/* PCI config space bit 4 for 4306c0 slow clock source */
273#define PCI_CFG_GPIO_SCS 0x10
274/* PCI config space GPIO 14 for Xtal power-up */
275#define PCI_CFG_GPIO_XTAL 0x40
276/* PCI config space GPIO 15 for PLL power-down */
277#define PCI_CFG_GPIO_PLL 0x80
278
279/* power control defines */
280#define PLL_DELAY 150 /* us pll on delay */
281#define FREF_DELAY 200 /* us fref change delay */
282#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
283
284/* resetctrl */
285#define AIRC_RESET 1
286
287#define NOREV -1 /* Invalid rev */
288
289/* GPIO Based LED powersave defines */
290#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
291#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
292
293/* When Srom support present, fields in sromcontrol */
294#define SRC_START 0x80000000
295#define SRC_BUSY 0x80000000
296#define SRC_OPCODE 0x60000000
297#define SRC_OP_READ 0x00000000
298#define SRC_OP_WRITE 0x20000000
299#define SRC_OP_WRDIS 0x40000000
300#define SRC_OP_WREN 0x60000000
301#define SRC_OTPSEL 0x00000010
302#define SRC_LOCK 0x00000008
303#define SRC_SIZE_MASK 0x00000006
304#define SRC_SIZE_1K 0x00000000
305#define SRC_SIZE_4K 0x00000002
306#define SRC_SIZE_16K 0x00000004
307#define SRC_SIZE_SHIFT 1
308#define SRC_PRESENT 0x00000001
309
310/* External PA enable mask */
311#define GPIO_CTRL_EPA_EN_MASK 0x40
312
313#define DEFAULT_GPIOTIMERVAL \
314 ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
315
316#define BADIDX (SI_MAXCORES + 1)
317
5b435de0
AS		 318#define IS_SIM(chippkg) \
319 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
320
8ae74654 321#ifdef DEBUG
8505a7e6 322#define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__)
5b435de0 323#else
8505a7e6 324#define SI_MSG(fmt, ...) no_printk(fmt, ##__VA_ARGS__)
8ae74654 325#endif /* DEBUG */
5b435de0
AS		 326
327#define GOODCOREADDR(x, b) \
328 (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
329 IS_ALIGNED((x), SI_CORE_SIZE))
330
5b435de0
AS		 331struct aidmp {
332 u32 oobselina30; /* 0x000 */
333 u32 oobselina74; /* 0x004 */
334 u32 PAD[6];
335 u32 oobselinb30; /* 0x020 */
336 u32 oobselinb74; /* 0x024 */
337 u32 PAD[6];
338 u32 oobselinc30; /* 0x040 */
339 u32 oobselinc74; /* 0x044 */
340 u32 PAD[6];
341 u32 oobselind30; /* 0x060 */
342 u32 oobselind74; /* 0x064 */
343 u32 PAD[38];
344 u32 oobselouta30; /* 0x100 */
345 u32 oobselouta74; /* 0x104 */
346 u32 PAD[6];
347 u32 oobseloutb30; /* 0x120 */
348 u32 oobseloutb74; /* 0x124 */
349 u32 PAD[6];
350 u32 oobseloutc30; /* 0x140 */
351 u32 oobseloutc74; /* 0x144 */
352 u32 PAD[6];
353 u32 oobseloutd30; /* 0x160 */
354 u32 oobseloutd74; /* 0x164 */
355 u32 PAD[38];
356 u32 oobsynca; /* 0x200 */
357 u32 oobseloutaen; /* 0x204 */
358 u32 PAD[6];
359 u32 oobsyncb; /* 0x220 */
360 u32 oobseloutben; /* 0x224 */
361 u32 PAD[6];
362 u32 oobsyncc; /* 0x240 */
363 u32 oobseloutcen; /* 0x244 */
364 u32 PAD[6];
365 u32 oobsyncd; /* 0x260 */
366 u32 oobseloutden; /* 0x264 */
367 u32 PAD[38];
368 u32 oobaextwidth; /* 0x300 */
369 u32 oobainwidth; /* 0x304 */
370 u32 oobaoutwidth; /* 0x308 */
371 u32 PAD[5];
372 u32 oobbextwidth; /* 0x320 */
373 u32 oobbinwidth; /* 0x324 */
374 u32 oobboutwidth; /* 0x328 */
375 u32 PAD[5];
376 u32 oobcextwidth; /* 0x340 */
377 u32 oobcinwidth; /* 0x344 */
378 u32 oobcoutwidth; /* 0x348 */
379 u32 PAD[5];
380 u32 oobdextwidth; /* 0x360 */
381 u32 oobdinwidth; /* 0x364 */
382 u32 oobdoutwidth; /* 0x368 */
383 u32 PAD[37];
384 u32 ioctrlset; /* 0x400 */
385 u32 ioctrlclear; /* 0x404 */
386 u32 ioctrl; /* 0x408 */
387 u32 PAD[61];
388 u32 iostatus; /* 0x500 */
389 u32 PAD[127];
390 u32 ioctrlwidth; /* 0x700 */
391 u32 iostatuswidth; /* 0x704 */
392 u32 PAD[62];
393 u32 resetctrl; /* 0x800 */
394 u32 resetstatus; /* 0x804 */
395 u32 resetreadid; /* 0x808 */
396 u32 resetwriteid; /* 0x80c */
397 u32 PAD[60];
398 u32 errlogctrl; /* 0x900 */
399 u32 errlogdone; /* 0x904 */
400 u32 errlogstatus; /* 0x908 */
401 u32 errlogaddrlo; /* 0x90c */
402 u32 errlogaddrhi; /* 0x910 */
403 u32 errlogid; /* 0x914 */
404 u32 errloguser; /* 0x918 */
405 u32 errlogflags; /* 0x91c */
406 u32 PAD[56];
407 u32 intstatus; /* 0xa00 */
408 u32 PAD[127];
409 u32 config; /* 0xe00 */
410 u32 PAD[63];
411 u32 itcr; /* 0xf00 */
412 u32 PAD[3];
413 u32 itipooba; /* 0xf10 */
414 u32 itipoobb; /* 0xf14 */
415 u32 itipoobc; /* 0xf18 */
416 u32 itipoobd; /* 0xf1c */
417 u32 PAD[4];
418 u32 itipoobaout; /* 0xf30 */
419 u32 itipoobbout; /* 0xf34 */
420 u32 itipoobcout; /* 0xf38 */
421 u32 itipoobdout; /* 0xf3c */
422 u32 PAD[4];
423 u32 itopooba; /* 0xf50 */
424 u32 itopoobb; /* 0xf54 */
425 u32 itopoobc; /* 0xf58 */
426 u32 itopoobd; /* 0xf5c */
427 u32 PAD[4];
428 u32 itopoobain; /* 0xf70 */
429 u32 itopoobbin; /* 0xf74 */
430 u32 itopoobcin; /* 0xf78 */
431 u32 itopoobdin; /* 0xf7c */
432 u32 PAD[4];
433 u32 itopreset; /* 0xf90 */
434 u32 PAD[15];
435 u32 peripherialid4; /* 0xfd0 */
436 u32 peripherialid5; /* 0xfd4 */
437 u32 peripherialid6; /* 0xfd8 */
438 u32 peripherialid7; /* 0xfdc */
439 u32 peripherialid0; /* 0xfe0 */
440 u32 peripherialid1; /* 0xfe4 */
441 u32 peripherialid2; /* 0xfe8 */
442 u32 peripherialid3; /* 0xfec */
443 u32 componentid0; /* 0xff0 */
444 u32 componentid1; /* 0xff4 */
445 u32 componentid2; /* 0xff8 */
446 u32 componentid3; /* 0xffc */
447};
448
5b435de0 449static bool
c8086745 450ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
5b435de0 451{
99559f13
AS		 452 /* no cores found, bail out */
453 if (cc->bus->nr_cores == 0)
454 return false;
455
5b435de0 456 /* get chipcommon rev */
c8086745 457 sii->pub.ccrev = cc->id.rev;
5b435de0
AS		 458
459 /* get chipcommon chipstatus */
d43c1c52 460 sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
5b435de0
AS		 461
462 /* get chipcommon capabilites */
c8086745 463 sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));
5b435de0
AS		 464
465 /* get pmu rev and caps */
b2ffec46 466 if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
c8086745
AS		 467 sii->pub.pmucaps = bcma_read32(cc,
468 CHIPCREGOFFS(pmucapabilities));
5b435de0
AS		 469 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
470 }
471
5b435de0
AS		 472 return true;
473}
474
5b435de0 475static struct si_info *ai_doattach(struct si_info *sii,
28a53442 476 struct bcma_bus *pbus)
5b435de0
AS		 477{
478 struct si_pub *sih = &sii->pub;
479 u32 w, savewin;
c8086745 480 struct bcma_device *cc;
898d3c3b 481 struct ssb_sprom *sprom = &pbus->sprom;
5b435de0 482
5b435de0
AS		 483 savewin = 0;
484
28a53442 485 sii->icbus = pbus;
28a53442 486 sii->pcibus = pbus->host_pci;
5b435de0 487
16d2812e 488 /* switch to Chipcommon core */
c8086745 489 cc = pbus->drv_cc.core;
5b435de0 490
1928ad71
HM		 491 sih->chip = pbus->chipinfo.id;
492 sih->chiprev = pbus->chipinfo.rev;
493 sih->chippkg = pbus->chipinfo.pkg;
494 sih->boardvendor = pbus->boardinfo.vendor;
495 sih->boardtype = pbus->boardinfo.type;
5b435de0 496
c8086745 497 if (!ai_buscore_setup(sii, cc))
5b435de0
AS		 498 goto exit;
499
5b435de0 500 /* === NVRAM, clock is ready === */
c8086745
AS		 501 bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0);
502 bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0);
5b435de0
AS		 503
504 /* PMU specific initializations */
b2ffec46 505 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
5b435de0 506 si_pmu_init(sih);
291ed3dc 507 (void)si_pmu_measure_alpclk(sih);
5b435de0 508 si_pmu_res_init(sih);
5b435de0
AS		 509 }
510
511 /* setup the GPIO based LED powersave register */
898d3c3b
HM		 512 w = (sprom->leddc_on_time << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
513 (sprom->leddc_off_time << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT);
5b435de0
AS		 514 if (w == 0)
515 w = DEFAULT_GPIOTIMERVAL;
7d8e18e4
AS		 516 ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
517 ~0, w);
5b435de0 518
b2ffec46 519 if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
5b435de0
AS		 520 /*
521 * enable 12 mA drive strenth for 43224 and
522 * set chipControl register bit 15
523 */
b2ffec46 524 if (ai_get_chiprev(sih) == 0) {
8505a7e6 525 SI_MSG("Applying 43224A0 WARs\n");
7d8e18e4
AS		 526 ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol),
527 CCTRL43224_GPIO_TOGGLE,
528 CCTRL43224_GPIO_TOGGLE);
5b435de0
AS		 529 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
530 CCTRL_43224A0_12MA_LED_DRIVE);
531 }
b2ffec46 532 if (ai_get_chiprev(sih) >= 1) {
8505a7e6 533 SI_MSG("Applying 43224B0+ WARs\n");
5b435de0
AS		 534 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
535 CCTRL_43224B0_12MA_LED_DRIVE);
536 }
537 }
538
b2ffec46 539 if (ai_get_chip_id(sih) == BCM4313_CHIP_ID) {
5b435de0
AS		 540 /*
541 * enable 12 mA drive strenth for 4313 and
542 * set chipControl register bit 1
543 */
8505a7e6 544 SI_MSG("Applying 4313 WARs\n");
5b435de0
AS		 545 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
546 CCTRL_4313_12MA_LED_DRIVE);
547 }
548
549 return sii;
550
551 exit:
5b435de0
AS		 552
553 return NULL;
554}
555
556/*
28a53442 557 * Allocate a si handle and do the attach.
5b435de0
AS		 558 */
559struct si_pub *
28a53442 560ai_attach(struct bcma_bus *pbus)
5b435de0
AS		 561{
562 struct si_info *sii;
563
564 /* alloc struct si_info */
00d2ec0c 565 sii = kzalloc(sizeof(struct si_info), GFP_ATOMIC);
5b435de0
AS		 566 if (sii == NULL)
567 return NULL;
568
28a53442 569 if (ai_doattach(sii, pbus) == NULL) {
5b435de0
AS		 570 kfree(sii);
571 return NULL;
572 }
573
574 return (struct si_pub *) sii;
575}
576
577/* may be called with core in reset */
578void ai_detach(struct si_pub *sih)
579{
580 struct si_info *sii;
581
582 struct si_pub *si_local = NULL;
583 memcpy(&si_local, &sih, sizeof(struct si_pub **));
584
585 sii = (struct si_info *)sih;
586
587 if (sii == NULL)
588 return;
589
5b435de0
AS		 590 kfree(sii);
591}
592
5b435de0 593/* return index of coreid or BADIDX if not found */
d3126c52 594struct bcma_device *ai_findcore(struct si_pub *sih, u16 coreid, u16 coreunit)
5b435de0 595{
16d2812e 596 struct bcma_device *core;
5b435de0
AS		 597 struct si_info *sii;
598 uint found;
5b435de0
AS		 599
600 sii = (struct si_info *)sih;
601
602 found = 0;
603
16d2812e
AS		 604 list_for_each_entry(core, &sii->icbus->cores, list)
605 if (core->id.id == coreid) {
5b435de0 606 if (found == coreunit)
d3126c52 607 return core;
5b435de0
AS		 608 found++;
609 }
610
d3126c52 611 return NULL;
5b435de0
AS		 612}
613
614/*
3b758a68 615 * read/modify chipcommon core register.
5b435de0 616 */
7d8e18e4 617uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
5b435de0 618{
7d8e18e4 619 struct bcma_device *cc;
7d8e18e4 620 u32 w;
5b435de0
AS		 621 struct si_info *sii;
622
623 sii = (struct si_info *)sih;
7d8e18e4 624 cc = sii->icbus->drv_cc.core;
5b435de0 625
5b435de0 626 /* mask and set */
2b0446c4 627 if (mask || val)
7d8e18e4 628 bcma_maskset32(cc, regoff, ~mask, val);
5b435de0
AS		 629
630 /* readback */
7d8e18e4 631 w = bcma_read32(cc, regoff);
5b435de0 632
5b435de0
AS		 633 return w;
634}
635
5b435de0 636/* return the slow clock source - LPO, XTAL, or PCI */
c8086745 637static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
5b435de0 638{
d43c1c52 639 return SCC_SS_XTAL;
5b435de0
AS		 640}
641
642/*
643* return the ILP (slowclock) min or max frequency
644* precondition: we've established the chip has dynamic clk control
645*/
c8086745
AS		 646static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq,
647 struct bcma_device *cc)
5b435de0 648{
5b435de0
AS		 649 uint div;
650
d43c1c52
HM		 651 /* Chipc rev 10 is InstaClock */
652 div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
653 div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
654 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
5b435de0
AS		 655}
656
657static void
c8086745 658ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc)
5b435de0
AS		 659{
660 uint slowmaxfreq, pll_delay, slowclk;
661 uint pll_on_delay, fref_sel_delay;
662
663 pll_delay = PLL_DELAY;
664
665 /*
666 * If the slow clock is not sourced by the xtal then
667 * add the xtal_on_delay since the xtal will also be
668 * powered down by dynamic clk control logic.
669 */
670
c8086745 671 slowclk = ai_slowclk_src(sih, cc);
5b435de0
AS		 672 if (slowclk != SCC_SS_XTAL)
673 pll_delay += XTAL_ON_DELAY;
674
675 /* Starting with 4318 it is ILP that is used for the delays */
676 slowmaxfreq =
d43c1c52 677 ai_slowclk_freq(sih, false, cc);
5b435de0
AS		 678
679 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
680 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
681
c8086745
AS		 682 bcma_write32(cc, CHIPCREGOFFS(pll_on_delay), pll_on_delay);
683 bcma_write32(cc, CHIPCREGOFFS(fref_sel_delay), fref_sel_delay);
5b435de0
AS		 684}
685
686/* initialize power control delay registers */
687void ai_clkctl_init(struct si_pub *sih)
688{
c8086745 689 struct bcma_device *cc;
5b435de0 690
b2ffec46 691 if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
5b435de0
AS		 692 return;
693
c8086745 694 cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
ad5db131
AS		 695 if (cc == NULL)
696 return;
5b435de0
AS		 697
698 /* set all Instaclk chip ILP to 1 MHz */
d43c1c52
HM		 699 bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
700 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5b435de0 701
c8086745 702 ai_clkctl_setdelay(sih, cc);
5b435de0
AS		 703}
704
705/*
706 * return the value suitable for writing to the
707 * dot11 core FAST_PWRUP_DELAY register
708 */
709u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
710{
711 struct si_info *sii;
c8086745 712 struct bcma_device *cc;
5b435de0
AS		 713 uint slowminfreq;
714 u16 fpdelay;
5b435de0
AS		 715
716 sii = (struct si_info *)sih;
b2ffec46 717 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
5b435de0 718 fpdelay = si_pmu_fast_pwrup_delay(sih);
5b435de0
AS		 719 return fpdelay;
720 }
721
b2ffec46 722 if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
5b435de0
AS		 723 return 0;
724
5b435de0 725 fpdelay = 0;
c8086745 726 cc = ai_findcore(sih, CC_CORE_ID, 0);
a232c8a1
AS		 727 if (cc) {
728 slowminfreq = ai_slowclk_freq(sih, false, cc);
729 fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2)
730 * 1000000) + (slowminfreq - 1)) / slowminfreq;
731 }
5b435de0
AS		 732 return fpdelay;
733}
734
5b435de0
AS		 735/*
736 * clock control policy function throught chipcommon
737 *
738 * set dynamic clk control mode (forceslow, forcefast, dynamic)
739 * returns true if we are forcing fast clock
740 * this is a wrapper over the next internal function
741 * to allow flexible policy settings for outside caller
742 */
712e3c1f 743bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode)
5b435de0
AS		 744{
745 struct si_info *sii;
712e3c1f 746 struct bcma_device *cc;
5b435de0
AS		 747
748 sii = (struct si_info *)sih;
749
712e3c1f
HM		 750 cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
751 bcma_core_set_clockmode(cc, mode);
752 return mode == BCMA_CLKMODE_FAST;
5b435de0
AS		 753}
754
5b435de0
AS		 755void ai_pci_up(struct si_pub *sih)
756{
757 struct si_info *sii;
758
759 sii = (struct si_info *)sih;
760
a55b316e 761 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2ffd795a 762 bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
5b435de0
AS		 763}
764
5b435de0
AS		 765/* Unconfigure and/or apply various WARs when going down */
766void ai_pci_down(struct si_pub *sih)
767{
768 struct si_info *sii;
769
770 sii = (struct si_info *)sih;
771
a55b316e 772 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2ffd795a 773 bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
5b435de0
AS		 774}
775
5b435de0
AS		 776/* Enable BT-COEX & Ex-PA for 4313 */
777void ai_epa_4313war(struct si_pub *sih)
778{
c8086745 779 struct bcma_device *cc;
5b435de0 780
c8086745 781 cc = ai_findcore(sih, CC_CORE_ID, 0);
5b435de0
AS		 782
783 /* EPA Fix */
c8086745 784 bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK);
5b435de0
AS		 785}
786
787/* check if the device is removed */
788bool ai_deviceremoved(struct si_pub *sih)
789{
790 u32 w;
791 struct si_info *sii;
792
793 sii = (struct si_info *)sih;
794
22291cea
HM		 795 if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI)
796 return false;
797
cbc80db2 798 pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w);
5b435de0
AS		 799 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
800 return true;
801
802 return false;
803}
Linux kernel - Deliverables
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