[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmsmac / aiutils.h

/*
 * Copyright (c) 2011 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_BRCM_AIUTILS_H_
#define	_BRCM_AIUTILS_H_

#include <linux/bcma/bcma.h>

#include "types.h"

/*
 * SOC Interconnect Address Map.
 * All regions may not exist on all chips.
 */
/* each core gets 4Kbytes for registers */
#define SI_CORE_SIZE		0x1000
/*
 * Max cores (this is arbitrary, for software
 * convenience and could be changed if we
 * make any larger chips
 */
#define	SI_MAXCORES		16

/* Client Mode sb2pcitranslation2 size in bytes */
#define SI_PCI_DMA_SZ		0x40000000

/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
#define SI_PCIE_DMA_H32		0x80000000

/* chipcommon being the first core: */
#define	SI_CC_IDX		0

/* SOC Interconnect types (aka chip types) */
#define	SOCI_AI			1

/* A register that is common to all cores to
 * communicate w/PMU regarding clock control.
 */
#define SI_CLK_CTL_ST		0x1e0	/* clock control and status */

/* clk_ctl_st register */
#define	CCS_FORCEALP		0x00000001	/* force ALP request */
#define	CCS_FORCEHT		0x00000002	/* force HT request */
#define	CCS_FORCEILP		0x00000004	/* force ILP request */
#define	CCS_ALPAREQ		0x00000008	/* ALP Avail Request */
#define	CCS_HTAREQ		0x00000010	/* HT Avail Request */
#define	CCS_FORCEHWREQOFF	0x00000020	/* Force HW Clock Request Off */
#define CCS_ERSRC_REQ_MASK	0x00000700	/* external resource requests */
#define CCS_ERSRC_REQ_SHIFT	8
#define	CCS_ALPAVAIL		0x00010000	/* ALP is available */
#define	CCS_HTAVAIL		0x00020000	/* HT is available */
#define CCS_BP_ON_APL		0x00040000	/* RO: running on ALP clock */
#define CCS_BP_ON_HT		0x00080000	/* RO: running on HT clock */
#define CCS_ERSRC_STS_MASK	0x07000000	/* external resource status */
#define CCS_ERSRC_STS_SHIFT	24

/* HT avail in chipc and pcmcia on 4328a0 */
#define	CCS0_HTAVAIL		0x00010000
/* ALP avail in chipc and pcmcia on 4328a0 */
#define	CCS0_ALPAVAIL		0x00020000

/* Not really related to SOC Interconnect, but a couple of software
 * conventions for the use the flash space:
 */

/* Minumum amount of flash we support */
#define FLASH_MIN		0x00020000	/* Minimum flash size */

#define	CC_SROM_OTP		0x800	/* SROM/OTP address space */

/* gpiotimerval */
#define GPIO_ONTIME_SHIFT	16

/* Fields in clkdiv */
#define	CLKD_OTP		0x000f0000
#define	CLKD_OTP_SHIFT		16

/* dynamic clock control defines */
#define	LPOMINFREQ		25000	/* low power oscillator min */
#define	LPOMAXFREQ		43000	/* low power oscillator max */
#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
#define	PCIMINFREQ		25000000	/* 25 MHz */
#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */

#define	ILP_DIV_5MHZ		0	/* ILP = 5 MHz */
#define	ILP_DIV_1MHZ		4	/* ILP = 1 MHz */

/* clkctl xtal what flags */
#define	XTAL			0x1	/* primary crystal oscillator (2050) */
#define	PLL			0x2	/* main chip pll */

/* GPIO usage priorities */
#define GPIO_DRV_PRIORITY	0	/* Driver */
#define GPIO_APP_PRIORITY	1	/* Application */
#define GPIO_HI_PRIORITY	2	/* Highest priority. Ignore GPIO
					 * reservation
					 */

/* GPIO pull up/down */
#define GPIO_PULLUP		0
#define GPIO_PULLDN		1

/* GPIO event regtype */
#define GPIO_REGEVT		0	/* GPIO register event */
#define GPIO_REGEVT_INTMSK	1	/* GPIO register event int mask */
#define GPIO_REGEVT_INTPOL	2	/* GPIO register event int polarity */

/* device path */
#define SI_DEVPATH_BUFSZ	16	/* min buffer size in bytes */

/* SI routine enumeration: to be used by update function with multiple hooks */
#define	SI_DOATTACH	1
#define SI_PCIDOWN	2
#define SI_PCIUP	3

/*
 * Data structure to export all chip specific common variables
 *   public (read-only) portion of aiutils handle returned by si_attach()
 */
struct si_pub {
	int ccrev;		/* chip common core rev */
	u32 cccaps;		/* chip common capabilities */
	int pmurev;		/* pmu core rev */
	u32 pmucaps;		/* pmu capabilities */
	uint boardtype;		/* board type */
	uint boardvendor;	/* board vendor */
	uint chip;		/* chip number */
	uint chiprev;		/* chip revision */
	uint chippkg;		/* chip package option */
};

struct pci_dev;

struct gpioh_item {
	void *arg;
	bool level;
	void (*handler) (u32 stat, void *arg);
	u32 event;
	struct gpioh_item *next;
};

/* misc si info needed by some of the routines */
struct si_info {
	struct si_pub pub;	/* back plane public state (must be first) */
	struct bcma_bus *icbus;	/* handle to soc interconnect bus */
	struct pci_dev *pcibus;	/* handle to pci bus */

	u32 chipst;		/* chip status */
};

/*
 * Many of the routines below take an 'sih' handle as their first arg.
 * Allocate this by calling si_attach().  Free it by calling si_detach().
 * At any one time, the sih is logically focused on one particular si core
 * (the "current core").
 * Use si_setcore() or si_setcoreidx() to change the association to another core
 */


/* AMBA Interconnect exported externs */
u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);

/* === exported functions === */
struct si_pub *ai_attach(struct bcma_bus *pbus);
void ai_detach(struct si_pub *sih);
uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
void ai_clkctl_init(struct si_pub *sih);
u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
bool ai_deviceremoved(struct si_pub *sih);

/* Enable Ex-PA for 4313 */
void ai_epa_4313war(struct si_pub *sih);

static inline u32 ai_get_cccaps(struct si_pub *sih)
{
	return sih->cccaps;
}

static inline int ai_get_pmurev(struct si_pub *sih)
{
	return sih->pmurev;
}

static inline u32 ai_get_pmucaps(struct si_pub *sih)
{
	return sih->pmucaps;
}

static inline uint ai_get_boardtype(struct si_pub *sih)
{
	return sih->boardtype;
}

static inline uint ai_get_boardvendor(struct si_pub *sih)
{
	return sih->boardvendor;
}

static inline uint ai_get_chip_id(struct si_pub *sih)
{
	return sih->chip;
}

static inline uint ai_get_chiprev(struct si_pub *sih)
{
	return sih->chiprev;
}

static inline uint ai_get_chippkg(struct si_pub *sih)
{
	return sih->chippkg;
}

#endif				/* _BRCM_AIUTILS_H_ */
Commit	Line	Data
5b435de0 AS	1	/*
	2	* Copyright (c) 2011 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef _BRCM_AIUTILS_H_
	18	#define _BRCM_AIUTILS_H_
	19
28a53442 AS	20	#include <linux/bcma/bcma.h>
28a53442 AS	21
5b435de0 AS	22	#include "types.h"
	23
	24	/*
	25	* SOC Interconnect Address Map.
	26	* All regions may not exist on all chips.
	27	*/
	28	/* each core gets 4Kbytes for registers */
	29	#define SI_CORE_SIZE 0x1000
	30	/*
	31	* Max cores (this is arbitrary, for software
	32	* convenience and could be changed if we
	33	* make any larger chips
	34	*/
	35	#define SI_MAXCORES 16
	36
	37	/* Client Mode sb2pcitranslation2 size in bytes */
	38	#define SI_PCI_DMA_SZ 0x40000000
	39
	40	/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
	41	#define SI_PCIE_DMA_H32 0x80000000
	42
5b435de0 AS	43	/* chipcommon being the first core: */
	44	#define SI_CC_IDX 0
	45
	46	/* SOC Interconnect types (aka chip types) */
	47	#define SOCI_AI 1
	48
5b435de0 AS	49	/* A register that is common to all cores to
	50	* communicate w/PMU regarding clock control.
	51	*/
	52	#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
	53
	54	/* clk_ctl_st register */
	55	#define CCS_FORCEALP 0x00000001 /* force ALP request */
	56	#define CCS_FORCEHT 0x00000002 /* force HT request */
	57	#define CCS_FORCEILP 0x00000004 /* force ILP request */
	58	#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
	59	#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
	60	#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
	61	#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
	62	#define CCS_ERSRC_REQ_SHIFT 8
	63	#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
	64	#define CCS_HTAVAIL 0x00020000 /* HT is available */
	65	#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
	66	#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
	67	#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
	68	#define CCS_ERSRC_STS_SHIFT 24
	69
	70	/* HT avail in chipc and pcmcia on 4328a0 */
	71	#define CCS0_HTAVAIL 0x00010000
	72	/* ALP avail in chipc and pcmcia on 4328a0 */
	73	#define CCS0_ALPAVAIL 0x00020000
	74
	75	/* Not really related to SOC Interconnect, but a couple of software
	76	* conventions for the use the flash space:
	77	*/
	78
	79	/* Minumum amount of flash we support */
	80	#define FLASH_MIN 0x00020000 /* Minimum flash size */
	81
	82	#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
	83
	84	/* gpiotimerval */
	85	#define GPIO_ONTIME_SHIFT 16
	86
	87	/* Fields in clkdiv */
	88	#define CLKD_OTP 0x000f0000
	89	#define CLKD_OTP_SHIFT 16
	90
5b435de0 AS	91	/* dynamic clock control defines */
	92	#define LPOMINFREQ 25000 /* low power oscillator min */
	93	#define LPOMAXFREQ 43000 /* low power oscillator max */
	94	#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
	95	#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
	96	#define PCIMINFREQ 25000000 /* 25 MHz */
	97	#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
	98
	99	#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
	100	#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
	101
	102	/* clkctl xtal what flags */
	103	#define XTAL 0x1 /* primary crystal oscillator (2050) */
	104	#define PLL 0x2 /* main chip pll */
	105
5b435de0 AS	106	/* GPIO usage priorities */
	107	#define GPIO_DRV_PRIORITY 0 /* Driver */
	108	#define GPIO_APP_PRIORITY 1 /* Application */
	109	#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
	110	* reservation
	111	*/
	112
	113	/* GPIO pull up/down */
	114	#define GPIO_PULLUP 0
	115	#define GPIO_PULLDN 1
	116
	117	/* GPIO event regtype */
	118	#define GPIO_REGEVT 0 /* GPIO register event */
	119	#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
	120	#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
	121
	122	/* device path */
	123	#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
	124
	125	/* SI routine enumeration: to be used by update function with multiple hooks */
	126	#define SI_DOATTACH 1
	127	#define SI_PCIDOWN 2
	128	#define SI_PCIUP 3
	129
	130	/*
	131	* Data structure to export all chip specific common variables
	132	* public (read-only) portion of aiutils handle returned by si_attach()
	133	*/
	134	struct si_pub {
5b435de0 AS	135	int ccrev; /* chip common core rev */
5b435de0 AS	136	u32 cccaps; /* chip common capabilities */
5b435de0 AS	137	int pmurev; /* pmu core rev */
	138	u32 pmucaps; /* pmu capabilities */
	139	uint boardtype; /* board type */
	140	uint boardvendor; /* board vendor */
5b435de0 AS	141	uint chip; /* chip number */
	142	uint chiprev; /* chip revision */
	143	uint chippkg; /* chip package option */
5b435de0 AS	144	};
	145
	146	struct pci_dev;
	147
	148	struct gpioh_item {
	149	void *arg;
	150	bool level;
	151	void (handler) (u32 stat, void arg);
	152	u32 event;
	153	struct gpioh_item *next;
	154	};
	155
	156	/* misc si info needed by some of the routines */
	157	struct si_info {
	158	struct si_pub pub; /* back plane public state (must be first) */
28a53442	159	struct bcma_bus icbus; / handle to soc interconnect bus */
cbc80db2	160	struct pci_dev pcibus; / handle to pci bus */
5b435de0	161
2e397c30	162	u32 chipst; /* chip status */
5b435de0 AS	163	};
	164
	165	/*
	166	* Many of the routines below take an 'sih' handle as their first arg.
	167	* Allocate this by calling si_attach(). Free it by calling si_detach().
	168	* At any one time, the sih is logically focused on one particular si core
	169	* (the "current core").
	170	* Use si_setcore() or si_setcoreidx() to change the association to another core
	171	*/
	172
	173
	174	/* AMBA Interconnect exported externs */
9bd91f3c	175	u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
5b435de0 AS	176
5b435de0 AS	177	/* === exported functions === */
9bd91f3c JP	178	struct si_pub ai_attach(struct bcma_bus pbus);
	179	void ai_detach(struct si_pub *sih);
	180	uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
	181	void ai_clkctl_init(struct si_pub *sih);
	182	u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
	183	bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
	184	bool ai_deviceremoved(struct si_pub *sih);
5b435de0	185
5b435de0	186	/* Enable Ex-PA for 4313 */
9bd91f3c	187	void ai_epa_4313war(struct si_pub *sih);
5b435de0	188
b2ffec46 AS	189	static inline u32 ai_get_cccaps(struct si_pub *sih)
	190	{
	191	return sih->cccaps;
	192	}
e922602e	193
b2ffec46 AS	194	static inline int ai_get_pmurev(struct si_pub *sih)
	195	{
	196	return sih->pmurev;
	197	}
e922602e	198
b2ffec46 AS	199	static inline u32 ai_get_pmucaps(struct si_pub *sih)
	200	{
	201	return sih->pmucaps;
	202	}
e922602e	203
b2ffec46 AS	204	static inline uint ai_get_boardtype(struct si_pub *sih)
	205	{
	206	return sih->boardtype;
	207	}
e922602e	208
b2ffec46 AS	209	static inline uint ai_get_boardvendor(struct si_pub *sih)
	210	{
	211	return sih->boardvendor;
	212	}
e922602e	213
b2ffec46 AS	214	static inline uint ai_get_chip_id(struct si_pub *sih)
	215	{
	216	return sih->chip;
	217	}
e922602e	218
b2ffec46 AS	219	static inline uint ai_get_chiprev(struct si_pub *sih)
	220	{
	221	return sih->chiprev;
	222	}
e922602e	223
b2ffec46 AS	224	static inline uint ai_get_chippkg(struct si_pub *sih)
	225	{
	226	return sih->chippkg;
	227	}
	228
5b435de0	229	#endif /* _BRCM_AIUTILS_H_ */