[deliverable/linux.git] / drivers / net / wireless / brcm80211 / brcmsmac / pmu.c

/*
 * Copyright (c) 2011 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/delay.h>
#include <linux/io.h>

#include <brcm_hw_ids.h>
#include <chipcommon.h>
#include <brcmu_utils.h>
#include "pub.h"
#include "aiutils.h"
#include "pmu.h"
#include "soc.h"

/*
 * external LPO crystal frequency
 */
#define EXT_ILP_HZ 32768

/*
 * Duration for ILP clock frequency measurment in milliseconds
 *
 * remark: 1000 must be an integer multiple of this duration
 */
#define ILP_CALC_DUR	10

/* Fields in pmucontrol */
#define	PCTL_ILP_DIV_MASK	0xffff0000
#define	PCTL_ILP_DIV_SHIFT	16
#define PCTL_PLL_PLLCTL_UPD	0x00000400	/* rev 2 */
#define PCTL_NOILP_ON_WAIT	0x00000200	/* rev 1 */
#define	PCTL_HT_REQ_EN		0x00000100
#define	PCTL_ALP_REQ_EN		0x00000080
#define	PCTL_XTALFREQ_MASK	0x0000007c
#define	PCTL_XTALFREQ_SHIFT	2
#define	PCTL_ILP_DIV_EN		0x00000002
#define	PCTL_LPO_SEL		0x00000001

/* ILP clock */
#define	ILP_CLOCK		32000

/* ALP clock on pre-PMU chips */
#define	ALP_CLOCK		20000000

/* pmustatus */
#define PST_EXTLPOAVAIL	0x0100
#define PST_WDRESET	0x0080
#define	PST_INTPEND	0x0040
#define	PST_SBCLKST	0x0030
#define	PST_SBCLKST_ILP	0x0010
#define	PST_SBCLKST_ALP	0x0020
#define	PST_SBCLKST_HT	0x0030
#define	PST_ALPAVAIL	0x0008
#define	PST_HTAVAIL	0x0004
#define	PST_RESINIT	0x0003

/* PMU resource bit position */
#define PMURES_BIT(bit)	(1 << (bit))

/* PMU corerev and chip specific PLL controls.
 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
 * number to differentiate different PLLs controlled by the same PMU rev.
 */

/* pmu XtalFreqRatio */
#define	PMU_XTALFREQ_REG_ILPCTR_MASK	0x00001FFF
#define	PMU_XTALFREQ_REG_MEASURE_MASK	0x80000000
#define	PMU_XTALFREQ_REG_MEASURE_SHIFT	31

/* 4313 resources */
#define	RES4313_BB_PU_RSRC		0
#define	RES4313_ILP_REQ_RSRC		1
#define	RES4313_XTAL_PU_RSRC		2
#define	RES4313_ALP_AVAIL_RSRC		3
#define	RES4313_RADIO_PU_RSRC		4
#define	RES4313_BG_PU_RSRC		5
#define	RES4313_VREG1P4_PU_RSRC		6
#define	RES4313_AFE_PWRSW_RSRC		7
#define	RES4313_RX_PWRSW_RSRC		8
#define	RES4313_TX_PWRSW_RSRC		9
#define	RES4313_BB_PWRSW_RSRC		10
#define	RES4313_SYNTH_PWRSW_RSRC	11
#define	RES4313_MISC_PWRSW_RSRC		12
#define	RES4313_BB_PLL_PWRSW_RSRC	13
#define	RES4313_HT_AVAIL_RSRC		14
#define	RES4313_MACPHY_CLK_AVAIL_RSRC	15

u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
{
	uint delay = PMU_MAX_TRANSITION_DLY;

	switch (ai_get_chip_id(sih)) {
	case BCMA_CHIP_ID_BCM43224:
	case BCMA_CHIP_ID_BCM43225:
	case BCMA_CHIP_ID_BCM4313:
		delay = 3700;
		break;
	default:
		break;
	}

	return (u16) delay;
}

/* Read/write a chipcontrol reg */
u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_addr), ~0, reg);
	return ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_data),
			 mask, val);
}

/* Read/write a regcontrol reg */
u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_addr), ~0, reg);
	return ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_data),
			 mask, val);
}

/* Read/write a pllcontrol reg */
u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_addr), ~0, reg);
	return ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_data),
			 mask, val);
}

/* PMU PLL update */
void si_pmu_pllupd(struct si_pub *sih)
{
	ai_cc_reg(sih, offsetof(struct chipcregs, pmucontrol),
		  PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
}

/* query alp/xtal clock frequency */
u32 si_pmu_alp_clock(struct si_pub *sih)
{
	u32 clock = ALP_CLOCK;

	/* bail out with default */
	if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
		return clock;

	switch (ai_get_chip_id(sih)) {
	case BCMA_CHIP_ID_BCM43224:
	case BCMA_CHIP_ID_BCM43225:
	case BCMA_CHIP_ID_BCM4313:
		/* always 20Mhz */
		clock = 20000 * 1000;
		break;
	default:
		break;
	}

	return clock;
}

u32 si_pmu_measure_alpclk(struct si_pub *sih)
{
	struct si_info *sii = container_of(sih, struct si_info, pub);
	struct bcma_device *core;
	u32 alp_khz;

	if (ai_get_pmurev(sih) < 10)
		return 0;

	/* Remember original core before switch to chipc */
	core = sii->icbus->drv_cc.core;

	if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
		u32 ilp_ctr, alp_hz;

		/*
		 * Enable the reg to measure the freq,
		 * in case it was disabled before
		 */
		bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
			    1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);

		/* Delay for well over 4 ILP clocks */
		udelay(1000);

		/* Read the latched number of ALP ticks per 4 ILP ticks */
		ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
			  PMU_XTALFREQ_REG_ILPCTR_MASK;

		/*
		 * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
		 * bit to save power
		 */
		bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);

		/* Calculate ALP frequency */
		alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;

		/*
		 * Round to nearest 100KHz, and at
		 * the same time convert to KHz
		 */
		alp_khz = (alp_hz + 50000) / 100000 * 100;
	} else
		alp_khz = 0;

	return alp_khz;
}
Commit	Line	Data
5b435de0 AS	1	/*
	2	* Copyright (c) 2011 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/delay.h>
	18	#include <linux/io.h>
	19
	20	#include <brcm_hw_ids.h>
	21	#include <chipcommon.h>
	22	#include <brcmu_utils.h>
	23	#include "pub.h"
	24	#include "aiutils.h"
	25	#include "pmu.h"
23038214	26	#include "soc.h"
5b435de0 AS	27
	28	/*
	29	* external LPO crystal frequency
	30	*/
	31	#define EXT_ILP_HZ 32768
	32
	33	/*
	34	* Duration for ILP clock frequency measurment in milliseconds
	35	*
	36	* remark: 1000 must be an integer multiple of this duration
	37	*/
	38	#define ILP_CALC_DUR 10
	39
	40	/* Fields in pmucontrol */
	41	#define PCTL_ILP_DIV_MASK 0xffff0000
	42	#define PCTL_ILP_DIV_SHIFT 16
	43	#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
	44	#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
	45	#define PCTL_HT_REQ_EN 0x00000100
	46	#define PCTL_ALP_REQ_EN 0x00000080
	47	#define PCTL_XTALFREQ_MASK 0x0000007c
	48	#define PCTL_XTALFREQ_SHIFT 2
	49	#define PCTL_ILP_DIV_EN 0x00000002
	50	#define PCTL_LPO_SEL 0x00000001
	51
	52	/* ILP clock */
	53	#define ILP_CLOCK 32000
	54
	55	/* ALP clock on pre-PMU chips */
	56	#define ALP_CLOCK 20000000
	57
	58	/* pmustatus */
	59	#define PST_EXTLPOAVAIL 0x0100
	60	#define PST_WDRESET 0x0080
	61	#define PST_INTPEND 0x0040
	62	#define PST_SBCLKST 0x0030
	63	#define PST_SBCLKST_ILP 0x0010
	64	#define PST_SBCLKST_ALP 0x0020
	65	#define PST_SBCLKST_HT 0x0030
	66	#define PST_ALPAVAIL 0x0008
	67	#define PST_HTAVAIL 0x0004
	68	#define PST_RESINIT 0x0003
	69
	70	/* PMU resource bit position */
	71	#define PMURES_BIT(bit) (1 << (bit))
	72
	73	/* PMU corerev and chip specific PLL controls.
	74	* PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
	75	* number to differentiate different PLLs controlled by the same PMU rev.
	76	*/
5b435de0 AS	77
	78	/* pmu XtalFreqRatio */
	79	#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
	80	#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
	81	#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
	82
	83	/* 4313 resources */
	84	#define RES4313_BB_PU_RSRC 0
	85	#define RES4313_ILP_REQ_RSRC 1
	86	#define RES4313_XTAL_PU_RSRC 2
	87	#define RES4313_ALP_AVAIL_RSRC 3
	88	#define RES4313_RADIO_PU_RSRC 4
	89	#define RES4313_BG_PU_RSRC 5
	90	#define RES4313_VREG1P4_PU_RSRC 6
	91	#define RES4313_AFE_PWRSW_RSRC 7
	92	#define RES4313_RX_PWRSW_RSRC 8
	93	#define RES4313_TX_PWRSW_RSRC 9
	94	#define RES4313_BB_PWRSW_RSRC 10
	95	#define RES4313_SYNTH_PWRSW_RSRC 11
	96	#define RES4313_MISC_PWRSW_RSRC 12
	97	#define RES4313_BB_PLL_PWRSW_RSRC 13
	98	#define RES4313_HT_AVAIL_RSRC 14
	99	#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
	100
5b435de0 AS	101	u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
	102	{
	103	uint delay = PMU_MAX_TRANSITION_DLY;
	104
b2ffec46	105	switch (ai_get_chip_id(sih)) {
1ef1a57d HM	106	case BCMA_CHIP_ID_BCM43224:
	107	case BCMA_CHIP_ID_BCM43225:
	108	case BCMA_CHIP_ID_BCM4313:
5b435de0 AS	109	delay = 3700;
	110	break;
	111	default:
	112	break;
	113	}
	114
	115	return (u16) delay;
	116	}
	117
5b435de0 AS	118	/* Read/write a chipcontrol reg */
	119	u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
	120	{
7d8e18e4 AS	121	ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_addr), ~0, reg);
	122	return ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_data),
	123	mask, val);
5b435de0 AS	124	}
	125
	126	/* Read/write a regcontrol reg */
	127	u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
	128	{
7d8e18e4 AS	129	ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_addr), ~0, reg);
	130	return ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_data),
	131	mask, val);
5b435de0 AS	132	}
	133
	134	/* Read/write a pllcontrol reg */
	135	u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
	136	{
7d8e18e4 AS	137	ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_addr), ~0, reg);
	138	return ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_data),
	139	mask, val);
5b435de0 AS	140	}
	141
	142	/* PMU PLL update */
	143	void si_pmu_pllupd(struct si_pub *sih)
	144	{
7d8e18e4 AS	145	ai_cc_reg(sih, offsetof(struct chipcregs, pmucontrol),
7d8e18e4 AS	146	PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
5b435de0 AS	147	}
	148
	149	/* query alp/xtal clock frequency */
	150	u32 si_pmu_alp_clock(struct si_pub *sih)
	151	{
	152	u32 clock = ALP_CLOCK;
	153
	154	/* bail out with default */
b2ffec46	155	if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
5b435de0 AS	156	return clock;
5b435de0 AS	157
b2ffec46	158	switch (ai_get_chip_id(sih)) {
1ef1a57d HM	159	case BCMA_CHIP_ID_BCM43224:
	160	case BCMA_CHIP_ID_BCM43225:
	161	case BCMA_CHIP_ID_BCM4313:
5b435de0 AS	162	/* always 20Mhz */
	163	clock = 20000 * 1000;
	164	break;
	165	default:
	166	break;
	167	}
	168
	169	return clock;
	170	}
	171
5b435de0 AS	172	u32 si_pmu_measure_alpclk(struct si_pub *sih)
5b435de0 AS	173	{
40bd94ce	174	struct si_info *sii = container_of(sih, struct si_info, pub);
8d30b708	175	struct bcma_device *core;
5b435de0 AS	176	u32 alp_khz;
5b435de0 AS	177
b2ffec46	178	if (ai_get_pmurev(sih) < 10)
5b435de0 AS	179	return 0;
	180
	181	/* Remember original core before switch to chipc */
40bd94ce	182	core = sii->icbus->drv_cc.core;
5b435de0	183
8d30b708	184	if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
5b435de0 AS	185	u32 ilp_ctr, alp_hz;
	186
	187	/*
	188	* Enable the reg to measure the freq,
	189	* in case it was disabled before
	190	*/
8d30b708 AS	191	bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
8d30b708 AS	192	1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
5b435de0 AS	193
	194	/* Delay for well over 4 ILP clocks */
	195	udelay(1000);
	196
	197	/* Read the latched number of ALP ticks per 4 ILP ticks */
8d30b708 AS	198	ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
8d30b708 AS	199	PMU_XTALFREQ_REG_ILPCTR_MASK;
5b435de0 AS	200
	201	/*
	202	* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
	203	* bit to save power
	204	*/
8d30b708	205	bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
5b435de0 AS	206
	207	/* Calculate ALP frequency */
	208	alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
	209
	210	/*
	211	* Round to nearest 100KHz, and at
	212	* the same time convert to KHz
	213	*/
	214	alp_khz = (alp_hz + 50000) / 100000 * 100;
	215	} else
	216	alp_khz = 0;
	217
5b435de0 AS	218	return alp_khz;
5b435de0 AS	219	}