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brcmfmac: Add support for the BCM4359 11ac RSDB PCIE device.
[deliverable/linux.git] / drivers / net / wireless / broadcom / brcm80211 / brcmfmac / pcie.c
CommitLineData
9e37f045
HM		 1/* Copyright (c) 2014 Broadcom Corporation
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/firmware.h>
19#include <linux/pci.h>
20#include <linux/vmalloc.h>
21#include <linux/delay.h>
9e37f045
HM		 22#include <linux/interrupt.h>
23#include <linux/bcma/bcma.h>
24#include <linux/sched.h>
a1d69c60 25#include <asm/unaligned.h>
9e37f045
HM		 26
27#include <soc.h>
28#include <chipcommon.h>
29#include <brcmu_utils.h>
30#include <brcmu_wifi.h>
31#include <brcm_hw_ids.h>
32
a8e8ed34 33#include "debug.h"
d14f78b9 34#include "bus.h"
9e37f045
HM		 35#include "commonring.h"
36#include "msgbuf.h"
37#include "pcie.h"
38#include "firmware.h"
39#include "chip.h"
40
41
42enum brcmf_pcie_state {
43 BRCMFMAC_PCIE_STATE_DOWN,
44 BRCMFMAC_PCIE_STATE_UP
45};
46
47
48#define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin"
49#define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt"
e3c92cb2
HM		 50#define BRCMF_PCIE_4350_FW_NAME "brcm/brcmfmac4350-pcie.bin"
51#define BRCMF_PCIE_4350_NVRAM_NAME "brcm/brcmfmac4350-pcie.txt"
9e37f045
HM		 52#define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin"
53#define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt"
54#define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin"
55#define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt"
67f3b6a3
AS		 56#define BRCMF_PCIE_4358_FW_NAME "brcm/brcmfmac4358-pcie.bin"
57#define BRCMF_PCIE_4358_NVRAM_NAME "brcm/brcmfmac4358-pcie.txt"
2aff0303
HM		 58#define BRCMF_PCIE_4359_FW_NAME "brcm/brcmfmac4359-pcie.bin"
59#define BRCMF_PCIE_4359_NVRAM_NAME "brcm/brcmfmac4359-pcie.txt"
55acca90
HM		 60#define BRCMF_PCIE_4365_FW_NAME "brcm/brcmfmac4365b-pcie.bin"
61#define BRCMF_PCIE_4365_NVRAM_NAME "brcm/brcmfmac4365b-pcie.txt"
62#define BRCMF_PCIE_4366_FW_NAME "brcm/brcmfmac4366b-pcie.bin"
63#define BRCMF_PCIE_4366_NVRAM_NAME "brcm/brcmfmac4366b-pcie.txt"
f8273baf
EC		 64#define BRCMF_PCIE_4371_FW_NAME "brcm/brcmfmac4371-pcie.bin"
65#define BRCMF_PCIE_4371_NVRAM_NAME "brcm/brcmfmac4371-pcie.txt"
9e37f045
HM		 66
67#define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */
68
69#define BRCMF_PCIE_TCM_MAP_SIZE (4096 * 1024)
70#define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
71
72/* backplane addres space accessed by BAR0 */
73#define BRCMF_PCIE_BAR0_WINDOW 0x80
74#define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
75#define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
76
77#define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
78#define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
79
80#define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
81#define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
82
83#define BRCMF_PCIE_REG_INTSTATUS 0x90
84#define BRCMF_PCIE_REG_INTMASK 0x94
85#define BRCMF_PCIE_REG_SBMBX 0x98
86
07fe2e38
HM		 87#define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC
88
9e37f045
HM		 89#define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
90#define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
91#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
92#define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
93#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
94#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
95
96#define BRCMF_PCIE_GENREV1 1
97#define BRCMF_PCIE_GENREV2 2
98
99#define BRCMF_PCIE2_INTA 0x01
100#define BRCMF_PCIE2_INTB 0x02
101
102#define BRCMF_PCIE_INT_0 0x01
103#define BRCMF_PCIE_INT_1 0x02
104#define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
105 BRCMF_PCIE_INT_1)
106
107#define BRCMF_PCIE_MB_INT_FN0_0 0x0100
108#define BRCMF_PCIE_MB_INT_FN0_1 0x0200
109#define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
110#define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
111#define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
112#define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
113#define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
114#define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
115#define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
116#define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
117
118#define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
119 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
120 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
121 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
122 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
123 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
124 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
125 BRCMF_PCIE_MB_INT_D2H3_DB1)
126
fd5e8cb8 127#define BRCMF_PCIE_MIN_SHARED_VERSION 5
9e37f045
HM		 128#define BRCMF_PCIE_MAX_SHARED_VERSION 5
129#define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
f3550aeb
FL		 130#define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
131#define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
9e37f045
HM		 132
133#define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
134#define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
135
136#define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
137#define BRCMF_SHARED_RING_BASE_OFFSET 52
138#define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
139#define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
140#define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
141#define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
142#define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
143#define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
144#define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
145#define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
146#define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
147
148#define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
149#define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
150#define BRCMF_RING_H2D_RING_MEM_OFFSET 4
151#define BRCMF_RING_H2D_RING_STATE_OFFSET 8
152
153#define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
154#define BRCMF_RING_MAX_ITEM_OFFSET 4
155#define BRCMF_RING_LEN_ITEMS_OFFSET 6
156#define BRCMF_RING_MEM_SZ 16
157#define BRCMF_RING_STATE_SZ 8
158
159#define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4
160#define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
161#define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
162#define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
f3550aeb
FL		 163#define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET 20
164#define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET 28
165#define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET 36
166#define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET 44
9e37f045
HM		 167#define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
168#define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
169
170#define BRCMF_DEF_MAX_RXBUFPOST 255
171
172#define BRCMF_CONSOLE_BUFADDR_OFFSET 8
173#define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
174#define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
175
176#define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
177#define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
178
179#define BRCMF_D2H_DEV_D3_ACK 0x00000001
180#define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
181#define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
182
183#define BRCMF_H2D_HOST_D3_INFORM 0x00000001
184#define BRCMF_H2D_HOST_DS_ACK 0x00000002
4eb3af7c
HM		 185#define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
186#define BRCMF_H2D_HOST_D0_INFORM 0x00000010
9e37f045
HM		 187
188#define BRCMF_PCIE_MBDATA_TIMEOUT 2000
189
bd4f82e3
HM		 190#define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
191#define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
192#define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
193#define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
194#define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
195#define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
196#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
197#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
198#define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
199#define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
200#define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
201#define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
202#define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
203
9e37f045
HM		 204
205MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
206MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
e3c92cb2
HM		 207MODULE_FIRMWARE(BRCMF_PCIE_4350_FW_NAME);
208MODULE_FIRMWARE(BRCMF_PCIE_4350_NVRAM_NAME);
7fca40eb
AS		 209MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME);
210MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME);
9e37f045
HM		 211MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
212MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
67f3b6a3
AS		 213MODULE_FIRMWARE(BRCMF_PCIE_4358_FW_NAME);
214MODULE_FIRMWARE(BRCMF_PCIE_4358_NVRAM_NAME);
2aff0303
HM		 215MODULE_FIRMWARE(BRCMF_PCIE_4359_FW_NAME);
216MODULE_FIRMWARE(BRCMF_PCIE_4359_NVRAM_NAME);
55acca90
HM		 217MODULE_FIRMWARE(BRCMF_PCIE_4365_FW_NAME);
218MODULE_FIRMWARE(BRCMF_PCIE_4365_NVRAM_NAME);
219MODULE_FIRMWARE(BRCMF_PCIE_4366_FW_NAME);
220MODULE_FIRMWARE(BRCMF_PCIE_4366_NVRAM_NAME);
f8273baf
EC		 221MODULE_FIRMWARE(BRCMF_PCIE_4371_FW_NAME);
222MODULE_FIRMWARE(BRCMF_PCIE_4371_NVRAM_NAME);
9e37f045
HM		 223
224
225struct brcmf_pcie_console {
226 u32 base_addr;
227 u32 buf_addr;
228 u32 bufsize;
229 u32 read_idx;
230 u8 log_str[256];
231 u8 log_idx;
232};
233
234struct brcmf_pcie_shared_info {
235 u32 tcm_base_address;
236 u32 flags;
237 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
238 struct brcmf_pcie_ringbuf *flowrings;
239 u16 max_rxbufpost;
240 u32 nrof_flowrings;
241 u32 rx_dataoffset;
242 u32 htod_mb_data_addr;
243 u32 dtoh_mb_data_addr;
244 u32 ring_info_addr;
245 struct brcmf_pcie_console console;
246 void *scratch;
247 dma_addr_t scratch_dmahandle;
248 void *ringupd;
249 dma_addr_t ringupd_dmahandle;
250};
251
252struct brcmf_pcie_core_info {
253 u32 base;
254 u32 wrapbase;
255};
256
257struct brcmf_pciedev_info {
258 enum brcmf_pcie_state state;
259 bool in_irq;
260 bool irq_requested;
261 struct pci_dev *pdev;
262 char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
263 char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
264 void __iomem *regs;
265 void __iomem *tcm;
266 u32 tcm_size;
267 u32 ram_base;
268 u32 ram_size;
269 struct brcmf_chip *ci;
270 u32 coreid;
271 u32 generic_corerev;
272 struct brcmf_pcie_shared_info shared;
273 void (*ringbell)(struct brcmf_pciedev_info *devinfo);
274 wait_queue_head_t mbdata_resp_wait;
275 bool mbdata_completed;
276 bool irq_allocated;
4eb3af7c 277 bool wowl_enabled;
f3550aeb
FL		 278 u8 dma_idx_sz;
279 void *idxbuf;
280 u32 idxbuf_sz;
281 dma_addr_t idxbuf_dmahandle;
282 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
283 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
284 u16 value);
9e37f045
HM		 285};
286
287struct brcmf_pcie_ringbuf {
288 struct brcmf_commonring commonring;
289 dma_addr_t dma_handle;
290 u32 w_idx_addr;
291 u32 r_idx_addr;
292 struct brcmf_pciedev_info *devinfo;
293 u8 id;
294};
295
296
297static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
298 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
299 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
300 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
301 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
302 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
303};
304
305static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
306 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
307 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
308 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
309 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
310 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
311};
312
313
9e37f045
HM		 314static u32
315brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
316{
317 void __iomem *address = devinfo->regs + reg_offset;
318
319 return (ioread32(address));
320}
321
322
323static void
324brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
325 u32 value)
326{
327 void __iomem *address = devinfo->regs + reg_offset;
328
329 iowrite32(value, address);
330}
331
332
333static u8
334brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
335{
336 void __iomem *address = devinfo->tcm + mem_offset;
337
338 return (ioread8(address));
339}
340
341
342static u16
343brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
344{
345 void __iomem *address = devinfo->tcm + mem_offset;
346
347 return (ioread16(address));
348}
349
350
351static void
352brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
353 u16 value)
354{
355 void __iomem *address = devinfo->tcm + mem_offset;
356
357 iowrite16(value, address);
358}
359
360
f3550aeb
FL		 361static u16
362brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
363{
364 u16 *address = devinfo->idxbuf + mem_offset;
365
366 return (*(address));
367}
368
369
370static void
371brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
372 u16 value)
373{
374 u16 *address = devinfo->idxbuf + mem_offset;
375
376 *(address) = value;
377}
378
379
9e37f045
HM		 380static u32
381brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
382{
383 void __iomem *address = devinfo->tcm + mem_offset;
384
385 return (ioread32(address));
386}
387
388
389static void
390brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
391 u32 value)
392{
393 void __iomem *address = devinfo->tcm + mem_offset;
394
395 iowrite32(value, address);
396}
397
398
399static u32
400brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
401{
402 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
403
404 return (ioread32(addr));
405}
406
407
408static void
409brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
410 u32 value)
411{
412 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
413
414 iowrite32(value, addr);
415}
416
417
418static void
419brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
420 void *srcaddr, u32 len)
421{
422 void __iomem *address = devinfo->tcm + mem_offset;
423 __le32 *src32;
424 __le16 *src16;
425 u8 *src8;
426
427 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
428 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
429 src8 = (u8 *)srcaddr;
430 while (len) {
431 iowrite8(*src8, address);
432 address++;
433 src8++;
434 len--;
435 }
436 } else {
437 len = len / 2;
438 src16 = (__le16 *)srcaddr;
439 while (len) {
440 iowrite16(le16_to_cpu(*src16), address);
441 address += 2;
442 src16++;
443 len--;
444 }
445 }
446 } else {
447 len = len / 4;
448 src32 = (__le32 *)srcaddr;
449 while (len) {
450 iowrite32(le32_to_cpu(*src32), address);
451 address += 4;
452 src32++;
453 len--;
454 }
455 }
456}
457
458
ff4445a8
AS		 459static void
460brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
461 void *dstaddr, u32 len)
462{
463 void __iomem *address = devinfo->tcm + mem_offset;
464 __le32 *dst32;
465 __le16 *dst16;
466 u8 *dst8;
467
468 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
469 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
470 dst8 = (u8 *)dstaddr;
471 while (len) {
472 *dst8 = ioread8(address);
473 address++;
474 dst8++;
475 len--;
476 }
477 } else {
478 len = len / 2;
479 dst16 = (__le16 *)dstaddr;
480 while (len) {
481 *dst16 = cpu_to_le16(ioread16(address));
482 address += 2;
483 dst16++;
484 len--;
485 }
486 }
487 } else {
488 len = len / 4;
489 dst32 = (__le32 *)dstaddr;
490 while (len) {
491 *dst32 = cpu_to_le32(ioread32(address));
492 address += 4;
493 dst32++;
494 len--;
495 }
496 }
497}
498
499
9e37f045
HM		 500#define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
501 CHIPCREGOFFS(reg), value)
502
503
504static void
505brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
506{
507 const struct pci_dev *pdev = devinfo->pdev;
508 struct brcmf_core *core;
509 u32 bar0_win;
510
511 core = brcmf_chip_get_core(devinfo->ci, coreid);
512 if (core) {
513 bar0_win = core->base;
514 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
515 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
516 &bar0_win) == 0) {
517 if (bar0_win != core->base) {
518 bar0_win = core->base;
519 pci_write_config_dword(pdev,
520 BRCMF_PCIE_BAR0_WINDOW,
521 bar0_win);
522 }
523 }
524 } else {
525 brcmf_err("Unsupported core selected %x\n", coreid);
526 }
527}
528
529
bd4f82e3 530static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
9e37f045 531{
07fe2e38 532 struct brcmf_core *core;
bd4f82e3
HM		 533 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
534 BRCMF_PCIE_CFGREG_PM_CSR,
535 BRCMF_PCIE_CFGREG_MSI_CAP,
536 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
537 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
538 BRCMF_PCIE_CFGREG_MSI_DATA,
539 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
540 BRCMF_PCIE_CFGREG_RBAR_CTRL,
541 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
542 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
543 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
9e37f045
HM		 544 u32 i;
545 u32 val;
bd4f82e3 546 u32 lsc;
9e37f045
HM		 547
548 if (!devinfo->ci)
549 return;
550
07fe2e38 551 /* Disable ASPM */
bd4f82e3 552 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
07fe2e38
HM		 553 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
554 &lsc);
bd4f82e3 555 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
07fe2e38
HM		 556 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
557 val);
9e37f045 558
07fe2e38 559 /* Watchdog reset */
bd4f82e3
HM		 560 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
561 WRITECC32(devinfo, watchdog, 4);
9e37f045
HM		 562 msleep(100);
563
07fe2e38 564 /* Restore ASPM */
bd4f82e3 565 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
07fe2e38
HM		 566 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
567 lsc);
568
569 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
570 if (core->rev <= 13) {
571 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
572 brcmf_pcie_write_reg32(devinfo,
573 BRCMF_PCIE_PCIE2REG_CONFIGADDR,
574 cfg_offset[i]);
575 val = brcmf_pcie_read_reg32(devinfo,
576 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
577 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
578 cfg_offset[i], val);
579 brcmf_pcie_write_reg32(devinfo,
580 BRCMF_PCIE_PCIE2REG_CONFIGDATA,
581 val);
582 }
9e37f045
HM		 583 }
584}
585
586
587static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
588{
589 u32 config;
590
591 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
9e37f045
HM		 592 /* BAR1 window may not be sized properly */
593 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
594 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
595 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
596 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
597
598 device_wakeup_enable(&devinfo->pdev->dev);
599}
600
601
602static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
603{
9e37f045
HM		 604 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
605 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
606 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
607 5);
608 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
609 0);
610 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
611 7);
612 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
613 0);
614 }
615 return 0;
616}
617
618
619static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
620 u32 resetintr)
621{
622 struct brcmf_core *core;
623
624 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
625 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
626 brcmf_chip_resetcore(core, 0, 0, 0);
627 }
628
d380ebc9 629 return !brcmf_chip_set_active(devinfo->ci, resetintr);
9e37f045
HM		 630}
631
632
4eb3af7c 633static int
9e37f045
HM		 634brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
635{
636 struct brcmf_pcie_shared_info *shared;
637 u32 addr;
638 u32 cur_htod_mb_data;
639 u32 i;
640
641 shared = &devinfo->shared;
642 addr = shared->htod_mb_data_addr;
643 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
644
645 if (cur_htod_mb_data != 0)
646 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
647 cur_htod_mb_data);
648
649 i = 0;
650 while (cur_htod_mb_data != 0) {
651 msleep(10);
652 i++;
653 if (i > 100)
4eb3af7c 654 return -EIO;
9e37f045
HM		 655 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
656 }
657
658 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
659 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
660 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
4eb3af7c
HM		 661
662 return 0;
9e37f045
HM		 663}
664
665
666static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
667{
668 struct brcmf_pcie_shared_info *shared;
669 u32 addr;
670 u32 dtoh_mb_data;
671
672 shared = &devinfo->shared;
673 addr = shared->dtoh_mb_data_addr;
674 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
675
676 if (!dtoh_mb_data)
677 return;
678
679 brcmf_pcie_write_tcm32(devinfo, addr, 0);
680
681 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
682 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
683 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
684 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
685 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
686 }
687 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
688 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
ebcc2f51 689 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
9e37f045
HM		 690 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
691 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
692 devinfo->mbdata_completed = true;
693 wake_up(&devinfo->mbdata_resp_wait);
694 }
ebcc2f51 695 }
9e37f045
HM		 696}
697
698
699static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
700{
701 struct brcmf_pcie_shared_info *shared;
702 struct brcmf_pcie_console *console;
703 u32 addr;
704
705 shared = &devinfo->shared;
706 console = &shared->console;
707 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
708 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
709
710 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
711 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
712 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
713 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
714
9d6c1dc4 715 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
9e37f045
HM		 716 console->base_addr, console->buf_addr, console->bufsize);
717}
718
719
720static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
721{
722 struct brcmf_pcie_console *console;
723 u32 addr;
724 u8 ch;
725 u32 newidx;
726
9d6c1dc4
AS		 727 if (!BRCMF_FWCON_ON())
728 return;
729
9e37f045
HM		 730 console = &devinfo->shared.console;
731 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
732 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
733 while (newidx != console->read_idx) {
734 addr = console->buf_addr + console->read_idx;
735 ch = brcmf_pcie_read_tcm8(devinfo, addr);
736 console->read_idx++;
737 if (console->read_idx == console->bufsize)
738 console->read_idx = 0;
739 if (ch == '\r')
740 continue;
741 console->log_str[console->log_idx] = ch;
742 console->log_idx++;
743 if ((ch != '\n') &&
744 (console->log_idx == (sizeof(console->log_str) - 2))) {
745 ch = '\n';
746 console->log_str[console->log_idx] = ch;
747 console->log_idx++;
748 }
9e37f045
HM		 749 if (ch == '\n') {
750 console->log_str[console->log_idx] = 0;
9d6c1dc4 751 pr_debug("CONSOLE: %s", console->log_str);
9e37f045
HM		 752 console->log_idx = 0;
753 }
754 }
755}
756
757
758static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
759{
760 u32 reg_value;
761
762 brcmf_dbg(PCIE, "RING !\n");
763 reg_value = brcmf_pcie_read_reg32(devinfo,
764 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
765 reg_value |= BRCMF_PCIE2_INTB;
766 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
767 reg_value);
768}
769
770
771static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
772{
773 brcmf_dbg(PCIE, "RING !\n");
774 /* Any arbitrary value will do, lets use 1 */
775 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
776}
777
778
779static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
780{
781 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
782 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
783 0);
784 else
785 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
786 0);
787}
788
789
790static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
791{
792 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
793 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
794 BRCMF_PCIE_INT_DEF);
795 else
796 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
797 BRCMF_PCIE_MB_INT_D2H_DB |
798 BRCMF_PCIE_MB_INT_FN0_0 |
799 BRCMF_PCIE_MB_INT_FN0_1);
800}
801
802
803static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
804{
805 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
806 u32 status;
807
808 status = 0;
809 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
810 if (status) {
811 brcmf_pcie_intr_disable(devinfo);
812 brcmf_dbg(PCIE, "Enter\n");
813 return IRQ_WAKE_THREAD;
814 }
815 return IRQ_NONE;
816}
817
818
819static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
820{
821 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
822
823 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
824 brcmf_pcie_intr_disable(devinfo);
825 brcmf_dbg(PCIE, "Enter\n");
826 return IRQ_WAKE_THREAD;
827 }
828 return IRQ_NONE;
829}
830
831
832static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
833{
834 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
835 const struct pci_dev *pdev = devinfo->pdev;
836 u32 status;
837
838 devinfo->in_irq = true;
839 status = 0;
840 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
841 brcmf_dbg(PCIE, "Enter %x\n", status);
842 if (status) {
843 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
844 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
845 brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
846 }
847 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
848 brcmf_pcie_intr_enable(devinfo);
849 devinfo->in_irq = false;
850 return IRQ_HANDLED;
851}
852
853
854static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
855{
856 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
857 u32 status;
858
859 devinfo->in_irq = true;
860 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
861 brcmf_dbg(PCIE, "Enter %x\n", status);
862 if (status) {
863 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
864 status);
865 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
866 BRCMF_PCIE_MB_INT_FN0_1))
867 brcmf_pcie_handle_mb_data(devinfo);
868 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
869 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
870 brcmf_proto_msgbuf_rx_trigger(
871 &devinfo->pdev->dev);
872 }
873 }
874 brcmf_pcie_bus_console_read(devinfo);
875 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
876 brcmf_pcie_intr_enable(devinfo);
877 devinfo->in_irq = false;
878 return IRQ_HANDLED;
879}
880
881
882static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
883{
884 struct pci_dev *pdev;
885
886 pdev = devinfo->pdev;
887
888 brcmf_pcie_intr_disable(devinfo);
889
890 brcmf_dbg(PCIE, "Enter\n");
891 /* is it a v1 or v2 implementation */
892 devinfo->irq_requested = false;
e9efa340 893 pci_enable_msi(pdev);
9e37f045
HM		 894 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
895 if (request_threaded_irq(pdev->irq,
896 brcmf_pcie_quick_check_isr_v1,
897 brcmf_pcie_isr_thread_v1,
898 IRQF_SHARED, "brcmf_pcie_intr",
899 devinfo)) {
e9efa340 900 pci_disable_msi(pdev);
9e37f045
HM		 901 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
902 return -EIO;
903 }
904 } else {
905 if (request_threaded_irq(pdev->irq,
906 brcmf_pcie_quick_check_isr_v2,
907 brcmf_pcie_isr_thread_v2,
908 IRQF_SHARED, "brcmf_pcie_intr",
909 devinfo)) {
e9efa340 910 pci_disable_msi(pdev);
9e37f045
HM		 911 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
912 return -EIO;
913 }
914 }
915 devinfo->irq_requested = true;
916 devinfo->irq_allocated = true;
917 return 0;
918}
919
920
921static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
922{
923 struct pci_dev *pdev;
924 u32 status;
925 u32 count;
926
927 if (!devinfo->irq_allocated)
928 return;
929
930 pdev = devinfo->pdev;
931
932 brcmf_pcie_intr_disable(devinfo);
933 if (!devinfo->irq_requested)
934 return;
935 devinfo->irq_requested = false;
936 free_irq(pdev->irq, devinfo);
e9efa340 937 pci_disable_msi(pdev);
9e37f045
HM		 938
939 msleep(50);
940 count = 0;
941 while ((devinfo->in_irq) && (count < 20)) {
942 msleep(50);
943 count++;
944 }
945 if (devinfo->in_irq)
946 brcmf_err("Still in IRQ (processing) !!!\n");
947
948 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
949 status = 0;
950 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
951 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
952 } else {
953 status = brcmf_pcie_read_reg32(devinfo,
954 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
955 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
956 status);
957 }
958 devinfo->irq_allocated = false;
959}
960
961
962static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
963{
964 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
965 struct brcmf_pciedev_info *devinfo = ring->devinfo;
966 struct brcmf_commonring *commonring = &ring->commonring;
967
968 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
969 return -EIO;
970
971 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
972 commonring->w_ptr, ring->id);
973
f3550aeb 974 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
9e37f045
HM		 975
976 return 0;
977}
978
979
980static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
981{
982 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
983 struct brcmf_pciedev_info *devinfo = ring->devinfo;
984 struct brcmf_commonring *commonring = &ring->commonring;
985
986 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
987 return -EIO;
988
989 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
990 commonring->r_ptr, ring->id);
991
f3550aeb 992 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
9e37f045
HM		 993
994 return 0;
995}
996
997
998static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
999{
1000 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1001 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1002
1003 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1004 return -EIO;
1005
1006 devinfo->ringbell(devinfo);
1007
1008 return 0;
1009}
1010
1011
1012static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
1013{
1014 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1015 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1016 struct brcmf_commonring *commonring = &ring->commonring;
1017
1018 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1019 return -EIO;
1020
f3550aeb 1021 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
9e37f045
HM		 1022
1023 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1024 commonring->w_ptr, ring->id);
1025
1026 return 0;
1027}
1028
1029
1030static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1031{
1032 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1033 struct brcmf_pciedev_info *devinfo = ring->devinfo;
1034 struct brcmf_commonring *commonring = &ring->commonring;
1035
1036 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1037 return -EIO;
1038
f3550aeb 1039 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
9e37f045
HM		 1040
1041 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1042 commonring->r_ptr, ring->id);
1043
1044 return 0;
1045}
1046
1047
1048static void *
1049brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1050 u32 size, u32 tcm_dma_phys_addr,
1051 dma_addr_t *dma_handle)
1052{
1053 void *ring;
83297aaa 1054 u64 address;
9e37f045
HM		 1055
1056 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1057 GFP_KERNEL);
1058 if (!ring)
1059 return NULL;
1060
83297aaa 1061 address = (u64)*dma_handle;
9e37f045
HM		 1062 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1063 address & 0xffffffff);
1064 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1065
1066 memset(ring, 0, size);
1067
1068 return (ring);
1069}
1070
1071
1072static struct brcmf_pcie_ringbuf *
1073brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1074 u32 tcm_ring_phys_addr)
1075{
1076 void *dma_buf;
1077 dma_addr_t dma_handle;
1078 struct brcmf_pcie_ringbuf *ring;
1079 u32 size;
1080 u32 addr;
1081
1082 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1083 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1084 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1085 &dma_handle);
1086 if (!dma_buf)
1087 return NULL;
1088
1089 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1090 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1091 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1092 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1093
1094 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1095 if (!ring) {
1096 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1097 dma_handle);
1098 return NULL;
1099 }
1100 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1101 brcmf_ring_itemsize[ring_id], dma_buf);
1102 ring->dma_handle = dma_handle;
1103 ring->devinfo = devinfo;
1104 brcmf_commonring_register_cb(&ring->commonring,
1105 brcmf_pcie_ring_mb_ring_bell,
1106 brcmf_pcie_ring_mb_update_rptr,
1107 brcmf_pcie_ring_mb_update_wptr,
1108 brcmf_pcie_ring_mb_write_rptr,
1109 brcmf_pcie_ring_mb_write_wptr, ring);
1110
1111 return (ring);
1112}
1113
1114
1115static void brcmf_pcie_release_ringbuffer(struct device *dev,
1116 struct brcmf_pcie_ringbuf *ring)
1117{
1118 void *dma_buf;
1119 u32 size;
1120
1121 if (!ring)
1122 return;
1123
1124 dma_buf = ring->commonring.buf_addr;
1125 if (dma_buf) {
1126 size = ring->commonring.depth * ring->commonring.item_len;
1127 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1128 }
1129 kfree(ring);
1130}
1131
1132
1133static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1134{
1135 u32 i;
1136
1137 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1138 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1139 devinfo->shared.commonrings[i]);
1140 devinfo->shared.commonrings[i] = NULL;
1141 }
1142 kfree(devinfo->shared.flowrings);
1143 devinfo->shared.flowrings = NULL;
f3550aeb
FL		 1144 if (devinfo->idxbuf) {
1145 dma_free_coherent(&devinfo->pdev->dev,
1146 devinfo->idxbuf_sz,
1147 devinfo->idxbuf,
1148 devinfo->idxbuf_dmahandle);
1149 devinfo->idxbuf = NULL;
1150 }
9e37f045
HM		 1151}
1152
1153
1154static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1155{
1156 struct brcmf_pcie_ringbuf *ring;
1157 struct brcmf_pcie_ringbuf *rings;
1158 u32 ring_addr;
1159 u32 d2h_w_idx_ptr;
1160 u32 d2h_r_idx_ptr;
1161 u32 h2d_w_idx_ptr;
1162 u32 h2d_r_idx_ptr;
1163 u32 addr;
1164 u32 ring_mem_ptr;
1165 u32 i;
f3550aeb
FL		 1166 u64 address;
1167 u32 bufsz;
9e37f045 1168 u16 max_sub_queues;
f3550aeb 1169 u8 idx_offset;
9e37f045
HM		 1170
1171 ring_addr = devinfo->shared.ring_info_addr;
1172 brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
f3550aeb
FL		 1173 addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1174 max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1175
1176 if (devinfo->dma_idx_sz != 0) {
1177 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1178 devinfo->dma_idx_sz * 2;
1179 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1180 &devinfo->idxbuf_dmahandle,
1181 GFP_KERNEL);
1182 if (!devinfo->idxbuf)
1183 devinfo->dma_idx_sz = 0;
1184 }
9e37f045 1185
f3550aeb
FL		 1186 if (devinfo->dma_idx_sz == 0) {
1187 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1188 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1189 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1190 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1191 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1192 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1193 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1194 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1195 idx_offset = sizeof(u32);
1196 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1197 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1198 brcmf_dbg(PCIE, "Using TCM indices\n");
1199 } else {
1200 memset(devinfo->idxbuf, 0, bufsz);
1201 devinfo->idxbuf_sz = bufsz;
1202 idx_offset = devinfo->dma_idx_sz;
1203 devinfo->write_ptr = brcmf_pcie_write_idx;
1204 devinfo->read_ptr = brcmf_pcie_read_idx;
1205
1206 h2d_w_idx_ptr = 0;
1207 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1208 address = (u64)devinfo->idxbuf_dmahandle;
1209 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1210 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1211
1212 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1213 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1214 address += max_sub_queues * idx_offset;
1215 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1216 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1217
1218 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1219 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1220 address += max_sub_queues * idx_offset;
1221 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1222 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1223
1224 d2h_r_idx_ptr = d2h_w_idx_ptr +
1225 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1226 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1227 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1228 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1229 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1230 brcmf_dbg(PCIE, "Using host memory indices\n");
1231 }
9e37f045
HM		 1232
1233 addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1234 ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1235
1236 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1237 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1238 if (!ring)
1239 goto fail;
1240 ring->w_idx_addr = h2d_w_idx_ptr;
1241 ring->r_idx_addr = h2d_r_idx_ptr;
1242 ring->id = i;
1243 devinfo->shared.commonrings[i] = ring;
1244
f3550aeb
FL		 1245 h2d_w_idx_ptr += idx_offset;
1246 h2d_r_idx_ptr += idx_offset;
9e37f045
HM		 1247 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1248 }
1249
1250 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1251 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1252 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1253 if (!ring)
1254 goto fail;
1255 ring->w_idx_addr = d2h_w_idx_ptr;
1256 ring->r_idx_addr = d2h_r_idx_ptr;
1257 ring->id = i;
1258 devinfo->shared.commonrings[i] = ring;
1259
f3550aeb
FL		 1260 d2h_w_idx_ptr += idx_offset;
1261 d2h_r_idx_ptr += idx_offset;
9e37f045
HM		 1262 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1263 }
1264
9e37f045
HM		 1265 devinfo->shared.nrof_flowrings =
1266 max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1267 rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1268 GFP_KERNEL);
1269 if (!rings)
1270 goto fail;
1271
1272 brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1273 devinfo->shared.nrof_flowrings);
1274
1275 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1276 ring = &rings[i];
1277 ring->devinfo = devinfo;
1278 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1279 brcmf_commonring_register_cb(&ring->commonring,
1280 brcmf_pcie_ring_mb_ring_bell,
1281 brcmf_pcie_ring_mb_update_rptr,
1282 brcmf_pcie_ring_mb_update_wptr,
1283 brcmf_pcie_ring_mb_write_rptr,
1284 brcmf_pcie_ring_mb_write_wptr,
1285 ring);
1286 ring->w_idx_addr = h2d_w_idx_ptr;
1287 ring->r_idx_addr = h2d_r_idx_ptr;
f3550aeb
FL		 1288 h2d_w_idx_ptr += idx_offset;
1289 h2d_r_idx_ptr += idx_offset;
9e37f045
HM		 1290 }
1291 devinfo->shared.flowrings = rings;
1292
1293 return 0;
1294
1295fail:
f3550aeb 1296 brcmf_err("Allocating ring buffers failed\n");
9e37f045
HM		 1297 brcmf_pcie_release_ringbuffers(devinfo);
1298 return -ENOMEM;
1299}
1300
1301
1302static void
1303brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1304{
1305 if (devinfo->shared.scratch)
1306 dma_free_coherent(&devinfo->pdev->dev,
1307 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1308 devinfo->shared.scratch,
1309 devinfo->shared.scratch_dmahandle);
1310 if (devinfo->shared.ringupd)
1311 dma_free_coherent(&devinfo->pdev->dev,
1312 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1313 devinfo->shared.ringupd,
1314 devinfo->shared.ringupd_dmahandle);
1315}
1316
1317static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1318{
83297aaa 1319 u64 address;
9e37f045
HM		 1320 u32 addr;
1321
1322 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1323 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1324 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1325 if (!devinfo->shared.scratch)
1326 goto fail;
1327
1328 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
9e37f045
HM		 1329
1330 addr = devinfo->shared.tcm_base_address +
1331 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
83297aaa 1332 address = (u64)devinfo->shared.scratch_dmahandle;
9e37f045
HM		 1333 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1334 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1335 addr = devinfo->shared.tcm_base_address +
1336 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1337 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1338
1339 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1340 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1341 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1342 if (!devinfo->shared.ringupd)
1343 goto fail;
1344
1345 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
9e37f045
HM		 1346
1347 addr = devinfo->shared.tcm_base_address +
1348 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
83297aaa 1349 address = (u64)devinfo->shared.ringupd_dmahandle;
9e37f045
HM		 1350 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1351 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1352 addr = devinfo->shared.tcm_base_address +
1353 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1354 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1355 return 0;
1356
1357fail:
1358 brcmf_err("Allocating scratch buffers failed\n");
1359 brcmf_pcie_release_scratchbuffers(devinfo);
1360 return -ENOMEM;
1361}
1362
1363
1364static void brcmf_pcie_down(struct device *dev)
1365{
1366}
1367
1368
1369static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1370{
1371 return 0;
1372}
1373
1374
1375static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1376 uint len)
1377{
1378 return 0;
1379}
1380
1381
1382static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1383 uint len)
1384{
1385 return 0;
1386}
1387
1388
4eb3af7c
HM		 1389static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1390{
1391 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1392 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1393 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1394
1395 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1396 devinfo->wowl_enabled = enabled;
1397 if (enabled)
1398 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1399 else
1400 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1401}
1402
1403
ff4445a8
AS		 1404static size_t brcmf_pcie_get_ramsize(struct device *dev)
1405{
1406 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1407 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1408 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1409
1410 return devinfo->ci->ramsize - devinfo->ci->srsize;
1411}
1412
1413
1414static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1415{
1416 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1417 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1418 struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1419
1420 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1421 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1422 return 0;
1423}
1424
1425
9e37f045
HM		 1426static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1427 .txdata = brcmf_pcie_tx,
1428 .stop = brcmf_pcie_down,
1429 .txctl = brcmf_pcie_tx_ctlpkt,
1430 .rxctl = brcmf_pcie_rx_ctlpkt,
4eb3af7c 1431 .wowl_config = brcmf_pcie_wowl_config,
ff4445a8
AS		 1432 .get_ramsize = brcmf_pcie_get_ramsize,
1433 .get_memdump = brcmf_pcie_get_memdump,
9e37f045
HM		 1434};
1435
1436
1437static int
1438brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1439 u32 sharedram_addr)
1440{
1441 struct brcmf_pcie_shared_info *shared;
1442 u32 addr;
1443 u32 version;
1444
1445 shared = &devinfo->shared;
1446 shared->tcm_base_address = sharedram_addr;
1447
1448 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1449 version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1450 brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1451 if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1452 (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1453 brcmf_err("Unsupported PCIE version %d\n", version);
1454 return -EINVAL;
1455 }
9e37f045 1456
f3550aeb
FL		 1457 /* check firmware support dma indicies */
1458 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1459 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1460 devinfo->dma_idx_sz = sizeof(u16);
1461 else
1462 devinfo->dma_idx_sz = sizeof(u32);
1463 }
1464
9e37f045
HM		 1465 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1466 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1467 if (shared->max_rxbufpost == 0)
1468 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1469
1470 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1471 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1472
1473 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1474 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1475
1476 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1477 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1478
1479 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1480 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1481
1482 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1483 shared->max_rxbufpost, shared->rx_dataoffset);
1484
1485 brcmf_pcie_bus_console_init(devinfo);
1486
1487 return 0;
1488}
1489
1490
1491static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1492{
1493 char *fw_name;
1494 char *nvram_name;
1495 uint fw_len, nv_len;
1496 char end;
1497
1498 brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1499 devinfo->ci->chiprev);
1500
1501 switch (devinfo->ci->chip) {
1502 case BRCM_CC_43602_CHIP_ID:
1503 fw_name = BRCMF_PCIE_43602_FW_NAME;
1504 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1505 break;
e3c92cb2
HM		 1506 case BRCM_CC_4350_CHIP_ID:
1507 fw_name = BRCMF_PCIE_4350_FW_NAME;
1508 nvram_name = BRCMF_PCIE_4350_NVRAM_NAME;
1509 break;
9e37f045
HM		 1510 case BRCM_CC_4356_CHIP_ID:
1511 fw_name = BRCMF_PCIE_4356_FW_NAME;
1512 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1513 break;
1514 case BRCM_CC_43567_CHIP_ID:
1515 case BRCM_CC_43569_CHIP_ID:
1516 case BRCM_CC_43570_CHIP_ID:
1517 fw_name = BRCMF_PCIE_43570_FW_NAME;
1518 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1519 break;
67f3b6a3
AS		 1520 case BRCM_CC_4358_CHIP_ID:
1521 fw_name = BRCMF_PCIE_4358_FW_NAME;
1522 nvram_name = BRCMF_PCIE_4358_NVRAM_NAME;
1523 break;
2aff0303
HM		 1524 case BRCM_CC_4359_CHIP_ID:
1525 fw_name = BRCMF_PCIE_4359_FW_NAME;
1526 nvram_name = BRCMF_PCIE_4359_NVRAM_NAME;
1527 break;
55acca90
HM		 1528 case BRCM_CC_4365_CHIP_ID:
1529 fw_name = BRCMF_PCIE_4365_FW_NAME;
1530 nvram_name = BRCMF_PCIE_4365_NVRAM_NAME;
1531 break;
1532 case BRCM_CC_4366_CHIP_ID:
1533 fw_name = BRCMF_PCIE_4366_FW_NAME;
1534 nvram_name = BRCMF_PCIE_4366_NVRAM_NAME;
1535 break;
f8273baf
EC		 1536 case BRCM_CC_4371_CHIP_ID:
1537 fw_name = BRCMF_PCIE_4371_FW_NAME;
1538 nvram_name = BRCMF_PCIE_4371_NVRAM_NAME;
1539 break;
9e37f045
HM		 1540 default:
1541 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1542 return -ENODEV;
1543 }
1544
1545 fw_len = sizeof(devinfo->fw_name) - 1;
1546 nv_len = sizeof(devinfo->nvram_name) - 1;
1547 /* check if firmware path is provided by module parameter */
1548 if (brcmf_firmware_path[0] != '\0') {
1549 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1550 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1551 fw_len -= strlen(devinfo->fw_name);
1552 nv_len -= strlen(devinfo->nvram_name);
1553
1554 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1555 if (end != '/') {
1556 strncat(devinfo->fw_name, "/", fw_len);
1557 strncat(devinfo->nvram_name, "/", nv_len);
1558 fw_len--;
1559 nv_len--;
1560 }
1561 }
1562 strncat(devinfo->fw_name, fw_name, fw_len);
1563 strncat(devinfo->nvram_name, nvram_name, nv_len);
1564
1565 return 0;
1566}
1567
1568
1569static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1570 const struct firmware *fw, void *nvram,
1571 u32 nvram_len)
1572{
1573 u32 sharedram_addr;
1574 u32 sharedram_addr_written;
1575 u32 loop_counter;
1576 int err;
1577 u32 address;
1578 u32 resetintr;
1579
1580 devinfo->ringbell = brcmf_pcie_ringbell_v2;
1581 devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1582
1583 brcmf_dbg(PCIE, "Halt ARM.\n");
1584 err = brcmf_pcie_enter_download_state(devinfo);
1585 if (err)
1586 return err;
1587
1588 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1589 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1590 (void *)fw->data, fw->size);
1591
1592 resetintr = get_unaligned_le32(fw->data);
1593 release_firmware(fw);
1594
1595 /* reset last 4 bytes of RAM address. to be used for shared
1596 * area. This identifies when FW is running
1597 */
1598 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1599
1600 if (nvram) {
1601 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1602 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1603 nvram_len;
1604 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1605 brcmf_fw_nvram_free(nvram);
1606 } else {
1607 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1608 devinfo->nvram_name);
1609 }
1610
1611 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1612 devinfo->ci->ramsize -
1613 4);
1614 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1615 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1616 if (err)
1617 return err;
1618
1619 brcmf_dbg(PCIE, "Wait for FW init\n");
1620 sharedram_addr = sharedram_addr_written;
1621 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1622 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1623 msleep(50);
1624 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1625 devinfo->ci->ramsize -
1626 4);
1627 loop_counter--;
1628 }
1629 if (sharedram_addr == sharedram_addr_written) {
1630 brcmf_err("FW failed to initialize\n");
1631 return -ENODEV;
1632 }
1633 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1634
1635 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1636}
1637
1638
1639static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1640{
1641 struct pci_dev *pdev;
1642 int err;
1643 phys_addr_t bar0_addr, bar1_addr;
1644 ulong bar1_size;
1645
1646 pdev = devinfo->pdev;
1647
1648 err = pci_enable_device(pdev);
1649 if (err) {
1650 brcmf_err("pci_enable_device failed err=%d\n", err);
1651 return err;
1652 }
1653
1654 pci_set_master(pdev);
1655
1656 /* Bar-0 mapped address */
1657 bar0_addr = pci_resource_start(pdev, 0);
1658 /* Bar-1 mapped address */
1659 bar1_addr = pci_resource_start(pdev, 2);
1660 /* read Bar-1 mapped memory range */
1661 bar1_size = pci_resource_len(pdev, 2);
1662 if ((bar1_size == 0) || (bar1_addr == 0)) {
1663 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1664 bar1_size, (unsigned long long)bar1_addr);
1665 return -EINVAL;
1666 }
1667
1668 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1669 devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1670 devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1671
1672 if (!devinfo->regs || !devinfo->tcm) {
1673 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1674 devinfo->tcm);
1675 return -EINVAL;
1676 }
1677 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1678 devinfo->regs, (unsigned long long)bar0_addr);
1679 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1680 devinfo->tcm, (unsigned long long)bar1_addr);
1681
1682 return 0;
1683}
1684
1685
1686static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1687{
1688 if (devinfo->tcm)
1689 iounmap(devinfo->tcm);
1690 if (devinfo->regs)
1691 iounmap(devinfo->regs);
1692
1693 pci_disable_device(devinfo->pdev);
1694}
1695
1696
1697static int brcmf_pcie_attach_bus(struct device *dev)
1698{
1699 int ret;
1700
1701 /* Attach to the common driver interface */
1702 ret = brcmf_attach(dev);
1703 if (ret) {
1704 brcmf_err("brcmf_attach failed\n");
1705 } else {
1706 ret = brcmf_bus_start(dev);
1707 if (ret)
1708 brcmf_err("dongle is not responding\n");
1709 }
1710
1711 return ret;
1712}
1713
1714
1715static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1716{
1717 u32 ret_addr;
1718
1719 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1720 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1721 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1722
1723 return ret_addr;
1724}
1725
1726
1727static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1728{
1729 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1730
1731 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1732 return brcmf_pcie_read_reg32(devinfo, addr);
1733}
1734
1735
1736static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1737{
1738 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1739
1740 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1741 brcmf_pcie_write_reg32(devinfo, addr, value);
1742}
1743
1744
1745static int brcmf_pcie_buscoreprep(void *ctx)
1746{
c161f29b 1747 return brcmf_pcie_get_resource(ctx);
9e37f045
HM		 1748}
1749
1750
07fe2e38
HM		 1751static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1752{
1753 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1754 u32 val;
1755
1756 devinfo->ci = chip;
1757 brcmf_pcie_reset_device(devinfo);
1758
1759 val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1760 if (val != 0xffffffff)
1761 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1762 val);
1763
1764 return 0;
1765}
1766
1767
d380ebc9
AS		 1768static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1769 u32 rstvec)
9e37f045
HM		 1770{
1771 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1772
1773 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1774}
1775
1776
1777static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1778 .prepare = brcmf_pcie_buscoreprep,
07fe2e38 1779 .reset = brcmf_pcie_buscore_reset,
d380ebc9 1780 .activate = brcmf_pcie_buscore_activate,
9e37f045
HM		 1781 .read32 = brcmf_pcie_buscore_read32,
1782 .write32 = brcmf_pcie_buscore_write32,
1783};
1784
1785static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1786 void *nvram, u32 nvram_len)
1787{
1788 struct brcmf_bus *bus = dev_get_drvdata(dev);
1789 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1790 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1791 struct brcmf_commonring **flowrings;
1792 int ret;
1793 u32 i;
1794
1795 brcmf_pcie_attach(devinfo);
1796
1797 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1798 if (ret)
1799 goto fail;
1800
1801 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1802
1803 ret = brcmf_pcie_init_ringbuffers(devinfo);
1804 if (ret)
1805 goto fail;
1806
1807 ret = brcmf_pcie_init_scratchbuffers(devinfo);
1808 if (ret)
1809 goto fail;
1810
1811 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1812 ret = brcmf_pcie_request_irq(devinfo);
1813 if (ret)
1814 goto fail;
1815
1816 /* hook the commonrings in the bus structure. */
1817 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1818 bus->msgbuf->commonrings[i] =
1819 &devinfo->shared.commonrings[i]->commonring;
1820
d5c5181c 1821 flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
9e37f045
HM		 1822 GFP_KERNEL);
1823 if (!flowrings)
1824 goto fail;
1825
1826 for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1827 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1828 bus->msgbuf->flowrings = flowrings;
1829
1830 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1831 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1832 bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1833
1834 init_waitqueue_head(&devinfo->mbdata_resp_wait);
1835
1836 brcmf_pcie_intr_enable(devinfo);
1837 if (brcmf_pcie_attach_bus(bus->dev) == 0)
1838 return;
1839
1840 brcmf_pcie_bus_console_read(devinfo);
1841
1842fail:
1843 device_release_driver(dev);
1844}
1845
1846static int
1847brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1848{
1849 int ret;
1850 struct brcmf_pciedev_info *devinfo;
1851 struct brcmf_pciedev *pcie_bus_dev;
1852 struct brcmf_bus *bus;
c4365534
HM		 1853 u16 domain_nr;
1854 u16 bus_nr;
9e37f045 1855
c4365534
HM		 1856 domain_nr = pci_domain_nr(pdev->bus) + 1;
1857 bus_nr = pdev->bus->number;
1858 brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1859 domain_nr, bus_nr);
9e37f045
HM		 1860
1861 ret = -ENOMEM;
1862 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1863 if (devinfo == NULL)
1864 return ret;
1865
1866 devinfo->pdev = pdev;
1867 pcie_bus_dev = NULL;
1868 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1869 if (IS_ERR(devinfo->ci)) {
1870 ret = PTR_ERR(devinfo->ci);
1871 devinfo->ci = NULL;
1872 goto fail;
1873 }
1874
1875 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1876 if (pcie_bus_dev == NULL) {
1877 ret = -ENOMEM;
1878 goto fail;
1879 }
1880
1881 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1882 if (!bus) {
1883 ret = -ENOMEM;
1884 goto fail;
1885 }
1886 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1887 if (!bus->msgbuf) {
1888 ret = -ENOMEM;
1889 kfree(bus);
1890 goto fail;
1891 }
1892
1893 /* hook it all together. */
1894 pcie_bus_dev->devinfo = devinfo;
1895 pcie_bus_dev->bus = bus;
1896 bus->dev = &pdev->dev;
1897 bus->bus_priv.pcie = pcie_bus_dev;
1898 bus->ops = &brcmf_pcie_bus_ops;
1899 bus->proto_type = BRCMF_PROTO_MSGBUF;
1900 bus->chip = devinfo->coreid;
4eb3af7c 1901 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
9e37f045
HM		 1902 dev_set_drvdata(&pdev->dev, bus);
1903
1904 ret = brcmf_pcie_get_fwnames(devinfo);
1905 if (ret)
1906 goto fail_bus;
1907
c4365534
HM		 1908 ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1909 BRCMF_FW_REQ_NV_OPTIONAL,
1910 devinfo->fw_name, devinfo->nvram_name,
1911 brcmf_pcie_setup, domain_nr, bus_nr);
9e37f045
HM		 1912 if (ret == 0)
1913 return 0;
1914fail_bus:
1915 kfree(bus->msgbuf);
1916 kfree(bus);
1917fail:
1918 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1919 brcmf_pcie_release_resource(devinfo);
1920 if (devinfo->ci)
1921 brcmf_chip_detach(devinfo->ci);
1922 kfree(pcie_bus_dev);
1923 kfree(devinfo);
1924 return ret;
1925}
1926
1927
1928static void
1929brcmf_pcie_remove(struct pci_dev *pdev)
1930{
1931 struct brcmf_pciedev_info *devinfo;
1932 struct brcmf_bus *bus;
1933
1934 brcmf_dbg(PCIE, "Enter\n");
1935
1936 bus = dev_get_drvdata(&pdev->dev);
1937 if (bus == NULL)
1938 return;
1939
1940 devinfo = bus->bus_priv.pcie->devinfo;
1941
1942 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1943 if (devinfo->ci)
1944 brcmf_pcie_intr_disable(devinfo);
1945
1946 brcmf_detach(&pdev->dev);
1947
1948 kfree(bus->bus_priv.pcie);
1949 kfree(bus->msgbuf->flowrings);
1950 kfree(bus->msgbuf);
1951 kfree(bus);
1952
1953 brcmf_pcie_release_irq(devinfo);
1954 brcmf_pcie_release_scratchbuffers(devinfo);
1955 brcmf_pcie_release_ringbuffers(devinfo);
bd4f82e3 1956 brcmf_pcie_reset_device(devinfo);
9e37f045
HM		 1957 brcmf_pcie_release_resource(devinfo);
1958
1959 if (devinfo->ci)
1960 brcmf_chip_detach(devinfo->ci);
1961
1962 kfree(devinfo);
1963 dev_set_drvdata(&pdev->dev, NULL);
1964}
1965
1966
1967#ifdef CONFIG_PM
1968
1969
1970static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1971{
1972 struct brcmf_pciedev_info *devinfo;
1973 struct brcmf_bus *bus;
1974 int err;
1975
1976 brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1977
1978 bus = dev_get_drvdata(&pdev->dev);
1979 devinfo = bus->bus_priv.pcie->devinfo;
1980
1981 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1982
1983 devinfo->mbdata_completed = false;
1984 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1985
1986 wait_event_timeout(devinfo->mbdata_resp_wait,
1987 devinfo->mbdata_completed,
1988 msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1989 if (!devinfo->mbdata_completed) {
1990 brcmf_err("Timeout on response for entering D3 substate\n");
1991 return -EIO;
1992 }
4eb3af7c 1993 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
9e37f045
HM		 1994
1995 err = pci_save_state(pdev);
4eb3af7c 1996 if (err)
9e37f045 1997 brcmf_err("pci_save_state failed, err=%d\n", err);
4eb3af7c
HM		 1998 if ((err) || (!devinfo->wowl_enabled)) {
1999 brcmf_chip_detach(devinfo->ci);
2000 devinfo->ci = NULL;
2001 brcmf_pcie_remove(pdev);
2002 return 0;
9e37f045
HM		 2003 }
2004
9e37f045
HM		 2005 return pci_prepare_to_sleep(pdev);
2006}
2007
9e37f045
HM		 2008static int brcmf_pcie_resume(struct pci_dev *pdev)
2009{
4eb3af7c
HM		 2010 struct brcmf_pciedev_info *devinfo;
2011 struct brcmf_bus *bus;
9e37f045
HM		 2012 int err;
2013
4eb3af7c
HM		 2014 bus = dev_get_drvdata(&pdev->dev);
2015 brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
9e37f045
HM		 2016
2017 err = pci_set_power_state(pdev, PCI_D0);
2018 if (err) {
2019 brcmf_err("pci_set_power_state failed, err=%d\n", err);
4eb3af7c 2020 goto cleanup;
9e37f045
HM		 2021 }
2022 pci_restore_state(pdev);
4eb3af7c
HM		 2023 pci_enable_wake(pdev, PCI_D3hot, false);
2024 pci_enable_wake(pdev, PCI_D3cold, false);
2025
2026 /* Check if device is still up and running, if so we are ready */
2027 if (bus) {
2028 devinfo = bus->bus_priv.pcie->devinfo;
2029 if (brcmf_pcie_read_reg32(devinfo,
2030 BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
2031 if (brcmf_pcie_send_mb_data(devinfo,
2032 BRCMF_H2D_HOST_D0_INFORM))
2033 goto cleanup;
2034 brcmf_dbg(PCIE, "Hot resume, continue....\n");
2035 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
a1cee865 2036 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
4eb3af7c
HM		 2037 brcmf_pcie_intr_enable(devinfo);
2038 return 0;
2039 }
2040 }
9e37f045 2041
4eb3af7c
HM		 2042cleanup:
2043 if (bus) {
2044 devinfo = bus->bus_priv.pcie->devinfo;
2045 brcmf_chip_detach(devinfo->ci);
2046 devinfo->ci = NULL;
2047 brcmf_pcie_remove(pdev);
2048 }
9e37f045
HM		 2049 err = brcmf_pcie_probe(pdev, NULL);
2050 if (err)
2051 brcmf_err("probe after resume failed, err=%d\n", err);
2052
2053 return err;
2054}
2055
2056
2057#endif /* CONFIG_PM */
2058
2059
2060#define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
2061 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
2062
2063static struct pci_device_id brcmf_pcie_devid_table[] = {
e3c92cb2 2064 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
9e37f045
HM		 2065 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
2066 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
2067 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
67f3b6a3 2068 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
2aff0303 2069 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
9e37f045 2070 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
48fd818f
HM		 2071 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
2072 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
27aace2d 2073 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
55acca90
HM		 2074 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
2075 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
2076 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
2077 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
2078 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
2079 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
f8273baf 2080 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
9e37f045
HM		 2081 { /* end: all zeroes */ }
2082};
2083
2084
2085MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2086
2087
2088static struct pci_driver brcmf_pciedrvr = {
2089 .node = {},
2090 .name = KBUILD_MODNAME,
2091 .id_table = brcmf_pcie_devid_table,
2092 .probe = brcmf_pcie_probe,
2093 .remove = brcmf_pcie_remove,
2094#ifdef CONFIG_PM
2095 .suspend = brcmf_pcie_suspend,
2096 .resume = brcmf_pcie_resume
2097#endif /* CONFIG_PM */
2098};
2099
2100
2101void brcmf_pcie_register(void)
2102{
2103 int err;
2104
2105 brcmf_dbg(PCIE, "Enter\n");
2106 err = pci_register_driver(&brcmf_pciedrvr);
2107 if (err)
2108 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2109}
2110
2111
2112void brcmf_pcie_exit(void)
2113{
2114 brcmf_dbg(PCIE, "Enter\n");
2115 pci_unregister_driver(&brcmf_pciedrvr);
2116}
Linux kernel - Deliverables
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