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a910e4a9 SP |
1 | /* |
2 | * Firmware I/O code for mac80211 ST-Ericsson CW1200 drivers | |
3 | * | |
4 | * Copyright (c) 2010, ST-Ericsson | |
5 | * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> | |
6 | * | |
7 | * Based on: | |
8 | * ST-Ericsson UMAC CW1200 driver which is | |
9 | * Copyright (c) 2010, ST-Ericsson | |
10 | * Author: Ajitpal Singh <ajitpal.singh@stericsson.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/vmalloc.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/firmware.h> | |
21 | ||
22 | #include "cw1200.h" | |
23 | #include "fwio.h" | |
24 | #include "hwio.h" | |
911373cc | 25 | #include "hwbus.h" |
a910e4a9 SP |
26 | #include "bh.h" |
27 | ||
28 | static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision) | |
29 | { | |
30 | int hw_type = -1; | |
31 | u32 silicon_type = (config_reg_val >> 24) & 0x7; | |
32 | u32 silicon_vers = (config_reg_val >> 31) & 0x1; | |
33 | ||
34 | switch (silicon_type) { | |
35 | case 0x00: | |
36 | *major_revision = 1; | |
37 | hw_type = HIF_9000_SILICON_VERSATILE; | |
38 | break; | |
39 | case 0x01: | |
40 | case 0x02: /* CW1x00 */ | |
41 | case 0x04: /* CW1x60 */ | |
42 | *major_revision = silicon_type; | |
43 | if (silicon_vers) | |
44 | hw_type = HIF_8601_VERSATILE; | |
45 | else | |
46 | hw_type = HIF_8601_SILICON; | |
47 | break; | |
48 | default: | |
49 | break; | |
50 | } | |
51 | ||
52 | return hw_type; | |
53 | } | |
54 | ||
55 | static int cw1200_load_firmware_cw1200(struct cw1200_common *priv) | |
56 | { | |
57 | int ret, block, num_blocks; | |
58 | unsigned i; | |
59 | u32 val32; | |
60 | u32 put = 0, get = 0; | |
61 | u8 *buf = NULL; | |
62 | const char *fw_path; | |
63 | const struct firmware *firmware = NULL; | |
64 | ||
65 | /* Macroses are local. */ | |
66 | #define APB_WRITE(reg, val) \ | |
67 | do { \ | |
68 | ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \ | |
69 | if (ret < 0) \ | |
70 | goto error; \ | |
71 | } while (0) | |
72 | #define APB_READ(reg, val) \ | |
73 | do { \ | |
74 | ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \ | |
75 | if (ret < 0) \ | |
76 | goto error; \ | |
77 | } while (0) | |
78 | #define REG_WRITE(reg, val) \ | |
79 | do { \ | |
80 | ret = cw1200_reg_write_32(priv, (reg), (val)); \ | |
81 | if (ret < 0) \ | |
82 | goto error; \ | |
83 | } while (0) | |
84 | #define REG_READ(reg, val) \ | |
85 | do { \ | |
86 | ret = cw1200_reg_read_32(priv, (reg), &(val)); \ | |
87 | if (ret < 0) \ | |
88 | goto error; \ | |
89 | } while (0) | |
90 | ||
91 | switch (priv->hw_revision) { | |
92 | case CW1200_HW_REV_CUT10: | |
93 | fw_path = FIRMWARE_CUT10; | |
94 | if (!priv->sdd_path) | |
95 | priv->sdd_path = SDD_FILE_10; | |
96 | break; | |
97 | case CW1200_HW_REV_CUT11: | |
98 | fw_path = FIRMWARE_CUT11; | |
99 | if (!priv->sdd_path) | |
100 | priv->sdd_path = SDD_FILE_11; | |
101 | break; | |
102 | case CW1200_HW_REV_CUT20: | |
103 | fw_path = FIRMWARE_CUT20; | |
104 | if (!priv->sdd_path) | |
105 | priv->sdd_path = SDD_FILE_20; | |
106 | break; | |
107 | case CW1200_HW_REV_CUT22: | |
108 | fw_path = FIRMWARE_CUT22; | |
109 | if (!priv->sdd_path) | |
110 | priv->sdd_path = SDD_FILE_22; | |
111 | break; | |
112 | case CW1X60_HW_REV: | |
113 | fw_path = FIRMWARE_CW1X60; | |
114 | if (!priv->sdd_path) | |
115 | priv->sdd_path = SDD_FILE_CW1X60; | |
116 | break; | |
117 | default: | |
118 | pr_err("Invalid silicon revision %d.\n", priv->hw_revision); | |
119 | return -EINVAL; | |
120 | } | |
121 | ||
122 | /* Initialize common registers */ | |
123 | APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE); | |
124 | APB_WRITE(DOWNLOAD_PUT_REG, 0); | |
125 | APB_WRITE(DOWNLOAD_GET_REG, 0); | |
126 | APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING); | |
127 | APB_WRITE(DOWNLOAD_FLAGS_REG, 0); | |
128 | ||
129 | /* Write the NOP Instruction */ | |
130 | REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000); | |
131 | REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE); | |
132 | ||
133 | /* Release CPU from RESET */ | |
134 | REG_READ(ST90TDS_CONFIG_REG_ID, val32); | |
135 | val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT; | |
136 | REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); | |
137 | ||
138 | /* Enable Clock */ | |
139 | val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT; | |
140 | REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); | |
141 | ||
a910e4a9 SP |
142 | /* Load a firmware file */ |
143 | ret = request_firmware(&firmware, fw_path, priv->pdev); | |
144 | if (ret) { | |
145 | pr_err("Can't load firmware file %s.\n", fw_path); | |
146 | goto error; | |
147 | } | |
148 | ||
149 | buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA); | |
150 | if (!buf) { | |
151 | pr_err("Can't allocate firmware load buffer.\n"); | |
152 | ret = -ENOMEM; | |
153 | goto error; | |
154 | } | |
155 | ||
156 | /* Check if the bootloader is ready */ | |
157 | for (i = 0; i < 100; i += 1 + i / 2) { | |
158 | APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32); | |
159 | if (val32 == DOWNLOAD_I_AM_HERE) | |
160 | break; | |
161 | mdelay(i); | |
162 | } /* End of for loop */ | |
163 | ||
164 | if (val32 != DOWNLOAD_I_AM_HERE) { | |
165 | pr_err("Bootloader is not ready.\n"); | |
166 | ret = -ETIMEDOUT; | |
167 | goto error; | |
168 | } | |
169 | ||
170 | /* Calculcate number of download blocks */ | |
171 | num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1; | |
172 | ||
173 | /* Updating the length in Download Ctrl Area */ | |
174 | val32 = firmware->size; /* Explicit cast from size_t to u32 */ | |
175 | APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, val32); | |
176 | ||
177 | /* Firmware downloading loop */ | |
178 | for (block = 0; block < num_blocks; block++) { | |
179 | size_t tx_size; | |
180 | size_t block_size; | |
181 | ||
182 | /* check the download status */ | |
183 | APB_READ(DOWNLOAD_STATUS_REG, val32); | |
184 | if (val32 != DOWNLOAD_PENDING) { | |
185 | pr_err("Bootloader reported error %d.\n", val32); | |
186 | ret = -EIO; | |
187 | goto error; | |
188 | } | |
189 | ||
190 | /* loop until put - get <= 24K */ | |
191 | for (i = 0; i < 100; i++) { | |
192 | APB_READ(DOWNLOAD_GET_REG, get); | |
193 | if ((put - get) <= | |
194 | (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) | |
195 | break; | |
196 | mdelay(i); | |
197 | } | |
198 | ||
199 | if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) { | |
200 | pr_err("Timeout waiting for FIFO.\n"); | |
201 | ret = -ETIMEDOUT; | |
202 | goto error; | |
203 | } | |
204 | ||
205 | /* calculate the block size */ | |
206 | tx_size = block_size = min((size_t)(firmware->size - put), | |
207 | (size_t)DOWNLOAD_BLOCK_SIZE); | |
208 | ||
209 | memcpy(buf, &firmware->data[put], block_size); | |
210 | if (block_size < DOWNLOAD_BLOCK_SIZE) { | |
211 | memset(&buf[block_size], 0, | |
212 | DOWNLOAD_BLOCK_SIZE - block_size); | |
213 | tx_size = DOWNLOAD_BLOCK_SIZE; | |
214 | } | |
215 | ||
216 | /* send the block to sram */ | |
217 | ret = cw1200_apb_write(priv, | |
218 | CW1200_APB(DOWNLOAD_FIFO_OFFSET + | |
219 | (put & (DOWNLOAD_FIFO_SIZE - 1))), | |
220 | buf, tx_size); | |
221 | if (ret < 0) { | |
222 | pr_err("Can't write firmware block @ %d!\n", | |
223 | put & (DOWNLOAD_FIFO_SIZE - 1)); | |
224 | goto error; | |
225 | } | |
226 | ||
227 | /* update the put register */ | |
228 | put += block_size; | |
229 | APB_WRITE(DOWNLOAD_PUT_REG, put); | |
230 | } /* End of firmware download loop */ | |
231 | ||
232 | /* Wait for the download completion */ | |
233 | for (i = 0; i < 300; i += 1 + i / 2) { | |
234 | APB_READ(DOWNLOAD_STATUS_REG, val32); | |
235 | if (val32 != DOWNLOAD_PENDING) | |
236 | break; | |
237 | mdelay(i); | |
238 | } | |
239 | if (val32 != DOWNLOAD_SUCCESS) { | |
240 | pr_err("Wait for download completion failed: 0x%.8X\n", val32); | |
241 | ret = -ETIMEDOUT; | |
242 | goto error; | |
243 | } else { | |
244 | pr_info("Firmware download completed.\n"); | |
245 | ret = 0; | |
246 | } | |
247 | ||
248 | error: | |
249 | kfree(buf); | |
250 | if (firmware) | |
251 | release_firmware(firmware); | |
252 | return ret; | |
253 | ||
254 | #undef APB_WRITE | |
255 | #undef APB_READ | |
256 | #undef REG_WRITE | |
257 | #undef REG_READ | |
258 | } | |
259 | ||
260 | ||
261 | static int config_reg_read(struct cw1200_common *priv, u32 *val) | |
262 | { | |
263 | switch (priv->hw_type) { | |
264 | case HIF_9000_SILICON_VERSATILE: { | |
265 | u16 val16; | |
266 | int ret = cw1200_reg_read_16(priv, | |
267 | ST90TDS_CONFIG_REG_ID, | |
268 | &val16); | |
269 | if (ret < 0) | |
270 | return ret; | |
271 | *val = val16; | |
272 | return 0; | |
273 | } | |
274 | case HIF_8601_VERSATILE: | |
275 | case HIF_8601_SILICON: | |
276 | default: | |
277 | cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val); | |
278 | break; | |
279 | } | |
280 | return 0; | |
281 | } | |
282 | ||
283 | static int config_reg_write(struct cw1200_common *priv, u32 val) | |
284 | { | |
285 | switch (priv->hw_type) { | |
286 | case HIF_9000_SILICON_VERSATILE: | |
287 | return cw1200_reg_write_16(priv, | |
288 | ST90TDS_CONFIG_REG_ID, | |
289 | (u16)val); | |
290 | case HIF_8601_VERSATILE: | |
291 | case HIF_8601_SILICON: | |
292 | default: | |
293 | return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val); | |
294 | break; | |
295 | } | |
296 | return 0; | |
297 | } | |
298 | ||
299 | int cw1200_load_firmware(struct cw1200_common *priv) | |
300 | { | |
301 | int ret; | |
302 | int i; | |
303 | u32 val32; | |
304 | u16 val16; | |
305 | int major_revision = -1; | |
306 | ||
307 | /* Read CONFIG Register */ | |
308 | ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32); | |
309 | if (ret < 0) { | |
310 | pr_err("Can't read config register.\n"); | |
311 | goto out; | |
312 | } | |
313 | ||
314 | if (val32 == 0 || val32 == 0xffffffff) { | |
315 | pr_err("Bad config register value (0x%08x)\n", val32); | |
316 | ret = -EIO; | |
317 | goto out; | |
318 | } | |
319 | ||
320 | priv->hw_type = cw1200_get_hw_type(val32, &major_revision); | |
321 | if (priv->hw_type < 0) { | |
322 | pr_err("Can't deduce hardware type.\n"); | |
323 | ret = -ENOTSUPP; | |
324 | goto out; | |
325 | } | |
326 | ||
327 | /* Set DPLL Reg value, and read back to confirm writes work */ | |
328 | ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID, | |
329 | cw1200_dpll_from_clk(priv->hw_refclk)); | |
330 | if (ret < 0) { | |
331 | pr_err("Can't write DPLL register.\n"); | |
332 | goto out; | |
333 | } | |
334 | ||
335 | msleep(20); | |
336 | ||
337 | ret = cw1200_reg_read_32(priv, | |
338 | ST90TDS_TSET_GEN_R_W_REG_ID, &val32); | |
339 | if (ret < 0) { | |
340 | pr_err("Can't read DPLL register.\n"); | |
341 | goto out; | |
342 | } | |
343 | ||
344 | if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) { | |
345 | pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n", | |
346 | cw1200_dpll_from_clk(priv->hw_refclk), val32); | |
347 | ret = -EIO; | |
348 | goto out; | |
349 | } | |
350 | ||
351 | /* Set wakeup bit in device */ | |
352 | ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16); | |
353 | if (ret < 0) { | |
354 | pr_err("set_wakeup: can't read control register.\n"); | |
355 | goto out; | |
356 | } | |
357 | ||
358 | ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID, | |
359 | val16 | ST90TDS_CONT_WUP_BIT); | |
360 | if (ret < 0) { | |
361 | pr_err("set_wakeup: can't write control register.\n"); | |
362 | goto out; | |
363 | } | |
364 | ||
365 | /* Wait for wakeup */ | |
366 | for (i = 0; i < 300; i += (1 + i / 2)) { | |
367 | ret = cw1200_reg_read_16(priv, | |
368 | ST90TDS_CONTROL_REG_ID, &val16); | |
369 | if (ret < 0) { | |
370 | pr_err("wait_for_wakeup: can't read control register.\n"); | |
371 | goto out; | |
372 | } | |
373 | ||
374 | if (val16 & ST90TDS_CONT_RDY_BIT) | |
375 | break; | |
376 | ||
377 | msleep(i); | |
378 | } | |
379 | ||
380 | if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) { | |
381 | pr_err("wait_for_wakeup: device is not responding.\n"); | |
382 | ret = -ETIMEDOUT; | |
383 | goto out; | |
384 | } | |
385 | ||
386 | switch (major_revision) { | |
387 | case 1: | |
388 | /* CW1200 Hardware detection logic : Check for CUT1.1 */ | |
389 | ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32); | |
390 | if (ret) { | |
391 | pr_err("HW detection: can't read CUT ID.\n"); | |
392 | goto out; | |
393 | } | |
394 | ||
395 | switch (val32) { | |
396 | case CW1200_CUT_11_ID_STR: | |
397 | pr_info("CW1x00 Cut 1.1 silicon detected.\n"); | |
398 | priv->hw_revision = CW1200_HW_REV_CUT11; | |
399 | break; | |
400 | default: | |
401 | pr_info("CW1x00 Cut 1.0 silicon detected.\n"); | |
402 | priv->hw_revision = CW1200_HW_REV_CUT10; | |
403 | break; | |
404 | } | |
405 | ||
406 | /* According to ST-E, CUT<2.0 has busted BA TID0-3. | |
407 | Just disable it entirely... | |
408 | */ | |
409 | priv->ba_rx_tid_mask = 0; | |
410 | priv->ba_tx_tid_mask = 0; | |
411 | break; | |
412 | case 2: { | |
413 | u32 ar1, ar2, ar3; | |
414 | ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1); | |
415 | if (ret) { | |
416 | pr_err("(1) HW detection: can't read CUT ID\n"); | |
417 | goto out; | |
418 | } | |
419 | ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2); | |
420 | if (ret) { | |
421 | pr_err("(2) HW detection: can't read CUT ID.\n"); | |
422 | goto out; | |
423 | } | |
424 | ||
425 | ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3); | |
426 | if (ret) { | |
427 | pr_err("(3) HW detection: can't read CUT ID.\n"); | |
428 | goto out; | |
429 | } | |
430 | ||
431 | if (ar1 == CW1200_CUT_22_ID_STR1 && | |
432 | ar2 == CW1200_CUT_22_ID_STR2 && | |
433 | ar3 == CW1200_CUT_22_ID_STR3) { | |
434 | pr_info("CW1x00 Cut 2.2 silicon detected.\n"); | |
435 | priv->hw_revision = CW1200_HW_REV_CUT22; | |
436 | } else { | |
437 | pr_info("CW1x00 Cut 2.0 silicon detected.\n"); | |
438 | priv->hw_revision = CW1200_HW_REV_CUT20; | |
439 | } | |
440 | break; | |
441 | } | |
442 | case 4: | |
443 | pr_info("CW1x60 silicon detected.\n"); | |
444 | priv->hw_revision = CW1X60_HW_REV; | |
445 | break; | |
446 | default: | |
447 | pr_err("Unsupported silicon major revision %d.\n", | |
448 | major_revision); | |
449 | ret = -ENOTSUPP; | |
450 | goto out; | |
451 | } | |
452 | ||
453 | /* Checking for access mode */ | |
454 | ret = config_reg_read(priv, &val32); | |
455 | if (ret < 0) { | |
456 | pr_err("Can't read config register.\n"); | |
457 | goto out; | |
458 | } | |
459 | ||
460 | if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) { | |
461 | pr_err("Device is already in QUEUE mode!\n"); | |
462 | ret = -EINVAL; | |
463 | goto out; | |
464 | } | |
465 | ||
466 | switch (priv->hw_type) { | |
467 | case HIF_8601_SILICON: | |
468 | if (priv->hw_revision == CW1X60_HW_REV) { | |
469 | pr_err("Can't handle CW1160/1260 firmware load yet.\n"); | |
470 | ret = -ENOTSUPP; | |
471 | goto out; | |
472 | } | |
473 | ret = cw1200_load_firmware_cw1200(priv); | |
474 | break; | |
475 | default: | |
476 | pr_err("Can't perform firmware load for hw type %d.\n", | |
477 | priv->hw_type); | |
478 | ret = -ENOTSUPP; | |
479 | goto out; | |
480 | } | |
481 | if (ret < 0) { | |
482 | pr_err("Firmware load error.\n"); | |
483 | goto out; | |
484 | } | |
485 | ||
486 | /* Enable interrupt signalling */ | |
911373cc | 487 | priv->hwbus_ops->lock(priv->hwbus_priv); |
c4fb19d2 | 488 | ret = __cw1200_irq_enable(priv, 1); |
911373cc | 489 | priv->hwbus_ops->unlock(priv->hwbus_priv); |
a910e4a9 SP |
490 | if (ret < 0) |
491 | goto unsubscribe; | |
492 | ||
493 | /* Configure device for MESSSAGE MODE */ | |
494 | ret = config_reg_read(priv, &val32); | |
495 | if (ret < 0) { | |
496 | pr_err("Can't read config register.\n"); | |
497 | goto unsubscribe; | |
498 | } | |
499 | ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT); | |
500 | if (ret < 0) { | |
501 | pr_err("Can't write config register.\n"); | |
502 | goto unsubscribe; | |
503 | } | |
504 | ||
505 | /* Unless we read the CONFIG Register we are | |
506 | * not able to get an interrupt | |
507 | */ | |
508 | mdelay(10); | |
509 | config_reg_read(priv, &val32); | |
510 | ||
511 | out: | |
512 | return ret; | |
513 | ||
514 | unsubscribe: | |
515 | /* Disable interrupt signalling */ | |
911373cc | 516 | priv->hwbus_ops->lock(priv->hwbus_priv); |
a910e4a9 | 517 | ret = __cw1200_irq_enable(priv, 0); |
911373cc | 518 | priv->hwbus_ops->unlock(priv->hwbus_priv); |
a910e4a9 SP |
519 | return ret; |
520 | } |