projects / deliverable / linux.git / blame
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|---|---|---|
| 6f83eaa1 TW |
1 | /****************************************************************************** |
| 2 | * | |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
| 4 | * redistributing this file, you may do so under either license. | |
| 5 | * | |
| 6 | * GPL LICENSE SUMMARY | |
| 7 | * | |
| 51368bf7 | 8 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
| 8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
| 2e5d4a8f | 10 | * Copyright(c) 2016 Intel Deutschland GmbH |
| 6f83eaa1 TW |
11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of version 2 of the GNU General Public License as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, but | |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 19 | * General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; if not, write to the Free Software | |
| 23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
| 24 | * USA | |
| 25 | * | |
| 26 | * The full GNU General Public License is included in this distribution | |
| 410dc5aa | 27 | * in the file called COPYING. |
| 6f83eaa1 TW |
28 | * |
| 29 | * Contact Information: | |
| cb2f8277 | 30 | * Intel Linux Wireless <linuxwifi@intel.com> |
| 6f83eaa1 TW |
31 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 32 | * | |
| 33 | * BSD LICENSE | |
| 34 | * | |
| 51368bf7 | 35 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
| 8b4139dc | 36 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
| 6f83eaa1 TW |
37 | * All rights reserved. |
| 38 | * | |
| 39 | * Redistribution and use in source and binary forms, with or without | |
| 40 | * modification, are permitted provided that the following conditions | |
| 41 | * are met: | |
| 42 | * | |
| 43 | * * Redistributions of source code must retain the above copyright | |
| 44 | * notice, this list of conditions and the following disclaimer. | |
| 45 | * * Redistributions in binary form must reproduce the above copyright | |
| 46 | * notice, this list of conditions and the following disclaimer in | |
| 47 | * the documentation and/or other materials provided with the | |
| 48 | * distribution. | |
| 49 | * * Neither the name Intel Corporation nor the names of its | |
| 50 | * contributors may be used to endorse or promote products derived | |
| 51 | * from this software without specific prior written permission. | |
| 52 | * | |
| 53 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 54 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 55 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 56 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 57 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 58 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 59 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 60 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 61 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 62 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 64 | * | |
| 65 | *****************************************************************************/ | |
| 65a0667b TW |
66 | #ifndef __iwl_csr_h__ |
| 67 | #define __iwl_csr_h__ | |
| 9e595d24 BC |
68 | /* |
| 69 | * CSR (control and status registers) | |
| 70 | * | |
| 71 | * CSR registers are mapped directly into PCI bus space, and are accessible | |
| 72 | * whenever platform supplies power to device, even when device is in | |
| 73 | * low power states due to driver-invoked device resets | |
| 74 | * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. | |
| 75 | * | |
| 76 | * Use iwl_write32() and iwl_read32() family to access these registers; | |
| 77 | * these provide simple PCI bus access, without waking up the MAC. | |
| 78 | * Do not use iwl_write_direct32() family for these registers; | |
| 79 | * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. | |
| 80 | * The MAC (uCode processor, etc.) does not need to be powered up for accessing | |
| 81 | * the CSR registers. | |
| 82 | * | |
| f8701fe3 | 83 | * NOTE: Device does need to be awake in order to read this memory |
| 9e595d24 BC |
84 | * via CSR_EEPROM and CSR_OTP registers |
| 85 | */ | |
| 6f83eaa1 TW |
86 | #define CSR_BASE (0x000) |
| 87 | ||
| 88 | #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ | |
| 9e595d24 | 89 | #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ |
| 6f83eaa1 TW |
90 | #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ |
| 91 | #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ | |
| 92 | #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ | |
| 93 | #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ | |
| 94 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ | |
| 95 | #define CSR_GP_CNTRL (CSR_BASE+0x024) | |
| 96 | ||
| 9e595d24 BC |
97 | /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ |
| 98 | #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) | |
| 99 | ||
| 6f83eaa1 TW |
100 | /* |
| 101 | * Hardware revision info | |
| 102 | * Bit fields: | |
| 08838cde EG |
103 | * 31-16: Reserved |
| 104 | * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions | |
| 6f83eaa1 | 105 | * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D |
| 9e595d24 | 106 | * 1-0: "Dash" (-) value, as in A-1, etc. |
| 6f83eaa1 TW |
107 | */ |
| 108 | #define CSR_HW_REV (CSR_BASE+0x028) | |
| 109 | ||
| 9e595d24 BC |
110 | /* |
| 111 | * EEPROM and OTP (one-time-programmable) memory reads | |
| 112 | * | |
| f8701fe3 RC |
113 | * NOTE: Device must be awake, initialized via apm_ops.init(), |
| 114 | * in order to read. | |
| 9e595d24 | 115 | */ |
| 6f83eaa1 TW |
116 | #define CSR_EEPROM_REG (CSR_BASE+0x02c) |
| 117 | #define CSR_EEPROM_GP (CSR_BASE+0x030) | |
| 0848e297 | 118 | #define CSR_OTP_GP_REG (CSR_BASE+0x034) |
| 9e595d24 | 119 | |
| 8f061891 | 120 | #define CSR_GIO_REG (CSR_BASE+0x03C) |
| 65b7998a WYG |
121 | #define CSR_GP_UCODE_REG (CSR_BASE+0x048) |
| 122 | #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) | |
| 9e595d24 BC |
123 | |
| 124 | /* | |
| 125 | * UCODE-DRIVER GP (general purpose) mailbox registers. | |
| 126 | * SET/CLR registers set/clear bit(s) if "1" is written. | |
| 127 | */ | |
| 6f83eaa1 TW |
128 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) |
| 129 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) | |
| 130 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) | |
| 131 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) | |
| 9e595d24 | 132 | |
| 6a08f514 EG |
133 | #define CSR_MBOX_SET_REG (CSR_BASE + 0x88) |
| 134 | ||
| ab53d8af | 135 | #define CSR_LED_REG (CSR_BASE+0x094) |
| ef850d7c | 136 | #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) |
| f81c1f48 WYG |
137 | #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */ |
| 138 | ||
| 9e595d24 BC |
139 | |
| 140 | /* GIO Chicken Bits (PCI Express bus link power management) */ | |
| 8f061891 | 141 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
| 6f83eaa1 | 142 | |
| a693f187 | 143 | /* Analog phase-lock-loop configuration */ |
| 6f83eaa1 | 144 | #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) |
| 9e595d24 | 145 | |
| a812cba9 AB |
146 | /* |
| 147 | * CSR HW resources monitor registers | |
| 148 | */ | |
| 149 | #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) | |
| 150 | #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) | |
| 151 | #define CSR_MONITOR_XTAL_RESOURCES (0x00000010) | |
| 152 | ||
| 6f83eaa1 | 153 | /* |
| 9e595d24 BC |
154 | * CSR Hardware Revision Workaround Register. Indicates hardware rev; |
| 155 | * "step" determines CCK backoff for txpower calculation. Used for 4965 only. | |
| 156 | * See also CSR_HW_REV register. | |
| 6f83eaa1 TW |
157 | * Bit fields: |
| 158 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step | |
| 9e595d24 | 159 | * 1-0: "Dash" (-) value, as in C-1, etc. |
| 6f83eaa1 | 160 | */ |
| 32004ee4 | 161 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
| 9e595d24 | 162 | |
| 32004ee4 WYG |
163 | #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) |
| 164 | #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) | |
| 6f83eaa1 TW |
165 | |
| 166 | /* Bits for CSR_HW_IF_CONFIG_REG */ | |
| 7b6a2be9 EG |
167 | #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) |
| 168 | #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) | |
| 169 | #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) | |
| 170 | #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) | |
| a395b920 | 171 | #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
| 7b6a2be9 EG |
172 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) |
| 173 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) | |
| 174 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) | |
| 175 | ||
| 176 | #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) | |
| 177 | #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) | |
| 178 | #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) | |
| 179 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) | |
| 180 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) | |
| 181 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) | |
| 6f83eaa1 | 182 | |
| 9e595d24 BC |
183 | #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
| 184 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | |
| 185 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ | |
| 186 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ | |
| 187 | #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ | |
| b7aaeae4 | 188 | #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) |
| a812cba9 | 189 | #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ |
| 4c43e0d0 | 190 | |
| 6a08f514 EG |
191 | #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) |
| 192 | ||
| 74ba67ed BC |
193 | #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ |
| 194 | #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ | |
| 6f83eaa1 TW |
195 | |
| 196 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | |
| 197 | * acknowledged (reset) by host writing "1" to flagged bits. */ | |
| 198 | #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ | |
| 199 | #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ | |
| 40cefda9 | 200 | #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ |
| 6f83eaa1 TW |
201 | #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ |
| 202 | #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ | |
| 203 | #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ | |
| e1120187 | 204 | #define CSR_INT_BIT_PAGING (1 << 24) /* SDIO PAGING */ |
| 6f83eaa1 TW |
205 | #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ |
| 206 | #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ | |
| f7d046f9 | 207 | #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ |
| 6f83eaa1 TW |
208 | #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
| 209 | #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ | |
| 210 | ||
| 211 | #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ | |
| 212 | CSR_INT_BIT_HW_ERR | \ | |
| 213 | CSR_INT_BIT_FH_TX | \ | |
| 214 | CSR_INT_BIT_SW_ERR | \ | |
| e1120187 | 215 | CSR_INT_BIT_PAGING | \ |
| 6f83eaa1 TW |
216 | CSR_INT_BIT_RF_KILL | \ |
| 217 | CSR_INT_BIT_SW_RX | \ | |
| 218 | CSR_INT_BIT_WAKEUP | \ | |
| eef31718 EG |
219 | CSR_INT_BIT_ALIVE | \ |
| 220 | CSR_INT_BIT_RX_PERIODIC) | |
| 6f83eaa1 TW |
221 | |
| 222 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | |
| 223 | #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ | |
| 224 | #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ | |
| 6f83eaa1 TW |
225 | #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ |
| 226 | #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ | |
| 6f83eaa1 TW |
227 | #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ |
| 228 | #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ | |
| 229 | ||
| f7d046f9 WYG |
230 | #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ |
| 231 | CSR_FH_INT_BIT_RX_CHNL1 | \ | |
| 232 | CSR_FH_INT_BIT_RX_CHNL0) | |
| 6f83eaa1 | 233 | |
| f7d046f9 WYG |
234 | #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ |
| 235 | CSR_FH_INT_BIT_TX_CHNL0) | |
| 6f83eaa1 | 236 | |
| 6f4083aa TW |
237 | /* GPIO */ |
| 238 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) | |
| 239 | #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) | |
| 240 | #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) | |
| 6f83eaa1 TW |
241 | |
| 242 | /* RESET */ | |
| 243 | #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) | |
| 244 | #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) | |
| 245 | #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) | |
| 246 | #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) | |
| 247 | #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) | |
| 32004ee4 | 248 | #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) |
| 6f83eaa1 | 249 | |
| 9e595d24 BC |
250 | /* |
| 251 | * GP (general purpose) CONTROL REGISTER | |
| 252 | * Bit fields: | |
| 253 | * 27: HW_RF_KILL_SW | |
| 254 | * Indicates state of (platform's) hardware RF-Kill switch | |
| 255 | * 26-24: POWER_SAVE_TYPE | |
| 256 | * Indicates current power-saving mode: | |
| 257 | * 000 -- No power saving | |
| 258 | * 001 -- MAC power-down | |
| 259 | * 010 -- PHY (radio) power-down | |
| 260 | * 011 -- Error | |
| a812cba9 | 261 | * 10: XTAL ON request |
| 9e595d24 BC |
262 | * 9-6: SYS_CONFIG |
| 263 | * Indicates current system configuration, reflecting pins on chip | |
| 264 | * as forced high/low by device circuit board. | |
| 265 | * 4: GOING_TO_SLEEP | |
| 266 | * Indicates MAC is entering a power-saving sleep power-down. | |
| 267 | * Not a good time to access device-internal resources. | |
| 268 | * 3: MAC_ACCESS_REQ | |
| 269 | * Host sets this to request and maintain MAC wakeup, to allow host | |
| 270 | * access to device-internal resources. Host must wait for | |
| 271 | * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR | |
| 272 | * device registers. | |
| 273 | * 2: INIT_DONE | |
| 274 | * Host sets this to put device into fully operational D0 power mode. | |
| 275 | * Host resets this after SW_RESET to put device into low power mode. | |
| 276 | * 0: MAC_CLOCK_READY | |
| 277 | * Indicates MAC (ucode processor, etc.) is powered up and can run. | |
| 278 | * Internal resources are accessible. | |
| 279 | * NOTE: This does not indicate that the processor is actually running. | |
| f7d046f9 | 280 | * NOTE: This does not indicate that device has completed |
| 9e595d24 BC |
281 | * init or post-power-down restore of internal SRAM memory. |
| 282 | * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that | |
| 283 | * SRAM is restored and uCode is in normal operation mode. | |
| 284 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and | |
| 285 | * do not need to save/restore it. | |
| 286 | * NOTE: After device reset, this bit remains "0" until host sets | |
| 287 | * INIT_DONE | |
| 288 | */ | |
| 6f83eaa1 TW |
289 | #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) |
| 290 | #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) | |
| 291 | #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) | |
| 292 | #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) | |
| a812cba9 | 293 | #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) |
| 6f83eaa1 TW |
294 | |
| 295 | #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) | |
| 296 | ||
| 297 | #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) | |
| 298 | #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) | |
| 299 | #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) | |
| 300 | ||
| 301 | ||
| b661c819 | 302 | /* HW REV */ |
| 08838cde EG |
303 | #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) |
| 304 | #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) | |
| 305 | ||
| c2a2b28b LK |
306 | |
| 307 | /** | |
| 308 | * hw_rev values | |
| 309 | */ | |
| 310 | enum { | |
| 311 | SILICON_A_STEP = 0, | |
| 312 | SILICON_B_STEP, | |
| 716e48a6 | 313 | SILICON_C_STEP, |
| c2a2b28b LK |
314 | }; |
| 315 | ||
| 316 | ||
| 3fd0d3c1 JB |
317 | #define CSR_HW_REV_TYPE_MSK (0x000FFF0) |
| 318 | #define CSR_HW_REV_TYPE_5300 (0x0000020) | |
| 319 | #define CSR_HW_REV_TYPE_5350 (0x0000030) | |
| 320 | #define CSR_HW_REV_TYPE_5100 (0x0000050) | |
| 321 | #define CSR_HW_REV_TYPE_5150 (0x0000040) | |
| 322 | #define CSR_HW_REV_TYPE_1000 (0x0000060) | |
| 323 | #define CSR_HW_REV_TYPE_6x00 (0x0000070) | |
| 324 | #define CSR_HW_REV_TYPE_6x50 (0x0000080) | |
| 325 | #define CSR_HW_REV_TYPE_6150 (0x0000084) | |
| 326 | #define CSR_HW_REV_TYPE_6x05 (0x00000B0) | |
| 327 | #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 | |
| 328 | #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 | |
| 329 | #define CSR_HW_REV_TYPE_2x30 (0x00000C0) | |
| 330 | #define CSR_HW_REV_TYPE_2x00 (0x0000100) | |
| 331 | #define CSR_HW_REV_TYPE_105 (0x0000110) | |
| 332 | #define CSR_HW_REV_TYPE_135 (0x0000120) | |
| 333 | #define CSR_HW_REV_TYPE_7265D (0x0000210) | |
| 334 | #define CSR_HW_REV_TYPE_NONE (0x00001F0) | |
| b661c819 | 335 | |
| 6f83eaa1 TW |
336 | /* EEPROM REG */ |
| 337 | #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) | |
| 338 | #define CSR_EEPROM_REG_BIT_CMD (0x00000002) | |
| 3d5717ad ZY |
339 | #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) |
| 340 | #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) | |
| 6f83eaa1 TW |
341 | |
| 342 | /* EEPROM GP */ | |
| 9e595d24 | 343 | #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ |
| 6f83eaa1 | 344 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
| 9e595d24 BC |
345 | #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) |
| 346 | #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) | |
| 347 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) | |
| 348 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) | |
| 349 | ||
| 350 | /* One-time-programmable memory general purpose reg */ | |
| 0848e297 WYG |
351 | #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ |
| 352 | #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ | |
| 353 | #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ | |
| 354 | #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ | |
| 9e595d24 BC |
355 | |
| 356 | /* GP REG */ | |
| c09430ab WYG |
357 | #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ |
| 358 | #define CSR_GP_REG_NO_POWER_SAVE (0x00000000) | |
| 359 | #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) | |
| 360 | #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) | |
| 361 | #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) | |
| 6f83eaa1 | 362 | |
| f41bb897 | 363 | |
| 8f061891 TW |
364 | /* CSR GIO */ |
| 365 | #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) | |
| 366 | ||
| 9e595d24 BC |
367 | /* |
| 368 | * UCODE-DRIVER GP (general purpose) mailbox register 1 | |
| 369 | * Host driver and uCode write and/or read this register to communicate with | |
| 370 | * each other. | |
| 371 | * Bit fields: | |
| 372 | * 4: UCODE_DISABLE | |
| 373 | * Host sets this to request permanent halt of uCode, same as | |
| 374 | * sending CARD_STATE command with "halt" bit set. | |
| 375 | * 3: CT_KILL_EXIT | |
| 376 | * Host sets this to request exit from CT_KILL state, i.e. host thinks | |
| 377 | * device temperature is low enough to continue normal operation. | |
| 378 | * 2: CMD_BLOCKED | |
| 379 | * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) | |
| 380 | * to release uCode to clear all Tx and command queues, enter | |
| 381 | * unassociated mode, and power down. | |
| 382 | * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. | |
| 383 | * 1: SW_BIT_RFKILL | |
| 384 | * Host sets this when issuing CARD_STATE command to request | |
| 385 | * device sleep. | |
| 386 | * 0: MAC_SLEEP | |
| 387 | * uCode sets this when preparing a power-saving power-down. | |
| 388 | * uCode resets this when power-up is complete and SRAM is sane. | |
| f7d046f9 | 389 | * NOTE: device saves internal SRAM data to host when powering down, |
| 9e595d24 BC |
390 | * and must restore this data after powering back up. |
| 391 | * MAC_SLEEP is the best indication that restore is complete. | |
| 392 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and | |
| 393 | * do not need to save/restore it. | |
| 394 | */ | |
| 6f83eaa1 TW |
395 | #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) |
| 396 | #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) | |
| 397 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) | |
| 398 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) | |
| c8ac61cf | 399 | #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) |
| 6f83eaa1 | 400 | |
| 65b7998a WYG |
401 | /* GP Driver */ |
| 402 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) | |
| 403 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) | |
| 404 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) | |
| 405 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) | |
| 02796d77 SZ |
406 | #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) |
| 407 | #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) | |
| 65b7998a | 408 | |
| 52e6b85f WYG |
409 | #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) |
| 410 | ||
| 9e595d24 | 411 | /* GIO Chicken Bits (PCI Express bus link power management) */ |
| 6f83eaa1 TW |
412 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
| 413 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) | |
| 414 | ||
| ab53d8af MA |
415 | /* LED */ |
| 416 | #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) | |
| c8f9b0fe EL |
417 | #define CSR_LED_REG_TURN_ON (0x60) |
| 418 | #define CSR_LED_REG_TURN_OFF (0x20) | |
| ab53d8af | 419 | |
| a693f187 | 420 | /* ANA_PLL */ |
| a693f187 TW |
421 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) |
| 422 | ||
| 4c43e0d0 TW |
423 | /* HPET MEM debug */ |
| 424 | #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) | |
| ef850d7c MA |
425 | |
| 426 | /* DRAM INT TABLE */ | |
| 427 | #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) | |
| 18f5a374 | 428 | #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) |
| ef850d7c MA |
429 | #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) |
| 430 | ||
| a812cba9 AB |
431 | /* |
| 432 | * SHR target access (Shared block memory space) | |
| 433 | * | |
| 434 | * Shared internal registers can be accessed directly from PCI bus through SHR | |
| 435 | * arbiter without need for the MAC HW to be powered up. This is possible due to | |
| 436 | * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and | |
| 437 | * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. | |
| 438 | * | |
| 439 | * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW | |
| 440 | * need not be powered up so no "grab inc access" is required. | |
| 441 | */ | |
| 442 | ||
| 443 | /* | |
| 444 | * Registers for accessing shared registers (e.g. SHR_APMG_GP1, | |
| 445 | * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), | |
| 446 | * first, write to the control register: | |
| 447 | * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) | |
| 448 | * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) | |
| 449 | * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. | |
| 450 | * | |
| 451 | * To write the register, first, write to the data register | |
| 452 | * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: | |
| 453 | * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) | |
| 454 | * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) | |
| 455 | */ | |
| 456 | #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) | |
| 457 | #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) | |
| 458 | ||
| 9e595d24 BC |
459 | /* |
| 460 | * HBUS (Host-side Bus) | |
| 461 | * | |
| 462 | * HBUS registers are mapped directly into PCI bus space, but are used | |
| 463 | * to indirectly access device's internal memory or registers that | |
| 464 | * may be powered-down. | |
| 465 | * | |
| 466 | * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; | |
| 467 | * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ | |
| 468 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing | |
| 469 | * internal resources. | |
| 470 | * | |
| 471 | * Do not use iwl_write32()/iwl_read32() family to access these registers; | |
| 472 | * these provide only simple PCI bus access, without waking up the MAC. | |
| 473 | */ | |
| 750fe639 | 474 | #define HBUS_BASE (0x400) |
| 9e595d24 | 475 | |
| 750fe639 TW |
476 | /* |
| 477 | * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM | |
| 478 | * structures, error log, event log, verifying uCode load). | |
| 479 | * First write to address register, then read from or write to data register | |
| 480 | * to complete the job. Once the address register is set up, accesses to | |
| 481 | * data registers auto-increment the address by one dword. | |
| 482 | * Bit usage for address registers (read or write): | |
| 483 | * 0-31: memory address within device | |
| 484 | */ | |
| 485 | #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) | |
| 486 | #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) | |
| 487 | #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) | |
| 488 | #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) | |
| 489 | ||
| 9e595d24 BC |
490 | /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ |
| 491 | #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) | |
| 492 | #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) | |
| 493 | ||
| 750fe639 TW |
494 | /* |
| 495 | * Registers for accessing device's internal peripheral registers | |
| 496 | * (e.g. SCD, BSM, etc.). First write to address register, | |
| 497 | * then read from or write to data register to complete the job. | |
| 498 | * Bit usage for address registers (read or write): | |
| 499 | * 0-15: register address (offset) within device | |
| 500 | * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) | |
| 501 | */ | |
| 502 | #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) | |
| 503 | #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) | |
| 504 | #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) | |
| 505 | #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) | |
| 506 | ||
| f8c6c6b5 AB |
507 | /* Used to enable DBGM */ |
| 508 | #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) | |
| 509 | ||
| 750fe639 | 510 | /* |
| 9e595d24 | 511 | * Per-Tx-queue write pointer (index, really!) |
| 750fe639 TW |
512 | * Indicates index to next TFD that driver will fill (1 past latest filled). |
| 513 | * Bit usage: | |
| 514 | * 0-7: queue write index | |
| 515 | * 11-8: queue selector | |
| 516 | */ | |
| 517 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) | |
| 750fe639 | 518 | |
| 7a10e3e4 EG |
519 | /********************************************************** |
| 520 | * CSR values | |
| 521 | **********************************************************/ | |
| 522 | /* | |
| 523 | * host interrupt timeout value | |
| 524 | * used with setting interrupt coalescing timer | |
| 525 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
| 526 | * | |
| 527 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
| 7a10e3e4 EG |
528 | */ |
| 529 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | |
| 530 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | |
| 531 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | |
| 6960a059 | 532 | #define IWL_HOST_INT_OPER_MODE BIT(31) |
| 7a10e3e4 | 533 | |
| 9ee718aa EL |
534 | /***************************************************************************** |
| 535 | * 7000/3000 series SHR DTS addresses * | |
| 536 | *****************************************************************************/ | |
| 537 | ||
| 538 | /* Diode Results Register Structure: */ | |
| 539 | enum dtd_diode_reg { | |
| 540 | DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ | |
| 541 | DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ | |
| 542 | DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ | |
| 543 | DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ | |
| 544 | DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ | |
| 545 | DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ | |
| 546 | /* Those are the masks INSIDE the flags bit-field: */ | |
| 547 | DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, | |
| 548 | DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ | |
| 549 | DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, | |
| 550 | DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ | |
| 551 | }; | |
| 552 | ||
| 2e5d4a8f HD |
553 | /***************************************************************************** |
| 554 | * MSIX related registers * | |
| 555 | *****************************************************************************/ | |
| 556 | ||
| 557 | #define CSR_MSIX_BASE (0x2000) | |
| 558 | #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800) | |
| 559 | #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804) | |
| 560 | #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808) | |
| 561 | #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C) | |
| 562 | #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810) | |
| 563 | #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880) | |
| 564 | #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890) | |
| 565 | #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000) | |
| 566 | #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause)) | |
| 567 | #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause)) | |
| 568 | ||
| 569 | #define MSIX_FH_INT_CAUSES_Q(q) (q) | |
| 570 | ||
| 571 | /* | |
| 572 | * Causes for the FH register interrupts | |
| 573 | */ | |
| 574 | enum msix_fh_int_causes { | |
| 575 | MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16), | |
| 576 | MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17), | |
| 577 | MSIX_FH_INT_CAUSES_S2D = BIT(19), | |
| 578 | MSIX_FH_INT_CAUSES_FH_ERR = BIT(21), | |
| 579 | }; | |
| 580 | ||
| 581 | /* | |
| 582 | * Causes for the HW register interrupts | |
| 583 | */ | |
| 584 | enum msix_hw_int_causes { | |
| 585 | MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0), | |
| 586 | MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1), | |
| 587 | MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6), | |
| 588 | MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7), | |
| 589 | MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8), | |
| 590 | MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25), | |
| 591 | MSIX_HW_INT_CAUSES_REG_SCD = BIT(26), | |
| 592 | MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27), | |
| 593 | MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29), | |
| 594 | MSIX_HW_INT_CAUSES_REG_HAP = BIT(30), | |
| 595 | }; | |
| 596 | ||
| 597 | #define MSIX_MIN_INTERRUPT_VECTORS 2 | |
| 598 | #define MSIX_AUTO_CLEAR_CAUSE 0 | |
| 599 | #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) | |
| 600 | ||
| 17c867bf SS |
601 | /***************************************************************************** |
| 602 | * HW address related registers * | |
| 603 | *****************************************************************************/ | |
| 604 | ||
| 605 | #define CSR_ADDR_BASE (0x380) | |
| 606 | #define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE) | |
| 607 | #define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4) | |
| 608 | #define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8) | |
| 609 | #define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC) | |
| 610 | ||
| 65a0667b | 611 | #endif /* !__iwl_csr_h__ */ |