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iwlwifi: mvm: fix RSS key sizing
[deliverable/linux.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw.c
CommitLineData
8ca151b5
JB		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
43413a97 10 * Copyright(c) 2016 Intel Deutschland GmbH
8ca151b5
JB		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
8ca151b5
JB		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
8ca151b5
JB		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
51368bf7 35 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
8ca151b5
JB		 37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *
65 *****************************************************************************/
66#include <net/mac80211.h>
67
68#include "iwl-trans.h"
69#include "iwl-op-mode.h"
70#include "iwl-fw.h"
71#include "iwl-debug.h"
72#include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
73#include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
8c23f95c 74#include "iwl-prph.h"
8ca151b5
JB		 75#include "iwl-eeprom-parse.h"
76
77#include "mvm.h"
2f89a5d7 78#include "fw-dbg.h"
8ca151b5
JB		 79#include "iwl-phy-db.h"
80
81#define MVM_UCODE_ALIVE_TIMEOUT HZ
82#define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
83
84#define UCODE_VALID_OK cpu_to_le32(0x1)
85
8ca151b5
JB		 86struct iwl_mvm_alive_data {
87 bool valid;
88 u32 scd_base_addr;
89};
90
91static inline const struct fw_img *
92iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type)
93{
94 if (ucode_type >= IWL_UCODE_TYPE_MAX)
95 return NULL;
96
97 return &mvm->fw->img[ucode_type];
98}
99
100static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
101{
102 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
103 .valid = cpu_to_le32(valid_tx_ant),
104 };
105
33223542 106 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 107 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB		 108 sizeof(tx_ant_cmd), &tx_ant_cmd);
109}
110
43413a97
SS		 111static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
112{
113 int i;
114 struct iwl_rss_config_cmd cmd = {
115 .flags = cpu_to_le32(IWL_RSS_ENABLE),
116 .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP |
117 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD |
118 IWL_RSS_HASH_TYPE_IPV6_TCP |
119 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
120 };
121
122 for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
123 cmd.indirection_table[i] = i % mvm->trans->num_rx_queues;
dd4d3161 124 memcpy(cmd.secret_key, mvm->secret_key, sizeof(cmd.secret_key));
43413a97
SS		 125
126 return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
127}
128
a6c4fb44
MG		 129static void iwl_free_fw_paging(struct iwl_mvm *mvm)
130{
131 int i;
132
133 if (!mvm->fw_paging_db[0].fw_paging_block)
134 return;
135
136 for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
137 if (!mvm->fw_paging_db[i].fw_paging_block) {
138 IWL_DEBUG_FW(mvm,
139 "Paging: block %d already freed, continue to next page\n",
140 i);
141
142 continue;
143 }
144
145 __free_pages(mvm->fw_paging_db[i].fw_paging_block,
146 get_order(mvm->fw_paging_db[i].fw_paging_size));
147 }
e1120187 148 kfree(mvm->trans->paging_download_buf);
a6c4fb44
MG		 149 memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db));
150}
151
152static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image)
153{
154 int sec_idx, idx;
155 u32 offset = 0;
156
157 /*
158 * find where is the paging image start point:
159 * if CPU2 exist and it's in paging format, then the image looks like:
160 * CPU1 sections (2 or more)
161 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
162 * CPU2 sections (not paged)
163 * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
164 * non paged to CPU2 paging sec
165 * CPU2 paging CSS
166 * CPU2 paging image (including instruction and data)
167 */
168 for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) {
169 if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
170 sec_idx++;
171 break;
172 }
173 }
174
175 if (sec_idx >= IWL_UCODE_SECTION_MAX) {
176 IWL_ERR(mvm, "driver didn't find paging image\n");
177 iwl_free_fw_paging(mvm);
178 return -EINVAL;
179 }
180
181 /* copy the CSS block to the dram */
182 IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n",
183 sec_idx);
184
185 memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block),
186 image->sec[sec_idx].data,
187 mvm->fw_paging_db[0].fw_paging_size);
188
189 IWL_DEBUG_FW(mvm,
190 "Paging: copied %d CSS bytes to first block\n",
191 mvm->fw_paging_db[0].fw_paging_size);
192
193 sec_idx++;
194
195 /*
196 * copy the paging blocks to the dram
197 * loop index start from 1 since that CSS block already copied to dram
198 * and CSS index is 0.
199 * loop stop at num_of_paging_blk since that last block is not full.
200 */
201 for (idx = 1; idx < mvm->num_of_paging_blk; idx++) {
202 memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
203 image->sec[sec_idx].data + offset,
204 mvm->fw_paging_db[idx].fw_paging_size);
205
206 IWL_DEBUG_FW(mvm,
207 "Paging: copied %d paging bytes to block %d\n",
208 mvm->fw_paging_db[idx].fw_paging_size,
209 idx);
210
211 offset += mvm->fw_paging_db[idx].fw_paging_size;
212 }
213
214 /* copy the last paging block */
215 if (mvm->num_of_pages_in_last_blk > 0) {
216 memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
217 image->sec[sec_idx].data + offset,
218 FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk);
219
220 IWL_DEBUG_FW(mvm,
221 "Paging: copied %d pages in the last block %d\n",
222 mvm->num_of_pages_in_last_blk, idx);
223 }
224
225 return 0;
226}
227
228static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm,
229 const struct fw_img *image)
230{
231 struct page *block;
232 dma_addr_t phys = 0;
233 int blk_idx = 0;
234 int order, num_of_pages;
235 int dma_enabled;
236
237 if (mvm->fw_paging_db[0].fw_paging_block)
238 return 0;
239
240 dma_enabled = is_device_dma_capable(mvm->trans->dev);
241
242 /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
243 BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
244
245 num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
246 mvm->num_of_paging_blk = ((num_of_pages - 1) /
247 NUM_OF_PAGE_PER_GROUP) + 1;
248
249 mvm->num_of_pages_in_last_blk =
250 num_of_pages -
251 NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1);
252
253 IWL_DEBUG_FW(mvm,
254 "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
255 mvm->num_of_paging_blk,
256 mvm->num_of_pages_in_last_blk);
257
258 /* allocate block of 4Kbytes for paging CSS */
259 order = get_order(FW_PAGING_SIZE);
260 block = alloc_pages(GFP_KERNEL, order);
261 if (!block) {
262 /* free all the previous pages since we failed */
263 iwl_free_fw_paging(mvm);
264 return -ENOMEM;
265 }
266
267 mvm->fw_paging_db[blk_idx].fw_paging_block = block;
268 mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE;
269
270 if (dma_enabled) {
271 phys = dma_map_page(mvm->trans->dev, block, 0,
272 PAGE_SIZE << order, DMA_BIDIRECTIONAL);
273 if (dma_mapping_error(mvm->trans->dev, phys)) {
274 /*
275 * free the previous pages and the current one since
276 * we failed to map_page.
277 */
278 iwl_free_fw_paging(mvm);
279 return -ENOMEM;
280 }
281 mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
e1120187
MG		 282 } else {
283 mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG |
284 blk_idx << BLOCK_2_EXP_SIZE;
a6c4fb44
MG		 285 }
286
287 IWL_DEBUG_FW(mvm,
288 "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
289 order);
290
291 /*
292 * allocate blocks in dram.
293 * since that CSS allocated in fw_paging_db[0] loop start from index 1
294 */
295 for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
296 /* allocate block of PAGING_BLOCK_SIZE (32K) */
297 order = get_order(PAGING_BLOCK_SIZE);
298 block = alloc_pages(GFP_KERNEL, order);
299 if (!block) {
300 /* free all the previous pages since we failed */
301 iwl_free_fw_paging(mvm);
302 return -ENOMEM;
303 }
304
305 mvm->fw_paging_db[blk_idx].fw_paging_block = block;
306 mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE;
307
308 if (dma_enabled) {
309 phys = dma_map_page(mvm->trans->dev, block, 0,
310 PAGE_SIZE << order,
311 DMA_BIDIRECTIONAL);
312 if (dma_mapping_error(mvm->trans->dev, phys)) {
313 /*
314 * free the previous pages and the current one
315 * since we failed to map_page.
316 */
317 iwl_free_fw_paging(mvm);
318 return -ENOMEM;
319 }
320 mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
e1120187
MG		 321 } else {
322 mvm->fw_paging_db[blk_idx].fw_paging_phys =
323 PAGING_ADDR_SIG |
324 blk_idx << BLOCK_2_EXP_SIZE;
a6c4fb44
MG		 325 }
326
327 IWL_DEBUG_FW(mvm,
328 "Paging: allocated 32K bytes (order %d) for firmware paging.\n",
329 order);
330 }
331
332 return 0;
333}
334
335static int iwl_save_fw_paging(struct iwl_mvm *mvm,
336 const struct fw_img *fw)
337{
338 int ret;
339
340 ret = iwl_alloc_fw_paging_mem(mvm, fw);
341 if (ret)
342 return ret;
343
344 return iwl_fill_paging_mem(mvm, fw);
345}
346
347/* send paging cmd to FW in case CPU2 has paging image */
348static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw)
349{
350 int blk_idx;
351 __le32 dev_phy_addr;
352 struct iwl_fw_paging_cmd fw_paging_cmd = {
353 .flags =
354 cpu_to_le32(PAGING_CMD_IS_SECURED |
355 PAGING_CMD_IS_ENABLED |
356 (mvm->num_of_pages_in_last_blk <<
357 PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
358 .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
359 .block_num = cpu_to_le32(mvm->num_of_paging_blk),
360 };
361
362 /* loop for for all paging blocks + CSS block */
363 for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
364 dev_phy_addr =
365 cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >>
366 PAGE_2_EXP_SIZE);
367 fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr;
368 }
369
370 return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD,
371 IWL_ALWAYS_LONG_GROUP, 0),
372 0, sizeof(fw_paging_cmd), &fw_paging_cmd);
373}
374
e1120187
MG		 375/*
376 * Send paging item cmd to FW in case CPU2 has paging image
377 */
378static int iwl_trans_get_paging_item(struct iwl_mvm *mvm)
379{
380 int ret;
381 struct iwl_fw_get_item_cmd fw_get_item_cmd = {
382 .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING),
383 };
384
385 struct iwl_fw_get_item_resp *item_resp;
386 struct iwl_host_cmd cmd = {
387 .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0),
388 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
389 .data = { &fw_get_item_cmd, },
390 };
391
392 cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd);
393
394 ret = iwl_mvm_send_cmd(mvm, &cmd);
395 if (ret) {
396 IWL_ERR(mvm,
397 "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n",
398 ret);
399 return ret;
400 }
401
402 item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data;
403 if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) {
404 IWL_ERR(mvm,
405 "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n",
406 le32_to_cpu(item_resp->item_id));
407 ret = -EIO;
408 goto exit;
409 }
410
411 mvm->trans->paging_download_buf = kzalloc(MAX_PAGING_IMAGE_SIZE,
412 GFP_KERNEL);
413 if (!mvm->trans->paging_download_buf) {
414 ret = -ENOMEM;
415 goto exit;
416 }
417 mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val);
418 mvm->trans->paging_db = mvm->fw_paging_db;
419 IWL_DEBUG_FW(mvm,
420 "Paging: got paging request address (paging_req_addr 0x%08x)\n",
421 mvm->trans->paging_req_addr);
422
423exit:
424 iwl_free_resp(&cmd);
425
426 return ret;
427}
428
8ca151b5
JB		 429static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
430 struct iwl_rx_packet *pkt, void *data)
431{
432 struct iwl_mvm *mvm =
433 container_of(notif_wait, struct iwl_mvm, notif_wait);
434 struct iwl_mvm_alive_data *alive_data = data;
7e1223b5 435 struct mvm_alive_resp_ver1 *palive1;
01a9ca51 436 struct mvm_alive_resp_ver2 *palive2;
7e1223b5 437 struct mvm_alive_resp *palive;
01a9ca51 438
7e1223b5
EG		 439 if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) {
440 palive1 = (void *)pkt->data;
01a9ca51
EH		 441
442 mvm->support_umac_log = false;
443 mvm->error_event_table =
7e1223b5
EG		 444 le32_to_cpu(palive1->error_event_table_ptr);
445 mvm->log_event_table =
446 le32_to_cpu(palive1->log_event_table_ptr);
447 alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr);
01a9ca51 448
7e1223b5 449 alive_data->valid = le16_to_cpu(palive1->status) ==
01a9ca51
EH		 450 IWL_ALIVE_STATUS_OK;
451 IWL_DEBUG_FW(mvm,
452 "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
7e1223b5
EG		 453 le16_to_cpu(palive1->status), palive1->ver_type,
454 palive1->ver_subtype, palive1->flags);
455 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) {
01a9ca51
EH		 456 palive2 = (void *)pkt->data;
457
01a9ca51
EH		 458 mvm->error_event_table =
459 le32_to_cpu(palive2->error_event_table_ptr);
460 mvm->log_event_table =
461 le32_to_cpu(palive2->log_event_table_ptr);
462 alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr);
463 mvm->umac_error_event_table =
464 le32_to_cpu(palive2->error_info_addr);
91479b64
EH		 465 mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr);
466 mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size);
01a9ca51
EH		 467
468 alive_data->valid = le16_to_cpu(palive2->status) ==
469 IWL_ALIVE_STATUS_OK;
ffa70264
EG		 470 if (mvm->umac_error_event_table)
471 mvm->support_umac_log = true;
472
01a9ca51
EH		 473 IWL_DEBUG_FW(mvm,
474 "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
475 le16_to_cpu(palive2->status), palive2->ver_type,
476 palive2->ver_subtype, palive2->flags);
477
478 IWL_DEBUG_FW(mvm,
479 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
480 palive2->umac_major, palive2->umac_minor);
7e1223b5
EG		 481 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
482 palive = (void *)pkt->data;
483
484 mvm->error_event_table =
485 le32_to_cpu(palive->error_event_table_ptr);
486 mvm->log_event_table =
487 le32_to_cpu(palive->log_event_table_ptr);
488 alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr);
489 mvm->umac_error_event_table =
490 le32_to_cpu(palive->error_info_addr);
491 mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr);
492 mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size);
493
494 alive_data->valid = le16_to_cpu(palive->status) ==
495 IWL_ALIVE_STATUS_OK;
496 if (mvm->umac_error_event_table)
497 mvm->support_umac_log = true;
498
499 IWL_DEBUG_FW(mvm,
500 "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
501 le16_to_cpu(palive->status), palive->ver_type,
502 palive->ver_subtype, palive->flags);
503
504 IWL_DEBUG_FW(mvm,
505 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
506 le32_to_cpu(palive->umac_major),
507 le32_to_cpu(palive->umac_minor));
01a9ca51 508 }
8ca151b5
JB		 509
510 return true;
511}
512
513static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
514 struct iwl_rx_packet *pkt, void *data)
515{
516 struct iwl_phy_db *phy_db = data;
517
518 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
519 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
520 return true;
521 }
522
523 WARN_ON(iwl_phy_db_set_section(phy_db, pkt, GFP_ATOMIC));
524
525 return false;
526}
527
528static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
529 enum iwl_ucode_type ucode_type)
530{
531 struct iwl_notification_wait alive_wait;
532 struct iwl_mvm_alive_data alive_data;
533 const struct fw_img *fw;
534 int ret, i;
535 enum iwl_ucode_type old_type = mvm->cur_ucode;
6eb031d2 536 static const u16 alive_cmd[] = { MVM_ALIVE };
91479b64 537 struct iwl_sf_region st_fwrd_space;
8ca151b5 538
61df750c 539 if (ucode_type == IWL_UCODE_REGULAR &&
d2709ad7 540 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE))
61df750c
EH		 541 fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER);
542 else
543 fw = iwl_get_ucode_image(mvm, ucode_type);
befe9b6f 544 if (WARN_ON(!fw))
8ca151b5 545 return -EINVAL;
befe9b6f
JB		 546 mvm->cur_ucode = ucode_type;
547 mvm->ucode_loaded = false;
8ca151b5
JB		 548
549 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
550 alive_cmd, ARRAY_SIZE(alive_cmd),
551 iwl_alive_fn, &alive_data);
552
553 ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT);
554 if (ret) {
555 mvm->cur_ucode = old_type;
556 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
557 return ret;
558 }
559
560 /*
561 * Some things may run in the background now, but we
562 * just wait for the ALIVE notification here.
563 */
564 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
565 MVM_UCODE_ALIVE_TIMEOUT);
566 if (ret) {
192de2b4
DS		 567 if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
568 IWL_ERR(mvm,
569 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
570 iwl_read_prph(mvm->trans, SB_CPU_1_STATUS),
571 iwl_read_prph(mvm->trans, SB_CPU_2_STATUS));
8ca151b5
JB		 572 mvm->cur_ucode = old_type;
573 return ret;
574 }
575
576 if (!alive_data.valid) {
577 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
578 mvm->cur_ucode = old_type;
579 return -EIO;
580 }
581
91479b64
EH		 582 /*
583 * update the sdio allocation according to the pointer we get in the
584 * alive notification.
585 */
586 st_fwrd_space.addr = mvm->sf_space.addr;
587 st_fwrd_space.size = mvm->sf_space.size;
588 ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space);
82e8aea0
ES		 589 if (ret) {
590 IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret);
591 return ret;
592 }
91479b64 593
8ca151b5
JB		 594 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
595
a6c4fb44
MG		 596 /*
597 * configure and operate fw paging mechanism.
598 * driver configures the paging flow only once, CPU2 paging image
599 * included in the IWL_UCODE_INIT image.
600 */
601 if (fw->paging_mem_size) {
e1120187
MG		 602 /*
603 * When dma is not enabled, the driver needs to copy / write
604 * the downloaded / uploaded page to / from the smem.
605 * This gets the location of the place were the pages are
606 * stored.
607 */
608 if (!is_device_dma_capable(mvm->trans->dev)) {
609 ret = iwl_trans_get_paging_item(mvm);
610 if (ret) {
611 IWL_ERR(mvm, "failed to get FW paging item\n");
612 return ret;
613 }
614 }
615
a6c4fb44
MG		 616 ret = iwl_save_fw_paging(mvm, fw);
617 if (ret) {
618 IWL_ERR(mvm, "failed to save the FW paging image\n");
619 return ret;
620 }
621
622 ret = iwl_send_paging_cmd(mvm, fw);
623 if (ret) {
624 IWL_ERR(mvm, "failed to send the paging cmd\n");
625 iwl_free_fw_paging(mvm);
626 return ret;
627 }
628 }
629
8ca151b5
JB		 630 /*
631 * Note: all the queues are enabled as part of the interface
632 * initialization, but in firmware restart scenarios they
633 * could be stopped, so wake them up. In firmware restart,
634 * mac80211 will have the queues stopped as well until the
635 * reconfiguration completes. During normal startup, they
636 * will be empty.
637 */
638
4ecafae9
LK		 639 memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
640 mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1;
8ca151b5 641
df197c00
JB		 642 for (i = 0; i < IEEE80211_MAX_QUEUES; i++)
643 atomic_set(&mvm->mac80211_queue_stop_count[i], 0);
8ca151b5
JB		 644
645 mvm->ucode_loaded = true;
646
647 return 0;
648}
8ca151b5
JB		 649
650static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
651{
652 struct iwl_phy_cfg_cmd phy_cfg_cmd;
653 enum iwl_ucode_type ucode_type = mvm->cur_ucode;
654
655 /* Set parameters */
a0544272 656 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
8ca151b5
JB		 657 phy_cfg_cmd.calib_control.event_trigger =
658 mvm->fw->default_calib[ucode_type].event_trigger;
659 phy_cfg_cmd.calib_control.flow_trigger =
660 mvm->fw->default_calib[ucode_type].flow_trigger;
661
662 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
663 phy_cfg_cmd.phy_cfg);
664
a1022927 665 return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
8ca151b5
JB		 666 sizeof(phy_cfg_cmd), &phy_cfg_cmd);
667}
668
8ca151b5
JB		 669int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
670{
671 struct iwl_notification_wait calib_wait;
6eb031d2 672 static const u16 init_complete[] = {
8ca151b5
JB		 673 INIT_COMPLETE_NOTIF,
674 CALIB_RES_NOTIF_PHY_DB
675 };
676 int ret;
677
678 lockdep_assert_held(&mvm->mutex);
679
8d193ca2 680 if (WARN_ON_ONCE(mvm->calibrating))
8ca151b5
JB		 681 return 0;
682
683 iwl_init_notification_wait(&mvm->notif_wait,
684 &calib_wait,
685 init_complete,
686 ARRAY_SIZE(init_complete),
687 iwl_wait_phy_db_entry,
688 mvm->phy_db);
689
690 /* Will also start the device */
691 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
692 if (ret) {
693 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
694 goto error;
695 }
696
ae397472 697 ret = iwl_send_bt_init_conf(mvm);
931d4160
EG		 698 if (ret)
699 goto error;
700
81a67e32 701 /* Read the NVM only at driver load time, no need to do this twice */
8ca151b5
JB		 702 if (read_nvm) {
703 /* Read nvm */
14b485f0 704 ret = iwl_nvm_init(mvm, true);
8ca151b5
JB		 705 if (ret) {
706 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
707 goto error;
708 }
709 }
710
81a67e32 711 /* In case we read the NVM from external file, load it to the NIC */
e02a9d60 712 if (mvm->nvm_file_name)
81a67e32
EL		 713 iwl_mvm_load_nvm_to_nic(mvm);
714
8ca151b5
JB		 715 ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans);
716 WARN_ON(ret);
717
4f59334b
EH		 718 /*
719 * abort after reading the nvm in case RF Kill is on, we will complete
720 * the init seq later when RF kill will switch to off
721 */
1a3fe0b2 722 if (iwl_mvm_is_radio_hw_killed(mvm)) {
4f59334b
EH		 723 IWL_DEBUG_RF_KILL(mvm,
724 "jump over all phy activities due to RF kill\n");
725 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
a4082843
AN		 726 ret = 1;
727 goto out;
4f59334b
EH		 728 }
729
31b8b343
EG		 730 mvm->calibrating = true;
731
e07cbb53 732 /* Send TX valid antennas before triggering calibrations */
a0544272 733 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53
DS		 734 if (ret)
735 goto error;
736
8ca151b5
JB		 737 /*
738 * Send phy configurations command to init uCode
739 * to start the 16.0 uCode init image internal calibrations.
740 */
741 ret = iwl_send_phy_cfg_cmd(mvm);
742 if (ret) {
743 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
744 ret);
745 goto error;
746 }
747
748 /*
749 * Some things may run in the background now, but we
750 * just wait for the calibration complete notification.
751 */
752 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
753 MVM_UCODE_CALIB_TIMEOUT);
31b8b343 754
1a3fe0b2 755 if (ret && iwl_mvm_is_radio_hw_killed(mvm)) {
31b8b343
EG		 756 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
757 ret = 1;
758 }
8ca151b5
JB		 759 goto out;
760
761error:
762 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
763out:
31b8b343 764 mvm->calibrating = false;
a4082843 765 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB		 766 /* we want to debug INIT and we have no NVM - fake */
767 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
768 sizeof(struct ieee80211_channel) +
769 sizeof(struct ieee80211_rate),
770 GFP_KERNEL);
771 if (!mvm->nvm_data)
772 return -ENOMEM;
8ca151b5
JB		 773 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
774 mvm->nvm_data->bands[0].n_channels = 1;
775 mvm->nvm_data->bands[0].n_bitrates = 1;
776 mvm->nvm_data->bands[0].bitrates =
777 (void *)mvm->nvm_data->channels + 1;
778 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
779 }
780
781 return ret;
782}
783
04fd2c28
LK		 784static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm)
785{
786 struct iwl_host_cmd cmd = {
787 .id = SHARED_MEM_CFG,
788 .flags = CMD_WANT_SKB,
789 .data = { NULL, },
790 .len = { 0, },
791 };
792 struct iwl_rx_packet *pkt;
793 struct iwl_shared_mem_cfg *mem_cfg;
794 u32 i;
795
796 lockdep_assert_held(&mvm->mutex);
797
798 if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd)))
799 return;
800
801 pkt = cmd.resp_pkt;
04fd2c28
LK		 802 mem_cfg = (void *)pkt->data;
803
804 mvm->shared_mem_cfg.shared_mem_addr =
805 le32_to_cpu(mem_cfg->shared_mem_addr);
806 mvm->shared_mem_cfg.shared_mem_size =
807 le32_to_cpu(mem_cfg->shared_mem_size);
808 mvm->shared_mem_cfg.sample_buff_addr =
809 le32_to_cpu(mem_cfg->sample_buff_addr);
810 mvm->shared_mem_cfg.sample_buff_size =
811 le32_to_cpu(mem_cfg->sample_buff_size);
812 mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr);
813 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++)
814 mvm->shared_mem_cfg.txfifo_size[i] =
815 le32_to_cpu(mem_cfg->txfifo_size[i]);
816 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
817 mvm->shared_mem_cfg.rxfifo_size[i] =
818 le32_to_cpu(mem_cfg->rxfifo_size[i]);
819 mvm->shared_mem_cfg.page_buff_addr =
820 le32_to_cpu(mem_cfg->page_buff_addr);
821 mvm->shared_mem_cfg.page_buff_size =
822 le32_to_cpu(mem_cfg->page_buff_size);
823 IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n");
824
04fd2c28
LK		 825 iwl_free_resp(&cmd);
826}
827
84bfffa9
EG		 828static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
829{
830 struct iwl_ltr_config_cmd cmd = {
831 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
832 };
833
834 if (!mvm->trans->ltr_enabled)
835 return 0;
836
84bfffa9
EG		 837 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
838 sizeof(cmd), &cmd);
839}
840
8ca151b5
JB		 841int iwl_mvm_up(struct iwl_mvm *mvm)
842{
843 int ret, i;
53a9d61e
IP		 844 struct ieee80211_channel *chan;
845 struct cfg80211_chan_def chandef;
8ca151b5
JB		 846
847 lockdep_assert_held(&mvm->mutex);
848
849 ret = iwl_trans_start_hw(mvm->trans);
850 if (ret)
851 return ret;
852
ff116373
EL		 853 /*
854 * If we haven't completed the run of the init ucode during
855 * module loading, load init ucode now
856 * (for example, if we were in RFKILL)
857 */
8d193ca2
EH		 858 ret = iwl_run_init_mvm_ucode(mvm, false);
859 if (ret && !iwlmvm_mod_params.init_dbg) {
860 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
861 /* this can't happen */
862 if (WARN_ON(ret > 0))
863 ret = -ERFKILL;
864 goto error;
865 }
866 if (!iwlmvm_mod_params.init_dbg) {
867 /*
868 * Stop and start the transport without entering low power
869 * mode. This will save the state of other components on the
870 * device that are triggered by the INIT firwmare (MFUART).
871 */
872 _iwl_trans_stop_device(mvm->trans, false);
d643c432 873 ret = _iwl_trans_start_hw(mvm->trans, false);
8d193ca2 874 if (ret)
d643c432 875 goto error;
8ca151b5
JB		 876 }
877
878 if (iwlmvm_mod_params.init_dbg)
879 return 0;
880
881 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
882 if (ret) {
883 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
884 goto error;
885 }
886
6c7d32cf 887 iwl_mvm_get_shared_mem_conf(mvm);
04fd2c28 888
1f3b0ff8
LE		 889 ret = iwl_mvm_sf_update(mvm, NULL, false);
890 if (ret)
891 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
892
6a951267 893 mvm->fw_dbg_conf = FW_DBG_INVALID;
945d4202
EG		 894 /* if we have a destination, assume EARLY START */
895 if (mvm->fw->dbg_dest_tlv)
896 mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE;
d2709ad7 897 iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE);
6a951267 898
a0544272 899 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 900 if (ret)
901 goto error;
902
931d4160
EG		 903 ret = iwl_send_bt_init_conf(mvm);
904 if (ret)
905 goto error;
906
8ca151b5
JB		 907 /* Send phy db control command and then phy db calibration*/
908 ret = iwl_send_phy_db_data(mvm->phy_db);
909 if (ret)
910 goto error;
911
912 ret = iwl_send_phy_cfg_cmd(mvm);
913 if (ret)
914 goto error;
915
43413a97
SS		 916 /* Init RSS configuration */
917 if (iwl_mvm_has_new_rx_api(mvm)) {
918 ret = iwl_send_rss_cfg_cmd(mvm);
919 if (ret) {
920 IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
921 ret);
922 goto error;
923 }
924 }
925
8ca151b5
JB		 926 /* init the fw <-> mac80211 STA mapping */
927 for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
928 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
929
1d3c3f63
AN		 930 mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT;
931
b2b7875b
JB		 932 /* reset quota debouncing buffer - 0xff will yield invalid data */
933 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
934
8ca151b5
JB		 935 /* Add auxiliary station for scanning */
936 ret = iwl_mvm_add_aux_sta(mvm);
937 if (ret)
938 goto error;
939
53a9d61e
IP		 940 /* Add all the PHY contexts */
941 chan = &mvm->hw->wiphy->bands[IEEE80211_BAND_2GHZ]->channels[0];
942 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
943 for (i = 0; i < NUM_PHY_CTX; i++) {
944 /*
945 * The channel used here isn't relevant as it's
946 * going to be overwritten in the other flows.
947 * For now use the first channel we have.
948 */
949 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
950 &chandef, 1, 1);
951 if (ret)
952 goto error;
953 }
8ca151b5 954
c221daf2
CRI		 955#ifdef CONFIG_THERMAL
956 if (iwl_mvm_is_tt_in_fw(mvm)) {
957 /* in order to give the responsibility of ct-kill and
958 * TX backoff to FW we need to send empty temperature reporting
959 * cmd during init time
960 */
961 iwl_mvm_send_temp_report_ths_cmd(mvm);
962 } else {
963 /* Initialize tx backoffs to the minimal possible */
964 iwl_mvm_tt_tx_backoff(mvm, 0);
965 }
5c89e7bc
CRI		 966
967 /* TODO: read the budget from BIOS / Platform NVM */
968 if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0)
969 ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
970 mvm->cooling_dev.cur_state);
c221daf2 971#else
0c0e2c71
IY		 972 /* Initialize tx backoffs to the minimal possible */
973 iwl_mvm_tt_tx_backoff(mvm, 0);
c221daf2 974#endif
0c0e2c71 975
84bfffa9 976 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 977
c1cb92fc 978 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB		 979 if (ret)
980 goto error;
981
35af15d1
AN		 982 /*
983 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
984 * anyway, so don't init MCC.
985 */
986 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
987 ret = iwl_mvm_init_mcc(mvm);
988 if (ret)
989 goto error;
990 }
90d4f7db 991
859d914c 992 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
4ca87a5f 993 mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
d2496221
DS		 994 ret = iwl_mvm_config_scan(mvm);
995 if (ret)
996 goto error;
997 }
998
93190fb0
AA		 999 if (iwl_mvm_is_csum_supported(mvm) &&
1000 mvm->cfg->features & NETIF_F_RXCSUM)
1001 iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3);
1002
7498cf4c
EP		 1003 /* allow FW/transport low power modes if not during restart */
1004 if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1005 iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN);
1006
53a9d61e 1007 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB		 1008 return 0;
1009 error:
1010 iwl_trans_stop_device(mvm->trans);
1011 return ret;
1012}
1013
1014int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1015{
1016 int ret, i;
1017
1018 lockdep_assert_held(&mvm->mutex);
1019
1020 ret = iwl_trans_start_hw(mvm->trans);
1021 if (ret)
1022 return ret;
1023
1024 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1025 if (ret) {
1026 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1027 goto error;
1028 }
1029
a0544272 1030 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1031 if (ret)
1032 goto error;
1033
1034 /* Send phy db control command and then phy db calibration*/
1035 ret = iwl_send_phy_db_data(mvm->phy_db);
1036 if (ret)
1037 goto error;
1038
1039 ret = iwl_send_phy_cfg_cmd(mvm);
1040 if (ret)
1041 goto error;
1042
1043 /* init the fw <-> mac80211 STA mapping */
1044 for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
1045 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1046
1047 /* Add auxiliary station for scanning */
1048 ret = iwl_mvm_add_aux_sta(mvm);
1049 if (ret)
1050 goto error;
1051
1052 return 0;
1053 error:
1054 iwl_trans_stop_device(mvm->trans);
1055 return ret;
1056}
1057
0416841d
JB		 1058void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
1059 struct iwl_rx_cmd_buffer *rxb)
8ca151b5
JB		 1060{
1061 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1062 struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
1063 u32 flags = le32_to_cpu(card_state_notif->flags);
1064
1065 IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
1066 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1067 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
1068 (flags & CT_KILL_CARD_DISABLED) ?
1069 "Reached" : "Not reached");
8ca151b5
JB		 1070}
1071
0416841d
JB		 1072void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1073 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI		 1074{
1075 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1076 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1077
1078 IWL_DEBUG_INFO(mvm,
1079 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1080 le32_to_cpu(mfuart_notif->installed_ver),
1081 le32_to_cpu(mfuart_notif->external_ver),
1082 le32_to_cpu(mfuart_notif->status),
1083 le32_to_cpu(mfuart_notif->duration));
30269c12 1084}
Linux kernel - Deliverables
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