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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
4fb06283 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
6fa52430 | 10 | * Copyright(c) 2016 Intel Deutschland GmbH |
8ca151b5 JB |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of version 2 of the GNU General Public License as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
24 | * USA | |
25 | * | |
26 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 27 | * in the file called COPYING. |
8ca151b5 JB |
28 | * |
29 | * Contact Information: | |
cb2f8277 | 30 | * Intel Linux Wireless <linuxwifi@intel.com> |
8ca151b5 JB |
31 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
32 | * | |
33 | * BSD LICENSE | |
34 | * | |
51368bf7 | 35 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
4fb06283 | 36 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
6fa52430 | 37 | * Copyright(c) 2016 Intel Deutschland GmbH |
8ca151b5 JB |
38 | * All rights reserved. |
39 | * | |
40 | * Redistribution and use in source and binary forms, with or without | |
41 | * modification, are permitted provided that the following conditions | |
42 | * are met: | |
43 | * | |
44 | * * Redistributions of source code must retain the above copyright | |
45 | * notice, this list of conditions and the following disclaimer. | |
46 | * * Redistributions in binary form must reproduce the above copyright | |
47 | * notice, this list of conditions and the following disclaimer in | |
48 | * the documentation and/or other materials provided with the | |
49 | * distribution. | |
50 | * * Neither the name Intel Corporation nor the names of its | |
51 | * contributors may be used to endorse or promote products derived | |
52 | * from this software without specific prior written permission. | |
53 | * | |
54 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
55 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
56 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
57 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
58 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
59 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
60 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
61 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
62 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
63 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
64 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
65 | * | |
66 | *****************************************************************************/ | |
1214755c | 67 | #include <linux/firmware.h> |
90d4f7db | 68 | #include <linux/rtnetlink.h> |
7f0344c2 JD |
69 | #include <linux/pci.h> |
70 | #include <linux/acpi.h> | |
8ca151b5 | 71 | #include "iwl-trans.h" |
c2a2b28b | 72 | #include "iwl-csr.h" |
8ca151b5 JB |
73 | #include "mvm.h" |
74 | #include "iwl-eeprom-parse.h" | |
75 | #include "iwl-eeprom-read.h" | |
76 | #include "iwl-nvm-parse.h" | |
8ba2d7a1 | 77 | #include "iwl-prph.h" |
8ca151b5 | 78 | |
1fd4afe2 | 79 | /* Default NVM size to read */ |
1214755c | 80 | #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024) |
f251c07c | 81 | #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 |
5dd9c68a | 82 | #define IWL_MAX_NVM_8000_SECTION_SIZE 0x1ffc |
1fd4afe2 | 83 | |
1214755c EH |
84 | #define NVM_WRITE_OPCODE 1 |
85 | #define NVM_READ_OPCODE 0 | |
86 | ||
d6aeb354 EH |
87 | /* load nvm chunk response */ |
88 | enum { | |
89 | READ_NVM_CHUNK_SUCCEED = 0, | |
90 | READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 | |
91 | }; | |
92 | ||
1214755c EH |
93 | /* |
94 | * prepare the NVM host command w/ the pointers to the nvm buffer | |
95 | * and send it to fw | |
96 | */ | |
97 | static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, | |
98 | u16 offset, u16 length, const u8 *data) | |
8ca151b5 | 99 | { |
1214755c EH |
100 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
101 | .offset = cpu_to_le16(offset), | |
102 | .length = cpu_to_le16(length), | |
103 | .type = cpu_to_le16(section), | |
104 | .op_code = NVM_WRITE_OPCODE, | |
105 | }; | |
106 | struct iwl_host_cmd cmd = { | |
107 | .id = NVM_ACCESS_CMD, | |
108 | .len = { sizeof(struct iwl_nvm_access_cmd), length }, | |
9a57f650 | 109 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
1214755c EH |
110 | .data = { &nvm_access_cmd, data }, |
111 | /* data may come from vmalloc, so use _DUP */ | |
112 | .dataflags = { 0, IWL_HCMD_DFL_DUP }, | |
113 | }; | |
9a57f650 MG |
114 | struct iwl_rx_packet *pkt; |
115 | struct iwl_nvm_access_resp *nvm_resp; | |
116 | int ret; | |
1214755c | 117 | |
9a57f650 MG |
118 | ret = iwl_mvm_send_cmd(mvm, &cmd); |
119 | if (ret) | |
120 | return ret; | |
121 | ||
122 | pkt = cmd.resp_pkt; | |
123 | if (!pkt) { | |
124 | IWL_ERR(mvm, "Error in NVM_ACCESS response\n"); | |
125 | return -EINVAL; | |
126 | } | |
127 | /* Extract & check NVM write response */ | |
128 | nvm_resp = (void *)pkt->data; | |
129 | if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) { | |
130 | IWL_ERR(mvm, | |
131 | "NVM access write command failed for section %u (status = 0x%x)\n", | |
132 | section, le16_to_cpu(nvm_resp->status)); | |
133 | ret = -EIO; | |
134 | } | |
135 | ||
136 | iwl_free_resp(&cmd); | |
137 | return ret; | |
8ca151b5 JB |
138 | } |
139 | ||
140 | static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, | |
141 | u16 offset, u16 length, u8 *data) | |
142 | { | |
1214755c EH |
143 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
144 | .offset = cpu_to_le16(offset), | |
145 | .length = cpu_to_le16(length), | |
146 | .type = cpu_to_le16(section), | |
147 | .op_code = NVM_READ_OPCODE, | |
148 | }; | |
b9545b48 | 149 | struct iwl_nvm_access_resp *nvm_resp; |
8ca151b5 JB |
150 | struct iwl_rx_packet *pkt; |
151 | struct iwl_host_cmd cmd = { | |
152 | .id = NVM_ACCESS_CMD, | |
a1022927 | 153 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
8ca151b5 JB |
154 | .data = { &nvm_access_cmd, }, |
155 | }; | |
156 | int ret, bytes_read, offset_read; | |
157 | u8 *resp_data; | |
158 | ||
b9545b48 | 159 | cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); |
8ca151b5 JB |
160 | |
161 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
162 | if (ret) | |
163 | return ret; | |
164 | ||
165 | pkt = cmd.resp_pkt; | |
8ca151b5 JB |
166 | |
167 | /* Extract NVM response */ | |
168 | nvm_resp = (void *)pkt->data; | |
b9545b48 EG |
169 | ret = le16_to_cpu(nvm_resp->status); |
170 | bytes_read = le16_to_cpu(nvm_resp->length); | |
171 | offset_read = le16_to_cpu(nvm_resp->offset); | |
172 | resp_data = nvm_resp->data; | |
8ca151b5 | 173 | if (ret) { |
d6aeb354 EH |
174 | if ((offset != 0) && |
175 | (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { | |
176 | /* | |
177 | * meaning of NOT_VALID_ADDRESS: | |
178 | * driver try to read chunk from address that is | |
179 | * multiple of 2K and got an error since addr is empty. | |
180 | * meaning of (offset != 0): driver already | |
181 | * read valid data from another chunk so this case | |
182 | * is not an error. | |
183 | */ | |
184 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
185 | "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", | |
186 | offset); | |
187 | ret = 0; | |
188 | } else { | |
189 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
190 | "NVM access command failed with status %d (device: %s)\n", | |
191 | ret, mvm->cfg->name); | |
192 | ret = -EIO; | |
193 | } | |
8ca151b5 JB |
194 | goto exit; |
195 | } | |
196 | ||
197 | if (offset_read != offset) { | |
198 | IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", | |
199 | offset_read); | |
200 | ret = -EINVAL; | |
201 | goto exit; | |
202 | } | |
203 | ||
204 | /* Write data to NVM */ | |
205 | memcpy(data + offset, resp_data, bytes_read); | |
206 | ret = bytes_read; | |
207 | ||
208 | exit: | |
209 | iwl_free_resp(&cmd); | |
210 | return ret; | |
211 | } | |
212 | ||
1214755c EH |
213 | static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, |
214 | const u8 *data, u16 length) | |
215 | { | |
216 | int offset = 0; | |
217 | ||
218 | /* copy data in chunks of 2k (and remainder if any) */ | |
219 | ||
220 | while (offset < length) { | |
221 | int chunk_size, ret; | |
222 | ||
223 | chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, | |
224 | length - offset); | |
225 | ||
226 | ret = iwl_nvm_write_chunk(mvm, section, offset, | |
227 | chunk_size, data + offset); | |
228 | if (ret < 0) | |
229 | return ret; | |
230 | ||
231 | offset += chunk_size; | |
232 | } | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
7d162045 JB |
237 | static void iwl_mvm_nvm_fixups(struct iwl_mvm *mvm, unsigned int section, |
238 | u8 *data, unsigned int len) | |
239 | { | |
240 | #define IWL_4165_DEVICE_ID 0x5501 | |
241 | #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) | |
242 | ||
243 | if (section == NVM_SECTION_TYPE_PHY_SKU && | |
244 | mvm->trans->hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && | |
245 | (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) | |
246 | /* OTP 0x52 bug work around: it's a 1x1 device */ | |
247 | data[3] = ANT_B | (ANT_B << 4); | |
248 | } | |
249 | ||
8ca151b5 JB |
250 | /* |
251 | * Reads an NVM section completely. | |
252 | * NICs prior to 7000 family doesn't have a real NVM, but just read | |
253 | * section 0 which is the EEPROM. Because the EEPROM reading is unlimited | |
254 | * by uCode, we need to manually check in this case that we don't | |
255 | * overflow and try to read more than the EEPROM size. | |
256 | * For 7000 family NICs, we supply the maximal size we can read, and | |
257 | * the uCode fills the response with as much data as we can, | |
258 | * without overflowing, so no check is needed. | |
259 | */ | |
260 | static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, | |
5daddc99 | 261 | u8 *data, u32 size_read) |
8ca151b5 JB |
262 | { |
263 | u16 length, offset = 0; | |
264 | int ret; | |
8ca151b5 | 265 | |
1fd4afe2 DS |
266 | /* Set nvm section read length */ |
267 | length = IWL_NVM_DEFAULT_CHUNK_SIZE; | |
268 | ||
8ca151b5 JB |
269 | ret = length; |
270 | ||
271 | /* Read the NVM until exhausted (reading less than requested) */ | |
272 | while (ret == length) { | |
5daddc99 LK |
273 | /* Check no memory assumptions fail and cause an overflow */ |
274 | if ((size_read + offset + length) > | |
275 | mvm->cfg->base_params->eeprom_size) { | |
276 | IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); | |
277 | return -ENOBUFS; | |
278 | } | |
279 | ||
8ca151b5 JB |
280 | ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); |
281 | if (ret < 0) { | |
d6aeb354 EH |
282 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
283 | "Cannot read NVM from section %d offset %d, length %d\n", | |
284 | section, offset, length); | |
8ca151b5 JB |
285 | return ret; |
286 | } | |
287 | offset += ret; | |
8ca151b5 JB |
288 | } |
289 | ||
7d162045 JB |
290 | iwl_mvm_nvm_fixups(mvm, section, data, offset); |
291 | ||
07fd7d28 JB |
292 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
293 | "NVM section %d read completed\n", section); | |
8ca151b5 JB |
294 | return offset; |
295 | } | |
296 | ||
297 | static struct iwl_nvm_data * | |
298 | iwl_parse_nvm_sections(struct iwl_mvm *mvm) | |
299 | { | |
300 | struct iwl_nvm_section *sections = mvm->nvm_sections; | |
ce500071 | 301 | const __le16 *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku; |
5dd9c68a | 302 | bool lar_enabled; |
8ca151b5 JB |
303 | |
304 | /* Checking for required sections */ | |
77db0a3c EH |
305 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
306 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || | |
307 | !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { | |
abf09c56 | 308 | IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); |
77db0a3c EH |
309 | return NULL; |
310 | } | |
311 | } else { | |
9f32e017 | 312 | /* SW and REGULATORY sections are mandatory */ |
77db0a3c | 313 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
77db0a3c EH |
314 | !mvm->nvm_sections[NVM_SECTION_TYPE_REGULATORY].data) { |
315 | IWL_ERR(mvm, | |
abf09c56 | 316 | "Can't parse empty family 8000 OTP/NVM sections\n"); |
77db0a3c EH |
317 | return NULL; |
318 | } | |
9f32e017 | 319 | /* MAC_OVERRIDE or at least HW section must exist */ |
bb926924 | 320 | if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && |
9f32e017 EH |
321 | !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { |
322 | IWL_ERR(mvm, | |
323 | "Can't parse mac_address, empty sections\n"); | |
324 | return NULL; | |
325 | } | |
ce500071 | 326 | |
ce500071 | 327 | /* PHY_SKU section is mandatory in B0 */ |
5dd9c68a | 328 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) { |
ce500071 EH |
329 | IWL_ERR(mvm, |
330 | "Can't parse phy_sku in B0, empty sections\n"); | |
331 | return NULL; | |
332 | } | |
8ca151b5 JB |
333 | } |
334 | ||
335 | if (WARN_ON(!mvm->cfg)) | |
336 | return NULL; | |
337 | ||
ae2b21b0 | 338 | hw = (const __le16 *)sections[mvm->cfg->nvm_hw_section_num].data; |
8ca151b5 JB |
339 | sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; |
340 | calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; | |
77db0a3c EH |
341 | regulatory = (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; |
342 | mac_override = | |
343 | (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; | |
ce500071 | 344 | phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data; |
77db0a3c | 345 | |
5711cac4 | 346 | lar_enabled = !iwlwifi_mod_params.lar_disable && |
859d914c JB |
347 | fw_has_capa(&mvm->fw->ucode_capa, |
348 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
5711cac4 | 349 | |
afd5b170 | 350 | return iwl_parse_nvm_data(mvm->trans, mvm->cfg, hw, sw, calib, |
ce500071 | 351 | regulatory, mac_override, phy_sku, |
5711cac4 | 352 | mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant, |
afd5b170 | 353 | lar_enabled); |
8ca151b5 JB |
354 | } |
355 | ||
1214755c EH |
356 | #define MAX_NVM_FILE_LEN 16384 |
357 | ||
358 | /* | |
81a67e32 EL |
359 | * Reads external NVM from a file into mvm->nvm_sections |
360 | * | |
1214755c EH |
361 | * HOW TO CREATE THE NVM FILE FORMAT: |
362 | * ------------------------------ | |
363 | * 1. create hex file, format: | |
364 | * 3800 -> header | |
365 | * 0000 -> header | |
366 | * 5a40 -> data | |
367 | * | |
368 | * rev - 6 bit (word1) | |
369 | * len - 10 bit (word1) | |
370 | * id - 4 bit (word2) | |
371 | * rsv - 12 bit (word2) | |
372 | * | |
373 | * 2. flip 8bits with 8 bits per line to get the right NVM file format | |
374 | * | |
375 | * 3. create binary file from the hex file | |
376 | * | |
377 | * 4. save as "iNVM_xxx.bin" under /lib/firmware | |
378 | */ | |
81a67e32 | 379 | static int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm) |
1214755c | 380 | { |
81a67e32 EL |
381 | int ret, section_size; |
382 | u16 section_id; | |
1214755c EH |
383 | const struct firmware *fw_entry; |
384 | const struct { | |
385 | __le16 word1; | |
386 | __le16 word2; | |
387 | u8 data[]; | |
388 | } *file_sec; | |
7d162045 JB |
389 | const u8 *eof; |
390 | u8 *temp; | |
f251c07c | 391 | int max_section_size; |
a4e5df28 | 392 | const __le32 *dword_buff; |
1214755c EH |
393 | |
394 | #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) | |
395 | #define NVM_WORD2_ID(x) (x >> 12) | |
77db0a3c EH |
396 | #define NVM_WORD2_LEN_FAMILY_8000(x) (2 * ((x & 0xFF) << 8 | x >> 8)) |
397 | #define NVM_WORD1_ID_FAMILY_8000(x) (x >> 4) | |
a4e5df28 IK |
398 | #define NVM_HEADER_0 (0x2A504C54) |
399 | #define NVM_HEADER_1 (0x4E564D2A) | |
400 | #define NVM_HEADER_SIZE (4 * sizeof(u32)) | |
1214755c | 401 | |
81a67e32 EL |
402 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n"); |
403 | ||
f251c07c LK |
404 | /* Maximal size depends on HW family and step */ |
405 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
406 | max_section_size = IWL_MAX_NVM_SECTION_SIZE; | |
5dd9c68a EG |
407 | else |
408 | max_section_size = IWL_MAX_NVM_8000_SECTION_SIZE; | |
f251c07c | 409 | |
1214755c EH |
410 | /* |
411 | * Obtain NVM image via request_firmware. Since we already used | |
412 | * request_firmware_nowait() for the firmware binary load and only | |
413 | * get here after that we assume the NVM request can be satisfied | |
414 | * synchronously. | |
415 | */ | |
e02a9d60 | 416 | ret = request_firmware(&fw_entry, mvm->nvm_file_name, |
1214755c EH |
417 | mvm->trans->dev); |
418 | if (ret) { | |
419 | IWL_ERR(mvm, "ERROR: %s isn't available %d\n", | |
e02a9d60 | 420 | mvm->nvm_file_name, ret); |
1214755c EH |
421 | return ret; |
422 | } | |
423 | ||
424 | IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n", | |
e02a9d60 | 425 | mvm->nvm_file_name, fw_entry->size); |
1214755c | 426 | |
1214755c EH |
427 | if (fw_entry->size > MAX_NVM_FILE_LEN) { |
428 | IWL_ERR(mvm, "NVM file too large\n"); | |
429 | ret = -EINVAL; | |
430 | goto out; | |
431 | } | |
432 | ||
433 | eof = fw_entry->data + fw_entry->size; | |
a4e5df28 IK |
434 | dword_buff = (__le32 *)fw_entry->data; |
435 | ||
436 | /* some NVM file will contain a header. | |
437 | * The header is identified by 2 dwords header as follow: | |
438 | * dword[0] = 0x2A504C54 | |
439 | * dword[1] = 0x4E564D2A | |
440 | * | |
441 | * This header must be skipped when providing the NVM data to the FW. | |
442 | */ | |
443 | if (fw_entry->size > NVM_HEADER_SIZE && | |
444 | dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && | |
445 | dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { | |
446 | file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); | |
447 | IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); | |
448 | IWL_INFO(mvm, "NVM Manufacturing date %08X\n", | |
449 | le32_to_cpu(dword_buff[3])); | |
d383c740 EH |
450 | |
451 | /* nvm file validation, dword_buff[2] holds the file version */ | |
452 | if ((CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_C_STEP && | |
453 | le32_to_cpu(dword_buff[2]) < 0xE4A) || | |
454 | (CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP && | |
455 | le32_to_cpu(dword_buff[2]) >= 0xE4A)) { | |
456 | ret = -EFAULT; | |
457 | goto out; | |
458 | } | |
a4e5df28 IK |
459 | } else { |
460 | file_sec = (void *)fw_entry->data; | |
461 | } | |
1214755c EH |
462 | |
463 | while (true) { | |
464 | if (file_sec->data > eof) { | |
465 | IWL_ERR(mvm, | |
466 | "ERROR - NVM file too short for section header\n"); | |
467 | ret = -EINVAL; | |
468 | break; | |
469 | } | |
470 | ||
471 | /* check for EOF marker */ | |
472 | if (!file_sec->word1 && !file_sec->word2) { | |
473 | ret = 0; | |
474 | break; | |
475 | } | |
476 | ||
77db0a3c EH |
477 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
478 | section_size = | |
479 | 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); | |
480 | section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); | |
481 | } else { | |
482 | section_size = 2 * NVM_WORD2_LEN_FAMILY_8000( | |
483 | le16_to_cpu(file_sec->word2)); | |
484 | section_id = NVM_WORD1_ID_FAMILY_8000( | |
485 | le16_to_cpu(file_sec->word1)); | |
486 | } | |
1214755c | 487 | |
f251c07c | 488 | if (section_size > max_section_size) { |
1214755c EH |
489 | IWL_ERR(mvm, "ERROR - section too large (%d)\n", |
490 | section_size); | |
491 | ret = -EINVAL; | |
492 | break; | |
493 | } | |
494 | ||
495 | if (!section_size) { | |
496 | IWL_ERR(mvm, "ERROR - section empty\n"); | |
497 | ret = -EINVAL; | |
498 | break; | |
499 | } | |
500 | ||
501 | if (file_sec->data + section_size > eof) { | |
502 | IWL_ERR(mvm, | |
503 | "ERROR - NVM file too short for section (%d bytes)\n", | |
504 | section_size); | |
505 | ret = -EINVAL; | |
506 | break; | |
507 | } | |
508 | ||
ae2b21b0 | 509 | if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, |
a4a12478 EL |
510 | "Invalid NVM section ID %d\n", section_id)) { |
511 | ret = -EINVAL; | |
512 | break; | |
513 | } | |
514 | ||
81a67e32 EL |
515 | temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); |
516 | if (!temp) { | |
517 | ret = -ENOMEM; | |
518 | break; | |
519 | } | |
7d162045 JB |
520 | |
521 | iwl_mvm_nvm_fixups(mvm, section_id, temp, section_size); | |
522 | ||
2edb7a33 | 523 | kfree(mvm->nvm_sections[section_id].data); |
81a67e32 EL |
524 | mvm->nvm_sections[section_id].data = temp; |
525 | mvm->nvm_sections[section_id].length = section_size; | |
1214755c EH |
526 | |
527 | /* advance to the next section */ | |
528 | file_sec = (void *)(file_sec->data + section_size); | |
529 | } | |
530 | out: | |
531 | release_firmware(fw_entry); | |
532 | return ret; | |
533 | } | |
534 | ||
81a67e32 EL |
535 | /* Loads the NVM data stored in mvm->nvm_sections into the NIC */ |
536 | int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) | |
537 | { | |
05159fcc | 538 | int i, ret = 0; |
81a67e32 EL |
539 | struct iwl_nvm_section *sections = mvm->nvm_sections; |
540 | ||
541 | IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); | |
542 | ||
099d8f20 EG |
543 | for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { |
544 | if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) | |
545 | continue; | |
546 | ret = iwl_nvm_write_section(mvm, i, sections[i].data, | |
547 | sections[i].length); | |
81a67e32 EL |
548 | if (ret < 0) { |
549 | IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); | |
550 | break; | |
551 | } | |
552 | } | |
553 | return ret; | |
554 | } | |
555 | ||
14b485f0 | 556 | int iwl_nvm_init(struct iwl_mvm *mvm, bool read_nvm_from_nic) |
8ca151b5 | 557 | { |
d6aeb354 | 558 | int ret, section; |
5daddc99 | 559 | u32 size_read = 0; |
8ca151b5 | 560 | u8 *nvm_buffer, *temp; |
d383c740 EH |
561 | const char *nvm_file_B = mvm->cfg->default_nvm_file_B_step; |
562 | const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step; | |
8ca151b5 | 563 | |
ae2b21b0 EH |
564 | if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) |
565 | return -EINVAL; | |
566 | ||
26481bf4 | 567 | /* load NVM values from nic */ |
14b485f0 | 568 | if (read_nvm_from_nic) { |
81a67e32 EL |
569 | /* Read From FW NVM */ |
570 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); | |
571 | ||
81a67e32 EL |
572 | nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size, |
573 | GFP_KERNEL); | |
574 | if (!nvm_buffer) | |
575 | return -ENOMEM; | |
d6aeb354 | 576 | for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { |
81a67e32 | 577 | /* we override the constness for initial read */ |
5daddc99 LK |
578 | ret = iwl_nvm_read_section(mvm, section, nvm_buffer, |
579 | size_read); | |
81a67e32 | 580 | if (ret < 0) |
d6aeb354 | 581 | continue; |
5daddc99 | 582 | size_read += ret; |
81a67e32 EL |
583 | temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); |
584 | if (!temp) { | |
585 | ret = -ENOMEM; | |
586 | break; | |
587 | } | |
7d162045 JB |
588 | |
589 | iwl_mvm_nvm_fixups(mvm, section, temp, ret); | |
590 | ||
81a67e32 EL |
591 | mvm->nvm_sections[section].data = temp; |
592 | mvm->nvm_sections[section].length = ret; | |
086f7368 EG |
593 | |
594 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
595 | switch (section) { | |
086f7368 EG |
596 | case NVM_SECTION_TYPE_SW: |
597 | mvm->nvm_sw_blob.data = temp; | |
598 | mvm->nvm_sw_blob.size = ret; | |
599 | break; | |
600 | case NVM_SECTION_TYPE_CALIBRATION: | |
601 | mvm->nvm_calib_blob.data = temp; | |
602 | mvm->nvm_calib_blob.size = ret; | |
603 | break; | |
604 | case NVM_SECTION_TYPE_PRODUCTION: | |
605 | mvm->nvm_prod_blob.data = temp; | |
606 | mvm->nvm_prod_blob.size = ret; | |
607 | break; | |
91fac940 MH |
608 | case NVM_SECTION_TYPE_PHY_SKU: |
609 | mvm->nvm_phy_sku_blob.data = temp; | |
610 | mvm->nvm_phy_sku_blob.size = ret; | |
611 | break; | |
086f7368 | 612 | default: |
ae2b21b0 EH |
613 | if (section == mvm->cfg->nvm_hw_section_num) { |
614 | mvm->nvm_hw_blob.data = temp; | |
615 | mvm->nvm_hw_blob.size = ret; | |
616 | break; | |
617 | } | |
086f7368 EG |
618 | } |
619 | #endif | |
8ca151b5 | 620 | } |
bdce40f0 EH |
621 | if (!size_read) |
622 | IWL_ERR(mvm, "OTP is blank\n"); | |
81a67e32 | 623 | kfree(nvm_buffer); |
8ca151b5 JB |
624 | } |
625 | ||
4fb06283 | 626 | /* Only if PNVM selected in the mod param - load external NVM */ |
e02a9d60 | 627 | if (mvm->nvm_file_name) { |
4fb06283 | 628 | /* read External NVM file from the mod param */ |
26481bf4 | 629 | ret = iwl_mvm_read_external_nvm(mvm); |
d383c740 EH |
630 | if (ret) { |
631 | /* choose the nvm_file name according to the | |
632 | * HW step | |
633 | */ | |
634 | if (CSR_HW_REV_STEP(mvm->trans->hw_rev) == | |
635 | SILICON_B_STEP) | |
636 | mvm->nvm_file_name = nvm_file_B; | |
637 | else | |
638 | mvm->nvm_file_name = nvm_file_C; | |
639 | ||
488c28e1 OG |
640 | if ((ret == -EFAULT || ret == -ENOENT) && |
641 | mvm->nvm_file_name) { | |
d383c740 EH |
642 | /* in case nvm file was failed try again */ |
643 | ret = iwl_mvm_read_external_nvm(mvm); | |
644 | if (ret) | |
645 | return ret; | |
646 | } else { | |
647 | return ret; | |
648 | } | |
649 | } | |
26481bf4 EH |
650 | } |
651 | ||
652 | /* parse the relevant nvm sections */ | |
b9545b48 | 653 | mvm->nvm_data = iwl_parse_nvm_sections(mvm); |
82598b4f JB |
654 | if (!mvm->nvm_data) |
655 | return -ENODATA; | |
2a831e08 EH |
656 | IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", |
657 | mvm->nvm_data->nvm_version); | |
8ca151b5 | 658 | |
82598b4f | 659 | return 0; |
8ca151b5 | 660 | } |
dcaf9f5e AN |
661 | |
662 | struct iwl_mcc_update_resp * | |
8ba2d7a1 EH |
663 | iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2, |
664 | enum iwl_mcc_source src_id) | |
dcaf9f5e AN |
665 | { |
666 | struct iwl_mcc_update_cmd mcc_update_cmd = { | |
667 | .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), | |
8ba2d7a1 | 668 | .source_id = (u8)src_id, |
dcaf9f5e AN |
669 | }; |
670 | struct iwl_mcc_update_resp *mcc_resp, *resp_cp = NULL; | |
6fa52430 | 671 | struct iwl_mcc_update_resp_v1 *mcc_resp_v1 = NULL; |
dcaf9f5e AN |
672 | struct iwl_rx_packet *pkt; |
673 | struct iwl_host_cmd cmd = { | |
674 | .id = MCC_UPDATE_CMD, | |
675 | .flags = CMD_WANT_SKB, | |
676 | .data = { &mcc_update_cmd }, | |
677 | }; | |
678 | ||
679 | int ret; | |
680 | u32 status; | |
681 | int resp_len, n_channels; | |
682 | u16 mcc; | |
6fa52430 MG |
683 | bool resp_v2 = fw_has_capa(&mvm->fw->ucode_capa, |
684 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V2); | |
dcaf9f5e AN |
685 | |
686 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
687 | return ERR_PTR(-EOPNOTSUPP); | |
688 | ||
689 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); | |
6fa52430 MG |
690 | if (!resp_v2) |
691 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd_v1); | |
dcaf9f5e | 692 | |
8ba2d7a1 EH |
693 | IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n", |
694 | alpha2[0], alpha2[1], src_id); | |
dcaf9f5e AN |
695 | |
696 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
697 | if (ret) | |
698 | return ERR_PTR(ret); | |
699 | ||
700 | pkt = cmd.resp_pkt; | |
dcaf9f5e AN |
701 | |
702 | /* Extract MCC response */ | |
6fa52430 MG |
703 | if (resp_v2) { |
704 | mcc_resp = (void *)pkt->data; | |
705 | n_channels = __le32_to_cpu(mcc_resp->n_channels); | |
706 | } else { | |
707 | mcc_resp_v1 = (void *)pkt->data; | |
708 | n_channels = __le32_to_cpu(mcc_resp_v1->n_channels); | |
709 | } | |
dcaf9f5e | 710 | |
6fa52430 MG |
711 | resp_len = sizeof(struct iwl_mcc_update_resp) + n_channels * |
712 | sizeof(__le32); | |
713 | ||
714 | resp_cp = kzalloc(resp_len, GFP_KERNEL); | |
715 | if (!resp_cp) { | |
716 | ret = -ENOMEM; | |
717 | goto exit; | |
718 | } | |
719 | ||
720 | if (resp_v2) { | |
721 | memcpy(resp_cp, mcc_resp, resp_len); | |
722 | } else { | |
723 | resp_cp->status = mcc_resp_v1->status; | |
724 | resp_cp->mcc = mcc_resp_v1->mcc; | |
725 | resp_cp->cap = mcc_resp_v1->cap; | |
726 | resp_cp->source_id = mcc_resp_v1->source_id; | |
727 | resp_cp->n_channels = mcc_resp_v1->n_channels; | |
728 | memcpy(resp_cp->channels, mcc_resp_v1->channels, | |
729 | n_channels * sizeof(__le32)); | |
730 | } | |
731 | ||
732 | status = le32_to_cpu(resp_cp->status); | |
733 | ||
734 | mcc = le16_to_cpu(resp_cp->mcc); | |
dcaf9f5e AN |
735 | |
736 | /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ | |
737 | if (mcc == 0) { | |
738 | mcc = 0x3030; /* "00" - world */ | |
6fa52430 | 739 | resp_cp->mcc = cpu_to_le16(mcc); |
dcaf9f5e AN |
740 | } |
741 | ||
dcaf9f5e AN |
742 | IWL_DEBUG_LAR(mvm, |
743 | "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n", | |
744 | status, mcc, mcc >> 8, mcc & 0xff, | |
47c8b154 | 745 | !!(status == MCC_RESP_NEW_CHAN_PROFILE), n_channels); |
dcaf9f5e | 746 | |
dcaf9f5e AN |
747 | exit: |
748 | iwl_free_resp(&cmd); | |
749 | if (ret) | |
750 | return ERR_PTR(ret); | |
751 | return resp_cp; | |
752 | } | |
90d4f7db | 753 | |
7f0344c2 JD |
754 | #ifdef CONFIG_ACPI |
755 | #define WRD_METHOD "WRDD" | |
756 | #define WRDD_WIFI (0x07) | |
757 | #define WRDD_WIGIG (0x10) | |
758 | ||
759 | static u32 iwl_mvm_wrdd_get_mcc(struct iwl_mvm *mvm, union acpi_object *wrdd) | |
760 | { | |
761 | union acpi_object *mcc_pkg, *domain_type, *mcc_value; | |
762 | u32 i; | |
763 | ||
764 | if (wrdd->type != ACPI_TYPE_PACKAGE || | |
765 | wrdd->package.count < 2 || | |
766 | wrdd->package.elements[0].type != ACPI_TYPE_INTEGER || | |
767 | wrdd->package.elements[0].integer.value != 0) { | |
768 | IWL_DEBUG_LAR(mvm, "Unsupported wrdd structure\n"); | |
769 | return 0; | |
770 | } | |
771 | ||
772 | for (i = 1 ; i < wrdd->package.count ; ++i) { | |
773 | mcc_pkg = &wrdd->package.elements[i]; | |
774 | ||
775 | if (mcc_pkg->type != ACPI_TYPE_PACKAGE || | |
776 | mcc_pkg->package.count < 2 || | |
777 | mcc_pkg->package.elements[0].type != ACPI_TYPE_INTEGER || | |
778 | mcc_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) { | |
779 | mcc_pkg = NULL; | |
780 | continue; | |
781 | } | |
782 | ||
783 | domain_type = &mcc_pkg->package.elements[0]; | |
784 | if (domain_type->integer.value == WRDD_WIFI) | |
785 | break; | |
786 | ||
787 | mcc_pkg = NULL; | |
788 | } | |
789 | ||
790 | if (mcc_pkg) { | |
791 | mcc_value = &mcc_pkg->package.elements[1]; | |
792 | return mcc_value->integer.value; | |
793 | } | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc) | |
799 | { | |
800 | acpi_handle root_handle; | |
801 | acpi_handle handle; | |
802 | struct acpi_buffer wrdd = {ACPI_ALLOCATE_BUFFER, NULL}; | |
803 | acpi_status status; | |
804 | u32 mcc_val; | |
805 | struct pci_dev *pdev = to_pci_dev(mvm->dev); | |
806 | ||
807 | root_handle = ACPI_HANDLE(&pdev->dev); | |
808 | if (!root_handle) { | |
809 | IWL_DEBUG_LAR(mvm, | |
810 | "Could not retrieve root port ACPI handle\n"); | |
811 | return -ENOENT; | |
812 | } | |
813 | ||
814 | /* Get the method's handle */ | |
815 | status = acpi_get_handle(root_handle, (acpi_string)WRD_METHOD, &handle); | |
816 | if (ACPI_FAILURE(status)) { | |
817 | IWL_DEBUG_LAR(mvm, "WRD method not found\n"); | |
818 | return -ENOENT; | |
819 | } | |
820 | ||
821 | /* Call WRDD with no arguments */ | |
822 | status = acpi_evaluate_object(handle, NULL, NULL, &wrdd); | |
823 | if (ACPI_FAILURE(status)) { | |
824 | IWL_DEBUG_LAR(mvm, "WRDC invocation failed (0x%x)\n", status); | |
825 | return -ENOENT; | |
826 | } | |
827 | ||
828 | mcc_val = iwl_mvm_wrdd_get_mcc(mvm, wrdd.pointer); | |
829 | kfree(wrdd.pointer); | |
830 | if (!mcc_val) | |
831 | return -ENOENT; | |
832 | ||
833 | mcc[0] = (mcc_val >> 8) & 0xff; | |
834 | mcc[1] = mcc_val & 0xff; | |
835 | mcc[2] = '\0'; | |
836 | return 0; | |
837 | } | |
838 | #else /* CONFIG_ACPI */ | |
839 | static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc) | |
840 | { | |
841 | return -ENOENT; | |
842 | } | |
843 | #endif | |
844 | ||
90d4f7db AN |
845 | int iwl_mvm_init_mcc(struct iwl_mvm *mvm) |
846 | { | |
d0d15197 MG |
847 | bool tlv_lar; |
848 | bool nvm_lar; | |
8ba2d7a1 EH |
849 | int retval; |
850 | struct ieee80211_regdomain *regd; | |
7f0344c2 | 851 | char mcc[3]; |
d0d15197 MG |
852 | |
853 | if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000) { | |
859d914c JB |
854 | tlv_lar = fw_has_capa(&mvm->fw->ucode_capa, |
855 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
d0d15197 MG |
856 | nvm_lar = mvm->nvm_data->lar_enabled; |
857 | if (tlv_lar != nvm_lar) | |
858 | IWL_INFO(mvm, | |
859 | "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n", | |
860 | tlv_lar ? "enabled" : "disabled", | |
861 | nvm_lar ? "enabled" : "disabled"); | |
862 | } | |
863 | ||
90d4f7db AN |
864 | if (!iwl_mvm_is_lar_supported(mvm)) |
865 | return 0; | |
866 | ||
867 | /* | |
b6e160ab | 868 | * try to replay the last set MCC to FW. If it doesn't exist, |
90d4f7db AN |
869 | * queue an update to cfg80211 to retrieve the default alpha2 from FW. |
870 | */ | |
b6e160ab AN |
871 | retval = iwl_mvm_init_fw_regd(mvm); |
872 | if (retval != -ENOENT) | |
873 | return retval; | |
90d4f7db AN |
874 | |
875 | /* | |
8ba2d7a1 EH |
876 | * Driver regulatory hint for initial update, this also informs the |
877 | * firmware we support wifi location updates. | |
88931cc9 AN |
878 | * Disallow scans that might crash the FW while the LAR regdomain |
879 | * is not set. | |
90d4f7db | 880 | */ |
88931cc9 | 881 | mvm->lar_regdom_set = false; |
8ba2d7a1 | 882 | |
47c8b154 | 883 | regd = iwl_mvm_get_current_regdomain(mvm, NULL); |
8ba2d7a1 EH |
884 | if (IS_ERR_OR_NULL(regd)) |
885 | return -EIO; | |
886 | ||
7f0344c2 JD |
887 | if (iwl_mvm_is_wifi_mcc_supported(mvm) && |
888 | !iwl_mvm_get_bios_mcc(mvm, mcc)) { | |
889 | kfree(regd); | |
890 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, | |
47c8b154 | 891 | MCC_SOURCE_BIOS, NULL); |
7f0344c2 JD |
892 | if (IS_ERR_OR_NULL(regd)) |
893 | return -EIO; | |
894 | } | |
895 | ||
8ba2d7a1 EH |
896 | retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd); |
897 | kfree(regd); | |
898 | return retval; | |
88931cc9 AN |
899 | } |
900 | ||
0416841d JB |
901 | void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, |
902 | struct iwl_rx_cmd_buffer *rxb) | |
88931cc9 AN |
903 | { |
904 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
905 | struct iwl_mcc_chub_notif *notif = (void *)pkt->data; | |
8ba2d7a1 | 906 | enum iwl_mcc_source src; |
88931cc9 | 907 | char mcc[3]; |
8ba2d7a1 EH |
908 | struct ieee80211_regdomain *regd; |
909 | ||
910 | lockdep_assert_held(&mvm->mutex); | |
88931cc9 AN |
911 | |
912 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
0416841d | 913 | return; |
88931cc9 AN |
914 | |
915 | mcc[0] = notif->mcc >> 8; | |
916 | mcc[1] = notif->mcc & 0xff; | |
917 | mcc[2] = '\0'; | |
8ba2d7a1 | 918 | src = notif->source_id; |
88931cc9 AN |
919 | |
920 | IWL_DEBUG_LAR(mvm, | |
8ba2d7a1 EH |
921 | "RX: received chub update mcc cmd (mcc '%s' src %d)\n", |
922 | mcc, src); | |
47c8b154 | 923 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL); |
8ba2d7a1 | 924 | if (IS_ERR_OR_NULL(regd)) |
0416841d | 925 | return; |
8ba2d7a1 EH |
926 | |
927 | regulatory_set_wiphy_regd(mvm->hw->wiphy, regd); | |
928 | kfree(regd); | |
90d4f7db | 929 | } |