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ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
fc8a350d IP |
3 | * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. |
4 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
ab697a9f EG |
5 | * |
6 | * Portions of this file are derived from the ipw3945 project, as well | |
7 | * as portions of the ieee80211 subsystem header files. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in the | |
23 | * file called LICENSE. | |
24 | * | |
25 | * Contact Information: | |
cb2f8277 | 26 | * Intel Linux Wireless <linuxwifi@intel.com> |
ab697a9f EG |
27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
28 | * | |
29 | *****************************************************************************/ | |
30 | #ifndef __iwl_trans_int_pcie_h__ | |
31 | #define __iwl_trans_int_pcie_h__ | |
32 | ||
a72b8b08 EG |
33 | #include <linux/spinlock.h> |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/skbuff.h> | |
13df1aab | 36 | #include <linux/wait.h> |
522376d2 | 37 | #include <linux/pci.h> |
7c5ba4a8 | 38 | #include <linux/timer.h> |
a72b8b08 | 39 | |
dda61a44 | 40 | #include "iwl-fh.h" |
a72b8b08 | 41 | #include "iwl-csr.h" |
a72b8b08 EG |
42 | #include "iwl-trans.h" |
43 | #include "iwl-debug.h" | |
44 | #include "iwl-io.h" | |
02e38358 | 45 | #include "iwl-op-mode.h" |
a72b8b08 | 46 | |
206eea78 JB |
47 | /* We need 2 entries for the TX command and header, and another one might |
48 | * be needed for potential data in the SKB's head. The remaining ones can | |
49 | * be used for frags. | |
50 | */ | |
51 | #define IWL_PCIE_MAX_FRAGS (IWL_NUM_OF_TBS - 3) | |
52 | ||
26d535ae SS |
53 | /* |
54 | * RX related structures and functions | |
55 | */ | |
56 | #define RX_NUM_QUEUES 1 | |
57 | #define RX_POST_REQ_ALLOC 2 | |
58 | #define RX_CLAIM_REQ_ALLOC 8 | |
59 | #define RX_POOL_SIZE ((RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC) * RX_NUM_QUEUES) | |
60 | #define RX_LOW_WATERMARK 8 | |
61 | ||
a72b8b08 | 62 | struct iwl_host_cmd; |
dda61a44 | 63 | |
ab697a9f EG |
64 | /*This file includes the declaration that are internal to the |
65 | * trans_pcie layer */ | |
66 | ||
48a2d66f JB |
67 | struct iwl_rx_mem_buffer { |
68 | dma_addr_t page_dma; | |
69 | struct page *page; | |
70 | struct list_head list; | |
71 | }; | |
72 | ||
1f7b6172 EG |
73 | /** |
74 | * struct isr_statistics - interrupt statistics | |
75 | * | |
76 | */ | |
77 | struct isr_statistics { | |
78 | u32 hw; | |
79 | u32 sw; | |
80 | u32 err_code; | |
81 | u32 sch; | |
82 | u32 alive; | |
83 | u32 rfkill; | |
84 | u32 ctkill; | |
85 | u32 wakeup; | |
86 | u32 rx; | |
87 | u32 tx; | |
88 | u32 unhandled; | |
89 | }; | |
90 | ||
5a878bf6 | 91 | /** |
990aa6d7 | 92 | * struct iwl_rxq - Rx queue |
5a878bf6 EG |
93 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) |
94 | * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) | |
5a878bf6 EG |
95 | * @read: Shared index to newest available Rx buffer |
96 | * @write: Shared index to oldest written Rx packet | |
97 | * @free_count: Number of pre-allocated buffers in rx_free | |
26d535ae | 98 | * @used_count: Number of RBDs handled to allocator to use for allocation |
5a878bf6 | 99 | * @write_actual: |
26d535ae SS |
100 | * @rx_free: list of RBDs with allocated RB ready for use |
101 | * @rx_used: list of RBDs with no RB attached | |
5a878bf6 EG |
102 | * @need_update: flag to indicate we need to update read/write index |
103 | * @rb_stts: driver's pointer to receive buffer status | |
104 | * @rb_stts_dma: bus address of receive buffer status | |
105 | * @lock: | |
26d535ae SS |
106 | * @pool: initial pool of iwl_rx_mem_buffer for the queue |
107 | * @queue: actual rx queue | |
5a878bf6 EG |
108 | * |
109 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers | |
110 | */ | |
990aa6d7 | 111 | struct iwl_rxq { |
5a878bf6 EG |
112 | __le32 *bd; |
113 | dma_addr_t bd_dma; | |
5a878bf6 EG |
114 | u32 read; |
115 | u32 write; | |
116 | u32 free_count; | |
26d535ae | 117 | u32 used_count; |
5a878bf6 EG |
118 | u32 write_actual; |
119 | struct list_head rx_free; | |
120 | struct list_head rx_used; | |
5d63f926 | 121 | bool need_update; |
5a878bf6 EG |
122 | struct iwl_rb_status *rb_stts; |
123 | dma_addr_t rb_stts_dma; | |
124 | spinlock_t lock; | |
26d535ae SS |
125 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE]; |
126 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
127 | }; | |
128 | ||
129 | /** | |
130 | * struct iwl_rb_allocator - Rx allocator | |
131 | * @pool: initial pool of allocator | |
132 | * @req_pending: number of requests the allcator had not processed yet | |
133 | * @req_ready: number of requests honored and ready for claiming | |
134 | * @rbd_allocated: RBDs with pages allocated and ready to be handled to | |
135 | * the queue. This is a list of &struct iwl_rx_mem_buffer | |
136 | * @rbd_empty: RBDs with no page attached for allocator use. This is a list | |
137 | * of &struct iwl_rx_mem_buffer | |
138 | * @lock: protects the rbd_allocated and rbd_empty lists | |
139 | * @alloc_wq: work queue for background calls | |
140 | * @rx_alloc: work struct for background calls | |
141 | */ | |
142 | struct iwl_rb_allocator { | |
143 | struct iwl_rx_mem_buffer pool[RX_POOL_SIZE]; | |
144 | atomic_t req_pending; | |
145 | atomic_t req_ready; | |
146 | struct list_head rbd_allocated; | |
147 | struct list_head rbd_empty; | |
148 | spinlock_t lock; | |
149 | struct workqueue_struct *alloc_wq; | |
150 | struct work_struct rx_alloc; | |
5a878bf6 EG |
151 | }; |
152 | ||
a72b8b08 EG |
153 | struct iwl_dma_ptr { |
154 | dma_addr_t dma; | |
155 | void *addr; | |
156 | size_t size; | |
157 | }; | |
158 | ||
bffc66ce JB |
159 | /** |
160 | * iwl_queue_inc_wrap - increment queue index, wrap back to beginning | |
161 | * @index -- current index | |
bffc66ce | 162 | */ |
83f32a4b | 163 | static inline int iwl_queue_inc_wrap(int index) |
bffc66ce | 164 | { |
83f32a4b | 165 | return ++index & (TFD_QUEUE_SIZE_MAX - 1); |
bffc66ce JB |
166 | } |
167 | ||
168 | /** | |
169 | * iwl_queue_dec_wrap - decrement queue index, wrap back to end | |
170 | * @index -- current index | |
bffc66ce | 171 | */ |
83f32a4b | 172 | static inline int iwl_queue_dec_wrap(int index) |
bffc66ce | 173 | { |
83f32a4b | 174 | return --index & (TFD_QUEUE_SIZE_MAX - 1); |
bffc66ce JB |
175 | } |
176 | ||
522376d2 EG |
177 | struct iwl_cmd_meta { |
178 | /* only for SYNC commands, iff the reply skb is wanted */ | |
179 | struct iwl_host_cmd *source; | |
c14c7372 | 180 | u32 flags; |
522376d2 EG |
181 | }; |
182 | ||
183 | /* | |
184 | * Generic queue structure | |
185 | * | |
186 | * Contains common data for Rx and Tx queues. | |
187 | * | |
83f32a4b JB |
188 | * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware |
189 | * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless | |
522376d2 EG |
190 | * there might be HW changes in the future). For the normal TX |
191 | * queues, n_window, which is the size of the software queue data | |
192 | * is also 256; however, for the command queue, n_window is only | |
193 | * 32 since we don't need so many commands pending. Since the HW | |
83f32a4b | 194 | * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result, |
522376d2 | 195 | * the software buffers (in the variables @meta, @txb in struct |
990aa6d7 EG |
196 | * iwl_txq) only have 32 entries, while the HW buffers (@tfds in |
197 | * the same struct) have 256. | |
522376d2 EG |
198 | * This means that we end up with the following: |
199 | * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | | |
200 | * SW entries: | 0 | ... | 31 | | |
201 | * where N is a number between 0 and 7. This means that the SW | |
202 | * data is a window overlayed over the HW queue. | |
203 | */ | |
204 | struct iwl_queue { | |
522376d2 EG |
205 | int write_ptr; /* 1-st empty entry (index) host_w*/ |
206 | int read_ptr; /* last used entry (index) host_r*/ | |
207 | /* use for monitoring and recovering the stuck queue */ | |
208 | dma_addr_t dma_addr; /* physical addr for BD's */ | |
209 | int n_window; /* safe queue window */ | |
210 | u32 id; | |
211 | int low_mark; /* low watermark, resume queue if free | |
212 | * space more than this */ | |
213 | int high_mark; /* high watermark, stop queue if free | |
214 | * space less than this */ | |
215 | }; | |
216 | ||
bf8440e6 JB |
217 | #define TFD_TX_CMD_SLOTS 256 |
218 | #define TFD_CMD_SLOTS 32 | |
219 | ||
8a964f44 JB |
220 | /* |
221 | * The FH will write back to the first TB only, so we need | |
222 | * to copy some data into the buffer regardless of whether | |
38c0f334 JB |
223 | * it should be mapped or not. This indicates how big the |
224 | * first TB must be to include the scratch buffer. Since | |
225 | * the scratch is 4 bytes at offset 12, it's 16 now. If we | |
226 | * make it bigger then allocations will be bigger and copy | |
227 | * slower, so that's probably not useful. | |
8a964f44 | 228 | */ |
38c0f334 | 229 | #define IWL_HCMD_SCRATCHBUF_SIZE 16 |
8a964f44 | 230 | |
990aa6d7 | 231 | struct iwl_pcie_txq_entry { |
bf8440e6 JB |
232 | struct iwl_device_cmd *cmd; |
233 | struct sk_buff *skb; | |
f4feb8ac JB |
234 | /* buffer to free after command completes */ |
235 | const void *free_buf; | |
bf8440e6 JB |
236 | struct iwl_cmd_meta meta; |
237 | }; | |
238 | ||
38c0f334 JB |
239 | struct iwl_pcie_txq_scratch_buf { |
240 | struct iwl_cmd_header hdr; | |
241 | u8 buf[8]; | |
242 | __le32 scratch; | |
243 | }; | |
244 | ||
522376d2 | 245 | /** |
990aa6d7 | 246 | * struct iwl_txq - Tx Queue for DMA |
522376d2 | 247 | * @q: generic Rx/Tx queue descriptor |
bf8440e6 | 248 | * @tfds: transmit frame descriptors (DMA memory) |
38c0f334 JB |
249 | * @scratchbufs: start of command headers, including scratch buffers, for |
250 | * the writeback -- this is DMA memory and an array holding one buffer | |
251 | * for each command on the queue | |
252 | * @scratchbufs_dma: DMA address for the scratchbufs start | |
bf8440e6 JB |
253 | * @entries: transmit entries (driver state) |
254 | * @lock: queue lock | |
255 | * @stuck_timer: timer that fires if queue gets stuck | |
256 | * @trans_pcie: pointer back to transport (for timer) | |
522376d2 | 257 | * @need_update: indicates need to update read/write index |
bf8440e6 | 258 | * @active: stores if queue is active |
68972c46 | 259 | * @ampdu: true if this queue is an ampdu queue for an specific RA/TID |
4cf677fd | 260 | * @wd_timeout: queue watchdog timeout (jiffies) - per queue |
e0b8d405 EG |
261 | * @frozen: tx stuck queue timer is frozen |
262 | * @frozen_expiry_remainder: remember how long until the timer fires | |
522376d2 EG |
263 | * |
264 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame | |
265 | * descriptors) and required locking structures. | |
266 | */ | |
990aa6d7 | 267 | struct iwl_txq { |
522376d2 EG |
268 | struct iwl_queue q; |
269 | struct iwl_tfd *tfds; | |
38c0f334 JB |
270 | struct iwl_pcie_txq_scratch_buf *scratchbufs; |
271 | dma_addr_t scratchbufs_dma; | |
990aa6d7 | 272 | struct iwl_pcie_txq_entry *entries; |
015c15e1 | 273 | spinlock_t lock; |
e0b8d405 | 274 | unsigned long frozen_expiry_remainder; |
7c5ba4a8 JB |
275 | struct timer_list stuck_timer; |
276 | struct iwl_trans_pcie *trans_pcie; | |
43aa616f | 277 | bool need_update; |
e0b8d405 | 278 | bool frozen; |
522376d2 | 279 | u8 active; |
68972c46 | 280 | bool ampdu; |
0cd58eaa | 281 | bool block; |
4cf677fd | 282 | unsigned long wd_timeout; |
522376d2 EG |
283 | }; |
284 | ||
38c0f334 JB |
285 | static inline dma_addr_t |
286 | iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx) | |
287 | { | |
288 | return txq->scratchbufs_dma + | |
289 | sizeof(struct iwl_pcie_txq_scratch_buf) * idx; | |
290 | } | |
291 | ||
6eb5e529 EG |
292 | struct iwl_tso_hdr_page { |
293 | struct page *page; | |
294 | u8 *pos; | |
295 | }; | |
296 | ||
e6bb4c9c EG |
297 | /** |
298 | * struct iwl_trans_pcie - PCIe transport specific data | |
5a878bf6 | 299 | * @rxq: all the RX queue data |
26d535ae | 300 | * @rba: allocator for RX replenishing |
9130bab1 | 301 | * @drv - pointer to iwl_drv |
5a878bf6 | 302 | * @trans: pointer to the generic transport area |
105183b1 EG |
303 | * @scd_base_addr: scheduler sram base address in SRAM |
304 | * @scd_bc_tbls: pointer to the byte count table of the scheduler | |
9d6b2cb1 | 305 | * @kw: keep warm address |
a42a1844 EG |
306 | * @pci_dev: basic pci-network driver stuff |
307 | * @hw_base: pci hardware address support | |
13df1aab JB |
308 | * @ucode_write_complete: indicates that the ucode has been copied. |
309 | * @ucode_write_waitq: wait queue for uCode load | |
c6f600fc | 310 | * @cmd_queue - command queue number |
6c4fbcbc | 311 | * @rx_buf_size: Rx buffer size |
046db346 | 312 | * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) |
3a736bcb | 313 | * @scd_set_active: should the transport configure the SCD for HCMD queue |
ab02165c | 314 | * @wide_cmd_header: true when ucode supports wide command header format |
41837ca9 EG |
315 | * @sw_csum_tx: if true, then the transport will compute the csum of the TXed |
316 | * frame. | |
b2cf410c | 317 | * @rx_page_order: page order for receive buffer size |
e56b04ef | 318 | * @reg_lock: protect hw register access |
fa9f3281 | 319 | * @mutex: to protect stop_device / start_fw / start_hw |
b9439491 | 320 | * @cmd_in_flight: true when we have a host command in flight |
c2d20201 EG |
321 | * @fw_mon_phys: physical address of the buffer for the firmware monitor |
322 | * @fw_mon_page: points to the first page of the buffer for the firmware monitor | |
323 | * @fw_mon_size: size of the buffer for the firmware monitor | |
e6bb4c9c EG |
324 | */ |
325 | struct iwl_trans_pcie { | |
990aa6d7 | 326 | struct iwl_rxq rxq; |
26d535ae | 327 | struct iwl_rb_allocator rba; |
5a878bf6 | 328 | struct iwl_trans *trans; |
9130bab1 | 329 | struct iwl_drv *drv; |
0c325769 | 330 | |
f14d6b39 JB |
331 | struct net_device napi_dev; |
332 | struct napi_struct napi; | |
333 | ||
6eb5e529 EG |
334 | struct __percpu iwl_tso_hdr_page *tso_hdr_page; |
335 | ||
0c325769 EG |
336 | /* INT ICT Table */ |
337 | __le32 *ict_tbl; | |
0c325769 | 338 | dma_addr_t ict_tbl_dma; |
0c325769 | 339 | int ict_index; |
0c325769 | 340 | bool use_ict; |
fa9f3281 | 341 | bool is_down; |
1f7b6172 | 342 | struct isr_statistics isr_stats; |
0c325769 | 343 | |
7b11488f | 344 | spinlock_t irq_lock; |
fa9f3281 | 345 | struct mutex mutex; |
0c325769 | 346 | u32 inta_mask; |
105183b1 EG |
347 | u32 scd_base_addr; |
348 | struct iwl_dma_ptr scd_bc_tbls; | |
9d6b2cb1 | 349 | struct iwl_dma_ptr kw; |
e13c0c59 | 350 | |
990aa6d7 | 351 | struct iwl_txq *txq; |
9eae88fa | 352 | unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; |
8ad71bef | 353 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; |
a42a1844 EG |
354 | |
355 | /* PCI bus related data */ | |
356 | struct pci_dev *pci_dev; | |
357 | void __iomem *hw_base; | |
13df1aab JB |
358 | |
359 | bool ucode_write_complete; | |
360 | wait_queue_head_t ucode_write_waitq; | |
f946b529 EG |
361 | wait_queue_head_t wait_command_queue; |
362 | ||
c6f600fc | 363 | u8 cmd_queue; |
b04db9ac | 364 | u8 cmd_fifo; |
4cf677fd | 365 | unsigned int cmd_q_wdg_timeout; |
d663ee73 JB |
366 | u8 n_no_reclaim_cmds; |
367 | u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; | |
b2cf410c | 368 | |
6c4fbcbc | 369 | enum iwl_amsdu_size rx_buf_size; |
046db346 | 370 | bool bc_table_dword; |
3a736bcb | 371 | bool scd_set_active; |
ab02165c | 372 | bool wide_cmd_header; |
41837ca9 | 373 | bool sw_csum_tx; |
b2cf410c | 374 | u32 rx_page_order; |
7c5ba4a8 | 375 | |
e56b04ef LE |
376 | /*protect hw register */ |
377 | spinlock_t reg_lock; | |
fc8a350d | 378 | bool cmd_hold_nic_awake; |
7616f334 EP |
379 | bool ref_cmd_in_flight; |
380 | ||
381 | /* protect ref counter */ | |
382 | spinlock_t ref_lock; | |
383 | u32 ref_count; | |
c2d20201 EG |
384 | |
385 | dma_addr_t fw_mon_phys; | |
386 | struct page *fw_mon_page; | |
387 | u32 fw_mon_size; | |
e6bb4c9c EG |
388 | }; |
389 | ||
85e5a387 JB |
390 | static inline struct iwl_trans_pcie * |
391 | IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) | |
392 | { | |
393 | return (void *)trans->trans_specific; | |
394 | } | |
5a878bf6 | 395 | |
7c5ba4a8 JB |
396 | static inline struct iwl_trans * |
397 | iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) | |
398 | { | |
399 | return container_of((void *)trans_pcie, struct iwl_trans, | |
400 | trans_specific); | |
401 | } | |
402 | ||
f02831be EG |
403 | /* |
404 | * Convention: trans API functions: iwl_trans_pcie_XXX | |
405 | * Other functions: iwl_pcie_XXX | |
406 | */ | |
d1ff5253 JB |
407 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
408 | const struct pci_device_id *ent, | |
409 | const struct iwl_cfg *cfg); | |
410 | void iwl_trans_pcie_free(struct iwl_trans *trans); | |
411 | ||
253a634c EG |
412 | /***************************************************** |
413 | * RX | |
414 | ******************************************************/ | |
9805c446 | 415 | int iwl_pcie_rx_init(struct iwl_trans *trans); |
2bfb5092 | 416 | irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); |
9805c446 EG |
417 | int iwl_pcie_rx_stop(struct iwl_trans *trans); |
418 | void iwl_pcie_rx_free(struct iwl_trans *trans); | |
ab697a9f | 419 | |
1a361cd8 | 420 | /***************************************************** |
990aa6d7 | 421 | * ICT - interrupt handling |
1a361cd8 | 422 | ******************************************************/ |
85bf9da1 | 423 | irqreturn_t iwl_pcie_isr(int irq, void *data); |
990aa6d7 EG |
424 | int iwl_pcie_alloc_ict(struct iwl_trans *trans); |
425 | void iwl_pcie_free_ict(struct iwl_trans *trans); | |
426 | void iwl_pcie_reset_ict(struct iwl_trans *trans); | |
427 | void iwl_pcie_disable_ict(struct iwl_trans *trans); | |
1a361cd8 | 428 | |
253a634c EG |
429 | /***************************************************** |
430 | * TX / HCMD | |
431 | ******************************************************/ | |
f02831be EG |
432 | int iwl_pcie_tx_init(struct iwl_trans *trans); |
433 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); | |
434 | int iwl_pcie_tx_stop(struct iwl_trans *trans); | |
435 | void iwl_pcie_tx_free(struct iwl_trans *trans); | |
fea7795f | 436 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, |
4cf677fd EG |
437 | const struct iwl_trans_txq_scd_cfg *cfg, |
438 | unsigned int wdg_timeout); | |
d4578ea8 JB |
439 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, |
440 | bool configure_scd); | |
f02831be EG |
441 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
442 | struct iwl_device_cmd *dev_cmd, int txq_id); | |
ea68f460 | 443 | void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); |
f02831be | 444 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); |
990aa6d7 | 445 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
f7e6469f | 446 | struct iwl_rx_cmd_buffer *rxb); |
f02831be EG |
447 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
448 | struct sk_buff_head *skbs); | |
ddaf5a5b JB |
449 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); |
450 | ||
7616f334 EP |
451 | void iwl_trans_pcie_ref(struct iwl_trans *trans); |
452 | void iwl_trans_pcie_unref(struct iwl_trans *trans); | |
453 | ||
4d075007 JB |
454 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
455 | { | |
456 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
457 | ||
458 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
459 | } | |
460 | ||
7ff94706 EG |
461 | /***************************************************** |
462 | * Error handling | |
463 | ******************************************************/ | |
990aa6d7 | 464 | void iwl_pcie_dump_csr(struct iwl_trans *trans); |
16db88ba | 465 | |
8ad71bef EG |
466 | /***************************************************** |
467 | * Helpers | |
468 | ******************************************************/ | |
0c325769 EG |
469 | static inline void iwl_disable_interrupts(struct iwl_trans *trans) |
470 | { | |
eb7ff77e | 471 | clear_bit(STATUS_INT_ENABLED, &trans->status); |
0c325769 EG |
472 | |
473 | /* disable interrupts from uCode/NIC to host */ | |
1042db2a | 474 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); |
0c325769 EG |
475 | |
476 | /* acknowledge/clear/reset any interrupts still pending | |
477 | * from uCode or flow handler (Rx/Tx DMA) */ | |
1042db2a EG |
478 | iwl_write32(trans, CSR_INT, 0xffffffff); |
479 | iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); | |
0c325769 EG |
480 | IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); |
481 | } | |
482 | ||
483 | static inline void iwl_enable_interrupts(struct iwl_trans *trans) | |
484 | { | |
83626404 | 485 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
0c325769 EG |
486 | |
487 | IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); | |
eb7ff77e | 488 | set_bit(STATUS_INT_ENABLED, &trans->status); |
2dbc368d | 489 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1042db2a | 490 | iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); |
0c325769 EG |
491 | } |
492 | ||
a6bd005f EG |
493 | static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) |
494 | { | |
495 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
496 | ||
497 | IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); | |
498 | trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; | |
499 | iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); | |
500 | } | |
501 | ||
8722c899 SG |
502 | static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) |
503 | { | |
2dbc368d EG |
504 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
505 | ||
8722c899 | 506 | IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); |
2dbc368d EG |
507 | trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; |
508 | iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); | |
8722c899 SG |
509 | } |
510 | ||
e20d4341 | 511 | static inline void iwl_wake_queue(struct iwl_trans *trans, |
990aa6d7 | 512 | struct iwl_txq *txq) |
e20d4341 | 513 | { |
9eae88fa JB |
514 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
515 | ||
516 | if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) { | |
517 | IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id); | |
518 | iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id); | |
81a3de1c | 519 | } |
e20d4341 EG |
520 | } |
521 | ||
522 | static inline void iwl_stop_queue(struct iwl_trans *trans, | |
990aa6d7 | 523 | struct iwl_txq *txq) |
e20d4341 | 524 | { |
9eae88fa | 525 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 526 | |
9eae88fa JB |
527 | if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) { |
528 | iwl_op_mode_queue_full(trans->op_mode, txq->q.id); | |
529 | IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id); | |
530 | } else | |
531 | IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", | |
532 | txq->q.id); | |
8ad71bef EG |
533 | } |
534 | ||
6ca6ebc1 | 535 | static inline bool iwl_queue_used(const struct iwl_queue *q, int i) |
8ad71bef EG |
536 | { |
537 | return q->write_ptr >= q->read_ptr ? | |
538 | (i >= q->read_ptr && i < q->write_ptr) : | |
539 | !(i < q->read_ptr && i >= q->write_ptr); | |
540 | } | |
541 | ||
542 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index) | |
543 | { | |
544 | return index & (q->n_window - 1); | |
545 | } | |
546 | ||
8d425517 EG |
547 | static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) |
548 | { | |
549 | return !(iwl_read32(trans, CSR_GP_CNTRL) & | |
550 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
551 | } | |
552 | ||
b9439491 EG |
553 | static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, |
554 | u32 reg, u32 mask, u32 value) | |
555 | { | |
556 | u32 v; | |
557 | ||
558 | #ifdef CONFIG_IWLWIFI_DEBUG | |
559 | WARN_ON_ONCE(value & ~mask); | |
560 | #endif | |
561 | ||
562 | v = iwl_read32(trans, reg); | |
563 | v &= ~mask; | |
564 | v |= value; | |
565 | iwl_write32(trans, reg, v); | |
566 | } | |
567 | ||
568 | static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, | |
569 | u32 reg, u32 mask) | |
570 | { | |
571 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); | |
572 | } | |
573 | ||
574 | static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, | |
575 | u32 reg, u32 mask) | |
576 | { | |
577 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); | |
578 | } | |
579 | ||
14cfca71 JB |
580 | void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); |
581 | ||
f8a1edb7 JB |
582 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
583 | int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); | |
584 | #else | |
585 | static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) | |
586 | { | |
587 | return 0; | |
588 | } | |
589 | #endif | |
590 | ||
ab697a9f | 591 | #endif /* __iwl_trans_int_pcie_h__ */ |