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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
4cbb8e50 LC |
4 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
5 | * Copyright(c) 2016 Intel Deutschland GmbH | |
1053d35f RR |
6 | * |
7 | * Portions of this file are derived from the ipw3945 project, as well | |
8 | * as portions of the ieee80211 subsystem header files. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., | |
21 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
22 | * | |
23 | * The full GNU General Public License is included in this distribution in the | |
24 | * file called LICENSE. | |
25 | * | |
26 | * Contact Information: | |
cb2f8277 | 27 | * Intel Linux Wireless <linuxwifi@intel.com> |
1053d35f RR |
28 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
29 | * | |
30 | *****************************************************************************/ | |
fd4abac5 | 31 | #include <linux/etherdevice.h> |
6eb5e529 | 32 | #include <linux/ieee80211.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
253a634c | 34 | #include <linux/sched.h> |
6eb5e529 EG |
35 | #include <net/ip6_checksum.h> |
36 | #include <net/tso.h> | |
253a634c | 37 | |
522376d2 EG |
38 | #include "iwl-debug.h" |
39 | #include "iwl-csr.h" | |
40 | #include "iwl-prph.h" | |
1053d35f | 41 | #include "iwl-io.h" |
680073b7 | 42 | #include "iwl-scd.h" |
ed277c93 | 43 | #include "iwl-op-mode.h" |
6468a01a | 44 | #include "internal.h" |
6238b008 | 45 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 46 | #include "dvm/commands.h" |
1053d35f | 47 | |
522376d2 EG |
48 | #define IWL_TX_CRC_SIZE 4 |
49 | #define IWL_TX_DELIMITER_SIZE 4 | |
50 | ||
f02831be EG |
51 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
52 | * DMA services | |
53 | * | |
54 | * Theory of operation | |
55 | * | |
56 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
57 | * of buffer descriptors, each of which points to one or more data buffers for | |
58 | * the device to read from or fill. Driver and device exchange status of each | |
59 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
60 | * entries in each circular buffer, to protect against confusing empty and full | |
61 | * queue states. | |
62 | * | |
63 | * The device reads or writes the data in the queues via the device's several | |
64 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
65 | * | |
66 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
67 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
68 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
69 | * Tx queue resumed. | |
70 | * | |
71 | ***************************************************/ | |
72 | static int iwl_queue_space(const struct iwl_queue *q) | |
73 | { | |
a9b29246 IY |
74 | unsigned int max; |
75 | unsigned int used; | |
f02831be | 76 | |
a9b29246 IY |
77 | /* |
78 | * To avoid ambiguity between empty and completely full queues, there | |
83f32a4b JB |
79 | * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. |
80 | * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need | |
81 | * to reserve any queue entries for this purpose. | |
a9b29246 | 82 | */ |
83f32a4b | 83 | if (q->n_window < TFD_QUEUE_SIZE_MAX) |
a9b29246 IY |
84 | max = q->n_window; |
85 | else | |
83f32a4b | 86 | max = TFD_QUEUE_SIZE_MAX - 1; |
f02831be | 87 | |
a9b29246 | 88 | /* |
83f32a4b JB |
89 | * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to |
90 | * modulo by TFD_QUEUE_SIZE_MAX and is well defined. | |
a9b29246 | 91 | */ |
83f32a4b | 92 | used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); |
a9b29246 IY |
93 | |
94 | if (WARN_ON(used > max)) | |
95 | return 0; | |
96 | ||
97 | return max - used; | |
f02831be EG |
98 | } |
99 | ||
100 | /* | |
101 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
102 | */ | |
83f32a4b | 103 | static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id) |
f02831be | 104 | { |
f02831be EG |
105 | q->n_window = slots_num; |
106 | q->id = id; | |
107 | ||
f02831be EG |
108 | /* slots_num must be power-of-two size, otherwise |
109 | * get_cmd_index is broken. */ | |
110 | if (WARN_ON(!is_power_of_2(slots_num))) | |
111 | return -EINVAL; | |
112 | ||
113 | q->low_mark = q->n_window / 4; | |
114 | if (q->low_mark < 4) | |
115 | q->low_mark = 4; | |
116 | ||
117 | q->high_mark = q->n_window / 8; | |
118 | if (q->high_mark < 2) | |
119 | q->high_mark = 2; | |
120 | ||
121 | q->write_ptr = 0; | |
122 | q->read_ptr = 0; | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
f02831be EG |
127 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
128 | struct iwl_dma_ptr *ptr, size_t size) | |
129 | { | |
130 | if (WARN_ON(ptr->addr)) | |
131 | return -EINVAL; | |
132 | ||
133 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
134 | &ptr->dma, GFP_KERNEL); | |
135 | if (!ptr->addr) | |
136 | return -ENOMEM; | |
137 | ptr->size = size; | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
142 | struct iwl_dma_ptr *ptr) | |
143 | { | |
144 | if (unlikely(!ptr->addr)) | |
145 | return; | |
146 | ||
147 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
148 | memset(ptr, 0, sizeof(*ptr)); | |
149 | } | |
150 | ||
151 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
152 | { | |
153 | struct iwl_txq *txq = (void *)data; | |
f02831be EG |
154 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; |
155 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
156 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
157 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
158 | u8 buf[16]; | |
159 | int i; | |
160 | ||
161 | spin_lock(&txq->lock); | |
162 | /* check if triggered erroneously */ | |
163 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
164 | spin_unlock(&txq->lock); | |
165 | return; | |
166 | } | |
167 | spin_unlock(&txq->lock); | |
168 | ||
169 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
4cf677fd | 170 | jiffies_to_msecs(txq->wd_timeout)); |
f02831be EG |
171 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
172 | txq->q.read_ptr, txq->q.write_ptr); | |
173 | ||
4fd442db | 174 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
175 | |
176 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
177 | ||
178 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
179 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
180 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
181 | ||
182 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
183 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
184 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
185 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
186 | u32 tbl_dw = | |
4fd442db EG |
187 | iwl_trans_read_mem32(trans, |
188 | trans_pcie->scd_base_addr + | |
189 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
190 | |
191 | if (i & 0x1) | |
192 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
193 | else | |
194 | tbl_dw = tbl_dw & 0x0000FFFF; | |
195 | ||
196 | IWL_ERR(trans, | |
197 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
198 | i, active ? "" : "in", fifo, tbl_dw, | |
83f32a4b JB |
199 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) & |
200 | (TFD_QUEUE_SIZE_MAX - 1), | |
f02831be EG |
201 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); |
202 | } | |
203 | ||
4c9706dc | 204 | iwl_force_nmi(trans); |
f02831be EG |
205 | } |
206 | ||
990aa6d7 EG |
207 | /* |
208 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 209 | */ |
f02831be EG |
210 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
211 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 212 | { |
105183b1 | 213 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 214 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
215 | int write_ptr = txq->q.write_ptr; |
216 | int txq_id = txq->q.id; | |
217 | u8 sec_ctl = 0; | |
218 | u8 sta_id = 0; | |
219 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
220 | __le16 bc_ent; | |
132f98c2 | 221 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 222 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 223 | |
105183b1 EG |
224 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
225 | ||
132f98c2 EG |
226 | sta_id = tx_cmd->sta_id; |
227 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
228 | |
229 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
230 | case TX_CMD_SEC_CCM: | |
4325f6ca | 231 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
232 | break; |
233 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 234 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
235 | break; |
236 | case TX_CMD_SEC_WEP: | |
4325f6ca | 237 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
238 | break; |
239 | } | |
240 | ||
046db346 EG |
241 | if (trans_pcie->bc_table_dword) |
242 | len = DIV_ROUND_UP(len, 4); | |
243 | ||
31f920b6 EG |
244 | if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) |
245 | return; | |
246 | ||
046db346 | 247 | bc_ent = cpu_to_le16(len | (sta_id << 12)); |
48d42c42 EG |
248 | |
249 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
250 | ||
251 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
252 | scd_bc_tbl[txq_id]. | |
253 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
254 | } | |
255 | ||
f02831be EG |
256 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
257 | struct iwl_txq *txq) | |
258 | { | |
259 | struct iwl_trans_pcie *trans_pcie = | |
260 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
261 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
262 | int txq_id = txq->q.id; | |
263 | int read_ptr = txq->q.read_ptr; | |
264 | u8 sta_id = 0; | |
265 | __le16 bc_ent; | |
266 | struct iwl_tx_cmd *tx_cmd = | |
267 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
268 | ||
269 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
270 | ||
271 | if (txq_id != trans_pcie->cmd_queue) | |
272 | sta_id = tx_cmd->sta_id; | |
273 | ||
274 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
275 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
276 | ||
277 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
278 | scd_bc_tbl[txq_id]. | |
279 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
280 | } | |
281 | ||
990aa6d7 EG |
282 | /* |
283 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 284 | */ |
ea68f460 JB |
285 | static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, |
286 | struct iwl_txq *txq) | |
fd4abac5 | 287 | { |
23e76d1a | 288 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
fd4abac5 | 289 | u32 reg = 0; |
fd4abac5 TW |
290 | int txq_id = txq->q.id; |
291 | ||
ea68f460 | 292 | lockdep_assert_held(&txq->lock); |
fd4abac5 | 293 | |
5045388c EP |
294 | /* |
295 | * explicitly wake up the NIC if: | |
296 | * 1. shadow registers aren't enabled | |
297 | * 2. NIC is woken up for CMD regardless of shadow outside this function | |
298 | * 3. there is a chance that the NIC is asleep | |
299 | */ | |
300 | if (!trans->cfg->base_params->shadow_reg_enable && | |
301 | txq_id != trans_pcie->cmd_queue && | |
302 | test_bit(STATUS_TPOWER_PMI, &trans->status)) { | |
f81c1f48 | 303 | /* |
5045388c EP |
304 | * wake up nic if it's powered down ... |
305 | * uCode will wake up, and interrupt us again, so next | |
306 | * time we'll skip this part. | |
f81c1f48 | 307 | */ |
5045388c EP |
308 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
309 | ||
310 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
311 | IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", | |
312 | txq_id, reg); | |
313 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
314 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ea68f460 | 315 | txq->need_update = true; |
5045388c EP |
316 | return; |
317 | } | |
f81c1f48 | 318 | } |
5045388c EP |
319 | |
320 | /* | |
321 | * if not in power-save mode, uCode will never sleep when we're | |
322 | * trying to tx (during RFKILL, we're not trying to tx). | |
323 | */ | |
324 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); | |
0cd58eaa EG |
325 | if (!txq->block) |
326 | iwl_write32(trans, HBUS_TARG_WRPTR, | |
327 | txq->q.write_ptr | (txq_id << 8)); | |
ea68f460 | 328 | } |
5045388c | 329 | |
ea68f460 JB |
330 | void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) |
331 | { | |
332 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
333 | int i; | |
334 | ||
335 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
336 | struct iwl_txq *txq = &trans_pcie->txq[i]; | |
337 | ||
d090f878 | 338 | spin_lock_bh(&txq->lock); |
ea68f460 JB |
339 | if (trans_pcie->txq[i].need_update) { |
340 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
341 | trans_pcie->txq[i].need_update = false; | |
342 | } | |
d090f878 | 343 | spin_unlock_bh(&txq->lock); |
ea68f460 | 344 | } |
fd4abac5 | 345 | } |
fd4abac5 | 346 | |
f02831be | 347 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
348 | { |
349 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
350 | ||
351 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
352 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
353 | addr |= | |
354 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
355 | ||
356 | return addr; | |
357 | } | |
358 | ||
f02831be EG |
359 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
360 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
361 | { |
362 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
363 | u16 hi_n_len = len << 4; | |
364 | ||
365 | put_unaligned_le32(addr, &tb->lo); | |
366 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
367 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
368 | ||
369 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
370 | ||
371 | tfd->num_tbs = idx + 1; | |
372 | } | |
373 | ||
f02831be | 374 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
375 | { |
376 | return tfd->num_tbs & 0x1f; | |
377 | } | |
378 | ||
f02831be | 379 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 JB |
380 | struct iwl_cmd_meta *meta, |
381 | struct iwl_tfd *tfd) | |
214d14d4 | 382 | { |
214d14d4 JB |
383 | int i; |
384 | int num_tbs; | |
385 | ||
214d14d4 | 386 | /* Sanity check on number of chunks */ |
f02831be | 387 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
388 | |
389 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 390 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
391 | /* @todo issue fatal error, it is quite serious situation */ |
392 | return; | |
393 | } | |
394 | ||
38c0f334 | 395 | /* first TB is never freed - it's the scratchbuf data */ |
214d14d4 | 396 | |
206eea78 JB |
397 | for (i = 1; i < num_tbs; i++) { |
398 | if (meta->flags & BIT(i + CMD_TB_BITMAP_POS)) | |
399 | dma_unmap_page(trans->dev, | |
400 | iwl_pcie_tfd_tb_get_addr(tfd, i), | |
401 | iwl_pcie_tfd_tb_get_len(tfd, i), | |
402 | DMA_TO_DEVICE); | |
403 | else | |
404 | dma_unmap_single(trans->dev, | |
405 | iwl_pcie_tfd_tb_get_addr(tfd, i), | |
406 | iwl_pcie_tfd_tb_get_len(tfd, i), | |
407 | DMA_TO_DEVICE); | |
408 | } | |
ebed633c | 409 | tfd->num_tbs = 0; |
4ce7cc2b JB |
410 | } |
411 | ||
990aa6d7 EG |
412 | /* |
413 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 414 | * @trans - transport private data |
4ce7cc2b | 415 | * @txq - tx queue |
ebed633c | 416 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
417 | * |
418 | * Does NOT advance any TFD circular buffer read/write indexes | |
419 | * Does NOT free the TFD itself (which is within circular buffer) | |
420 | */ | |
98891754 | 421 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b JB |
422 | { |
423 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 424 | |
83f32a4b JB |
425 | /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and |
426 | * idx is bounded by n_window | |
427 | */ | |
ebed633c EG |
428 | int rd_ptr = txq->q.read_ptr; |
429 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
430 | ||
015c15e1 JB |
431 | lockdep_assert_held(&txq->lock); |
432 | ||
83f32a4b JB |
433 | /* We have only q->n_window txq->entries, but we use |
434 | * TFD_QUEUE_SIZE_MAX tfds | |
435 | */ | |
98891754 | 436 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); |
214d14d4 JB |
437 | |
438 | /* free SKB */ | |
bf8440e6 | 439 | if (txq->entries) { |
214d14d4 JB |
440 | struct sk_buff *skb; |
441 | ||
ebed633c | 442 | skb = txq->entries[idx].skb; |
214d14d4 | 443 | |
909e9b23 EG |
444 | /* Can be called from irqs-disabled context |
445 | * If skb is not NULL, it means that the whole queue is being | |
446 | * freed and that the queue is not empty - free the skb | |
447 | */ | |
214d14d4 | 448 | if (skb) { |
ed277c93 | 449 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 450 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
451 | } |
452 | } | |
453 | } | |
454 | ||
f02831be | 455 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
6d6e68f8 | 456 | dma_addr_t addr, u16 len, bool reset) |
214d14d4 JB |
457 | { |
458 | struct iwl_queue *q; | |
459 | struct iwl_tfd *tfd, *tfd_tmp; | |
460 | u32 num_tbs; | |
461 | ||
462 | q = &txq->q; | |
4ce7cc2b | 463 | tfd_tmp = txq->tfds; |
214d14d4 JB |
464 | tfd = &tfd_tmp[q->write_ptr]; |
465 | ||
f02831be EG |
466 | if (reset) |
467 | memset(tfd, 0, sizeof(*tfd)); | |
468 | ||
469 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
470 | ||
471 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
472 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
473 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
474 | IWL_NUM_OF_TBS); | |
475 | return -EINVAL; | |
476 | } | |
477 | ||
1092b9bc EP |
478 | if (WARN(addr & ~IWL_TX_DMA_MASK, |
479 | "Unaligned address = %llx\n", (unsigned long long)addr)) | |
f02831be EG |
480 | return -EINVAL; |
481 | ||
f02831be EG |
482 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); |
483 | ||
206eea78 | 484 | return num_tbs; |
f02831be EG |
485 | } |
486 | ||
487 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
488 | struct iwl_txq *txq, int slots_num, | |
489 | u32 txq_id) | |
490 | { | |
491 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
492 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
38c0f334 | 493 | size_t scratchbuf_sz; |
f02831be EG |
494 | int i; |
495 | ||
496 | if (WARN_ON(txq->entries || txq->tfds)) | |
497 | return -EINVAL; | |
498 | ||
499 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
500 | (unsigned long)txq); | |
501 | txq->trans_pcie = trans_pcie; | |
502 | ||
503 | txq->q.n_window = slots_num; | |
504 | ||
505 | txq->entries = kcalloc(slots_num, | |
506 | sizeof(struct iwl_pcie_txq_entry), | |
507 | GFP_KERNEL); | |
508 | ||
509 | if (!txq->entries) | |
510 | goto error; | |
511 | ||
512 | if (txq_id == trans_pcie->cmd_queue) | |
513 | for (i = 0; i < slots_num; i++) { | |
514 | txq->entries[i].cmd = | |
515 | kmalloc(sizeof(struct iwl_device_cmd), | |
516 | GFP_KERNEL); | |
517 | if (!txq->entries[i].cmd) | |
518 | goto error; | |
519 | } | |
520 | ||
521 | /* Circular buffer of transmit frame descriptors (TFDs), | |
522 | * shared with device */ | |
523 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
524 | &txq->q.dma_addr, GFP_KERNEL); | |
d0320f75 | 525 | if (!txq->tfds) |
f02831be | 526 | goto error; |
38c0f334 JB |
527 | |
528 | BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); | |
529 | BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != | |
530 | sizeof(struct iwl_cmd_header) + | |
531 | offsetof(struct iwl_tx_cmd, scratch)); | |
532 | ||
533 | scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; | |
534 | ||
535 | txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, | |
536 | &txq->scratchbufs_dma, | |
537 | GFP_KERNEL); | |
538 | if (!txq->scratchbufs) | |
539 | goto err_free_tfds; | |
540 | ||
f02831be EG |
541 | txq->q.id = txq_id; |
542 | ||
543 | return 0; | |
38c0f334 JB |
544 | err_free_tfds: |
545 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); | |
f02831be EG |
546 | error: |
547 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
548 | for (i = 0; i < slots_num; i++) | |
549 | kfree(txq->entries[i].cmd); | |
550 | kfree(txq->entries); | |
551 | txq->entries = NULL; | |
552 | ||
553 | return -ENOMEM; | |
554 | ||
555 | } | |
556 | ||
557 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
558 | int slots_num, u32 txq_id) | |
559 | { | |
560 | int ret; | |
561 | ||
43aa616f | 562 | txq->need_update = false; |
f02831be EG |
563 | |
564 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
565 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
566 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
567 | ||
568 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
83f32a4b | 569 | ret = iwl_queue_init(&txq->q, slots_num, txq_id); |
f02831be EG |
570 | if (ret) |
571 | return ret; | |
572 | ||
573 | spin_lock_init(&txq->lock); | |
3955525d | 574 | __skb_queue_head_init(&txq->overflow_q); |
f02831be EG |
575 | |
576 | /* | |
577 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
578 | * given Tx queue, and enable the DMA channel used for that queue. | |
579 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
580 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
581 | txq->q.dma_addr >> 8); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
6eb5e529 EG |
586 | static void iwl_pcie_free_tso_page(struct sk_buff *skb) |
587 | { | |
588 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
589 | ||
590 | if (info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]) { | |
591 | struct page *page = | |
592 | info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]; | |
593 | ||
594 | __free_page(page); | |
595 | info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = NULL; | |
596 | } | |
597 | } | |
598 | ||
f02831be EG |
599 | /* |
600 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
601 | */ | |
602 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
603 | { | |
604 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
605 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
606 | struct iwl_queue *q = &txq->q; | |
f02831be | 607 | |
f02831be EG |
608 | spin_lock_bh(&txq->lock); |
609 | while (q->write_ptr != q->read_ptr) { | |
b967613d EG |
610 | IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", |
611 | txq_id, q->read_ptr); | |
6eb5e529 EG |
612 | |
613 | if (txq_id != trans_pcie->cmd_queue) { | |
614 | struct sk_buff *skb = txq->entries[q->read_ptr].skb; | |
615 | ||
616 | if (WARN_ON_ONCE(!skb)) | |
617 | continue; | |
618 | ||
619 | iwl_pcie_free_tso_page(skb); | |
620 | } | |
98891754 | 621 | iwl_pcie_txq_free_tfd(trans, txq); |
83f32a4b | 622 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr); |
f02831be | 623 | } |
b967613d | 624 | txq->active = false; |
3955525d EG |
625 | |
626 | while (!skb_queue_empty(&txq->overflow_q)) { | |
627 | struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); | |
628 | ||
629 | iwl_op_mode_free_skb(trans->op_mode, skb); | |
630 | } | |
631 | ||
f02831be | 632 | spin_unlock_bh(&txq->lock); |
8a487b1a EG |
633 | |
634 | /* just in case - this queue may have been stopped */ | |
635 | iwl_wake_queue(trans, txq); | |
f02831be EG |
636 | } |
637 | ||
638 | /* | |
639 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
640 | * @txq: Transmit queue to deallocate. | |
641 | * | |
642 | * Empty queue by removing and destroying all BD's. | |
643 | * Free all buffers. | |
644 | * 0-fill, but do not free "txq" descriptor structure. | |
645 | */ | |
646 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
647 | { | |
648 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
649 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
650 | struct device *dev = trans->dev; | |
651 | int i; | |
652 | ||
653 | if (WARN_ON(!txq)) | |
654 | return; | |
655 | ||
656 | iwl_pcie_txq_unmap(trans, txq_id); | |
657 | ||
658 | /* De-alloc array of command/tx buffers */ | |
659 | if (txq_id == trans_pcie->cmd_queue) | |
660 | for (i = 0; i < txq->q.n_window; i++) { | |
5d4185ae JB |
661 | kzfree(txq->entries[i].cmd); |
662 | kzfree(txq->entries[i].free_buf); | |
f02831be EG |
663 | } |
664 | ||
665 | /* De-alloc circular buffer of TFDs */ | |
83f32a4b JB |
666 | if (txq->tfds) { |
667 | dma_free_coherent(dev, | |
668 | sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX, | |
669 | txq->tfds, txq->q.dma_addr); | |
d21fa2da | 670 | txq->q.dma_addr = 0; |
83f32a4b | 671 | txq->tfds = NULL; |
38c0f334 JB |
672 | |
673 | dma_free_coherent(dev, | |
674 | sizeof(*txq->scratchbufs) * txq->q.n_window, | |
675 | txq->scratchbufs, txq->scratchbufs_dma); | |
f02831be EG |
676 | } |
677 | ||
678 | kfree(txq->entries); | |
679 | txq->entries = NULL; | |
680 | ||
681 | del_timer_sync(&txq->stuck_timer); | |
682 | ||
683 | /* 0-fill queue descriptor structure */ | |
684 | memset(txq, 0, sizeof(*txq)); | |
685 | } | |
686 | ||
f02831be EG |
687 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) |
688 | { | |
689 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 690 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
691 | int chan; |
692 | u32 reg_val; | |
22dc3c95 JB |
693 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
694 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
695 | |
696 | /* make sure all queue are not stopped/used */ | |
697 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
698 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
699 | ||
700 | trans_pcie->scd_base_addr = | |
701 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
702 | ||
703 | WARN_ON(scd_base_addr != 0 && | |
704 | scd_base_addr != trans_pcie->scd_base_addr); | |
705 | ||
22dc3c95 JB |
706 | /* reset context data, TX status and translation data */ |
707 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
708 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
709 | NULL, clear_dwords); | |
f02831be EG |
710 | |
711 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
712 | trans_pcie->scd_bc_tbls.dma >> 10); | |
713 | ||
714 | /* The chain extension of the SCD doesn't work well. This feature is | |
715 | * enabled by default by the HW, so we need to disable it manually. | |
716 | */ | |
e03bbb62 EG |
717 | if (trans->cfg->base_params->scd_chain_ext_wa) |
718 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
f02831be EG |
719 | |
720 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
4cf677fd EG |
721 | trans_pcie->cmd_fifo, |
722 | trans_pcie->cmd_q_wdg_timeout); | |
f02831be EG |
723 | |
724 | /* Activate all Tx DMA/FIFO channels */ | |
680073b7 | 725 | iwl_scd_activate_fifos(trans); |
f02831be EG |
726 | |
727 | /* Enable DMA channel */ | |
728 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
729 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
730 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
731 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
732 | ||
733 | /* Update FH chicken bits */ | |
734 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
735 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
736 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
737 | ||
738 | /* Enable L1-Active */ | |
3073d8c0 EH |
739 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
740 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
741 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
f02831be EG |
742 | } |
743 | ||
ddaf5a5b JB |
744 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
745 | { | |
746 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
747 | int txq_id; | |
748 | ||
749 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
750 | txq_id++) { | |
751 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
752 | ||
753 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
754 | txq->q.dma_addr >> 8); | |
755 | iwl_pcie_txq_unmap(trans, txq_id); | |
756 | txq->q.read_ptr = 0; | |
757 | txq->q.write_ptr = 0; | |
758 | } | |
759 | ||
760 | /* Tell NIC where to find the "keep warm" buffer */ | |
761 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
762 | trans_pcie->kw.dma >> 4); | |
763 | ||
cd8f4384 EG |
764 | /* |
765 | * Send 0 as the scd_base_addr since the device may have be reset | |
766 | * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will | |
767 | * contain garbage. | |
768 | */ | |
769 | iwl_pcie_tx_start(trans, 0); | |
ddaf5a5b JB |
770 | } |
771 | ||
36277234 EG |
772 | static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) |
773 | { | |
774 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
775 | unsigned long flags; | |
776 | int ch, ret; | |
777 | u32 mask = 0; | |
778 | ||
779 | spin_lock(&trans_pcie->irq_lock); | |
780 | ||
23ba9340 | 781 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
36277234 EG |
782 | goto out; |
783 | ||
784 | /* Stop each Tx DMA channel */ | |
785 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
786 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
787 | mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); | |
788 | } | |
789 | ||
790 | /* Wait for DMA channels to be idle */ | |
791 | ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); | |
792 | if (ret < 0) | |
793 | IWL_ERR(trans, | |
794 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
795 | ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); | |
796 | ||
797 | iwl_trans_release_nic_access(trans, &flags); | |
798 | ||
799 | out: | |
800 | spin_unlock(&trans_pcie->irq_lock); | |
801 | } | |
802 | ||
f02831be EG |
803 | /* |
804 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
805 | */ | |
806 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
807 | { | |
808 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
36277234 | 809 | int txq_id; |
f02831be EG |
810 | |
811 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 812 | iwl_scd_deactivate_fifos(trans); |
f02831be | 813 | |
36277234 EG |
814 | /* Turn off all Tx DMA channels */ |
815 | iwl_pcie_tx_stop_fh(trans); | |
f02831be | 816 | |
fba1c627 EG |
817 | /* |
818 | * This function can be called before the op_mode disabled the | |
819 | * queues. This happens when we have an rfkill interrupt. | |
820 | * Since we stop Tx altogether - mark the queues as stopped. | |
821 | */ | |
822 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
823 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
824 | ||
825 | /* This can happen: start_hw, stop_device */ | |
826 | if (!trans_pcie->txq) | |
f02831be | 827 | return 0; |
f02831be EG |
828 | |
829 | /* Unmap DMA from host system and free skb's */ | |
830 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
831 | txq_id++) | |
832 | iwl_pcie_txq_unmap(trans, txq_id); | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
837 | /* | |
838 | * iwl_trans_tx_free - Free TXQ Context | |
839 | * | |
840 | * Destroy all TX DMA queues and structures | |
841 | */ | |
842 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
843 | { | |
844 | int txq_id; | |
845 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
846 | ||
847 | /* Tx queues */ | |
848 | if (trans_pcie->txq) { | |
849 | for (txq_id = 0; | |
850 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
851 | iwl_pcie_txq_free(trans, txq_id); | |
852 | } | |
853 | ||
854 | kfree(trans_pcie->txq); | |
855 | trans_pcie->txq = NULL; | |
856 | ||
857 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
858 | ||
859 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
860 | } | |
861 | ||
862 | /* | |
863 | * iwl_pcie_tx_alloc - allocate TX context | |
864 | * Allocate all Tx DMA structures and initialize them | |
865 | */ | |
866 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
867 | { | |
868 | int ret; | |
869 | int txq_id, slots_num; | |
870 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
871 | ||
872 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
873 | sizeof(struct iwlagn_scd_bc_tbl); | |
874 | ||
875 | /*It is not allowed to alloc twice, so warn when this happens. | |
876 | * We cannot rely on the previous allocation, so free and fail */ | |
877 | if (WARN_ON(trans_pcie->txq)) { | |
878 | ret = -EINVAL; | |
879 | goto error; | |
880 | } | |
881 | ||
882 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
883 | scd_bc_tbls_size); | |
884 | if (ret) { | |
885 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
886 | goto error; | |
887 | } | |
888 | ||
889 | /* Alloc keep-warm buffer */ | |
890 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
891 | if (ret) { | |
892 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
893 | goto error; | |
894 | } | |
895 | ||
896 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
897 | sizeof(struct iwl_txq), GFP_KERNEL); | |
898 | if (!trans_pcie->txq) { | |
899 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
2ab9ba0f | 900 | ret = -ENOMEM; |
f02831be EG |
901 | goto error; |
902 | } | |
903 | ||
904 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
905 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
906 | txq_id++) { | |
907 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
908 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
909 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
910 | slots_num, txq_id); | |
911 | if (ret) { | |
912 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
913 | goto error; | |
914 | } | |
915 | } | |
916 | ||
917 | return 0; | |
918 | ||
919 | error: | |
920 | iwl_pcie_tx_free(trans); | |
921 | ||
922 | return ret; | |
923 | } | |
924 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
925 | { | |
926 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
927 | int ret; | |
928 | int txq_id, slots_num; | |
f02831be EG |
929 | bool alloc = false; |
930 | ||
931 | if (!trans_pcie->txq) { | |
932 | ret = iwl_pcie_tx_alloc(trans); | |
933 | if (ret) | |
934 | goto error; | |
935 | alloc = true; | |
936 | } | |
937 | ||
7b70bd63 | 938 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
939 | |
940 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 941 | iwl_scd_deactivate_fifos(trans); |
f02831be EG |
942 | |
943 | /* Tell NIC where to find the "keep warm" buffer */ | |
944 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
945 | trans_pcie->kw.dma >> 4); | |
946 | ||
7b70bd63 | 947 | spin_unlock(&trans_pcie->irq_lock); |
f02831be EG |
948 | |
949 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
950 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
951 | txq_id++) { | |
952 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
953 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
954 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
955 | slots_num, txq_id); | |
956 | if (ret) { | |
957 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
958 | goto error; | |
959 | } | |
960 | } | |
961 | ||
94ce9e5e | 962 | iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); |
cb6bb128 EG |
963 | if (trans->cfg->base_params->num_of_queues > 20) |
964 | iwl_set_bits_prph(trans, SCD_GP_CTRL, | |
965 | SCD_GP_CTRL_ENABLE_31_QUEUES); | |
966 | ||
f02831be EG |
967 | return 0; |
968 | error: | |
969 | /*Upon error, free only if we allocated something */ | |
970 | if (alloc) | |
971 | iwl_pcie_tx_free(trans); | |
972 | return ret; | |
973 | } | |
974 | ||
4cf677fd | 975 | static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) |
f02831be | 976 | { |
e0b8d405 EG |
977 | lockdep_assert_held(&txq->lock); |
978 | ||
4cf677fd | 979 | if (!txq->wd_timeout) |
f02831be EG |
980 | return; |
981 | ||
e0b8d405 EG |
982 | /* |
983 | * station is asleep and we send data - that must | |
984 | * be uAPSD or PS-Poll. Don't rearm the timer. | |
985 | */ | |
986 | if (txq->frozen) | |
987 | return; | |
988 | ||
f02831be EG |
989 | /* |
990 | * if empty delete timer, otherwise move timer forward | |
991 | * since we're making progress on this queue | |
992 | */ | |
993 | if (txq->q.read_ptr == txq->q.write_ptr) | |
994 | del_timer(&txq->stuck_timer); | |
995 | else | |
4cf677fd | 996 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); |
f02831be EG |
997 | } |
998 | ||
999 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
1000 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
1001 | struct sk_buff_head *skbs) | |
f02831be EG |
1002 | { |
1003 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1004 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
83f32a4b | 1005 | int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); |
f02831be EG |
1006 | struct iwl_queue *q = &txq->q; |
1007 | int last_to_free; | |
f02831be EG |
1008 | |
1009 | /* This function is not meant to release cmd queue*/ | |
1010 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 1011 | return; |
214d14d4 | 1012 | |
2bfb5092 | 1013 | spin_lock_bh(&txq->lock); |
f6d497cd | 1014 | |
b967613d EG |
1015 | if (!txq->active) { |
1016 | IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", | |
1017 | txq_id, ssn); | |
1018 | goto out; | |
1019 | } | |
1020 | ||
f6d497cd EG |
1021 | if (txq->q.read_ptr == tfd_num) |
1022 | goto out; | |
1023 | ||
1024 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
1025 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 1026 | |
f02831be EG |
1027 | /*Since we free until index _not_ inclusive, the one before index is |
1028 | * the last we will free. This one must be used */ | |
83f32a4b | 1029 | last_to_free = iwl_queue_dec_wrap(tfd_num); |
f02831be | 1030 | |
6ca6ebc1 | 1031 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
1032 | IWL_ERR(trans, |
1033 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 1034 | __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, |
f02831be | 1035 | q->write_ptr, q->read_ptr); |
f6d497cd | 1036 | goto out; |
214d14d4 JB |
1037 | } |
1038 | ||
f02831be | 1039 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 1040 | goto out; |
214d14d4 | 1041 | |
f02831be | 1042 | for (; |
f6d497cd | 1043 | q->read_ptr != tfd_num; |
83f32a4b | 1044 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { |
6eb5e529 | 1045 | struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb; |
214d14d4 | 1046 | |
6eb5e529 | 1047 | if (WARN_ON_ONCE(!skb)) |
f02831be | 1048 | continue; |
214d14d4 | 1049 | |
6eb5e529 EG |
1050 | iwl_pcie_free_tso_page(skb); |
1051 | ||
1052 | __skb_queue_tail(skbs, skb); | |
214d14d4 | 1053 | |
f02831be | 1054 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 1055 | |
f02831be | 1056 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 1057 | |
98891754 | 1058 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 1059 | } |
fd4abac5 | 1060 | |
4cf677fd | 1061 | iwl_pcie_txq_progress(txq); |
f02831be | 1062 | |
3955525d EG |
1063 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && |
1064 | test_bit(txq_id, trans_pcie->queue_stopped)) { | |
685b346c | 1065 | struct sk_buff_head overflow_skbs; |
3955525d | 1066 | |
685b346c EG |
1067 | __skb_queue_head_init(&overflow_skbs); |
1068 | skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); | |
3955525d EG |
1069 | |
1070 | /* | |
1071 | * This is tricky: we are in reclaim path which is non | |
1072 | * re-entrant, so noone will try to take the access the | |
1073 | * txq data from that path. We stopped tx, so we can't | |
1074 | * have tx as well. Bottom line, we can unlock and re-lock | |
1075 | * later. | |
1076 | */ | |
1077 | spin_unlock_bh(&txq->lock); | |
1078 | ||
685b346c EG |
1079 | while (!skb_queue_empty(&overflow_skbs)) { |
1080 | struct sk_buff *skb = __skb_dequeue(&overflow_skbs); | |
3955525d EG |
1081 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
1082 | u8 dev_cmd_idx = IWL_TRANS_FIRST_DRIVER_DATA + 1; | |
1083 | struct iwl_device_cmd *dev_cmd = | |
1084 | info->driver_data[dev_cmd_idx]; | |
1085 | ||
1086 | /* | |
1087 | * Note that we can very well be overflowing again. | |
1088 | * In that case, iwl_queue_space will be small again | |
1089 | * and we won't wake mac80211's queue. | |
1090 | */ | |
1091 | iwl_trans_pcie_tx(trans, skb, dev_cmd, txq_id); | |
1092 | } | |
1093 | spin_lock_bh(&txq->lock); | |
1094 | ||
1095 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) | |
1096 | iwl_wake_queue(trans, txq); | |
1097 | } | |
7616f334 EP |
1098 | |
1099 | if (q->read_ptr == q->write_ptr) { | |
1100 | IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id); | |
1101 | iwl_trans_pcie_unref(trans); | |
1102 | } | |
1103 | ||
f6d497cd | 1104 | out: |
2bfb5092 | 1105 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
1106 | } |
1107 | ||
7616f334 EP |
1108 | static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, |
1109 | const struct iwl_host_cmd *cmd) | |
804d4c5a EP |
1110 | { |
1111 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1112 | int ret; | |
1113 | ||
1114 | lockdep_assert_held(&trans_pcie->reg_lock); | |
1115 | ||
7616f334 EP |
1116 | if (!(cmd->flags & CMD_SEND_IN_IDLE) && |
1117 | !trans_pcie->ref_cmd_in_flight) { | |
1118 | trans_pcie->ref_cmd_in_flight = true; | |
1119 | IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); | |
1120 | iwl_trans_pcie_ref(trans); | |
1121 | } | |
1122 | ||
804d4c5a EP |
1123 | /* |
1124 | * wake up the NIC to make sure that the firmware will see the host | |
1125 | * command - we will let the NIC sleep once all the host commands | |
1126 | * returned. This needs to be done only on NICs that have | |
1127 | * apmg_wake_up_wa set. | |
1128 | */ | |
fc8a350d IP |
1129 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1130 | !trans_pcie->cmd_hold_nic_awake) { | |
804d4c5a EP |
1131 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
1132 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1133 | |
1134 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1135 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1136 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1137 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), | |
1138 | 15000); | |
1139 | if (ret < 0) { | |
1140 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
1141 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1142 | IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); |
1143 | return -EIO; | |
1144 | } | |
fc8a350d | 1145 | trans_pcie->cmd_hold_nic_awake = true; |
804d4c5a EP |
1146 | } |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) | |
1152 | { | |
1153 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1154 | ||
1155 | lockdep_assert_held(&trans_pcie->reg_lock); | |
1156 | ||
7616f334 EP |
1157 | if (trans_pcie->ref_cmd_in_flight) { |
1158 | trans_pcie->ref_cmd_in_flight = false; | |
1159 | IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); | |
1160 | iwl_trans_pcie_unref(trans); | |
1161 | } | |
1162 | ||
fc8a350d IP |
1163 | if (trans->cfg->base_params->apmg_wake_up_wa) { |
1164 | if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) | |
1165 | return 0; | |
804d4c5a | 1166 | |
fc8a350d | 1167 | trans_pcie->cmd_hold_nic_awake = false; |
804d4c5a | 1168 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
fc8a350d IP |
1169 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
1170 | } | |
804d4c5a EP |
1171 | return 0; |
1172 | } | |
1173 | ||
f02831be EG |
1174 | /* |
1175 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
1176 | * | |
1177 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1178 | * need to be reclaimed. As result, some free space forms. If there is | |
1179 | * enough free space (> low mark), wake the stack that feeds us. | |
1180 | */ | |
1181 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 1182 | { |
f02831be EG |
1183 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1184 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
1185 | struct iwl_queue *q = &txq->q; | |
b9439491 | 1186 | unsigned long flags; |
f02831be | 1187 | int nfreed = 0; |
48d42c42 | 1188 | |
f02831be | 1189 | lockdep_assert_held(&txq->lock); |
48d42c42 | 1190 | |
83f32a4b | 1191 | if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
1192 | IWL_ERR(trans, |
1193 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 1194 | __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, |
f02831be EG |
1195 | q->write_ptr, q->read_ptr); |
1196 | return; | |
1197 | } | |
48d42c42 | 1198 | |
83f32a4b JB |
1199 | for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx; |
1200 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { | |
48d42c42 | 1201 | |
f02831be EG |
1202 | if (nfreed++ > 0) { |
1203 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1204 | idx, q->write_ptr, q->read_ptr); | |
4c9706dc | 1205 | iwl_force_nmi(trans); |
f02831be EG |
1206 | } |
1207 | } | |
1208 | ||
804d4c5a | 1209 | if (q->read_ptr == q->write_ptr) { |
b9439491 | 1210 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
804d4c5a | 1211 | iwl_pcie_clear_cmd_in_flight(trans); |
b9439491 EG |
1212 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1213 | } | |
1214 | ||
4cf677fd | 1215 | iwl_pcie_txq_progress(txq); |
48d42c42 EG |
1216 | } |
1217 | ||
f02831be | 1218 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1219 | u16 txq_id) |
48d42c42 | 1220 | { |
20d3b647 | 1221 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1222 | u32 tbl_dw_addr; |
1223 | u32 tbl_dw; | |
1224 | u16 scd_q2ratid; | |
1225 | ||
1226 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1227 | ||
105183b1 | 1228 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1229 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1230 | ||
4fd442db | 1231 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1232 | |
1233 | if (txq_id & 0x1) | |
1234 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1235 | else | |
1236 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1237 | ||
4fd442db | 1238 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1239 | |
1240 | return 0; | |
1241 | } | |
1242 | ||
bd5f6a34 EG |
1243 | /* Receiver address (actually, Rx station's index into station table), |
1244 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1245 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1246 | ||
fea7795f | 1247 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, |
4cf677fd EG |
1248 | const struct iwl_trans_txq_scd_cfg *cfg, |
1249 | unsigned int wdg_timeout) | |
48d42c42 | 1250 | { |
9eae88fa | 1251 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4cf677fd | 1252 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; |
d4578ea8 | 1253 | int fifo = -1; |
4beaf6c2 | 1254 | |
9eae88fa JB |
1255 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1256 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1257 | |
4cf677fd EG |
1258 | txq->wd_timeout = msecs_to_jiffies(wdg_timeout); |
1259 | ||
d4578ea8 JB |
1260 | if (cfg) { |
1261 | fifo = cfg->fifo; | |
48d42c42 | 1262 | |
002a9e26 | 1263 | /* Disable the scheduler prior configuring the cmd queue */ |
3a736bcb EG |
1264 | if (txq_id == trans_pcie->cmd_queue && |
1265 | trans_pcie->scd_set_active) | |
002a9e26 AA |
1266 | iwl_scd_enable_set_active(trans, 0); |
1267 | ||
d4578ea8 JB |
1268 | /* Stop this Tx queue before configuring it */ |
1269 | iwl_scd_txq_set_inactive(trans, txq_id); | |
4beaf6c2 | 1270 | |
d4578ea8 JB |
1271 | /* Set this queue as a chain-building queue unless it is CMD */ |
1272 | if (txq_id != trans_pcie->cmd_queue) | |
1273 | iwl_scd_txq_set_chain(trans, txq_id); | |
48d42c42 | 1274 | |
64ba8930 | 1275 | if (cfg->aggregate) { |
d4578ea8 | 1276 | u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); |
48d42c42 | 1277 | |
d4578ea8 JB |
1278 | /* Map receiver-address / traffic-ID to this queue */ |
1279 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); | |
f4772520 | 1280 | |
d4578ea8 JB |
1281 | /* enable aggregations for the queue */ |
1282 | iwl_scd_txq_enable_agg(trans, txq_id); | |
4cf677fd | 1283 | txq->ampdu = true; |
d4578ea8 JB |
1284 | } else { |
1285 | /* | |
1286 | * disable aggregations for the queue, this will also | |
1287 | * make the ra_tid mapping configuration irrelevant | |
1288 | * since it is now a non-AGG queue. | |
1289 | */ | |
1290 | iwl_scd_txq_disable_agg(trans, txq_id); | |
1291 | ||
4cf677fd | 1292 | ssn = txq->q.read_ptr; |
d4578ea8 | 1293 | } |
4beaf6c2 | 1294 | } |
48d42c42 EG |
1295 | |
1296 | /* Place first TFD at index corresponding to start sequence number. | |
1297 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
4cf677fd EG |
1298 | txq->q.read_ptr = (ssn & 0xff); |
1299 | txq->q.write_ptr = (ssn & 0xff); | |
0294d9ee EG |
1300 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
1301 | (ssn & 0xff) | (txq_id << 8)); | |
1ce8658c | 1302 | |
d4578ea8 JB |
1303 | if (cfg) { |
1304 | u8 frame_limit = cfg->frame_limit; | |
48d42c42 | 1305 | |
d4578ea8 JB |
1306 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); |
1307 | ||
1308 | /* Set up Tx window size and frame limit for this queue */ | |
1309 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + | |
1310 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | |
1311 | iwl_trans_write_mem32(trans, | |
1312 | trans_pcie->scd_base_addr + | |
9eae88fa JB |
1313 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1314 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
d4578ea8 | 1315 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | |
9eae88fa | 1316 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & |
d4578ea8 JB |
1317 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); |
1318 | ||
1319 | /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ | |
1320 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), | |
1321 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1322 | (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1323 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1324 | SCD_QUEUE_STTS_REG_MSK); | |
002a9e26 AA |
1325 | |
1326 | /* enable the scheduler for this queue (only) */ | |
3a736bcb EG |
1327 | if (txq_id == trans_pcie->cmd_queue && |
1328 | trans_pcie->scd_set_active) | |
002a9e26 | 1329 | iwl_scd_enable_set_active(trans, BIT(txq_id)); |
0294d9ee EG |
1330 | |
1331 | IWL_DEBUG_TX_QUEUES(trans, | |
1332 | "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1333 | txq_id, fifo, ssn & 0xff); | |
1334 | } else { | |
1335 | IWL_DEBUG_TX_QUEUES(trans, | |
1336 | "Activate queue %d WrPtr: %d\n", | |
1337 | txq_id, ssn & 0xff); | |
d4578ea8 JB |
1338 | } |
1339 | ||
4cf677fd | 1340 | txq->active = true; |
4beaf6c2 EG |
1341 | } |
1342 | ||
d4578ea8 JB |
1343 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, |
1344 | bool configure_scd) | |
288712a6 | 1345 | { |
8ad71bef | 1346 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1347 | u32 stts_addr = trans_pcie->scd_base_addr + |
1348 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1349 | static const u32 zero_val[4] = {}; | |
288712a6 | 1350 | |
e0b8d405 EG |
1351 | trans_pcie->txq[txq_id].frozen_expiry_remainder = 0; |
1352 | trans_pcie->txq[txq_id].frozen = false; | |
1353 | ||
fba1c627 EG |
1354 | /* |
1355 | * Upon HW Rfkill - we stop the device, and then stop the queues | |
1356 | * in the op_mode. Just for the sake of the simplicity of the op_mode, | |
1357 | * allow the op_mode to call txq_disable after it already called | |
1358 | * stop_device. | |
1359 | */ | |
9eae88fa | 1360 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
fba1c627 EG |
1361 | WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), |
1362 | "queue %d not used", txq_id); | |
9eae88fa | 1363 | return; |
48d42c42 EG |
1364 | } |
1365 | ||
d4578ea8 JB |
1366 | if (configure_scd) { |
1367 | iwl_scd_txq_set_inactive(trans, txq_id); | |
ac928f8d | 1368 | |
d4578ea8 JB |
1369 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1370 | ARRAY_SIZE(zero_val)); | |
1371 | } | |
986ea6c9 | 1372 | |
990aa6d7 | 1373 | iwl_pcie_txq_unmap(trans, txq_id); |
68972c46 | 1374 | trans_pcie->txq[txq_id].ampdu = false; |
6c3fd3f0 | 1375 | |
1ce8658c | 1376 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1377 | } |
1378 | ||
fd4abac5 TW |
1379 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1380 | ||
990aa6d7 | 1381 | /* |
f02831be | 1382 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 | 1383 | * @priv: device private data point |
e89044d7 | 1384 | * @cmd: a pointer to the ucode command structure |
fd4abac5 | 1385 | * |
e89044d7 EP |
1386 | * The function returns < 0 values to indicate the operation |
1387 | * failed. On success, it returns the index (>= 0) of command in the | |
fd4abac5 TW |
1388 | * command queue. |
1389 | */ | |
f02831be EG |
1390 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1391 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1392 | { |
8ad71bef | 1393 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1394 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1395 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1396 | struct iwl_device_cmd *out_cmd; |
1397 | struct iwl_cmd_meta *out_meta; | |
b9439491 | 1398 | unsigned long flags; |
f4feb8ac | 1399 | void *dup_buf = NULL; |
fd4abac5 | 1400 | dma_addr_t phys_addr; |
f4feb8ac | 1401 | int idx; |
38c0f334 | 1402 | u16 copy_size, cmd_size, scratch_size; |
4ce7cc2b | 1403 | bool had_nocopy = false; |
ab02165c | 1404 | u8 group_id = iwl_cmd_groupid(cmd->id); |
b9439491 | 1405 | int i, ret; |
96791422 | 1406 | u32 cmd_pos; |
1afbfb60 JB |
1407 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1408 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1409 | |
88742c9e JB |
1410 | if (WARN(!trans_pcie->wide_cmd_header && |
1411 | group_id > IWL_ALWAYS_LONG_GROUP, | |
ab02165c AE |
1412 | "unsupported wide command %#x\n", cmd->id)) |
1413 | return -EINVAL; | |
1414 | ||
1415 | if (group_id != 0) { | |
1416 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1417 | cmd_size = sizeof(struct iwl_cmd_header_wide); | |
1418 | } else { | |
1419 | copy_size = sizeof(struct iwl_cmd_header); | |
1420 | cmd_size = sizeof(struct iwl_cmd_header); | |
1421 | } | |
4ce7cc2b JB |
1422 | |
1423 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1424 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1425 | |
1afbfb60 | 1426 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1427 | cmddata[i] = cmd->data[i]; |
1428 | cmdlen[i] = cmd->len[i]; | |
1429 | ||
4ce7cc2b JB |
1430 | if (!cmd->len[i]) |
1431 | continue; | |
8a964f44 | 1432 | |
38c0f334 JB |
1433 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1434 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1435 | int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1436 | |
1437 | if (copy > cmdlen[i]) | |
1438 | copy = cmdlen[i]; | |
1439 | cmdlen[i] -= copy; | |
1440 | cmddata[i] += copy; | |
1441 | copy_size += copy; | |
1442 | } | |
1443 | ||
4ce7cc2b JB |
1444 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1445 | had_nocopy = true; | |
f4feb8ac JB |
1446 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1447 | idx = -EINVAL; | |
1448 | goto free_dup_buf; | |
1449 | } | |
1450 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1451 | /* | |
1452 | * This is also a chunk that isn't copied | |
1453 | * to the static buffer so set had_nocopy. | |
1454 | */ | |
1455 | had_nocopy = true; | |
1456 | ||
1457 | /* only allowed once */ | |
1458 | if (WARN_ON(dup_buf)) { | |
1459 | idx = -EINVAL; | |
1460 | goto free_dup_buf; | |
1461 | } | |
1462 | ||
8a964f44 | 1463 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1464 | GFP_ATOMIC); |
1465 | if (!dup_buf) | |
1466 | return -ENOMEM; | |
4ce7cc2b JB |
1467 | } else { |
1468 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1469 | if (WARN_ON(had_nocopy)) { |
1470 | idx = -EINVAL; | |
1471 | goto free_dup_buf; | |
1472 | } | |
8a964f44 | 1473 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1474 | } |
1475 | cmd_size += cmd->len[i]; | |
1476 | } | |
fd4abac5 | 1477 | |
3e41ace5 JB |
1478 | /* |
1479 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1480 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1481 | * allocated into separate TFDs, then we will need to | |
1482 | * increase the size of the buffers. | |
3e41ace5 | 1483 | */ |
2a79e45e JB |
1484 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1485 | "Command %s (%#x) is too large (%d bytes)\n", | |
39bdb17e SD |
1486 | iwl_get_cmd_string(trans, cmd->id), |
1487 | cmd->id, copy_size)) { | |
f4feb8ac JB |
1488 | idx = -EINVAL; |
1489 | goto free_dup_buf; | |
1490 | } | |
fd4abac5 | 1491 | |
015c15e1 | 1492 | spin_lock_bh(&txq->lock); |
3598e177 | 1493 | |
c2acea8e | 1494 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1495 | spin_unlock_bh(&txq->lock); |
3598e177 | 1496 | |
6d8f6eeb | 1497 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1498 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1499 | idx = -ENOSPC; |
1500 | goto free_dup_buf; | |
fd4abac5 TW |
1501 | } |
1502 | ||
4ce7cc2b | 1503 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1504 | out_cmd = txq->entries[idx].cmd; |
1505 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1506 | |
8ce73f3a | 1507 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1508 | if (cmd->flags & CMD_WANT_SKB) |
1509 | out_meta->source = cmd; | |
fd4abac5 | 1510 | |
4ce7cc2b | 1511 | /* set up the header */ |
ab02165c AE |
1512 | if (group_id != 0) { |
1513 | out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); | |
1514 | out_cmd->hdr_wide.group_id = group_id; | |
1515 | out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); | |
1516 | out_cmd->hdr_wide.length = | |
1517 | cpu_to_le16(cmd_size - | |
1518 | sizeof(struct iwl_cmd_header_wide)); | |
1519 | out_cmd->hdr_wide.reserved = 0; | |
1520 | out_cmd->hdr_wide.sequence = | |
1521 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
1522 | INDEX_TO_SEQ(q->write_ptr)); | |
1523 | ||
1524 | cmd_pos = sizeof(struct iwl_cmd_header_wide); | |
1525 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1526 | } else { | |
1527 | out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); | |
1528 | out_cmd->hdr.sequence = | |
1529 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
1530 | INDEX_TO_SEQ(q->write_ptr)); | |
1531 | out_cmd->hdr.group_id = 0; | |
1532 | ||
1533 | cmd_pos = sizeof(struct iwl_cmd_header); | |
1534 | copy_size = sizeof(struct iwl_cmd_header); | |
1535 | } | |
4ce7cc2b JB |
1536 | |
1537 | /* and copy the data that needs to be copied */ | |
1afbfb60 | 1538 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
4d075007 | 1539 | int copy; |
8a964f44 | 1540 | |
cc904c71 | 1541 | if (!cmd->len[i]) |
4ce7cc2b | 1542 | continue; |
8a964f44 | 1543 | |
8a964f44 JB |
1544 | /* copy everything if not nocopy/dup */ |
1545 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
4d075007 | 1546 | IWL_HCMD_DFL_DUP))) { |
8a964f44 JB |
1547 | copy = cmd->len[i]; |
1548 | ||
8a964f44 JB |
1549 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); |
1550 | cmd_pos += copy; | |
1551 | copy_size += copy; | |
4d075007 JB |
1552 | continue; |
1553 | } | |
1554 | ||
1555 | /* | |
1556 | * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied | |
1557 | * in total (for the scratchbuf handling), but copy up to what | |
1558 | * we can fit into the payload for debug dump purposes. | |
1559 | */ | |
1560 | copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); | |
1561 | ||
1562 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1563 | cmd_pos += copy; | |
1564 | ||
1565 | /* However, treat copy_size the proper way, we need it below */ | |
1566 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1567 | copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
1568 | ||
1569 | if (copy > cmd->len[i]) | |
1570 | copy = cmd->len[i]; | |
1571 | copy_size += copy; | |
8a964f44 | 1572 | } |
96791422 EG |
1573 | } |
1574 | ||
d9fb6465 | 1575 | IWL_DEBUG_HC(trans, |
ab02165c | 1576 | "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
39bdb17e | 1577 | iwl_get_cmd_string(trans, cmd->id), |
ab02165c AE |
1578 | group_id, out_cmd->hdr.cmd, |
1579 | le16_to_cpu(out_cmd->hdr.sequence), | |
20d3b647 | 1580 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); |
4ce7cc2b | 1581 | |
38c0f334 JB |
1582 | /* start the TFD with the scratchbuf */ |
1583 | scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); | |
1584 | memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); | |
1585 | iwl_pcie_txq_build_tfd(trans, txq, | |
1586 | iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), | |
6d6e68f8 | 1587 | scratch_size, true); |
38c0f334 JB |
1588 | |
1589 | /* map first command fragment, if any remains */ | |
1590 | if (copy_size > scratch_size) { | |
1591 | phys_addr = dma_map_single(trans->dev, | |
1592 | ((u8 *)&out_cmd->hdr) + scratch_size, | |
1593 | copy_size - scratch_size, | |
1594 | DMA_TO_DEVICE); | |
1595 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
1596 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1597 | &txq->tfds[q->write_ptr]); | |
1598 | idx = -ENOMEM; | |
1599 | goto out; | |
1600 | } | |
8a964f44 | 1601 | |
38c0f334 | 1602 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
6d6e68f8 | 1603 | copy_size - scratch_size, false); |
2c46f72e JB |
1604 | } |
1605 | ||
8a964f44 | 1606 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1607 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1608 | const void *data = cmddata[i]; |
f4feb8ac | 1609 | |
8a964f44 | 1610 | if (!cmdlen[i]) |
4ce7cc2b | 1611 | continue; |
f4feb8ac JB |
1612 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1613 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1614 | continue; |
f4feb8ac JB |
1615 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1616 | data = dup_buf; | |
1617 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1618 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1619 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be | 1620 | iwl_pcie_tfd_unmap(trans, out_meta, |
98891754 | 1621 | &txq->tfds[q->write_ptr]); |
4ce7cc2b JB |
1622 | idx = -ENOMEM; |
1623 | goto out; | |
1624 | } | |
1625 | ||
6d6e68f8 | 1626 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); |
4ce7cc2b | 1627 | } |
df833b1d | 1628 | |
206eea78 JB |
1629 | BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS > |
1630 | sizeof(out_meta->flags) * BITS_PER_BYTE); | |
afaf6b57 | 1631 | out_meta->flags = cmd->flags; |
f4feb8ac | 1632 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
5d4185ae | 1633 | kzfree(txq->entries[idx].free_buf); |
f4feb8ac | 1634 | txq->entries[idx].free_buf = dup_buf; |
2c46f72e | 1635 | |
ab02165c | 1636 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); |
df833b1d | 1637 | |
7c5ba4a8 | 1638 | /* start timer if queue currently empty */ |
4cf677fd EG |
1639 | if (q->read_ptr == q->write_ptr && txq->wd_timeout) |
1640 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); | |
7c5ba4a8 | 1641 | |
b9439491 | 1642 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
7616f334 | 1643 | ret = iwl_pcie_set_cmd_in_flight(trans, cmd); |
804d4c5a EP |
1644 | if (ret < 0) { |
1645 | idx = ret; | |
1646 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1647 | goto out; | |
b9439491 EG |
1648 | } |
1649 | ||
fd4abac5 | 1650 | /* Increment and update queue's write index */ |
83f32a4b | 1651 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); |
990aa6d7 | 1652 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1653 | |
b9439491 EG |
1654 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1655 | ||
2c46f72e | 1656 | out: |
015c15e1 | 1657 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1658 | free_dup_buf: |
1659 | if (idx < 0) | |
1660 | kfree(dup_buf); | |
7bfedc59 | 1661 | return idx; |
fd4abac5 TW |
1662 | } |
1663 | ||
990aa6d7 EG |
1664 | /* |
1665 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1666 | * @rxb: Rx buffer to reclaim |
17b88929 | 1667 | */ |
990aa6d7 | 1668 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
f7e6469f | 1669 | struct iwl_rx_cmd_buffer *rxb) |
17b88929 | 1670 | { |
2f301227 | 1671 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 | 1672 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
39bdb17e SD |
1673 | u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id); |
1674 | u32 cmd_id; | |
17b88929 TW |
1675 | int txq_id = SEQ_TO_QUEUE(sequence); |
1676 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1677 | int cmd_index; |
c2acea8e JB |
1678 | struct iwl_device_cmd *cmd; |
1679 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1680 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1681 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1682 | |
1683 | /* If a Tx command is being handled and it isn't in the actual | |
1684 | * command queue then there a command routing bug has been introduced | |
1685 | * in the queue management code. */ | |
c6f600fc | 1686 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1687 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1688 | txq_id, trans_pcie->cmd_queue, sequence, |
1689 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1690 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1691 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1692 | return; |
01ef9323 | 1693 | } |
17b88929 | 1694 | |
2bfb5092 | 1695 | spin_lock_bh(&txq->lock); |
015c15e1 | 1696 | |
4ce7cc2b | 1697 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1698 | cmd = txq->entries[cmd_index].cmd; |
1699 | meta = &txq->entries[cmd_index].meta; | |
39bdb17e | 1700 | cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); |
17b88929 | 1701 | |
98891754 | 1702 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); |
c33de625 | 1703 | |
17b88929 | 1704 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1705 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1706 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1707 | |
65b94a4a JB |
1708 | meta->source->resp_pkt = pkt; |
1709 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1710 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1711 | } |
2624e96c | 1712 | |
dcbb4746 EG |
1713 | if (meta->flags & CMD_WANT_ASYNC_CALLBACK) |
1714 | iwl_op_mode_async_cb(trans->op_mode, cmd); | |
1715 | ||
f02831be | 1716 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1717 | |
c2acea8e | 1718 | if (!(meta->flags & CMD_ASYNC)) { |
eb7ff77e | 1719 | if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { |
05c89b91 WYG |
1720 | IWL_WARN(trans, |
1721 | "HCMD_ACTIVE already clear for command %s\n", | |
39bdb17e | 1722 | iwl_get_cmd_string(trans, cmd_id)); |
05c89b91 | 1723 | } |
eb7ff77e | 1724 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6d8f6eeb | 1725 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
39bdb17e | 1726 | iwl_get_cmd_string(trans, cmd_id)); |
f946b529 | 1727 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1728 | } |
3598e177 | 1729 | |
4cbb8e50 LC |
1730 | if (meta->flags & CMD_MAKE_TRANS_IDLE) { |
1731 | IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", | |
1732 | iwl_get_cmd_string(trans, cmd->hdr.cmd)); | |
1733 | set_bit(STATUS_TRANS_IDLE, &trans->status); | |
1734 | wake_up(&trans_pcie->d0i3_waitq); | |
1735 | } | |
1736 | ||
1737 | if (meta->flags & CMD_WAKE_UP_TRANS) { | |
1738 | IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", | |
1739 | iwl_get_cmd_string(trans, cmd->hdr.cmd)); | |
1740 | clear_bit(STATUS_TRANS_IDLE, &trans->status); | |
1741 | wake_up(&trans_pcie->d0i3_waitq); | |
1742 | } | |
1743 | ||
dd487449 | 1744 | meta->flags = 0; |
3598e177 | 1745 | |
2bfb5092 | 1746 | spin_unlock_bh(&txq->lock); |
17b88929 | 1747 | } |
253a634c | 1748 | |
9439eac7 | 1749 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
253a634c | 1750 | |
f02831be EG |
1751 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1752 | struct iwl_host_cmd *cmd) | |
253a634c EG |
1753 | { |
1754 | int ret; | |
1755 | ||
1756 | /* An asynchronous command can not expect an SKB to be set. */ | |
1757 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1758 | return -EINVAL; | |
1759 | ||
f02831be | 1760 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1761 | if (ret < 0) { |
721c32f7 | 1762 | IWL_ERR(trans, |
b36b110c | 1763 | "Error sending %s: enqueue_hcmd failed: %d\n", |
39bdb17e | 1764 | iwl_get_cmd_string(trans, cmd->id), ret); |
253a634c EG |
1765 | return ret; |
1766 | } | |
1767 | return 0; | |
1768 | } | |
1769 | ||
f02831be EG |
1770 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1771 | struct iwl_host_cmd *cmd) | |
253a634c | 1772 | { |
8ad71bef | 1773 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1774 | int cmd_idx; |
1775 | int ret; | |
1776 | ||
6d8f6eeb | 1777 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
39bdb17e | 1778 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c | 1779 | |
eb7ff77e AN |
1780 | if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, |
1781 | &trans->status), | |
bcbb8c9c | 1782 | "Command %s: a command is already active!\n", |
39bdb17e | 1783 | iwl_get_cmd_string(trans, cmd->id))) |
2cc39c94 | 1784 | return -EIO; |
2cc39c94 | 1785 | |
6d8f6eeb | 1786 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
39bdb17e | 1787 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c | 1788 | |
f02831be | 1789 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1790 | if (cmd_idx < 0) { |
1791 | ret = cmd_idx; | |
eb7ff77e | 1792 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
721c32f7 | 1793 | IWL_ERR(trans, |
b36b110c | 1794 | "Error sending %s: enqueue_hcmd failed: %d\n", |
39bdb17e | 1795 | iwl_get_cmd_string(trans, cmd->id), ret); |
253a634c EG |
1796 | return ret; |
1797 | } | |
1798 | ||
b9439491 EG |
1799 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
1800 | !test_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1801 | &trans->status), | |
1802 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1803 | if (!ret) { |
6dde8c48 JB |
1804 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
1805 | struct iwl_queue *q = &txq->q; | |
d10630af | 1806 | |
6dde8c48 | 1807 | IWL_ERR(trans, "Error sending %s: time out after %dms.\n", |
39bdb17e | 1808 | iwl_get_cmd_string(trans, cmd->id), |
6dde8c48 | 1809 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
253a634c | 1810 | |
6dde8c48 JB |
1811 | IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", |
1812 | q->read_ptr, q->write_ptr); | |
d10630af | 1813 | |
eb7ff77e | 1814 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6dde8c48 | 1815 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
39bdb17e | 1816 | iwl_get_cmd_string(trans, cmd->id)); |
6dde8c48 | 1817 | ret = -ETIMEDOUT; |
42550a53 | 1818 | |
4c9706dc | 1819 | iwl_force_nmi(trans); |
2a988e98 | 1820 | iwl_trans_fw_error(trans); |
42550a53 | 1821 | |
6dde8c48 | 1822 | goto cancel; |
253a634c EG |
1823 | } |
1824 | ||
eb7ff77e | 1825 | if (test_bit(STATUS_FW_ERROR, &trans->status)) { |
d18aa87f | 1826 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", |
39bdb17e | 1827 | iwl_get_cmd_string(trans, cmd->id)); |
b656fa33 | 1828 | dump_stack(); |
d18aa87f JB |
1829 | ret = -EIO; |
1830 | goto cancel; | |
1831 | } | |
1832 | ||
1094fa26 | 1833 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1834 | test_bit(STATUS_RFKILL, &trans->status)) { |
f946b529 EG |
1835 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1836 | ret = -ERFKILL; | |
1837 | goto cancel; | |
1838 | } | |
1839 | ||
65b94a4a | 1840 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1841 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
39bdb17e | 1842 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c EG |
1843 | ret = -EIO; |
1844 | goto cancel; | |
1845 | } | |
1846 | ||
1847 | return 0; | |
1848 | ||
1849 | cancel: | |
1850 | if (cmd->flags & CMD_WANT_SKB) { | |
1851 | /* | |
1852 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1853 | * TX cmd queue. Otherwise in case the cmd comes | |
1854 | * in later, it will possibly set an invalid | |
1855 | * address (cmd->meta.source). | |
1856 | */ | |
bf8440e6 JB |
1857 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1858 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1859 | } |
9cac4943 | 1860 | |
65b94a4a JB |
1861 | if (cmd->resp_pkt) { |
1862 | iwl_free_resp(cmd); | |
1863 | cmd->resp_pkt = NULL; | |
253a634c EG |
1864 | } |
1865 | ||
1866 | return ret; | |
1867 | } | |
1868 | ||
f02831be | 1869 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1870 | { |
4f59334b | 1871 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1872 | test_bit(STATUS_RFKILL, &trans->status)) { |
754d7d9e EG |
1873 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1874 | cmd->id); | |
f946b529 | 1875 | return -ERFKILL; |
754d7d9e | 1876 | } |
f946b529 | 1877 | |
253a634c | 1878 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1879 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1880 | |
f946b529 | 1881 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1882 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1883 | } |
1884 | ||
3a0b2a42 EG |
1885 | static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, |
1886 | struct iwl_txq *txq, u8 hdr_len, | |
1887 | struct iwl_cmd_meta *out_meta, | |
1888 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
1889 | { | |
1890 | struct iwl_queue *q = &txq->q; | |
1891 | u16 tb2_len; | |
1892 | int i; | |
1893 | ||
1894 | /* | |
1895 | * Set up TFD's third entry to point directly to remainder | |
1896 | * of skb's head, if any | |
1897 | */ | |
1898 | tb2_len = skb_headlen(skb) - hdr_len; | |
1899 | ||
1900 | if (tb2_len > 0) { | |
1901 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1902 | skb->data + hdr_len, | |
1903 | tb2_len, DMA_TO_DEVICE); | |
1904 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
1905 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1906 | &txq->tfds[q->write_ptr]); | |
1907 | return -EINVAL; | |
1908 | } | |
1909 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); | |
1910 | } | |
1911 | ||
1912 | /* set up the remaining entries to point to the data */ | |
1913 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1914 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1915 | dma_addr_t tb_phys; | |
1916 | int tb_idx; | |
1917 | ||
1918 | if (!skb_frag_size(frag)) | |
1919 | continue; | |
1920 | ||
1921 | tb_phys = skb_frag_dma_map(trans->dev, frag, 0, | |
1922 | skb_frag_size(frag), DMA_TO_DEVICE); | |
1923 | ||
1924 | if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { | |
1925 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1926 | &txq->tfds[q->write_ptr]); | |
1927 | return -EINVAL; | |
1928 | } | |
1929 | tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, | |
1930 | skb_frag_size(frag), false); | |
1931 | ||
1932 | out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS); | |
1933 | } | |
1934 | ||
1935 | trace_iwlwifi_dev_tx(trans->dev, skb, | |
1936 | &txq->tfds[txq->q.write_ptr], | |
1937 | sizeof(struct iwl_tfd), | |
1938 | &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, | |
1939 | skb->data + hdr_len, tb2_len); | |
1940 | trace_iwlwifi_dev_tx_data(trans->dev, skb, | |
1941 | hdr_len, skb->len - hdr_len); | |
1942 | return 0; | |
1943 | } | |
1944 | ||
6eb5e529 EG |
1945 | #ifdef CONFIG_INET |
1946 | static struct iwl_tso_hdr_page * | |
1947 | get_page_hdr(struct iwl_trans *trans, size_t len) | |
1948 | { | |
1949 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1950 | struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); | |
1951 | ||
1952 | if (!p->page) | |
1953 | goto alloc; | |
1954 | ||
1955 | /* enough room on this page */ | |
1956 | if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) | |
1957 | return p; | |
1958 | ||
1959 | /* We don't have enough room on this page, get a new one. */ | |
1960 | __free_page(p->page); | |
1961 | ||
1962 | alloc: | |
1963 | p->page = alloc_page(GFP_ATOMIC); | |
1964 | if (!p->page) | |
1965 | return NULL; | |
1966 | p->pos = page_address(p->page); | |
1967 | return p; | |
1968 | } | |
1969 | ||
1970 | static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, | |
1971 | bool ipv6, unsigned int len) | |
1972 | { | |
1973 | if (ipv6) { | |
1974 | struct ipv6hdr *iphv6 = iph; | |
1975 | ||
1976 | tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, | |
1977 | len + tcph->doff * 4, | |
1978 | IPPROTO_TCP, 0); | |
1979 | } else { | |
1980 | struct iphdr *iphv4 = iph; | |
1981 | ||
1982 | ip_send_check(iphv4); | |
1983 | tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, | |
1984 | len + tcph->doff * 4, | |
1985 | IPPROTO_TCP, 0); | |
1986 | } | |
1987 | } | |
1988 | ||
1989 | static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, | |
1990 | struct iwl_txq *txq, u8 hdr_len, | |
1991 | struct iwl_cmd_meta *out_meta, | |
1992 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
1993 | { | |
1994 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1995 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
1996 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
1997 | unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; | |
1998 | unsigned int mss = skb_shinfo(skb)->gso_size; | |
1999 | struct iwl_queue *q = &txq->q; | |
2000 | u16 length, iv_len, amsdu_pad; | |
2001 | u8 *start_hdr; | |
2002 | struct iwl_tso_hdr_page *hdr_page; | |
2003 | int ret; | |
2004 | struct tso_t tso; | |
2005 | ||
2006 | /* if the packet is protected, then it must be CCMP or GCMP */ | |
2007 | BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); | |
2008 | iv_len = ieee80211_has_protected(hdr->frame_control) ? | |
2009 | IEEE80211_CCMP_HDR_LEN : 0; | |
2010 | ||
2011 | trace_iwlwifi_dev_tx(trans->dev, skb, | |
2012 | &txq->tfds[txq->q.write_ptr], | |
2013 | sizeof(struct iwl_tfd), | |
2014 | &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, | |
2015 | NULL, 0); | |
2016 | ||
2017 | ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); | |
2018 | snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); | |
2019 | total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; | |
2020 | amsdu_pad = 0; | |
2021 | ||
2022 | /* total amount of header we may need for this A-MSDU */ | |
2023 | hdr_room = DIV_ROUND_UP(total_len, mss) * | |
2024 | (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; | |
2025 | ||
2026 | /* Our device supports 9 segments at most, it will fit in 1 page */ | |
2027 | hdr_page = get_page_hdr(trans, hdr_room); | |
2028 | if (!hdr_page) | |
2029 | return -ENOMEM; | |
2030 | ||
2031 | get_page(hdr_page->page); | |
2032 | start_hdr = hdr_page->pos; | |
2033 | info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = hdr_page->page; | |
2034 | memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); | |
2035 | hdr_page->pos += iv_len; | |
2036 | ||
2037 | /* | |
2038 | * Pull the ieee80211 header + IV to be able to use TSO core, | |
2039 | * we will restore it for the tx_status flow. | |
2040 | */ | |
2041 | skb_pull(skb, hdr_len + iv_len); | |
2042 | ||
2043 | tso_start(skb, &tso); | |
2044 | ||
2045 | while (total_len) { | |
2046 | /* this is the data left for this subframe */ | |
2047 | unsigned int data_left = | |
2048 | min_t(unsigned int, mss, total_len); | |
2049 | struct sk_buff *csum_skb = NULL; | |
2050 | unsigned int hdr_tb_len; | |
2051 | dma_addr_t hdr_tb_phys; | |
2052 | struct tcphdr *tcph; | |
2053 | u8 *iph; | |
2054 | ||
2055 | total_len -= data_left; | |
2056 | ||
2057 | memset(hdr_page->pos, 0, amsdu_pad); | |
2058 | hdr_page->pos += amsdu_pad; | |
2059 | amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + | |
2060 | data_left)) & 0x3; | |
2061 | ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); | |
2062 | hdr_page->pos += ETH_ALEN; | |
2063 | ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); | |
2064 | hdr_page->pos += ETH_ALEN; | |
2065 | ||
2066 | length = snap_ip_tcp_hdrlen + data_left; | |
2067 | *((__be16 *)hdr_page->pos) = cpu_to_be16(length); | |
2068 | hdr_page->pos += sizeof(length); | |
2069 | ||
2070 | /* | |
2071 | * This will copy the SNAP as well which will be considered | |
2072 | * as MAC header. | |
2073 | */ | |
2074 | tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); | |
2075 | iph = hdr_page->pos + 8; | |
2076 | tcph = (void *)(iph + ip_hdrlen); | |
2077 | ||
2078 | /* For testing on current hardware only */ | |
2079 | if (trans_pcie->sw_csum_tx) { | |
2080 | csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), | |
2081 | GFP_ATOMIC); | |
2082 | if (!csum_skb) { | |
2083 | ret = -ENOMEM; | |
2084 | goto out_unmap; | |
2085 | } | |
2086 | ||
2087 | iwl_compute_pseudo_hdr_csum(iph, tcph, | |
2088 | skb->protocol == | |
2089 | htons(ETH_P_IPV6), | |
2090 | data_left); | |
2091 | ||
2092 | memcpy(skb_put(csum_skb, tcp_hdrlen(skb)), | |
2093 | tcph, tcp_hdrlen(skb)); | |
2094 | skb_set_transport_header(csum_skb, 0); | |
2095 | csum_skb->csum_start = | |
2096 | (unsigned char *)tcp_hdr(csum_skb) - | |
2097 | csum_skb->head; | |
2098 | } | |
2099 | ||
2100 | hdr_page->pos += snap_ip_tcp_hdrlen; | |
2101 | ||
2102 | hdr_tb_len = hdr_page->pos - start_hdr; | |
2103 | hdr_tb_phys = dma_map_single(trans->dev, start_hdr, | |
2104 | hdr_tb_len, DMA_TO_DEVICE); | |
2105 | if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { | |
2106 | dev_kfree_skb(csum_skb); | |
2107 | ret = -EINVAL; | |
2108 | goto out_unmap; | |
2109 | } | |
2110 | iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, | |
2111 | hdr_tb_len, false); | |
2112 | trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, | |
2113 | hdr_tb_len); | |
2114 | ||
2115 | /* prepare the start_hdr for the next subframe */ | |
2116 | start_hdr = hdr_page->pos; | |
2117 | ||
2118 | /* put the payload */ | |
2119 | while (data_left) { | |
2120 | unsigned int size = min_t(unsigned int, tso.size, | |
2121 | data_left); | |
2122 | dma_addr_t tb_phys; | |
2123 | ||
2124 | if (trans_pcie->sw_csum_tx) | |
2125 | memcpy(skb_put(csum_skb, size), tso.data, size); | |
2126 | ||
2127 | tb_phys = dma_map_single(trans->dev, tso.data, | |
2128 | size, DMA_TO_DEVICE); | |
2129 | if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { | |
2130 | dev_kfree_skb(csum_skb); | |
2131 | ret = -EINVAL; | |
2132 | goto out_unmap; | |
2133 | } | |
2134 | ||
2135 | iwl_pcie_txq_build_tfd(trans, txq, tb_phys, | |
2136 | size, false); | |
2137 | trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, | |
2138 | size); | |
2139 | ||
2140 | data_left -= size; | |
2141 | tso_build_data(skb, &tso, size); | |
2142 | } | |
2143 | ||
2144 | /* For testing on early hardware only */ | |
2145 | if (trans_pcie->sw_csum_tx) { | |
2146 | __wsum csum; | |
2147 | ||
2148 | csum = skb_checksum(csum_skb, | |
2149 | skb_checksum_start_offset(csum_skb), | |
2150 | csum_skb->len - | |
2151 | skb_checksum_start_offset(csum_skb), | |
2152 | 0); | |
2153 | dev_kfree_skb(csum_skb); | |
2154 | dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, | |
2155 | hdr_tb_len, DMA_TO_DEVICE); | |
2156 | tcph->check = csum_fold(csum); | |
2157 | dma_sync_single_for_device(trans->dev, hdr_tb_phys, | |
2158 | hdr_tb_len, DMA_TO_DEVICE); | |
2159 | } | |
2160 | } | |
2161 | ||
2162 | /* re -add the WiFi header and IV */ | |
2163 | skb_push(skb, hdr_len + iv_len); | |
2164 | ||
2165 | return 0; | |
2166 | ||
2167 | out_unmap: | |
2168 | iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]); | |
2169 | return ret; | |
2170 | } | |
2171 | #else /* CONFIG_INET */ | |
2172 | static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, | |
2173 | struct iwl_txq *txq, u8 hdr_len, | |
2174 | struct iwl_cmd_meta *out_meta, | |
2175 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
2176 | { | |
2177 | /* No A-MSDU without CONFIG_INET */ | |
2178 | WARN_ON(1); | |
2179 | ||
2180 | return -1; | |
2181 | } | |
2182 | #endif /* CONFIG_INET */ | |
2183 | ||
f02831be EG |
2184 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
2185 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 2186 | { |
8ad71bef | 2187 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
206eea78 | 2188 | struct ieee80211_hdr *hdr; |
f02831be EG |
2189 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; |
2190 | struct iwl_cmd_meta *out_meta; | |
2191 | struct iwl_txq *txq; | |
2192 | struct iwl_queue *q; | |
38c0f334 JB |
2193 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
2194 | void *tb1_addr; | |
3a0b2a42 | 2195 | u16 len, tb1_len; |
ea68f460 | 2196 | bool wait_write_ptr; |
206eea78 JB |
2197 | __le16 fc; |
2198 | u8 hdr_len; | |
68972c46 | 2199 | u16 wifi_seq; |
f02831be EG |
2200 | |
2201 | txq = &trans_pcie->txq[txq_id]; | |
2202 | q = &txq->q; | |
a0eaad71 | 2203 | |
961de6a5 JB |
2204 | if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), |
2205 | "TX on unused queue %d\n", txq_id)) | |
f02831be | 2206 | return -EINVAL; |
39644e9a | 2207 | |
41837ca9 EG |
2208 | if (unlikely(trans_pcie->sw_csum_tx && |
2209 | skb->ip_summed == CHECKSUM_PARTIAL)) { | |
2210 | int offs = skb_checksum_start_offset(skb); | |
2211 | int csum_offs = offs + skb->csum_offset; | |
2212 | __wsum csum; | |
2213 | ||
2214 | if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) | |
2215 | return -1; | |
2216 | ||
2217 | csum = skb_checksum(skb, offs, skb->len - offs, 0); | |
2218 | *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); | |
3955525d EG |
2219 | |
2220 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
41837ca9 EG |
2221 | } |
2222 | ||
206eea78 JB |
2223 | if (skb_is_nonlinear(skb) && |
2224 | skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS && | |
2225 | __skb_linearize(skb)) | |
2226 | return -ENOMEM; | |
2227 | ||
2228 | /* mac80211 always puts the full header into the SKB's head, | |
2229 | * so there's no need to check if it's readable there | |
2230 | */ | |
2231 | hdr = (struct ieee80211_hdr *)skb->data; | |
2232 | fc = hdr->frame_control; | |
2233 | hdr_len = ieee80211_hdrlen(fc); | |
2234 | ||
f02831be | 2235 | spin_lock(&txq->lock); |
015c15e1 | 2236 | |
3955525d EG |
2237 | if (iwl_queue_space(q) < q->high_mark) { |
2238 | iwl_stop_queue(trans, txq); | |
2239 | ||
2240 | /* don't put the packet on the ring, if there is no room */ | |
2241 | if (unlikely(iwl_queue_space(q) < 3)) { | |
2242 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
2243 | ||
2244 | info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA + 1] = | |
2245 | dev_cmd; | |
2246 | __skb_queue_tail(&txq->overflow_q, skb); | |
2247 | ||
2248 | spin_unlock(&txq->lock); | |
2249 | return 0; | |
2250 | } | |
2251 | } | |
2252 | ||
f02831be EG |
2253 | /* In AGG mode, the index in the ring must correspond to the WiFi |
2254 | * sequence number. This is a HW requirements to help the SCD to parse | |
2255 | * the BA. | |
2256 | * Check here that the packets are in the right place on the ring. | |
2257 | */ | |
9a886586 | 2258 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
1092b9bc | 2259 | WARN_ONCE(txq->ampdu && |
68972c46 | 2260 | (wifi_seq & 0xff) != q->write_ptr, |
f02831be EG |
2261 | "Q: %d WiFi Seq %d tfdNum %d", |
2262 | txq_id, wifi_seq, q->write_ptr); | |
f02831be EG |
2263 | |
2264 | /* Set up driver data for this TFD */ | |
2265 | txq->entries[q->write_ptr].skb = skb; | |
2266 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
2267 | ||
f02831be EG |
2268 | dev_cmd->hdr.sequence = |
2269 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
2270 | INDEX_TO_SEQ(q->write_ptr))); | |
2271 | ||
38c0f334 JB |
2272 | tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); |
2273 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + | |
2274 | offsetof(struct iwl_tx_cmd, scratch); | |
2275 | ||
2276 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
2277 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
2278 | ||
f02831be EG |
2279 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
2280 | out_meta = &txq->entries[q->write_ptr].meta; | |
206eea78 | 2281 | out_meta->flags = 0; |
a0eaad71 | 2282 | |
f02831be | 2283 | /* |
38c0f334 JB |
2284 | * The second TB (tb1) points to the remainder of the TX command |
2285 | * and the 802.11 header - dword aligned size | |
2286 | * (This calculation modifies the TX command, so do it before the | |
2287 | * setup of the first TB) | |
f02831be | 2288 | */ |
38c0f334 JB |
2289 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
2290 | hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; | |
1092b9bc | 2291 | tb1_len = ALIGN(len, 4); |
f02831be EG |
2292 | |
2293 | /* Tell NIC about any 2-byte padding after MAC header */ | |
38c0f334 | 2294 | if (tb1_len != len) |
f02831be EG |
2295 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
2296 | ||
38c0f334 JB |
2297 | /* The first TB points to the scratchbuf data - min_copy bytes */ |
2298 | memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, | |
2299 | IWL_HCMD_SCRATCHBUF_SIZE); | |
2300 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, | |
6d6e68f8 | 2301 | IWL_HCMD_SCRATCHBUF_SIZE, true); |
f02831be | 2302 | |
38c0f334 JB |
2303 | /* there must be data left over for TB1 or this code must be changed */ |
2304 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); | |
2305 | ||
2306 | /* map the data for TB1 */ | |
2307 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; | |
2308 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); | |
2309 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
2310 | goto out_err; | |
6d6e68f8 | 2311 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); |
a0eaad71 | 2312 | |
6eb5e529 EG |
2313 | if (ieee80211_is_data_qos(fc) && |
2314 | (*ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_A_MSDU_PRESENT)) { | |
2315 | if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, | |
2316 | out_meta, dev_cmd, | |
2317 | tb1_len))) | |
2318 | goto out_err; | |
2319 | } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, | |
2320 | out_meta, dev_cmd, tb1_len))) { | |
3a0b2a42 | 2321 | goto out_err; |
6eb5e529 | 2322 | } |
206eea78 | 2323 | |
f02831be EG |
2324 | /* Set up entry for this TFD in Tx byte-count array */ |
2325 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 2326 | |
ea68f460 | 2327 | wait_write_ptr = ieee80211_has_morefrags(fc); |
7c5ba4a8 | 2328 | |
f02831be | 2329 | /* start timer if queue currently empty */ |
7616f334 | 2330 | if (q->read_ptr == q->write_ptr) { |
aecdc63d EG |
2331 | if (txq->wd_timeout) { |
2332 | /* | |
2333 | * If the TXQ is active, then set the timer, if not, | |
2334 | * set the timer in remainder so that the timer will | |
2335 | * be armed with the right value when the station will | |
2336 | * wake up. | |
2337 | */ | |
2338 | if (!txq->frozen) | |
2339 | mod_timer(&txq->stuck_timer, | |
2340 | jiffies + txq->wd_timeout); | |
2341 | else | |
2342 | txq->frozen_expiry_remainder = txq->wd_timeout; | |
2343 | } | |
7616f334 EP |
2344 | IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id); |
2345 | iwl_trans_pcie_ref(trans); | |
2346 | } | |
f02831be EG |
2347 | |
2348 | /* Tell device the write index *just past* this latest filled TFD */ | |
83f32a4b | 2349 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); |
ea68f460 JB |
2350 | if (!wait_write_ptr) |
2351 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
f02831be EG |
2352 | |
2353 | /* | |
2354 | * At this point the frame is "transmitted" successfully | |
43aa616f | 2355 | * and we will get a TX status notification eventually. |
f02831be | 2356 | */ |
f02831be EG |
2357 | spin_unlock(&txq->lock); |
2358 | return 0; | |
2359 | out_err: | |
2360 | spin_unlock(&txq->lock); | |
2361 | return -1; | |
a0eaad71 | 2362 | } |