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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
4cbb8e50 LC |
4 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
5 | * Copyright(c) 2016 Intel Deutschland GmbH | |
1053d35f RR |
6 | * |
7 | * Portions of this file are derived from the ipw3945 project, as well | |
8 | * as portions of the ieee80211 subsystem header files. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., | |
21 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
22 | * | |
23 | * The full GNU General Public License is included in this distribution in the | |
24 | * file called LICENSE. | |
25 | * | |
26 | * Contact Information: | |
cb2f8277 | 27 | * Intel Linux Wireless <linuxwifi@intel.com> |
1053d35f RR |
28 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
29 | * | |
30 | *****************************************************************************/ | |
fd4abac5 | 31 | #include <linux/etherdevice.h> |
6eb5e529 | 32 | #include <linux/ieee80211.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
253a634c | 34 | #include <linux/sched.h> |
71b1230c | 35 | #include <linux/pm_runtime.h> |
6eb5e529 EG |
36 | #include <net/ip6_checksum.h> |
37 | #include <net/tso.h> | |
253a634c | 38 | |
522376d2 EG |
39 | #include "iwl-debug.h" |
40 | #include "iwl-csr.h" | |
41 | #include "iwl-prph.h" | |
1053d35f | 42 | #include "iwl-io.h" |
680073b7 | 43 | #include "iwl-scd.h" |
ed277c93 | 44 | #include "iwl-op-mode.h" |
6468a01a | 45 | #include "internal.h" |
6238b008 | 46 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 47 | #include "dvm/commands.h" |
1053d35f | 48 | |
522376d2 EG |
49 | #define IWL_TX_CRC_SIZE 4 |
50 | #define IWL_TX_DELIMITER_SIZE 4 | |
51 | ||
f02831be EG |
52 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
53 | * DMA services | |
54 | * | |
55 | * Theory of operation | |
56 | * | |
57 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
58 | * of buffer descriptors, each of which points to one or more data buffers for | |
59 | * the device to read from or fill. Driver and device exchange status of each | |
60 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
61 | * entries in each circular buffer, to protect against confusing empty and full | |
62 | * queue states. | |
63 | * | |
64 | * The device reads or writes the data in the queues via the device's several | |
65 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
66 | * | |
67 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
68 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
69 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
70 | * Tx queue resumed. | |
71 | * | |
72 | ***************************************************/ | |
e22744af | 73 | |
f02831be EG |
74 | static int iwl_queue_space(const struct iwl_queue *q) |
75 | { | |
a9b29246 IY |
76 | unsigned int max; |
77 | unsigned int used; | |
f02831be | 78 | |
a9b29246 IY |
79 | /* |
80 | * To avoid ambiguity between empty and completely full queues, there | |
83f32a4b JB |
81 | * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. |
82 | * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need | |
83 | * to reserve any queue entries for this purpose. | |
a9b29246 | 84 | */ |
83f32a4b | 85 | if (q->n_window < TFD_QUEUE_SIZE_MAX) |
a9b29246 IY |
86 | max = q->n_window; |
87 | else | |
83f32a4b | 88 | max = TFD_QUEUE_SIZE_MAX - 1; |
f02831be | 89 | |
a9b29246 | 90 | /* |
83f32a4b JB |
91 | * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to |
92 | * modulo by TFD_QUEUE_SIZE_MAX and is well defined. | |
a9b29246 | 93 | */ |
83f32a4b | 94 | used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); |
a9b29246 IY |
95 | |
96 | if (WARN_ON(used > max)) | |
97 | return 0; | |
98 | ||
99 | return max - used; | |
f02831be EG |
100 | } |
101 | ||
102 | /* | |
103 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
104 | */ | |
83f32a4b | 105 | static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id) |
f02831be | 106 | { |
f02831be EG |
107 | q->n_window = slots_num; |
108 | q->id = id; | |
109 | ||
f02831be EG |
110 | /* slots_num must be power-of-two size, otherwise |
111 | * get_cmd_index is broken. */ | |
112 | if (WARN_ON(!is_power_of_2(slots_num))) | |
113 | return -EINVAL; | |
114 | ||
115 | q->low_mark = q->n_window / 4; | |
116 | if (q->low_mark < 4) | |
117 | q->low_mark = 4; | |
118 | ||
119 | q->high_mark = q->n_window / 8; | |
120 | if (q->high_mark < 2) | |
121 | q->high_mark = 2; | |
122 | ||
123 | q->write_ptr = 0; | |
124 | q->read_ptr = 0; | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
f02831be EG |
129 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
130 | struct iwl_dma_ptr *ptr, size_t size) | |
131 | { | |
132 | if (WARN_ON(ptr->addr)) | |
133 | return -EINVAL; | |
134 | ||
135 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
136 | &ptr->dma, GFP_KERNEL); | |
137 | if (!ptr->addr) | |
138 | return -ENOMEM; | |
139 | ptr->size = size; | |
140 | return 0; | |
141 | } | |
142 | ||
143 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
144 | struct iwl_dma_ptr *ptr) | |
145 | { | |
146 | if (unlikely(!ptr->addr)) | |
147 | return; | |
148 | ||
149 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
150 | memset(ptr, 0, sizeof(*ptr)); | |
151 | } | |
152 | ||
153 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
154 | { | |
155 | struct iwl_txq *txq = (void *)data; | |
f02831be EG |
156 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; |
157 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
158 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
159 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
160 | u8 buf[16]; | |
161 | int i; | |
162 | ||
163 | spin_lock(&txq->lock); | |
164 | /* check if triggered erroneously */ | |
165 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
166 | spin_unlock(&txq->lock); | |
167 | return; | |
168 | } | |
169 | spin_unlock(&txq->lock); | |
170 | ||
171 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
4cf677fd | 172 | jiffies_to_msecs(txq->wd_timeout)); |
f02831be EG |
173 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
174 | txq->q.read_ptr, txq->q.write_ptr); | |
175 | ||
4fd442db | 176 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
177 | |
178 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
179 | ||
180 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
181 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
182 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
183 | ||
184 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
185 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
186 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
187 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
188 | u32 tbl_dw = | |
4fd442db EG |
189 | iwl_trans_read_mem32(trans, |
190 | trans_pcie->scd_base_addr + | |
191 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
192 | |
193 | if (i & 0x1) | |
194 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
195 | else | |
196 | tbl_dw = tbl_dw & 0x0000FFFF; | |
197 | ||
198 | IWL_ERR(trans, | |
199 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
200 | i, active ? "" : "in", fifo, tbl_dw, | |
83f32a4b JB |
201 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) & |
202 | (TFD_QUEUE_SIZE_MAX - 1), | |
f02831be EG |
203 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); |
204 | } | |
205 | ||
4c9706dc | 206 | iwl_force_nmi(trans); |
f02831be EG |
207 | } |
208 | ||
990aa6d7 EG |
209 | /* |
210 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 211 | */ |
f02831be EG |
212 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
213 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 214 | { |
105183b1 | 215 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 216 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
217 | int write_ptr = txq->q.write_ptr; |
218 | int txq_id = txq->q.id; | |
219 | u8 sec_ctl = 0; | |
220 | u8 sta_id = 0; | |
221 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
222 | __le16 bc_ent; | |
132f98c2 | 223 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 224 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 225 | |
105183b1 EG |
226 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
227 | ||
132f98c2 EG |
228 | sta_id = tx_cmd->sta_id; |
229 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
230 | |
231 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
232 | case TX_CMD_SEC_CCM: | |
4325f6ca | 233 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
234 | break; |
235 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 236 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
237 | break; |
238 | case TX_CMD_SEC_WEP: | |
4325f6ca | 239 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
240 | break; |
241 | } | |
242 | ||
046db346 EG |
243 | if (trans_pcie->bc_table_dword) |
244 | len = DIV_ROUND_UP(len, 4); | |
245 | ||
31f920b6 EG |
246 | if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) |
247 | return; | |
248 | ||
046db346 | 249 | bc_ent = cpu_to_le16(len | (sta_id << 12)); |
48d42c42 EG |
250 | |
251 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
252 | ||
253 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
254 | scd_bc_tbl[txq_id]. | |
255 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
256 | } | |
257 | ||
f02831be EG |
258 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
259 | struct iwl_txq *txq) | |
260 | { | |
261 | struct iwl_trans_pcie *trans_pcie = | |
262 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
263 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
264 | int txq_id = txq->q.id; | |
265 | int read_ptr = txq->q.read_ptr; | |
266 | u8 sta_id = 0; | |
267 | __le16 bc_ent; | |
268 | struct iwl_tx_cmd *tx_cmd = | |
269 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
270 | ||
271 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
272 | ||
273 | if (txq_id != trans_pcie->cmd_queue) | |
274 | sta_id = tx_cmd->sta_id; | |
275 | ||
276 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
277 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
278 | ||
279 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
280 | scd_bc_tbl[txq_id]. | |
281 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
282 | } | |
283 | ||
990aa6d7 EG |
284 | /* |
285 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 286 | */ |
ea68f460 JB |
287 | static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, |
288 | struct iwl_txq *txq) | |
fd4abac5 | 289 | { |
23e76d1a | 290 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
fd4abac5 | 291 | u32 reg = 0; |
fd4abac5 TW |
292 | int txq_id = txq->q.id; |
293 | ||
ea68f460 | 294 | lockdep_assert_held(&txq->lock); |
fd4abac5 | 295 | |
5045388c EP |
296 | /* |
297 | * explicitly wake up the NIC if: | |
298 | * 1. shadow registers aren't enabled | |
299 | * 2. NIC is woken up for CMD regardless of shadow outside this function | |
300 | * 3. there is a chance that the NIC is asleep | |
301 | */ | |
302 | if (!trans->cfg->base_params->shadow_reg_enable && | |
303 | txq_id != trans_pcie->cmd_queue && | |
304 | test_bit(STATUS_TPOWER_PMI, &trans->status)) { | |
f81c1f48 | 305 | /* |
5045388c EP |
306 | * wake up nic if it's powered down ... |
307 | * uCode will wake up, and interrupt us again, so next | |
308 | * time we'll skip this part. | |
f81c1f48 | 309 | */ |
5045388c EP |
310 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
311 | ||
312 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
313 | IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", | |
314 | txq_id, reg); | |
315 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
316 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ea68f460 | 317 | txq->need_update = true; |
5045388c EP |
318 | return; |
319 | } | |
f81c1f48 | 320 | } |
5045388c EP |
321 | |
322 | /* | |
323 | * if not in power-save mode, uCode will never sleep when we're | |
324 | * trying to tx (during RFKILL, we're not trying to tx). | |
325 | */ | |
326 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); | |
0cd58eaa EG |
327 | if (!txq->block) |
328 | iwl_write32(trans, HBUS_TARG_WRPTR, | |
329 | txq->q.write_ptr | (txq_id << 8)); | |
ea68f460 | 330 | } |
5045388c | 331 | |
ea68f460 JB |
332 | void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) |
333 | { | |
334 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
335 | int i; | |
336 | ||
337 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
338 | struct iwl_txq *txq = &trans_pcie->txq[i]; | |
339 | ||
d090f878 | 340 | spin_lock_bh(&txq->lock); |
ea68f460 JB |
341 | if (trans_pcie->txq[i].need_update) { |
342 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
343 | trans_pcie->txq[i].need_update = false; | |
344 | } | |
d090f878 | 345 | spin_unlock_bh(&txq->lock); |
ea68f460 | 346 | } |
fd4abac5 | 347 | } |
fd4abac5 | 348 | |
f02831be | 349 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
350 | { |
351 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
352 | ||
353 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
354 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
355 | addr |= | |
356 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
357 | ||
358 | return addr; | |
359 | } | |
360 | ||
f02831be EG |
361 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
362 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
363 | { |
364 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
365 | u16 hi_n_len = len << 4; | |
366 | ||
367 | put_unaligned_le32(addr, &tb->lo); | |
368 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
369 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
370 | ||
371 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
372 | ||
373 | tfd->num_tbs = idx + 1; | |
374 | } | |
375 | ||
f02831be | 376 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
377 | { |
378 | return tfd->num_tbs & 0x1f; | |
379 | } | |
380 | ||
f02831be | 381 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 JB |
382 | struct iwl_cmd_meta *meta, |
383 | struct iwl_tfd *tfd) | |
214d14d4 | 384 | { |
214d14d4 JB |
385 | int i; |
386 | int num_tbs; | |
387 | ||
214d14d4 | 388 | /* Sanity check on number of chunks */ |
f02831be | 389 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
390 | |
391 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 392 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
393 | /* @todo issue fatal error, it is quite serious situation */ |
394 | return; | |
395 | } | |
396 | ||
8de437c7 | 397 | /* first TB is never freed - it's the bidirectional DMA data */ |
214d14d4 | 398 | |
206eea78 JB |
399 | for (i = 1; i < num_tbs; i++) { |
400 | if (meta->flags & BIT(i + CMD_TB_BITMAP_POS)) | |
401 | dma_unmap_page(trans->dev, | |
402 | iwl_pcie_tfd_tb_get_addr(tfd, i), | |
403 | iwl_pcie_tfd_tb_get_len(tfd, i), | |
404 | DMA_TO_DEVICE); | |
405 | else | |
406 | dma_unmap_single(trans->dev, | |
407 | iwl_pcie_tfd_tb_get_addr(tfd, i), | |
408 | iwl_pcie_tfd_tb_get_len(tfd, i), | |
409 | DMA_TO_DEVICE); | |
410 | } | |
ebed633c | 411 | tfd->num_tbs = 0; |
4ce7cc2b JB |
412 | } |
413 | ||
990aa6d7 EG |
414 | /* |
415 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 416 | * @trans - transport private data |
4ce7cc2b | 417 | * @txq - tx queue |
ebed633c | 418 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
419 | * |
420 | * Does NOT advance any TFD circular buffer read/write indexes | |
421 | * Does NOT free the TFD itself (which is within circular buffer) | |
422 | */ | |
98891754 | 423 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b JB |
424 | { |
425 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 426 | |
83f32a4b JB |
427 | /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and |
428 | * idx is bounded by n_window | |
429 | */ | |
ebed633c EG |
430 | int rd_ptr = txq->q.read_ptr; |
431 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
432 | ||
015c15e1 JB |
433 | lockdep_assert_held(&txq->lock); |
434 | ||
83f32a4b JB |
435 | /* We have only q->n_window txq->entries, but we use |
436 | * TFD_QUEUE_SIZE_MAX tfds | |
437 | */ | |
98891754 | 438 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); |
214d14d4 JB |
439 | |
440 | /* free SKB */ | |
bf8440e6 | 441 | if (txq->entries) { |
214d14d4 JB |
442 | struct sk_buff *skb; |
443 | ||
ebed633c | 444 | skb = txq->entries[idx].skb; |
214d14d4 | 445 | |
909e9b23 EG |
446 | /* Can be called from irqs-disabled context |
447 | * If skb is not NULL, it means that the whole queue is being | |
448 | * freed and that the queue is not empty - free the skb | |
449 | */ | |
214d14d4 | 450 | if (skb) { |
ed277c93 | 451 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 452 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
453 | } |
454 | } | |
455 | } | |
456 | ||
f02831be | 457 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
6d6e68f8 | 458 | dma_addr_t addr, u16 len, bool reset) |
214d14d4 JB |
459 | { |
460 | struct iwl_queue *q; | |
461 | struct iwl_tfd *tfd, *tfd_tmp; | |
462 | u32 num_tbs; | |
463 | ||
464 | q = &txq->q; | |
4ce7cc2b | 465 | tfd_tmp = txq->tfds; |
214d14d4 JB |
466 | tfd = &tfd_tmp[q->write_ptr]; |
467 | ||
f02831be EG |
468 | if (reset) |
469 | memset(tfd, 0, sizeof(*tfd)); | |
470 | ||
471 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
472 | ||
473 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
474 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
475 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
476 | IWL_NUM_OF_TBS); | |
477 | return -EINVAL; | |
478 | } | |
479 | ||
1092b9bc EP |
480 | if (WARN(addr & ~IWL_TX_DMA_MASK, |
481 | "Unaligned address = %llx\n", (unsigned long long)addr)) | |
f02831be EG |
482 | return -EINVAL; |
483 | ||
f02831be EG |
484 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); |
485 | ||
206eea78 | 486 | return num_tbs; |
f02831be EG |
487 | } |
488 | ||
489 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
490 | struct iwl_txq *txq, int slots_num, | |
491 | u32 txq_id) | |
492 | { | |
493 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
494 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
8de437c7 | 495 | size_t tb0_buf_sz; |
f02831be EG |
496 | int i; |
497 | ||
498 | if (WARN_ON(txq->entries || txq->tfds)) | |
499 | return -EINVAL; | |
500 | ||
501 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
502 | (unsigned long)txq); | |
503 | txq->trans_pcie = trans_pcie; | |
504 | ||
505 | txq->q.n_window = slots_num; | |
506 | ||
507 | txq->entries = kcalloc(slots_num, | |
508 | sizeof(struct iwl_pcie_txq_entry), | |
509 | GFP_KERNEL); | |
510 | ||
511 | if (!txq->entries) | |
512 | goto error; | |
513 | ||
514 | if (txq_id == trans_pcie->cmd_queue) | |
515 | for (i = 0; i < slots_num; i++) { | |
516 | txq->entries[i].cmd = | |
517 | kmalloc(sizeof(struct iwl_device_cmd), | |
518 | GFP_KERNEL); | |
519 | if (!txq->entries[i].cmd) | |
520 | goto error; | |
521 | } | |
522 | ||
523 | /* Circular buffer of transmit frame descriptors (TFDs), | |
524 | * shared with device */ | |
525 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
526 | &txq->q.dma_addr, GFP_KERNEL); | |
d0320f75 | 527 | if (!txq->tfds) |
f02831be | 528 | goto error; |
38c0f334 | 529 | |
8de437c7 | 530 | BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); |
38c0f334 | 531 | |
8de437c7 | 532 | tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; |
38c0f334 | 533 | |
8de437c7 SS |
534 | txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, |
535 | &txq->first_tb_dma, | |
38c0f334 | 536 | GFP_KERNEL); |
8de437c7 | 537 | if (!txq->first_tb_bufs) |
38c0f334 JB |
538 | goto err_free_tfds; |
539 | ||
f02831be EG |
540 | txq->q.id = txq_id; |
541 | ||
542 | return 0; | |
38c0f334 JB |
543 | err_free_tfds: |
544 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); | |
f02831be EG |
545 | error: |
546 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
547 | for (i = 0; i < slots_num; i++) | |
548 | kfree(txq->entries[i].cmd); | |
549 | kfree(txq->entries); | |
550 | txq->entries = NULL; | |
551 | ||
552 | return -ENOMEM; | |
553 | ||
554 | } | |
555 | ||
556 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
557 | int slots_num, u32 txq_id) | |
558 | { | |
559 | int ret; | |
560 | ||
43aa616f | 561 | txq->need_update = false; |
f02831be EG |
562 | |
563 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
564 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
565 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
566 | ||
567 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
83f32a4b | 568 | ret = iwl_queue_init(&txq->q, slots_num, txq_id); |
f02831be EG |
569 | if (ret) |
570 | return ret; | |
571 | ||
572 | spin_lock_init(&txq->lock); | |
3955525d | 573 | __skb_queue_head_init(&txq->overflow_q); |
f02831be EG |
574 | |
575 | /* | |
576 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
577 | * given Tx queue, and enable the DMA channel used for that queue. | |
578 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
e22744af SS |
579 | if (trans->cfg->use_tfh) |
580 | iwl_write_direct64(trans, | |
581 | FH_MEM_CBBC_QUEUE(trans, txq_id), | |
582 | txq->q.dma_addr); | |
583 | else | |
584 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), | |
585 | txq->q.dma_addr >> 8); | |
f02831be EG |
586 | |
587 | return 0; | |
588 | } | |
589 | ||
21cb3222 JB |
590 | static void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, |
591 | struct sk_buff *skb) | |
6eb5e529 | 592 | { |
21cb3222 | 593 | struct page **page_ptr; |
6eb5e529 | 594 | |
21cb3222 | 595 | page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); |
6eb5e529 | 596 | |
21cb3222 JB |
597 | if (*page_ptr) { |
598 | __free_page(*page_ptr); | |
599 | *page_ptr = NULL; | |
6eb5e529 EG |
600 | } |
601 | } | |
602 | ||
01d11cd1 SS |
603 | static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) |
604 | { | |
605 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
606 | ||
607 | lockdep_assert_held(&trans_pcie->reg_lock); | |
608 | ||
609 | if (trans_pcie->ref_cmd_in_flight) { | |
610 | trans_pcie->ref_cmd_in_flight = false; | |
611 | IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); | |
c24c7f58 | 612 | iwl_trans_unref(trans); |
01d11cd1 SS |
613 | } |
614 | ||
615 | if (!trans->cfg->base_params->apmg_wake_up_wa) | |
616 | return; | |
617 | if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) | |
618 | return; | |
619 | ||
620 | trans_pcie->cmd_hold_nic_awake = false; | |
621 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
622 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
623 | } | |
624 | ||
f02831be EG |
625 | /* |
626 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
627 | */ | |
628 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
629 | { | |
630 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
631 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
632 | struct iwl_queue *q = &txq->q; | |
f02831be | 633 | |
f02831be EG |
634 | spin_lock_bh(&txq->lock); |
635 | while (q->write_ptr != q->read_ptr) { | |
b967613d EG |
636 | IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", |
637 | txq_id, q->read_ptr); | |
6eb5e529 EG |
638 | |
639 | if (txq_id != trans_pcie->cmd_queue) { | |
640 | struct sk_buff *skb = txq->entries[q->read_ptr].skb; | |
641 | ||
642 | if (WARN_ON_ONCE(!skb)) | |
643 | continue; | |
644 | ||
21cb3222 | 645 | iwl_pcie_free_tso_page(trans_pcie, skb); |
6eb5e529 | 646 | } |
98891754 | 647 | iwl_pcie_txq_free_tfd(trans, txq); |
83f32a4b | 648 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr); |
01d11cd1 SS |
649 | |
650 | if (q->read_ptr == q->write_ptr) { | |
651 | unsigned long flags; | |
652 | ||
653 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); | |
654 | if (txq_id != trans_pcie->cmd_queue) { | |
655 | IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", | |
656 | q->id); | |
c24c7f58 | 657 | iwl_trans_unref(trans); |
01d11cd1 SS |
658 | } else { |
659 | iwl_pcie_clear_cmd_in_flight(trans); | |
660 | } | |
661 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
662 | } | |
f02831be | 663 | } |
b967613d | 664 | txq->active = false; |
3955525d EG |
665 | |
666 | while (!skb_queue_empty(&txq->overflow_q)) { | |
667 | struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); | |
668 | ||
669 | iwl_op_mode_free_skb(trans->op_mode, skb); | |
670 | } | |
671 | ||
f02831be | 672 | spin_unlock_bh(&txq->lock); |
8a487b1a EG |
673 | |
674 | /* just in case - this queue may have been stopped */ | |
675 | iwl_wake_queue(trans, txq); | |
f02831be EG |
676 | } |
677 | ||
678 | /* | |
679 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
680 | * @txq: Transmit queue to deallocate. | |
681 | * | |
682 | * Empty queue by removing and destroying all BD's. | |
683 | * Free all buffers. | |
684 | * 0-fill, but do not free "txq" descriptor structure. | |
685 | */ | |
686 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
687 | { | |
688 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
689 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
690 | struct device *dev = trans->dev; | |
691 | int i; | |
692 | ||
693 | if (WARN_ON(!txq)) | |
694 | return; | |
695 | ||
696 | iwl_pcie_txq_unmap(trans, txq_id); | |
697 | ||
698 | /* De-alloc array of command/tx buffers */ | |
699 | if (txq_id == trans_pcie->cmd_queue) | |
700 | for (i = 0; i < txq->q.n_window; i++) { | |
5d4185ae JB |
701 | kzfree(txq->entries[i].cmd); |
702 | kzfree(txq->entries[i].free_buf); | |
f02831be EG |
703 | } |
704 | ||
705 | /* De-alloc circular buffer of TFDs */ | |
83f32a4b JB |
706 | if (txq->tfds) { |
707 | dma_free_coherent(dev, | |
708 | sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX, | |
709 | txq->tfds, txq->q.dma_addr); | |
d21fa2da | 710 | txq->q.dma_addr = 0; |
83f32a4b | 711 | txq->tfds = NULL; |
38c0f334 JB |
712 | |
713 | dma_free_coherent(dev, | |
8de437c7 SS |
714 | sizeof(*txq->first_tb_bufs) * txq->q.n_window, |
715 | txq->first_tb_bufs, txq->first_tb_dma); | |
f02831be EG |
716 | } |
717 | ||
718 | kfree(txq->entries); | |
719 | txq->entries = NULL; | |
720 | ||
721 | del_timer_sync(&txq->stuck_timer); | |
722 | ||
723 | /* 0-fill queue descriptor structure */ | |
724 | memset(txq, 0, sizeof(*txq)); | |
725 | } | |
726 | ||
f02831be EG |
727 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) |
728 | { | |
729 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 730 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
731 | int chan; |
732 | u32 reg_val; | |
22dc3c95 JB |
733 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
734 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
735 | |
736 | /* make sure all queue are not stopped/used */ | |
737 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
738 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
739 | ||
740 | trans_pcie->scd_base_addr = | |
741 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
742 | ||
743 | WARN_ON(scd_base_addr != 0 && | |
744 | scd_base_addr != trans_pcie->scd_base_addr); | |
745 | ||
22dc3c95 JB |
746 | /* reset context data, TX status and translation data */ |
747 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
748 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
749 | NULL, clear_dwords); | |
f02831be EG |
750 | |
751 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
752 | trans_pcie->scd_bc_tbls.dma >> 10); | |
753 | ||
754 | /* The chain extension of the SCD doesn't work well. This feature is | |
755 | * enabled by default by the HW, so we need to disable it manually. | |
756 | */ | |
e03bbb62 EG |
757 | if (trans->cfg->base_params->scd_chain_ext_wa) |
758 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
f02831be EG |
759 | |
760 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
4cf677fd EG |
761 | trans_pcie->cmd_fifo, |
762 | trans_pcie->cmd_q_wdg_timeout); | |
f02831be EG |
763 | |
764 | /* Activate all Tx DMA/FIFO channels */ | |
680073b7 | 765 | iwl_scd_activate_fifos(trans); |
f02831be EG |
766 | |
767 | /* Enable DMA channel */ | |
768 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
769 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
770 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
771 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
772 | ||
773 | /* Update FH chicken bits */ | |
774 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
775 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
776 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
777 | ||
778 | /* Enable L1-Active */ | |
3073d8c0 EH |
779 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
780 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
781 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
f02831be EG |
782 | } |
783 | ||
ddaf5a5b JB |
784 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
785 | { | |
786 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
787 | int txq_id; | |
788 | ||
789 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
790 | txq_id++) { | |
791 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
e22744af SS |
792 | if (trans->cfg->use_tfh) |
793 | iwl_write_direct64(trans, | |
794 | FH_MEM_CBBC_QUEUE(trans, txq_id), | |
795 | txq->q.dma_addr); | |
796 | else | |
797 | iwl_write_direct32(trans, | |
798 | FH_MEM_CBBC_QUEUE(trans, txq_id), | |
799 | txq->q.dma_addr >> 8); | |
ddaf5a5b JB |
800 | iwl_pcie_txq_unmap(trans, txq_id); |
801 | txq->q.read_ptr = 0; | |
802 | txq->q.write_ptr = 0; | |
803 | } | |
804 | ||
805 | /* Tell NIC where to find the "keep warm" buffer */ | |
806 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
807 | trans_pcie->kw.dma >> 4); | |
808 | ||
cd8f4384 EG |
809 | /* |
810 | * Send 0 as the scd_base_addr since the device may have be reset | |
811 | * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will | |
812 | * contain garbage. | |
813 | */ | |
814 | iwl_pcie_tx_start(trans, 0); | |
ddaf5a5b JB |
815 | } |
816 | ||
36277234 EG |
817 | static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) |
818 | { | |
819 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
820 | unsigned long flags; | |
821 | int ch, ret; | |
822 | u32 mask = 0; | |
823 | ||
824 | spin_lock(&trans_pcie->irq_lock); | |
825 | ||
23ba9340 | 826 | if (!iwl_trans_grab_nic_access(trans, &flags)) |
36277234 EG |
827 | goto out; |
828 | ||
829 | /* Stop each Tx DMA channel */ | |
830 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
831 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
832 | mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); | |
833 | } | |
834 | ||
835 | /* Wait for DMA channels to be idle */ | |
836 | ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); | |
837 | if (ret < 0) | |
838 | IWL_ERR(trans, | |
839 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
840 | ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); | |
841 | ||
842 | iwl_trans_release_nic_access(trans, &flags); | |
843 | ||
844 | out: | |
845 | spin_unlock(&trans_pcie->irq_lock); | |
846 | } | |
847 | ||
f02831be EG |
848 | /* |
849 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
850 | */ | |
851 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
852 | { | |
853 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
36277234 | 854 | int txq_id; |
f02831be EG |
855 | |
856 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 857 | iwl_scd_deactivate_fifos(trans); |
f02831be | 858 | |
36277234 EG |
859 | /* Turn off all Tx DMA channels */ |
860 | iwl_pcie_tx_stop_fh(trans); | |
f02831be | 861 | |
fba1c627 EG |
862 | /* |
863 | * This function can be called before the op_mode disabled the | |
864 | * queues. This happens when we have an rfkill interrupt. | |
865 | * Since we stop Tx altogether - mark the queues as stopped. | |
866 | */ | |
867 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
868 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
869 | ||
870 | /* This can happen: start_hw, stop_device */ | |
871 | if (!trans_pcie->txq) | |
f02831be | 872 | return 0; |
f02831be EG |
873 | |
874 | /* Unmap DMA from host system and free skb's */ | |
875 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
876 | txq_id++) | |
877 | iwl_pcie_txq_unmap(trans, txq_id); | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
882 | /* | |
883 | * iwl_trans_tx_free - Free TXQ Context | |
884 | * | |
885 | * Destroy all TX DMA queues and structures | |
886 | */ | |
887 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
888 | { | |
889 | int txq_id; | |
890 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
891 | ||
892 | /* Tx queues */ | |
893 | if (trans_pcie->txq) { | |
894 | for (txq_id = 0; | |
895 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
896 | iwl_pcie_txq_free(trans, txq_id); | |
897 | } | |
898 | ||
899 | kfree(trans_pcie->txq); | |
900 | trans_pcie->txq = NULL; | |
901 | ||
902 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
903 | ||
904 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
905 | } | |
906 | ||
907 | /* | |
908 | * iwl_pcie_tx_alloc - allocate TX context | |
909 | * Allocate all Tx DMA structures and initialize them | |
910 | */ | |
911 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
912 | { | |
913 | int ret; | |
914 | int txq_id, slots_num; | |
915 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
916 | ||
917 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
918 | sizeof(struct iwlagn_scd_bc_tbl); | |
919 | ||
920 | /*It is not allowed to alloc twice, so warn when this happens. | |
921 | * We cannot rely on the previous allocation, so free and fail */ | |
922 | if (WARN_ON(trans_pcie->txq)) { | |
923 | ret = -EINVAL; | |
924 | goto error; | |
925 | } | |
926 | ||
927 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
928 | scd_bc_tbls_size); | |
929 | if (ret) { | |
930 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
931 | goto error; | |
932 | } | |
933 | ||
934 | /* Alloc keep-warm buffer */ | |
935 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
936 | if (ret) { | |
937 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
938 | goto error; | |
939 | } | |
940 | ||
941 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
942 | sizeof(struct iwl_txq), GFP_KERNEL); | |
943 | if (!trans_pcie->txq) { | |
944 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
2ab9ba0f | 945 | ret = -ENOMEM; |
f02831be EG |
946 | goto error; |
947 | } | |
948 | ||
949 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
950 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
951 | txq_id++) { | |
952 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
953 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
954 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
955 | slots_num, txq_id); | |
956 | if (ret) { | |
957 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
958 | goto error; | |
959 | } | |
960 | } | |
961 | ||
962 | return 0; | |
963 | ||
964 | error: | |
965 | iwl_pcie_tx_free(trans); | |
966 | ||
967 | return ret; | |
968 | } | |
969 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
970 | { | |
971 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
972 | int ret; | |
973 | int txq_id, slots_num; | |
f02831be EG |
974 | bool alloc = false; |
975 | ||
976 | if (!trans_pcie->txq) { | |
977 | ret = iwl_pcie_tx_alloc(trans); | |
978 | if (ret) | |
979 | goto error; | |
980 | alloc = true; | |
981 | } | |
982 | ||
7b70bd63 | 983 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
984 | |
985 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 986 | iwl_scd_deactivate_fifos(trans); |
f02831be EG |
987 | |
988 | /* Tell NIC where to find the "keep warm" buffer */ | |
989 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
990 | trans_pcie->kw.dma >> 4); | |
991 | ||
7b70bd63 | 992 | spin_unlock(&trans_pcie->irq_lock); |
f02831be EG |
993 | |
994 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
995 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
996 | txq_id++) { | |
997 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
998 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
999 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
1000 | slots_num, txq_id); | |
1001 | if (ret) { | |
1002 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
1003 | goto error; | |
1004 | } | |
1005 | } | |
1006 | ||
e22744af SS |
1007 | if (trans->cfg->use_tfh) |
1008 | iwl_write_direct32(trans, TFH_TRANSFER_MODE, | |
1009 | TFH_TRANSFER_MAX_PENDING_REQ | | |
1010 | TFH_CHUNK_SIZE_128 | | |
1011 | TFH_CHUNK_SPLIT_MODE); | |
1012 | ||
94ce9e5e | 1013 | iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); |
cb6bb128 EG |
1014 | if (trans->cfg->base_params->num_of_queues > 20) |
1015 | iwl_set_bits_prph(trans, SCD_GP_CTRL, | |
1016 | SCD_GP_CTRL_ENABLE_31_QUEUES); | |
1017 | ||
f02831be EG |
1018 | return 0; |
1019 | error: | |
1020 | /*Upon error, free only if we allocated something */ | |
1021 | if (alloc) | |
1022 | iwl_pcie_tx_free(trans); | |
1023 | return ret; | |
1024 | } | |
1025 | ||
4cf677fd | 1026 | static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) |
f02831be | 1027 | { |
e0b8d405 EG |
1028 | lockdep_assert_held(&txq->lock); |
1029 | ||
4cf677fd | 1030 | if (!txq->wd_timeout) |
f02831be EG |
1031 | return; |
1032 | ||
e0b8d405 EG |
1033 | /* |
1034 | * station is asleep and we send data - that must | |
1035 | * be uAPSD or PS-Poll. Don't rearm the timer. | |
1036 | */ | |
1037 | if (txq->frozen) | |
1038 | return; | |
1039 | ||
f02831be EG |
1040 | /* |
1041 | * if empty delete timer, otherwise move timer forward | |
1042 | * since we're making progress on this queue | |
1043 | */ | |
1044 | if (txq->q.read_ptr == txq->q.write_ptr) | |
1045 | del_timer(&txq->stuck_timer); | |
1046 | else | |
4cf677fd | 1047 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); |
f02831be EG |
1048 | } |
1049 | ||
1050 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
1051 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
1052 | struct sk_buff_head *skbs) | |
f02831be EG |
1053 | { |
1054 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1055 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
83f32a4b | 1056 | int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); |
f02831be EG |
1057 | struct iwl_queue *q = &txq->q; |
1058 | int last_to_free; | |
f02831be EG |
1059 | |
1060 | /* This function is not meant to release cmd queue*/ | |
1061 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 1062 | return; |
214d14d4 | 1063 | |
2bfb5092 | 1064 | spin_lock_bh(&txq->lock); |
f6d497cd | 1065 | |
b967613d EG |
1066 | if (!txq->active) { |
1067 | IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", | |
1068 | txq_id, ssn); | |
1069 | goto out; | |
1070 | } | |
1071 | ||
f6d497cd EG |
1072 | if (txq->q.read_ptr == tfd_num) |
1073 | goto out; | |
1074 | ||
1075 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
1076 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 1077 | |
f02831be EG |
1078 | /*Since we free until index _not_ inclusive, the one before index is |
1079 | * the last we will free. This one must be used */ | |
83f32a4b | 1080 | last_to_free = iwl_queue_dec_wrap(tfd_num); |
f02831be | 1081 | |
6ca6ebc1 | 1082 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
1083 | IWL_ERR(trans, |
1084 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 1085 | __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, |
f02831be | 1086 | q->write_ptr, q->read_ptr); |
f6d497cd | 1087 | goto out; |
214d14d4 JB |
1088 | } |
1089 | ||
f02831be | 1090 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 1091 | goto out; |
214d14d4 | 1092 | |
f02831be | 1093 | for (; |
f6d497cd | 1094 | q->read_ptr != tfd_num; |
83f32a4b | 1095 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { |
6eb5e529 | 1096 | struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb; |
214d14d4 | 1097 | |
6eb5e529 | 1098 | if (WARN_ON_ONCE(!skb)) |
f02831be | 1099 | continue; |
214d14d4 | 1100 | |
21cb3222 | 1101 | iwl_pcie_free_tso_page(trans_pcie, skb); |
6eb5e529 EG |
1102 | |
1103 | __skb_queue_tail(skbs, skb); | |
214d14d4 | 1104 | |
f02831be | 1105 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 1106 | |
f02831be | 1107 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 1108 | |
98891754 | 1109 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 1110 | } |
fd4abac5 | 1111 | |
4cf677fd | 1112 | iwl_pcie_txq_progress(txq); |
f02831be | 1113 | |
3955525d EG |
1114 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && |
1115 | test_bit(txq_id, trans_pcie->queue_stopped)) { | |
685b346c | 1116 | struct sk_buff_head overflow_skbs; |
3955525d | 1117 | |
685b346c EG |
1118 | __skb_queue_head_init(&overflow_skbs); |
1119 | skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); | |
3955525d EG |
1120 | |
1121 | /* | |
1122 | * This is tricky: we are in reclaim path which is non | |
1123 | * re-entrant, so noone will try to take the access the | |
1124 | * txq data from that path. We stopped tx, so we can't | |
1125 | * have tx as well. Bottom line, we can unlock and re-lock | |
1126 | * later. | |
1127 | */ | |
1128 | spin_unlock_bh(&txq->lock); | |
1129 | ||
685b346c EG |
1130 | while (!skb_queue_empty(&overflow_skbs)) { |
1131 | struct sk_buff *skb = __skb_dequeue(&overflow_skbs); | |
21cb3222 JB |
1132 | struct iwl_device_cmd *dev_cmd_ptr; |
1133 | ||
1134 | dev_cmd_ptr = *(void **)((u8 *)skb->cb + | |
1135 | trans_pcie->dev_cmd_offs); | |
3955525d EG |
1136 | |
1137 | /* | |
1138 | * Note that we can very well be overflowing again. | |
1139 | * In that case, iwl_queue_space will be small again | |
1140 | * and we won't wake mac80211's queue. | |
1141 | */ | |
21cb3222 | 1142 | iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id); |
3955525d EG |
1143 | } |
1144 | spin_lock_bh(&txq->lock); | |
1145 | ||
1146 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) | |
1147 | iwl_wake_queue(trans, txq); | |
1148 | } | |
7616f334 EP |
1149 | |
1150 | if (q->read_ptr == q->write_ptr) { | |
1151 | IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id); | |
c24c7f58 | 1152 | iwl_trans_unref(trans); |
7616f334 EP |
1153 | } |
1154 | ||
f6d497cd | 1155 | out: |
2bfb5092 | 1156 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
1157 | } |
1158 | ||
7616f334 EP |
1159 | static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, |
1160 | const struct iwl_host_cmd *cmd) | |
804d4c5a EP |
1161 | { |
1162 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1163 | int ret; | |
1164 | ||
1165 | lockdep_assert_held(&trans_pcie->reg_lock); | |
1166 | ||
7616f334 EP |
1167 | if (!(cmd->flags & CMD_SEND_IN_IDLE) && |
1168 | !trans_pcie->ref_cmd_in_flight) { | |
1169 | trans_pcie->ref_cmd_in_flight = true; | |
1170 | IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); | |
c24c7f58 | 1171 | iwl_trans_ref(trans); |
7616f334 EP |
1172 | } |
1173 | ||
804d4c5a EP |
1174 | /* |
1175 | * wake up the NIC to make sure that the firmware will see the host | |
1176 | * command - we will let the NIC sleep once all the host commands | |
1177 | * returned. This needs to be done only on NICs that have | |
1178 | * apmg_wake_up_wa set. | |
1179 | */ | |
fc8a350d IP |
1180 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1181 | !trans_pcie->cmd_hold_nic_awake) { | |
804d4c5a EP |
1182 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
1183 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1184 | |
1185 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1186 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1187 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1188 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), | |
1189 | 15000); | |
1190 | if (ret < 0) { | |
1191 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
1192 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1193 | IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); |
1194 | return -EIO; | |
1195 | } | |
fc8a350d | 1196 | trans_pcie->cmd_hold_nic_awake = true; |
804d4c5a EP |
1197 | } |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
f02831be EG |
1202 | /* |
1203 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
1204 | * | |
1205 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1206 | * need to be reclaimed. As result, some free space forms. If there is | |
1207 | * enough free space (> low mark), wake the stack that feeds us. | |
1208 | */ | |
1209 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 1210 | { |
f02831be EG |
1211 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1212 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
1213 | struct iwl_queue *q = &txq->q; | |
b9439491 | 1214 | unsigned long flags; |
f02831be | 1215 | int nfreed = 0; |
48d42c42 | 1216 | |
f02831be | 1217 | lockdep_assert_held(&txq->lock); |
48d42c42 | 1218 | |
83f32a4b | 1219 | if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
1220 | IWL_ERR(trans, |
1221 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 1222 | __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, |
f02831be EG |
1223 | q->write_ptr, q->read_ptr); |
1224 | return; | |
1225 | } | |
48d42c42 | 1226 | |
83f32a4b JB |
1227 | for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx; |
1228 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { | |
48d42c42 | 1229 | |
f02831be EG |
1230 | if (nfreed++ > 0) { |
1231 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1232 | idx, q->write_ptr, q->read_ptr); | |
4c9706dc | 1233 | iwl_force_nmi(trans); |
f02831be EG |
1234 | } |
1235 | } | |
1236 | ||
804d4c5a | 1237 | if (q->read_ptr == q->write_ptr) { |
b9439491 | 1238 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
804d4c5a | 1239 | iwl_pcie_clear_cmd_in_flight(trans); |
b9439491 EG |
1240 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1241 | } | |
1242 | ||
4cf677fd | 1243 | iwl_pcie_txq_progress(txq); |
48d42c42 EG |
1244 | } |
1245 | ||
f02831be | 1246 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1247 | u16 txq_id) |
48d42c42 | 1248 | { |
20d3b647 | 1249 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1250 | u32 tbl_dw_addr; |
1251 | u32 tbl_dw; | |
1252 | u16 scd_q2ratid; | |
1253 | ||
1254 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1255 | ||
105183b1 | 1256 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1257 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1258 | ||
4fd442db | 1259 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1260 | |
1261 | if (txq_id & 0x1) | |
1262 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1263 | else | |
1264 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1265 | ||
4fd442db | 1266 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1267 | |
1268 | return 0; | |
1269 | } | |
1270 | ||
bd5f6a34 EG |
1271 | /* Receiver address (actually, Rx station's index into station table), |
1272 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1273 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1274 | ||
fea7795f | 1275 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, |
4cf677fd EG |
1276 | const struct iwl_trans_txq_scd_cfg *cfg, |
1277 | unsigned int wdg_timeout) | |
48d42c42 | 1278 | { |
9eae88fa | 1279 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4cf677fd | 1280 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; |
d4578ea8 | 1281 | int fifo = -1; |
4beaf6c2 | 1282 | |
9eae88fa JB |
1283 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1284 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1285 | |
4cf677fd EG |
1286 | txq->wd_timeout = msecs_to_jiffies(wdg_timeout); |
1287 | ||
d4578ea8 JB |
1288 | if (cfg) { |
1289 | fifo = cfg->fifo; | |
48d42c42 | 1290 | |
002a9e26 | 1291 | /* Disable the scheduler prior configuring the cmd queue */ |
3a736bcb EG |
1292 | if (txq_id == trans_pcie->cmd_queue && |
1293 | trans_pcie->scd_set_active) | |
002a9e26 AA |
1294 | iwl_scd_enable_set_active(trans, 0); |
1295 | ||
d4578ea8 JB |
1296 | /* Stop this Tx queue before configuring it */ |
1297 | iwl_scd_txq_set_inactive(trans, txq_id); | |
4beaf6c2 | 1298 | |
d4578ea8 JB |
1299 | /* Set this queue as a chain-building queue unless it is CMD */ |
1300 | if (txq_id != trans_pcie->cmd_queue) | |
1301 | iwl_scd_txq_set_chain(trans, txq_id); | |
48d42c42 | 1302 | |
64ba8930 | 1303 | if (cfg->aggregate) { |
d4578ea8 | 1304 | u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); |
48d42c42 | 1305 | |
d4578ea8 JB |
1306 | /* Map receiver-address / traffic-ID to this queue */ |
1307 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); | |
f4772520 | 1308 | |
d4578ea8 JB |
1309 | /* enable aggregations for the queue */ |
1310 | iwl_scd_txq_enable_agg(trans, txq_id); | |
4cf677fd | 1311 | txq->ampdu = true; |
d4578ea8 JB |
1312 | } else { |
1313 | /* | |
1314 | * disable aggregations for the queue, this will also | |
1315 | * make the ra_tid mapping configuration irrelevant | |
1316 | * since it is now a non-AGG queue. | |
1317 | */ | |
1318 | iwl_scd_txq_disable_agg(trans, txq_id); | |
1319 | ||
4cf677fd | 1320 | ssn = txq->q.read_ptr; |
d4578ea8 | 1321 | } |
4beaf6c2 | 1322 | } |
48d42c42 EG |
1323 | |
1324 | /* Place first TFD at index corresponding to start sequence number. | |
1325 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
4cf677fd EG |
1326 | txq->q.read_ptr = (ssn & 0xff); |
1327 | txq->q.write_ptr = (ssn & 0xff); | |
0294d9ee EG |
1328 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
1329 | (ssn & 0xff) | (txq_id << 8)); | |
1ce8658c | 1330 | |
d4578ea8 JB |
1331 | if (cfg) { |
1332 | u8 frame_limit = cfg->frame_limit; | |
48d42c42 | 1333 | |
d4578ea8 JB |
1334 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); |
1335 | ||
1336 | /* Set up Tx window size and frame limit for this queue */ | |
1337 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + | |
1338 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | |
1339 | iwl_trans_write_mem32(trans, | |
1340 | trans_pcie->scd_base_addr + | |
9eae88fa JB |
1341 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1342 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
d4578ea8 | 1343 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | |
9eae88fa | 1344 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & |
d4578ea8 JB |
1345 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); |
1346 | ||
1347 | /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ | |
1348 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), | |
1349 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1350 | (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1351 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1352 | SCD_QUEUE_STTS_REG_MSK); | |
002a9e26 AA |
1353 | |
1354 | /* enable the scheduler for this queue (only) */ | |
3a736bcb EG |
1355 | if (txq_id == trans_pcie->cmd_queue && |
1356 | trans_pcie->scd_set_active) | |
002a9e26 | 1357 | iwl_scd_enable_set_active(trans, BIT(txq_id)); |
0294d9ee EG |
1358 | |
1359 | IWL_DEBUG_TX_QUEUES(trans, | |
1360 | "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1361 | txq_id, fifo, ssn & 0xff); | |
1362 | } else { | |
1363 | IWL_DEBUG_TX_QUEUES(trans, | |
1364 | "Activate queue %d WrPtr: %d\n", | |
1365 | txq_id, ssn & 0xff); | |
d4578ea8 JB |
1366 | } |
1367 | ||
4cf677fd | 1368 | txq->active = true; |
4beaf6c2 EG |
1369 | } |
1370 | ||
42db09c1 LK |
1371 | void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, |
1372 | bool shared_mode) | |
1373 | { | |
1374 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1375 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
1376 | ||
1377 | txq->ampdu = !shared_mode; | |
1378 | } | |
1379 | ||
d4578ea8 JB |
1380 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, |
1381 | bool configure_scd) | |
288712a6 | 1382 | { |
8ad71bef | 1383 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1384 | u32 stts_addr = trans_pcie->scd_base_addr + |
1385 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1386 | static const u32 zero_val[4] = {}; | |
288712a6 | 1387 | |
e0b8d405 EG |
1388 | trans_pcie->txq[txq_id].frozen_expiry_remainder = 0; |
1389 | trans_pcie->txq[txq_id].frozen = false; | |
1390 | ||
fba1c627 EG |
1391 | /* |
1392 | * Upon HW Rfkill - we stop the device, and then stop the queues | |
1393 | * in the op_mode. Just for the sake of the simplicity of the op_mode, | |
1394 | * allow the op_mode to call txq_disable after it already called | |
1395 | * stop_device. | |
1396 | */ | |
9eae88fa | 1397 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
fba1c627 EG |
1398 | WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), |
1399 | "queue %d not used", txq_id); | |
9eae88fa | 1400 | return; |
48d42c42 EG |
1401 | } |
1402 | ||
d4578ea8 JB |
1403 | if (configure_scd) { |
1404 | iwl_scd_txq_set_inactive(trans, txq_id); | |
ac928f8d | 1405 | |
d4578ea8 JB |
1406 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1407 | ARRAY_SIZE(zero_val)); | |
1408 | } | |
986ea6c9 | 1409 | |
990aa6d7 | 1410 | iwl_pcie_txq_unmap(trans, txq_id); |
68972c46 | 1411 | trans_pcie->txq[txq_id].ampdu = false; |
6c3fd3f0 | 1412 | |
1ce8658c | 1413 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1414 | } |
1415 | ||
fd4abac5 TW |
1416 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1417 | ||
990aa6d7 | 1418 | /* |
f02831be | 1419 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 | 1420 | * @priv: device private data point |
e89044d7 | 1421 | * @cmd: a pointer to the ucode command structure |
fd4abac5 | 1422 | * |
e89044d7 EP |
1423 | * The function returns < 0 values to indicate the operation |
1424 | * failed. On success, it returns the index (>= 0) of command in the | |
fd4abac5 TW |
1425 | * command queue. |
1426 | */ | |
f02831be EG |
1427 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1428 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1429 | { |
8ad71bef | 1430 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1431 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1432 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1433 | struct iwl_device_cmd *out_cmd; |
1434 | struct iwl_cmd_meta *out_meta; | |
b9439491 | 1435 | unsigned long flags; |
f4feb8ac | 1436 | void *dup_buf = NULL; |
fd4abac5 | 1437 | dma_addr_t phys_addr; |
f4feb8ac | 1438 | int idx; |
8de437c7 | 1439 | u16 copy_size, cmd_size, tb0_size; |
4ce7cc2b | 1440 | bool had_nocopy = false; |
ab02165c | 1441 | u8 group_id = iwl_cmd_groupid(cmd->id); |
b9439491 | 1442 | int i, ret; |
96791422 | 1443 | u32 cmd_pos; |
1afbfb60 JB |
1444 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1445 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1446 | |
88742c9e JB |
1447 | if (WARN(!trans_pcie->wide_cmd_header && |
1448 | group_id > IWL_ALWAYS_LONG_GROUP, | |
ab02165c AE |
1449 | "unsupported wide command %#x\n", cmd->id)) |
1450 | return -EINVAL; | |
1451 | ||
1452 | if (group_id != 0) { | |
1453 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1454 | cmd_size = sizeof(struct iwl_cmd_header_wide); | |
1455 | } else { | |
1456 | copy_size = sizeof(struct iwl_cmd_header); | |
1457 | cmd_size = sizeof(struct iwl_cmd_header); | |
1458 | } | |
4ce7cc2b JB |
1459 | |
1460 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1461 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1462 | |
1afbfb60 | 1463 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1464 | cmddata[i] = cmd->data[i]; |
1465 | cmdlen[i] = cmd->len[i]; | |
1466 | ||
4ce7cc2b JB |
1467 | if (!cmd->len[i]) |
1468 | continue; | |
8a964f44 | 1469 | |
8de437c7 SS |
1470 | /* need at least IWL_FIRST_TB_SIZE copied */ |
1471 | if (copy_size < IWL_FIRST_TB_SIZE) { | |
1472 | int copy = IWL_FIRST_TB_SIZE - copy_size; | |
8a964f44 JB |
1473 | |
1474 | if (copy > cmdlen[i]) | |
1475 | copy = cmdlen[i]; | |
1476 | cmdlen[i] -= copy; | |
1477 | cmddata[i] += copy; | |
1478 | copy_size += copy; | |
1479 | } | |
1480 | ||
4ce7cc2b JB |
1481 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1482 | had_nocopy = true; | |
f4feb8ac JB |
1483 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1484 | idx = -EINVAL; | |
1485 | goto free_dup_buf; | |
1486 | } | |
1487 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1488 | /* | |
1489 | * This is also a chunk that isn't copied | |
1490 | * to the static buffer so set had_nocopy. | |
1491 | */ | |
1492 | had_nocopy = true; | |
1493 | ||
1494 | /* only allowed once */ | |
1495 | if (WARN_ON(dup_buf)) { | |
1496 | idx = -EINVAL; | |
1497 | goto free_dup_buf; | |
1498 | } | |
1499 | ||
8a964f44 | 1500 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1501 | GFP_ATOMIC); |
1502 | if (!dup_buf) | |
1503 | return -ENOMEM; | |
4ce7cc2b JB |
1504 | } else { |
1505 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1506 | if (WARN_ON(had_nocopy)) { |
1507 | idx = -EINVAL; | |
1508 | goto free_dup_buf; | |
1509 | } | |
8a964f44 | 1510 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1511 | } |
1512 | cmd_size += cmd->len[i]; | |
1513 | } | |
fd4abac5 | 1514 | |
3e41ace5 JB |
1515 | /* |
1516 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1517 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1518 | * allocated into separate TFDs, then we will need to | |
1519 | * increase the size of the buffers. | |
3e41ace5 | 1520 | */ |
2a79e45e JB |
1521 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1522 | "Command %s (%#x) is too large (%d bytes)\n", | |
39bdb17e SD |
1523 | iwl_get_cmd_string(trans, cmd->id), |
1524 | cmd->id, copy_size)) { | |
f4feb8ac JB |
1525 | idx = -EINVAL; |
1526 | goto free_dup_buf; | |
1527 | } | |
fd4abac5 | 1528 | |
015c15e1 | 1529 | spin_lock_bh(&txq->lock); |
3598e177 | 1530 | |
c2acea8e | 1531 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1532 | spin_unlock_bh(&txq->lock); |
3598e177 | 1533 | |
6d8f6eeb | 1534 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1535 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1536 | idx = -ENOSPC; |
1537 | goto free_dup_buf; | |
fd4abac5 TW |
1538 | } |
1539 | ||
4ce7cc2b | 1540 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1541 | out_cmd = txq->entries[idx].cmd; |
1542 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1543 | |
8ce73f3a | 1544 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1545 | if (cmd->flags & CMD_WANT_SKB) |
1546 | out_meta->source = cmd; | |
fd4abac5 | 1547 | |
4ce7cc2b | 1548 | /* set up the header */ |
ab02165c AE |
1549 | if (group_id != 0) { |
1550 | out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); | |
1551 | out_cmd->hdr_wide.group_id = group_id; | |
1552 | out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); | |
1553 | out_cmd->hdr_wide.length = | |
1554 | cpu_to_le16(cmd_size - | |
1555 | sizeof(struct iwl_cmd_header_wide)); | |
1556 | out_cmd->hdr_wide.reserved = 0; | |
1557 | out_cmd->hdr_wide.sequence = | |
1558 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
1559 | INDEX_TO_SEQ(q->write_ptr)); | |
1560 | ||
1561 | cmd_pos = sizeof(struct iwl_cmd_header_wide); | |
1562 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1563 | } else { | |
1564 | out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); | |
1565 | out_cmd->hdr.sequence = | |
1566 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
1567 | INDEX_TO_SEQ(q->write_ptr)); | |
1568 | out_cmd->hdr.group_id = 0; | |
1569 | ||
1570 | cmd_pos = sizeof(struct iwl_cmd_header); | |
1571 | copy_size = sizeof(struct iwl_cmd_header); | |
1572 | } | |
4ce7cc2b JB |
1573 | |
1574 | /* and copy the data that needs to be copied */ | |
1afbfb60 | 1575 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
4d075007 | 1576 | int copy; |
8a964f44 | 1577 | |
cc904c71 | 1578 | if (!cmd->len[i]) |
4ce7cc2b | 1579 | continue; |
8a964f44 | 1580 | |
8a964f44 JB |
1581 | /* copy everything if not nocopy/dup */ |
1582 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
4d075007 | 1583 | IWL_HCMD_DFL_DUP))) { |
8a964f44 JB |
1584 | copy = cmd->len[i]; |
1585 | ||
8a964f44 JB |
1586 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); |
1587 | cmd_pos += copy; | |
1588 | copy_size += copy; | |
4d075007 JB |
1589 | continue; |
1590 | } | |
1591 | ||
1592 | /* | |
8de437c7 SS |
1593 | * Otherwise we need at least IWL_FIRST_TB_SIZE copied |
1594 | * in total (for bi-directional DMA), but copy up to what | |
4d075007 JB |
1595 | * we can fit into the payload for debug dump purposes. |
1596 | */ | |
1597 | copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); | |
1598 | ||
1599 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1600 | cmd_pos += copy; | |
1601 | ||
1602 | /* However, treat copy_size the proper way, we need it below */ | |
8de437c7 SS |
1603 | if (copy_size < IWL_FIRST_TB_SIZE) { |
1604 | copy = IWL_FIRST_TB_SIZE - copy_size; | |
4d075007 JB |
1605 | |
1606 | if (copy > cmd->len[i]) | |
1607 | copy = cmd->len[i]; | |
1608 | copy_size += copy; | |
8a964f44 | 1609 | } |
96791422 EG |
1610 | } |
1611 | ||
d9fb6465 | 1612 | IWL_DEBUG_HC(trans, |
ab02165c | 1613 | "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
39bdb17e | 1614 | iwl_get_cmd_string(trans, cmd->id), |
ab02165c AE |
1615 | group_id, out_cmd->hdr.cmd, |
1616 | le16_to_cpu(out_cmd->hdr.sequence), | |
20d3b647 | 1617 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); |
4ce7cc2b | 1618 | |
8de437c7 SS |
1619 | /* start the TFD with the minimum copy bytes */ |
1620 | tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); | |
1621 | memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); | |
38c0f334 | 1622 | iwl_pcie_txq_build_tfd(trans, txq, |
8de437c7 SS |
1623 | iwl_pcie_get_first_tb_dma(txq, idx), |
1624 | tb0_size, true); | |
38c0f334 JB |
1625 | |
1626 | /* map first command fragment, if any remains */ | |
8de437c7 | 1627 | if (copy_size > tb0_size) { |
38c0f334 | 1628 | phys_addr = dma_map_single(trans->dev, |
8de437c7 SS |
1629 | ((u8 *)&out_cmd->hdr) + tb0_size, |
1630 | copy_size - tb0_size, | |
38c0f334 JB |
1631 | DMA_TO_DEVICE); |
1632 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
1633 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1634 | &txq->tfds[q->write_ptr]); | |
1635 | idx = -ENOMEM; | |
1636 | goto out; | |
1637 | } | |
8a964f44 | 1638 | |
38c0f334 | 1639 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
8de437c7 | 1640 | copy_size - tb0_size, false); |
2c46f72e JB |
1641 | } |
1642 | ||
8a964f44 | 1643 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1644 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1645 | const void *data = cmddata[i]; |
f4feb8ac | 1646 | |
8a964f44 | 1647 | if (!cmdlen[i]) |
4ce7cc2b | 1648 | continue; |
f4feb8ac JB |
1649 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1650 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1651 | continue; |
f4feb8ac JB |
1652 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1653 | data = dup_buf; | |
1654 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1655 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1656 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be | 1657 | iwl_pcie_tfd_unmap(trans, out_meta, |
98891754 | 1658 | &txq->tfds[q->write_ptr]); |
4ce7cc2b JB |
1659 | idx = -ENOMEM; |
1660 | goto out; | |
1661 | } | |
1662 | ||
6d6e68f8 | 1663 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); |
4ce7cc2b | 1664 | } |
df833b1d | 1665 | |
206eea78 JB |
1666 | BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS > |
1667 | sizeof(out_meta->flags) * BITS_PER_BYTE); | |
afaf6b57 | 1668 | out_meta->flags = cmd->flags; |
f4feb8ac | 1669 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
5d4185ae | 1670 | kzfree(txq->entries[idx].free_buf); |
f4feb8ac | 1671 | txq->entries[idx].free_buf = dup_buf; |
2c46f72e | 1672 | |
ab02165c | 1673 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); |
df833b1d | 1674 | |
7c5ba4a8 | 1675 | /* start timer if queue currently empty */ |
4cf677fd EG |
1676 | if (q->read_ptr == q->write_ptr && txq->wd_timeout) |
1677 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); | |
7c5ba4a8 | 1678 | |
b9439491 | 1679 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
7616f334 | 1680 | ret = iwl_pcie_set_cmd_in_flight(trans, cmd); |
804d4c5a EP |
1681 | if (ret < 0) { |
1682 | idx = ret; | |
1683 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1684 | goto out; | |
b9439491 EG |
1685 | } |
1686 | ||
fd4abac5 | 1687 | /* Increment and update queue's write index */ |
83f32a4b | 1688 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); |
990aa6d7 | 1689 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1690 | |
b9439491 EG |
1691 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1692 | ||
2c46f72e | 1693 | out: |
015c15e1 | 1694 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1695 | free_dup_buf: |
1696 | if (idx < 0) | |
1697 | kfree(dup_buf); | |
7bfedc59 | 1698 | return idx; |
fd4abac5 TW |
1699 | } |
1700 | ||
990aa6d7 EG |
1701 | /* |
1702 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1703 | * @rxb: Rx buffer to reclaim |
17b88929 | 1704 | */ |
990aa6d7 | 1705 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
f7e6469f | 1706 | struct iwl_rx_cmd_buffer *rxb) |
17b88929 | 1707 | { |
2f301227 | 1708 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 | 1709 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
39bdb17e SD |
1710 | u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id); |
1711 | u32 cmd_id; | |
17b88929 TW |
1712 | int txq_id = SEQ_TO_QUEUE(sequence); |
1713 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1714 | int cmd_index; |
c2acea8e JB |
1715 | struct iwl_device_cmd *cmd; |
1716 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1717 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1718 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1719 | |
1720 | /* If a Tx command is being handled and it isn't in the actual | |
1721 | * command queue then there a command routing bug has been introduced | |
1722 | * in the queue management code. */ | |
c6f600fc | 1723 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1724 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1725 | txq_id, trans_pcie->cmd_queue, sequence, |
1726 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1727 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1728 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1729 | return; |
01ef9323 | 1730 | } |
17b88929 | 1731 | |
2bfb5092 | 1732 | spin_lock_bh(&txq->lock); |
015c15e1 | 1733 | |
4ce7cc2b | 1734 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1735 | cmd = txq->entries[cmd_index].cmd; |
1736 | meta = &txq->entries[cmd_index].meta; | |
39bdb17e | 1737 | cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); |
17b88929 | 1738 | |
98891754 | 1739 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); |
c33de625 | 1740 | |
17b88929 | 1741 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1742 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1743 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1744 | |
65b94a4a JB |
1745 | meta->source->resp_pkt = pkt; |
1746 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1747 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1748 | } |
2624e96c | 1749 | |
dcbb4746 EG |
1750 | if (meta->flags & CMD_WANT_ASYNC_CALLBACK) |
1751 | iwl_op_mode_async_cb(trans->op_mode, cmd); | |
1752 | ||
f02831be | 1753 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1754 | |
c2acea8e | 1755 | if (!(meta->flags & CMD_ASYNC)) { |
eb7ff77e | 1756 | if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { |
05c89b91 WYG |
1757 | IWL_WARN(trans, |
1758 | "HCMD_ACTIVE already clear for command %s\n", | |
39bdb17e | 1759 | iwl_get_cmd_string(trans, cmd_id)); |
05c89b91 | 1760 | } |
eb7ff77e | 1761 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6d8f6eeb | 1762 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
39bdb17e | 1763 | iwl_get_cmd_string(trans, cmd_id)); |
f946b529 | 1764 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1765 | } |
3598e177 | 1766 | |
4cbb8e50 LC |
1767 | if (meta->flags & CMD_MAKE_TRANS_IDLE) { |
1768 | IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", | |
1769 | iwl_get_cmd_string(trans, cmd->hdr.cmd)); | |
1770 | set_bit(STATUS_TRANS_IDLE, &trans->status); | |
1771 | wake_up(&trans_pcie->d0i3_waitq); | |
1772 | } | |
1773 | ||
1774 | if (meta->flags & CMD_WAKE_UP_TRANS) { | |
1775 | IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", | |
1776 | iwl_get_cmd_string(trans, cmd->hdr.cmd)); | |
1777 | clear_bit(STATUS_TRANS_IDLE, &trans->status); | |
1778 | wake_up(&trans_pcie->d0i3_waitq); | |
1779 | } | |
1780 | ||
dd487449 | 1781 | meta->flags = 0; |
3598e177 | 1782 | |
2bfb5092 | 1783 | spin_unlock_bh(&txq->lock); |
17b88929 | 1784 | } |
253a634c | 1785 | |
9439eac7 | 1786 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
253a634c | 1787 | |
f02831be EG |
1788 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1789 | struct iwl_host_cmd *cmd) | |
253a634c EG |
1790 | { |
1791 | int ret; | |
1792 | ||
1793 | /* An asynchronous command can not expect an SKB to be set. */ | |
1794 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1795 | return -EINVAL; | |
1796 | ||
f02831be | 1797 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1798 | if (ret < 0) { |
721c32f7 | 1799 | IWL_ERR(trans, |
b36b110c | 1800 | "Error sending %s: enqueue_hcmd failed: %d\n", |
39bdb17e | 1801 | iwl_get_cmd_string(trans, cmd->id), ret); |
253a634c EG |
1802 | return ret; |
1803 | } | |
1804 | return 0; | |
1805 | } | |
1806 | ||
f02831be EG |
1807 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1808 | struct iwl_host_cmd *cmd) | |
253a634c | 1809 | { |
8ad71bef | 1810 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1811 | int cmd_idx; |
1812 | int ret; | |
1813 | ||
6d8f6eeb | 1814 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
39bdb17e | 1815 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c | 1816 | |
eb7ff77e AN |
1817 | if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, |
1818 | &trans->status), | |
bcbb8c9c | 1819 | "Command %s: a command is already active!\n", |
39bdb17e | 1820 | iwl_get_cmd_string(trans, cmd->id))) |
2cc39c94 | 1821 | return -EIO; |
2cc39c94 | 1822 | |
6d8f6eeb | 1823 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
39bdb17e | 1824 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c | 1825 | |
71b1230c LC |
1826 | if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { |
1827 | ret = wait_event_timeout(trans_pcie->d0i3_waitq, | |
1828 | pm_runtime_active(&trans_pcie->pci_dev->dev), | |
1829 | msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); | |
1830 | if (!ret) { | |
1831 | IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); | |
1832 | return -ETIMEDOUT; | |
1833 | } | |
1834 | } | |
1835 | ||
f02831be | 1836 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1837 | if (cmd_idx < 0) { |
1838 | ret = cmd_idx; | |
eb7ff77e | 1839 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
721c32f7 | 1840 | IWL_ERR(trans, |
b36b110c | 1841 | "Error sending %s: enqueue_hcmd failed: %d\n", |
39bdb17e | 1842 | iwl_get_cmd_string(trans, cmd->id), ret); |
253a634c EG |
1843 | return ret; |
1844 | } | |
1845 | ||
b9439491 EG |
1846 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
1847 | !test_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1848 | &trans->status), | |
1849 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1850 | if (!ret) { |
6dde8c48 JB |
1851 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
1852 | struct iwl_queue *q = &txq->q; | |
d10630af | 1853 | |
6dde8c48 | 1854 | IWL_ERR(trans, "Error sending %s: time out after %dms.\n", |
39bdb17e | 1855 | iwl_get_cmd_string(trans, cmd->id), |
6dde8c48 | 1856 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
253a634c | 1857 | |
6dde8c48 JB |
1858 | IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", |
1859 | q->read_ptr, q->write_ptr); | |
d10630af | 1860 | |
eb7ff77e | 1861 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6dde8c48 | 1862 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
39bdb17e | 1863 | iwl_get_cmd_string(trans, cmd->id)); |
6dde8c48 | 1864 | ret = -ETIMEDOUT; |
42550a53 | 1865 | |
4c9706dc | 1866 | iwl_force_nmi(trans); |
2a988e98 | 1867 | iwl_trans_fw_error(trans); |
42550a53 | 1868 | |
6dde8c48 | 1869 | goto cancel; |
253a634c EG |
1870 | } |
1871 | ||
eb7ff77e | 1872 | if (test_bit(STATUS_FW_ERROR, &trans->status)) { |
d18aa87f | 1873 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", |
39bdb17e | 1874 | iwl_get_cmd_string(trans, cmd->id)); |
b656fa33 | 1875 | dump_stack(); |
d18aa87f JB |
1876 | ret = -EIO; |
1877 | goto cancel; | |
1878 | } | |
1879 | ||
1094fa26 | 1880 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1881 | test_bit(STATUS_RFKILL, &trans->status)) { |
f946b529 EG |
1882 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1883 | ret = -ERFKILL; | |
1884 | goto cancel; | |
1885 | } | |
1886 | ||
65b94a4a | 1887 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1888 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
39bdb17e | 1889 | iwl_get_cmd_string(trans, cmd->id)); |
253a634c EG |
1890 | ret = -EIO; |
1891 | goto cancel; | |
1892 | } | |
1893 | ||
1894 | return 0; | |
1895 | ||
1896 | cancel: | |
1897 | if (cmd->flags & CMD_WANT_SKB) { | |
1898 | /* | |
1899 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1900 | * TX cmd queue. Otherwise in case the cmd comes | |
1901 | * in later, it will possibly set an invalid | |
1902 | * address (cmd->meta.source). | |
1903 | */ | |
bf8440e6 JB |
1904 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1905 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1906 | } |
9cac4943 | 1907 | |
65b94a4a JB |
1908 | if (cmd->resp_pkt) { |
1909 | iwl_free_resp(cmd); | |
1910 | cmd->resp_pkt = NULL; | |
253a634c EG |
1911 | } |
1912 | ||
1913 | return ret; | |
1914 | } | |
1915 | ||
f02831be | 1916 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1917 | { |
4f59334b | 1918 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1919 | test_bit(STATUS_RFKILL, &trans->status)) { |
754d7d9e EG |
1920 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1921 | cmd->id); | |
f946b529 | 1922 | return -ERFKILL; |
754d7d9e | 1923 | } |
f946b529 | 1924 | |
253a634c | 1925 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1926 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1927 | |
f946b529 | 1928 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1929 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1930 | } |
1931 | ||
3a0b2a42 EG |
1932 | static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, |
1933 | struct iwl_txq *txq, u8 hdr_len, | |
1934 | struct iwl_cmd_meta *out_meta, | |
1935 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
1936 | { | |
1937 | struct iwl_queue *q = &txq->q; | |
1938 | u16 tb2_len; | |
1939 | int i; | |
1940 | ||
1941 | /* | |
1942 | * Set up TFD's third entry to point directly to remainder | |
1943 | * of skb's head, if any | |
1944 | */ | |
1945 | tb2_len = skb_headlen(skb) - hdr_len; | |
1946 | ||
1947 | if (tb2_len > 0) { | |
1948 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1949 | skb->data + hdr_len, | |
1950 | tb2_len, DMA_TO_DEVICE); | |
1951 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
1952 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1953 | &txq->tfds[q->write_ptr]); | |
1954 | return -EINVAL; | |
1955 | } | |
1956 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); | |
1957 | } | |
1958 | ||
1959 | /* set up the remaining entries to point to the data */ | |
1960 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1961 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1962 | dma_addr_t tb_phys; | |
1963 | int tb_idx; | |
1964 | ||
1965 | if (!skb_frag_size(frag)) | |
1966 | continue; | |
1967 | ||
1968 | tb_phys = skb_frag_dma_map(trans->dev, frag, 0, | |
1969 | skb_frag_size(frag), DMA_TO_DEVICE); | |
1970 | ||
1971 | if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { | |
1972 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1973 | &txq->tfds[q->write_ptr]); | |
1974 | return -EINVAL; | |
1975 | } | |
1976 | tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, | |
1977 | skb_frag_size(frag), false); | |
1978 | ||
1979 | out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS); | |
1980 | } | |
1981 | ||
1982 | trace_iwlwifi_dev_tx(trans->dev, skb, | |
1983 | &txq->tfds[txq->q.write_ptr], | |
1984 | sizeof(struct iwl_tfd), | |
8de437c7 | 1985 | &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, |
3a0b2a42 EG |
1986 | skb->data + hdr_len, tb2_len); |
1987 | trace_iwlwifi_dev_tx_data(trans->dev, skb, | |
1988 | hdr_len, skb->len - hdr_len); | |
1989 | return 0; | |
1990 | } | |
1991 | ||
6eb5e529 EG |
1992 | #ifdef CONFIG_INET |
1993 | static struct iwl_tso_hdr_page * | |
1994 | get_page_hdr(struct iwl_trans *trans, size_t len) | |
1995 | { | |
1996 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1997 | struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); | |
1998 | ||
1999 | if (!p->page) | |
2000 | goto alloc; | |
2001 | ||
2002 | /* enough room on this page */ | |
2003 | if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) | |
2004 | return p; | |
2005 | ||
2006 | /* We don't have enough room on this page, get a new one. */ | |
2007 | __free_page(p->page); | |
2008 | ||
2009 | alloc: | |
2010 | p->page = alloc_page(GFP_ATOMIC); | |
2011 | if (!p->page) | |
2012 | return NULL; | |
2013 | p->pos = page_address(p->page); | |
2014 | return p; | |
2015 | } | |
2016 | ||
2017 | static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, | |
2018 | bool ipv6, unsigned int len) | |
2019 | { | |
2020 | if (ipv6) { | |
2021 | struct ipv6hdr *iphv6 = iph; | |
2022 | ||
2023 | tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, | |
2024 | len + tcph->doff * 4, | |
2025 | IPPROTO_TCP, 0); | |
2026 | } else { | |
2027 | struct iphdr *iphv4 = iph; | |
2028 | ||
2029 | ip_send_check(iphv4); | |
2030 | tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, | |
2031 | len + tcph->doff * 4, | |
2032 | IPPROTO_TCP, 0); | |
2033 | } | |
2034 | } | |
2035 | ||
2036 | static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, | |
2037 | struct iwl_txq *txq, u8 hdr_len, | |
2038 | struct iwl_cmd_meta *out_meta, | |
2039 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
2040 | { | |
6eb5e529 EG |
2041 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; |
2042 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
2043 | unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; | |
2044 | unsigned int mss = skb_shinfo(skb)->gso_size; | |
2045 | struct iwl_queue *q = &txq->q; | |
2046 | u16 length, iv_len, amsdu_pad; | |
2047 | u8 *start_hdr; | |
2048 | struct iwl_tso_hdr_page *hdr_page; | |
21cb3222 | 2049 | struct page **page_ptr; |
6eb5e529 EG |
2050 | int ret; |
2051 | struct tso_t tso; | |
2052 | ||
2053 | /* if the packet is protected, then it must be CCMP or GCMP */ | |
2054 | BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); | |
2055 | iv_len = ieee80211_has_protected(hdr->frame_control) ? | |
2056 | IEEE80211_CCMP_HDR_LEN : 0; | |
2057 | ||
2058 | trace_iwlwifi_dev_tx(trans->dev, skb, | |
2059 | &txq->tfds[txq->q.write_ptr], | |
2060 | sizeof(struct iwl_tfd), | |
8de437c7 | 2061 | &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, |
6eb5e529 EG |
2062 | NULL, 0); |
2063 | ||
2064 | ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); | |
2065 | snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); | |
2066 | total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; | |
2067 | amsdu_pad = 0; | |
2068 | ||
2069 | /* total amount of header we may need for this A-MSDU */ | |
2070 | hdr_room = DIV_ROUND_UP(total_len, mss) * | |
2071 | (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; | |
2072 | ||
2073 | /* Our device supports 9 segments at most, it will fit in 1 page */ | |
2074 | hdr_page = get_page_hdr(trans, hdr_room); | |
2075 | if (!hdr_page) | |
2076 | return -ENOMEM; | |
2077 | ||
2078 | get_page(hdr_page->page); | |
2079 | start_hdr = hdr_page->pos; | |
21cb3222 JB |
2080 | page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); |
2081 | *page_ptr = hdr_page->page; | |
6eb5e529 EG |
2082 | memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); |
2083 | hdr_page->pos += iv_len; | |
2084 | ||
2085 | /* | |
2086 | * Pull the ieee80211 header + IV to be able to use TSO core, | |
2087 | * we will restore it for the tx_status flow. | |
2088 | */ | |
2089 | skb_pull(skb, hdr_len + iv_len); | |
2090 | ||
2091 | tso_start(skb, &tso); | |
2092 | ||
2093 | while (total_len) { | |
2094 | /* this is the data left for this subframe */ | |
2095 | unsigned int data_left = | |
2096 | min_t(unsigned int, mss, total_len); | |
2097 | struct sk_buff *csum_skb = NULL; | |
2098 | unsigned int hdr_tb_len; | |
2099 | dma_addr_t hdr_tb_phys; | |
2100 | struct tcphdr *tcph; | |
2101 | u8 *iph; | |
2102 | ||
2103 | total_len -= data_left; | |
2104 | ||
2105 | memset(hdr_page->pos, 0, amsdu_pad); | |
2106 | hdr_page->pos += amsdu_pad; | |
2107 | amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + | |
2108 | data_left)) & 0x3; | |
2109 | ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); | |
2110 | hdr_page->pos += ETH_ALEN; | |
2111 | ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); | |
2112 | hdr_page->pos += ETH_ALEN; | |
2113 | ||
2114 | length = snap_ip_tcp_hdrlen + data_left; | |
2115 | *((__be16 *)hdr_page->pos) = cpu_to_be16(length); | |
2116 | hdr_page->pos += sizeof(length); | |
2117 | ||
2118 | /* | |
2119 | * This will copy the SNAP as well which will be considered | |
2120 | * as MAC header. | |
2121 | */ | |
2122 | tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); | |
2123 | iph = hdr_page->pos + 8; | |
2124 | tcph = (void *)(iph + ip_hdrlen); | |
2125 | ||
2126 | /* For testing on current hardware only */ | |
2127 | if (trans_pcie->sw_csum_tx) { | |
2128 | csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), | |
2129 | GFP_ATOMIC); | |
2130 | if (!csum_skb) { | |
2131 | ret = -ENOMEM; | |
2132 | goto out_unmap; | |
2133 | } | |
2134 | ||
2135 | iwl_compute_pseudo_hdr_csum(iph, tcph, | |
2136 | skb->protocol == | |
2137 | htons(ETH_P_IPV6), | |
2138 | data_left); | |
2139 | ||
2140 | memcpy(skb_put(csum_skb, tcp_hdrlen(skb)), | |
2141 | tcph, tcp_hdrlen(skb)); | |
2142 | skb_set_transport_header(csum_skb, 0); | |
2143 | csum_skb->csum_start = | |
2144 | (unsigned char *)tcp_hdr(csum_skb) - | |
2145 | csum_skb->head; | |
2146 | } | |
2147 | ||
2148 | hdr_page->pos += snap_ip_tcp_hdrlen; | |
2149 | ||
2150 | hdr_tb_len = hdr_page->pos - start_hdr; | |
2151 | hdr_tb_phys = dma_map_single(trans->dev, start_hdr, | |
2152 | hdr_tb_len, DMA_TO_DEVICE); | |
2153 | if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { | |
2154 | dev_kfree_skb(csum_skb); | |
2155 | ret = -EINVAL; | |
2156 | goto out_unmap; | |
2157 | } | |
2158 | iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, | |
2159 | hdr_tb_len, false); | |
2160 | trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, | |
2161 | hdr_tb_len); | |
2162 | ||
2163 | /* prepare the start_hdr for the next subframe */ | |
2164 | start_hdr = hdr_page->pos; | |
2165 | ||
2166 | /* put the payload */ | |
2167 | while (data_left) { | |
2168 | unsigned int size = min_t(unsigned int, tso.size, | |
2169 | data_left); | |
2170 | dma_addr_t tb_phys; | |
2171 | ||
2172 | if (trans_pcie->sw_csum_tx) | |
2173 | memcpy(skb_put(csum_skb, size), tso.data, size); | |
2174 | ||
2175 | tb_phys = dma_map_single(trans->dev, tso.data, | |
2176 | size, DMA_TO_DEVICE); | |
2177 | if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { | |
2178 | dev_kfree_skb(csum_skb); | |
2179 | ret = -EINVAL; | |
2180 | goto out_unmap; | |
2181 | } | |
2182 | ||
2183 | iwl_pcie_txq_build_tfd(trans, txq, tb_phys, | |
2184 | size, false); | |
2185 | trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, | |
2186 | size); | |
2187 | ||
2188 | data_left -= size; | |
2189 | tso_build_data(skb, &tso, size); | |
2190 | } | |
2191 | ||
2192 | /* For testing on early hardware only */ | |
2193 | if (trans_pcie->sw_csum_tx) { | |
2194 | __wsum csum; | |
2195 | ||
2196 | csum = skb_checksum(csum_skb, | |
2197 | skb_checksum_start_offset(csum_skb), | |
2198 | csum_skb->len - | |
2199 | skb_checksum_start_offset(csum_skb), | |
2200 | 0); | |
2201 | dev_kfree_skb(csum_skb); | |
2202 | dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, | |
2203 | hdr_tb_len, DMA_TO_DEVICE); | |
2204 | tcph->check = csum_fold(csum); | |
2205 | dma_sync_single_for_device(trans->dev, hdr_tb_phys, | |
2206 | hdr_tb_len, DMA_TO_DEVICE); | |
2207 | } | |
2208 | } | |
2209 | ||
2210 | /* re -add the WiFi header and IV */ | |
2211 | skb_push(skb, hdr_len + iv_len); | |
2212 | ||
2213 | return 0; | |
2214 | ||
2215 | out_unmap: | |
2216 | iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]); | |
2217 | return ret; | |
2218 | } | |
2219 | #else /* CONFIG_INET */ | |
2220 | static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, | |
2221 | struct iwl_txq *txq, u8 hdr_len, | |
2222 | struct iwl_cmd_meta *out_meta, | |
2223 | struct iwl_device_cmd *dev_cmd, u16 tb1_len) | |
2224 | { | |
2225 | /* No A-MSDU without CONFIG_INET */ | |
2226 | WARN_ON(1); | |
2227 | ||
2228 | return -1; | |
2229 | } | |
2230 | #endif /* CONFIG_INET */ | |
2231 | ||
f02831be EG |
2232 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
2233 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 2234 | { |
8ad71bef | 2235 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
206eea78 | 2236 | struct ieee80211_hdr *hdr; |
f02831be EG |
2237 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; |
2238 | struct iwl_cmd_meta *out_meta; | |
2239 | struct iwl_txq *txq; | |
2240 | struct iwl_queue *q; | |
38c0f334 JB |
2241 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
2242 | void *tb1_addr; | |
3a0b2a42 | 2243 | u16 len, tb1_len; |
ea68f460 | 2244 | bool wait_write_ptr; |
206eea78 JB |
2245 | __le16 fc; |
2246 | u8 hdr_len; | |
68972c46 | 2247 | u16 wifi_seq; |
c772a3d3 | 2248 | bool amsdu; |
f02831be EG |
2249 | |
2250 | txq = &trans_pcie->txq[txq_id]; | |
2251 | q = &txq->q; | |
a0eaad71 | 2252 | |
961de6a5 JB |
2253 | if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), |
2254 | "TX on unused queue %d\n", txq_id)) | |
f02831be | 2255 | return -EINVAL; |
39644e9a | 2256 | |
41837ca9 EG |
2257 | if (unlikely(trans_pcie->sw_csum_tx && |
2258 | skb->ip_summed == CHECKSUM_PARTIAL)) { | |
2259 | int offs = skb_checksum_start_offset(skb); | |
2260 | int csum_offs = offs + skb->csum_offset; | |
2261 | __wsum csum; | |
2262 | ||
2263 | if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) | |
2264 | return -1; | |
2265 | ||
2266 | csum = skb_checksum(skb, offs, skb->len - offs, 0); | |
2267 | *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); | |
3955525d EG |
2268 | |
2269 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
41837ca9 EG |
2270 | } |
2271 | ||
206eea78 JB |
2272 | if (skb_is_nonlinear(skb) && |
2273 | skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS && | |
2274 | __skb_linearize(skb)) | |
2275 | return -ENOMEM; | |
2276 | ||
2277 | /* mac80211 always puts the full header into the SKB's head, | |
2278 | * so there's no need to check if it's readable there | |
2279 | */ | |
2280 | hdr = (struct ieee80211_hdr *)skb->data; | |
2281 | fc = hdr->frame_control; | |
2282 | hdr_len = ieee80211_hdrlen(fc); | |
2283 | ||
f02831be | 2284 | spin_lock(&txq->lock); |
015c15e1 | 2285 | |
3955525d EG |
2286 | if (iwl_queue_space(q) < q->high_mark) { |
2287 | iwl_stop_queue(trans, txq); | |
2288 | ||
2289 | /* don't put the packet on the ring, if there is no room */ | |
2290 | if (unlikely(iwl_queue_space(q) < 3)) { | |
21cb3222 JB |
2291 | struct iwl_device_cmd **dev_cmd_ptr; |
2292 | ||
2293 | dev_cmd_ptr = (void *)((u8 *)skb->cb + | |
2294 | trans_pcie->dev_cmd_offs); | |
3955525d | 2295 | |
21cb3222 | 2296 | *dev_cmd_ptr = dev_cmd; |
3955525d EG |
2297 | __skb_queue_tail(&txq->overflow_q, skb); |
2298 | ||
2299 | spin_unlock(&txq->lock); | |
2300 | return 0; | |
2301 | } | |
2302 | } | |
2303 | ||
f02831be EG |
2304 | /* In AGG mode, the index in the ring must correspond to the WiFi |
2305 | * sequence number. This is a HW requirements to help the SCD to parse | |
2306 | * the BA. | |
2307 | * Check here that the packets are in the right place on the ring. | |
2308 | */ | |
9a886586 | 2309 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
1092b9bc | 2310 | WARN_ONCE(txq->ampdu && |
68972c46 | 2311 | (wifi_seq & 0xff) != q->write_ptr, |
f02831be EG |
2312 | "Q: %d WiFi Seq %d tfdNum %d", |
2313 | txq_id, wifi_seq, q->write_ptr); | |
f02831be EG |
2314 | |
2315 | /* Set up driver data for this TFD */ | |
2316 | txq->entries[q->write_ptr].skb = skb; | |
2317 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
2318 | ||
f02831be EG |
2319 | dev_cmd->hdr.sequence = |
2320 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
2321 | INDEX_TO_SEQ(q->write_ptr))); | |
2322 | ||
8de437c7 | 2323 | tb0_phys = iwl_pcie_get_first_tb_dma(txq, q->write_ptr); |
38c0f334 JB |
2324 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + |
2325 | offsetof(struct iwl_tx_cmd, scratch); | |
2326 | ||
2327 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
2328 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
2329 | ||
f02831be EG |
2330 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
2331 | out_meta = &txq->entries[q->write_ptr].meta; | |
206eea78 | 2332 | out_meta->flags = 0; |
a0eaad71 | 2333 | |
f02831be | 2334 | /* |
38c0f334 JB |
2335 | * The second TB (tb1) points to the remainder of the TX command |
2336 | * and the 802.11 header - dword aligned size | |
2337 | * (This calculation modifies the TX command, so do it before the | |
2338 | * setup of the first TB) | |
f02831be | 2339 | */ |
38c0f334 | 2340 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
8de437c7 | 2341 | hdr_len - IWL_FIRST_TB_SIZE; |
c772a3d3 SS |
2342 | /* do not align A-MSDU to dword as the subframe header aligns it */ |
2343 | amsdu = ieee80211_is_data_qos(fc) && | |
2344 | (*ieee80211_get_qos_ctl(hdr) & | |
2345 | IEEE80211_QOS_CTL_A_MSDU_PRESENT); | |
2346 | if (trans_pcie->sw_csum_tx || !amsdu) { | |
2347 | tb1_len = ALIGN(len, 4); | |
2348 | /* Tell NIC about any 2-byte padding after MAC header */ | |
2349 | if (tb1_len != len) | |
2350 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
2351 | } else { | |
2352 | tb1_len = len; | |
2353 | } | |
f02831be | 2354 | |
8de437c7 SS |
2355 | /* The first TB points to bi-directional DMA data */ |
2356 | memcpy(&txq->first_tb_bufs[q->write_ptr], &dev_cmd->hdr, | |
2357 | IWL_FIRST_TB_SIZE); | |
38c0f334 | 2358 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, |
8de437c7 | 2359 | IWL_FIRST_TB_SIZE, true); |
f02831be | 2360 | |
38c0f334 | 2361 | /* there must be data left over for TB1 or this code must be changed */ |
8de437c7 | 2362 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); |
38c0f334 JB |
2363 | |
2364 | /* map the data for TB1 */ | |
8de437c7 | 2365 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; |
38c0f334 JB |
2366 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); |
2367 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
2368 | goto out_err; | |
6d6e68f8 | 2369 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); |
a0eaad71 | 2370 | |
c772a3d3 | 2371 | if (amsdu) { |
6eb5e529 EG |
2372 | if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, |
2373 | out_meta, dev_cmd, | |
2374 | tb1_len))) | |
2375 | goto out_err; | |
2376 | } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, | |
2377 | out_meta, dev_cmd, tb1_len))) { | |
3a0b2a42 | 2378 | goto out_err; |
6eb5e529 | 2379 | } |
206eea78 | 2380 | |
f02831be EG |
2381 | /* Set up entry for this TFD in Tx byte-count array */ |
2382 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 2383 | |
ea68f460 | 2384 | wait_write_ptr = ieee80211_has_morefrags(fc); |
7c5ba4a8 | 2385 | |
f02831be | 2386 | /* start timer if queue currently empty */ |
7616f334 | 2387 | if (q->read_ptr == q->write_ptr) { |
aecdc63d EG |
2388 | if (txq->wd_timeout) { |
2389 | /* | |
2390 | * If the TXQ is active, then set the timer, if not, | |
2391 | * set the timer in remainder so that the timer will | |
2392 | * be armed with the right value when the station will | |
2393 | * wake up. | |
2394 | */ | |
2395 | if (!txq->frozen) | |
2396 | mod_timer(&txq->stuck_timer, | |
2397 | jiffies + txq->wd_timeout); | |
2398 | else | |
2399 | txq->frozen_expiry_remainder = txq->wd_timeout; | |
2400 | } | |
7616f334 | 2401 | IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id); |
c24c7f58 | 2402 | iwl_trans_ref(trans); |
7616f334 | 2403 | } |
f02831be EG |
2404 | |
2405 | /* Tell device the write index *just past* this latest filled TFD */ | |
83f32a4b | 2406 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); |
ea68f460 JB |
2407 | if (!wait_write_ptr) |
2408 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
f02831be EG |
2409 | |
2410 | /* | |
2411 | * At this point the frame is "transmitted" successfully | |
43aa616f | 2412 | * and we will get a TX status notification eventually. |
f02831be | 2413 | */ |
f02831be EG |
2414 | spin_unlock(&txq->lock); |
2415 | return 0; | |
2416 | out_err: | |
2417 | spin_unlock(&txq->lock); | |
2418 | return -1; | |
a0eaad71 | 2419 | } |