iwlwifi: mvm: modify the max SP to infinite
[deliverable/linux.git] / drivers / net / wireless / intel / iwlwifi / pcie / tx.c
CommitLineData
1053d35f
RR
1/******************************************************************************
2 *
51368bf7 3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4cbb8e50
LC
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 Intel Deutschland GmbH
1053d35f
RR
6 *
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
25 *
26 * Contact Information:
cb2f8277 27 * Intel Linux Wireless <linuxwifi@intel.com>
1053d35f
RR
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *
30 *****************************************************************************/
fd4abac5 31#include <linux/etherdevice.h>
6eb5e529 32#include <linux/ieee80211.h>
5a0e3ad6 33#include <linux/slab.h>
253a634c 34#include <linux/sched.h>
6eb5e529
EG
35#include <net/ip6_checksum.h>
36#include <net/tso.h>
253a634c 37
522376d2
EG
38#include "iwl-debug.h"
39#include "iwl-csr.h"
40#include "iwl-prph.h"
1053d35f 41#include "iwl-io.h"
680073b7 42#include "iwl-scd.h"
ed277c93 43#include "iwl-op-mode.h"
6468a01a 44#include "internal.h"
6238b008 45/* FIXME: need to abstract out TX command (once we know what it looks like) */
1023fdc4 46#include "dvm/commands.h"
1053d35f 47
522376d2
EG
48#define IWL_TX_CRC_SIZE 4
49#define IWL_TX_DELIMITER_SIZE 4
50
f02831be
EG
51/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
52 * DMA services
53 *
54 * Theory of operation
55 *
56 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
57 * of buffer descriptors, each of which points to one or more data buffers for
58 * the device to read from or fill. Driver and device exchange status of each
59 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
60 * entries in each circular buffer, to protect against confusing empty and full
61 * queue states.
62 *
63 * The device reads or writes the data in the queues via the device's several
64 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
65 *
66 * For Tx queue, there are low mark and high mark limits. If, after queuing
67 * the packet for Tx, free space become < low mark, Tx queue stopped. When
68 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
69 * Tx queue resumed.
70 *
71 ***************************************************/
72static int iwl_queue_space(const struct iwl_queue *q)
73{
a9b29246
IY
74 unsigned int max;
75 unsigned int used;
f02831be 76
a9b29246
IY
77 /*
78 * To avoid ambiguity between empty and completely full queues, there
83f32a4b
JB
79 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
80 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
81 * to reserve any queue entries for this purpose.
a9b29246 82 */
83f32a4b 83 if (q->n_window < TFD_QUEUE_SIZE_MAX)
a9b29246
IY
84 max = q->n_window;
85 else
83f32a4b 86 max = TFD_QUEUE_SIZE_MAX - 1;
f02831be 87
a9b29246 88 /*
83f32a4b
JB
89 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
90 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
a9b29246 91 */
83f32a4b 92 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
a9b29246
IY
93
94 if (WARN_ON(used > max))
95 return 0;
96
97 return max - used;
f02831be
EG
98}
99
100/*
101 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
102 */
83f32a4b 103static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
f02831be 104{
f02831be
EG
105 q->n_window = slots_num;
106 q->id = id;
107
f02831be
EG
108 /* slots_num must be power-of-two size, otherwise
109 * get_cmd_index is broken. */
110 if (WARN_ON(!is_power_of_2(slots_num)))
111 return -EINVAL;
112
113 q->low_mark = q->n_window / 4;
114 if (q->low_mark < 4)
115 q->low_mark = 4;
116
117 q->high_mark = q->n_window / 8;
118 if (q->high_mark < 2)
119 q->high_mark = 2;
120
121 q->write_ptr = 0;
122 q->read_ptr = 0;
123
124 return 0;
125}
126
f02831be
EG
127static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
128 struct iwl_dma_ptr *ptr, size_t size)
129{
130 if (WARN_ON(ptr->addr))
131 return -EINVAL;
132
133 ptr->addr = dma_alloc_coherent(trans->dev, size,
134 &ptr->dma, GFP_KERNEL);
135 if (!ptr->addr)
136 return -ENOMEM;
137 ptr->size = size;
138 return 0;
139}
140
141static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
142 struct iwl_dma_ptr *ptr)
143{
144 if (unlikely(!ptr->addr))
145 return;
146
147 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
148 memset(ptr, 0, sizeof(*ptr));
149}
150
151static void iwl_pcie_txq_stuck_timer(unsigned long data)
152{
153 struct iwl_txq *txq = (void *)data;
f02831be
EG
154 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
155 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
156 u32 scd_sram_addr = trans_pcie->scd_base_addr +
157 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
158 u8 buf[16];
159 int i;
160
161 spin_lock(&txq->lock);
162 /* check if triggered erroneously */
163 if (txq->q.read_ptr == txq->q.write_ptr) {
164 spin_unlock(&txq->lock);
165 return;
166 }
167 spin_unlock(&txq->lock);
168
169 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
4cf677fd 170 jiffies_to_msecs(txq->wd_timeout));
f02831be
EG
171 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
172 txq->q.read_ptr, txq->q.write_ptr);
173
4fd442db 174 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
f02831be
EG
175
176 iwl_print_hex_error(trans, buf, sizeof(buf));
177
178 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
179 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
180 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
181
182 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
183 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
184 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
185 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
186 u32 tbl_dw =
4fd442db
EG
187 iwl_trans_read_mem32(trans,
188 trans_pcie->scd_base_addr +
189 SCD_TRANS_TBL_OFFSET_QUEUE(i));
f02831be
EG
190
191 if (i & 0x1)
192 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
193 else
194 tbl_dw = tbl_dw & 0x0000FFFF;
195
196 IWL_ERR(trans,
197 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
198 i, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB
199 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
200 (TFD_QUEUE_SIZE_MAX - 1),
f02831be
EG
201 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
202 }
203
4c9706dc 204 iwl_force_nmi(trans);
f02831be
EG
205}
206
990aa6d7
EG
207/*
208 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
48d42c42 209 */
f02831be
EG
210static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
211 struct iwl_txq *txq, u16 byte_cnt)
48d42c42 212{
105183b1 213 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
20d3b647 214 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
48d42c42
EG
215 int write_ptr = txq->q.write_ptr;
216 int txq_id = txq->q.id;
217 u8 sec_ctl = 0;
218 u8 sta_id = 0;
219 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
220 __le16 bc_ent;
132f98c2 221 struct iwl_tx_cmd *tx_cmd =
bf8440e6 222 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
48d42c42 223
105183b1
EG
224 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
225
132f98c2
EG
226 sta_id = tx_cmd->sta_id;
227 sec_ctl = tx_cmd->sec_ctl;
48d42c42
EG
228
229 switch (sec_ctl & TX_CMD_SEC_MSK) {
230 case TX_CMD_SEC_CCM:
4325f6ca 231 len += IEEE80211_CCMP_MIC_LEN;
48d42c42
EG
232 break;
233 case TX_CMD_SEC_TKIP:
4325f6ca 234 len += IEEE80211_TKIP_ICV_LEN;
48d42c42
EG
235 break;
236 case TX_CMD_SEC_WEP:
4325f6ca 237 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
48d42c42
EG
238 break;
239 }
240
046db346
EG
241 if (trans_pcie->bc_table_dword)
242 len = DIV_ROUND_UP(len, 4);
243
31f920b6
EG
244 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
245 return;
246
046db346 247 bc_ent = cpu_to_le16(len | (sta_id << 12));
48d42c42
EG
248
249 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
250
251 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
252 scd_bc_tbl[txq_id].
253 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
254}
255
f02831be
EG
256static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
257 struct iwl_txq *txq)
258{
259 struct iwl_trans_pcie *trans_pcie =
260 IWL_TRANS_GET_PCIE_TRANS(trans);
261 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
262 int txq_id = txq->q.id;
263 int read_ptr = txq->q.read_ptr;
264 u8 sta_id = 0;
265 __le16 bc_ent;
266 struct iwl_tx_cmd *tx_cmd =
267 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
268
269 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
270
271 if (txq_id != trans_pcie->cmd_queue)
272 sta_id = tx_cmd->sta_id;
273
274 bc_ent = cpu_to_le16(1 | (sta_id << 12));
275 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
276
277 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
278 scd_bc_tbl[txq_id].
279 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
280}
281
990aa6d7
EG
282/*
283 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
fd4abac5 284 */
ea68f460
JB
285static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
286 struct iwl_txq *txq)
fd4abac5 287{
23e76d1a 288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
fd4abac5 289 u32 reg = 0;
fd4abac5
TW
290 int txq_id = txq->q.id;
291
ea68f460 292 lockdep_assert_held(&txq->lock);
fd4abac5 293
5045388c
EP
294 /*
295 * explicitly wake up the NIC if:
296 * 1. shadow registers aren't enabled
297 * 2. NIC is woken up for CMD regardless of shadow outside this function
298 * 3. there is a chance that the NIC is asleep
299 */
300 if (!trans->cfg->base_params->shadow_reg_enable &&
301 txq_id != trans_pcie->cmd_queue &&
302 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
f81c1f48 303 /*
5045388c
EP
304 * wake up nic if it's powered down ...
305 * uCode will wake up, and interrupt us again, so next
306 * time we'll skip this part.
f81c1f48 307 */
5045388c
EP
308 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
309
310 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
311 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
312 txq_id, reg);
313 iwl_set_bit(trans, CSR_GP_CNTRL,
314 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ea68f460 315 txq->need_update = true;
5045388c
EP
316 return;
317 }
f81c1f48 318 }
5045388c
EP
319
320 /*
321 * if not in power-save mode, uCode will never sleep when we're
322 * trying to tx (during RFKILL, we're not trying to tx).
323 */
324 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
0cd58eaa
EG
325 if (!txq->block)
326 iwl_write32(trans, HBUS_TARG_WRPTR,
327 txq->q.write_ptr | (txq_id << 8));
ea68f460 328}
5045388c 329
ea68f460
JB
330void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
331{
332 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
333 int i;
334
335 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
336 struct iwl_txq *txq = &trans_pcie->txq[i];
337
d090f878 338 spin_lock_bh(&txq->lock);
ea68f460
JB
339 if (trans_pcie->txq[i].need_update) {
340 iwl_pcie_txq_inc_wr_ptr(trans, txq);
341 trans_pcie->txq[i].need_update = false;
342 }
d090f878 343 spin_unlock_bh(&txq->lock);
ea68f460 344 }
fd4abac5 345}
fd4abac5 346
f02831be 347static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
214d14d4
JB
348{
349 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
350
351 dma_addr_t addr = get_unaligned_le32(&tb->lo);
352 if (sizeof(dma_addr_t) > sizeof(u32))
353 addr |=
354 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
355
356 return addr;
357}
358
f02831be
EG
359static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
360 dma_addr_t addr, u16 len)
214d14d4
JB
361{
362 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
363 u16 hi_n_len = len << 4;
364
365 put_unaligned_le32(addr, &tb->lo);
366 if (sizeof(dma_addr_t) > sizeof(u32))
367 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
368
369 tb->hi_n_len = cpu_to_le16(hi_n_len);
370
371 tfd->num_tbs = idx + 1;
372}
373
f02831be 374static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
214d14d4
JB
375{
376 return tfd->num_tbs & 0x1f;
377}
378
f02831be 379static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
98891754
JB
380 struct iwl_cmd_meta *meta,
381 struct iwl_tfd *tfd)
214d14d4 382{
214d14d4
JB
383 int i;
384 int num_tbs;
385
214d14d4 386 /* Sanity check on number of chunks */
f02831be 387 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
214d14d4
JB
388
389 if (num_tbs >= IWL_NUM_OF_TBS) {
6d8f6eeb 390 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
214d14d4
JB
391 /* @todo issue fatal error, it is quite serious situation */
392 return;
393 }
394
38c0f334 395 /* first TB is never freed - it's the scratchbuf data */
214d14d4 396
206eea78
JB
397 for (i = 1; i < num_tbs; i++) {
398 if (meta->flags & BIT(i + CMD_TB_BITMAP_POS))
399 dma_unmap_page(trans->dev,
400 iwl_pcie_tfd_tb_get_addr(tfd, i),
401 iwl_pcie_tfd_tb_get_len(tfd, i),
402 DMA_TO_DEVICE);
403 else
404 dma_unmap_single(trans->dev,
405 iwl_pcie_tfd_tb_get_addr(tfd, i),
406 iwl_pcie_tfd_tb_get_len(tfd, i),
407 DMA_TO_DEVICE);
408 }
ebed633c 409 tfd->num_tbs = 0;
4ce7cc2b
JB
410}
411
990aa6d7
EG
412/*
413 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
6d8f6eeb 414 * @trans - transport private data
4ce7cc2b 415 * @txq - tx queue
ebed633c 416 * @dma_dir - the direction of the DMA mapping
4ce7cc2b
JB
417 *
418 * Does NOT advance any TFD circular buffer read/write indexes
419 * Does NOT free the TFD itself (which is within circular buffer)
420 */
98891754 421static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
4ce7cc2b
JB
422{
423 struct iwl_tfd *tfd_tmp = txq->tfds;
4ce7cc2b 424
83f32a4b
JB
425 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
426 * idx is bounded by n_window
427 */
ebed633c
EG
428 int rd_ptr = txq->q.read_ptr;
429 int idx = get_cmd_index(&txq->q, rd_ptr);
430
015c15e1
JB
431 lockdep_assert_held(&txq->lock);
432
83f32a4b
JB
433 /* We have only q->n_window txq->entries, but we use
434 * TFD_QUEUE_SIZE_MAX tfds
435 */
98891754 436 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
214d14d4
JB
437
438 /* free SKB */
bf8440e6 439 if (txq->entries) {
214d14d4
JB
440 struct sk_buff *skb;
441
ebed633c 442 skb = txq->entries[idx].skb;
214d14d4 443
909e9b23
EG
444 /* Can be called from irqs-disabled context
445 * If skb is not NULL, it means that the whole queue is being
446 * freed and that the queue is not empty - free the skb
447 */
214d14d4 448 if (skb) {
ed277c93 449 iwl_op_mode_free_skb(trans->op_mode, skb);
ebed633c 450 txq->entries[idx].skb = NULL;
214d14d4
JB
451 }
452 }
453}
454
f02831be 455static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
6d6e68f8 456 dma_addr_t addr, u16 len, bool reset)
214d14d4
JB
457{
458 struct iwl_queue *q;
459 struct iwl_tfd *tfd, *tfd_tmp;
460 u32 num_tbs;
461
462 q = &txq->q;
4ce7cc2b 463 tfd_tmp = txq->tfds;
214d14d4
JB
464 tfd = &tfd_tmp[q->write_ptr];
465
f02831be
EG
466 if (reset)
467 memset(tfd, 0, sizeof(*tfd));
468
469 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
470
471 /* Each TFD can point to a maximum 20 Tx buffers */
472 if (num_tbs >= IWL_NUM_OF_TBS) {
473 IWL_ERR(trans, "Error can not send more than %d chunks\n",
474 IWL_NUM_OF_TBS);
475 return -EINVAL;
476 }
477
1092b9bc
EP
478 if (WARN(addr & ~IWL_TX_DMA_MASK,
479 "Unaligned address = %llx\n", (unsigned long long)addr))
f02831be
EG
480 return -EINVAL;
481
f02831be
EG
482 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
483
206eea78 484 return num_tbs;
f02831be
EG
485}
486
487static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
488 struct iwl_txq *txq, int slots_num,
489 u32 txq_id)
490{
491 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
492 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
38c0f334 493 size_t scratchbuf_sz;
f02831be
EG
494 int i;
495
496 if (WARN_ON(txq->entries || txq->tfds))
497 return -EINVAL;
498
499 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
500 (unsigned long)txq);
501 txq->trans_pcie = trans_pcie;
502
503 txq->q.n_window = slots_num;
504
505 txq->entries = kcalloc(slots_num,
506 sizeof(struct iwl_pcie_txq_entry),
507 GFP_KERNEL);
508
509 if (!txq->entries)
510 goto error;
511
512 if (txq_id == trans_pcie->cmd_queue)
513 for (i = 0; i < slots_num; i++) {
514 txq->entries[i].cmd =
515 kmalloc(sizeof(struct iwl_device_cmd),
516 GFP_KERNEL);
517 if (!txq->entries[i].cmd)
518 goto error;
519 }
520
521 /* Circular buffer of transmit frame descriptors (TFDs),
522 * shared with device */
523 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
524 &txq->q.dma_addr, GFP_KERNEL);
d0320f75 525 if (!txq->tfds)
f02831be 526 goto error;
38c0f334
JB
527
528 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
529 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
530 sizeof(struct iwl_cmd_header) +
531 offsetof(struct iwl_tx_cmd, scratch));
532
533 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
534
535 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
536 &txq->scratchbufs_dma,
537 GFP_KERNEL);
538 if (!txq->scratchbufs)
539 goto err_free_tfds;
540
f02831be
EG
541 txq->q.id = txq_id;
542
543 return 0;
38c0f334
JB
544err_free_tfds:
545 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
f02831be
EG
546error:
547 if (txq->entries && txq_id == trans_pcie->cmd_queue)
548 for (i = 0; i < slots_num; i++)
549 kfree(txq->entries[i].cmd);
550 kfree(txq->entries);
551 txq->entries = NULL;
552
553 return -ENOMEM;
554
555}
556
557static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
558 int slots_num, u32 txq_id)
559{
560 int ret;
561
43aa616f 562 txq->need_update = false;
f02831be
EG
563
564 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
565 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
566 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
567
568 /* Initialize queue's high/low-water marks, and head/tail indexes */
83f32a4b 569 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
f02831be
EG
570 if (ret)
571 return ret;
572
573 spin_lock_init(&txq->lock);
3955525d 574 __skb_queue_head_init(&txq->overflow_q);
f02831be
EG
575
576 /*
577 * Tell nic where to find circular buffer of Tx Frame Descriptors for
578 * given Tx queue, and enable the DMA channel used for that queue.
579 * Circular buffer (TFD queue in DRAM) physical base address */
580 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
581 txq->q.dma_addr >> 8);
582
583 return 0;
584}
585
6eb5e529
EG
586static void iwl_pcie_free_tso_page(struct sk_buff *skb)
587{
588 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
589
590 if (info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]) {
591 struct page *page =
592 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA];
593
594 __free_page(page);
595 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = NULL;
596 }
597}
598
01d11cd1
SS
599static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
600{
601 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
602
603 lockdep_assert_held(&trans_pcie->reg_lock);
604
605 if (trans_pcie->ref_cmd_in_flight) {
606 trans_pcie->ref_cmd_in_flight = false;
607 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
608 iwl_trans_pcie_unref(trans);
609 }
610
611 if (!trans->cfg->base_params->apmg_wake_up_wa)
612 return;
613 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
614 return;
615
616 trans_pcie->cmd_hold_nic_awake = false;
617 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
618 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
619}
620
f02831be
EG
621/*
622 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
623 */
624static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
625{
626 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
627 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
628 struct iwl_queue *q = &txq->q;
f02831be 629
f02831be
EG
630 spin_lock_bh(&txq->lock);
631 while (q->write_ptr != q->read_ptr) {
b967613d
EG
632 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
633 txq_id, q->read_ptr);
6eb5e529
EG
634
635 if (txq_id != trans_pcie->cmd_queue) {
636 struct sk_buff *skb = txq->entries[q->read_ptr].skb;
637
638 if (WARN_ON_ONCE(!skb))
639 continue;
640
641 iwl_pcie_free_tso_page(skb);
642 }
98891754 643 iwl_pcie_txq_free_tfd(trans, txq);
83f32a4b 644 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
01d11cd1
SS
645
646 if (q->read_ptr == q->write_ptr) {
647 unsigned long flags;
648
649 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
650 if (txq_id != trans_pcie->cmd_queue) {
651 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
652 q->id);
653 iwl_trans_pcie_unref(trans);
654 } else {
655 iwl_pcie_clear_cmd_in_flight(trans);
656 }
657 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
658 }
f02831be 659 }
b967613d 660 txq->active = false;
3955525d
EG
661
662 while (!skb_queue_empty(&txq->overflow_q)) {
663 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
664
665 iwl_op_mode_free_skb(trans->op_mode, skb);
666 }
667
f02831be 668 spin_unlock_bh(&txq->lock);
8a487b1a
EG
669
670 /* just in case - this queue may have been stopped */
671 iwl_wake_queue(trans, txq);
f02831be
EG
672}
673
674/*
675 * iwl_pcie_txq_free - Deallocate DMA queue.
676 * @txq: Transmit queue to deallocate.
677 *
678 * Empty queue by removing and destroying all BD's.
679 * Free all buffers.
680 * 0-fill, but do not free "txq" descriptor structure.
681 */
682static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
683{
684 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
685 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
686 struct device *dev = trans->dev;
687 int i;
688
689 if (WARN_ON(!txq))
690 return;
691
692 iwl_pcie_txq_unmap(trans, txq_id);
693
694 /* De-alloc array of command/tx buffers */
695 if (txq_id == trans_pcie->cmd_queue)
696 for (i = 0; i < txq->q.n_window; i++) {
5d4185ae
JB
697 kzfree(txq->entries[i].cmd);
698 kzfree(txq->entries[i].free_buf);
f02831be
EG
699 }
700
701 /* De-alloc circular buffer of TFDs */
83f32a4b
JB
702 if (txq->tfds) {
703 dma_free_coherent(dev,
704 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
705 txq->tfds, txq->q.dma_addr);
d21fa2da 706 txq->q.dma_addr = 0;
83f32a4b 707 txq->tfds = NULL;
38c0f334
JB
708
709 dma_free_coherent(dev,
710 sizeof(*txq->scratchbufs) * txq->q.n_window,
711 txq->scratchbufs, txq->scratchbufs_dma);
f02831be
EG
712 }
713
714 kfree(txq->entries);
715 txq->entries = NULL;
716
717 del_timer_sync(&txq->stuck_timer);
718
719 /* 0-fill queue descriptor structure */
720 memset(txq, 0, sizeof(*txq));
721}
722
f02831be
EG
723void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
724{
725 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
22dc3c95 726 int nq = trans->cfg->base_params->num_of_queues;
f02831be
EG
727 int chan;
728 u32 reg_val;
22dc3c95
JB
729 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
730 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
f02831be
EG
731
732 /* make sure all queue are not stopped/used */
733 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
734 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
735
736 trans_pcie->scd_base_addr =
737 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
738
739 WARN_ON(scd_base_addr != 0 &&
740 scd_base_addr != trans_pcie->scd_base_addr);
741
22dc3c95
JB
742 /* reset context data, TX status and translation data */
743 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
744 SCD_CONTEXT_MEM_LOWER_BOUND,
745 NULL, clear_dwords);
f02831be
EG
746
747 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
748 trans_pcie->scd_bc_tbls.dma >> 10);
749
750 /* The chain extension of the SCD doesn't work well. This feature is
751 * enabled by default by the HW, so we need to disable it manually.
752 */
e03bbb62
EG
753 if (trans->cfg->base_params->scd_chain_ext_wa)
754 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
f02831be
EG
755
756 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
4cf677fd
EG
757 trans_pcie->cmd_fifo,
758 trans_pcie->cmd_q_wdg_timeout);
f02831be
EG
759
760 /* Activate all Tx DMA/FIFO channels */
680073b7 761 iwl_scd_activate_fifos(trans);
f02831be
EG
762
763 /* Enable DMA channel */
764 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
765 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
766 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
767 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
768
769 /* Update FH chicken bits */
770 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
771 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
772 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
773
774 /* Enable L1-Active */
3073d8c0
EH
775 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
776 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
777 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
f02831be
EG
778}
779
ddaf5a5b
JB
780void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
781{
782 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
783 int txq_id;
784
785 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
786 txq_id++) {
787 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
788
789 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
790 txq->q.dma_addr >> 8);
791 iwl_pcie_txq_unmap(trans, txq_id);
792 txq->q.read_ptr = 0;
793 txq->q.write_ptr = 0;
794 }
795
796 /* Tell NIC where to find the "keep warm" buffer */
797 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
798 trans_pcie->kw.dma >> 4);
799
cd8f4384
EG
800 /*
801 * Send 0 as the scd_base_addr since the device may have be reset
802 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
803 * contain garbage.
804 */
805 iwl_pcie_tx_start(trans, 0);
ddaf5a5b
JB
806}
807
36277234
EG
808static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
809{
810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
811 unsigned long flags;
812 int ch, ret;
813 u32 mask = 0;
814
815 spin_lock(&trans_pcie->irq_lock);
816
23ba9340 817 if (!iwl_trans_grab_nic_access(trans, &flags))
36277234
EG
818 goto out;
819
820 /* Stop each Tx DMA channel */
821 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
822 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
823 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
824 }
825
826 /* Wait for DMA channels to be idle */
827 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
828 if (ret < 0)
829 IWL_ERR(trans,
830 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
831 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
832
833 iwl_trans_release_nic_access(trans, &flags);
834
835out:
836 spin_unlock(&trans_pcie->irq_lock);
837}
838
f02831be
EG
839/*
840 * iwl_pcie_tx_stop - Stop all Tx DMA channels
841 */
842int iwl_pcie_tx_stop(struct iwl_trans *trans)
843{
844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
36277234 845 int txq_id;
f02831be
EG
846
847 /* Turn off all Tx DMA fifos */
680073b7 848 iwl_scd_deactivate_fifos(trans);
f02831be 849
36277234
EG
850 /* Turn off all Tx DMA channels */
851 iwl_pcie_tx_stop_fh(trans);
f02831be 852
fba1c627
EG
853 /*
854 * This function can be called before the op_mode disabled the
855 * queues. This happens when we have an rfkill interrupt.
856 * Since we stop Tx altogether - mark the queues as stopped.
857 */
858 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
859 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
860
861 /* This can happen: start_hw, stop_device */
862 if (!trans_pcie->txq)
f02831be 863 return 0;
f02831be
EG
864
865 /* Unmap DMA from host system and free skb's */
866 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
867 txq_id++)
868 iwl_pcie_txq_unmap(trans, txq_id);
869
870 return 0;
871}
872
873/*
874 * iwl_trans_tx_free - Free TXQ Context
875 *
876 * Destroy all TX DMA queues and structures
877 */
878void iwl_pcie_tx_free(struct iwl_trans *trans)
879{
880 int txq_id;
881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
882
883 /* Tx queues */
884 if (trans_pcie->txq) {
885 for (txq_id = 0;
886 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
887 iwl_pcie_txq_free(trans, txq_id);
888 }
889
890 kfree(trans_pcie->txq);
891 trans_pcie->txq = NULL;
892
893 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
894
895 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
896}
897
898/*
899 * iwl_pcie_tx_alloc - allocate TX context
900 * Allocate all Tx DMA structures and initialize them
901 */
902static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
903{
904 int ret;
905 int txq_id, slots_num;
906 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
907
908 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
909 sizeof(struct iwlagn_scd_bc_tbl);
910
911 /*It is not allowed to alloc twice, so warn when this happens.
912 * We cannot rely on the previous allocation, so free and fail */
913 if (WARN_ON(trans_pcie->txq)) {
914 ret = -EINVAL;
915 goto error;
916 }
917
918 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
919 scd_bc_tbls_size);
920 if (ret) {
921 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
922 goto error;
923 }
924
925 /* Alloc keep-warm buffer */
926 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
927 if (ret) {
928 IWL_ERR(trans, "Keep Warm allocation failed\n");
929 goto error;
930 }
931
932 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
933 sizeof(struct iwl_txq), GFP_KERNEL);
934 if (!trans_pcie->txq) {
935 IWL_ERR(trans, "Not enough memory for txq\n");
2ab9ba0f 936 ret = -ENOMEM;
f02831be
EG
937 goto error;
938 }
939
940 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
941 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
942 txq_id++) {
943 slots_num = (txq_id == trans_pcie->cmd_queue) ?
944 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
945 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
946 slots_num, txq_id);
947 if (ret) {
948 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
949 goto error;
950 }
951 }
952
953 return 0;
954
955error:
956 iwl_pcie_tx_free(trans);
957
958 return ret;
959}
960int iwl_pcie_tx_init(struct iwl_trans *trans)
961{
962 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
963 int ret;
964 int txq_id, slots_num;
f02831be
EG
965 bool alloc = false;
966
967 if (!trans_pcie->txq) {
968 ret = iwl_pcie_tx_alloc(trans);
969 if (ret)
970 goto error;
971 alloc = true;
972 }
973
7b70bd63 974 spin_lock(&trans_pcie->irq_lock);
f02831be
EG
975
976 /* Turn off all Tx DMA fifos */
680073b7 977 iwl_scd_deactivate_fifos(trans);
f02831be
EG
978
979 /* Tell NIC where to find the "keep warm" buffer */
980 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
981 trans_pcie->kw.dma >> 4);
982
7b70bd63 983 spin_unlock(&trans_pcie->irq_lock);
f02831be
EG
984
985 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
986 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
987 txq_id++) {
988 slots_num = (txq_id == trans_pcie->cmd_queue) ?
989 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
990 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
991 slots_num, txq_id);
992 if (ret) {
993 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
994 goto error;
995 }
996 }
997
94ce9e5e 998 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
cb6bb128
EG
999 if (trans->cfg->base_params->num_of_queues > 20)
1000 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1001 SCD_GP_CTRL_ENABLE_31_QUEUES);
1002
f02831be
EG
1003 return 0;
1004error:
1005 /*Upon error, free only if we allocated something */
1006 if (alloc)
1007 iwl_pcie_tx_free(trans);
1008 return ret;
1009}
1010
4cf677fd 1011static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
f02831be 1012{
e0b8d405
EG
1013 lockdep_assert_held(&txq->lock);
1014
4cf677fd 1015 if (!txq->wd_timeout)
f02831be
EG
1016 return;
1017
e0b8d405
EG
1018 /*
1019 * station is asleep and we send data - that must
1020 * be uAPSD or PS-Poll. Don't rearm the timer.
1021 */
1022 if (txq->frozen)
1023 return;
1024
f02831be
EG
1025 /*
1026 * if empty delete timer, otherwise move timer forward
1027 * since we're making progress on this queue
1028 */
1029 if (txq->q.read_ptr == txq->q.write_ptr)
1030 del_timer(&txq->stuck_timer);
1031 else
4cf677fd 1032 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
f02831be
EG
1033}
1034
1035/* Frees buffers until index _not_ inclusive */
f6d497cd
EG
1036void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1037 struct sk_buff_head *skbs)
f02831be
EG
1038{
1039 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1040 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
83f32a4b 1041 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
f02831be
EG
1042 struct iwl_queue *q = &txq->q;
1043 int last_to_free;
f02831be
EG
1044
1045 /* This function is not meant to release cmd queue*/
1046 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
f6d497cd 1047 return;
214d14d4 1048
2bfb5092 1049 spin_lock_bh(&txq->lock);
f6d497cd 1050
b967613d
EG
1051 if (!txq->active) {
1052 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1053 txq_id, ssn);
1054 goto out;
1055 }
1056
f6d497cd
EG
1057 if (txq->q.read_ptr == tfd_num)
1058 goto out;
1059
1060 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1061 txq_id, txq->q.read_ptr, tfd_num, ssn);
214d14d4 1062
f02831be
EG
1063 /*Since we free until index _not_ inclusive, the one before index is
1064 * the last we will free. This one must be used */
83f32a4b 1065 last_to_free = iwl_queue_dec_wrap(tfd_num);
f02831be 1066
6ca6ebc1 1067 if (!iwl_queue_used(q, last_to_free)) {
f02831be
EG
1068 IWL_ERR(trans,
1069 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
83f32a4b 1070 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
f02831be 1071 q->write_ptr, q->read_ptr);
f6d497cd 1072 goto out;
214d14d4
JB
1073 }
1074
f02831be 1075 if (WARN_ON(!skb_queue_empty(skbs)))
f6d497cd 1076 goto out;
214d14d4 1077
f02831be 1078 for (;
f6d497cd 1079 q->read_ptr != tfd_num;
83f32a4b 1080 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
6eb5e529 1081 struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb;
214d14d4 1082
6eb5e529 1083 if (WARN_ON_ONCE(!skb))
f02831be 1084 continue;
214d14d4 1085
6eb5e529
EG
1086 iwl_pcie_free_tso_page(skb);
1087
1088 __skb_queue_tail(skbs, skb);
214d14d4 1089
f02831be 1090 txq->entries[txq->q.read_ptr].skb = NULL;
fd4abac5 1091
f02831be 1092 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
fd4abac5 1093
98891754 1094 iwl_pcie_txq_free_tfd(trans, txq);
f02831be 1095 }
fd4abac5 1096
4cf677fd 1097 iwl_pcie_txq_progress(txq);
f02831be 1098
3955525d
EG
1099 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1100 test_bit(txq_id, trans_pcie->queue_stopped)) {
685b346c 1101 struct sk_buff_head overflow_skbs;
3955525d 1102
685b346c
EG
1103 __skb_queue_head_init(&overflow_skbs);
1104 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
3955525d
EG
1105
1106 /*
1107 * This is tricky: we are in reclaim path which is non
1108 * re-entrant, so noone will try to take the access the
1109 * txq data from that path. We stopped tx, so we can't
1110 * have tx as well. Bottom line, we can unlock and re-lock
1111 * later.
1112 */
1113 spin_unlock_bh(&txq->lock);
1114
685b346c
EG
1115 while (!skb_queue_empty(&overflow_skbs)) {
1116 struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
3955525d
EG
1117 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1118 u8 dev_cmd_idx = IWL_TRANS_FIRST_DRIVER_DATA + 1;
1119 struct iwl_device_cmd *dev_cmd =
1120 info->driver_data[dev_cmd_idx];
1121
1122 /*
1123 * Note that we can very well be overflowing again.
1124 * In that case, iwl_queue_space will be small again
1125 * and we won't wake mac80211's queue.
1126 */
1127 iwl_trans_pcie_tx(trans, skb, dev_cmd, txq_id);
1128 }
1129 spin_lock_bh(&txq->lock);
1130
1131 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1132 iwl_wake_queue(trans, txq);
1133 }
7616f334
EP
1134
1135 if (q->read_ptr == q->write_ptr) {
1136 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1137 iwl_trans_pcie_unref(trans);
1138 }
1139
f6d497cd 1140out:
2bfb5092 1141 spin_unlock_bh(&txq->lock);
1053d35f
RR
1142}
1143
7616f334
EP
1144static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1145 const struct iwl_host_cmd *cmd)
804d4c5a
EP
1146{
1147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1148 int ret;
1149
1150 lockdep_assert_held(&trans_pcie->reg_lock);
1151
7616f334
EP
1152 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1153 !trans_pcie->ref_cmd_in_flight) {
1154 trans_pcie->ref_cmd_in_flight = true;
1155 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1156 iwl_trans_pcie_ref(trans);
1157 }
1158
804d4c5a
EP
1159 /*
1160 * wake up the NIC to make sure that the firmware will see the host
1161 * command - we will let the NIC sleep once all the host commands
1162 * returned. This needs to be done only on NICs that have
1163 * apmg_wake_up_wa set.
1164 */
fc8a350d
IP
1165 if (trans->cfg->base_params->apmg_wake_up_wa &&
1166 !trans_pcie->cmd_hold_nic_awake) {
804d4c5a
EP
1167 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1168 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
804d4c5a
EP
1169
1170 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1171 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1172 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1173 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1174 15000);
1175 if (ret < 0) {
1176 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1177 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
804d4c5a
EP
1178 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1179 return -EIO;
1180 }
fc8a350d 1181 trans_pcie->cmd_hold_nic_awake = true;
804d4c5a
EP
1182 }
1183
1184 return 0;
1185}
1186
f02831be
EG
1187/*
1188 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1189 *
1190 * When FW advances 'R' index, all entries between old and new 'R' index
1191 * need to be reclaimed. As result, some free space forms. If there is
1192 * enough free space (> low mark), wake the stack that feeds us.
1193 */
1194static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
48d42c42 1195{
f02831be
EG
1196 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1197 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1198 struct iwl_queue *q = &txq->q;
b9439491 1199 unsigned long flags;
f02831be 1200 int nfreed = 0;
48d42c42 1201
f02831be 1202 lockdep_assert_held(&txq->lock);
48d42c42 1203
83f32a4b 1204 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
f02831be
EG
1205 IWL_ERR(trans,
1206 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
83f32a4b 1207 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
f02831be
EG
1208 q->write_ptr, q->read_ptr);
1209 return;
1210 }
48d42c42 1211
83f32a4b
JB
1212 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1213 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
48d42c42 1214
f02831be
EG
1215 if (nfreed++ > 0) {
1216 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1217 idx, q->write_ptr, q->read_ptr);
4c9706dc 1218 iwl_force_nmi(trans);
f02831be
EG
1219 }
1220 }
1221
804d4c5a 1222 if (q->read_ptr == q->write_ptr) {
b9439491 1223 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
804d4c5a 1224 iwl_pcie_clear_cmd_in_flight(trans);
b9439491
EG
1225 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1226 }
1227
4cf677fd 1228 iwl_pcie_txq_progress(txq);
48d42c42
EG
1229}
1230
f02831be 1231static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1ce8658c 1232 u16 txq_id)
48d42c42 1233{
20d3b647 1234 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
48d42c42
EG
1235 u32 tbl_dw_addr;
1236 u32 tbl_dw;
1237 u16 scd_q2ratid;
1238
1239 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1240
105183b1 1241 tbl_dw_addr = trans_pcie->scd_base_addr +
48d42c42
EG
1242 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1243
4fd442db 1244 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
48d42c42
EG
1245
1246 if (txq_id & 0x1)
1247 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1248 else
1249 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1250
4fd442db 1251 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
48d42c42
EG
1252
1253 return 0;
1254}
1255
bd5f6a34
EG
1256/* Receiver address (actually, Rx station's index into station table),
1257 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1258#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1259
fea7795f 1260void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
4cf677fd
EG
1261 const struct iwl_trans_txq_scd_cfg *cfg,
1262 unsigned int wdg_timeout)
48d42c42 1263{
9eae88fa 1264 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4cf677fd 1265 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
d4578ea8 1266 int fifo = -1;
4beaf6c2 1267
9eae88fa
JB
1268 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1269 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
48d42c42 1270
4cf677fd
EG
1271 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1272
d4578ea8
JB
1273 if (cfg) {
1274 fifo = cfg->fifo;
48d42c42 1275
002a9e26 1276 /* Disable the scheduler prior configuring the cmd queue */
3a736bcb
EG
1277 if (txq_id == trans_pcie->cmd_queue &&
1278 trans_pcie->scd_set_active)
002a9e26
AA
1279 iwl_scd_enable_set_active(trans, 0);
1280
d4578ea8
JB
1281 /* Stop this Tx queue before configuring it */
1282 iwl_scd_txq_set_inactive(trans, txq_id);
4beaf6c2 1283
d4578ea8
JB
1284 /* Set this queue as a chain-building queue unless it is CMD */
1285 if (txq_id != trans_pcie->cmd_queue)
1286 iwl_scd_txq_set_chain(trans, txq_id);
48d42c42 1287
64ba8930 1288 if (cfg->aggregate) {
d4578ea8 1289 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
48d42c42 1290
d4578ea8
JB
1291 /* Map receiver-address / traffic-ID to this queue */
1292 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
f4772520 1293
d4578ea8
JB
1294 /* enable aggregations for the queue */
1295 iwl_scd_txq_enable_agg(trans, txq_id);
4cf677fd 1296 txq->ampdu = true;
d4578ea8
JB
1297 } else {
1298 /*
1299 * disable aggregations for the queue, this will also
1300 * make the ra_tid mapping configuration irrelevant
1301 * since it is now a non-AGG queue.
1302 */
1303 iwl_scd_txq_disable_agg(trans, txq_id);
1304
4cf677fd 1305 ssn = txq->q.read_ptr;
d4578ea8 1306 }
4beaf6c2 1307 }
48d42c42
EG
1308
1309 /* Place first TFD at index corresponding to start sequence number.
1310 * Assumes that ssn_idx is valid (!= 0xFFF) */
4cf677fd
EG
1311 txq->q.read_ptr = (ssn & 0xff);
1312 txq->q.write_ptr = (ssn & 0xff);
0294d9ee
EG
1313 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1314 (ssn & 0xff) | (txq_id << 8));
1ce8658c 1315
d4578ea8
JB
1316 if (cfg) {
1317 u8 frame_limit = cfg->frame_limit;
48d42c42 1318
d4578ea8
JB
1319 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1320
1321 /* Set up Tx window size and frame limit for this queue */
1322 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1323 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1324 iwl_trans_write_mem32(trans,
1325 trans_pcie->scd_base_addr +
9eae88fa
JB
1326 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1327 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
d4578ea8 1328 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
9eae88fa 1329 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
d4578ea8
JB
1330 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1331
1332 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1333 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1334 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1335 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1336 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1337 SCD_QUEUE_STTS_REG_MSK);
002a9e26
AA
1338
1339 /* enable the scheduler for this queue (only) */
3a736bcb
EG
1340 if (txq_id == trans_pcie->cmd_queue &&
1341 trans_pcie->scd_set_active)
002a9e26 1342 iwl_scd_enable_set_active(trans, BIT(txq_id));
0294d9ee
EG
1343
1344 IWL_DEBUG_TX_QUEUES(trans,
1345 "Activate queue %d on FIFO %d WrPtr: %d\n",
1346 txq_id, fifo, ssn & 0xff);
1347 } else {
1348 IWL_DEBUG_TX_QUEUES(trans,
1349 "Activate queue %d WrPtr: %d\n",
1350 txq_id, ssn & 0xff);
d4578ea8
JB
1351 }
1352
4cf677fd 1353 txq->active = true;
4beaf6c2
EG
1354}
1355
d4578ea8
JB
1356void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1357 bool configure_scd)
288712a6 1358{
8ad71bef 1359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
986ea6c9
EG
1360 u32 stts_addr = trans_pcie->scd_base_addr +
1361 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1362 static const u32 zero_val[4] = {};
288712a6 1363
e0b8d405
EG
1364 trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1365 trans_pcie->txq[txq_id].frozen = false;
1366
fba1c627
EG
1367 /*
1368 * Upon HW Rfkill - we stop the device, and then stop the queues
1369 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1370 * allow the op_mode to call txq_disable after it already called
1371 * stop_device.
1372 */
9eae88fa 1373 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
fba1c627
EG
1374 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1375 "queue %d not used", txq_id);
9eae88fa 1376 return;
48d42c42
EG
1377 }
1378
d4578ea8
JB
1379 if (configure_scd) {
1380 iwl_scd_txq_set_inactive(trans, txq_id);
ac928f8d 1381
d4578ea8
JB
1382 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1383 ARRAY_SIZE(zero_val));
1384 }
986ea6c9 1385
990aa6d7 1386 iwl_pcie_txq_unmap(trans, txq_id);
68972c46 1387 trans_pcie->txq[txq_id].ampdu = false;
6c3fd3f0 1388
1ce8658c 1389 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
48d42c42
EG
1390}
1391
fd4abac5
TW
1392/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1393
990aa6d7 1394/*
f02831be 1395 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
fd4abac5 1396 * @priv: device private data point
e89044d7 1397 * @cmd: a pointer to the ucode command structure
fd4abac5 1398 *
e89044d7
EP
1399 * The function returns < 0 values to indicate the operation
1400 * failed. On success, it returns the index (>= 0) of command in the
fd4abac5
TW
1401 * command queue.
1402 */
f02831be
EG
1403static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1404 struct iwl_host_cmd *cmd)
fd4abac5 1405{
8ad71bef 1406 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1407 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
fd4abac5 1408 struct iwl_queue *q = &txq->q;
c2acea8e
JB
1409 struct iwl_device_cmd *out_cmd;
1410 struct iwl_cmd_meta *out_meta;
b9439491 1411 unsigned long flags;
f4feb8ac 1412 void *dup_buf = NULL;
fd4abac5 1413 dma_addr_t phys_addr;
f4feb8ac 1414 int idx;
38c0f334 1415 u16 copy_size, cmd_size, scratch_size;
4ce7cc2b 1416 bool had_nocopy = false;
ab02165c 1417 u8 group_id = iwl_cmd_groupid(cmd->id);
b9439491 1418 int i, ret;
96791422 1419 u32 cmd_pos;
1afbfb60
JB
1420 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1421 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
fd4abac5 1422
88742c9e
JB
1423 if (WARN(!trans_pcie->wide_cmd_header &&
1424 group_id > IWL_ALWAYS_LONG_GROUP,
ab02165c
AE
1425 "unsupported wide command %#x\n", cmd->id))
1426 return -EINVAL;
1427
1428 if (group_id != 0) {
1429 copy_size = sizeof(struct iwl_cmd_header_wide);
1430 cmd_size = sizeof(struct iwl_cmd_header_wide);
1431 } else {
1432 copy_size = sizeof(struct iwl_cmd_header);
1433 cmd_size = sizeof(struct iwl_cmd_header);
1434 }
4ce7cc2b
JB
1435
1436 /* need one for the header if the first is NOCOPY */
1afbfb60 1437 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
4ce7cc2b 1438
1afbfb60 1439 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
8a964f44
JB
1440 cmddata[i] = cmd->data[i];
1441 cmdlen[i] = cmd->len[i];
1442
4ce7cc2b
JB
1443 if (!cmd->len[i])
1444 continue;
8a964f44 1445
38c0f334
JB
1446 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1447 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1448 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
8a964f44
JB
1449
1450 if (copy > cmdlen[i])
1451 copy = cmdlen[i];
1452 cmdlen[i] -= copy;
1453 cmddata[i] += copy;
1454 copy_size += copy;
1455 }
1456
4ce7cc2b
JB
1457 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1458 had_nocopy = true;
f4feb8ac
JB
1459 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1460 idx = -EINVAL;
1461 goto free_dup_buf;
1462 }
1463 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1464 /*
1465 * This is also a chunk that isn't copied
1466 * to the static buffer so set had_nocopy.
1467 */
1468 had_nocopy = true;
1469
1470 /* only allowed once */
1471 if (WARN_ON(dup_buf)) {
1472 idx = -EINVAL;
1473 goto free_dup_buf;
1474 }
1475
8a964f44 1476 dup_buf = kmemdup(cmddata[i], cmdlen[i],
f4feb8ac
JB
1477 GFP_ATOMIC);
1478 if (!dup_buf)
1479 return -ENOMEM;
4ce7cc2b
JB
1480 } else {
1481 /* NOCOPY must not be followed by normal! */
f4feb8ac
JB
1482 if (WARN_ON(had_nocopy)) {
1483 idx = -EINVAL;
1484 goto free_dup_buf;
1485 }
8a964f44 1486 copy_size += cmdlen[i];
4ce7cc2b
JB
1487 }
1488 cmd_size += cmd->len[i];
1489 }
fd4abac5 1490
3e41ace5
JB
1491 /*
1492 * If any of the command structures end up being larger than
4ce7cc2b
JB
1493 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1494 * allocated into separate TFDs, then we will need to
1495 * increase the size of the buffers.
3e41ace5 1496 */
2a79e45e
JB
1497 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1498 "Command %s (%#x) is too large (%d bytes)\n",
39bdb17e
SD
1499 iwl_get_cmd_string(trans, cmd->id),
1500 cmd->id, copy_size)) {
f4feb8ac
JB
1501 idx = -EINVAL;
1502 goto free_dup_buf;
1503 }
fd4abac5 1504
015c15e1 1505 spin_lock_bh(&txq->lock);
3598e177 1506
c2acea8e 1507 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
015c15e1 1508 spin_unlock_bh(&txq->lock);
3598e177 1509
6d8f6eeb 1510 IWL_ERR(trans, "No space in command queue\n");
0e781842 1511 iwl_op_mode_cmd_queue_full(trans->op_mode);
f4feb8ac
JB
1512 idx = -ENOSPC;
1513 goto free_dup_buf;
fd4abac5
TW
1514 }
1515
4ce7cc2b 1516 idx = get_cmd_index(q, q->write_ptr);
bf8440e6
JB
1517 out_cmd = txq->entries[idx].cmd;
1518 out_meta = &txq->entries[idx].meta;
c2acea8e 1519
8ce73f3a 1520 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
c2acea8e
JB
1521 if (cmd->flags & CMD_WANT_SKB)
1522 out_meta->source = cmd;
fd4abac5 1523
4ce7cc2b 1524 /* set up the header */
ab02165c
AE
1525 if (group_id != 0) {
1526 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1527 out_cmd->hdr_wide.group_id = group_id;
1528 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1529 out_cmd->hdr_wide.length =
1530 cpu_to_le16(cmd_size -
1531 sizeof(struct iwl_cmd_header_wide));
1532 out_cmd->hdr_wide.reserved = 0;
1533 out_cmd->hdr_wide.sequence =
1534 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1535 INDEX_TO_SEQ(q->write_ptr));
1536
1537 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1538 copy_size = sizeof(struct iwl_cmd_header_wide);
1539 } else {
1540 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1541 out_cmd->hdr.sequence =
1542 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1543 INDEX_TO_SEQ(q->write_ptr));
1544 out_cmd->hdr.group_id = 0;
1545
1546 cmd_pos = sizeof(struct iwl_cmd_header);
1547 copy_size = sizeof(struct iwl_cmd_header);
1548 }
4ce7cc2b
JB
1549
1550 /* and copy the data that needs to be copied */
1afbfb60 1551 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
4d075007 1552 int copy;
8a964f44 1553
cc904c71 1554 if (!cmd->len[i])
4ce7cc2b 1555 continue;
8a964f44 1556
8a964f44
JB
1557 /* copy everything if not nocopy/dup */
1558 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
4d075007 1559 IWL_HCMD_DFL_DUP))) {
8a964f44
JB
1560 copy = cmd->len[i];
1561
8a964f44
JB
1562 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1563 cmd_pos += copy;
1564 copy_size += copy;
4d075007
JB
1565 continue;
1566 }
1567
1568 /*
1569 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1570 * in total (for the scratchbuf handling), but copy up to what
1571 * we can fit into the payload for debug dump purposes.
1572 */
1573 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1574
1575 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1576 cmd_pos += copy;
1577
1578 /* However, treat copy_size the proper way, we need it below */
1579 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1580 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1581
1582 if (copy > cmd->len[i])
1583 copy = cmd->len[i];
1584 copy_size += copy;
8a964f44 1585 }
96791422
EG
1586 }
1587
d9fb6465 1588 IWL_DEBUG_HC(trans,
ab02165c 1589 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
39bdb17e 1590 iwl_get_cmd_string(trans, cmd->id),
ab02165c
AE
1591 group_id, out_cmd->hdr.cmd,
1592 le16_to_cpu(out_cmd->hdr.sequence),
20d3b647 1593 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
4ce7cc2b 1594
38c0f334
JB
1595 /* start the TFD with the scratchbuf */
1596 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1597 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1598 iwl_pcie_txq_build_tfd(trans, txq,
1599 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
6d6e68f8 1600 scratch_size, true);
38c0f334
JB
1601
1602 /* map first command fragment, if any remains */
1603 if (copy_size > scratch_size) {
1604 phys_addr = dma_map_single(trans->dev,
1605 ((u8 *)&out_cmd->hdr) + scratch_size,
1606 copy_size - scratch_size,
1607 DMA_TO_DEVICE);
1608 if (dma_mapping_error(trans->dev, phys_addr)) {
1609 iwl_pcie_tfd_unmap(trans, out_meta,
1610 &txq->tfds[q->write_ptr]);
1611 idx = -ENOMEM;
1612 goto out;
1613 }
8a964f44 1614
38c0f334 1615 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
6d6e68f8 1616 copy_size - scratch_size, false);
2c46f72e
JB
1617 }
1618
8a964f44 1619 /* map the remaining (adjusted) nocopy/dup fragments */
1afbfb60 1620 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
8a964f44 1621 const void *data = cmddata[i];
f4feb8ac 1622
8a964f44 1623 if (!cmdlen[i])
4ce7cc2b 1624 continue;
f4feb8ac
JB
1625 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1626 IWL_HCMD_DFL_DUP)))
4ce7cc2b 1627 continue;
f4feb8ac
JB
1628 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1629 data = dup_buf;
1630 phys_addr = dma_map_single(trans->dev, (void *)data,
98891754 1631 cmdlen[i], DMA_TO_DEVICE);
1042db2a 1632 if (dma_mapping_error(trans->dev, phys_addr)) {
f02831be 1633 iwl_pcie_tfd_unmap(trans, out_meta,
98891754 1634 &txq->tfds[q->write_ptr]);
4ce7cc2b
JB
1635 idx = -ENOMEM;
1636 goto out;
1637 }
1638
6d6e68f8 1639 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
4ce7cc2b 1640 }
df833b1d 1641
206eea78
JB
1642 BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS >
1643 sizeof(out_meta->flags) * BITS_PER_BYTE);
afaf6b57 1644 out_meta->flags = cmd->flags;
f4feb8ac 1645 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
5d4185ae 1646 kzfree(txq->entries[idx].free_buf);
f4feb8ac 1647 txq->entries[idx].free_buf = dup_buf;
2c46f72e 1648
ab02165c 1649 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
df833b1d 1650
7c5ba4a8 1651 /* start timer if queue currently empty */
4cf677fd
EG
1652 if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1653 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
7c5ba4a8 1654
b9439491 1655 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
7616f334 1656 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
804d4c5a
EP
1657 if (ret < 0) {
1658 idx = ret;
1659 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1660 goto out;
b9439491
EG
1661 }
1662
fd4abac5 1663 /* Increment and update queue's write index */
83f32a4b 1664 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
990aa6d7 1665 iwl_pcie_txq_inc_wr_ptr(trans, txq);
fd4abac5 1666
b9439491
EG
1667 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1668
2c46f72e 1669 out:
015c15e1 1670 spin_unlock_bh(&txq->lock);
f4feb8ac
JB
1671 free_dup_buf:
1672 if (idx < 0)
1673 kfree(dup_buf);
7bfedc59 1674 return idx;
fd4abac5
TW
1675}
1676
990aa6d7
EG
1677/*
1678 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
17b88929 1679 * @rxb: Rx buffer to reclaim
17b88929 1680 */
990aa6d7 1681void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
f7e6469f 1682 struct iwl_rx_cmd_buffer *rxb)
17b88929 1683{
2f301227 1684 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17b88929 1685 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
39bdb17e
SD
1686 u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id);
1687 u32 cmd_id;
17b88929
TW
1688 int txq_id = SEQ_TO_QUEUE(sequence);
1689 int index = SEQ_TO_INDEX(sequence);
17b88929 1690 int cmd_index;
c2acea8e
JB
1691 struct iwl_device_cmd *cmd;
1692 struct iwl_cmd_meta *meta;
8ad71bef 1693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1694 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
17b88929
TW
1695
1696 /* If a Tx command is being handled and it isn't in the actual
1697 * command queue then there a command routing bug has been introduced
1698 * in the queue management code. */
c6f600fc 1699 if (WARN(txq_id != trans_pcie->cmd_queue,
13bb9483 1700 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
20d3b647
JB
1701 txq_id, trans_pcie->cmd_queue, sequence,
1702 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1703 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
3e10caeb 1704 iwl_print_hex_error(trans, pkt, 32);
55d6a3cd 1705 return;
01ef9323 1706 }
17b88929 1707
2bfb5092 1708 spin_lock_bh(&txq->lock);
015c15e1 1709
4ce7cc2b 1710 cmd_index = get_cmd_index(&txq->q, index);
bf8440e6
JB
1711 cmd = txq->entries[cmd_index].cmd;
1712 meta = &txq->entries[cmd_index].meta;
39bdb17e 1713 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
17b88929 1714
98891754 1715 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
c33de625 1716
17b88929 1717 /* Input error checking is done when commands are added to queue. */
c2acea8e 1718 if (meta->flags & CMD_WANT_SKB) {
48a2d66f 1719 struct page *p = rxb_steal_page(rxb);
65b94a4a 1720
65b94a4a
JB
1721 meta->source->resp_pkt = pkt;
1722 meta->source->_rx_page_addr = (unsigned long)page_address(p);
b2cf410c 1723 meta->source->_rx_page_order = trans_pcie->rx_page_order;
247c61d6 1724 }
2624e96c 1725
dcbb4746
EG
1726 if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1727 iwl_op_mode_async_cb(trans->op_mode, cmd);
1728
f02831be 1729 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
17b88929 1730
c2acea8e 1731 if (!(meta->flags & CMD_ASYNC)) {
eb7ff77e 1732 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
05c89b91
WYG
1733 IWL_WARN(trans,
1734 "HCMD_ACTIVE already clear for command %s\n",
39bdb17e 1735 iwl_get_cmd_string(trans, cmd_id));
05c89b91 1736 }
eb7ff77e 1737 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
6d8f6eeb 1738 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
39bdb17e 1739 iwl_get_cmd_string(trans, cmd_id));
f946b529 1740 wake_up(&trans_pcie->wait_command_queue);
17b88929 1741 }
3598e177 1742
4cbb8e50
LC
1743 if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1744 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1745 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1746 set_bit(STATUS_TRANS_IDLE, &trans->status);
1747 wake_up(&trans_pcie->d0i3_waitq);
1748 }
1749
1750 if (meta->flags & CMD_WAKE_UP_TRANS) {
1751 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1752 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1753 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1754 wake_up(&trans_pcie->d0i3_waitq);
1755 }
1756
dd487449 1757 meta->flags = 0;
3598e177 1758
2bfb5092 1759 spin_unlock_bh(&txq->lock);
17b88929 1760}
253a634c 1761
9439eac7 1762#define HOST_COMPLETE_TIMEOUT (2 * HZ)
253a634c 1763
f02831be
EG
1764static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1765 struct iwl_host_cmd *cmd)
253a634c
EG
1766{
1767 int ret;
1768
1769 /* An asynchronous command can not expect an SKB to be set. */
1770 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1771 return -EINVAL;
1772
f02831be 1773 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
253a634c 1774 if (ret < 0) {
721c32f7 1775 IWL_ERR(trans,
b36b110c 1776 "Error sending %s: enqueue_hcmd failed: %d\n",
39bdb17e 1777 iwl_get_cmd_string(trans, cmd->id), ret);
253a634c
EG
1778 return ret;
1779 }
1780 return 0;
1781}
1782
f02831be
EG
1783static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1784 struct iwl_host_cmd *cmd)
253a634c 1785{
8ad71bef 1786 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
253a634c
EG
1787 int cmd_idx;
1788 int ret;
1789
6d8f6eeb 1790 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
39bdb17e 1791 iwl_get_cmd_string(trans, cmd->id));
253a634c 1792
eb7ff77e
AN
1793 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1794 &trans->status),
bcbb8c9c 1795 "Command %s: a command is already active!\n",
39bdb17e 1796 iwl_get_cmd_string(trans, cmd->id)))
2cc39c94 1797 return -EIO;
2cc39c94 1798
6d8f6eeb 1799 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
39bdb17e 1800 iwl_get_cmd_string(trans, cmd->id));
253a634c 1801
f02831be 1802 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
253a634c
EG
1803 if (cmd_idx < 0) {
1804 ret = cmd_idx;
eb7ff77e 1805 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
721c32f7 1806 IWL_ERR(trans,
b36b110c 1807 "Error sending %s: enqueue_hcmd failed: %d\n",
39bdb17e 1808 iwl_get_cmd_string(trans, cmd->id), ret);
253a634c
EG
1809 return ret;
1810 }
1811
b9439491
EG
1812 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1813 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1814 &trans->status),
1815 HOST_COMPLETE_TIMEOUT);
253a634c 1816 if (!ret) {
6dde8c48
JB
1817 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1818 struct iwl_queue *q = &txq->q;
d10630af 1819
6dde8c48 1820 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
39bdb17e 1821 iwl_get_cmd_string(trans, cmd->id),
6dde8c48 1822 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
253a634c 1823
6dde8c48
JB
1824 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1825 q->read_ptr, q->write_ptr);
d10630af 1826
eb7ff77e 1827 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
6dde8c48 1828 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
39bdb17e 1829 iwl_get_cmd_string(trans, cmd->id));
6dde8c48 1830 ret = -ETIMEDOUT;
42550a53 1831
4c9706dc 1832 iwl_force_nmi(trans);
2a988e98 1833 iwl_trans_fw_error(trans);
42550a53 1834
6dde8c48 1835 goto cancel;
253a634c
EG
1836 }
1837
eb7ff77e 1838 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
d18aa87f 1839 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
39bdb17e 1840 iwl_get_cmd_string(trans, cmd->id));
b656fa33 1841 dump_stack();
d18aa87f
JB
1842 ret = -EIO;
1843 goto cancel;
1844 }
1845
1094fa26 1846 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
eb7ff77e 1847 test_bit(STATUS_RFKILL, &trans->status)) {
f946b529
EG
1848 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1849 ret = -ERFKILL;
1850 goto cancel;
1851 }
1852
65b94a4a 1853 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
6d8f6eeb 1854 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
39bdb17e 1855 iwl_get_cmd_string(trans, cmd->id));
253a634c
EG
1856 ret = -EIO;
1857 goto cancel;
1858 }
1859
1860 return 0;
1861
1862cancel:
1863 if (cmd->flags & CMD_WANT_SKB) {
1864 /*
1865 * Cancel the CMD_WANT_SKB flag for the cmd in the
1866 * TX cmd queue. Otherwise in case the cmd comes
1867 * in later, it will possibly set an invalid
1868 * address (cmd->meta.source).
1869 */
bf8440e6
JB
1870 trans_pcie->txq[trans_pcie->cmd_queue].
1871 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
253a634c 1872 }
9cac4943 1873
65b94a4a
JB
1874 if (cmd->resp_pkt) {
1875 iwl_free_resp(cmd);
1876 cmd->resp_pkt = NULL;
253a634c
EG
1877 }
1878
1879 return ret;
1880}
1881
f02831be 1882int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
253a634c 1883{
4f59334b 1884 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
eb7ff77e 1885 test_bit(STATUS_RFKILL, &trans->status)) {
754d7d9e
EG
1886 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1887 cmd->id);
f946b529 1888 return -ERFKILL;
754d7d9e 1889 }
f946b529 1890
253a634c 1891 if (cmd->flags & CMD_ASYNC)
f02831be 1892 return iwl_pcie_send_hcmd_async(trans, cmd);
253a634c 1893
f946b529 1894 /* We still can fail on RFKILL that can be asserted while we wait */
f02831be 1895 return iwl_pcie_send_hcmd_sync(trans, cmd);
253a634c
EG
1896}
1897
3a0b2a42
EG
1898static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1899 struct iwl_txq *txq, u8 hdr_len,
1900 struct iwl_cmd_meta *out_meta,
1901 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1902{
1903 struct iwl_queue *q = &txq->q;
1904 u16 tb2_len;
1905 int i;
1906
1907 /*
1908 * Set up TFD's third entry to point directly to remainder
1909 * of skb's head, if any
1910 */
1911 tb2_len = skb_headlen(skb) - hdr_len;
1912
1913 if (tb2_len > 0) {
1914 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1915 skb->data + hdr_len,
1916 tb2_len, DMA_TO_DEVICE);
1917 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1918 iwl_pcie_tfd_unmap(trans, out_meta,
1919 &txq->tfds[q->write_ptr]);
1920 return -EINVAL;
1921 }
1922 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1923 }
1924
1925 /* set up the remaining entries to point to the data */
1926 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1927 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1928 dma_addr_t tb_phys;
1929 int tb_idx;
1930
1931 if (!skb_frag_size(frag))
1932 continue;
1933
1934 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1935 skb_frag_size(frag), DMA_TO_DEVICE);
1936
1937 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
1938 iwl_pcie_tfd_unmap(trans, out_meta,
1939 &txq->tfds[q->write_ptr]);
1940 return -EINVAL;
1941 }
1942 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1943 skb_frag_size(frag), false);
1944
1945 out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS);
1946 }
1947
1948 trace_iwlwifi_dev_tx(trans->dev, skb,
1949 &txq->tfds[txq->q.write_ptr],
1950 sizeof(struct iwl_tfd),
1951 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1952 skb->data + hdr_len, tb2_len);
1953 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1954 hdr_len, skb->len - hdr_len);
1955 return 0;
1956}
1957
6eb5e529
EG
1958#ifdef CONFIG_INET
1959static struct iwl_tso_hdr_page *
1960get_page_hdr(struct iwl_trans *trans, size_t len)
1961{
1962 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1963 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
1964
1965 if (!p->page)
1966 goto alloc;
1967
1968 /* enough room on this page */
1969 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
1970 return p;
1971
1972 /* We don't have enough room on this page, get a new one. */
1973 __free_page(p->page);
1974
1975alloc:
1976 p->page = alloc_page(GFP_ATOMIC);
1977 if (!p->page)
1978 return NULL;
1979 p->pos = page_address(p->page);
1980 return p;
1981}
1982
1983static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
1984 bool ipv6, unsigned int len)
1985{
1986 if (ipv6) {
1987 struct ipv6hdr *iphv6 = iph;
1988
1989 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
1990 len + tcph->doff * 4,
1991 IPPROTO_TCP, 0);
1992 } else {
1993 struct iphdr *iphv4 = iph;
1994
1995 ip_send_check(iphv4);
1996 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
1997 len + tcph->doff * 4,
1998 IPPROTO_TCP, 0);
1999 }
2000}
2001
2002static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2003 struct iwl_txq *txq, u8 hdr_len,
2004 struct iwl_cmd_meta *out_meta,
2005 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2006{
2007 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2008 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2009 struct ieee80211_hdr *hdr = (void *)skb->data;
2010 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2011 unsigned int mss = skb_shinfo(skb)->gso_size;
2012 struct iwl_queue *q = &txq->q;
2013 u16 length, iv_len, amsdu_pad;
2014 u8 *start_hdr;
2015 struct iwl_tso_hdr_page *hdr_page;
2016 int ret;
2017 struct tso_t tso;
2018
2019 /* if the packet is protected, then it must be CCMP or GCMP */
2020 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2021 iv_len = ieee80211_has_protected(hdr->frame_control) ?
2022 IEEE80211_CCMP_HDR_LEN : 0;
2023
2024 trace_iwlwifi_dev_tx(trans->dev, skb,
2025 &txq->tfds[txq->q.write_ptr],
2026 sizeof(struct iwl_tfd),
2027 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
2028 NULL, 0);
2029
2030 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2031 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2032 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2033 amsdu_pad = 0;
2034
2035 /* total amount of header we may need for this A-MSDU */
2036 hdr_room = DIV_ROUND_UP(total_len, mss) *
2037 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2038
2039 /* Our device supports 9 segments at most, it will fit in 1 page */
2040 hdr_page = get_page_hdr(trans, hdr_room);
2041 if (!hdr_page)
2042 return -ENOMEM;
2043
2044 get_page(hdr_page->page);
2045 start_hdr = hdr_page->pos;
2046 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = hdr_page->page;
2047 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2048 hdr_page->pos += iv_len;
2049
2050 /*
2051 * Pull the ieee80211 header + IV to be able to use TSO core,
2052 * we will restore it for the tx_status flow.
2053 */
2054 skb_pull(skb, hdr_len + iv_len);
2055
2056 tso_start(skb, &tso);
2057
2058 while (total_len) {
2059 /* this is the data left for this subframe */
2060 unsigned int data_left =
2061 min_t(unsigned int, mss, total_len);
2062 struct sk_buff *csum_skb = NULL;
2063 unsigned int hdr_tb_len;
2064 dma_addr_t hdr_tb_phys;
2065 struct tcphdr *tcph;
2066 u8 *iph;
2067
2068 total_len -= data_left;
2069
2070 memset(hdr_page->pos, 0, amsdu_pad);
2071 hdr_page->pos += amsdu_pad;
2072 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2073 data_left)) & 0x3;
2074 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2075 hdr_page->pos += ETH_ALEN;
2076 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2077 hdr_page->pos += ETH_ALEN;
2078
2079 length = snap_ip_tcp_hdrlen + data_left;
2080 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2081 hdr_page->pos += sizeof(length);
2082
2083 /*
2084 * This will copy the SNAP as well which will be considered
2085 * as MAC header.
2086 */
2087 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2088 iph = hdr_page->pos + 8;
2089 tcph = (void *)(iph + ip_hdrlen);
2090
2091 /* For testing on current hardware only */
2092 if (trans_pcie->sw_csum_tx) {
2093 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2094 GFP_ATOMIC);
2095 if (!csum_skb) {
2096 ret = -ENOMEM;
2097 goto out_unmap;
2098 }
2099
2100 iwl_compute_pseudo_hdr_csum(iph, tcph,
2101 skb->protocol ==
2102 htons(ETH_P_IPV6),
2103 data_left);
2104
2105 memcpy(skb_put(csum_skb, tcp_hdrlen(skb)),
2106 tcph, tcp_hdrlen(skb));
2107 skb_set_transport_header(csum_skb, 0);
2108 csum_skb->csum_start =
2109 (unsigned char *)tcp_hdr(csum_skb) -
2110 csum_skb->head;
2111 }
2112
2113 hdr_page->pos += snap_ip_tcp_hdrlen;
2114
2115 hdr_tb_len = hdr_page->pos - start_hdr;
2116 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2117 hdr_tb_len, DMA_TO_DEVICE);
2118 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2119 dev_kfree_skb(csum_skb);
2120 ret = -EINVAL;
2121 goto out_unmap;
2122 }
2123 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2124 hdr_tb_len, false);
2125 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2126 hdr_tb_len);
2127
2128 /* prepare the start_hdr for the next subframe */
2129 start_hdr = hdr_page->pos;
2130
2131 /* put the payload */
2132 while (data_left) {
2133 unsigned int size = min_t(unsigned int, tso.size,
2134 data_left);
2135 dma_addr_t tb_phys;
2136
2137 if (trans_pcie->sw_csum_tx)
2138 memcpy(skb_put(csum_skb, size), tso.data, size);
2139
2140 tb_phys = dma_map_single(trans->dev, tso.data,
2141 size, DMA_TO_DEVICE);
2142 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2143 dev_kfree_skb(csum_skb);
2144 ret = -EINVAL;
2145 goto out_unmap;
2146 }
2147
2148 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2149 size, false);
2150 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2151 size);
2152
2153 data_left -= size;
2154 tso_build_data(skb, &tso, size);
2155 }
2156
2157 /* For testing on early hardware only */
2158 if (trans_pcie->sw_csum_tx) {
2159 __wsum csum;
2160
2161 csum = skb_checksum(csum_skb,
2162 skb_checksum_start_offset(csum_skb),
2163 csum_skb->len -
2164 skb_checksum_start_offset(csum_skb),
2165 0);
2166 dev_kfree_skb(csum_skb);
2167 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2168 hdr_tb_len, DMA_TO_DEVICE);
2169 tcph->check = csum_fold(csum);
2170 dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2171 hdr_tb_len, DMA_TO_DEVICE);
2172 }
2173 }
2174
2175 /* re -add the WiFi header and IV */
2176 skb_push(skb, hdr_len + iv_len);
2177
2178 return 0;
2179
2180out_unmap:
2181 iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]);
2182 return ret;
2183}
2184#else /* CONFIG_INET */
2185static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2186 struct iwl_txq *txq, u8 hdr_len,
2187 struct iwl_cmd_meta *out_meta,
2188 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2189{
2190 /* No A-MSDU without CONFIG_INET */
2191 WARN_ON(1);
2192
2193 return -1;
2194}
2195#endif /* CONFIG_INET */
2196
f02831be
EG
2197int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2198 struct iwl_device_cmd *dev_cmd, int txq_id)
a0eaad71 2199{
8ad71bef 2200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
206eea78 2201 struct ieee80211_hdr *hdr;
f02831be
EG
2202 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2203 struct iwl_cmd_meta *out_meta;
2204 struct iwl_txq *txq;
2205 struct iwl_queue *q;
38c0f334
JB
2206 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2207 void *tb1_addr;
3a0b2a42 2208 u16 len, tb1_len;
ea68f460 2209 bool wait_write_ptr;
206eea78
JB
2210 __le16 fc;
2211 u8 hdr_len;
68972c46 2212 u16 wifi_seq;
f02831be
EG
2213
2214 txq = &trans_pcie->txq[txq_id];
2215 q = &txq->q;
a0eaad71 2216
961de6a5
JB
2217 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2218 "TX on unused queue %d\n", txq_id))
f02831be 2219 return -EINVAL;
39644e9a 2220
41837ca9
EG
2221 if (unlikely(trans_pcie->sw_csum_tx &&
2222 skb->ip_summed == CHECKSUM_PARTIAL)) {
2223 int offs = skb_checksum_start_offset(skb);
2224 int csum_offs = offs + skb->csum_offset;
2225 __wsum csum;
2226
2227 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2228 return -1;
2229
2230 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2231 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
3955525d
EG
2232
2233 skb->ip_summed = CHECKSUM_UNNECESSARY;
41837ca9
EG
2234 }
2235
206eea78
JB
2236 if (skb_is_nonlinear(skb) &&
2237 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS &&
2238 __skb_linearize(skb))
2239 return -ENOMEM;
2240
2241 /* mac80211 always puts the full header into the SKB's head,
2242 * so there's no need to check if it's readable there
2243 */
2244 hdr = (struct ieee80211_hdr *)skb->data;
2245 fc = hdr->frame_control;
2246 hdr_len = ieee80211_hdrlen(fc);
2247
f02831be 2248 spin_lock(&txq->lock);
015c15e1 2249
3955525d
EG
2250 if (iwl_queue_space(q) < q->high_mark) {
2251 iwl_stop_queue(trans, txq);
2252
2253 /* don't put the packet on the ring, if there is no room */
2254 if (unlikely(iwl_queue_space(q) < 3)) {
2255 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2256
2257 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA + 1] =
2258 dev_cmd;
2259 __skb_queue_tail(&txq->overflow_q, skb);
2260
2261 spin_unlock(&txq->lock);
2262 return 0;
2263 }
2264 }
2265
f02831be
EG
2266 /* In AGG mode, the index in the ring must correspond to the WiFi
2267 * sequence number. This is a HW requirements to help the SCD to parse
2268 * the BA.
2269 * Check here that the packets are in the right place on the ring.
2270 */
9a886586 2271 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1092b9bc 2272 WARN_ONCE(txq->ampdu &&
68972c46 2273 (wifi_seq & 0xff) != q->write_ptr,
f02831be
EG
2274 "Q: %d WiFi Seq %d tfdNum %d",
2275 txq_id, wifi_seq, q->write_ptr);
f02831be
EG
2276
2277 /* Set up driver data for this TFD */
2278 txq->entries[q->write_ptr].skb = skb;
2279 txq->entries[q->write_ptr].cmd = dev_cmd;
2280
f02831be
EG
2281 dev_cmd->hdr.sequence =
2282 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2283 INDEX_TO_SEQ(q->write_ptr)));
2284
38c0f334
JB
2285 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
2286 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2287 offsetof(struct iwl_tx_cmd, scratch);
2288
2289 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2290 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2291
f02831be
EG
2292 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2293 out_meta = &txq->entries[q->write_ptr].meta;
206eea78 2294 out_meta->flags = 0;
a0eaad71 2295
f02831be 2296 /*
38c0f334
JB
2297 * The second TB (tb1) points to the remainder of the TX command
2298 * and the 802.11 header - dword aligned size
2299 * (This calculation modifies the TX command, so do it before the
2300 * setup of the first TB)
f02831be 2301 */
38c0f334
JB
2302 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2303 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1092b9bc 2304 tb1_len = ALIGN(len, 4);
f02831be
EG
2305
2306 /* Tell NIC about any 2-byte padding after MAC header */
38c0f334 2307 if (tb1_len != len)
f02831be
EG
2308 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2309
38c0f334
JB
2310 /* The first TB points to the scratchbuf data - min_copy bytes */
2311 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
2312 IWL_HCMD_SCRATCHBUF_SIZE);
2313 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
6d6e68f8 2314 IWL_HCMD_SCRATCHBUF_SIZE, true);
f02831be 2315
38c0f334
JB
2316 /* there must be data left over for TB1 or this code must be changed */
2317 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
2318
2319 /* map the data for TB1 */
2320 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
2321 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2322 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2323 goto out_err;
6d6e68f8 2324 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
a0eaad71 2325
6eb5e529
EG
2326 if (ieee80211_is_data_qos(fc) &&
2327 (*ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_A_MSDU_PRESENT)) {
2328 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2329 out_meta, dev_cmd,
2330 tb1_len)))
2331 goto out_err;
2332 } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2333 out_meta, dev_cmd, tb1_len))) {
3a0b2a42 2334 goto out_err;
6eb5e529 2335 }
206eea78 2336
f02831be
EG
2337 /* Set up entry for this TFD in Tx byte-count array */
2338 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
a0eaad71 2339
ea68f460 2340 wait_write_ptr = ieee80211_has_morefrags(fc);
7c5ba4a8 2341
f02831be 2342 /* start timer if queue currently empty */
7616f334 2343 if (q->read_ptr == q->write_ptr) {
aecdc63d
EG
2344 if (txq->wd_timeout) {
2345 /*
2346 * If the TXQ is active, then set the timer, if not,
2347 * set the timer in remainder so that the timer will
2348 * be armed with the right value when the station will
2349 * wake up.
2350 */
2351 if (!txq->frozen)
2352 mod_timer(&txq->stuck_timer,
2353 jiffies + txq->wd_timeout);
2354 else
2355 txq->frozen_expiry_remainder = txq->wd_timeout;
2356 }
7616f334
EP
2357 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
2358 iwl_trans_pcie_ref(trans);
2359 }
f02831be
EG
2360
2361 /* Tell device the write index *just past* this latest filled TFD */
83f32a4b 2362 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
ea68f460
JB
2363 if (!wait_write_ptr)
2364 iwl_pcie_txq_inc_wr_ptr(trans, txq);
f02831be
EG
2365
2366 /*
2367 * At this point the frame is "transmitted" successfully
43aa616f 2368 * and we will get a TX status notification eventually.
f02831be 2369 */
f02831be
EG
2370 spin_unlock(&txq->lock);
2371 return 0;
2372out_err:
2373 spin_unlock(&txq->lock);
2374 return -1;
a0eaad71 2375}
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