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Catch ipw2200 up to equivelancy with v1.0.2
[deliverable/linux.git] / drivers / net / wireless / ipw2200.h
CommitLineData
43f66a6c 1/******************************************************************************
bf79451e 2
43f66a6c 3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
bf79451e
JG		 4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
43f66a6c 7 published by the Free Software Foundation.
bf79451e
JG		 8
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
43f66a6c 12 more details.
bf79451e 13
43f66a6c 14 You should have received a copy of the GNU General Public License along with
bf79451e 15 this program; if not, write to the Free Software Foundation, Inc., 59
43f66a6c 16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
bf79451e 17
43f66a6c
JK		 18 The full GNU General Public License is included in this distribution in the
19 file called LICENSE.
bf79451e 20
43f66a6c
JK		 21 Contact Information:
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25******************************************************************************/
26
27#ifndef __ipw2200_h__
28#define __ipw2200_h__
29
30#define WEXT_USECHANNELS 1
31
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/config.h>
35#include <linux/init.h>
36
37#include <linux/version.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/ethtool.h>
41#include <linux/skbuff.h>
42#include <linux/etherdevice.h>
43#include <linux/delay.h>
44#include <linux/random.h>
843684a2 45#include <linux/dma-mapping.h>
43f66a6c
JK		 46
47#include <linux/firmware.h>
48#include <linux/wireless.h>
3da54c5b 49#include <linux/dma-mapping.h>
43f66a6c
JK		 50#include <asm/io.h>
51
52#include <net/ieee80211.h>
53
54#define DRV_NAME "ipw2200"
55
56#include <linux/workqueue.h>
57
43f66a6c 58/* Authentication and Association States */
0edd5b44 59enum connection_manager_assoc_states {
43f66a6c
JK		 60 CMAS_INIT = 0,
61 CMAS_TX_AUTH_SEQ_1,
62 CMAS_RX_AUTH_SEQ_2,
63 CMAS_AUTH_SEQ_1_PASS,
64 CMAS_AUTH_SEQ_1_FAIL,
65 CMAS_TX_AUTH_SEQ_3,
66 CMAS_RX_AUTH_SEQ_4,
67 CMAS_AUTH_SEQ_2_PASS,
68 CMAS_AUTH_SEQ_2_FAIL,
69 CMAS_AUTHENTICATED,
70 CMAS_TX_ASSOC,
71 CMAS_RX_ASSOC_RESP,
72 CMAS_ASSOCIATED,
73 CMAS_LAST
74};
75
43f66a6c
JK		 76#define IPW_WAIT (1<<0)
77#define IPW_QUIET (1<<1)
78#define IPW_ROAMING (1<<2)
79
80#define IPW_POWER_MODE_CAM 0x00 //(always on)
81#define IPW_POWER_INDEX_1 0x01
82#define IPW_POWER_INDEX_2 0x02
83#define IPW_POWER_INDEX_3 0x03
84#define IPW_POWER_INDEX_4 0x04
85#define IPW_POWER_INDEX_5 0x05
86#define IPW_POWER_AC 0x06
87#define IPW_POWER_BATTERY 0x07
88#define IPW_POWER_LIMIT 0x07
89#define IPW_POWER_MASK 0x0F
90#define IPW_POWER_ENABLED 0x10
91#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
92
93#define IPW_CMD_HOST_COMPLETE 2
94#define IPW_CMD_POWER_DOWN 4
95#define IPW_CMD_SYSTEM_CONFIG 6
96#define IPW_CMD_MULTICAST_ADDRESS 7
97#define IPW_CMD_SSID 8
98#define IPW_CMD_ADAPTER_ADDRESS 11
99#define IPW_CMD_PORT_TYPE 12
100#define IPW_CMD_RTS_THRESHOLD 15
101#define IPW_CMD_FRAG_THRESHOLD 16
102#define IPW_CMD_POWER_MODE 17
103#define IPW_CMD_WEP_KEY 18
104#define IPW_CMD_TGI_TX_KEY 19
105#define IPW_CMD_SCAN_REQUEST 20
106#define IPW_CMD_ASSOCIATE 21
107#define IPW_CMD_SUPPORTED_RATES 22
108#define IPW_CMD_SCAN_ABORT 23
109#define IPW_CMD_TX_FLUSH 24
110#define IPW_CMD_QOS_PARAMETERS 25
111#define IPW_CMD_SCAN_REQUEST_EXT 26
112#define IPW_CMD_DINO_CONFIG 30
113#define IPW_CMD_RSN_CAPABILITIES 31
114#define IPW_CMD_RX_KEY 32
115#define IPW_CMD_CARD_DISABLE 33
116#define IPW_CMD_SEED_NUMBER 34
117#define IPW_CMD_TX_POWER 35
118#define IPW_CMD_COUNTRY_INFO 36
119#define IPW_CMD_AIRONET_INFO 37
120#define IPW_CMD_AP_TX_POWER 38
121#define IPW_CMD_CCKM_INFO 39
122#define IPW_CMD_CCX_VER_INFO 40
123#define IPW_CMD_SET_CALIBRATION 41
124#define IPW_CMD_SENSITIVITY_CALIB 42
125#define IPW_CMD_RETRY_LIMIT 51
126#define IPW_CMD_IPW_PRE_POWER_DOWN 58
127#define IPW_CMD_VAP_BEACON_TEMPLATE 60
128#define IPW_CMD_VAP_DTIM_PERIOD 61
129#define IPW_CMD_EXT_SUPPORTED_RATES 62
130#define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
131#define IPW_CMD_VAP_QUIET_INTERVALS 64
132#define IPW_CMD_VAP_CHANNEL_SWITCH 65
133#define IPW_CMD_VAP_MANDATORY_CHANNELS 66
134#define IPW_CMD_VAP_CELL_PWR_LIMIT 67
135#define IPW_CMD_VAP_CF_PARAM_SET 68
136#define IPW_CMD_VAP_SET_BEACONING_STATE 69
137#define IPW_CMD_MEASUREMENT 80
138#define IPW_CMD_POWER_CAPABILITY 81
139#define IPW_CMD_SUPPORTED_CHANNELS 82
140#define IPW_CMD_TPC_REPORT 83
141#define IPW_CMD_WME_INFO 84
142#define IPW_CMD_PRODUCTION_COMMAND 85
143#define IPW_CMD_LINKSYS_EOU_INFO 90
144
145#define RFD_SIZE 4
146#define NUM_TFD_CHUNKS 6
147
148#define TX_QUEUE_SIZE 32
149#define RX_QUEUE_SIZE 32
150
151#define DINO_CMD_WEP_KEY 0x08
152#define DINO_CMD_TX 0x0B
153#define DCT_ANTENNA_A 0x01
154#define DCT_ANTENNA_B 0x02
155
156#define IPW_A_MODE 0
157#define IPW_B_MODE 1
158#define IPW_G_MODE 2
159
bf79451e
JG		 160/*
161 * TX Queue Flag Definitions
43f66a6c
JK		 162 */
163
164/* abort attempt if mgmt frame is rx'd */
bf79451e
JG		 165#define DCT_FLAG_ABORT_MGMT 0x01
166
43f66a6c
JK		 167/* require CTS */
168#define DCT_FLAG_CTS_REQUIRED 0x02
169
170/* use short preamble */
ea2b26e0
JK		 171#define DCT_FLAG_LONG_PREAMBLE 0x00
172#define DCT_FLAG_SHORT_PREAMBLE 0x04
43f66a6c
JK		 173
174/* RTS/CTS first */
175#define DCT_FLAG_RTS_REQD 0x08
176
177/* dont calculate duration field */
178#define DCT_FLAG_DUR_SET 0x10
179
180/* even if MAC WEP set (allows pre-encrypt) */
181#define DCT_FLAG_NO_WEP 0x20
8d45ff7d 182
43f66a6c
JK		 183/* overwrite TSF field */
184#define DCT_FLAG_TSF_REQD 0x40
185
186/* ACK rx is expected to follow */
bf79451e 187#define DCT_FLAG_ACK_REQD 0x80
43f66a6c
JK		 188
189#define DCT_FLAG_EXT_MODE_CCK 0x01
190#define DCT_FLAG_EXT_MODE_OFDM 0x00
191
43f66a6c
JK		 192#define TX_RX_TYPE_MASK 0xFF
193#define TX_FRAME_TYPE 0x00
194#define TX_HOST_COMMAND_TYPE 0x01
195#define RX_FRAME_TYPE 0x09
196#define RX_HOST_NOTIFICATION_TYPE 0x03
197#define RX_HOST_CMD_RESPONSE_TYPE 0x04
198#define RX_TX_FRAME_RESPONSE_TYPE 0x05
199#define TFD_NEED_IRQ_MASK 0x04
200
201#define HOST_CMD_DINO_CONFIG 30
202
203#define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
204#define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
205#define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
206#define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
207#define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
208#define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
209#define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
210#define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
211#define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
212#define HOST_NOTIFICATION_TX_STATUS 19
213#define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
214#define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
215#define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
216#define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
217#define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
218#define HOST_NOTIFICATION_NOISE_STATS 25
bf79451e 219#define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
43f66a6c
JK		 220#define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
221
222#define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
223#define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
224#define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
bf79451e 225#define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
43f66a6c
JK		 226
227#define MACADRR_BYTE_LEN 6
228
229#define DCR_TYPE_AP 0x01
230#define DCR_TYPE_WLAP 0x02
231#define DCR_TYPE_MU_ESS 0x03
232#define DCR_TYPE_MU_IBSS 0x04
233#define DCR_TYPE_MU_PIBSS 0x05
234#define DCR_TYPE_SNIFFER 0x06
235#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
236
237/**
238 * Generic queue structure
bf79451e 239 *
43f66a6c
JK		 240 * Contains common data for Rx and Tx queues
241 */
242struct clx2_queue {
0edd5b44
JG		 243 int n_bd; /**< number of BDs in this queue */
244 int first_empty; /**< 1-st empty entry (index) */
245 int last_used; /**< last used entry (index) */
246 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
247 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
248 dma_addr_t dma_addr; /**< physical addr for BD's */
249 int low_mark; /**< low watermark, resume queue if free space more than this */
250 int high_mark; /**< high watermark, stop queue if free space less than this */
43f66a6c
JK		 251} __attribute__ ((packed));
252
0edd5b44 253struct machdr32 {
43f66a6c 254 u16 frame_ctl;
0edd5b44
JG		 255 u16 duration; // watch out for endians!
256 u8 addr1[MACADRR_BYTE_LEN];
257 u8 addr2[MACADRR_BYTE_LEN];
258 u8 addr3[MACADRR_BYTE_LEN];
259 u16 seq_ctrl; // more endians!
260 u8 addr4[MACADRR_BYTE_LEN];
43f66a6c 261 u16 qos_ctrl;
0edd5b44 262} __attribute__ ((packed));
43f66a6c 263
0edd5b44 264struct machdr30 {
43f66a6c 265 u16 frame_ctl;
0edd5b44
JG		 266 u16 duration; // watch out for endians!
267 u8 addr1[MACADRR_BYTE_LEN];
268 u8 addr2[MACADRR_BYTE_LEN];
269 u8 addr3[MACADRR_BYTE_LEN];
270 u16 seq_ctrl; // more endians!
271 u8 addr4[MACADRR_BYTE_LEN];
272} __attribute__ ((packed));
273
274struct machdr26 {
43f66a6c 275 u16 frame_ctl;
0edd5b44
JG		 276 u16 duration; // watch out for endians!
277 u8 addr1[MACADRR_BYTE_LEN];
278 u8 addr2[MACADRR_BYTE_LEN];
279 u8 addr3[MACADRR_BYTE_LEN];
280 u16 seq_ctrl; // more endians!
43f66a6c 281 u16 qos_ctrl;
0edd5b44 282} __attribute__ ((packed));
43f66a6c 283
0edd5b44 284struct machdr24 {
43f66a6c 285 u16 frame_ctl;
0edd5b44
JG		 286 u16 duration; // watch out for endians!
287 u8 addr1[MACADRR_BYTE_LEN];
288 u8 addr2[MACADRR_BYTE_LEN];
289 u8 addr3[MACADRR_BYTE_LEN];
290 u16 seq_ctrl; // more endians!
291} __attribute__ ((packed));
43f66a6c
JK		 292
293// TX TFD with 32 byte MAC Header
0edd5b44
JG		 294struct tx_tfd_32 {
295 struct machdr32 mchdr; // 32
296 u32 uivplaceholder[2]; // 8
297} __attribute__ ((packed));
43f66a6c
JK		 298
299// TX TFD with 30 byte MAC Header
0edd5b44
JG		 300struct tx_tfd_30 {
301 struct machdr30 mchdr; // 30
302 u8 reserved[2]; // 2
303 u32 uivplaceholder[2]; // 8
304} __attribute__ ((packed));
43f66a6c
JK		 305
306// tx tfd with 26 byte mac header
0edd5b44
JG		 307struct tx_tfd_26 {
308 struct machdr26 mchdr; // 26
309 u8 reserved1[2]; // 2
310 u32 uivplaceholder[2]; // 8
311 u8 reserved2[4]; // 4
312} __attribute__ ((packed));
43f66a6c
JK		 313
314// tx tfd with 24 byte mac header
0edd5b44
JG		 315struct tx_tfd_24 {
316 struct machdr24 mchdr; // 24
317 u32 uivplaceholder[2]; // 8
318 u8 reserved[8]; // 8
319} __attribute__ ((packed));
43f66a6c
JK		 320
321#define DCT_WEP_KEY_FIELD_LENGTH 16
322
0edd5b44 323struct tfd_command {
43f66a6c
JK		 324 u8 index;
325 u8 length;
326 u16 reserved;
327 u8 payload[0];
0edd5b44 328} __attribute__ ((packed));
43f66a6c
JK		 329
330struct tfd_data {
331 /* Header */
332 u32 work_area_ptr;
0edd5b44 333 u8 station_number; /* 0 for BSS */
43f66a6c
JK		 334 u8 reserved1;
335 u16 reserved2;
336
337 /* Tx Parameters */
338 u8 cmd_id;
bf79451e
JG		 339 u8 seq_num;
340 u16 len;
43f66a6c
JK		 341 u8 priority;
342 u8 tx_flags;
343 u8 tx_flags_ext;
344 u8 key_index;
345 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
346 u8 rate;
347 u8 antenna;
348 u16 next_packet_duration;
bf79451e 349 u16 next_frag_len;
0edd5b44 350 u16 back_off_counter; //////txop;
43f66a6c 351 u8 retrylimit;
bf79451e 352 u16 cwcurrent;
43f66a6c
JK		 353 u8 reserved3;
354
355 /* 802.11 MAC Header */
0edd5b44 356 union {
43f66a6c
JK		 357 struct tx_tfd_24 tfd_24;
358 struct tx_tfd_26 tfd_26;
359 struct tx_tfd_30 tfd_30;
360 struct tx_tfd_32 tfd_32;
361 } tfd;
362
363 /* Payload DMA info */
364 u32 num_chunks;
365 u32 chunk_ptr[NUM_TFD_CHUNKS];
366 u16 chunk_len[NUM_TFD_CHUNKS];
367} __attribute__ ((packed));
368
0edd5b44 369struct txrx_control_flags {
43f66a6c
JK		 370 u8 message_type;
371 u8 rx_seq_num;
372 u8 control_bits;
373 u8 reserved;
374} __attribute__ ((packed));
375
376#define TFD_SIZE 128
377#define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
378
0edd5b44 379struct tfd_frame {
43f66a6c
JK		 380 struct txrx_control_flags control_flags;
381 union {
382 struct tfd_data data;
383 struct tfd_command cmd;
384 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
385 } u;
0edd5b44 386} __attribute__ ((packed));
43f66a6c 387
0edd5b44 388typedef void destructor_func(const void *);
43f66a6c
JK		 389
390/**
391 * Tx Queue for DMA. Queue consists of circular buffer of
392 * BD's and required locking structures.
393 */
394struct clx2_tx_queue {
395 struct clx2_queue q;
0edd5b44 396 struct tfd_frame *bd;
43f66a6c
JK		 397 struct ieee80211_txb **txb;
398};
399
400/*
401 * RX related structures and functions
402 */
403#define RX_FREE_BUFFERS 32
404#define RX_LOW_WATERMARK 8
405
a613bffd
JK		 406#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
407#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
408#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
43f66a6c
JK		 409
410// Used for passing to driver number of successes and failures per rate
0edd5b44 411struct rate_histogram {
43f66a6c
JK		 412 union {
413 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
414 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
415 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
416 } success;
417 union {
418 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
419 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
420 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
421 } failed;
422} __attribute__ ((packed));
423
bf79451e 424/* statistics command response */
43f66a6c
JK		 425struct ipw_cmd_stats {
426 u8 cmd_id;
427 u8 seq_num;
bf79451e
JG		 428 u16 good_sfd;
429 u16 bad_plcp;
430 u16 wrong_bssid;
431 u16 valid_mpdu;
432 u16 bad_mac_header;
433 u16 reserved_frame_types;
434 u16 rx_ina;
435 u16 bad_crc32;
436 u16 invalid_cts;
437 u16 invalid_acks;
438 u16 long_distance_ina_fina;
43f66a6c 439 u16 dsp_silence_unreachable;
bf79451e
JG		 440 u16 accumulated_rssi;
441 u16 rx_ovfl_frame_tossed;
43f66a6c
JK		 442 u16 rssi_silence_threshold;
443 u16 rx_ovfl_frame_supplied;
bf79451e
JG		 444 u16 last_rx_frame_signal;
445 u16 last_rx_frame_noise;
446 u16 rx_autodetec_no_ofdm;
43f66a6c
JK		 447 u16 rx_autodetec_no_barker;
448 u16 reserved;
449} __attribute__ ((packed));
450
451struct notif_channel_result {
452 u8 channel_num;
453 struct ipw_cmd_stats stats;
454 u8 uReserved;
455} __attribute__ ((packed));
456
457struct notif_scan_complete {
458 u8 scan_type;
459 u8 num_channels;
460 u8 status;
461 u8 reserved;
0edd5b44 462} __attribute__ ((packed));
43f66a6c
JK		 463
464struct notif_frag_length {
465 u16 frag_length;
466 u16 reserved;
0edd5b44 467} __attribute__ ((packed));
43f66a6c
JK		 468
469struct notif_beacon_state {
470 u32 state;
471 u32 number;
472} __attribute__ ((packed));
473
474struct notif_tgi_tx_key {
475 u8 key_state;
476 u8 security_type;
477 u8 station_index;
478 u8 reserved;
479} __attribute__ ((packed));
480
481struct notif_link_deterioration {
482 struct ipw_cmd_stats stats;
483 u8 rate;
484 u8 modulation;
485 struct rate_histogram histogram;
486 u8 reserved1;
487 u16 reserved2;
488} __attribute__ ((packed));
489
490struct notif_association {
491 u8 state;
492} __attribute__ ((packed));
493
494struct notif_authenticate {
495 u8 state;
496 struct machdr24 addr;
497 u16 status;
498} __attribute__ ((packed));
499
43f66a6c
JK		 500struct notif_calibration {
501 u8 data[104];
502} __attribute__ ((packed));
503
504struct notif_noise {
505 u32 value;
506} __attribute__ ((packed));
507
508struct ipw_rx_notification {
509 u8 reserved[8];
510 u8 subtype;
511 u8 flags;
512 u16 size;
513 union {
514 struct notif_association assoc;
515 struct notif_authenticate auth;
516 struct notif_channel_result channel_result;
517 struct notif_scan_complete scan_complete;
518 struct notif_frag_length frag_len;
519 struct notif_beacon_state beacon_state;
520 struct notif_tgi_tx_key tgi_tx_key;
521 struct notif_link_deterioration link_deterioration;
522 struct notif_calibration calibration;
523 struct notif_noise noise;
524 u8 raw[0];
525 } u;
526} __attribute__ ((packed));
527
528struct ipw_rx_frame {
bf79451e 529 u32 reserved1;
0edd5b44
JG		 530 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
531 u8 received_channel; // The channel that this frame was received on.
532 // Note that for .11b this does not have to be
533 // the same as the channel that it was sent.
534 // Filled by LMAC
43f66a6c
JK		 535 u8 frameStatus;
536 u8 rate;
537 u8 rssi;
538 u8 agc;
539 u8 rssi_dbm;
540 u16 signal;
541 u16 noise;
542 u8 antennaAndPhy;
0edd5b44
JG		 543 u8 control; // control bit should be on in bg
544 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
545 // is identical)
546 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
43f66a6c
JK		 547 u16 length;
548 u8 data[0];
549} __attribute__ ((packed));
bf79451e 550
43f66a6c
JK		 551struct ipw_rx_header {
552 u8 message_type;
553 u8 rx_seq_num;
554 u8 control_bits;
555 u8 reserved;
556} __attribute__ ((packed));
557
0edd5b44 558struct ipw_rx_packet {
43f66a6c
JK		 559 struct ipw_rx_header header;
560 union {
561 struct ipw_rx_frame frame;
562 struct ipw_rx_notification notification;
563 } u;
564} __attribute__ ((packed));
565
566#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
567#define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
568 sizeof(struct ipw_rx_frame)
569
570struct ipw_rx_mem_buffer {
571 dma_addr_t dma_addr;
572 struct ipw_rx_buffer *rxb;
573 struct sk_buff *skb;
574 struct list_head list;
0edd5b44 575}; /* Not transferred over network, so not __attribute__ ((packed)) */
43f66a6c
JK		 576
577struct ipw_rx_queue {
578 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
579 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
0edd5b44
JG		 580 u32 processed; /* Internal index to last handled Rx packet */
581 u32 read; /* Shared index to newest available Rx buffer */
582 u32 write; /* Shared index to oldest written Rx packet */
583 u32 free_count; /* Number of pre-allocated buffers in rx_free */
43f66a6c 584 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
0edd5b44
JG		 585 struct list_head rx_free; /* Own an SKBs */
586 struct list_head rx_used; /* No SKB allocated */
43f66a6c 587 spinlock_t lock;
0edd5b44 588}; /* Not transferred over network, so not __attribute__ ((packed)) */
43f66a6c
JK		 589
590struct alive_command_responce {
591 u8 alive_command;
592 u8 sequence_number;
593 u16 software_revision;
594 u8 device_identifier;
595 u8 reserved1[5];
596 u16 reserved2;
597 u16 reserved3;
598 u16 clock_settle_time;
599 u16 powerup_settle_time;
600 u16 reserved4;
601 u8 time_stamp[5]; /* month, day, year, hours, minutes */
602 u8 ucode_valid;
603} __attribute__ ((packed));
604
605#define IPW_MAX_RATES 12
606
607struct ipw_rates {
608 u8 num_rates;
609 u8 rates[IPW_MAX_RATES];
610} __attribute__ ((packed));
611
0edd5b44 612struct command_block {
43f66a6c
JK		 613 unsigned int control;
614 u32 source_addr;
615 u32 dest_addr;
616 unsigned int status;
617} __attribute__ ((packed));
618
619#define CB_NUMBER_OF_ELEMENTS_SMALL 64
0edd5b44 620struct fw_image_desc {
43f66a6c
JK		 621 unsigned long last_cb_index;
622 unsigned long current_cb_index;
623 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
0edd5b44 624 void *v_addr;
43f66a6c
JK		 625 unsigned long p_addr;
626 unsigned long len;
627};
628
0edd5b44 629struct ipw_sys_config {
43f66a6c
JK		 630 u8 bt_coexistence;
631 u8 reserved1;
632 u8 answer_broadcast_ssid_probe;
633 u8 accept_all_data_frames;
634 u8 accept_non_directed_frames;
635 u8 exclude_unicast_unencrypted;
636 u8 disable_unicast_decryption;
637 u8 exclude_multicast_unencrypted;
638 u8 disable_multicast_decryption;
639 u8 antenna_diversity;
640 u8 pass_crc_to_host;
641 u8 dot11g_auto_detection;
642 u8 enable_cts_to_self;
643 u8 enable_multicast_filtering;
644 u8 bt_coexist_collision_thr;
645 u8 reserved2;
646 u8 accept_all_mgmt_bcpr;
647 u8 accept_all_mgtm_frames;
648 u8 pass_noise_stats_to_host;
649 u8 reserved3;
650} __attribute__ ((packed));
651
0edd5b44 652struct ipw_multicast_addr {
43f66a6c
JK		 653 u8 num_of_multicast_addresses;
654 u8 reserved[3];
655 u8 mac1[6];
656 u8 mac2[6];
657 u8 mac3[6];
658 u8 mac4[6];
659} __attribute__ ((packed));
660
0edd5b44 661struct ipw_wep_key {
43f66a6c
JK		 662 u8 cmd_id;
663 u8 seq_num;
664 u8 key_index;
665 u8 key_size;
666 u8 key[16];
667} __attribute__ ((packed));
668
0edd5b44 669struct ipw_tgi_tx_key {
bf79451e 670 u8 key_id;
43f66a6c
JK		 671 u8 security_type;
672 u8 station_index;
673 u8 flags;
674 u8 key[16];
675 u32 tx_counter[2];
676} __attribute__ ((packed));
677
678#define IPW_SCAN_CHANNELS 54
679
0edd5b44 680struct ipw_scan_request {
43f66a6c
JK		 681 u8 scan_type;
682 u16 dwell_time;
683 u8 channels_list[IPW_SCAN_CHANNELS];
684 u8 channels_reserved[3];
685} __attribute__ ((packed));
686
687enum {
688 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
689 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
690 IPW_SCAN_ACTIVE_DIRECT_SCAN,
691 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
692 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
693 IPW_SCAN_TYPES
694};
695
0edd5b44 696struct ipw_scan_request_ext {
43f66a6c
JK		 697 u32 full_scan_index;
698 u8 channels_list[IPW_SCAN_CHANNELS];
699 u8 scan_type[IPW_SCAN_CHANNELS / 2];
700 u8 reserved;
701 u16 dwell_time[IPW_SCAN_TYPES];
702} __attribute__ ((packed));
703
bf79451e 704extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
43f66a6c
JK		 705{
706 if (index % 2)
707 return scan->scan_type[index / 2] & 0x0F;
708 else
709 return (scan->scan_type[index / 2] & 0xF0) >> 4;
710}
711
bf79451e 712extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
43f66a6c
JK		 713 u8 index, u8 scan_type)
714{
bf79451e
JG		 715 if (index % 2)
716 scan->scan_type[index / 2] =
0edd5b44 717 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
43f66a6c 718 else
bf79451e 719 scan->scan_type[index / 2] =
0edd5b44
JG		 720 (scan->scan_type[index / 2] & 0x0F) |
721 ((scan_type & 0x0F) << 4);
43f66a6c
JK		 722}
723
0edd5b44 724struct ipw_associate {
43f66a6c 725 u8 channel;
0edd5b44 726 u8 auth_type:4, auth_key:4;
43f66a6c
JK		 727 u8 assoc_type;
728 u8 reserved;
729 u16 policy_support;
730 u8 preamble_length;
731 u8 ieee_mode;
732 u8 bssid[ETH_ALEN];
733 u32 assoc_tsf_msw;
734 u32 assoc_tsf_lsw;
735 u16 capability;
736 u16 listen_interval;
737 u16 beacon_interval;
738 u8 dest[ETH_ALEN];
739 u16 atim_window;
740 u8 smr;
741 u8 reserved1;
742 u16 reserved2;
743} __attribute__ ((packed));
744
0edd5b44 745struct ipw_supported_rates {
43f66a6c
JK		 746 u8 ieee_mode;
747 u8 num_rates;
748 u8 purpose;
749 u8 reserved;
750 u8 supported_rates[IPW_MAX_RATES];
751} __attribute__ ((packed));
752
0edd5b44 753struct ipw_rts_threshold {
43f66a6c
JK		 754 u16 rts_threshold;
755 u16 reserved;
756} __attribute__ ((packed));
757
0edd5b44 758struct ipw_frag_threshold {
43f66a6c
JK		 759 u16 frag_threshold;
760 u16 reserved;
761} __attribute__ ((packed));
762
0edd5b44 763struct ipw_retry_limit {
43f66a6c
JK		 764 u8 short_retry_limit;
765 u8 long_retry_limit;
766 u16 reserved;
767} __attribute__ ((packed));
768
0edd5b44 769struct ipw_dino_config {
43f66a6c
JK		 770 u32 dino_config_addr;
771 u16 dino_config_size;
772 u8 dino_response;
773 u8 reserved;
774} __attribute__ ((packed));
775
0edd5b44 776struct ipw_aironet_info {
43f66a6c
JK		 777 u8 id;
778 u8 length;
779 u16 reserved;
780} __attribute__ ((packed));
781
0edd5b44 782struct ipw_rx_key {
43f66a6c
JK		 783 u8 station_index;
784 u8 key_type;
785 u8 key_id;
786 u8 key_flag;
787 u8 key[16];
788 u8 station_address[6];
789 u8 key_index;
790 u8 reserved;
791} __attribute__ ((packed));
792
0edd5b44 793struct ipw_country_channel_info {
43f66a6c
JK		 794 u8 first_channel;
795 u8 no_channels;
796 s8 max_tx_power;
797} __attribute__ ((packed));
798
0edd5b44 799struct ipw_country_info {
43f66a6c
JK		 800 u8 id;
801 u8 length;
802 u8 country_str[3];
803 struct ipw_country_channel_info groups[7];
804} __attribute__ ((packed));
805
0edd5b44 806struct ipw_channel_tx_power {
43f66a6c
JK		 807 u8 channel_number;
808 s8 tx_power;
809} __attribute__ ((packed));
810
811#define SCAN_ASSOCIATED_INTERVAL (HZ)
812#define SCAN_INTERVAL (HZ / 10)
813#define MAX_A_CHANNELS 37
814#define MAX_B_CHANNELS 14
815
0edd5b44 816struct ipw_tx_power {
43f66a6c
JK		 817 u8 num_channels;
818 u8 ieee_mode;
819 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
820} __attribute__ ((packed));
821
0edd5b44 822struct ipw_qos_parameters {
43f66a6c
JK		 823 u16 cw_min[4];
824 u16 cw_max[4];
825 u8 aifs[4];
826 u8 flag[4];
827 u16 tx_op_limit[4];
828} __attribute__ ((packed));
829
0edd5b44 830struct ipw_rsn_capabilities {
43f66a6c
JK		 831 u8 id;
832 u8 length;
833 u16 version;
834} __attribute__ ((packed));
835
0edd5b44 836struct ipw_sensitivity_calib {
43f66a6c
JK		 837 u16 beacon_rssi_raw;
838 u16 reserved;
839} __attribute__ ((packed));
840
841/**
842 * Host command structure.
bf79451e 843 *
43f66a6c
JK		 844 * On input, the following fields should be filled:
845 * - cmd
846 * - len
847 * - status_len
848 * - param (if needed)
bf79451e
JG		 849 *
850 * On output,
43f66a6c
JK		 851 * - \a status contains status;
852 * - \a param filled with status parameters.
853 */
854struct ipw_cmd {
0edd5b44
JG		 855 u32 cmd; /**< Host command */
856 u32 status;/**< Status */
857 u32 status_len;
858 /**< How many 32 bit parameters in the status */
859 u32 len; /**< incoming parameters length, bytes */
43f66a6c 860 /**
bf79451e
JG		 861 * command parameters.
862 * There should be enough space for incoming and
43f66a6c
JK		 863 * outcoming parameters.
864 * Incoming parameters listed 1-st, followed by outcoming params.
865 * nParams=(len+3)/4+status_len
866 */
0edd5b44 867 u32 param[0];
43f66a6c
JK		 868} __attribute__ ((packed));
869
0edd5b44 870#define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
43f66a6c
JK		 871
872#define STATUS_INT_ENABLED (1<<1)
873#define STATUS_RF_KILL_HW (1<<2)
874#define STATUS_RF_KILL_SW (1<<3)
875#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
876
877#define STATUS_INIT (1<<5)
878#define STATUS_AUTH (1<<6)
879#define STATUS_ASSOCIATED (1<<7)
880#define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
881
882#define STATUS_ASSOCIATING (1<<8)
883#define STATUS_DISASSOCIATING (1<<9)
884#define STATUS_ROAMING (1<<10)
885#define STATUS_EXIT_PENDING (1<<11)
886#define STATUS_DISASSOC_PENDING (1<<12)
887#define STATUS_STATE_PENDING (1<<13)
888
889#define STATUS_SCAN_PENDING (1<<20)
bf79451e
JG		 890#define STATUS_SCANNING (1<<21)
891#define STATUS_SCAN_ABORTING (1<<22)
43f66a6c 892
a613bffd
JK		 893#define STATUS_LED_LINK_ON (1<<24)
894#define STATUS_LED_ACT_ON (1<<25)
895
0edd5b44
JG		 896#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
897#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
898#define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
43f66a6c 899
0edd5b44 900#define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
43f66a6c 901
0edd5b44
JG		 902#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
903#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
904#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
43f66a6c 905#define CFG_CUSTOM_MAC (1<<3)
ea2b26e0 906#define CFG_PREAMBLE_LONG (1<<4)
43f66a6c
JK		 907#define CFG_ADHOC_PERSIST (1<<5)
908#define CFG_ASSOCIATE (1<<6)
909#define CFG_FIXED_RATE (1<<7)
910#define CFG_ADHOC_CREATE (1<<8)
a613bffd
JK		 911#define CFG_NO_LED (1<<9)
912#define CFG_BACKGROUND_SCAN (1<<10)
43f66a6c 913
0edd5b44
JG		 914#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
915#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
43f66a6c
JK		 916
917#define MAX_STATIONS 32
918#define IPW_INVALID_STATION (0xff)
919
920struct ipw_station_entry {
921 u8 mac_addr[ETH_ALEN];
922 u8 reserved;
923 u8 support_mode;
924};
925
926#define AVG_ENTRIES 8
927struct average {
928 s16 entries[AVG_ENTRIES];
929 u8 pos;
930 u8 init;
931 s32 sum;
932};
933
934struct ipw_priv {
935 /* ieee device used by generic ieee processing code */
936 struct ieee80211_device *ieee;
937 struct ieee80211_security sec;
938
939 /* spinlock */
940 spinlock_t lock;
941
942 /* basic pci-network driver stuff */
943 struct pci_dev *pci_dev;
944 struct net_device *net_dev;
945
946 /* pci hardware address support */
947 void __iomem *hw_base;
948 unsigned long hw_len;
bf79451e 949
43f66a6c
JK		 950 struct fw_image_desc sram_desc;
951
952 /* result of ucode download */
953 struct alive_command_responce dino_alive;
954
0edd5b44
JG		 955 wait_queue_head_t wait_command_queue;
956 wait_queue_head_t wait_state;
43f66a6c
JK		 957
958 /* Rx and Tx DMA processing queues */
959 struct ipw_rx_queue *rxq;
960 struct clx2_tx_queue txq_cmd;
961 struct clx2_tx_queue txq[4];
962 u32 status;
963 u32 config;
964 u32 capability;
965
966 u8 last_rx_rssi;
967 u8 last_noise;
968 struct average average_missed_beacons;
969 struct average average_rssi;
970 struct average average_noise;
971 u32 port_type;
0edd5b44
JG		 972 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
973 int rx_pend_max; /**< maximum pending buffers for one IRQ */
974 u32 hcmd_seq; /**< sequence number for hcmd */
43f66a6c 975 u32 missed_beacon_threshold;
bf79451e 976 u32 roaming_threshold;
43f66a6c
JK		 977
978 struct ipw_associate assoc_request;
979 struct ieee80211_network *assoc_network;
980
981 unsigned long ts_scan_abort;
982 struct ipw_supported_rates rates;
0edd5b44
JG		 983 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
984 struct ipw_rates supp; /**< software defined */
985 struct ipw_rates extended; /**< use for corresp. IE, AP only */
43f66a6c
JK		 986
987 struct notif_link_deterioration last_link_deterioration; /** for statistics */
0edd5b44 988 struct ipw_cmd *hcmd; /**< host command currently executed */
43f66a6c
JK		 989
990 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
0edd5b44 991 u32 tsf_bcn[2]; /**< TSF from latest beacon */
43f66a6c 992
0edd5b44 993 struct notif_calibration calib; /**< last calibration */
43f66a6c
JK		 994
995 /* ordinal interface with firmware */
996 u32 table0_addr;
997 u32 table0_len;
998 u32 table1_addr;
999 u32 table1_len;
1000 u32 table2_addr;
1001 u32 table2_len;
1002
1003 /* context information */
1004 u8 essid[IW_ESSID_MAX_SIZE];
1005 u8 essid_len;
1006 u8 nick[IW_ESSID_MAX_SIZE];
1007 u16 rates_mask;
1008 u8 channel;
1009 struct ipw_sys_config sys_config;
1010 u32 power_mode;
bf79451e 1011 u8 bssid[ETH_ALEN];
43f66a6c
JK		 1012 u16 rts_threshold;
1013 u8 mac_addr[ETH_ALEN];
1014 u8 num_stations;
bf79451e 1015 u8 stations[MAX_STATIONS][ETH_ALEN];
43f66a6c
JK		 1016
1017 u32 notif_missed_beacons;
1018
1019 /* Statistics and counters normalized with each association */
1020 u32 last_missed_beacons;
1021 u32 last_tx_packets;
1022 u32 last_rx_packets;
1023 u32 last_tx_failures;
1024 u32 last_rx_err;
1025 u32 last_rate;
1026
1027 u32 missed_adhoc_beacons;
1028 u32 missed_beacons;
1029 u32 rx_packets;
1030 u32 tx_packets;
1031 u32 quality;
1032
0edd5b44
JG		 1033 /* eeprom */
1034 u8 eeprom[0x100]; /* 256 bytes of eeprom */
43f66a6c
JK		 1035 int eeprom_delay;
1036
bf79451e 1037 struct iw_statistics wstats;
43f66a6c
JK		 1038
1039 struct workqueue_struct *workqueue;
bf79451e 1040
43f66a6c
JK		 1041 struct work_struct adhoc_check;
1042 struct work_struct associate;
1043 struct work_struct disassociate;
1044 struct work_struct rx_replenish;
1045 struct work_struct request_scan;
1046 struct work_struct adapter_restart;
1047 struct work_struct rf_kill;
1048 struct work_struct up;
1049 struct work_struct down;
1050 struct work_struct gather_stats;
1051 struct work_struct abort_scan;
1052 struct work_struct roam;
1053 struct work_struct scan_check;
a613bffd
JK		 1054 struct work_struct link_up;
1055 struct work_struct link_down;
43f66a6c
JK		 1056
1057 struct tasklet_struct irq_tasklet;
1058
a613bffd
JK		 1059 /* LED related variables and work_struct */
1060 u8 nic_type;
1061 u32 led_activity_on;
1062 u32 led_activity_off;
1063 u32 led_association_on;
1064 u32 led_association_off;
1065 u32 led_ofdm_on;
1066 u32 led_ofdm_off;
1067
1068 struct work_struct led_link_on;
1069 struct work_struct led_link_off;
1070 struct work_struct led_act_off;
1071
43f66a6c
JK		 1072#define IPW_2200BG 1
1073#define IPW_2915ABG 2
1074 u8 adapter;
1075
1076#define IPW_DEFAULT_TX_POWER 0x14
1077 u8 tx_power;
1078
bf79451e 1079#ifdef CONFIG_PM
43f66a6c
JK		 1080 u32 pm_state[16];
1081#endif
1082
1083 /* network state */
1084
1085 /* Used to pass the current INTA value from ISR to Tasklet */
1086 u32 isr_inta;
1087
1088 /* debugging info */
1089 u32 indirect_dword;
1090 u32 direct_dword;
1091 u32 indirect_byte;
1092}; /*ipw_priv */
1093
43f66a6c
JK		 1094/* debug macros */
1095
1096#ifdef CONFIG_IPW_DEBUG
1097#define IPW_DEBUG(level, fmt, args...) \
1098do { if (ipw_debug_level & (level)) \
1099 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1100 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1101#else
1102#define IPW_DEBUG(level, fmt, args...) do {} while (0)
1103#endif /* CONFIG_IPW_DEBUG */
1104
1105/*
1106 * To use the debug system;
1107 *
1108 * If you are defining a new debug classification, simply add it to the #define
1109 * list here in the form of:
1110 *
1111 * #define IPW_DL_xxxx VALUE
bf79451e 1112 *
43f66a6c
JK		 1113 * shifting value to the left one bit from the previous entry. xxxx should be
1114 * the name of the classification (for example, WEP)
1115 *
1116 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1117 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1118 * to send output to that classification.
1119 *
1120 * To add your debug level to the list of levels seen when you perform
1121 *
1122 * % cat /proc/net/ipw/debug_level
1123 *
1124 * you simply need to add your entry to the ipw_debug_levels array.
1125 *
bf79451e 1126 * If you do not see debug_level in /proc/net/ipw then you do not have
43f66a6c
JK		 1127 * CONFIG_IPW_DEBUG defined in your kernel configuration
1128 *
1129 */
1130
1131#define IPW_DL_ERROR (1<<0)
1132#define IPW_DL_WARNING (1<<1)
1133#define IPW_DL_INFO (1<<2)
1134#define IPW_DL_WX (1<<3)
1135#define IPW_DL_HOST_COMMAND (1<<5)
1136#define IPW_DL_STATE (1<<6)
1137
1138#define IPW_DL_NOTIF (1<<10)
1139#define IPW_DL_SCAN (1<<11)
1140#define IPW_DL_ASSOC (1<<12)
1141#define IPW_DL_DROP (1<<13)
1142#define IPW_DL_IOCTL (1<<14)
1143
1144#define IPW_DL_MANAGE (1<<15)
1145#define IPW_DL_FW (1<<16)
1146#define IPW_DL_RF_KILL (1<<17)
1147#define IPW_DL_FW_ERRORS (1<<18)
1148
a613bffd
JK		 1149#define IPW_DL_LED (1<<19)
1150
43f66a6c
JK		 1151#define IPW_DL_ORD (1<<20)
1152
1153#define IPW_DL_FRAG (1<<21)
1154#define IPW_DL_WEP (1<<22)
1155#define IPW_DL_TX (1<<23)
1156#define IPW_DL_RX (1<<24)
1157#define IPW_DL_ISR (1<<25)
1158#define IPW_DL_FW_INFO (1<<26)
1159#define IPW_DL_IO (1<<27)
1160#define IPW_DL_TRACE (1<<28)
1161
1162#define IPW_DL_STATS (1<<29)
1163
43f66a6c
JK		 1164#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1165#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1166#define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1167
1168#define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1169#define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1170#define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1171#define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1172#define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1173#define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1174#define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1175#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
a613bffd 1176#define IPW_DEBUG_LED(f, a...) IPW_DEBUG(IPW_DL_LED, f, ## a)
43f66a6c
JK		 1177#define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1178#define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1179#define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1180#define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1181#define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1182#define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1183#define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1184#define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1185#define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1186#define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1187#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1188#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1189#define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1190
1191#include <linux/ctype.h>
1192
1193/*
1194* Register bit definitions
1195*/
1196
1197/* Dino control registers bits */
1198
1199#define DINO_ENABLE_SYSTEM 0x80
1200#define DINO_ENABLE_CS 0x40
bf79451e 1201#define DINO_RXFIFO_DATA 0x01
43f66a6c
JK		 1202#define DINO_CONTROL_REG 0x00200000
1203
1204#define CX2_INTA_RW 0x00000008
1205#define CX2_INTA_MASK_R 0x0000000C
1206#define CX2_INDIRECT_ADDR 0x00000010
1207#define CX2_INDIRECT_DATA 0x00000014
1208#define CX2_AUTOINC_ADDR 0x00000018
1209#define CX2_AUTOINC_DATA 0x0000001C
1210#define CX2_RESET_REG 0x00000020
1211#define CX2_GP_CNTRL_RW 0x00000024
1212
1213#define CX2_READ_INT_REGISTER 0xFF4
1214
1215#define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
1216
1217#define CX2_REGISTER_DOMAIN1_END 0x00001000
1218#define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
1219
1220#define CX2_SHARED_LOWER_BOUND 0x00000200
1221#define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1222
1223#define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
1224#define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
1225
1226#define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1227#define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1228#define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1229
1230/*
1231 * RESET Register Bit Indexes
1232 */
ea2b26e0
JK		 1233#define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1234#define CX2_START_STANDBY (1<<2)
1235#define CX2_ACTIVITY_LED (1<<4)
1236#define CX2_ASSOCIATED_LED (1<<5)
1237#define CX2_OFDM_LED (1<<6)
1238#define CX2_RESET_REG_SW_RESET (1<<7)
1239#define CX2_RESET_REG_MASTER_DISABLED (1<<8)
1240#define CX2_RESET_REG_STOP_MASTER (1<<9)
1241#define CX2_GATE_ODMA (1<<25)
1242#define CX2_GATE_IDMA (1<<26)
1243#define CX2_ARC_KESHET_CONFIG (1<<27)
1244#define CX2_GATE_ADMA (1<<29)
43f66a6c
JK		 1245
1246#define CX2_CSR_CIS_UPPER_BOUND 0x00000200
1247#define CX2_DOMAIN_0_END 0x1000
1248#define CLX_MEM_BAR_SIZE 0x1000
1249
1250#define CX2_BASEBAND_CONTROL_STATUS 0X00200000
1251#define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
1252#define CX2_BASEBAND_RX_FIFO_READ 0X00200004
1253#define CX2_BASEBAND_CONTROL_STORE 0X00200010
1254
1255#define CX2_INTERNAL_CMD_EVENT 0X00300004
1256#define CX2_BASEBAND_POWER_DOWN 0x00000001
1257
1258#define CX2_MEM_HALT_AND_RESET 0x003000e0
1259
1260/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1261#define CX2_BIT_HALT_RESET_ON 0x80000000
1262#define CX2_BIT_HALT_RESET_OFF 0x00000000
1263
1264#define CB_LAST_VALID 0x20000000
1265#define CB_INT_ENABLED 0x40000000
1266#define CB_VALID 0x80000000
1267#define CB_SRC_LE 0x08000000
1268#define CB_DEST_LE 0x04000000
1269#define CB_SRC_AUTOINC 0x00800000
1270#define CB_SRC_IO_GATED 0x00400000
1271#define CB_DEST_AUTOINC 0x00080000
1272#define CB_SRC_SIZE_LONG 0x00200000
1273#define CB_DEST_SIZE_LONG 0x00020000
1274
43f66a6c
JK		 1275/* DMA DEFINES */
1276
1277#define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1278#define DMA_CB_STOP_AND_ABORT 0x00000C00
bf79451e 1279#define DMA_CB_START 0x00000100
43f66a6c 1280
43f66a6c
JK		 1281#define CX2_SHARED_SRAM_SIZE 0x00030000
1282#define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
1283#define CB_MAX_LENGTH 0x1FFF
1284
1285#define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1286#define CX2_EEPROM_IMAGE_SIZE 0x100
1287
43f66a6c
JK		 1288/* DMA defs */
1289#define CX2_DMA_I_CURRENT_CB 0x003000D0
1290#define CX2_DMA_O_CURRENT_CB 0x003000D4
1291#define CX2_DMA_I_DMA_CONTROL 0x003000A4
1292#define CX2_DMA_I_CB_BASE 0x003000A0
1293
a613bffd
JK		 1294#define CX2_TX_CMD_QUEUE_BD_BASE 0x00000200
1295#define CX2_TX_CMD_QUEUE_BD_SIZE 0x00000204
1296#define CX2_TX_QUEUE_0_BD_BASE 0x00000208
43f66a6c 1297#define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
a613bffd
JK		 1298#define CX2_TX_QUEUE_1_BD_BASE 0x00000210
1299#define CX2_TX_QUEUE_1_BD_SIZE 0x00000214
1300#define CX2_TX_QUEUE_2_BD_BASE 0x00000218
43f66a6c 1301#define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
a613bffd
JK		 1302#define CX2_TX_QUEUE_3_BD_BASE 0x00000220
1303#define CX2_TX_QUEUE_3_BD_SIZE 0x00000224
1304#define CX2_RX_BD_BASE 0x00000240
1305#define CX2_RX_BD_SIZE 0x00000244
1306#define CX2_RFDS_TABLE_LOWER 0x00000500
1307
1308#define CX2_TX_CMD_QUEUE_READ_INDEX 0x00000280
1309#define CX2_TX_QUEUE_0_READ_INDEX 0x00000284
1310#define CX2_TX_QUEUE_1_READ_INDEX 0x00000288
43f66a6c 1311#define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
a613bffd 1312#define CX2_TX_QUEUE_3_READ_INDEX 0x00000290
43f66a6c
JK		 1313#define CX2_RX_READ_INDEX (0x000002A0)
1314
1315#define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1316#define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1317#define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1318#define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1319#define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1320#define CX2_RX_WRITE_INDEX (0x00000FA0)
1321
1322/*
1323 * EEPROM Related Definitions
1324 */
1325
1326#define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
1327#define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
1328#define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
1329#define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
1330#define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
1331
1332#define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
1333#define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
1334#define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
1335#define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
1336#define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
1337#define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
1338
43f66a6c
JK		 1339#define MSB 1
1340#define LSB 0
1341#define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1342
1343#define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1344 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1345
1346/* EEPROM access by BYTE */
0edd5b44
JG		 1347#define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1348#define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1349#define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1350#define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1351#define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1352#define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1353#define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1354#define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1355#define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1356#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
43f66a6c
JK		 1357
1358/* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
a613bffd
JK		 1359#define EEPROM_NIC_TYPE_0 0
1360#define EEPROM_NIC_TYPE_1 1
1361#define EEPROM_NIC_TYPE_2 2
1362#define EEPROM_NIC_TYPE_3 3
1363#define EEPROM_NIC_TYPE_4 4
43f66a6c
JK		 1364
1365#define FW_MEM_REG_LOWER_BOUND 0x00300000
bf79451e 1366#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
a613bffd 1367#define CX2_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
43f66a6c
JK		 1368#define EEPROM_BIT_SK (1<<0)
1369#define EEPROM_BIT_CS (1<<1)
1370#define EEPROM_BIT_DI (1<<2)
1371#define EEPROM_BIT_DO (1<<4)
1372
1373#define EEPROM_CMD_READ 0x2
1374
1375/* Interrupts masks */
1376#define CX2_INTA_NONE 0x00000000
1377
1378#define CX2_INTA_BIT_RX_TRANSFER 0x00000002
1379#define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
1380#define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1381
1382//Inta Bits for CF
1383#define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
1384#define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
1385#define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
1386#define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
1387#define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
1388
1389#define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1390
1391#define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1392#define CX2_INTA_BIT_POWER_DOWN 0x00200000
1393
1394#define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1395#define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1396#define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
1397#define CX2_INTA_BIT_FATAL_ERROR 0x40000000
1398#define CX2_INTA_BIT_PARITY_ERROR 0x80000000
1399
1400/* Interrupts enabled at init time. */
1401#define CX2_INTA_MASK_ALL \
1402 (CX2_INTA_BIT_TX_QUEUE_1 | \
1403 CX2_INTA_BIT_TX_QUEUE_2 | \
1404 CX2_INTA_BIT_TX_QUEUE_3 | \
1405 CX2_INTA_BIT_TX_QUEUE_4 | \
1406 CX2_INTA_BIT_TX_CMD_QUEUE | \
1407 CX2_INTA_BIT_RX_TRANSFER | \
1408 CX2_INTA_BIT_FATAL_ERROR | \
1409 CX2_INTA_BIT_PARITY_ERROR | \
1410 CX2_INTA_BIT_STATUS_CHANGE | \
1411 CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
1412 CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1413 CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1414 CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1415 CX2_INTA_BIT_POWER_DOWN | \
1416 CX2_INTA_BIT_RF_KILL_DONE )
1417
1418#define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
1419#define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
1420
1421/* FW event log definitions */
1422#define EVENT_ELEM_SIZE (3 * sizeof(u32))
1423#define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1424
1425/* FW error log definitions */
1426#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1427#define ERROR_START_OFFSET (1 * sizeof(u32))
1428
1429enum {
1430 IPW_FW_ERROR_OK = 0,
1431 IPW_FW_ERROR_FAIL,
1432 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1433 IPW_FW_ERROR_MEMORY_OVERFLOW,
1434 IPW_FW_ERROR_BAD_PARAM,
1435 IPW_FW_ERROR_BAD_CHECKSUM,
1436 IPW_FW_ERROR_NMI_INTERRUPT,
1437 IPW_FW_ERROR_BAD_DATABASE,
1438 IPW_FW_ERROR_ALLOC_FAIL,
1439 IPW_FW_ERROR_DMA_UNDERRUN,
1440 IPW_FW_ERROR_DMA_STATUS,
1441 IPW_FW_ERROR_DINOSTATUS_ERROR,
1442 IPW_FW_ERROR_EEPROMSTATUS_ERROR,
1443 IPW_FW_ERROR_SYSASSERT,
1444 IPW_FW_ERROR_FATAL_ERROR
1445};
1446
1447#define AUTH_OPEN 0
1448#define AUTH_SHARED_KEY 1
1449#define AUTH_IGNORE 3
1450
1451#define HC_ASSOCIATE 0
1452#define HC_REASSOCIATE 1
1453#define HC_DISASSOCIATE 2
1454#define HC_IBSS_START 3
1455#define HC_IBSS_RECONF 4
1456#define HC_DISASSOC_QUIET 5
1457
1458#define IPW_RATE_CAPABILITIES 1
1459#define IPW_RATE_CONNECT 0
1460
bf79451e
JG		 1461/*
1462 * Rate values and masks
43f66a6c
JK		 1463 */
1464#define IPW_TX_RATE_1MB 0x0A
1465#define IPW_TX_RATE_2MB 0x14
1466#define IPW_TX_RATE_5MB 0x37
1467#define IPW_TX_RATE_6MB 0x0D
1468#define IPW_TX_RATE_9MB 0x0F
bf79451e 1469#define IPW_TX_RATE_11MB 0x6E
43f66a6c
JK		 1470#define IPW_TX_RATE_12MB 0x05
1471#define IPW_TX_RATE_18MB 0x07
1472#define IPW_TX_RATE_24MB 0x09
1473#define IPW_TX_RATE_36MB 0x0B
1474#define IPW_TX_RATE_48MB 0x01
1475#define IPW_TX_RATE_54MB 0x03
1476
1477#define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1478#define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1479
bf79451e
JG		 1480#define IPW_ORD_TABLE_0_MASK 0x0000F000
1481#define IPW_ORD_TABLE_1_MASK 0x0000F100
1482#define IPW_ORD_TABLE_2_MASK 0x0000F200
1483#define IPW_ORD_TABLE_3_MASK 0x0000F300
1484#define IPW_ORD_TABLE_4_MASK 0x0000F400
1485#define IPW_ORD_TABLE_5_MASK 0x0000F500
1486#define IPW_ORD_TABLE_6_MASK 0x0000F600
1487#define IPW_ORD_TABLE_7_MASK 0x0000F700
43f66a6c
JK		 1488
1489/*
1490 * Table 0 Entries (all entries are 32 bits)
1491 */
bf79451e 1492enum {
43f66a6c
JK		 1493 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1494 IPW_ORD_STAT_FRAG_TRESHOLD,
1495 IPW_ORD_STAT_RTS_THRESHOLD,
bf79451e
JG		 1496 IPW_ORD_STAT_TX_HOST_REQUESTS,
1497 IPW_ORD_STAT_TX_HOST_COMPLETE,
1498 IPW_ORD_STAT_TX_DIR_DATA,
43f66a6c
JK		 1499 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1500 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1501 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1502 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1503 /* Hole */
1504
43f66a6c
JK		 1505 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1506 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1507 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1508 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1509 IPW_ORD_STAT_TX_DIR_DATA_G_9,
bf79451e 1510 IPW_ORD_STAT_TX_DIR_DATA_G_11,
43f66a6c
JK		 1511 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1512 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1513 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1514 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1515 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1516 IPW_ORD_STAT_TX_DIR_DATA_G_54,
bf79451e 1517 IPW_ORD_STAT_TX_NON_DIR_DATA,
43f66a6c
JK		 1518 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1519 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1520 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
bf79451e 1521 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
43f66a6c
JK		 1522 /* Hole */
1523
43f66a6c
JK		 1524 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1525 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1526 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1527 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1528 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
bf79451e 1529 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
43f66a6c
JK		 1530 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1531 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1532 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1533 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1534 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1535 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1536 IPW_ORD_STAT_TX_RETRY,
1537 IPW_ORD_STAT_TX_FAILURE,
1538 IPW_ORD_STAT_RX_ERR_CRC,
1539 IPW_ORD_STAT_RX_ERR_ICV,
1540 IPW_ORD_STAT_RX_NO_BUFFER,
1541 IPW_ORD_STAT_FULL_SCANS,
1542 IPW_ORD_STAT_PARTIAL_SCANS,
1543 IPW_ORD_STAT_TGH_ABORTED_SCANS,
bf79451e 1544 IPW_ORD_STAT_TX_TOTAL_BYTES,
43f66a6c
JK		 1545 IPW_ORD_STAT_CURR_RSSI_RAW,
1546 IPW_ORD_STAT_RX_BEACON,
1547 IPW_ORD_STAT_MISSED_BEACONS,
bf79451e
JG		 1548 IPW_ORD_TABLE_0_LAST
1549};
43f66a6c
JK		 1550
1551#define IPW_RSSI_TO_DBM 112
1552
1553/* Table 1 Entries
1554 */
1555enum {
1556 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1557};
1558
1559/*
1560 * Table 2 Entries
1561 *
1562 * FW_VERSION: 16 byte string
1563 * FW_DATE: 16 byte string (only 14 bytes used)
1564 * UCODE_VERSION: 4 byte version code
1565 * UCODE_DATE: 5 bytes code code
1566 * ADDAPTER_MAC: 6 byte MAC address
1567 * RTC: 4 byte clock
1568 */
bf79451e 1569enum {
43f66a6c 1570 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
bf79451e 1571 IPW_ORD_STAT_FW_DATE,
43f66a6c 1572 IPW_ORD_STAT_UCODE_VERSION,
bf79451e
JG		 1573 IPW_ORD_STAT_UCODE_DATE,
1574 IPW_ORD_STAT_ADAPTER_MAC,
1575 IPW_ORD_STAT_RTC,
1576 IPW_ORD_TABLE_2_LAST
1577};
43f66a6c
JK		 1578
1579/* Table 3 */
1580enum {
1581 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1582 IPW_ORD_STAT_TX_PACKET_FAILURE,
1583 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1584 IPW_ORD_STAT_TX_PACKET_ABORTED,
1585 IPW_ORD_TABLE_3_LAST
1586};
1587
1588/* Table 4 */
1589enum {
1590 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1591};
1592
1593/* Table 5 */
1594enum {
1595 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1596 IPW_ORD_STAT_AP_ASSNS,
1597 IPW_ORD_STAT_ROAM,
1598 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1599 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1600 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1601 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1602 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1603 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1604 IPW_ORD_STAT_LINK_UP,
1605 IPW_ORD_STAT_LINK_DOWN,
1606 IPW_ORD_ANTENNA_DIVERSITY,
1607 IPW_ORD_CURR_FREQ,
1608 IPW_ORD_TABLE_5_LAST
1609};
1610
1611/* Table 6 */
1612enum {
1613 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1614 IPW_ORD_CURR_BSSID,
1615 IPW_ORD_CURR_SSID,
1616 IPW_ORD_TABLE_6_LAST
1617};
1618
1619/* Table 7 */
1620enum {
1621 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1622 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1623 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1624 IPW_ORD_STAT_CURR_RSSI_DBM,
1625 IPW_ORD_TABLE_7_LAST
1626};
1627
1628#define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
1629#define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
1630#define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
1631#define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
1632#define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
1633
1634struct ipw_fixed_rate {
1635 u16 tx_rates;
1636 u16 reserved;
1637} __attribute__ ((packed));
1638
1639#define CX2_INDIRECT_ADDR_MASK (~0x3ul)
1640
1641struct host_cmd {
1642 u8 cmd;
1643 u8 len;
1644 u16 reserved;
1645 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1646} __attribute__ ((packed));
1647
1648#define CFG_BT_COEXISTENCE_MIN 0x00
1649#define CFG_BT_COEXISTENCE_DEFER 0x02
1650#define CFG_BT_COEXISTENCE_KILL 0x04
1651#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1652#define CFG_BT_COEXISTENCE_OOB 0x10
1653#define CFG_BT_COEXISTENCE_MAX 0xFF
0edd5b44 1654#define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM */
43f66a6c
JK		 1655
1656#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1657#define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1658#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1659
1660#define CFG_SYS_ANTENNA_BOTH 0x000
1661#define CFG_SYS_ANTENNA_A 0x001
1662#define CFG_SYS_ANTENNA_B 0x003
1663
1664/*
bf79451e 1665 * The definitions below were lifted off the ipw2100 driver, which only
43f66a6c 1666 * supports 'b' mode, so I'm sure these are not exactly correct.
bf79451e 1667 *
43f66a6c
JK		 1668 * Somebody fix these!!
1669 */
1670#define REG_MIN_CHANNEL 0
1671#define REG_MAX_CHANNEL 14
1672
1673#define REG_CHANNEL_MASK 0x00003FFF
1674#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1675
bf79451e
JG		 1676static const long ipw_frequencies[] = {
1677 2412, 2417, 2422, 2427,
1678 2432, 2437, 2442, 2447,
1679 2452, 2457, 2462, 2467,
1680 2472, 2484
43f66a6c
JK		 1681};
1682
1683#define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
1684
1685#define IPW_MAX_CONFIG_RETRIES 10
1686
0dacca1f 1687static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr)
43f66a6c
JK		 1688{
1689 u32 retval;
1690 u16 fc;
1691
0dacca1f 1692 retval = sizeof(struct ieee80211_hdr_3addr);
43f66a6c
JK		 1693 fc = le16_to_cpu(hdr->frame_ctl);
1694
1695 /*
0edd5b44
JG		 1696 * Function ToDS FromDS
1697 * IBSS 0 0
1698 * To AP 1 0
1699 * From AP 0 1
1700 * WDS (bridge) 1 1
43f66a6c
JK		 1701 *
1702 * Only WDS frames use Address4 among them. --YZ
1703 */
1704 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1705 retval -= ETH_ALEN;
1706
1707 return retval;
1708}
1709
0edd5b44 1710#endif /* __ipw2200_h__ */
Linux kernel - Deliverables
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