iwl3945: do not print RFKILL message
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 3945-mac.c
CommitLineData
4bc85c13
WYG
1/******************************************************************************
2 *
be663ab6 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4bc85c13
WYG
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
4bc85c13
WYG
43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/ieee80211_radiotap.h>
48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
52#define DRV_NAME "iwl3945"
53
d4459a99 54#include "commands.h"
98613be0 55#include "common.h"
e94a4099 56#include "3945.h"
4bc85c13 57#include "iwl-spectrum.h"
4bc85c13
WYG
58
59/*
60 * module name, copyright, version, etc.
61 */
62
63#define DRV_DESCRIPTION \
64"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
65
d3175167 66#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
67#define VD "d"
68#else
69#define VD
70#endif
71
72/*
73 * add "s" to indicate spectrum measurement included.
74 * we add it here to be consistent with previous releases in which
75 * this was configurable.
76 */
77#define DRV_VERSION IWLWIFI_VERSION VD "s"
be663ab6 78#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
4bc85c13
WYG
79#define DRV_AUTHOR "<ilw@linux.intel.com>"
80
81MODULE_DESCRIPTION(DRV_DESCRIPTION);
82MODULE_VERSION(DRV_VERSION);
83MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
84MODULE_LICENSE("GPL");
85
86 /* module parameters */
e2ebc833 87struct il_mod_params il3945_mod_params = {
4bc85c13
WYG
88 .sw_crypto = 1,
89 .restart_fw = 1,
0263aa45 90 .disable_hw_scan = 1,
4bc85c13
WYG
91 /* the rest are 0 by default */
92};
93
94/**
e2ebc833 95 * il3945_get_antenna_flags - Get antenna flags for RXON command
46bc8d4b 96 * @il: eeprom and antenna fields are used to determine antenna flags
4bc85c13 97 *
46bc8d4b 98 * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
e2ebc833 99 * il3945_mod_params.antenna specifies the antenna diversity mode:
4bc85c13 100 *
e2ebc833
SG
101 * IL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
102 * IL_ANTENNA_MAIN - Force MAIN antenna
103 * IL_ANTENNA_AUX - Force AUX antenna
4bc85c13 104 */
e7392364
SG
105__le32
106il3945_get_antenna_flags(const struct il_priv *il)
4bc85c13 107{
46bc8d4b 108 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 109
e2ebc833
SG
110 switch (il3945_mod_params.antenna) {
111 case IL_ANTENNA_DIVERSITY:
4bc85c13
WYG
112 return 0;
113
e2ebc833 114 case IL_ANTENNA_MAIN:
4bc85c13
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115 if (eeprom->antenna_switch_type)
116 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
118
e2ebc833 119 case IL_ANTENNA_AUX:
4bc85c13
WYG
120 if (eeprom->antenna_switch_type)
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
123 }
124
125 /* bad antenna selector value */
9406f797 126 IL_ERR("Bad antenna selector value (0x%x)\n",
e7392364 127 il3945_mod_params.antenna);
4bc85c13
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128
129 return 0; /* "diversity" is default if error */
130}
131
e7392364
SG
132static int
133il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
134 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
135{
136 unsigned long flags;
137 __le16 key_flags = 0;
138 int ret;
139
140 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
141 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
142
b16db50a 143 if (sta_id == il->hw_params.bcast_id)
4bc85c13
WYG
144 key_flags |= STA_KEY_MULTICAST_MSK;
145
146 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
147 keyconf->hw_key_idx = keyconf->keyidx;
148 key_flags &= ~STA_KEY_FLG_INVALID;
149
46bc8d4b
SG
150 spin_lock_irqsave(&il->sta_lock, flags);
151 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
152 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
e7392364 153 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
4bc85c13 154
e7392364 155 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
4bc85c13 156
e7392364
SG
157 if ((il->stations[sta_id].sta.key.
158 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
46bc8d4b 159 il->stations[sta_id].sta.key.key_offset =
e7392364 160 il_get_free_ucode_key_idx(il);
4bc85c13 161 /* else, we are overriding an existing key => no need to allocated room
e7392364 162 * in uCode. */
4bc85c13 163
46bc8d4b 164 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 165 "no space for a new key");
4bc85c13 166
46bc8d4b
SG
167 il->stations[sta_id].sta.key.key_flags = key_flags;
168 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
169 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4bc85c13 170
58de00a4 171 D_INFO("hwcrypto: modify ucode station key info\n");
4bc85c13 172
e7392364 173 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
4bc85c13 174
46bc8d4b 175 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
176
177 return ret;
178}
179
e7392364
SG
180static int
181il3945_set_tkip_dynamic_key_info(struct il_priv *il,
182 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
183{
184 return -EOPNOTSUPP;
185}
186
e7392364
SG
187static int
188il3945_set_wep_dynamic_key_info(struct il_priv *il,
189 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
190{
191 return -EOPNOTSUPP;
192}
193
e7392364
SG
194static int
195il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
4bc85c13
WYG
196{
197 unsigned long flags;
e2ebc833 198 struct il_addsta_cmd sta_cmd;
4bc85c13 199
46bc8d4b
SG
200 spin_lock_irqsave(&il->sta_lock, flags);
201 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
e7392364 202 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
46bc8d4b
SG
203 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
204 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
205 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364
SG
206 memcpy(&sta_cmd, &il->stations[sta_id].sta,
207 sizeof(struct il_addsta_cmd));
46bc8d4b 208 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13 209
58de00a4 210 D_INFO("hwcrypto: clear ucode station key info\n");
46bc8d4b 211 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
4bc85c13
WYG
212}
213
e7392364
SG
214static int
215il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
216 u8 sta_id)
4bc85c13
WYG
217{
218 int ret = 0;
219
220 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
221
222 switch (keyconf->cipher) {
223 case WLAN_CIPHER_SUITE_CCMP:
46bc8d4b 224 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
WYG
225 break;
226 case WLAN_CIPHER_SUITE_TKIP:
46bc8d4b 227 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
WYG
228 break;
229 case WLAN_CIPHER_SUITE_WEP40:
230 case WLAN_CIPHER_SUITE_WEP104:
46bc8d4b 231 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
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232 break;
233 default:
e7392364 234 IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
4bc85c13
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235 ret = -EINVAL;
236 }
237
58de00a4 238 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
e7392364 239 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
4bc85c13
WYG
240
241 return ret;
242}
243
e7392364
SG
244static int
245il3945_remove_static_key(struct il_priv *il)
4bc85c13
WYG
246{
247 int ret = -EOPNOTSUPP;
248
249 return ret;
250}
251
e7392364
SG
252static int
253il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
4bc85c13
WYG
254{
255 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
256 key->cipher == WLAN_CIPHER_SUITE_WEP104)
257 return -EOPNOTSUPP;
258
9406f797 259 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
4bc85c13
WYG
260 return -EINVAL;
261}
262
e7392364
SG
263static void
264il3945_clear_free_frames(struct il_priv *il)
4bc85c13
WYG
265{
266 struct list_head *element;
267
e7392364 268 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
4bc85c13 269
46bc8d4b
SG
270 while (!list_empty(&il->free_frames)) {
271 element = il->free_frames.next;
4bc85c13 272 list_del(element);
e2ebc833 273 kfree(list_entry(element, struct il3945_frame, list));
46bc8d4b 274 il->frames_count--;
4bc85c13
WYG
275 }
276
46bc8d4b 277 if (il->frames_count) {
9406f797 278 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 279 il->frames_count);
46bc8d4b 280 il->frames_count = 0;
4bc85c13
WYG
281 }
282}
283
e7392364
SG
284static struct il3945_frame *
285il3945_get_free_frame(struct il_priv *il)
4bc85c13 286{
e2ebc833 287 struct il3945_frame *frame;
4bc85c13 288 struct list_head *element;
46bc8d4b 289 if (list_empty(&il->free_frames)) {
4bc85c13
WYG
290 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
291 if (!frame) {
9406f797 292 IL_ERR("Could not allocate frame!\n");
4bc85c13
WYG
293 return NULL;
294 }
295
46bc8d4b 296 il->frames_count++;
4bc85c13
WYG
297 return frame;
298 }
299
46bc8d4b 300 element = il->free_frames.next;
4bc85c13 301 list_del(element);
e2ebc833 302 return list_entry(element, struct il3945_frame, list);
4bc85c13
WYG
303}
304
e7392364
SG
305static void
306il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
4bc85c13
WYG
307{
308 memset(frame, 0, sizeof(*frame));
46bc8d4b 309 list_add(&frame->list, &il->free_frames);
4bc85c13
WYG
310}
311
e7392364
SG
312unsigned int
313il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
314 int left)
4bc85c13
WYG
315{
316
7c2cde2e 317 if (!il_is_associated(il) || !il->beacon_skb)
4bc85c13
WYG
318 return 0;
319
46bc8d4b 320 if (il->beacon_skb->len > left)
4bc85c13
WYG
321 return 0;
322
46bc8d4b 323 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
4bc85c13 324
46bc8d4b 325 return il->beacon_skb->len;
4bc85c13
WYG
326}
327
e7392364
SG
328static int
329il3945_send_beacon_cmd(struct il_priv *il)
4bc85c13 330{
e2ebc833 331 struct il3945_frame *frame;
4bc85c13
WYG
332 unsigned int frame_size;
333 int rc;
334 u8 rate;
335
46bc8d4b 336 frame = il3945_get_free_frame(il);
4bc85c13
WYG
337
338 if (!frame) {
9406f797 339 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 340 "command.\n");
4bc85c13
WYG
341 return -ENOMEM;
342 }
343
83007196 344 rate = il_get_lowest_plcp(il);
4bc85c13 345
46bc8d4b 346 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
4bc85c13 347
e7392364 348 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
4bc85c13 349
46bc8d4b 350 il3945_free_frame(il, frame);
4bc85c13
WYG
351
352 return rc;
353}
354
e7392364
SG
355static void
356il3945_unset_hw_params(struct il_priv *il)
4bc85c13 357{
46bc8d4b
SG
358 if (il->_3945.shared_virt)
359 dma_free_coherent(&il->pci_dev->dev,
e2ebc833 360 sizeof(struct il3945_shared),
e7392364 361 il->_3945.shared_virt, il->_3945.shared_phys);
4bc85c13
WYG
362}
363
e7392364
SG
364static void
365il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
366 struct il_device_cmd *cmd,
367 struct sk_buff *skb_frag, int sta_id)
4bc85c13 368{
e2ebc833 369 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
46bc8d4b 370 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
4bc85c13
WYG
371
372 tx_cmd->sec_ctl = 0;
373
374 switch (keyinfo->cipher) {
375 case WLAN_CIPHER_SUITE_CCMP:
376 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
377 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
58de00a4 378 D_TX("tx_cmd with AES hwcrypto\n");
4bc85c13
WYG
379 break;
380
381 case WLAN_CIPHER_SUITE_TKIP:
382 break;
383
384 case WLAN_CIPHER_SUITE_WEP104:
385 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
386 /* fall through */
387 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG
388 tx_cmd->sec_ctl |=
389 TX_CMD_SEC_WEP | (info->control.hw_key->
390 hw_key_idx & TX_CMD_SEC_MSK) <<
391 TX_CMD_SEC_SHIFT;
4bc85c13
WYG
392
393 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
394
e7392364
SG
395 D_TX("Configuring packet for WEP encryption " "with key %d\n",
396 info->control.hw_key->hw_key_idx);
4bc85c13
WYG
397 break;
398
399 default:
9406f797 400 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
4bc85c13
WYG
401 break;
402 }
403}
404
405/*
4d69c752 406 * handle build C_TX command notification.
4bc85c13 407 */
e7392364
SG
408static void
409il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
410 struct ieee80211_tx_info *info,
411 struct ieee80211_hdr *hdr, u8 std_id)
4bc85c13 412{
e2ebc833 413 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
4bc85c13
WYG
414 __le32 tx_flags = tx_cmd->tx_flags;
415 __le16 fc = hdr->frame_control;
416
417 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
418 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
419 tx_flags |= TX_CMD_FLG_ACK_MSK;
420 if (ieee80211_is_mgmt(fc))
421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
422 if (ieee80211_is_probe_resp(fc) &&
423 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
424 tx_flags |= TX_CMD_FLG_TSF_MSK;
425 } else {
426 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
427 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
428 }
429
430 tx_cmd->sta_id = std_id;
431 if (ieee80211_has_morefrags(fc))
432 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
433
434 if (ieee80211_is_data_qos(fc)) {
435 u8 *qc = ieee80211_get_qos_ctl(hdr);
436 tx_cmd->tid_tspec = qc[0] & 0xf;
437 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
438 } else {
439 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
440 }
441
46bc8d4b 442 il_tx_cmd_protection(il, info, fc, &tx_flags);
4bc85c13
WYG
443
444 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
445 if (ieee80211_is_mgmt(fc)) {
446 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
447 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
448 else
449 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
450 } else {
451 tx_cmd->timeout.pm_frame_timeout = 0;
452 }
453
454 tx_cmd->driver_txop = 0;
455 tx_cmd->tx_flags = tx_flags;
456 tx_cmd->next_frame_len = 0;
457}
458
459/*
4d69c752 460 * start C_TX command process
4bc85c13 461 */
e7392364 462static int
36323f81
TH
463il3945_tx_skb(struct il_priv *il,
464 struct ieee80211_sta *sta,
465 struct sk_buff *skb)
4bc85c13
WYG
466{
467 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e2ebc833
SG
469 struct il3945_tx_cmd *tx_cmd;
470 struct il_tx_queue *txq = NULL;
471 struct il_queue *q = NULL;
472 struct il_device_cmd *out_cmd;
473 struct il_cmd_meta *out_meta;
4bc85c13
WYG
474 dma_addr_t phys_addr;
475 dma_addr_t txcmd_phys;
476 int txq_id = skb_get_queue_mapping(skb);
477 u16 len, idx, hdr_len;
7f42ace3 478 u16 firstlen, secondlen;
4bc85c13
WYG
479 u8 id;
480 u8 unicast;
481 u8 sta_id;
482 u8 tid = 0;
483 __le16 fc;
484 u8 wait_write_ptr = 0;
485 unsigned long flags;
486
46bc8d4b
SG
487 spin_lock_irqsave(&il->lock, flags);
488 if (il_is_rfkill(il)) {
58de00a4 489 D_DROP("Dropping - RF KILL\n");
4bc85c13
WYG
490 goto drop_unlock;
491 }
492
e7392364
SG
493 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
494 IL_INVALID_RATE) {
9406f797 495 IL_ERR("ERROR: No TX rate available.\n");
4bc85c13
WYG
496 goto drop_unlock;
497 }
498
499 unicast = !is_multicast_ether_addr(hdr->addr1);
500 id = 0;
501
502 fc = hdr->frame_control;
503
d3175167 504#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13 505 if (ieee80211_is_auth(fc))
58de00a4 506 D_TX("Sending AUTH frame\n");
4bc85c13 507 else if (ieee80211_is_assoc_req(fc))
58de00a4 508 D_TX("Sending ASSOC frame\n");
4bc85c13 509 else if (ieee80211_is_reassoc_req(fc))
58de00a4 510 D_TX("Sending REASSOC frame\n");
4bc85c13
WYG
511#endif
512
46bc8d4b 513 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
514
515 hdr_len = ieee80211_hdrlen(fc);
516
0c2c8852 517 /* Find idx into station table for destination station */
36323f81 518 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 519 if (sta_id == IL_INVALID_STATION) {
e7392364 520 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
4bc85c13
WYG
521 goto drop;
522 }
523
58de00a4 524 D_RATE("station Id %d\n", sta_id);
4bc85c13
WYG
525
526 if (ieee80211_is_data_qos(fc)) {
527 u8 *qc = ieee80211_get_qos_ctl(hdr);
528 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
529 if (unlikely(tid >= MAX_TID_COUNT))
530 goto drop;
531 }
532
533 /* Descriptor for chosen Tx queue */
46bc8d4b 534 txq = &il->txq[txq_id];
4bc85c13
WYG
535 q = &txq->q;
536
e2ebc833 537 if ((il_queue_space(q) < q->high_mark))
4bc85c13
WYG
538 goto drop;
539
46bc8d4b 540 spin_lock_irqsave(&il->lock, flags);
4bc85c13 541
0c2c8852 542 idx = il_get_cmd_idx(q, q->write_ptr, 0);
4bc85c13 543
00ea99e1 544 txq->skbs[q->write_ptr] = skb;
4bc85c13
WYG
545
546 /* Init first empty entry in queue's array of Tx/cmd buffers */
547 out_cmd = txq->cmd[idx];
548 out_meta = &txq->meta[idx];
e2ebc833 549 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
4bc85c13
WYG
550 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
551 memset(tx_cmd, 0, sizeof(*tx_cmd));
552
553 /*
554 * Set up the Tx-command (not MAC!) header.
0c2c8852 555 * Store the chosen Tx queue and TFD idx within the sequence field;
4bc85c13
WYG
556 * after Tx, uCode's Tx response will return this value so driver can
557 * locate the frame within the tx queue and do post-tx processing.
558 */
4d69c752 559 out_cmd->hdr.cmd = C_TX;
e7392364
SG
560 out_cmd->hdr.sequence =
561 cpu_to_le16((u16)
562 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
4bc85c13
WYG
563
564 /* Copy MAC header from skb into command buffer */
565 memcpy(tx_cmd->hdr, hdr, hdr_len);
566
4bc85c13 567 if (info->control.hw_key)
46bc8d4b 568 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
4bc85c13
WYG
569
570 /* TODO need this for burst mode later on */
46bc8d4b 571 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
4bc85c13 572
81fb4613 573 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
4bc85c13
WYG
574
575 /* Total # bytes to be transmitted */
bdb084b2 576 tx_cmd->len = cpu_to_le16((u16) skb->len);
4bc85c13 577
4bc85c13
WYG
578 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
579 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
580
4bc85c13
WYG
581 /*
582 * Use the first empty entry in this queue's command buffer array
583 * to contain the Tx command and MAC header concatenated together
584 * (payload data will be in another buffer).
585 * Size of this varies, due to varying MAC header length.
586 * If end is not dword aligned, we'll have 2 extra bytes at the end
587 * of the MAC header (device reads on dword boundaries).
588 * We'll tell device about this padding later.
589 */
e7392364
SG
590 len =
591 sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
592 hdr_len;
7f42ace3 593 firstlen = (len + 3) & ~3;
4bc85c13
WYG
594
595 /* Physical address of this Tx command's header (not MAC header!),
596 * within command buffer array. */
e7392364 597 txcmd_phys =
7f42ace3
SG
598 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
599 PCI_DMA_TODEVICE);
bdb084b2
SG
600 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
601 goto drop_unlock;
4bc85c13
WYG
602
603 /* Set up TFD's 2nd entry to point directly to remainder of skb,
604 * if any (802.11 null frames have no payload). */
7f42ace3
SG
605 secondlen = skb->len - hdr_len;
606 if (secondlen > 0) {
e7392364 607 phys_addr =
7f42ace3 608 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
e7392364 609 PCI_DMA_TODEVICE);
bdb084b2
SG
610 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
611 goto drop_unlock;
612 }
613
614 /* Add buffer containing Tx command and MAC(!) header to TFD's
615 * first entry */
7f42ace3 616 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
bdb084b2 617 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
7f42ace3
SG
618 dma_unmap_len_set(out_meta, len, firstlen);
619 if (secondlen > 0)
620 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
621 U32_PAD(secondlen));
bdb084b2
SG
622
623 if (!ieee80211_has_morefrags(hdr->frame_control)) {
624 txq->need_update = 1;
625 } else {
626 wait_write_ptr = 1;
627 txq->need_update = 0;
4bc85c13
WYG
628 }
629
bdb084b2
SG
630 il_update_stats(il, true, fc, skb->len);
631
632 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
633 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
634 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
635 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
636 ieee80211_hdrlen(fc));
637
0c2c8852 638 /* Tell device the write idx *just past* this latest filled TFD */
e2ebc833 639 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
46bc8d4b
SG
640 il_txq_update_write_ptr(il, txq);
641 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 642
e7392364 643 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
4bc85c13 644 if (wait_write_ptr) {
46bc8d4b 645 spin_lock_irqsave(&il->lock, flags);
4bc85c13 646 txq->need_update = 1;
46bc8d4b
SG
647 il_txq_update_write_ptr(il, txq);
648 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
649 }
650
46bc8d4b 651 il_stop_queue(il, txq);
4bc85c13
WYG
652 }
653
654 return 0;
655
656drop_unlock:
46bc8d4b 657 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
658drop:
659 return -1;
660}
661
e7392364
SG
662static int
663il3945_get_measurement(struct il_priv *il,
664 struct ieee80211_measurement_params *params, u8 type)
4bc85c13 665{
e2ebc833 666 struct il_spectrum_cmd spectrum;
dcae1c64 667 struct il_rx_pkt *pkt;
e2ebc833 668 struct il_host_cmd cmd = {
4d69c752 669 .id = C_SPECTRUM_MEASUREMENT,
4bc85c13
WYG
670 .data = (void *)&spectrum,
671 .flags = CMD_WANT_SKB,
672 };
673 u32 add_time = le64_to_cpu(params->start_time);
674 int rc;
675 int spectrum_resp_status;
676 int duration = le16_to_cpu(params->duration);
4bc85c13 677
7c2cde2e 678 if (il_is_associated(il))
e7392364
SG
679 add_time =
680 il_usecs_to_beacons(il,
681 le64_to_cpu(params->start_time) -
682 il->_3945.last_tsf,
c8b03958 683 le16_to_cpu(il->timing.beacon_interval));
4bc85c13
WYG
684
685 memset(&spectrum, 0, sizeof(spectrum));
686
687 spectrum.channel_count = cpu_to_le16(1);
688 spectrum.flags =
689 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
690 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
691 cmd.len = sizeof(spectrum);
692 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
693
7c2cde2e 694 if (il_is_associated(il))
4bc85c13 695 spectrum.start_time =
e7392364 696 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
c8b03958 697 le16_to_cpu(il->timing.beacon_interval));
4bc85c13
WYG
698 else
699 spectrum.start_time = 0;
700
701 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
702 spectrum.channels[0].channel = params->channel;
703 spectrum.channels[0].type = type;
c8b03958 704 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
e7392364
SG
705 spectrum.flags |=
706 RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
707 RXON_FLG_TGG_PROTECT_MSK;
4bc85c13 708
46bc8d4b 709 rc = il_send_cmd_sync(il, &cmd);
4bc85c13
WYG
710 if (rc)
711 return rc;
712
dcae1c64 713 pkt = (struct il_rx_pkt *)cmd.reply_page;
e2ebc833 714 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
4d69c752 715 IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
4bc85c13
WYG
716 rc = -EIO;
717 }
718
719 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
720 switch (spectrum_resp_status) {
721 case 0: /* Command will be handled */
722 if (pkt->u.spectrum.id != 0xff) {
58de00a4 723 D_INFO("Replaced existing measurement: %d\n",
e7392364 724 pkt->u.spectrum.id);
46bc8d4b 725 il->measurement_status &= ~MEASUREMENT_READY;
4bc85c13 726 }
46bc8d4b 727 il->measurement_status |= MEASUREMENT_ACTIVE;
4bc85c13
WYG
728 rc = 0;
729 break;
730
731 case 1: /* Command will not be handled */
732 rc = -EAGAIN;
733 break;
734 }
735
46bc8d4b 736 il_free_pages(il, cmd.reply_page);
4bc85c13
WYG
737
738 return rc;
739}
740
e7392364
SG
741static void
742il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 743{
dcae1c64 744 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 745 struct il_alive_resp *palive;
4bc85c13
WYG
746 struct delayed_work *pwork;
747
748 palive = &pkt->u.alive_frame;
749
e7392364
SG
750 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
751 palive->is_valid, palive->ver_type, palive->ver_subtype);
4bc85c13
WYG
752
753 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 754 D_INFO("Initialization Alive received.\n");
46bc8d4b 755 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 756 sizeof(struct il_alive_resp));
46bc8d4b 757 pwork = &il->init_alive_start;
4bc85c13 758 } else {
58de00a4 759 D_INFO("Runtime Alive received.\n");
46bc8d4b 760 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 761 sizeof(struct il_alive_resp));
46bc8d4b
SG
762 pwork = &il->alive_start;
763 il3945_disable_events(il);
4bc85c13
WYG
764 }
765
766 /* We delay the ALIVE response by 5ms to
767 * give the HW RF Kill time to activate... */
768 if (palive->is_valid == UCODE_VALID_OK)
e7392364 769 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
4bc85c13 770 else
9406f797 771 IL_WARN("uCode did not respond OK.\n");
4bc85c13
WYG
772}
773
e7392364
SG
774static void
775il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 776{
d3175167 777#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 778 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13
WYG
779#endif
780
4d69c752 781 D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
4bc85c13
WYG
782}
783
e7392364
SG
784static void
785il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 786{
dcae1c64 787 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 788 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
d3175167 789#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
790 u8 rate = beacon->beacon_notify_hdr.rate;
791
e7392364
SG
792 D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
793 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
794 beacon->beacon_notify_hdr.failure_frame,
795 le32_to_cpu(beacon->ibss_mgr_status),
796 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
4bc85c13
WYG
797#endif
798
46bc8d4b 799 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
4bc85c13 800
4bc85c13
WYG
801}
802
803/* Handle notification from uCode that card's power state is changing
804 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG
805static void
806il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 807{
dcae1c64 808 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13 809 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 810 unsigned long status = il->status;
4bc85c13 811
9406f797 812 IL_WARN("Card state received: HW:%s SW:%s\n",
e7392364
SG
813 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
814 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
4bc85c13 815
e7392364 816 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4bc85c13
WYG
817
818 if (flags & HW_CARD_DISABLED)
bc269a8e 819 set_bit(S_RFKILL, &il->status);
4bc85c13 820 else
bc269a8e 821 clear_bit(S_RFKILL, &il->status);
4bc85c13 822
46bc8d4b 823 il_scan_cancel(il);
4bc85c13 824
bc269a8e
SG
825 if ((test_bit(S_RFKILL, &status) !=
826 test_bit(S_RFKILL, &il->status)))
46bc8d4b 827 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 828 test_bit(S_RFKILL, &il->status));
4bc85c13 829 else
46bc8d4b 830 wake_up(&il->wait_command_queue);
4bc85c13
WYG
831}
832
833/**
d0c72347 834 * il3945_setup_handlers - Initialize Rx handler callbacks
4bc85c13
WYG
835 *
836 * Setup the RX handlers for each of the reply types sent from the uCode
837 * to the host.
838 *
839 * This function chains into the hardware specific files for them to setup
840 * any hardware specific handlers as well.
841 */
e7392364
SG
842static void
843il3945_setup_handlers(struct il_priv *il)
4bc85c13 844{
6e9848b4
SG
845 il->handlers[N_ALIVE] = il3945_hdl_alive;
846 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
847 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 848 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 849 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 850 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 851 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 852 il->handlers[N_BEACON] = il3945_hdl_beacon;
4bc85c13
WYG
853
854 /*
855 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG
856 * stats request from the host as well as for the periodic
857 * stats notifications (after received beacons) from the uCode.
4bc85c13 858 */
d2dfb33e
SG
859 il->handlers[C_STATS] = il3945_hdl_c_stats;
860 il->handlers[N_STATS] = il3945_hdl_stats;
4bc85c13 861
46bc8d4b 862 il_setup_rx_scan_handlers(il);
d2dfb33e 863 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
4bc85c13
WYG
864
865 /* Set up hardware specific Rx handlers */
d0c72347 866 il3945_hw_handler_setup(il);
4bc85c13
WYG
867}
868
869/************************** RX-FUNCTIONS ****************************/
870/*
871 * Rx theory of operation
872 *
873 * The host allocates 32 DMA target addresses and passes the host address
3b98c7f4 874 * to the firmware at register IL_RFDS_TBL_LOWER + N * RFD_SIZE where N is
4bc85c13
WYG
875 * 0 to 31
876 *
877 * Rx Queue Indexes
0c2c8852 878 * The host/firmware share two idx registers for managing the Rx buffers.
4bc85c13 879 *
0c2c8852 880 * The READ idx maps to the first position that the firmware may be writing
4bc85c13
WYG
881 * to -- the driver can read up to (but not including) this position and get
882 * good data.
0c2c8852 883 * The READ idx is managed by the firmware once the card is enabled.
4bc85c13 884 *
0c2c8852 885 * The WRITE idx maps to the last position the driver has read from -- the
4bc85c13
WYG
886 * position preceding WRITE is the last slot the firmware can place a packet.
887 *
888 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
889 * WRITE = READ.
890 *
891 * During initialization, the host sets up the READ queue position to the first
2d09b062 892 * IDX position, and WRITE to the last (READ - 1 wrapped)
4bc85c13 893 *
0c2c8852
SG
894 * When the firmware places a packet in a buffer, it will advance the READ idx
895 * and fire the RX interrupt. The driver can then query the READ idx and
896 * process as many packets as possible, moving the WRITE idx forward as it
4bc85c13
WYG
897 * resets the Rx queue buffers with new memory.
898 *
899 * The management in the driver is as follows:
900 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
901 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
902 * to replenish the iwl->rxq->rx_free.
e2ebc833 903 * + In il3945_rx_replenish (scheduled) if 'processed' != 'read' then the
2d09b062 904 * iwl->rxq is replenished and the READ IDX is updated (updating the
0c2c8852 905 * 'processed' and 'read' driver idxes as well)
4bc85c13 906 * + A received packet is processed and handed to the kernel network stack,
0c2c8852 907 * detached from the iwl->rxq. The driver 'processed' idx is updated.
4bc85c13
WYG
908 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
909 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2d09b062 910 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
4bc85c13
WYG
911 * were enough free buffers and RX_STALLED is set it is cleared.
912 *
913 *
914 * Driver sequence:
915 *
e2ebc833
SG
916 * il3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
917 * il3945_rx_queue_restock
918 * il3945_rx_queue_restock() Moves available buffers from rx_free into Rx
4bc85c13 919 * queue, updates firmware pointers, and updates
0c2c8852 920 * the WRITE idx. If insufficient rx_free buffers
e2ebc833 921 * are available, schedules il3945_rx_replenish
4bc85c13
WYG
922 *
923 * -- enable interrupts --
b73bb5f1 924 * ISR - il3945_rx() Detach il_rx_bufs from pool up to the
2d09b062 925 * READ IDX, detaching the SKB from the pool.
4bc85c13 926 * Moves the packet buffer from queue to rx_used.
e2ebc833 927 * Calls il3945_rx_queue_restock to refill any empty
4bc85c13
WYG
928 * slots.
929 * ...
930 *
931 */
932
933/**
e2ebc833 934 * il3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
4bc85c13 935 */
e7392364
SG
936static inline __le32
937il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
4bc85c13 938{
e7392364 939 return cpu_to_le32((u32) dma_addr);
4bc85c13
WYG
940}
941
942/**
e2ebc833 943 * il3945_rx_queue_restock - refill RX queue from pre-allocated pool
4bc85c13
WYG
944 *
945 * If there are slots in the RX queue that need to be restocked,
946 * and we have free pre-allocated buffers, fill the ranks as much
947 * as we can, pulling from rx_free.
948 *
0c2c8852 949 * This moves the 'write' idx forward to catch up with 'processed', and
4bc85c13
WYG
950 * also updates the memory address in the firmware to reference the new
951 * target buffer.
952 */
e7392364
SG
953static void
954il3945_rx_queue_restock(struct il_priv *il)
4bc85c13 955{
46bc8d4b 956 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 957 struct list_head *element;
b73bb5f1 958 struct il_rx_buf *rxb;
4bc85c13
WYG
959 unsigned long flags;
960 int write;
961
962 spin_lock_irqsave(&rxq->lock, flags);
963 write = rxq->write & ~0x7;
232913b5 964 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
4bc85c13
WYG
965 /* Get next free Rx buffer, remove from free list */
966 element = rxq->rx_free.next;
b73bb5f1 967 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13
WYG
968 list_del(element);
969
970 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG
971 rxq->bd[rxq->write] =
972 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
4bc85c13
WYG
973 rxq->queue[rxq->write] = rxb;
974 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
975 rxq->free_count--;
976 }
977 spin_unlock_irqrestore(&rxq->lock, flags);
978 /* If the pre-allocated buffer pool is dropping low, schedule to
979 * refill it */
980 if (rxq->free_count <= RX_LOW_WATERMARK)
46bc8d4b 981 queue_work(il->workqueue, &il->rx_replenish);
4bc85c13 982
4bc85c13
WYG
983 /* If we've added more space for the firmware to place data, tell it.
984 * Increment device's write pointer in multiples of 8. */
232913b5
SG
985 if (rxq->write_actual != (rxq->write & ~0x7) ||
986 abs(rxq->write - rxq->read) > 7) {
4bc85c13
WYG
987 spin_lock_irqsave(&rxq->lock, flags);
988 rxq->need_update = 1;
989 spin_unlock_irqrestore(&rxq->lock, flags);
46bc8d4b 990 il_rx_queue_update_write_ptr(il, rxq);
4bc85c13
WYG
991 }
992}
993
994/**
e2ebc833 995 * il3945_rx_replenish - Move all used packet from rx_used to rx_free
4bc85c13
WYG
996 *
997 * When moving to rx_free an SKB is allocated for the slot.
998 *
e2ebc833 999 * Also restock the Rx queue via il3945_rx_queue_restock.
4bc85c13
WYG
1000 * This is called as a scheduled work item (except for during initialization)
1001 */
e7392364
SG
1002static void
1003il3945_rx_allocate(struct il_priv *il, gfp_t priority)
4bc85c13 1004{
46bc8d4b 1005 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 1006 struct list_head *element;
b73bb5f1 1007 struct il_rx_buf *rxb;
4bc85c13 1008 struct page *page;
96ebbe8d 1009 dma_addr_t page_dma;
4bc85c13
WYG
1010 unsigned long flags;
1011 gfp_t gfp_mask = priority;
1012
1013 while (1) {
1014 spin_lock_irqsave(&rxq->lock, flags);
4bc85c13
WYG
1015 if (list_empty(&rxq->rx_used)) {
1016 spin_unlock_irqrestore(&rxq->lock, flags);
1017 return;
1018 }
1019 spin_unlock_irqrestore(&rxq->lock, flags);
1020
1021 if (rxq->free_count > RX_LOW_WATERMARK)
1022 gfp_mask |= __GFP_NOWARN;
1023
46bc8d4b 1024 if (il->hw_params.rx_page_order > 0)
4bc85c13
WYG
1025 gfp_mask |= __GFP_COMP;
1026
1027 /* Alloc a new receive buffer */
46bc8d4b 1028 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
4bc85c13
WYG
1029 if (!page) {
1030 if (net_ratelimit())
58de00a4 1031 D_INFO("Failed to allocate SKB buffer.\n");
232913b5 1032 if (rxq->free_count <= RX_LOW_WATERMARK &&
4bc85c13 1033 net_ratelimit())
1722f8e1
SG
1034 IL_ERR("Failed to allocate SKB buffer with %0x."
1035 "Only %u free buffers remaining.\n",
1036 priority, rxq->free_count);
4bc85c13
WYG
1037 /* We don't reschedule replenish work here -- we will
1038 * call the restock method and if it still needs
1039 * more buffers it will schedule replenish */
1040 break;
1041 }
1042
96ebbe8d
SG
1043 /* Get physical address of RB/SKB */
1044 page_dma =
1045 pci_map_page(il->pci_dev, page, 0,
1046 PAGE_SIZE << il->hw_params.rx_page_order,
1047 PCI_DMA_FROMDEVICE);
1048
1049 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
1050 __free_pages(page, il->hw_params.rx_page_order);
1051 break;
1052 }
1053
4bc85c13 1054 spin_lock_irqsave(&rxq->lock, flags);
96ebbe8d 1055
4bc85c13
WYG
1056 if (list_empty(&rxq->rx_used)) {
1057 spin_unlock_irqrestore(&rxq->lock, flags);
96ebbe8d
SG
1058 pci_unmap_page(il->pci_dev, page_dma,
1059 PAGE_SIZE << il->hw_params.rx_page_order,
1060 PCI_DMA_FROMDEVICE);
46bc8d4b 1061 __free_pages(page, il->hw_params.rx_page_order);
4bc85c13
WYG
1062 return;
1063 }
96ebbe8d 1064
4bc85c13 1065 element = rxq->rx_used.next;
b73bb5f1 1066 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13 1067 list_del(element);
4bc85c13
WYG
1068
1069 rxb->page = page;
96ebbe8d 1070 rxb->page_dma = page_dma;
4bc85c13
WYG
1071 list_add_tail(&rxb->list, &rxq->rx_free);
1072 rxq->free_count++;
46bc8d4b 1073 il->alloc_rxb_page++;
4bc85c13
WYG
1074
1075 spin_unlock_irqrestore(&rxq->lock, flags);
1076 }
1077}
1078
e7392364
SG
1079void
1080il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1081{
1082 unsigned long flags;
1083 int i;
1084 spin_lock_irqsave(&rxq->lock, flags);
1085 INIT_LIST_HEAD(&rxq->rx_free);
1086 INIT_LIST_HEAD(&rxq->rx_used);
1087 /* Fill the rx_used queue with _all_ of the Rx buffers */
1088 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1089 /* In the reset function, these buffers may have been allocated
1090 * to an SKB, so we need to unmap and free potential storage */
1091 if (rxq->pool[i].page != NULL) {
46bc8d4b 1092 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG
1093 PAGE_SIZE << il->hw_params.rx_page_order,
1094 PCI_DMA_FROMDEVICE);
46bc8d4b 1095 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1096 rxq->pool[i].page = NULL;
1097 }
1098 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1099 }
1100
1101 /* Set us so that we have processed and used all buffers, but have
1102 * not restocked the Rx queue with fresh buffers */
1103 rxq->read = rxq->write = 0;
1104 rxq->write_actual = 0;
1105 rxq->free_count = 0;
1106 spin_unlock_irqrestore(&rxq->lock, flags);
1107}
1108
e7392364
SG
1109void
1110il3945_rx_replenish(void *data)
4bc85c13 1111{
46bc8d4b 1112 struct il_priv *il = data;
4bc85c13
WYG
1113 unsigned long flags;
1114
46bc8d4b 1115 il3945_rx_allocate(il, GFP_KERNEL);
4bc85c13 1116
46bc8d4b
SG
1117 spin_lock_irqsave(&il->lock, flags);
1118 il3945_rx_queue_restock(il);
1119 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1120}
1121
e7392364
SG
1122static void
1123il3945_rx_replenish_now(struct il_priv *il)
4bc85c13 1124{
46bc8d4b 1125 il3945_rx_allocate(il, GFP_ATOMIC);
4bc85c13 1126
46bc8d4b 1127 il3945_rx_queue_restock(il);
4bc85c13
WYG
1128}
1129
4bc85c13
WYG
1130/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1131 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1132 * This free routine walks the list of POOL entries and if SKB is set to
1133 * non NULL it is unmapped and freed
1134 */
e7392364
SG
1135static void
1136il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1137{
1138 int i;
1139 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1140 if (rxq->pool[i].page != NULL) {
46bc8d4b 1141 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG
1142 PAGE_SIZE << il->hw_params.rx_page_order,
1143 PCI_DMA_FROMDEVICE);
46bc8d4b 1144 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1145 rxq->pool[i].page = NULL;
1146 }
1147 }
1148
46bc8d4b 1149 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4bc85c13 1150 rxq->bd_dma);
46bc8d4b 1151 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
4bc85c13
WYG
1152 rxq->rb_stts, rxq->rb_stts_dma);
1153 rxq->bd = NULL;
e7392364 1154 rxq->rb_stts = NULL;
4bc85c13
WYG
1155}
1156
4bc85c13
WYG
1157/* Convert linear signal-to-noise ratio into dB */
1158static u8 ratio2dB[100] = {
1159/* 0 1 2 3 4 5 6 7 8 9 */
e7392364
SG
1160 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1161 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1162 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1163 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1164 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1165 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1166 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1167 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1168 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1169 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4bc85c13
WYG
1170};
1171
1172/* Calculates a relative dB value from a ratio of linear
1173 * (i.e. not dB) signal levels.
1174 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
e7392364
SG
1175int
1176il3945_calc_db_from_ratio(int sig_ratio)
4bc85c13
WYG
1177{
1178 /* 1000:1 or higher just report as 60 dB */
1179 if (sig_ratio >= 1000)
1180 return 60;
1181
1182 /* 100:1 or higher, divide by 10 and use table,
1183 * add 20 dB to make up for divide by 10 */
1184 if (sig_ratio >= 100)
e7392364 1185 return 20 + (int)ratio2dB[sig_ratio / 10];
4bc85c13
WYG
1186
1187 /* We shouldn't see this */
1188 if (sig_ratio < 1)
1189 return 0;
1190
1191 /* Use table for ratios 1:1 - 99:1 */
1192 return (int)ratio2dB[sig_ratio];
1193}
1194
1195/**
e2ebc833 1196 * il3945_rx_handle - Main entry function for receiving responses from uCode
4bc85c13 1197 *
d0c72347 1198 * Uses the il->handlers callback function array to invoke
4bc85c13
WYG
1199 * the appropriate handlers, including command responses,
1200 * frame-received notifications, and other notifications.
1201 */
e7392364
SG
1202static void
1203il3945_rx_handle(struct il_priv *il)
4bc85c13 1204{
b73bb5f1 1205 struct il_rx_buf *rxb;
dcae1c64 1206 struct il_rx_pkt *pkt;
46bc8d4b 1207 struct il_rx_queue *rxq = &il->rxq;
4bc85c13
WYG
1208 u32 r, i;
1209 int reclaim;
1210 unsigned long flags;
1211 u8 fill_rx = 0;
1212 u32 count = 8;
1213 int total_empty = 0;
1214
0c2c8852 1215 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
4bc85c13 1216 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 1217 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
4bc85c13
WYG
1218 i = rxq->read;
1219
1220 /* calculate total frames need to be restock after handling RX */
1221 total_empty = r - rxq->write_actual;
1222 if (total_empty < 0)
1223 total_empty += RX_QUEUE_SIZE;
1224
1225 if (total_empty > (RX_QUEUE_SIZE / 2))
1226 fill_rx = 1;
1227 /* Rx interrupt, but nothing sent from uCode */
1228 if (i == r)
58de00a4 1229 D_RX("r = %d, i = %d\n", r, i);
4bc85c13
WYG
1230
1231 while (i != r) {
1232 int len;
1233
1234 rxb = rxq->queue[i];
1235
1236 /* If an RXB doesn't have a Rx queue slot associated with it,
1237 * then a bug has been introduced in the queue refilling
1238 * routines -- catch it here */
1239 BUG_ON(rxb == NULL);
1240
1241 rxq->queue[i] = NULL;
1242
46bc8d4b
SG
1243 pci_unmap_page(il->pci_dev, rxb->page_dma,
1244 PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13
WYG
1245 PCI_DMA_FROMDEVICE);
1246 pkt = rxb_addr(rxb);
1247
e94a4099 1248 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 1249 len += sizeof(u32); /* account for status word */
4bc85c13
WYG
1250
1251 /* Reclaim a command buffer only if this packet is a response
1252 * to a (driver-originated) command.
1253 * If the packet (e.g. Rx frame) originated from uCode,
1254 * there is no command buffer to reclaim.
1255 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1256 * but apparently a few don't get set; catch them here. */
1257 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364 1258 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX;
4bc85c13
WYG
1259
1260 /* Based on type of command response or notification,
1261 * handle those that need handling via function in
d0c72347
SG
1262 * handlers table. See il3945_setup_handlers() */
1263 if (il->handlers[pkt->hdr.cmd]) {
58de00a4 1264 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
e7392364 1265 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG
1266 il->isr_stats.handlers[pkt->hdr.cmd]++;
1267 il->handlers[pkt->hdr.cmd] (il, rxb);
4bc85c13
WYG
1268 } else {
1269 /* No handling needed */
e7392364
SG
1270 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1271 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4bc85c13
WYG
1272 }
1273
1274 /*
1275 * XXX: After here, we should always check rxb->page
1276 * against NULL before touching it or its virtual
d0c72347 1277 * memory (pkt). Because some handler might have
4bc85c13
WYG
1278 * already taken or freed the pages.
1279 */
1280
1281 if (reclaim) {
1282 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 1283 * and fire off the (possibly) blocking il_send_cmd()
4bc85c13
WYG
1284 * as we reclaim the driver command queue */
1285 if (rxb->page)
46bc8d4b 1286 il_tx_cmd_complete(il, rxb);
4bc85c13 1287 else
9406f797 1288 IL_WARN("Claim null rxb?\n");
4bc85c13
WYG
1289 }
1290
1291 /* Reuse the page if possible. For notification packets and
1292 * SKBs that fail to Rx correctly, add them back into the
1293 * rx_free list for reuse later. */
1294 spin_lock_irqsave(&rxq->lock, flags);
1295 if (rxb->page != NULL) {
e7392364
SG
1296 rxb->page_dma =
1297 pci_map_page(il->pci_dev, rxb->page, 0,
1298 PAGE_SIZE << il->hw_params.
1299 rx_page_order, PCI_DMA_FROMDEVICE);
96ebbe8d
SG
1300 if (unlikely(pci_dma_mapping_error(il->pci_dev,
1301 rxb->page_dma))) {
1302 __il_free_pages(il, rxb->page);
1303 rxb->page = NULL;
1304 list_add_tail(&rxb->list, &rxq->rx_used);
1305 } else {
1306 list_add_tail(&rxb->list, &rxq->rx_free);
1307 rxq->free_count++;
1308 }
4bc85c13
WYG
1309 } else
1310 list_add_tail(&rxb->list, &rxq->rx_used);
1311
1312 spin_unlock_irqrestore(&rxq->lock, flags);
1313
1314 i = (i + 1) & RX_QUEUE_MASK;
1315 /* If there are a lot of unused frames,
1316 * restock the Rx queue so ucode won't assert. */
1317 if (fill_rx) {
1318 count++;
1319 if (count >= 8) {
1320 rxq->read = i;
46bc8d4b 1321 il3945_rx_replenish_now(il);
4bc85c13
WYG
1322 count = 0;
1323 }
1324 }
1325 }
1326
1327 /* Backtrack one entry */
1328 rxq->read = i;
1329 if (fill_rx)
46bc8d4b 1330 il3945_rx_replenish_now(il);
4bc85c13 1331 else
46bc8d4b 1332 il3945_rx_queue_restock(il);
4bc85c13
WYG
1333}
1334
1335/* call this function to flush any scheduled tasklet */
e7392364
SG
1336static inline void
1337il3945_synchronize_irq(struct il_priv *il)
4bc85c13 1338{
e7392364 1339 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG
1340 synchronize_irq(il->pci_dev->irq);
1341 tasklet_kill(&il->irq_tasklet);
4bc85c13
WYG
1342}
1343
e7392364
SG
1344static const char *
1345il3945_desc_lookup(int i)
4bc85c13
WYG
1346{
1347 switch (i) {
1348 case 1:
1349 return "FAIL";
1350 case 2:
1351 return "BAD_PARAM";
1352 case 3:
1353 return "BAD_CHECKSUM";
1354 case 4:
1355 return "NMI_INTERRUPT";
1356 case 5:
1357 return "SYSASSERT";
1358 case 6:
1359 return "FATAL_ERROR";
1360 }
1361
1362 return "UNKNOWN";
1363}
1364
1365#define ERROR_START_OFFSET (1 * sizeof(u32))
1366#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1367
e7392364
SG
1368void
1369il3945_dump_nic_error_log(struct il_priv *il)
4bc85c13
WYG
1370{
1371 u32 i;
1372 u32 desc, time, count, base, data1;
1373 u32 blink1, blink2, ilink1, ilink2;
1374
46bc8d4b 1375 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
4bc85c13 1376
e2ebc833 1377 if (!il3945_hw_valid_rtc_data_addr(base)) {
9406f797 1378 IL_ERR("Not valid error log pointer 0x%08X\n", base);
4bc85c13
WYG
1379 return;
1380 }
1381
46bc8d4b 1382 count = il_read_targ_mem(il, base);
4bc85c13
WYG
1383
1384 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 1385 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 1386 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
4bc85c13
WYG
1387 }
1388
9406f797 1389 IL_ERR("Desc Time asrtPC blink2 "
e7392364 1390 "ilink1 nmiPC Line\n");
4bc85c13
WYG
1391 for (i = ERROR_START_OFFSET;
1392 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1393 i += ERROR_ELEM_SIZE) {
46bc8d4b 1394 desc = il_read_targ_mem(il, base + i);
e7392364
SG
1395 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1396 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1397 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1398 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1399 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1400 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
4bc85c13 1401
e7392364
SG
1402 IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1403 il3945_desc_lookup(desc), desc, time, blink1, blink2,
1404 ilink1, ilink2, data1);
4bc85c13
WYG
1405 }
1406}
1407
e7392364
SG
1408static void
1409il3945_irq_tasklet(struct il_priv *il)
4bc85c13
WYG
1410{
1411 u32 inta, handled = 0;
1412 u32 inta_fh;
1413 unsigned long flags;
d3175167 1414#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
1415 u32 inta_mask;
1416#endif
1417
46bc8d4b 1418 spin_lock_irqsave(&il->lock, flags);
4bc85c13
WYG
1419
1420 /* Ack/clear/reset pending uCode interrupts.
1421 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1422 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG
1423 inta = _il_rd(il, CSR_INT);
1424 _il_wr(il, CSR_INT, inta);
4bc85c13
WYG
1425
1426 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1427 * Any new interrupts that happen after this, either while we're
1428 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG
1429 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1430 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4bc85c13 1431
d3175167 1432#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1433 if (il_get_debug_level(il) & IL_DL_ISR) {
4bc85c13 1434 /* just for debug */
841b2cca 1435 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG
1436 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1437 inta_mask, inta_fh);
4bc85c13
WYG
1438 }
1439#endif
1440
46bc8d4b 1441 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1442
1443 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1444 * atomic, make sure that inta covers all the interrupts that
1445 * we've discovered, even if FH interrupt came in just after
1446 * reading CSR_INT. */
1447 if (inta_fh & CSR39_FH_INT_RX_MASK)
1448 inta |= CSR_INT_BIT_FH_RX;
1449 if (inta_fh & CSR39_FH_INT_TX_MASK)
1450 inta |= CSR_INT_BIT_FH_TX;
1451
1452 /* Now service all interrupt bits discovered above. */
1453 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 1454 IL_ERR("Hardware error detected. Restarting.\n");
4bc85c13
WYG
1455
1456 /* Tell the device to stop sending interrupts */
46bc8d4b 1457 il_disable_interrupts(il);
4bc85c13 1458
46bc8d4b
SG
1459 il->isr_stats.hw++;
1460 il_irq_handle_error(il);
4bc85c13
WYG
1461
1462 handled |= CSR_INT_BIT_HW_ERR;
1463
1464 return;
1465 }
d3175167 1466#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1467 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4bc85c13
WYG
1468 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1469 if (inta & CSR_INT_BIT_SCD) {
58de00a4 1470 D_ISR("Scheduler finished to transmit "
e7392364 1471 "the frame/frames.\n");
46bc8d4b 1472 il->isr_stats.sch++;
4bc85c13
WYG
1473 }
1474
1475 /* Alive notification via Rx interrupt will do the real work */
1476 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 1477 D_ISR("Alive interrupt\n");
46bc8d4b 1478 il->isr_stats.alive++;
4bc85c13
WYG
1479 }
1480 }
1481#endif
1482 /* Safely ignore these bits for debug checks below */
1483 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1484
1485 /* Error detected by uCode */
1486 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG
1487 IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1488 inta);
46bc8d4b
SG
1489 il->isr_stats.sw++;
1490 il_irq_handle_error(il);
4bc85c13
WYG
1491 handled |= CSR_INT_BIT_SW_ERR;
1492 }
1493
1494 /* uCode wakes up after power-down sleep */
1495 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 1496 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG
1497 il_rx_queue_update_write_ptr(il, &il->rxq);
1498 il_txq_update_write_ptr(il, &il->txq[0]);
1499 il_txq_update_write_ptr(il, &il->txq[1]);
1500 il_txq_update_write_ptr(il, &il->txq[2]);
1501 il_txq_update_write_ptr(il, &il->txq[3]);
1502 il_txq_update_write_ptr(il, &il->txq[4]);
1503 il_txq_update_write_ptr(il, &il->txq[5]);
1504
1505 il->isr_stats.wakeup++;
4bc85c13
WYG
1506 handled |= CSR_INT_BIT_WAKEUP;
1507 }
1508
1509 /* All uCode command responses, including Tx command responses,
1510 * Rx "responses" (frame-received notification), and other
1511 * notifications from uCode come through here*/
1512 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG
1513 il3945_rx_handle(il);
1514 il->isr_stats.rx++;
4bc85c13
WYG
1515 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1516 }
1517
1518 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 1519 D_ISR("Tx interrupt\n");
46bc8d4b 1520 il->isr_stats.tx++;
4bc85c13 1521
841b2cca 1522 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
e7392364 1523 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
4bc85c13
WYG
1524 handled |= CSR_INT_BIT_FH_TX;
1525 }
1526
1527 if (inta & ~handled) {
9406f797 1528 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 1529 il->isr_stats.unhandled++;
4bc85c13
WYG
1530 }
1531
46bc8d4b 1532 if (inta & ~il->inta_mask) {
9406f797 1533 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 1534 inta & ~il->inta_mask);
53143a18 1535 IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
4bc85c13
WYG
1536 }
1537
1538 /* Re-enable all interrupts */
1539 /* only Re-enable if disabled by irq */
a6766ccd 1540 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 1541 il_enable_interrupts(il);
4bc85c13 1542
d3175167 1543#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1544 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG
1545 inta = _il_rd(il, CSR_INT);
1546 inta_mask = _il_rd(il, CSR_INT_MASK);
1547 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
58de00a4 1548 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
e7392364 1549 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4bc85c13
WYG
1550 }
1551#endif
1552}
1553
e7392364
SG
1554static int
1555il3945_get_channels_for_scan(struct il_priv *il, enum ieee80211_band band,
1556 u8 is_active, u8 n_probes,
1557 struct il3945_scan_channel *scan_ch,
1558 struct ieee80211_vif *vif)
4bc85c13
WYG
1559{
1560 struct ieee80211_channel *chan;
1561 const struct ieee80211_supported_band *sband;
e2ebc833 1562 const struct il_channel_info *ch_info;
4bc85c13
WYG
1563 u16 passive_dwell = 0;
1564 u16 active_dwell = 0;
1565 int added, i;
1566
46bc8d4b 1567 sband = il_get_hw_mode(il, band);
4bc85c13
WYG
1568 if (!sband)
1569 return 0;
1570
46bc8d4b
SG
1571 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1572 passive_dwell = il_get_passive_dwell_time(il, band, vif);
4bc85c13
WYG
1573
1574 if (passive_dwell <= active_dwell)
1575 passive_dwell = active_dwell + 1;
1576
46bc8d4b
SG
1577 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1578 chan = il->scan_request->channels[i];
4bc85c13
WYG
1579
1580 if (chan->band != band)
1581 continue;
1582
1583 scan_ch->channel = chan->hw_value;
1584
e7392364 1585 ch_info = il_get_channel_info(il, band, scan_ch->channel);
e2ebc833 1586 if (!il_is_channel_valid(ch_info)) {
e7392364 1587 D_SCAN("Channel %d is INVALID for this band.\n",
be663ab6 1588 scan_ch->channel);
4bc85c13
WYG
1589 continue;
1590 }
1591
1592 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1593 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1594 /* If passive , set up for auto-switch
1595 * and use long active_dwell time.
1596 */
e2ebc833 1597 if (!is_active || il_is_channel_passive(ch_info) ||
8fe02e16 1598 (chan->flags & IEEE80211_CHAN_NO_IR)) {
4bc85c13 1599 scan_ch->type = 0; /* passive */
46bc8d4b 1600 if (IL_UCODE_API(il->ucode_ver) == 1)
e7392364
SG
1601 scan_ch->active_dwell =
1602 cpu_to_le16(passive_dwell - 1);
4bc85c13
WYG
1603 } else {
1604 scan_ch->type = 1; /* active */
1605 }
1606
1607 /* Set direct probe bits. These may be used both for active
1608 * scan channels (probes gets sent right away),
1609 * or for passive channels (probes get se sent only after
1610 * hearing clear Rx packet).*/
46bc8d4b 1611 if (IL_UCODE_API(il->ucode_ver) >= 2) {
4bc85c13 1612 if (n_probes)
d3175167 1613 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1614 } else {
1615 /* uCode v1 does not allow setting direct probe bits on
1616 * passive channel. */
1617 if ((scan_ch->type & 1) && n_probes)
d3175167 1618 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1619 }
1620
1621 /* Set txpower levels to defaults */
1622 scan_ch->tpc.dsp_atten = 110;
1623 /* scan_pwr_info->tpc.dsp_atten; */
1624
1625 /*scan_pwr_info->tpc.tx_gain; */
1626 if (band == IEEE80211_BAND_5GHZ)
1627 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1628 else {
1629 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1630 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1631 * power level:
1632 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
1633 */
1634 }
1635
e7392364
SG
1636 D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1637 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1638 (scan_ch->type & 1) ? active_dwell : passive_dwell);
4bc85c13
WYG
1639
1640 scan_ch++;
1641 added++;
1642 }
1643
58de00a4 1644 D_SCAN("total channels to scan %d\n", added);
4bc85c13
WYG
1645 return added;
1646}
1647
e7392364
SG
1648static void
1649il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
4bc85c13
WYG
1650{
1651 int i;
1652
2eb05816 1653 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
e2ebc833 1654 rates[i].bitrate = il3945_rates[i].ieee * 5;
e7392364 1655 rates[i].hw_value = i; /* Rate scaling will work on idxes */
4bc85c13
WYG
1656 rates[i].hw_value_short = i;
1657 rates[i].flags = 0;
d3175167 1658 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
4bc85c13
WYG
1659 /*
1660 * If CCK != 1M then set short preamble rate flag.
1661 */
e7392364
SG
1662 rates[i].flags |=
1663 (il3945_rates[i].plcp ==
1664 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4bc85c13
WYG
1665 }
1666 }
1667}
1668
1669/******************************************************************************
1670 *
1671 * uCode download functions
1672 *
1673 ******************************************************************************/
1674
e7392364
SG
1675static void
1676il3945_dealloc_ucode_pci(struct il_priv *il)
4bc85c13 1677{
46bc8d4b
SG
1678 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1679 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1680 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1681 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1682 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1683 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13
WYG
1684}
1685
1686/**
e2ebc833 1687 * il3945_verify_inst_full - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1688 * looking at all data.
1689 */
e7392364
SG
1690static int
1691il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
4bc85c13
WYG
1692{
1693 u32 val;
1694 u32 save_len = len;
1695 int rc = 0;
1696 u32 errcnt;
1697
58de00a4 1698 D_INFO("ucode inst image size is %u\n", len);
4bc85c13 1699
e7392364 1700 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
4bc85c13
WYG
1701
1702 errcnt = 0;
1703 for (; len > 0; len -= sizeof(u32), image++) {
1704 /* read data comes through single port, auto-incr addr */
1705 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1706 * if IL_DL_IO is set */
1c8cae57 1707 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13 1708 if (val != le32_to_cpu(*image)) {
9406f797 1709 IL_ERR("uCode INST section is invalid at "
e7392364
SG
1710 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1711 save_len - len, val, le32_to_cpu(*image));
4bc85c13
WYG
1712 rc = -EIO;
1713 errcnt++;
1714 if (errcnt >= 20)
1715 break;
1716 }
1717 }
1718
4bc85c13 1719 if (!errcnt)
e7392364 1720 D_INFO("ucode image in INSTRUCTION memory is good\n");
4bc85c13
WYG
1721
1722 return rc;
1723}
1724
4bc85c13 1725/**
e2ebc833 1726 * il3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1727 * using sample data 100 bytes apart. If these sample points are good,
1728 * it's a pretty good bet that everything between them is good, too.
1729 */
e7392364
SG
1730static int
1731il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
4bc85c13
WYG
1732{
1733 u32 val;
1734 int rc = 0;
1735 u32 errcnt = 0;
1736 u32 i;
1737
58de00a4 1738 D_INFO("ucode inst image size is %u\n", len);
4bc85c13 1739
e7392364 1740 for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
4bc85c13
WYG
1741 /* read data comes through single port, auto-incr addr */
1742 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1743 * if IL_DL_IO is set */
e7392364 1744 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1c8cae57 1745 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13 1746 if (val != le32_to_cpu(*image)) {
e7392364 1747#if 0 /* Enable this if you want to see details */
9406f797 1748 IL_ERR("uCode INST section is invalid at "
e7392364
SG
1749 "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1750 *image);
4bc85c13
WYG
1751#endif
1752 rc = -EIO;
1753 errcnt++;
1754 if (errcnt >= 3)
1755 break;
1756 }
1757 }
1758
1759 return rc;
1760}
1761
4bc85c13 1762/**
e2ebc833 1763 * il3945_verify_ucode - determine which instruction image is in SRAM,
4bc85c13
WYG
1764 * and verify its contents
1765 */
e7392364
SG
1766static int
1767il3945_verify_ucode(struct il_priv *il)
4bc85c13
WYG
1768{
1769 __le32 *image;
1770 u32 len;
1771 int rc = 0;
1772
1773 /* Try bootstrap */
e7392364 1774 image = (__le32 *) il->ucode_boot.v_addr;
46bc8d4b
SG
1775 len = il->ucode_boot.len;
1776 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1777 if (rc == 0) {
58de00a4 1778 D_INFO("Bootstrap uCode is good in inst SRAM\n");
4bc85c13
WYG
1779 return 0;
1780 }
1781
1782 /* Try initialize */
e7392364 1783 image = (__le32 *) il->ucode_init.v_addr;
46bc8d4b
SG
1784 len = il->ucode_init.len;
1785 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1786 if (rc == 0) {
58de00a4 1787 D_INFO("Initialize uCode is good in inst SRAM\n");
4bc85c13
WYG
1788 return 0;
1789 }
1790
1791 /* Try runtime/protocol */
e7392364 1792 image = (__le32 *) il->ucode_code.v_addr;
46bc8d4b
SG
1793 len = il->ucode_code.len;
1794 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1795 if (rc == 0) {
58de00a4 1796 D_INFO("Runtime uCode is good in inst SRAM\n");
4bc85c13
WYG
1797 return 0;
1798 }
1799
9406f797 1800 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
4bc85c13
WYG
1801
1802 /* Since nothing seems to match, show first several data entries in
1803 * instruction SRAM, so maybe visual inspection will give a clue.
1804 * Selection of bootstrap image (vs. other images) is arbitrary. */
e7392364 1805 image = (__le32 *) il->ucode_boot.v_addr;
46bc8d4b
SG
1806 len = il->ucode_boot.len;
1807 rc = il3945_verify_inst_full(il, image, len);
4bc85c13
WYG
1808
1809 return rc;
1810}
1811
e7392364
SG
1812static void
1813il3945_nic_start(struct il_priv *il)
4bc85c13
WYG
1814{
1815 /* Remove all resets to allow NIC to operate */
841b2cca 1816 _il_wr(il, CSR_RESET, 0);
4bc85c13
WYG
1817}
1818
d3175167 1819#define IL3945_UCODE_GET(item) \
e2ebc833 1820static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
4bc85c13 1821{ \
be663ab6 1822 return le32_to_cpu(ucode->v1.item); \
4bc85c13
WYG
1823}
1824
e7392364
SG
1825static u32
1826il3945_ucode_get_header_size(u32 api_ver)
4bc85c13
WYG
1827{
1828 return 24;
1829}
1830
e7392364
SG
1831static u8 *
1832il3945_ucode_get_data(const struct il_ucode_header *ucode)
4bc85c13 1833{
be663ab6 1834 return (u8 *) ucode->v1.data;
4bc85c13
WYG
1835}
1836
d3175167
SG
1837IL3945_UCODE_GET(inst_size);
1838IL3945_UCODE_GET(data_size);
1839IL3945_UCODE_GET(init_size);
1840IL3945_UCODE_GET(init_data_size);
1841IL3945_UCODE_GET(boot_size);
4bc85c13
WYG
1842
1843/**
e2ebc833 1844 * il3945_read_ucode - Read uCode images from disk file.
4bc85c13
WYG
1845 *
1846 * Copy into buffers for card to fetch via bus-mastering
1847 */
e7392364
SG
1848static int
1849il3945_read_ucode(struct il_priv *il)
4bc85c13 1850{
e2ebc833 1851 const struct il_ucode_header *ucode;
0c2c8852 1852 int ret = -EINVAL, idx;
4bc85c13
WYG
1853 const struct firmware *ucode_raw;
1854 /* firmware file name contains uCode/driver compatibility version */
46bc8d4b
SG
1855 const char *name_pre = il->cfg->fw_name_pre;
1856 const unsigned int api_max = il->cfg->ucode_api_max;
1857 const unsigned int api_min = il->cfg->ucode_api_min;
4bc85c13
WYG
1858 char buf[25];
1859 u8 *src;
1860 size_t len;
1861 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1862
1863 /* Ask kernel firmware_class module to get the boot firmware off disk.
1864 * request_firmware() is synchronous, file is in memory on return. */
0c2c8852
SG
1865 for (idx = api_max; idx >= api_min; idx--) {
1866 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
46bc8d4b 1867 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
4bc85c13 1868 if (ret < 0) {
e7392364 1869 IL_ERR("%s firmware file req failed: %d\n", buf, ret);
4bc85c13
WYG
1870 if (ret == -ENOENT)
1871 continue;
1872 else
1873 goto error;
1874 } else {
0c2c8852 1875 if (idx < api_max)
9406f797 1876 IL_ERR("Loaded firmware %s, "
e7392364
SG
1877 "which is deprecated. "
1878 " Please use API v%u instead.\n", buf,
1879 api_max);
58de00a4 1880 D_INFO("Got firmware '%s' file "
e7392364 1881 "(%zd bytes) from disk\n", buf, ucode_raw->size);
4bc85c13
WYG
1882 break;
1883 }
1884 }
1885
1886 if (ret < 0)
1887 goto error;
1888
1889 /* Make sure that we got at least our header! */
e7392364 1890 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
9406f797 1891 IL_ERR("File size way too small!\n");
4bc85c13
WYG
1892 ret = -EINVAL;
1893 goto err_release;
1894 }
1895
1896 /* Data from ucode file: header followed by uCode images */
e2ebc833 1897 ucode = (struct il_ucode_header *)ucode_raw->data;
4bc85c13 1898
46bc8d4b
SG
1899 il->ucode_ver = le32_to_cpu(ucode->ver);
1900 api_ver = IL_UCODE_API(il->ucode_ver);
e2ebc833
SG
1901 inst_size = il3945_ucode_get_inst_size(ucode);
1902 data_size = il3945_ucode_get_data_size(ucode);
1903 init_size = il3945_ucode_get_init_size(ucode);
1904 init_data_size = il3945_ucode_get_init_data_size(ucode);
1905 boot_size = il3945_ucode_get_boot_size(ucode);
1906 src = il3945_ucode_get_data(ucode);
4bc85c13
WYG
1907
1908 /* api_ver should match the api version forming part of the
1909 * firmware filename ... but we don't check for that and only rely
1910 * on the API version read from firmware header from here on forward */
1911
1912 if (api_ver < api_min || api_ver > api_max) {
9406f797 1913 IL_ERR("Driver unable to support your firmware API. "
e7392364
SG
1914 "Driver supports v%u, firmware is v%u.\n", api_max,
1915 api_ver);
46bc8d4b 1916 il->ucode_ver = 0;
4bc85c13
WYG
1917 ret = -EINVAL;
1918 goto err_release;
1919 }
1920 if (api_ver != api_max)
9406f797 1921 IL_ERR("Firmware has old API version. Expected %u, "
e7392364
SG
1922 "got %u. New firmware can be obtained "
1923 "from http://www.intellinuxwireless.org.\n", api_max,
1924 api_ver);
4bc85c13 1925
9406f797 1926 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG
1927 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1928 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
46bc8d4b 1929
e7392364
SG
1930 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1931 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1932 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1933 IL_UCODE_SERIAL(il->ucode_ver));
4bc85c13 1934
e7392364
SG
1935 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1936 D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1937 D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1938 D_INFO("f/w package hdr init inst size = %u\n", init_size);
1939 D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1940 D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
4bc85c13
WYG
1941
1942 /* Verify size of file vs. image size info in file's header */
e7392364
SG
1943 if (ucode_raw->size !=
1944 il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1945 init_size + init_data_size + boot_size) {
4bc85c13 1946
e7392364
SG
1947 D_INFO("uCode file size %zd does not match expected size\n",
1948 ucode_raw->size);
4bc85c13
WYG
1949 ret = -EINVAL;
1950 goto err_release;
1951 }
1952
1953 /* Verify that uCode images will fit in card's SRAM */
d3175167 1954 if (inst_size > IL39_MAX_INST_SIZE) {
e7392364 1955 D_INFO("uCode instr len %d too large to fit in\n", inst_size);
4bc85c13
WYG
1956 ret = -EINVAL;
1957 goto err_release;
1958 }
1959
d3175167 1960 if (data_size > IL39_MAX_DATA_SIZE) {
e7392364 1961 D_INFO("uCode data len %d too large to fit in\n", data_size);
4bc85c13
WYG
1962 ret = -EINVAL;
1963 goto err_release;
1964 }
d3175167 1965 if (init_size > IL39_MAX_INST_SIZE) {
e7392364
SG
1966 D_INFO("uCode init instr len %d too large to fit in\n",
1967 init_size);
4bc85c13
WYG
1968 ret = -EINVAL;
1969 goto err_release;
1970 }
d3175167 1971 if (init_data_size > IL39_MAX_DATA_SIZE) {
e7392364
SG
1972 D_INFO("uCode init data len %d too large to fit in\n",
1973 init_data_size);
4bc85c13
WYG
1974 ret = -EINVAL;
1975 goto err_release;
1976 }
d3175167 1977 if (boot_size > IL39_MAX_BSM_SIZE) {
e7392364
SG
1978 D_INFO("uCode boot instr len %d too large to fit in\n",
1979 boot_size);
4bc85c13
WYG
1980 ret = -EINVAL;
1981 goto err_release;
1982 }
1983
1984 /* Allocate ucode buffers for card's bus-master loading ... */
1985
1986 /* Runtime instructions and 2 copies of data:
1987 * 1) unmodified from disk
1988 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG
1989 il->ucode_code.len = inst_size;
1990 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4bc85c13 1991
46bc8d4b
SG
1992 il->ucode_data.len = data_size;
1993 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4bc85c13 1994
46bc8d4b
SG
1995 il->ucode_data_backup.len = data_size;
1996 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4bc85c13 1997
46bc8d4b
SG
1998 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1999 !il->ucode_data_backup.v_addr)
4bc85c13
WYG
2000 goto err_pci_alloc;
2001
2002 /* Initialization instructions and data */
2003 if (init_size && init_data_size) {
46bc8d4b
SG
2004 il->ucode_init.len = init_size;
2005 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4bc85c13 2006
46bc8d4b
SG
2007 il->ucode_init_data.len = init_data_size;
2008 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4bc85c13 2009
46bc8d4b 2010 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4bc85c13
WYG
2011 goto err_pci_alloc;
2012 }
2013
2014 /* Bootstrap (instructions only, no data) */
2015 if (boot_size) {
46bc8d4b
SG
2016 il->ucode_boot.len = boot_size;
2017 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13 2018
46bc8d4b 2019 if (!il->ucode_boot.v_addr)
4bc85c13
WYG
2020 goto err_pci_alloc;
2021 }
2022
2023 /* Copy images into buffers for card's bus-master reads ... */
2024
2025 /* Runtime instructions (first block of data in file) */
2026 len = inst_size;
e7392364 2027 D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
46bc8d4b 2028 memcpy(il->ucode_code.v_addr, src, len);
4bc85c13
WYG
2029 src += len;
2030
58de00a4 2031 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 2032 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4bc85c13
WYG
2033
2034 /* Runtime data (2nd block)
e2ebc833 2035 * NOTE: Copy into backup buffer will be done in il3945_up() */
4bc85c13 2036 len = data_size;
e7392364 2037 D_INFO("Copying (but not loading) uCode data len %zd\n", len);
46bc8d4b
SG
2038 memcpy(il->ucode_data.v_addr, src, len);
2039 memcpy(il->ucode_data_backup.v_addr, src, len);
4bc85c13
WYG
2040 src += len;
2041
2042 /* Initialization instructions (3rd block) */
2043 if (init_size) {
2044 len = init_size;
e7392364 2045 D_INFO("Copying (but not loading) init instr len %zd\n", len);
46bc8d4b 2046 memcpy(il->ucode_init.v_addr, src, len);
4bc85c13
WYG
2047 src += len;
2048 }
2049
2050 /* Initialization data (4th block) */
2051 if (init_data_size) {
2052 len = init_data_size;
e7392364 2053 D_INFO("Copying (but not loading) init data len %zd\n", len);
46bc8d4b 2054 memcpy(il->ucode_init_data.v_addr, src, len);
4bc85c13
WYG
2055 src += len;
2056 }
2057
2058 /* Bootstrap instructions (5th block) */
2059 len = boot_size;
e7392364 2060 D_INFO("Copying (but not loading) boot instr len %zd\n", len);
46bc8d4b 2061 memcpy(il->ucode_boot.v_addr, src, len);
4bc85c13
WYG
2062
2063 /* We have our copies now, allow OS release its copies */
2064 release_firmware(ucode_raw);
2065 return 0;
2066
e7392364 2067err_pci_alloc:
9406f797 2068 IL_ERR("failed to allocate pci memory\n");
4bc85c13 2069 ret = -ENOMEM;
46bc8d4b 2070 il3945_dealloc_ucode_pci(il);
4bc85c13 2071
e7392364 2072err_release:
4bc85c13
WYG
2073 release_firmware(ucode_raw);
2074
e7392364 2075error:
4bc85c13
WYG
2076 return ret;
2077}
2078
4bc85c13 2079/**
e2ebc833 2080 * il3945_set_ucode_ptrs - Set uCode address location
4bc85c13
WYG
2081 *
2082 * Tell initialization uCode where to find runtime uCode.
2083 *
2084 * BSM registers initially contain pointers to initialization uCode.
2085 * We need to replace them to load runtime uCode inst and data,
2086 * and to save runtime data when powering down.
2087 */
e7392364
SG
2088static int
2089il3945_set_ucode_ptrs(struct il_priv *il)
4bc85c13
WYG
2090{
2091 dma_addr_t pinst;
2092 dma_addr_t pdata;
2093
2094 /* bits 31:0 for 3945 */
46bc8d4b
SG
2095 pinst = il->ucode_code.p_addr;
2096 pdata = il->ucode_data_backup.p_addr;
4bc85c13
WYG
2097
2098 /* Tell bootstrap uCode where to find image to load */
db54eb57
SG
2099 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2100 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
e7392364 2101 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
4bc85c13
WYG
2102
2103 /* Inst byte count must be last to set up, bit 31 signals uCode
2104 * that all new ptr/size info is in place */
db54eb57 2105 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
e7392364 2106 il->ucode_code.len | BSM_DRAM_INST_LOAD);
4bc85c13 2107
58de00a4 2108 D_INFO("Runtime uCode pointers are set.\n");
4bc85c13
WYG
2109
2110 return 0;
2111}
2112
2113/**
4d69c752 2114 * il3945_init_alive_start - Called after N_ALIVE notification received
4bc85c13 2115 *
4d69c752 2116 * Called after N_ALIVE notification received from "initialize" uCode.
4bc85c13
WYG
2117 *
2118 * Tell "initialize" uCode to go ahead and load the runtime uCode.
2119 */
e7392364
SG
2120static void
2121il3945_init_alive_start(struct il_priv *il)
4bc85c13
WYG
2122{
2123 /* Check alive response for "valid" sign from uCode */
46bc8d4b 2124 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2125 /* We had an error bringing up the hardware, so take it
2126 * all the way back down so we can try again */
58de00a4 2127 D_INFO("Initialize Alive failed.\n");
4bc85c13
WYG
2128 goto restart;
2129 }
2130
2131 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2132 * This is a paranoid check, because we would not have gotten the
2133 * "initialize" alive if code weren't properly loaded. */
46bc8d4b 2134 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2135 /* Runtime instruction load was bad;
2136 * take it all the way back down so we can try again */
58de00a4 2137 D_INFO("Bad \"initialize\" uCode load.\n");
4bc85c13
WYG
2138 goto restart;
2139 }
2140
2141 /* Send pointers to protocol/runtime uCode image ... init code will
2142 * load and launch runtime uCode, which will send us another "Alive"
2143 * notification. */
58de00a4 2144 D_INFO("Initialization Alive received.\n");
46bc8d4b 2145 if (il3945_set_ucode_ptrs(il)) {
4bc85c13
WYG
2146 /* Runtime instruction load won't happen;
2147 * take it all the way back down so we can try again */
58de00a4 2148 D_INFO("Couldn't set up uCode pointers.\n");
4bc85c13
WYG
2149 goto restart;
2150 }
2151 return;
2152
e7392364 2153restart:
46bc8d4b 2154 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2155}
2156
2157/**
4d69c752 2158 * il3945_alive_start - called after N_ALIVE notification received
4bc85c13 2159 * from protocol/runtime uCode (initialization uCode's
e2ebc833 2160 * Alive gets handled by il3945_init_alive_start()).
4bc85c13 2161 */
e7392364
SG
2162static void
2163il3945_alive_start(struct il_priv *il)
4bc85c13
WYG
2164{
2165 int thermal_spin = 0;
2166 u32 rfkill;
4bc85c13 2167
58de00a4 2168 D_INFO("Runtime Alive received.\n");
4bc85c13 2169
46bc8d4b 2170 if (il->card_alive.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2171 /* We had an error bringing up the hardware, so take it
2172 * all the way back down so we can try again */
58de00a4 2173 D_INFO("Alive failed.\n");
4bc85c13
WYG
2174 goto restart;
2175 }
2176
2177 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2178 * This is a paranoid check, because we would not have gotten the
2179 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 2180 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2181 /* Runtime instruction load was bad;
2182 * take it all the way back down so we can try again */
58de00a4 2183 D_INFO("Bad runtime uCode load.\n");
4bc85c13
WYG
2184 goto restart;
2185 }
2186
db54eb57 2187 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
58de00a4 2188 D_INFO("RFKILL status: 0x%x\n", rfkill);
4bc85c13
WYG
2189
2190 if (rfkill & 0x1) {
bc269a8e 2191 clear_bit(S_RFKILL, &il->status);
4bc85c13
WYG
2192 /* if RFKILL is not on, then wait for thermal
2193 * sensor in adapter to kick in */
46bc8d4b 2194 while (il3945_hw_get_temperature(il) == 0) {
4bc85c13
WYG
2195 thermal_spin++;
2196 udelay(10);
2197 }
2198
2199 if (thermal_spin)
58de00a4 2200 D_INFO("Thermal calibration took %dus\n",
e7392364 2201 thermal_spin * 10);
4bc85c13 2202 } else
bc269a8e 2203 set_bit(S_RFKILL, &il->status);
4bc85c13
WYG
2204
2205 /* After the ALIVE response, we can send commands to 3945 uCode */
a6766ccd 2206 set_bit(S_ALIVE, &il->status);
4bc85c13
WYG
2207
2208 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 2209 il_setup_watchdog(il);
4bc85c13 2210
46bc8d4b 2211 if (il_is_rfkill(il))
4bc85c13
WYG
2212 return;
2213
46bc8d4b 2214 ieee80211_wake_queues(il->hw);
4bc85c13 2215
2eb05816 2216 il->active_rate = RATES_MASK_3945;
4bc85c13 2217
46bc8d4b 2218 il_power_update_mode(il, true);
4bc85c13 2219
7c2cde2e 2220 if (il_is_associated(il)) {
e2ebc833 2221 struct il3945_rxon_cmd *active_rxon =
c8b03958 2222 (struct il3945_rxon_cmd *)(&il->active);
4bc85c13 2223
c8b03958 2224 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
4bc85c13
WYG
2225 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2226 } else {
2227 /* Initialize our rx_config data */
83007196 2228 il_connection_init_rx_config(il);
4bc85c13
WYG
2229 }
2230
2231 /* Configure Bluetooth device coexistence support */
46bc8d4b 2232 il_send_bt_config(il);
4bc85c13 2233
a6766ccd 2234 set_bit(S_READY, &il->status);
4bc85c13
WYG
2235
2236 /* Configure the adapter for unassociated operation */
83007196 2237 il3945_commit_rxon(il);
4bc85c13 2238
46bc8d4b 2239 il3945_reg_txpower_periodic(il);
4bc85c13 2240
58de00a4 2241 D_INFO("ALIVE processing complete.\n");
46bc8d4b 2242 wake_up(&il->wait_command_queue);
4bc85c13
WYG
2243
2244 return;
2245
e7392364 2246restart:
46bc8d4b 2247 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2248}
2249
46bc8d4b 2250static void il3945_cancel_deferred_work(struct il_priv *il);
4bc85c13 2251
e7392364
SG
2252static void
2253__il3945_down(struct il_priv *il)
4bc85c13
WYG
2254{
2255 unsigned long flags;
2256 int exit_pending;
2257
58de00a4 2258 D_INFO(DRV_NAME " is going down\n");
4bc85c13 2259
46bc8d4b 2260 il_scan_cancel_timeout(il, 200);
4bc85c13 2261
a6766ccd 2262 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
4bc85c13 2263
a6766ccd 2264 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
4bc85c13 2265 * to prevent rearm timer */
46bc8d4b 2266 del_timer_sync(&il->watchdog);
4bc85c13
WYG
2267
2268 /* Station information will now be cleared in device */
83007196 2269 il_clear_ucode_stations(il);
46bc8d4b
SG
2270 il_dealloc_bcast_stations(il);
2271 il_clear_driver_stations(il);
4bc85c13
WYG
2272
2273 /* Unblock any waiting calls */
46bc8d4b 2274 wake_up_all(&il->wait_command_queue);
4bc85c13
WYG
2275
2276 /* Wipe out the EXIT_PENDING status bit if we are not actually
2277 * exiting the module */
2278 if (!exit_pending)
a6766ccd 2279 clear_bit(S_EXIT_PENDING, &il->status);
4bc85c13
WYG
2280
2281 /* stop and reset the on-board processor */
841b2cca 2282 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
2283
2284 /* tell the device to stop sending interrupts */
46bc8d4b
SG
2285 spin_lock_irqsave(&il->lock, flags);
2286 il_disable_interrupts(il);
2287 spin_unlock_irqrestore(&il->lock, flags);
2288 il3945_synchronize_irq(il);
4bc85c13 2289
46bc8d4b
SG
2290 if (il->mac80211_registered)
2291 ieee80211_stop_queues(il->hw);
4bc85c13 2292
e2ebc833 2293 /* If we have not previously called il3945_init() then
4bc85c13 2294 * clear all bits but the RF Kill bits and return */
46bc8d4b 2295 if (!il_is_init(il)) {
e7392364 2296 il->status =
bc269a8e 2297 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0 2298 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
e7392364 2299 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
4bc85c13
WYG
2300 goto exit;
2301 }
2302
2303 /* ...otherwise clear out all the status bits but the RF Kill
2304 * bit and continue taking the NIC down. */
e7392364 2305 il->status &=
bc269a8e 2306 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0
SG
2307 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2308 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
e7392364 2309 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
4bc85c13 2310
775ed8ab
SG
2311 /*
2312 * We disabled and synchronized interrupt, and priv->mutex is taken, so
2313 * here is the only thread which will program device registers, but
2314 * still have lockdep assertions, so we are taking reg_lock.
2315 */
2316 spin_lock_irq(&il->reg_lock);
2317 /* FIXME: il_grab_nic_access if rfkill is off ? */
2318
46bc8d4b
SG
2319 il3945_hw_txq_ctx_stop(il);
2320 il3945_hw_rxq_stop(il);
4bc85c13 2321 /* Power-down device's busmaster DMA clocks */
775ed8ab 2322 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
4bc85c13 2323 udelay(5);
4bc85c13 2324 /* Stop the device, and put it in low power state */
775ed8ab
SG
2325 _il_apm_stop(il);
2326
2327 spin_unlock_irq(&il->reg_lock);
4bc85c13 2328
775ed8ab 2329 il3945_hw_txq_ctx_free(il);
e7392364 2330exit:
46bc8d4b 2331 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
4bc85c13 2332
46bc8d4b
SG
2333 if (il->beacon_skb)
2334 dev_kfree_skb(il->beacon_skb);
2335 il->beacon_skb = NULL;
4bc85c13
WYG
2336
2337 /* clear out any free frames */
46bc8d4b 2338 il3945_clear_free_frames(il);
4bc85c13
WYG
2339}
2340
e7392364
SG
2341static void
2342il3945_down(struct il_priv *il)
4bc85c13 2343{
46bc8d4b
SG
2344 mutex_lock(&il->mutex);
2345 __il3945_down(il);
2346 mutex_unlock(&il->mutex);
4bc85c13 2347
46bc8d4b 2348 il3945_cancel_deferred_work(il);
4bc85c13
WYG
2349}
2350
2351#define MAX_HW_RESTARTS 5
2352
e7392364
SG
2353static int
2354il3945_alloc_bcast_station(struct il_priv *il)
4bc85c13 2355{
4bc85c13
WYG
2356 unsigned long flags;
2357 u8 sta_id;
2358
46bc8d4b 2359 spin_lock_irqsave(&il->sta_lock, flags);
83007196 2360 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
e2ebc833 2361 if (sta_id == IL_INVALID_STATION) {
9406f797 2362 IL_ERR("Unable to prepare broadcast station\n");
46bc8d4b 2363 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2364
2365 return -EINVAL;
2366 }
2367
46bc8d4b
SG
2368 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2369 il->stations[sta_id].used |= IL_STA_BCAST;
2370 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2371
2372 return 0;
2373}
2374
e7392364
SG
2375static int
2376__il3945_up(struct il_priv *il)
4bc85c13
WYG
2377{
2378 int rc, i;
2379
46bc8d4b 2380 rc = il3945_alloc_bcast_station(il);
4bc85c13
WYG
2381 if (rc)
2382 return rc;
2383
a6766ccd 2384 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 2385 IL_WARN("Exit pending; will not bring the NIC up\n");
4bc85c13
WYG
2386 return -EIO;
2387 }
2388
46bc8d4b 2389 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 2390 IL_ERR("ucode not available for device bring up\n");
4bc85c13
WYG
2391 return -EIO;
2392 }
2393
2394 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 2395 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 2396 clear_bit(S_RFKILL, &il->status);
4bc85c13 2397 else {
bc269a8e 2398 set_bit(S_RFKILL, &il->status);
5f5deff3 2399 return -ERFKILL;
4bc85c13
WYG
2400 }
2401
841b2cca 2402 _il_wr(il, CSR_INT, 0xFFFFFFFF);
4bc85c13 2403
46bc8d4b 2404 rc = il3945_hw_nic_init(il);
4bc85c13 2405 if (rc) {
9406f797 2406 IL_ERR("Unable to int nic\n");
4bc85c13
WYG
2407 return rc;
2408 }
2409
2410 /* make sure rfkill handshake bits are cleared */
841b2cca 2411 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 2412 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4bc85c13
WYG
2413
2414 /* clear (again), then enable host interrupts */
841b2cca 2415 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 2416 il_enable_interrupts(il);
4bc85c13
WYG
2417
2418 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG
2419 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2420 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4bc85c13
WYG
2421
2422 /* Copy original ucode data image from disk into backup cache.
2423 * This will be used to initialize the on-board processor's
2424 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG
2425 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2426 il->ucode_data.len);
4bc85c13
WYG
2427
2428 /* We return success when we resume from suspend and rf_kill is on. */
bc269a8e 2429 if (test_bit(S_RFKILL, &il->status))
4bc85c13
WYG
2430 return 0;
2431
2432 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2433
2434 /* load bootstrap state machine,
2435 * load bootstrap program into processor's memory,
2436 * prepare to load the "initialize" uCode */
1600b875 2437 rc = il->ops->load_ucode(il);
4bc85c13
WYG
2438
2439 if (rc) {
e7392364 2440 IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
4bc85c13
WYG
2441 continue;
2442 }
2443
2444 /* start card; "initialize" will load runtime ucode */
46bc8d4b 2445 il3945_nic_start(il);
4bc85c13 2446
58de00a4 2447 D_INFO(DRV_NAME " is coming up\n");
4bc85c13
WYG
2448
2449 return 0;
2450 }
2451
a6766ccd 2452 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 2453 __il3945_down(il);
a6766ccd 2454 clear_bit(S_EXIT_PENDING, &il->status);
4bc85c13
WYG
2455
2456 /* tried to restart and config the device for as long as our
2457 * patience could withstand */
9406f797 2458 IL_ERR("Unable to initialize device after %d attempts.\n", i);
4bc85c13
WYG
2459 return -EIO;
2460}
2461
4bc85c13
WYG
2462/*****************************************************************************
2463 *
2464 * Workqueue callbacks
2465 *
2466 *****************************************************************************/
2467
e7392364
SG
2468static void
2469il3945_bg_init_alive_start(struct work_struct *data)
4bc85c13 2470{
46bc8d4b 2471 struct il_priv *il =
e2ebc833 2472 container_of(data, struct il_priv, init_alive_start.work);
4bc85c13 2473
46bc8d4b 2474 mutex_lock(&il->mutex);
a6766ccd 2475 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 2476 goto out;
4bc85c13 2477
46bc8d4b 2478 il3945_init_alive_start(il);
28a6e577 2479out:
46bc8d4b 2480 mutex_unlock(&il->mutex);
4bc85c13
WYG
2481}
2482
e7392364
SG
2483static void
2484il3945_bg_alive_start(struct work_struct *data)
4bc85c13 2485{
46bc8d4b 2486 struct il_priv *il =
e2ebc833 2487 container_of(data, struct il_priv, alive_start.work);
4bc85c13 2488
46bc8d4b 2489 mutex_lock(&il->mutex);
210787e8 2490 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
28a6e577 2491 goto out;
4bc85c13 2492
46bc8d4b 2493 il3945_alive_start(il);
28a6e577 2494out:
46bc8d4b 2495 mutex_unlock(&il->mutex);
4bc85c13
WYG
2496}
2497
2498/*
2499 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2500 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2501 * *is* readable even when device has been SW_RESET into low power mode
2502 * (e.g. during RF KILL).
2503 */
e7392364
SG
2504static void
2505il3945_rfkill_poll(struct work_struct *data)
4bc85c13 2506{
46bc8d4b 2507 struct il_priv *il =
e2ebc833 2508 container_of(data, struct il_priv, _3945.rfkill_poll.work);
bc269a8e 2509 bool old_rfkill = test_bit(S_RFKILL, &il->status);
e7392364
SG
2510 bool new_rfkill =
2511 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
4bc85c13
WYG
2512
2513 if (new_rfkill != old_rfkill) {
2514 if (new_rfkill)
bc269a8e 2515 set_bit(S_RFKILL, &il->status);
4bc85c13 2516 else
bc269a8e 2517 clear_bit(S_RFKILL, &il->status);
4bc85c13 2518
46bc8d4b 2519 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
4bc85c13 2520
58de00a4 2521 D_RF_KILL("RF_KILL bit toggled to %s.\n",
e7392364 2522 new_rfkill ? "disable radio" : "enable radio");
4bc85c13
WYG
2523 }
2524
2525 /* Keep this running, even if radio now enabled. This will be
2526 * cancelled in mac_start() if system decides to start again */
46bc8d4b 2527 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2528 round_jiffies_relative(2 * HZ));
2529
2530}
2531
e7392364
SG
2532int
2533il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
4bc85c13 2534{
e2ebc833 2535 struct il_host_cmd cmd = {
4d69c752 2536 .id = C_SCAN,
e2ebc833 2537 .len = sizeof(struct il3945_scan_cmd),
4bc85c13
WYG
2538 .flags = CMD_SIZE_HUGE,
2539 };
e2ebc833 2540 struct il3945_scan_cmd *scan;
4bc85c13
WYG
2541 u8 n_probes = 0;
2542 enum ieee80211_band band;
2543 bool is_active = false;
2544 int ret;
dd6d2a8a 2545 u16 len;
4bc85c13 2546
46bc8d4b 2547 lockdep_assert_held(&il->mutex);
4bc85c13 2548
46bc8d4b 2549 if (!il->scan_cmd) {
e7392364
SG
2550 il->scan_cmd =
2551 kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2552 GFP_KERNEL);
46bc8d4b 2553 if (!il->scan_cmd) {
58de00a4 2554 D_SCAN("Fail to allocate scan memory\n");
4bc85c13
WYG
2555 return -ENOMEM;
2556 }
2557 }
46bc8d4b 2558 scan = il->scan_cmd;
e2ebc833 2559 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
4bc85c13 2560
e2ebc833
SG
2561 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2562 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
4bc85c13 2563
7c2cde2e 2564 if (il_is_associated(il)) {
dd6d2a8a 2565 u16 interval;
4bc85c13
WYG
2566 u32 extra;
2567 u32 suspend_time = 100;
2568 u32 scan_suspend_time = 100;
2569
58de00a4 2570 D_INFO("Scanning while associated...\n");
4bc85c13 2571
dd6d2a8a 2572 interval = vif->bss_conf.beacon_int;
4bc85c13
WYG
2573
2574 scan->suspend_time = 0;
2575 scan->max_out_time = cpu_to_le32(200 * 1024);
2576 if (!interval)
2577 interval = suspend_time;
2578 /*
2579 * suspend time format:
2580 * 0-19: beacon interval in usec (time before exec.)
2581 * 20-23: 0
2582 * 24-31: number of beacons (suspend between channels)
2583 */
2584
2585 extra = (suspend_time / interval) << 24;
e7392364
SG
2586 scan_suspend_time =
2587 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
4bc85c13
WYG
2588
2589 scan->suspend_time = cpu_to_le32(scan_suspend_time);
58de00a4 2590 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 2591 scan_suspend_time, interval);
4bc85c13
WYG
2592 }
2593
46bc8d4b 2594 if (il->scan_request->n_ssids) {
4bc85c13 2595 int i, p = 0;
58de00a4 2596 D_SCAN("Kicking off active scan\n");
46bc8d4b 2597 for (i = 0; i < il->scan_request->n_ssids; i++) {
4bc85c13 2598 /* always does wildcard anyway */
46bc8d4b 2599 if (!il->scan_request->ssids[i].ssid_len)
4bc85c13
WYG
2600 continue;
2601 scan->direct_scan[p].id = WLAN_EID_SSID;
2602 scan->direct_scan[p].len =
e7392364 2603 il->scan_request->ssids[i].ssid_len;
4bc85c13 2604 memcpy(scan->direct_scan[p].ssid,
46bc8d4b
SG
2605 il->scan_request->ssids[i].ssid,
2606 il->scan_request->ssids[i].ssid_len);
4bc85c13
WYG
2607 n_probes++;
2608 p++;
2609 }
2610 is_active = true;
2611 } else
58de00a4 2612 D_SCAN("Kicking off passive scan.\n");
4bc85c13
WYG
2613
2614 /* We don't build a direct scan probe request; the uCode will do
2615 * that based on the direct_mask added to each channel entry */
2616 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 2617 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
4bc85c13
WYG
2618 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2619
2620 /* flags + rate selection */
2621
46bc8d4b 2622 switch (il->scan_band) {
4bc85c13
WYG
2623 case IEEE80211_BAND_2GHZ:
2624 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2eb05816 2625 scan->tx_cmd.rate = RATE_1M_PLCP;
4bc85c13
WYG
2626 band = IEEE80211_BAND_2GHZ;
2627 break;
2628 case IEEE80211_BAND_5GHZ:
2eb05816 2629 scan->tx_cmd.rate = RATE_6M_PLCP;
4bc85c13
WYG
2630 band = IEEE80211_BAND_5GHZ;
2631 break;
2632 default:
9406f797 2633 IL_WARN("Invalid scan band\n");
4bc85c13
WYG
2634 return -EIO;
2635 }
2636
2637 /*
68acc4af
SG
2638 * If active scaning is requested but a certain channel is marked
2639 * passive, we can do active scanning if we detect transmissions. For
2640 * passive only scanning disable switching to active on any channel.
4bc85c13 2641 */
e7392364 2642 scan->good_CRC_th =
68acc4af 2643 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
e7392364
SG
2644
2645 len =
2646 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2647 vif->addr, il->scan_request->ie,
2648 il->scan_request->ie_len,
2649 IL_MAX_SCAN_SIZE - sizeof(*scan));
dd6d2a8a
SG
2650 scan->tx_cmd.len = cpu_to_le16(len);
2651
4bc85c13 2652 /* select Rx antennas */
46bc8d4b 2653 scan->flags |= il3945_get_antenna_flags(il);
4bc85c13 2654
e7392364
SG
2655 scan->channel_count =
2656 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2657 (void *)&scan->data[len], vif);
4bc85c13 2658 if (scan->channel_count == 0) {
58de00a4 2659 D_SCAN("channel count %d\n", scan->channel_count);
4bc85c13
WYG
2660 return -EIO;
2661 }
2662
e7392364
SG
2663 cmd.len +=
2664 le16_to_cpu(scan->tx_cmd.len) +
e2ebc833 2665 scan->channel_count * sizeof(struct il3945_scan_channel);
4bc85c13
WYG
2666 cmd.data = scan;
2667 scan->len = cpu_to_le16(cmd.len);
2668
a6766ccd 2669 set_bit(S_SCAN_HW, &il->status);
46bc8d4b 2670 ret = il_send_cmd_sync(il, &cmd);
4bc85c13 2671 if (ret)
a6766ccd 2672 clear_bit(S_SCAN_HW, &il->status);
4bc85c13
WYG
2673 return ret;
2674}
2675
e7392364
SG
2676void
2677il3945_post_scan(struct il_priv *il)
4bc85c13 2678{
4bc85c13
WYG
2679 /*
2680 * Since setting the RXON may have been deferred while
2681 * performing the scan, fire one off if needed
2682 */
c8b03958 2683 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
83007196 2684 il3945_commit_rxon(il);
4bc85c13
WYG
2685}
2686
e7392364
SG
2687static void
2688il3945_bg_restart(struct work_struct *data)
4bc85c13 2689{
46bc8d4b 2690 struct il_priv *il = container_of(data, struct il_priv, restart);
4bc85c13 2691
a6766ccd 2692 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2693 return;
2694
a6766ccd 2695 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 2696 mutex_lock(&il->mutex);
46bc8d4b
SG
2697 il->is_open = 0;
2698 mutex_unlock(&il->mutex);
2699 il3945_down(il);
2700 ieee80211_restart_hw(il->hw);
4bc85c13 2701 } else {
46bc8d4b 2702 il3945_down(il);
4bc85c13 2703
46bc8d4b 2704 mutex_lock(&il->mutex);
a6766ccd 2705 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 2706 mutex_unlock(&il->mutex);
4bc85c13 2707 return;
28a6e577 2708 }
4bc85c13 2709
46bc8d4b
SG
2710 __il3945_up(il);
2711 mutex_unlock(&il->mutex);
4bc85c13
WYG
2712 }
2713}
2714
e7392364
SG
2715static void
2716il3945_bg_rx_replenish(struct work_struct *data)
4bc85c13 2717{
e7392364 2718 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
4bc85c13 2719
46bc8d4b 2720 mutex_lock(&il->mutex);
a6766ccd 2721 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 2722 goto out;
4bc85c13 2723
46bc8d4b 2724 il3945_rx_replenish(il);
28a6e577 2725out:
46bc8d4b 2726 mutex_unlock(&il->mutex);
4bc85c13
WYG
2727}
2728
e7392364
SG
2729void
2730il3945_post_associate(struct il_priv *il)
4bc85c13
WYG
2731{
2732 int rc = 0;
2733 struct ieee80211_conf *conf = NULL;
4bc85c13 2734
83007196 2735 if (!il->vif || !il->is_open)
4bc85c13
WYG
2736 return;
2737
83007196 2738 D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
c8b03958 2739 il->active.bssid_addr);
4bc85c13 2740
a6766ccd 2741 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2742 return;
2743
46bc8d4b 2744 il_scan_cancel_timeout(il, 200);
4bc85c13 2745
6278ddab 2746 conf = &il->hw->conf;
4bc85c13 2747
c8b03958 2748 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 2749 il3945_commit_rxon(il);
4bc85c13 2750
83007196 2751 rc = il_send_rxon_timing(il);
4bc85c13 2752 if (rc)
e7392364 2753 IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
4bc85c13 2754
c8b03958 2755 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
4bc85c13 2756
83007196 2757 il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
4bc85c13 2758
83007196
SG
2759 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2760 il->vif->bss_conf.beacon_int);
4bc85c13 2761
83007196 2762 if (il->vif->bss_conf.use_short_preamble)
c8b03958 2763 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2764 else
c8b03958 2765 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2766
c8b03958 2767 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
83007196 2768 if (il->vif->bss_conf.use_short_slot)
c8b03958 2769 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
4bc85c13 2770 else
c8b03958 2771 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
4bc85c13
WYG
2772 }
2773
83007196 2774 il3945_commit_rxon(il);
4bc85c13 2775
83007196 2776 switch (il->vif->type) {
4bc85c13 2777 case NL80211_IFTYPE_STATION:
46bc8d4b 2778 il3945_rate_scale_init(il->hw, IL_AP_ID);
4bc85c13
WYG
2779 break;
2780 case NL80211_IFTYPE_ADHOC:
46bc8d4b 2781 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2782 break;
2783 default:
e7392364 2784 IL_ERR("%s Should not be called in %d mode\n", __func__,
83007196 2785 il->vif->type);
4bc85c13
WYG
2786 break;
2787 }
2788}
2789
2790/*****************************************************************************
2791 *
2792 * mac80211 entry point functions
2793 *
2794 *****************************************************************************/
2795
2796#define UCODE_READY_TIMEOUT (2 * HZ)
2797
e7392364
SG
2798static int
2799il3945_mac_start(struct ieee80211_hw *hw)
4bc85c13 2800{
46bc8d4b 2801 struct il_priv *il = hw->priv;
4bc85c13
WYG
2802 int ret;
2803
4bc85c13 2804 /* we should be verifying the device is ready to be opened */
46bc8d4b 2805 mutex_lock(&il->mutex);
9ce7b73c 2806 D_MAC80211("enter\n");
4bc85c13
WYG
2807
2808 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2809 * ucode filename and max sizes are card-specific. */
2810
46bc8d4b
SG
2811 if (!il->ucode_code.len) {
2812 ret = il3945_read_ucode(il);
4bc85c13 2813 if (ret) {
9406f797 2814 IL_ERR("Could not read microcode: %d\n", ret);
46bc8d4b 2815 mutex_unlock(&il->mutex);
4bc85c13
WYG
2816 goto out_release_irq;
2817 }
2818 }
2819
46bc8d4b 2820 ret = __il3945_up(il);
4bc85c13 2821
46bc8d4b 2822 mutex_unlock(&il->mutex);
4bc85c13
WYG
2823
2824 if (ret)
2825 goto out_release_irq;
2826
58de00a4 2827 D_INFO("Start UP work.\n");
4bc85c13
WYG
2828
2829 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
2830 * mac80211 will not be run successfully. */
46bc8d4b 2831 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG
2832 test_bit(S_READY, &il->status),
2833 UCODE_READY_TIMEOUT);
4bc85c13 2834 if (!ret) {
a6766ccd 2835 if (!test_bit(S_READY, &il->status)) {
e7392364
SG
2836 IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2837 jiffies_to_msecs(UCODE_READY_TIMEOUT));
4bc85c13
WYG
2838 ret = -ETIMEDOUT;
2839 goto out_release_irq;
2840 }
2841 }
2842
2843 /* ucode is running and will send rfkill notifications,
2844 * no need to poll the killswitch state anymore */
46bc8d4b 2845 cancel_delayed_work(&il->_3945.rfkill_poll);
4bc85c13 2846
46bc8d4b 2847 il->is_open = 1;
58de00a4 2848 D_MAC80211("leave\n");
4bc85c13
WYG
2849 return 0;
2850
2851out_release_irq:
46bc8d4b 2852 il->is_open = 0;
58de00a4 2853 D_MAC80211("leave - failed\n");
4bc85c13
WYG
2854 return ret;
2855}
2856
e7392364
SG
2857static void
2858il3945_mac_stop(struct ieee80211_hw *hw)
4bc85c13 2859{
46bc8d4b 2860 struct il_priv *il = hw->priv;
4bc85c13 2861
58de00a4 2862 D_MAC80211("enter\n");
4bc85c13 2863
46bc8d4b 2864 if (!il->is_open) {
58de00a4 2865 D_MAC80211("leave - skip\n");
4bc85c13
WYG
2866 return;
2867 }
2868
46bc8d4b 2869 il->is_open = 0;
4bc85c13 2870
46bc8d4b 2871 il3945_down(il);
4bc85c13 2872
46bc8d4b 2873 flush_workqueue(il->workqueue);
4bc85c13
WYG
2874
2875 /* start polling the killswitch state again */
46bc8d4b 2876 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2877 round_jiffies_relative(2 * HZ));
2878
58de00a4 2879 D_MAC80211("leave\n");
4bc85c13
WYG
2880}
2881
e7392364 2882static void
36323f81
TH
2883il3945_mac_tx(struct ieee80211_hw *hw,
2884 struct ieee80211_tx_control *control,
2885 struct sk_buff *skb)
4bc85c13 2886{
46bc8d4b 2887 struct il_priv *il = hw->priv;
4bc85c13 2888
58de00a4 2889 D_MAC80211("enter\n");
4bc85c13 2890
58de00a4 2891 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 2892 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
4bc85c13 2893
36323f81 2894 if (il3945_tx_skb(il, control->sta, skb))
4bc85c13
WYG
2895 dev_kfree_skb_any(skb);
2896
58de00a4 2897 D_MAC80211("leave\n");
4bc85c13
WYG
2898}
2899
e7392364
SG
2900void
2901il3945_config_ap(struct il_priv *il)
4bc85c13 2902{
83007196 2903 struct ieee80211_vif *vif = il->vif;
4bc85c13
WYG
2904 int rc = 0;
2905
a6766ccd 2906 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2907 return;
2908
2909 /* The following should be done only at AP bring up */
7c2cde2e 2910 if (!(il_is_associated(il))) {
4bc85c13
WYG
2911
2912 /* RXON - unassoc (to set timing command) */
c8b03958 2913 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 2914 il3945_commit_rxon(il);
4bc85c13
WYG
2915
2916 /* RXON Timing */
83007196 2917 rc = il_send_rxon_timing(il);
4bc85c13 2918 if (rc)
4d69c752 2919 IL_WARN("C_RXON_TIMING failed - "
e7392364 2920 "Attempting to continue.\n");
4bc85c13 2921
c8b03958 2922 il->staging.assoc_id = 0;
4bc85c13
WYG
2923
2924 if (vif->bss_conf.use_short_preamble)
c8b03958 2925 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2926 else
c8b03958 2927 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2928
c8b03958 2929 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
4bc85c13 2930 if (vif->bss_conf.use_short_slot)
c8b03958 2931 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
4bc85c13 2932 else
c8b03958 2933 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
4bc85c13
WYG
2934 }
2935 /* restore RXON assoc */
c8b03958 2936 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
83007196 2937 il3945_commit_rxon(il);
4bc85c13 2938 }
46bc8d4b 2939 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2940}
2941
e7392364
SG
2942static int
2943il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2944 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2945 struct ieee80211_key_conf *key)
4bc85c13 2946{
46bc8d4b 2947 struct il_priv *il = hw->priv;
4bc85c13 2948 int ret = 0;
e2ebc833 2949 u8 sta_id = IL_INVALID_STATION;
4bc85c13
WYG
2950 u8 static_key;
2951
58de00a4 2952 D_MAC80211("enter\n");
4bc85c13 2953
e2ebc833 2954 if (il3945_mod_params.sw_crypto) {
58de00a4 2955 D_MAC80211("leave - hwcrypto disabled\n");
4bc85c13
WYG
2956 return -EOPNOTSUPP;
2957 }
2958
2959 /*
2960 * To support IBSS RSN, don't program group keys in IBSS, the
2961 * hardware will then not attempt to decrypt the frames.
2962 */
2963 if (vif->type == NL80211_IFTYPE_ADHOC &&
9ce7b73c
SG
2964 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2965 D_MAC80211("leave - IBSS RSN\n");
4bc85c13 2966 return -EOPNOTSUPP;
9ce7b73c 2967 }
4bc85c13 2968
7c2cde2e 2969 static_key = !il_is_associated(il);
4bc85c13
WYG
2970
2971 if (!static_key) {
83007196 2972 sta_id = il_sta_id_or_broadcast(il, sta);
9ce7b73c
SG
2973 if (sta_id == IL_INVALID_STATION) {
2974 D_MAC80211("leave - station not found\n");
4bc85c13 2975 return -EINVAL;
9ce7b73c 2976 }
4bc85c13
WYG
2977 }
2978
46bc8d4b
SG
2979 mutex_lock(&il->mutex);
2980 il_scan_cancel_timeout(il, 100);
4bc85c13
WYG
2981
2982 switch (cmd) {
2983 case SET_KEY:
2984 if (static_key)
46bc8d4b 2985 ret = il3945_set_static_key(il, key);
4bc85c13 2986 else
46bc8d4b 2987 ret = il3945_set_dynamic_key(il, key, sta_id);
58de00a4 2988 D_MAC80211("enable hwcrypto key\n");
4bc85c13
WYG
2989 break;
2990 case DISABLE_KEY:
2991 if (static_key)
46bc8d4b 2992 ret = il3945_remove_static_key(il);
4bc85c13 2993 else
46bc8d4b 2994 ret = il3945_clear_sta_key_info(il, sta_id);
58de00a4 2995 D_MAC80211("disable hwcrypto key\n");
4bc85c13
WYG
2996 break;
2997 default:
2998 ret = -EINVAL;
2999 }
3000
9ce7b73c 3001 D_MAC80211("leave ret %d\n", ret);
46bc8d4b 3002 mutex_unlock(&il->mutex);
4bc85c13
WYG
3003
3004 return ret;
3005}
3006
e7392364
SG
3007static int
3008il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3009 struct ieee80211_sta *sta)
4bc85c13 3010{
46bc8d4b 3011 struct il_priv *il = hw->priv;
e2ebc833 3012 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
4bc85c13
WYG
3013 int ret;
3014 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3015 u8 sta_id;
3016
46bc8d4b 3017 mutex_lock(&il->mutex);
9ce7b73c 3018 D_INFO("station %pM\n", sta->addr);
e2ebc833 3019 sta_priv->common.sta_id = IL_INVALID_STATION;
4bc85c13 3020
83007196 3021 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
4bc85c13 3022 if (ret) {
e7392364 3023 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
4bc85c13 3024 /* Should we return success if return code is EEXIST ? */
46bc8d4b 3025 mutex_unlock(&il->mutex);
4bc85c13
WYG
3026 return ret;
3027 }
3028
3029 sta_priv->common.sta_id = sta_id;
3030
3031 /* Initialize rate scaling */
e7392364 3032 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG
3033 il3945_rs_rate_init(il, sta, sta_id);
3034 mutex_unlock(&il->mutex);
4bc85c13
WYG
3035
3036 return 0;
3037}
3038
e7392364
SG
3039static void
3040il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3041 unsigned int *total_flags, u64 multicast)
4bc85c13 3042{
46bc8d4b 3043 struct il_priv *il = hw->priv;
4bc85c13 3044 __le32 filter_or = 0, filter_nand = 0;
4bc85c13
WYG
3045
3046#define CHK(test, flag) do { \
3047 if (*total_flags & (test)) \
3048 filter_or |= (flag); \
3049 else \
3050 filter_nand |= (flag); \
3051 } while (0)
3052
e7392364
SG
3053 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3054 *total_flags);
4bc85c13
WYG
3055
3056 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3057 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3058 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3059
3060#undef CHK
3061
46bc8d4b 3062 mutex_lock(&il->mutex);
4bc85c13 3063
c8b03958
SG
3064 il->staging.filter_flags &= ~filter_nand;
3065 il->staging.filter_flags |= filter_or;
4bc85c13
WYG
3066
3067 /*
3068 * Not committing directly because hardware can perform a scan,
3069 * but even if hw is ready, committing here breaks for some reason,
3070 * we'll eventually commit the filter flags change anyway.
3071 */
3072
46bc8d4b 3073 mutex_unlock(&il->mutex);
4bc85c13
WYG
3074
3075 /*
3076 * Receiving all multicast frames is always enabled by the
e2ebc833 3077 * default flags setup in il_connection_init_rx_config()
4bc85c13
WYG
3078 * since we currently do not support programming multicast
3079 * filters into the device.
3080 */
e7392364
SG
3081 *total_flags &=
3082 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3083 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4bc85c13
WYG
3084}
3085
4bc85c13
WYG
3086/*****************************************************************************
3087 *
3088 * sysfs attributes
3089 *
3090 *****************************************************************************/
3091
d3175167 3092#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3093
3094/*
3095 * The following adds a new attribute to the sysfs representation
3096 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3097 * used for controlling the debug level.
3098 *
3099 * See the level definitions in iwl for details.
3100 *
3101 * The debug_level being managed using sysfs below is a per device debug
3102 * level that is used instead of the global debug level if it (the per
3103 * device debug level) is set.
3104 */
e7392364
SG
3105static ssize_t
3106il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3107 char *buf)
4bc85c13 3108{
46bc8d4b
SG
3109 struct il_priv *il = dev_get_drvdata(d);
3110 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4bc85c13 3111}
e7392364
SG
3112
3113static ssize_t
3114il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3115 const char *buf, size_t count)
4bc85c13 3116{
46bc8d4b 3117 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3118 unsigned long val;
3119 int ret;
3120
27d7f477 3121 ret = kstrtoul(buf, 0, &val);
4bc85c13 3122 if (ret)
9406f797 3123 IL_INFO("%s is not in hex or decimal form.\n", buf);
288f9954 3124 else
46bc8d4b 3125 il->debug_level = val;
288f9954 3126
4bc85c13
WYG
3127 return strnlen(buf, count);
3128}
3129
e7392364
SG
3130static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il3945_show_debug_level,
3131 il3945_store_debug_level);
4bc85c13 3132
d3175167 3133#endif /* CONFIG_IWLEGACY_DEBUG */
4bc85c13 3134
e7392364
SG
3135static ssize_t
3136il3945_show_temperature(struct device *d, struct device_attribute *attr,
3137 char *buf)
4bc85c13 3138{
46bc8d4b 3139 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3140
46bc8d4b 3141 if (!il_is_alive(il))
4bc85c13
WYG
3142 return -EAGAIN;
3143
46bc8d4b 3144 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
4bc85c13
WYG
3145}
3146
e2ebc833 3147static DEVICE_ATTR(temperature, S_IRUGO, il3945_show_temperature, NULL);
4bc85c13 3148
e7392364
SG
3149static ssize_t
3150il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3151{
46bc8d4b
SG
3152 struct il_priv *il = dev_get_drvdata(d);
3153 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4bc85c13
WYG
3154}
3155
e7392364
SG
3156static ssize_t
3157il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3158 const char *buf, size_t count)
4bc85c13 3159{
46bc8d4b 3160 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3161 char *p = (char *)buf;
3162 u32 val;
3163
3164 val = simple_strtoul(p, &p, 10);
3165 if (p == buf)
9406f797 3166 IL_INFO(": %s is not in decimal form.\n", buf);
4bc85c13 3167 else
46bc8d4b 3168 il3945_hw_reg_set_txpower(il, val);
4bc85c13
WYG
3169
3170 return count;
3171}
3172
e7392364
SG
3173static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il3945_show_tx_power,
3174 il3945_store_tx_power);
4bc85c13 3175
e7392364
SG
3176static ssize_t
3177il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3178{
46bc8d4b 3179 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3180
c8b03958 3181 return sprintf(buf, "0x%04X\n", il->active.flags);
4bc85c13
WYG
3182}
3183
e7392364
SG
3184static ssize_t
3185il3945_store_flags(struct device *d, struct device_attribute *attr,
3186 const char *buf, size_t count)
4bc85c13 3187{
46bc8d4b 3188 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3189 u32 flags = simple_strtoul(buf, NULL, 0);
4bc85c13 3190
46bc8d4b 3191 mutex_lock(&il->mutex);
c8b03958 3192 if (le32_to_cpu(il->staging.flags) != flags) {
4bc85c13 3193 /* Cancel any currently running scans... */
46bc8d4b 3194 if (il_scan_cancel_timeout(il, 100))
9406f797 3195 IL_WARN("Could not cancel scan.\n");
4bc85c13 3196 else {
e7392364 3197 D_INFO("Committing rxon.flags = 0x%04X\n", flags);
c8b03958 3198 il->staging.flags = cpu_to_le32(flags);
83007196 3199 il3945_commit_rxon(il);
4bc85c13
WYG
3200 }
3201 }
46bc8d4b 3202 mutex_unlock(&il->mutex);
4bc85c13
WYG
3203
3204 return count;
3205}
3206
e7392364
SG
3207static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, il3945_show_flags,
3208 il3945_store_flags);
4bc85c13 3209
e7392364
SG
3210static ssize_t
3211il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3212 char *buf)
4bc85c13 3213{
46bc8d4b 3214 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3215
c8b03958 3216 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
4bc85c13
WYG
3217}
3218
e7392364
SG
3219static ssize_t
3220il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3221 const char *buf, size_t count)
4bc85c13 3222{
46bc8d4b 3223 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3224 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3225
46bc8d4b 3226 mutex_lock(&il->mutex);
c8b03958 3227 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
4bc85c13 3228 /* Cancel any currently running scans... */
46bc8d4b 3229 if (il_scan_cancel_timeout(il, 100))
9406f797 3230 IL_WARN("Could not cancel scan.\n");
4bc85c13 3231 else {
e7392364
SG
3232 D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3233 filter_flags);
c8b03958 3234 il->staging.filter_flags = cpu_to_le32(filter_flags);
83007196 3235 il3945_commit_rxon(il);
4bc85c13
WYG
3236 }
3237 }
46bc8d4b 3238 mutex_unlock(&il->mutex);
4bc85c13
WYG
3239
3240 return count;
3241}
3242
e2ebc833
SG
3243static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, il3945_show_filter_flags,
3244 il3945_store_filter_flags);
4bc85c13 3245
e7392364
SG
3246static ssize_t
3247il3945_show_measurement(struct device *d, struct device_attribute *attr,
3248 char *buf)
4bc85c13 3249{
46bc8d4b 3250 struct il_priv *il = dev_get_drvdata(d);
e2ebc833 3251 struct il_spectrum_notification measure_report;
4bc85c13 3252 u32 size = sizeof(measure_report), len = 0, ofs = 0;
1722f8e1 3253 u8 *data = (u8 *) &measure_report;
4bc85c13
WYG
3254 unsigned long flags;
3255
46bc8d4b
SG
3256 spin_lock_irqsave(&il->lock, flags);
3257 if (!(il->measurement_status & MEASUREMENT_READY)) {
3258 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
3259 return 0;
3260 }
46bc8d4b
SG
3261 memcpy(&measure_report, &il->measure_report, size);
3262 il->measurement_status = 0;
3263 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3264
232913b5 3265 while (size && PAGE_SIZE - len) {
4bc85c13
WYG
3266 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3267 PAGE_SIZE - len, 1);
3268 len = strlen(buf);
3269 if (PAGE_SIZE - len)
3270 buf[len++] = '\n';
3271
3272 ofs += 16;
3273 size -= min(size, 16U);
3274 }
3275
3276 return len;
3277}
3278
e7392364
SG
3279static ssize_t
3280il3945_store_measurement(struct device *d, struct device_attribute *attr,
3281 const char *buf, size_t count)
4bc85c13 3282{
46bc8d4b 3283 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3284 struct ieee80211_measurement_params params = {
c8b03958 3285 .channel = le16_to_cpu(il->active.channel),
46bc8d4b 3286 .start_time = cpu_to_le64(il->_3945.last_tsf),
4bc85c13
WYG
3287 .duration = cpu_to_le16(1),
3288 };
e2ebc833 3289 u8 type = IL_MEASURE_BASIC;
4bc85c13
WYG
3290 u8 buffer[32];
3291 u8 channel;
3292
3293 if (count) {
3294 char *p = buffer;
407ee237 3295 strlcpy(buffer, buf, sizeof(buffer));
4bc85c13
WYG
3296 channel = simple_strtoul(p, NULL, 0);
3297 if (channel)
3298 params.channel = channel;
3299
3300 p = buffer;
3301 while (*p && *p != ' ')
3302 p++;
3303 if (*p)
3304 type = simple_strtoul(p + 1, NULL, 0);
3305 }
3306
e7392364
SG
3307 D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3308 type, params.channel, buf);
46bc8d4b 3309 il3945_get_measurement(il, &params, type);
4bc85c13
WYG
3310
3311 return count;
3312}
3313
e7392364
SG
3314static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, il3945_show_measurement,
3315 il3945_store_measurement);
4bc85c13 3316
e7392364
SG
3317static ssize_t
3318il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3319 const char *buf, size_t count)
4bc85c13 3320{
46bc8d4b 3321 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3322
46bc8d4b
SG
3323 il->retry_rate = simple_strtoul(buf, NULL, 0);
3324 if (il->retry_rate <= 0)
3325 il->retry_rate = 1;
4bc85c13
WYG
3326
3327 return count;
3328}
3329
e7392364
SG
3330static ssize_t
3331il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3332 char *buf)
4bc85c13 3333{
46bc8d4b
SG
3334 struct il_priv *il = dev_get_drvdata(d);
3335 return sprintf(buf, "%d", il->retry_rate);
4bc85c13
WYG
3336}
3337
e2ebc833
SG
3338static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, il3945_show_retry_rate,
3339 il3945_store_retry_rate);
4bc85c13 3340
e7392364
SG
3341static ssize_t
3342il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13
WYG
3343{
3344 /* all this shit doesn't belong into sysfs anyway */
3345 return 0;
3346}
3347
e2ebc833 3348static DEVICE_ATTR(channels, S_IRUSR, il3945_show_channels, NULL);
4bc85c13 3349
e7392364
SG
3350static ssize_t
3351il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3352{
46bc8d4b 3353 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3354
46bc8d4b 3355 if (!il_is_alive(il))
4bc85c13
WYG
3356 return -EAGAIN;
3357
e2ebc833 3358 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
4bc85c13
WYG
3359}
3360
e7392364
SG
3361static ssize_t
3362il3945_store_antenna(struct device *d, struct device_attribute *attr,
3363 const char *buf, size_t count)
4bc85c13 3364{
46bc8d4b 3365 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
4bc85c13
WYG
3366 int ant;
3367
3368 if (count == 0)
3369 return 0;
3370
3371 if (sscanf(buf, "%1i", &ant) != 1) {
58de00a4 3372 D_INFO("not in hex or decimal form.\n");
4bc85c13
WYG
3373 return count;
3374 }
3375
232913b5 3376 if (ant >= 0 && ant <= 2) {
58de00a4 3377 D_INFO("Setting antenna select to %d.\n", ant);
e2ebc833 3378 il3945_mod_params.antenna = (enum il3945_antenna)ant;
4bc85c13 3379 } else
58de00a4 3380 D_INFO("Bad antenna select value %d.\n", ant);
4bc85c13 3381
4bc85c13
WYG
3382 return count;
3383}
3384
e7392364
SG
3385static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, il3945_show_antenna,
3386 il3945_store_antenna);
4bc85c13 3387
e7392364
SG
3388static ssize_t
3389il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3390{
46bc8d4b
SG
3391 struct il_priv *il = dev_get_drvdata(d);
3392 if (!il_is_alive(il))
4bc85c13 3393 return -EAGAIN;
46bc8d4b 3394 return sprintf(buf, "0x%08x\n", (int)il->status);
4bc85c13
WYG
3395}
3396
e2ebc833 3397static DEVICE_ATTR(status, S_IRUGO, il3945_show_status, NULL);
4bc85c13 3398
e7392364
SG
3399static ssize_t
3400il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3401 const char *buf, size_t count)
4bc85c13 3402{
46bc8d4b 3403 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3404 char *p = (char *)buf;
3405
3406 if (p[0] == '1')
46bc8d4b 3407 il3945_dump_nic_error_log(il);
4bc85c13
WYG
3408
3409 return strnlen(buf, count);
3410}
3411
e2ebc833 3412static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, il3945_dump_error_log);
4bc85c13
WYG
3413
3414/*****************************************************************************
3415 *
3416 * driver setup and tear down
3417 *
3418 *****************************************************************************/
3419
e7392364
SG
3420static void
3421il3945_setup_deferred_work(struct il_priv *il)
4bc85c13 3422{
46bc8d4b 3423 il->workqueue = create_singlethread_workqueue(DRV_NAME);
4bc85c13 3424
46bc8d4b 3425 init_waitqueue_head(&il->wait_command_queue);
4bc85c13 3426
46bc8d4b
SG
3427 INIT_WORK(&il->restart, il3945_bg_restart);
3428 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3429 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3430 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3431 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
4bc85c13 3432
46bc8d4b 3433 il_setup_scan_deferred_work(il);
4bc85c13 3434
46bc8d4b 3435 il3945_hw_setup_deferred_work(il);
4bc85c13 3436
46bc8d4b
SG
3437 init_timer(&il->watchdog);
3438 il->watchdog.data = (unsigned long)il;
3439 il->watchdog.function = il_bg_watchdog;
4bc85c13 3440
e7392364
SG
3441 tasklet_init(&il->irq_tasklet,
3442 (void (*)(unsigned long))il3945_irq_tasklet,
3443 (unsigned long)il);
4bc85c13
WYG
3444}
3445
e7392364
SG
3446static void
3447il3945_cancel_deferred_work(struct il_priv *il)
4bc85c13 3448{
46bc8d4b 3449 il3945_hw_cancel_deferred_work(il);
4bc85c13 3450
46bc8d4b
SG
3451 cancel_delayed_work_sync(&il->init_alive_start);
3452 cancel_delayed_work(&il->alive_start);
4bc85c13 3453
46bc8d4b 3454 il_cancel_scan_deferred_work(il);
4bc85c13
WYG
3455}
3456
e2ebc833 3457static struct attribute *il3945_sysfs_entries[] = {
4bc85c13
WYG
3458 &dev_attr_antenna.attr,
3459 &dev_attr_channels.attr,
3460 &dev_attr_dump_errors.attr,
3461 &dev_attr_flags.attr,
3462 &dev_attr_filter_flags.attr,
3463 &dev_attr_measurement.attr,
3464 &dev_attr_retry_rate.attr,
3465 &dev_attr_status.attr,
3466 &dev_attr_temperature.attr,
3467 &dev_attr_tx_power.attr,
d3175167 3468#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3469 &dev_attr_debug_level.attr,
3470#endif
3471 NULL
3472};
3473
e2ebc833 3474static struct attribute_group il3945_attribute_group = {
4bc85c13 3475 .name = NULL, /* put in device directory */
e2ebc833 3476 .attrs = il3945_sysfs_entries,
4bc85c13
WYG
3477};
3478
60c46bf8 3479static struct ieee80211_ops il3945_mac_ops __read_mostly = {
e2ebc833
SG
3480 .tx = il3945_mac_tx,
3481 .start = il3945_mac_start,
3482 .stop = il3945_mac_stop,
3483 .add_interface = il_mac_add_interface,
3484 .remove_interface = il_mac_remove_interface,
3485 .change_interface = il_mac_change_interface,
3486 .config = il_mac_config,
3487 .configure_filter = il3945_configure_filter,
3488 .set_key = il3945_mac_set_key,
3489 .conf_tx = il_mac_conf_tx,
3490 .reset_tsf = il_mac_reset_tsf,
3491 .bss_info_changed = il_mac_bss_info_changed,
3492 .hw_scan = il_mac_hw_scan,
3493 .sta_add = il3945_mac_sta_add,
3494 .sta_remove = il_mac_sta_remove,
3495 .tx_last_beacon = il_mac_tx_last_beacon,
70277f47 3496 .flush = il_mac_flush,
4bc85c13
WYG
3497};
3498
e7392364
SG
3499static int
3500il3945_init_drv(struct il_priv *il)
4bc85c13
WYG
3501{
3502 int ret;
46bc8d4b 3503 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 3504
46bc8d4b
SG
3505 il->retry_rate = 1;
3506 il->beacon_skb = NULL;
4bc85c13 3507
46bc8d4b
SG
3508 spin_lock_init(&il->sta_lock);
3509 spin_lock_init(&il->hcmd_lock);
4bc85c13 3510
46bc8d4b 3511 INIT_LIST_HEAD(&il->free_frames);
4bc85c13 3512
46bc8d4b 3513 mutex_init(&il->mutex);
4bc85c13 3514
46bc8d4b
SG
3515 il->ieee_channels = NULL;
3516 il->ieee_rates = NULL;
3517 il->band = IEEE80211_BAND_2GHZ;
4bc85c13 3518
46bc8d4b
SG
3519 il->iw_mode = NL80211_IFTYPE_STATION;
3520 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
4bc85c13
WYG
3521
3522 /* initialize force reset */
46bc8d4b 3523 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
4bc85c13 3524
4bc85c13 3525 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
9406f797 3526 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
e7392364 3527 eeprom->version);
4bc85c13
WYG
3528 ret = -EINVAL;
3529 goto err;
3530 }
46bc8d4b 3531 ret = il_init_channel_map(il);
4bc85c13 3532 if (ret) {
9406f797 3533 IL_ERR("initializing regulatory failed: %d\n", ret);
4bc85c13
WYG
3534 goto err;
3535 }
3536
3537 /* Set up txpower settings in driver for all channels */
46bc8d4b 3538 if (il3945_txpower_set_from_eeprom(il)) {
4bc85c13
WYG
3539 ret = -EIO;
3540 goto err_free_channel_map;
3541 }
3542
46bc8d4b 3543 ret = il_init_geos(il);
4bc85c13 3544 if (ret) {
9406f797 3545 IL_ERR("initializing geos failed: %d\n", ret);
4bc85c13
WYG
3546 goto err_free_channel_map;
3547 }
46bc8d4b 3548 il3945_init_hw_rates(il, il->ieee_rates);
4bc85c13
WYG
3549
3550 return 0;
3551
3552err_free_channel_map:
46bc8d4b 3553 il_free_channel_map(il);
4bc85c13
WYG
3554err:
3555 return ret;
3556}
3557
d3175167 3558#define IL3945_MAX_PROBE_REQUEST 200
4bc85c13 3559
e7392364
SG
3560static int
3561il3945_setup_mac(struct il_priv *il)
4bc85c13
WYG
3562{
3563 int ret;
46bc8d4b 3564 struct ieee80211_hw *hw = il->hw;
4bc85c13
WYG
3565
3566 hw->rate_control_algorithm = "iwl-3945-rs";
e2ebc833
SG
3567 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3568 hw->vif_data_size = sizeof(struct il_vif_priv);
4bc85c13
WYG
3569
3570 /* Tell mac80211 our characteristics */
07db8f8f
SG
3571 hw->flags = IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_SPECTRUM_MGMT |
3572 IEEE80211_HW_SUPPORTS_PS | IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
4bc85c13 3573
8c9c48d5
SG
3574 hw->wiphy->interface_modes =
3575 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
4bc85c13 3576
a2f73b6c
LR
3577 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
3578 hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
3579 REGULATORY_DISABLE_BEACON_HINTS;
4bc85c13 3580
07db8f8f
SG
3581 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3582
4bc85c13
WYG
3583 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3584 /* we create the 802.11 header and a zero-length SSID element */
d3175167 3585 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
4bc85c13
WYG
3586
3587 /* Default value; 4 EDCA QOS priorities */
3588 hw->queues = 4;
3589
46bc8d4b
SG
3590 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
3591 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 3592 &il->bands[IEEE80211_BAND_2GHZ];
4bc85c13 3593
46bc8d4b
SG
3594 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
3595 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 3596 &il->bands[IEEE80211_BAND_5GHZ];
4bc85c13 3597
46bc8d4b 3598 il_leds_init(il);
4bc85c13 3599
46bc8d4b 3600 ret = ieee80211_register_hw(il->hw);
4bc85c13 3601 if (ret) {
9406f797 3602 IL_ERR("Failed to register hw (error %d)\n", ret);
4bc85c13
WYG
3603 return ret;
3604 }
46bc8d4b 3605 il->mac80211_registered = 1;
4bc85c13
WYG
3606
3607 return 0;
3608}
3609
e7392364
SG
3610static int
3611il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4bc85c13 3612{
7c2cde2e 3613 int err = 0;
46bc8d4b 3614 struct il_priv *il;
4bc85c13 3615 struct ieee80211_hw *hw;
e2ebc833
SG
3616 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3617 struct il3945_eeprom *eeprom;
4bc85c13
WYG
3618 unsigned long flags;
3619
3620 /***********************
3621 * 1. Allocating HW data
3622 * ********************/
3623
c39ae9fd
SG
3624 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3625 if (!hw) {
4bc85c13
WYG
3626 err = -ENOMEM;
3627 goto out;
3628 }
46bc8d4b 3629 il = hw->priv;
c39ae9fd 3630 il->hw = hw;
4bc85c13
WYG
3631 SET_IEEE80211_DEV(hw, &pdev->dev);
3632
d3175167 3633 il->cmd_queue = IL39_CMD_QUEUE_NUM;
4bc85c13 3634
4bc85c13
WYG
3635 /*
3636 * Disabling hardware scan means that mac80211 will perform scans
3637 * "the hard way", rather than using device's scan.
3638 */
e2ebc833 3639 if (il3945_mod_params.disable_hw_scan) {
58de00a4 3640 D_INFO("Disabling hw_scan\n");
c39ae9fd 3641 il3945_mac_ops.hw_scan = NULL;
4bc85c13
WYG
3642 }
3643
58de00a4 3644 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 3645 il->cfg = cfg;
c39ae9fd 3646 il->ops = &il3945_ops;
93b7654e
SG
3647#ifdef CONFIG_IWLEGACY_DEBUGFS
3648 il->debugfs_ops = &il3945_debugfs_ops;
3649#endif
46bc8d4b
SG
3650 il->pci_dev = pdev;
3651 il->inta_mask = CSR_INI_SET_MASK;
4bc85c13 3652
4bc85c13
WYG
3653 /***************************
3654 * 2. Initializing PCI bus
3655 * *************************/
e7392364
SG
3656 pci_disable_link_state(pdev,
3657 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3658 PCIE_LINK_STATE_CLKPM);
4bc85c13
WYG
3659
3660 if (pci_enable_device(pdev)) {
3661 err = -ENODEV;
3662 goto out_ieee80211_free_hw;
3663 }
3664
3665 pci_set_master(pdev);
3666
3667 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3668 if (!err)
3669 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3670 if (err) {
9406f797 3671 IL_WARN("No suitable DMA available.\n");
4bc85c13
WYG
3672 goto out_pci_disable_device;
3673 }
3674
46bc8d4b 3675 pci_set_drvdata(pdev, il);
4bc85c13
WYG
3676 err = pci_request_regions(pdev, DRV_NAME);
3677 if (err)
3678 goto out_pci_disable_device;
3679
3680 /***********************
3681 * 3. Read REV Register
3682 * ********************/
a5f16137 3683 il->hw_base = pci_ioremap_bar(pdev, 0);
46bc8d4b 3684 if (!il->hw_base) {
4bc85c13
WYG
3685 err = -ENODEV;
3686 goto out_pci_release_regions;
3687 }
3688
58de00a4 3689 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 3690 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 3691 D_INFO("pci_resource_base = %p\n", il->hw_base);
4bc85c13
WYG
3692
3693 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3694 * PCI Tx retries from interfering with C3 CPU state */
3695 pci_write_config_byte(pdev, 0x41, 0x00);
3696
f03ee2a8 3697 /* these spin locks will be used in apm_init and EEPROM access
4bc85c13
WYG
3698 * we should init now
3699 */
46bc8d4b
SG
3700 spin_lock_init(&il->reg_lock);
3701 spin_lock_init(&il->lock);
4bc85c13
WYG
3702
3703 /*
3704 * stop and reset the on-board processor just in case it is in a
3705 * strange state ... like being left stranded by a primary kernel
3706 * and this is now the kdump kernel trying to start up
3707 */
841b2cca 3708 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
3709
3710 /***********************
3711 * 4. Read EEPROM
3712 * ********************/
3713
3714 /* Read the EEPROM */
46bc8d4b 3715 err = il_eeprom_init(il);
4bc85c13 3716 if (err) {
9406f797 3717 IL_ERR("Unable to init EEPROM\n");
4bc85c13
WYG
3718 goto out_iounmap;
3719 }
3720 /* MAC Address location in EEPROM same for 3945/4965 */
46bc8d4b 3721 eeprom = (struct il3945_eeprom *)il->eeprom;
58de00a4 3722 D_INFO("MAC address: %pM\n", eeprom->mac_address);
46bc8d4b 3723 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
4bc85c13
WYG
3724
3725 /***********************
3726 * 5. Setup HW Constants
3727 * ********************/
3728 /* Device-specific setup */
ca3ae513
WY
3729 err = il3945_hw_set_hw_params(il);
3730 if (err) {
9406f797 3731 IL_ERR("failed to set hw settings\n");
4bc85c13
WYG
3732 goto out_eeprom_free;
3733 }
3734
3735 /***********************
46bc8d4b 3736 * 6. Setup il
4bc85c13
WYG
3737 * ********************/
3738
46bc8d4b 3739 err = il3945_init_drv(il);
4bc85c13 3740 if (err) {
9406f797 3741 IL_ERR("initializing driver failed\n");
4bc85c13
WYG
3742 goto out_unset_hw_params;
3743 }
3744
e7392364 3745 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
4bc85c13
WYG
3746
3747 /***********************
3748 * 7. Setup Services
3749 * ********************/
3750
46bc8d4b
SG
3751 spin_lock_irqsave(&il->lock, flags);
3752 il_disable_interrupts(il);
3753 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3754
46bc8d4b 3755 pci_enable_msi(il->pci_dev);
4bc85c13 3756
e7392364 3757 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
4bc85c13 3758 if (err) {
9406f797 3759 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
4bc85c13
WYG
3760 goto out_disable_msi;
3761 }
3762
e2ebc833 3763 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3764 if (err) {
9406f797 3765 IL_ERR("failed to create sysfs device attributes\n");
4bc85c13
WYG
3766 goto out_release_irq;
3767 }
3768
83007196 3769 il_set_rxon_channel(il, &il->bands[IEEE80211_BAND_2GHZ].channels[5]);
46bc8d4b 3770 il3945_setup_deferred_work(il);
d0c72347 3771 il3945_setup_handlers(il);
46bc8d4b 3772 il_power_initialize(il);
4bc85c13
WYG
3773
3774 /*********************************
3775 * 8. Setup and Register mac80211
3776 * *******************************/
3777
46bc8d4b 3778 il_enable_interrupts(il);
4bc85c13 3779
46bc8d4b 3780 err = il3945_setup_mac(il);
4bc85c13 3781 if (err)
e7392364 3782 goto out_remove_sysfs;
4bc85c13 3783
46bc8d4b 3784 err = il_dbgfs_register(il, DRV_NAME);
4bc85c13 3785 if (err)
e7392364
SG
3786 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
3787 err);
4bc85c13
WYG
3788
3789 /* Start monitoring the killswitch */
e7392364 3790 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
4bc85c13
WYG
3791
3792 return 0;
3793
e7392364 3794out_remove_sysfs:
46bc8d4b
SG
3795 destroy_workqueue(il->workqueue);
3796 il->workqueue = NULL;
e2ebc833 3797 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
e7392364 3798out_release_irq:
46bc8d4b 3799 free_irq(il->pci_dev->irq, il);
e7392364 3800out_disable_msi:
46bc8d4b
SG
3801 pci_disable_msi(il->pci_dev);
3802 il_free_geos(il);
3803 il_free_channel_map(il);
e7392364 3804out_unset_hw_params:
46bc8d4b 3805 il3945_unset_hw_params(il);
e7392364 3806out_eeprom_free:
46bc8d4b 3807 il_eeprom_free(il);
e7392364 3808out_iounmap:
a5f16137 3809 iounmap(il->hw_base);
e7392364 3810out_pci_release_regions:
4bc85c13 3811 pci_release_regions(pdev);
e7392364 3812out_pci_disable_device:
4bc85c13 3813 pci_disable_device(pdev);
e7392364 3814out_ieee80211_free_hw:
46bc8d4b 3815 ieee80211_free_hw(il->hw);
e7392364 3816out:
4bc85c13
WYG
3817 return err;
3818}
3819
a027cb88 3820static void
e7392364 3821il3945_pci_remove(struct pci_dev *pdev)
4bc85c13 3822{
46bc8d4b 3823 struct il_priv *il = pci_get_drvdata(pdev);
4bc85c13
WYG
3824 unsigned long flags;
3825
46bc8d4b 3826 if (!il)
4bc85c13
WYG
3827 return;
3828
58de00a4 3829 D_INFO("*** UNLOAD DRIVER ***\n");
4bc85c13 3830
46bc8d4b 3831 il_dbgfs_unregister(il);
4bc85c13 3832
a6766ccd 3833 set_bit(S_EXIT_PENDING, &il->status);
4bc85c13 3834
46bc8d4b 3835 il_leds_exit(il);
4bc85c13 3836
46bc8d4b
SG
3837 if (il->mac80211_registered) {
3838 ieee80211_unregister_hw(il->hw);
3839 il->mac80211_registered = 0;
4bc85c13 3840 } else {
46bc8d4b 3841 il3945_down(il);
4bc85c13
WYG
3842 }
3843
3844 /*
3845 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG
3846 * This may be redundant with il_down(), but there are paths to
3847 * run il_down() without calling apm_ops.stop(), and there are
3848 * paths to avoid running il_down() at all before leaving driver.
4bc85c13
WYG
3849 * This (inexpensive) call *makes sure* device is reset.
3850 */
46bc8d4b 3851 il_apm_stop(il);
4bc85c13
WYG
3852
3853 /* make sure we flush any pending irq or
3854 * tasklet for the driver
3855 */
46bc8d4b
SG
3856 spin_lock_irqsave(&il->lock, flags);
3857 il_disable_interrupts(il);
3858 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3859
46bc8d4b 3860 il3945_synchronize_irq(il);
4bc85c13 3861
e2ebc833 3862 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3863
46bc8d4b 3864 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
4bc85c13 3865
46bc8d4b 3866 il3945_dealloc_ucode_pci(il);
4bc85c13 3867
46bc8d4b
SG
3868 if (il->rxq.bd)
3869 il3945_rx_queue_free(il, &il->rxq);
3870 il3945_hw_txq_ctx_free(il);
4bc85c13 3871
46bc8d4b 3872 il3945_unset_hw_params(il);
4bc85c13
WYG
3873
3874 /*netif_stop_queue(dev); */
46bc8d4b 3875 flush_workqueue(il->workqueue);
4bc85c13 3876
e2ebc833 3877 /* ieee80211_unregister_hw calls il3945_mac_stop, which flushes
46bc8d4b 3878 * il->workqueue... so we can't take down the workqueue
4bc85c13 3879 * until now... */
46bc8d4b
SG
3880 destroy_workqueue(il->workqueue);
3881 il->workqueue = NULL;
4bc85c13 3882
46bc8d4b 3883 free_irq(pdev->irq, il);
4bc85c13
WYG
3884 pci_disable_msi(pdev);
3885
a5f16137 3886 iounmap(il->hw_base);
4bc85c13
WYG
3887 pci_release_regions(pdev);
3888 pci_disable_device(pdev);
4bc85c13 3889
46bc8d4b
SG
3890 il_free_channel_map(il);
3891 il_free_geos(il);
3892 kfree(il->scan_cmd);
3893 if (il->beacon_skb)
3894 dev_kfree_skb(il->beacon_skb);
4bc85c13 3895
46bc8d4b 3896 ieee80211_free_hw(il->hw);
4bc85c13
WYG
3897}
3898
4bc85c13
WYG
3899/*****************************************************************************
3900 *
3901 * driver and module entry point
3902 *
3903 *****************************************************************************/
3904
e2ebc833 3905static struct pci_driver il3945_driver = {
4bc85c13 3906 .name = DRV_NAME,
e2ebc833
SG
3907 .id_table = il3945_hw_card_ids,
3908 .probe = il3945_pci_probe,
a027cb88 3909 .remove = il3945_pci_remove,
e2ebc833 3910 .driver.pm = IL_LEGACY_PM_OPS,
4bc85c13
WYG
3911};
3912
e7392364
SG
3913static int __init
3914il3945_init(void)
4bc85c13
WYG
3915{
3916
3917 int ret;
3918 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3919 pr_info(DRV_COPYRIGHT "\n");
3920
e2ebc833 3921 ret = il3945_rate_control_register();
4bc85c13
WYG
3922 if (ret) {
3923 pr_err("Unable to register rate control algorithm: %d\n", ret);
3924 return ret;
3925 }
3926
e2ebc833 3927 ret = pci_register_driver(&il3945_driver);
4bc85c13
WYG
3928 if (ret) {
3929 pr_err("Unable to initialize PCI module\n");
3930 goto error_register;
3931 }
3932
3933 return ret;
3934
3935error_register:
e2ebc833 3936 il3945_rate_control_unregister();
4bc85c13
WYG
3937 return ret;
3938}
3939
e7392364
SG
3940static void __exit
3941il3945_exit(void)
4bc85c13 3942{
e2ebc833
SG
3943 pci_unregister_driver(&il3945_driver);
3944 il3945_rate_control_unregister();
4bc85c13
WYG
3945}
3946
d3175167 3947MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
4bc85c13 3948
e2ebc833 3949module_param_named(antenna, il3945_mod_params.antenna, int, S_IRUGO);
4bc85c13 3950MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
e2ebc833 3951module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, S_IRUGO);
e7392364
SG
3952MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3953module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3954 S_IRUGO);
0263aa45 3955MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
d3175167 3956#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 3957module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
4bc85c13
WYG
3958MODULE_PARM_DESC(debug, "debug output mask");
3959#endif
e2ebc833 3960module_param_named(fw_restart, il3945_mod_params.restart_fw, int, S_IRUGO);
be663ab6 3961MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4bc85c13 3962
e2ebc833
SG
3963module_exit(il3945_exit);
3964module_init(il3945_init);
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