Merge branch 'late/fixes' into fixes
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 3945-mac.c
CommitLineData
4bc85c13
WYG
1/******************************************************************************
2 *
be663ab6 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4bc85c13
WYG
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
4bc85c13
WYG
43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/ieee80211_radiotap.h>
48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
52#define DRV_NAME "iwl3945"
53
d4459a99 54#include "commands.h"
98613be0 55#include "common.h"
e94a4099 56#include "3945.h"
4bc85c13 57#include "iwl-spectrum.h"
4bc85c13
WYG
58
59/*
60 * module name, copyright, version, etc.
61 */
62
63#define DRV_DESCRIPTION \
64"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
65
d3175167 66#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
67#define VD "d"
68#else
69#define VD
70#endif
71
72/*
73 * add "s" to indicate spectrum measurement included.
74 * we add it here to be consistent with previous releases in which
75 * this was configurable.
76 */
77#define DRV_VERSION IWLWIFI_VERSION VD "s"
be663ab6 78#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
4bc85c13
WYG
79#define DRV_AUTHOR "<ilw@linux.intel.com>"
80
81MODULE_DESCRIPTION(DRV_DESCRIPTION);
82MODULE_VERSION(DRV_VERSION);
83MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
84MODULE_LICENSE("GPL");
85
86 /* module parameters */
e2ebc833 87struct il_mod_params il3945_mod_params = {
4bc85c13
WYG
88 .sw_crypto = 1,
89 .restart_fw = 1,
0263aa45 90 .disable_hw_scan = 1,
4bc85c13
WYG
91 /* the rest are 0 by default */
92};
93
94/**
e2ebc833 95 * il3945_get_antenna_flags - Get antenna flags for RXON command
46bc8d4b 96 * @il: eeprom and antenna fields are used to determine antenna flags
4bc85c13 97 *
46bc8d4b 98 * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
e2ebc833 99 * il3945_mod_params.antenna specifies the antenna diversity mode:
4bc85c13 100 *
e2ebc833
SG
101 * IL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
102 * IL_ANTENNA_MAIN - Force MAIN antenna
103 * IL_ANTENNA_AUX - Force AUX antenna
4bc85c13 104 */
e7392364
SG
105__le32
106il3945_get_antenna_flags(const struct il_priv *il)
4bc85c13 107{
46bc8d4b 108 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 109
e2ebc833
SG
110 switch (il3945_mod_params.antenna) {
111 case IL_ANTENNA_DIVERSITY:
4bc85c13
WYG
112 return 0;
113
e2ebc833 114 case IL_ANTENNA_MAIN:
4bc85c13
WYG
115 if (eeprom->antenna_switch_type)
116 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
118
e2ebc833 119 case IL_ANTENNA_AUX:
4bc85c13
WYG
120 if (eeprom->antenna_switch_type)
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
123 }
124
125 /* bad antenna selector value */
9406f797 126 IL_ERR("Bad antenna selector value (0x%x)\n",
e7392364 127 il3945_mod_params.antenna);
4bc85c13
WYG
128
129 return 0; /* "diversity" is default if error */
130}
131
e7392364
SG
132static int
133il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
134 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
135{
136 unsigned long flags;
137 __le16 key_flags = 0;
138 int ret;
139
140 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
141 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
142
b16db50a 143 if (sta_id == il->hw_params.bcast_id)
4bc85c13
WYG
144 key_flags |= STA_KEY_MULTICAST_MSK;
145
146 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
147 keyconf->hw_key_idx = keyconf->keyidx;
148 key_flags &= ~STA_KEY_FLG_INVALID;
149
46bc8d4b
SG
150 spin_lock_irqsave(&il->sta_lock, flags);
151 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
152 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
e7392364 153 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
4bc85c13 154
e7392364 155 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
4bc85c13 156
e7392364
SG
157 if ((il->stations[sta_id].sta.key.
158 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
46bc8d4b 159 il->stations[sta_id].sta.key.key_offset =
e7392364 160 il_get_free_ucode_key_idx(il);
4bc85c13 161 /* else, we are overriding an existing key => no need to allocated room
e7392364 162 * in uCode. */
4bc85c13 163
46bc8d4b 164 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 165 "no space for a new key");
4bc85c13 166
46bc8d4b
SG
167 il->stations[sta_id].sta.key.key_flags = key_flags;
168 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
169 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4bc85c13 170
58de00a4 171 D_INFO("hwcrypto: modify ucode station key info\n");
4bc85c13 172
e7392364 173 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
4bc85c13 174
46bc8d4b 175 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
176
177 return ret;
178}
179
e7392364
SG
180static int
181il3945_set_tkip_dynamic_key_info(struct il_priv *il,
182 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
183{
184 return -EOPNOTSUPP;
185}
186
e7392364
SG
187static int
188il3945_set_wep_dynamic_key_info(struct il_priv *il,
189 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
190{
191 return -EOPNOTSUPP;
192}
193
e7392364
SG
194static int
195il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
4bc85c13
WYG
196{
197 unsigned long flags;
e2ebc833 198 struct il_addsta_cmd sta_cmd;
4bc85c13 199
46bc8d4b
SG
200 spin_lock_irqsave(&il->sta_lock, flags);
201 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
e7392364 202 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
46bc8d4b
SG
203 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
204 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
205 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364
SG
206 memcpy(&sta_cmd, &il->stations[sta_id].sta,
207 sizeof(struct il_addsta_cmd));
46bc8d4b 208 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13 209
58de00a4 210 D_INFO("hwcrypto: clear ucode station key info\n");
46bc8d4b 211 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
4bc85c13
WYG
212}
213
e7392364
SG
214static int
215il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
216 u8 sta_id)
4bc85c13
WYG
217{
218 int ret = 0;
219
220 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
221
222 switch (keyconf->cipher) {
223 case WLAN_CIPHER_SUITE_CCMP:
46bc8d4b 224 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
WYG
225 break;
226 case WLAN_CIPHER_SUITE_TKIP:
46bc8d4b 227 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
WYG
228 break;
229 case WLAN_CIPHER_SUITE_WEP40:
230 case WLAN_CIPHER_SUITE_WEP104:
46bc8d4b 231 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
WYG
232 break;
233 default:
e7392364 234 IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
4bc85c13
WYG
235 ret = -EINVAL;
236 }
237
58de00a4 238 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
e7392364 239 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
4bc85c13
WYG
240
241 return ret;
242}
243
e7392364
SG
244static int
245il3945_remove_static_key(struct il_priv *il)
4bc85c13
WYG
246{
247 int ret = -EOPNOTSUPP;
248
249 return ret;
250}
251
e7392364
SG
252static int
253il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
4bc85c13
WYG
254{
255 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
256 key->cipher == WLAN_CIPHER_SUITE_WEP104)
257 return -EOPNOTSUPP;
258
9406f797 259 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
4bc85c13
WYG
260 return -EINVAL;
261}
262
e7392364
SG
263static void
264il3945_clear_free_frames(struct il_priv *il)
4bc85c13
WYG
265{
266 struct list_head *element;
267
e7392364 268 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
4bc85c13 269
46bc8d4b
SG
270 while (!list_empty(&il->free_frames)) {
271 element = il->free_frames.next;
4bc85c13 272 list_del(element);
e2ebc833 273 kfree(list_entry(element, struct il3945_frame, list));
46bc8d4b 274 il->frames_count--;
4bc85c13
WYG
275 }
276
46bc8d4b 277 if (il->frames_count) {
9406f797 278 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 279 il->frames_count);
46bc8d4b 280 il->frames_count = 0;
4bc85c13
WYG
281 }
282}
283
e7392364
SG
284static struct il3945_frame *
285il3945_get_free_frame(struct il_priv *il)
4bc85c13 286{
e2ebc833 287 struct il3945_frame *frame;
4bc85c13 288 struct list_head *element;
46bc8d4b 289 if (list_empty(&il->free_frames)) {
4bc85c13
WYG
290 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
291 if (!frame) {
9406f797 292 IL_ERR("Could not allocate frame!\n");
4bc85c13
WYG
293 return NULL;
294 }
295
46bc8d4b 296 il->frames_count++;
4bc85c13
WYG
297 return frame;
298 }
299
46bc8d4b 300 element = il->free_frames.next;
4bc85c13 301 list_del(element);
e2ebc833 302 return list_entry(element, struct il3945_frame, list);
4bc85c13
WYG
303}
304
e7392364
SG
305static void
306il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
4bc85c13
WYG
307{
308 memset(frame, 0, sizeof(*frame));
46bc8d4b 309 list_add(&frame->list, &il->free_frames);
4bc85c13
WYG
310}
311
e7392364
SG
312unsigned int
313il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
314 int left)
4bc85c13
WYG
315{
316
7c2cde2e 317 if (!il_is_associated(il) || !il->beacon_skb)
4bc85c13
WYG
318 return 0;
319
46bc8d4b 320 if (il->beacon_skb->len > left)
4bc85c13
WYG
321 return 0;
322
46bc8d4b 323 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
4bc85c13 324
46bc8d4b 325 return il->beacon_skb->len;
4bc85c13
WYG
326}
327
e7392364
SG
328static int
329il3945_send_beacon_cmd(struct il_priv *il)
4bc85c13 330{
e2ebc833 331 struct il3945_frame *frame;
4bc85c13
WYG
332 unsigned int frame_size;
333 int rc;
334 u8 rate;
335
46bc8d4b 336 frame = il3945_get_free_frame(il);
4bc85c13
WYG
337
338 if (!frame) {
9406f797 339 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 340 "command.\n");
4bc85c13
WYG
341 return -ENOMEM;
342 }
343
83007196 344 rate = il_get_lowest_plcp(il);
4bc85c13 345
46bc8d4b 346 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
4bc85c13 347
e7392364 348 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
4bc85c13 349
46bc8d4b 350 il3945_free_frame(il, frame);
4bc85c13
WYG
351
352 return rc;
353}
354
e7392364
SG
355static void
356il3945_unset_hw_params(struct il_priv *il)
4bc85c13 357{
46bc8d4b
SG
358 if (il->_3945.shared_virt)
359 dma_free_coherent(&il->pci_dev->dev,
e2ebc833 360 sizeof(struct il3945_shared),
e7392364 361 il->_3945.shared_virt, il->_3945.shared_phys);
4bc85c13
WYG
362}
363
e7392364
SG
364static void
365il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
366 struct il_device_cmd *cmd,
367 struct sk_buff *skb_frag, int sta_id)
4bc85c13 368{
e2ebc833 369 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
46bc8d4b 370 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
4bc85c13
WYG
371
372 tx_cmd->sec_ctl = 0;
373
374 switch (keyinfo->cipher) {
375 case WLAN_CIPHER_SUITE_CCMP:
376 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
377 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
58de00a4 378 D_TX("tx_cmd with AES hwcrypto\n");
4bc85c13
WYG
379 break;
380
381 case WLAN_CIPHER_SUITE_TKIP:
382 break;
383
384 case WLAN_CIPHER_SUITE_WEP104:
385 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
386 /* fall through */
387 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG
388 tx_cmd->sec_ctl |=
389 TX_CMD_SEC_WEP | (info->control.hw_key->
390 hw_key_idx & TX_CMD_SEC_MSK) <<
391 TX_CMD_SEC_SHIFT;
4bc85c13
WYG
392
393 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
394
e7392364
SG
395 D_TX("Configuring packet for WEP encryption " "with key %d\n",
396 info->control.hw_key->hw_key_idx);
4bc85c13
WYG
397 break;
398
399 default:
9406f797 400 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
4bc85c13
WYG
401 break;
402 }
403}
404
405/*
4d69c752 406 * handle build C_TX command notification.
4bc85c13 407 */
e7392364
SG
408static void
409il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
410 struct ieee80211_tx_info *info,
411 struct ieee80211_hdr *hdr, u8 std_id)
4bc85c13 412{
e2ebc833 413 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
4bc85c13
WYG
414 __le32 tx_flags = tx_cmd->tx_flags;
415 __le16 fc = hdr->frame_control;
416
417 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
418 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
419 tx_flags |= TX_CMD_FLG_ACK_MSK;
420 if (ieee80211_is_mgmt(fc))
421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
422 if (ieee80211_is_probe_resp(fc) &&
423 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
424 tx_flags |= TX_CMD_FLG_TSF_MSK;
425 } else {
426 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
427 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
428 }
429
430 tx_cmd->sta_id = std_id;
431 if (ieee80211_has_morefrags(fc))
432 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
433
434 if (ieee80211_is_data_qos(fc)) {
435 u8 *qc = ieee80211_get_qos_ctl(hdr);
436 tx_cmd->tid_tspec = qc[0] & 0xf;
437 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
438 } else {
439 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
440 }
441
46bc8d4b 442 il_tx_cmd_protection(il, info, fc, &tx_flags);
4bc85c13
WYG
443
444 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
445 if (ieee80211_is_mgmt(fc)) {
446 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
447 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
448 else
449 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
450 } else {
451 tx_cmd->timeout.pm_frame_timeout = 0;
452 }
453
454 tx_cmd->driver_txop = 0;
455 tx_cmd->tx_flags = tx_flags;
456 tx_cmd->next_frame_len = 0;
457}
458
459/*
4d69c752 460 * start C_TX command process
4bc85c13 461 */
e7392364 462static int
36323f81
TH
463il3945_tx_skb(struct il_priv *il,
464 struct ieee80211_sta *sta,
465 struct sk_buff *skb)
4bc85c13
WYG
466{
467 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e2ebc833
SG
469 struct il3945_tx_cmd *tx_cmd;
470 struct il_tx_queue *txq = NULL;
471 struct il_queue *q = NULL;
472 struct il_device_cmd *out_cmd;
473 struct il_cmd_meta *out_meta;
4bc85c13
WYG
474 dma_addr_t phys_addr;
475 dma_addr_t txcmd_phys;
476 int txq_id = skb_get_queue_mapping(skb);
477 u16 len, idx, hdr_len;
478 u8 id;
479 u8 unicast;
480 u8 sta_id;
481 u8 tid = 0;
482 __le16 fc;
483 u8 wait_write_ptr = 0;
484 unsigned long flags;
485
46bc8d4b
SG
486 spin_lock_irqsave(&il->lock, flags);
487 if (il_is_rfkill(il)) {
58de00a4 488 D_DROP("Dropping - RF KILL\n");
4bc85c13
WYG
489 goto drop_unlock;
490 }
491
e7392364
SG
492 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
493 IL_INVALID_RATE) {
9406f797 494 IL_ERR("ERROR: No TX rate available.\n");
4bc85c13
WYG
495 goto drop_unlock;
496 }
497
498 unicast = !is_multicast_ether_addr(hdr->addr1);
499 id = 0;
500
501 fc = hdr->frame_control;
502
d3175167 503#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13 504 if (ieee80211_is_auth(fc))
58de00a4 505 D_TX("Sending AUTH frame\n");
4bc85c13 506 else if (ieee80211_is_assoc_req(fc))
58de00a4 507 D_TX("Sending ASSOC frame\n");
4bc85c13 508 else if (ieee80211_is_reassoc_req(fc))
58de00a4 509 D_TX("Sending REASSOC frame\n");
4bc85c13
WYG
510#endif
511
46bc8d4b 512 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
513
514 hdr_len = ieee80211_hdrlen(fc);
515
0c2c8852 516 /* Find idx into station table for destination station */
36323f81 517 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 518 if (sta_id == IL_INVALID_STATION) {
e7392364 519 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
4bc85c13
WYG
520 goto drop;
521 }
522
58de00a4 523 D_RATE("station Id %d\n", sta_id);
4bc85c13
WYG
524
525 if (ieee80211_is_data_qos(fc)) {
526 u8 *qc = ieee80211_get_qos_ctl(hdr);
527 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
528 if (unlikely(tid >= MAX_TID_COUNT))
529 goto drop;
530 }
531
532 /* Descriptor for chosen Tx queue */
46bc8d4b 533 txq = &il->txq[txq_id];
4bc85c13
WYG
534 q = &txq->q;
535
e2ebc833 536 if ((il_queue_space(q) < q->high_mark))
4bc85c13
WYG
537 goto drop;
538
46bc8d4b 539 spin_lock_irqsave(&il->lock, flags);
4bc85c13 540
0c2c8852 541 idx = il_get_cmd_idx(q, q->write_ptr, 0);
4bc85c13 542
00ea99e1 543 txq->skbs[q->write_ptr] = skb;
4bc85c13
WYG
544
545 /* Init first empty entry in queue's array of Tx/cmd buffers */
546 out_cmd = txq->cmd[idx];
547 out_meta = &txq->meta[idx];
e2ebc833 548 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
4bc85c13
WYG
549 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
550 memset(tx_cmd, 0, sizeof(*tx_cmd));
551
552 /*
553 * Set up the Tx-command (not MAC!) header.
0c2c8852 554 * Store the chosen Tx queue and TFD idx within the sequence field;
4bc85c13
WYG
555 * after Tx, uCode's Tx response will return this value so driver can
556 * locate the frame within the tx queue and do post-tx processing.
557 */
4d69c752 558 out_cmd->hdr.cmd = C_TX;
e7392364
SG
559 out_cmd->hdr.sequence =
560 cpu_to_le16((u16)
561 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
4bc85c13
WYG
562
563 /* Copy MAC header from skb into command buffer */
564 memcpy(tx_cmd->hdr, hdr, hdr_len);
565
4bc85c13 566 if (info->control.hw_key)
46bc8d4b 567 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
4bc85c13
WYG
568
569 /* TODO need this for burst mode later on */
46bc8d4b 570 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
4bc85c13 571
81fb4613 572 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
4bc85c13
WYG
573
574 /* Total # bytes to be transmitted */
e7392364 575 len = (u16) skb->len;
4bc85c13
WYG
576 tx_cmd->len = cpu_to_le16(len);
577
46bc8d4b 578 il_update_stats(il, true, fc, len);
4bc85c13
WYG
579 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
580 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
581
582 if (!ieee80211_has_morefrags(hdr->frame_control)) {
583 txq->need_update = 1;
584 } else {
585 wait_write_ptr = 1;
586 txq->need_update = 0;
587 }
588
e7392364 589 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
58de00a4 590 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
46bc8d4b 591 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
e7392364
SG
592 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
593 ieee80211_hdrlen(fc));
4bc85c13
WYG
594
595 /*
596 * Use the first empty entry in this queue's command buffer array
597 * to contain the Tx command and MAC header concatenated together
598 * (payload data will be in another buffer).
599 * Size of this varies, due to varying MAC header length.
600 * If end is not dword aligned, we'll have 2 extra bytes at the end
601 * of the MAC header (device reads on dword boundaries).
602 * We'll tell device about this padding later.
603 */
e7392364
SG
604 len =
605 sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
606 hdr_len;
4bc85c13
WYG
607 len = (len + 3) & ~3;
608
609 /* Physical address of this Tx command's header (not MAC header!),
610 * within command buffer array. */
e7392364
SG
611 txcmd_phys =
612 pci_map_single(il->pci_dev, &out_cmd->hdr, len, PCI_DMA_TODEVICE);
4bc85c13
WYG
613 /* we do not map meta data ... so we can safely access address to
614 * provide to unmap command*/
615 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
616 dma_unmap_len_set(out_meta, len, len);
617
618 /* Add buffer containing Tx command and MAC(!) header to TFD's
619 * first entry */
1600b875 620 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, len, 1, 0);
4bc85c13
WYG
621
622 /* Set up TFD's 2nd entry to point directly to remainder of skb,
623 * if any (802.11 null frames have no payload). */
624 len = skb->len - hdr_len;
625 if (len) {
e7392364
SG
626 phys_addr =
627 pci_map_single(il->pci_dev, skb->data + hdr_len, len,
628 PCI_DMA_TODEVICE);
1600b875
SG
629 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, len, 0,
630 U32_PAD(len));
4bc85c13
WYG
631 }
632
0c2c8852 633 /* Tell device the write idx *just past* this latest filled TFD */
e2ebc833 634 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
46bc8d4b
SG
635 il_txq_update_write_ptr(il, txq);
636 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 637
e7392364 638 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
4bc85c13 639 if (wait_write_ptr) {
46bc8d4b 640 spin_lock_irqsave(&il->lock, flags);
4bc85c13 641 txq->need_update = 1;
46bc8d4b
SG
642 il_txq_update_write_ptr(il, txq);
643 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
644 }
645
46bc8d4b 646 il_stop_queue(il, txq);
4bc85c13
WYG
647 }
648
649 return 0;
650
651drop_unlock:
46bc8d4b 652 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
653drop:
654 return -1;
655}
656
e7392364
SG
657static int
658il3945_get_measurement(struct il_priv *il,
659 struct ieee80211_measurement_params *params, u8 type)
4bc85c13 660{
e2ebc833 661 struct il_spectrum_cmd spectrum;
dcae1c64 662 struct il_rx_pkt *pkt;
e2ebc833 663 struct il_host_cmd cmd = {
4d69c752 664 .id = C_SPECTRUM_MEASUREMENT,
4bc85c13
WYG
665 .data = (void *)&spectrum,
666 .flags = CMD_WANT_SKB,
667 };
668 u32 add_time = le64_to_cpu(params->start_time);
669 int rc;
670 int spectrum_resp_status;
671 int duration = le16_to_cpu(params->duration);
4bc85c13 672
7c2cde2e 673 if (il_is_associated(il))
e7392364
SG
674 add_time =
675 il_usecs_to_beacons(il,
676 le64_to_cpu(params->start_time) -
677 il->_3945.last_tsf,
c8b03958 678 le16_to_cpu(il->timing.beacon_interval));
4bc85c13
WYG
679
680 memset(&spectrum, 0, sizeof(spectrum));
681
682 spectrum.channel_count = cpu_to_le16(1);
683 spectrum.flags =
684 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
685 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
686 cmd.len = sizeof(spectrum);
687 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
688
7c2cde2e 689 if (il_is_associated(il))
4bc85c13 690 spectrum.start_time =
e7392364 691 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
c8b03958 692 le16_to_cpu(il->timing.beacon_interval));
4bc85c13
WYG
693 else
694 spectrum.start_time = 0;
695
696 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
697 spectrum.channels[0].channel = params->channel;
698 spectrum.channels[0].type = type;
c8b03958 699 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
e7392364
SG
700 spectrum.flags |=
701 RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
702 RXON_FLG_TGG_PROTECT_MSK;
4bc85c13 703
46bc8d4b 704 rc = il_send_cmd_sync(il, &cmd);
4bc85c13
WYG
705 if (rc)
706 return rc;
707
dcae1c64 708 pkt = (struct il_rx_pkt *)cmd.reply_page;
e2ebc833 709 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
4d69c752 710 IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
4bc85c13
WYG
711 rc = -EIO;
712 }
713
714 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
715 switch (spectrum_resp_status) {
716 case 0: /* Command will be handled */
717 if (pkt->u.spectrum.id != 0xff) {
58de00a4 718 D_INFO("Replaced existing measurement: %d\n",
e7392364 719 pkt->u.spectrum.id);
46bc8d4b 720 il->measurement_status &= ~MEASUREMENT_READY;
4bc85c13 721 }
46bc8d4b 722 il->measurement_status |= MEASUREMENT_ACTIVE;
4bc85c13
WYG
723 rc = 0;
724 break;
725
726 case 1: /* Command will not be handled */
727 rc = -EAGAIN;
728 break;
729 }
730
46bc8d4b 731 il_free_pages(il, cmd.reply_page);
4bc85c13
WYG
732
733 return rc;
734}
735
e7392364
SG
736static void
737il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 738{
dcae1c64 739 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 740 struct il_alive_resp *palive;
4bc85c13
WYG
741 struct delayed_work *pwork;
742
743 palive = &pkt->u.alive_frame;
744
e7392364
SG
745 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
746 palive->is_valid, palive->ver_type, palive->ver_subtype);
4bc85c13
WYG
747
748 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 749 D_INFO("Initialization Alive received.\n");
46bc8d4b 750 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 751 sizeof(struct il_alive_resp));
46bc8d4b 752 pwork = &il->init_alive_start;
4bc85c13 753 } else {
58de00a4 754 D_INFO("Runtime Alive received.\n");
46bc8d4b 755 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 756 sizeof(struct il_alive_resp));
46bc8d4b
SG
757 pwork = &il->alive_start;
758 il3945_disable_events(il);
4bc85c13
WYG
759 }
760
761 /* We delay the ALIVE response by 5ms to
762 * give the HW RF Kill time to activate... */
763 if (palive->is_valid == UCODE_VALID_OK)
e7392364 764 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
4bc85c13 765 else
9406f797 766 IL_WARN("uCode did not respond OK.\n");
4bc85c13
WYG
767}
768
e7392364
SG
769static void
770il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 771{
d3175167 772#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 773 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13
WYG
774#endif
775
4d69c752 776 D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
4bc85c13
WYG
777}
778
e7392364
SG
779static void
780il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 781{
dcae1c64 782 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 783 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
d3175167 784#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
785 u8 rate = beacon->beacon_notify_hdr.rate;
786
e7392364
SG
787 D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
788 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
789 beacon->beacon_notify_hdr.failure_frame,
790 le32_to_cpu(beacon->ibss_mgr_status),
791 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
4bc85c13
WYG
792#endif
793
46bc8d4b 794 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
4bc85c13 795
4bc85c13
WYG
796}
797
798/* Handle notification from uCode that card's power state is changing
799 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG
800static void
801il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 802{
dcae1c64 803 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13 804 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 805 unsigned long status = il->status;
4bc85c13 806
9406f797 807 IL_WARN("Card state received: HW:%s SW:%s\n",
e7392364
SG
808 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
809 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
4bc85c13 810
e7392364 811 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4bc85c13
WYG
812
813 if (flags & HW_CARD_DISABLED)
bc269a8e 814 set_bit(S_RFKILL, &il->status);
4bc85c13 815 else
bc269a8e 816 clear_bit(S_RFKILL, &il->status);
4bc85c13 817
46bc8d4b 818 il_scan_cancel(il);
4bc85c13 819
bc269a8e
SG
820 if ((test_bit(S_RFKILL, &status) !=
821 test_bit(S_RFKILL, &il->status)))
46bc8d4b 822 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 823 test_bit(S_RFKILL, &il->status));
4bc85c13 824 else
46bc8d4b 825 wake_up(&il->wait_command_queue);
4bc85c13
WYG
826}
827
828/**
d0c72347 829 * il3945_setup_handlers - Initialize Rx handler callbacks
4bc85c13
WYG
830 *
831 * Setup the RX handlers for each of the reply types sent from the uCode
832 * to the host.
833 *
834 * This function chains into the hardware specific files for them to setup
835 * any hardware specific handlers as well.
836 */
e7392364
SG
837static void
838il3945_setup_handlers(struct il_priv *il)
4bc85c13 839{
6e9848b4
SG
840 il->handlers[N_ALIVE] = il3945_hdl_alive;
841 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
842 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 843 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 844 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 845 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 846 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 847 il->handlers[N_BEACON] = il3945_hdl_beacon;
4bc85c13
WYG
848
849 /*
850 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG
851 * stats request from the host as well as for the periodic
852 * stats notifications (after received beacons) from the uCode.
4bc85c13 853 */
d2dfb33e
SG
854 il->handlers[C_STATS] = il3945_hdl_c_stats;
855 il->handlers[N_STATS] = il3945_hdl_stats;
4bc85c13 856
46bc8d4b 857 il_setup_rx_scan_handlers(il);
d2dfb33e 858 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
4bc85c13
WYG
859
860 /* Set up hardware specific Rx handlers */
d0c72347 861 il3945_hw_handler_setup(il);
4bc85c13
WYG
862}
863
864/************************** RX-FUNCTIONS ****************************/
865/*
866 * Rx theory of operation
867 *
868 * The host allocates 32 DMA target addresses and passes the host address
3b98c7f4 869 * to the firmware at register IL_RFDS_TBL_LOWER + N * RFD_SIZE where N is
4bc85c13
WYG
870 * 0 to 31
871 *
872 * Rx Queue Indexes
0c2c8852 873 * The host/firmware share two idx registers for managing the Rx buffers.
4bc85c13 874 *
0c2c8852 875 * The READ idx maps to the first position that the firmware may be writing
4bc85c13
WYG
876 * to -- the driver can read up to (but not including) this position and get
877 * good data.
0c2c8852 878 * The READ idx is managed by the firmware once the card is enabled.
4bc85c13 879 *
0c2c8852 880 * The WRITE idx maps to the last position the driver has read from -- the
4bc85c13
WYG
881 * position preceding WRITE is the last slot the firmware can place a packet.
882 *
883 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
884 * WRITE = READ.
885 *
886 * During initialization, the host sets up the READ queue position to the first
2d09b062 887 * IDX position, and WRITE to the last (READ - 1 wrapped)
4bc85c13 888 *
0c2c8852
SG
889 * When the firmware places a packet in a buffer, it will advance the READ idx
890 * and fire the RX interrupt. The driver can then query the READ idx and
891 * process as many packets as possible, moving the WRITE idx forward as it
4bc85c13
WYG
892 * resets the Rx queue buffers with new memory.
893 *
894 * The management in the driver is as follows:
895 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
896 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
897 * to replenish the iwl->rxq->rx_free.
e2ebc833 898 * + In il3945_rx_replenish (scheduled) if 'processed' != 'read' then the
2d09b062 899 * iwl->rxq is replenished and the READ IDX is updated (updating the
0c2c8852 900 * 'processed' and 'read' driver idxes as well)
4bc85c13 901 * + A received packet is processed and handed to the kernel network stack,
0c2c8852 902 * detached from the iwl->rxq. The driver 'processed' idx is updated.
4bc85c13
WYG
903 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
904 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2d09b062 905 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
4bc85c13
WYG
906 * were enough free buffers and RX_STALLED is set it is cleared.
907 *
908 *
909 * Driver sequence:
910 *
e2ebc833
SG
911 * il3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
912 * il3945_rx_queue_restock
913 * il3945_rx_queue_restock() Moves available buffers from rx_free into Rx
4bc85c13 914 * queue, updates firmware pointers, and updates
0c2c8852 915 * the WRITE idx. If insufficient rx_free buffers
e2ebc833 916 * are available, schedules il3945_rx_replenish
4bc85c13
WYG
917 *
918 * -- enable interrupts --
b73bb5f1 919 * ISR - il3945_rx() Detach il_rx_bufs from pool up to the
2d09b062 920 * READ IDX, detaching the SKB from the pool.
4bc85c13 921 * Moves the packet buffer from queue to rx_used.
e2ebc833 922 * Calls il3945_rx_queue_restock to refill any empty
4bc85c13
WYG
923 * slots.
924 * ...
925 *
926 */
927
928/**
e2ebc833 929 * il3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
4bc85c13 930 */
e7392364
SG
931static inline __le32
932il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
4bc85c13 933{
e7392364 934 return cpu_to_le32((u32) dma_addr);
4bc85c13
WYG
935}
936
937/**
e2ebc833 938 * il3945_rx_queue_restock - refill RX queue from pre-allocated pool
4bc85c13
WYG
939 *
940 * If there are slots in the RX queue that need to be restocked,
941 * and we have free pre-allocated buffers, fill the ranks as much
942 * as we can, pulling from rx_free.
943 *
0c2c8852 944 * This moves the 'write' idx forward to catch up with 'processed', and
4bc85c13
WYG
945 * also updates the memory address in the firmware to reference the new
946 * target buffer.
947 */
e7392364
SG
948static void
949il3945_rx_queue_restock(struct il_priv *il)
4bc85c13 950{
46bc8d4b 951 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 952 struct list_head *element;
b73bb5f1 953 struct il_rx_buf *rxb;
4bc85c13
WYG
954 unsigned long flags;
955 int write;
956
957 spin_lock_irqsave(&rxq->lock, flags);
958 write = rxq->write & ~0x7;
232913b5 959 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
4bc85c13
WYG
960 /* Get next free Rx buffer, remove from free list */
961 element = rxq->rx_free.next;
b73bb5f1 962 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13
WYG
963 list_del(element);
964
965 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG
966 rxq->bd[rxq->write] =
967 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
4bc85c13
WYG
968 rxq->queue[rxq->write] = rxb;
969 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
970 rxq->free_count--;
971 }
972 spin_unlock_irqrestore(&rxq->lock, flags);
973 /* If the pre-allocated buffer pool is dropping low, schedule to
974 * refill it */
975 if (rxq->free_count <= RX_LOW_WATERMARK)
46bc8d4b 976 queue_work(il->workqueue, &il->rx_replenish);
4bc85c13 977
4bc85c13
WYG
978 /* If we've added more space for the firmware to place data, tell it.
979 * Increment device's write pointer in multiples of 8. */
232913b5
SG
980 if (rxq->write_actual != (rxq->write & ~0x7) ||
981 abs(rxq->write - rxq->read) > 7) {
4bc85c13
WYG
982 spin_lock_irqsave(&rxq->lock, flags);
983 rxq->need_update = 1;
984 spin_unlock_irqrestore(&rxq->lock, flags);
46bc8d4b 985 il_rx_queue_update_write_ptr(il, rxq);
4bc85c13
WYG
986 }
987}
988
989/**
e2ebc833 990 * il3945_rx_replenish - Move all used packet from rx_used to rx_free
4bc85c13
WYG
991 *
992 * When moving to rx_free an SKB is allocated for the slot.
993 *
e2ebc833 994 * Also restock the Rx queue via il3945_rx_queue_restock.
4bc85c13
WYG
995 * This is called as a scheduled work item (except for during initialization)
996 */
e7392364
SG
997static void
998il3945_rx_allocate(struct il_priv *il, gfp_t priority)
4bc85c13 999{
46bc8d4b 1000 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 1001 struct list_head *element;
b73bb5f1 1002 struct il_rx_buf *rxb;
4bc85c13
WYG
1003 struct page *page;
1004 unsigned long flags;
1005 gfp_t gfp_mask = priority;
1006
1007 while (1) {
1008 spin_lock_irqsave(&rxq->lock, flags);
1009
1010 if (list_empty(&rxq->rx_used)) {
1011 spin_unlock_irqrestore(&rxq->lock, flags);
1012 return;
1013 }
1014 spin_unlock_irqrestore(&rxq->lock, flags);
1015
1016 if (rxq->free_count > RX_LOW_WATERMARK)
1017 gfp_mask |= __GFP_NOWARN;
1018
46bc8d4b 1019 if (il->hw_params.rx_page_order > 0)
4bc85c13
WYG
1020 gfp_mask |= __GFP_COMP;
1021
1022 /* Alloc a new receive buffer */
46bc8d4b 1023 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
4bc85c13
WYG
1024 if (!page) {
1025 if (net_ratelimit())
58de00a4 1026 D_INFO("Failed to allocate SKB buffer.\n");
232913b5 1027 if (rxq->free_count <= RX_LOW_WATERMARK &&
4bc85c13 1028 net_ratelimit())
1722f8e1
SG
1029 IL_ERR("Failed to allocate SKB buffer with %0x."
1030 "Only %u free buffers remaining.\n",
1031 priority, rxq->free_count);
4bc85c13
WYG
1032 /* We don't reschedule replenish work here -- we will
1033 * call the restock method and if it still needs
1034 * more buffers it will schedule replenish */
1035 break;
1036 }
1037
1038 spin_lock_irqsave(&rxq->lock, flags);
1039 if (list_empty(&rxq->rx_used)) {
1040 spin_unlock_irqrestore(&rxq->lock, flags);
46bc8d4b 1041 __free_pages(page, il->hw_params.rx_page_order);
4bc85c13
WYG
1042 return;
1043 }
1044 element = rxq->rx_used.next;
b73bb5f1 1045 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13
WYG
1046 list_del(element);
1047 spin_unlock_irqrestore(&rxq->lock, flags);
1048
1049 rxb->page = page;
1050 /* Get physical address of RB/SKB */
e7392364
SG
1051 rxb->page_dma =
1052 pci_map_page(il->pci_dev, page, 0,
1053 PAGE_SIZE << il->hw_params.rx_page_order,
1054 PCI_DMA_FROMDEVICE);
4bc85c13
WYG
1055
1056 spin_lock_irqsave(&rxq->lock, flags);
1057
1058 list_add_tail(&rxb->list, &rxq->rx_free);
1059 rxq->free_count++;
46bc8d4b 1060 il->alloc_rxb_page++;
4bc85c13
WYG
1061
1062 spin_unlock_irqrestore(&rxq->lock, flags);
1063 }
1064}
1065
e7392364
SG
1066void
1067il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1068{
1069 unsigned long flags;
1070 int i;
1071 spin_lock_irqsave(&rxq->lock, flags);
1072 INIT_LIST_HEAD(&rxq->rx_free);
1073 INIT_LIST_HEAD(&rxq->rx_used);
1074 /* Fill the rx_used queue with _all_ of the Rx buffers */
1075 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1076 /* In the reset function, these buffers may have been allocated
1077 * to an SKB, so we need to unmap and free potential storage */
1078 if (rxq->pool[i].page != NULL) {
46bc8d4b 1079 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG
1080 PAGE_SIZE << il->hw_params.rx_page_order,
1081 PCI_DMA_FROMDEVICE);
46bc8d4b 1082 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1083 rxq->pool[i].page = NULL;
1084 }
1085 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1086 }
1087
1088 /* Set us so that we have processed and used all buffers, but have
1089 * not restocked the Rx queue with fresh buffers */
1090 rxq->read = rxq->write = 0;
1091 rxq->write_actual = 0;
1092 rxq->free_count = 0;
1093 spin_unlock_irqrestore(&rxq->lock, flags);
1094}
1095
e7392364
SG
1096void
1097il3945_rx_replenish(void *data)
4bc85c13 1098{
46bc8d4b 1099 struct il_priv *il = data;
4bc85c13
WYG
1100 unsigned long flags;
1101
46bc8d4b 1102 il3945_rx_allocate(il, GFP_KERNEL);
4bc85c13 1103
46bc8d4b
SG
1104 spin_lock_irqsave(&il->lock, flags);
1105 il3945_rx_queue_restock(il);
1106 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1107}
1108
e7392364
SG
1109static void
1110il3945_rx_replenish_now(struct il_priv *il)
4bc85c13 1111{
46bc8d4b 1112 il3945_rx_allocate(il, GFP_ATOMIC);
4bc85c13 1113
46bc8d4b 1114 il3945_rx_queue_restock(il);
4bc85c13
WYG
1115}
1116
4bc85c13
WYG
1117/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1118 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1119 * This free routine walks the list of POOL entries and if SKB is set to
1120 * non NULL it is unmapped and freed
1121 */
e7392364
SG
1122static void
1123il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1124{
1125 int i;
1126 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1127 if (rxq->pool[i].page != NULL) {
46bc8d4b 1128 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG
1129 PAGE_SIZE << il->hw_params.rx_page_order,
1130 PCI_DMA_FROMDEVICE);
46bc8d4b 1131 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1132 rxq->pool[i].page = NULL;
1133 }
1134 }
1135
46bc8d4b 1136 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4bc85c13 1137 rxq->bd_dma);
46bc8d4b 1138 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
4bc85c13
WYG
1139 rxq->rb_stts, rxq->rb_stts_dma);
1140 rxq->bd = NULL;
e7392364 1141 rxq->rb_stts = NULL;
4bc85c13
WYG
1142}
1143
4bc85c13
WYG
1144/* Convert linear signal-to-noise ratio into dB */
1145static u8 ratio2dB[100] = {
1146/* 0 1 2 3 4 5 6 7 8 9 */
e7392364
SG
1147 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1148 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1149 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1150 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1151 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1152 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1153 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1154 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1155 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1156 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4bc85c13
WYG
1157};
1158
1159/* Calculates a relative dB value from a ratio of linear
1160 * (i.e. not dB) signal levels.
1161 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
e7392364
SG
1162int
1163il3945_calc_db_from_ratio(int sig_ratio)
4bc85c13
WYG
1164{
1165 /* 1000:1 or higher just report as 60 dB */
1166 if (sig_ratio >= 1000)
1167 return 60;
1168
1169 /* 100:1 or higher, divide by 10 and use table,
1170 * add 20 dB to make up for divide by 10 */
1171 if (sig_ratio >= 100)
e7392364 1172 return 20 + (int)ratio2dB[sig_ratio / 10];
4bc85c13
WYG
1173
1174 /* We shouldn't see this */
1175 if (sig_ratio < 1)
1176 return 0;
1177
1178 /* Use table for ratios 1:1 - 99:1 */
1179 return (int)ratio2dB[sig_ratio];
1180}
1181
1182/**
e2ebc833 1183 * il3945_rx_handle - Main entry function for receiving responses from uCode
4bc85c13 1184 *
d0c72347 1185 * Uses the il->handlers callback function array to invoke
4bc85c13
WYG
1186 * the appropriate handlers, including command responses,
1187 * frame-received notifications, and other notifications.
1188 */
e7392364
SG
1189static void
1190il3945_rx_handle(struct il_priv *il)
4bc85c13 1191{
b73bb5f1 1192 struct il_rx_buf *rxb;
dcae1c64 1193 struct il_rx_pkt *pkt;
46bc8d4b 1194 struct il_rx_queue *rxq = &il->rxq;
4bc85c13
WYG
1195 u32 r, i;
1196 int reclaim;
1197 unsigned long flags;
1198 u8 fill_rx = 0;
1199 u32 count = 8;
1200 int total_empty = 0;
1201
0c2c8852 1202 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
4bc85c13 1203 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 1204 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
4bc85c13
WYG
1205 i = rxq->read;
1206
1207 /* calculate total frames need to be restock after handling RX */
1208 total_empty = r - rxq->write_actual;
1209 if (total_empty < 0)
1210 total_empty += RX_QUEUE_SIZE;
1211
1212 if (total_empty > (RX_QUEUE_SIZE / 2))
1213 fill_rx = 1;
1214 /* Rx interrupt, but nothing sent from uCode */
1215 if (i == r)
58de00a4 1216 D_RX("r = %d, i = %d\n", r, i);
4bc85c13
WYG
1217
1218 while (i != r) {
1219 int len;
1220
1221 rxb = rxq->queue[i];
1222
1223 /* If an RXB doesn't have a Rx queue slot associated with it,
1224 * then a bug has been introduced in the queue refilling
1225 * routines -- catch it here */
1226 BUG_ON(rxb == NULL);
1227
1228 rxq->queue[i] = NULL;
1229
46bc8d4b
SG
1230 pci_unmap_page(il->pci_dev, rxb->page_dma,
1231 PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13
WYG
1232 PCI_DMA_FROMDEVICE);
1233 pkt = rxb_addr(rxb);
1234
e94a4099 1235 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 1236 len += sizeof(u32); /* account for status word */
4bc85c13
WYG
1237
1238 /* Reclaim a command buffer only if this packet is a response
1239 * to a (driver-originated) command.
1240 * If the packet (e.g. Rx frame) originated from uCode,
1241 * there is no command buffer to reclaim.
1242 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1243 * but apparently a few don't get set; catch them here. */
1244 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364 1245 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX;
4bc85c13
WYG
1246
1247 /* Based on type of command response or notification,
1248 * handle those that need handling via function in
d0c72347
SG
1249 * handlers table. See il3945_setup_handlers() */
1250 if (il->handlers[pkt->hdr.cmd]) {
58de00a4 1251 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
e7392364 1252 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG
1253 il->isr_stats.handlers[pkt->hdr.cmd]++;
1254 il->handlers[pkt->hdr.cmd] (il, rxb);
4bc85c13
WYG
1255 } else {
1256 /* No handling needed */
e7392364
SG
1257 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1258 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4bc85c13
WYG
1259 }
1260
1261 /*
1262 * XXX: After here, we should always check rxb->page
1263 * against NULL before touching it or its virtual
d0c72347 1264 * memory (pkt). Because some handler might have
4bc85c13
WYG
1265 * already taken or freed the pages.
1266 */
1267
1268 if (reclaim) {
1269 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 1270 * and fire off the (possibly) blocking il_send_cmd()
4bc85c13
WYG
1271 * as we reclaim the driver command queue */
1272 if (rxb->page)
46bc8d4b 1273 il_tx_cmd_complete(il, rxb);
4bc85c13 1274 else
9406f797 1275 IL_WARN("Claim null rxb?\n");
4bc85c13
WYG
1276 }
1277
1278 /* Reuse the page if possible. For notification packets and
1279 * SKBs that fail to Rx correctly, add them back into the
1280 * rx_free list for reuse later. */
1281 spin_lock_irqsave(&rxq->lock, flags);
1282 if (rxb->page != NULL) {
e7392364
SG
1283 rxb->page_dma =
1284 pci_map_page(il->pci_dev, rxb->page, 0,
1285 PAGE_SIZE << il->hw_params.
1286 rx_page_order, PCI_DMA_FROMDEVICE);
4bc85c13
WYG
1287 list_add_tail(&rxb->list, &rxq->rx_free);
1288 rxq->free_count++;
1289 } else
1290 list_add_tail(&rxb->list, &rxq->rx_used);
1291
1292 spin_unlock_irqrestore(&rxq->lock, flags);
1293
1294 i = (i + 1) & RX_QUEUE_MASK;
1295 /* If there are a lot of unused frames,
1296 * restock the Rx queue so ucode won't assert. */
1297 if (fill_rx) {
1298 count++;
1299 if (count >= 8) {
1300 rxq->read = i;
46bc8d4b 1301 il3945_rx_replenish_now(il);
4bc85c13
WYG
1302 count = 0;
1303 }
1304 }
1305 }
1306
1307 /* Backtrack one entry */
1308 rxq->read = i;
1309 if (fill_rx)
46bc8d4b 1310 il3945_rx_replenish_now(il);
4bc85c13 1311 else
46bc8d4b 1312 il3945_rx_queue_restock(il);
4bc85c13
WYG
1313}
1314
1315/* call this function to flush any scheduled tasklet */
e7392364
SG
1316static inline void
1317il3945_synchronize_irq(struct il_priv *il)
4bc85c13 1318{
e7392364 1319 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG
1320 synchronize_irq(il->pci_dev->irq);
1321 tasklet_kill(&il->irq_tasklet);
4bc85c13
WYG
1322}
1323
e7392364
SG
1324static const char *
1325il3945_desc_lookup(int i)
4bc85c13
WYG
1326{
1327 switch (i) {
1328 case 1:
1329 return "FAIL";
1330 case 2:
1331 return "BAD_PARAM";
1332 case 3:
1333 return "BAD_CHECKSUM";
1334 case 4:
1335 return "NMI_INTERRUPT";
1336 case 5:
1337 return "SYSASSERT";
1338 case 6:
1339 return "FATAL_ERROR";
1340 }
1341
1342 return "UNKNOWN";
1343}
1344
1345#define ERROR_START_OFFSET (1 * sizeof(u32))
1346#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1347
e7392364
SG
1348void
1349il3945_dump_nic_error_log(struct il_priv *il)
4bc85c13
WYG
1350{
1351 u32 i;
1352 u32 desc, time, count, base, data1;
1353 u32 blink1, blink2, ilink1, ilink2;
1354
46bc8d4b 1355 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
4bc85c13 1356
e2ebc833 1357 if (!il3945_hw_valid_rtc_data_addr(base)) {
9406f797 1358 IL_ERR("Not valid error log pointer 0x%08X\n", base);
4bc85c13
WYG
1359 return;
1360 }
1361
46bc8d4b 1362 count = il_read_targ_mem(il, base);
4bc85c13
WYG
1363
1364 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 1365 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 1366 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
4bc85c13
WYG
1367 }
1368
9406f797 1369 IL_ERR("Desc Time asrtPC blink2 "
e7392364 1370 "ilink1 nmiPC Line\n");
4bc85c13
WYG
1371 for (i = ERROR_START_OFFSET;
1372 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1373 i += ERROR_ELEM_SIZE) {
46bc8d4b 1374 desc = il_read_targ_mem(il, base + i);
e7392364
SG
1375 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1376 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1377 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1378 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1379 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1380 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
4bc85c13 1381
e7392364
SG
1382 IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1383 il3945_desc_lookup(desc), desc, time, blink1, blink2,
1384 ilink1, ilink2, data1);
4bc85c13
WYG
1385 }
1386}
1387
e7392364
SG
1388static void
1389il3945_irq_tasklet(struct il_priv *il)
4bc85c13
WYG
1390{
1391 u32 inta, handled = 0;
1392 u32 inta_fh;
1393 unsigned long flags;
d3175167 1394#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
1395 u32 inta_mask;
1396#endif
1397
46bc8d4b 1398 spin_lock_irqsave(&il->lock, flags);
4bc85c13
WYG
1399
1400 /* Ack/clear/reset pending uCode interrupts.
1401 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1402 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG
1403 inta = _il_rd(il, CSR_INT);
1404 _il_wr(il, CSR_INT, inta);
4bc85c13
WYG
1405
1406 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1407 * Any new interrupts that happen after this, either while we're
1408 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG
1409 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1410 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4bc85c13 1411
d3175167 1412#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1413 if (il_get_debug_level(il) & IL_DL_ISR) {
4bc85c13 1414 /* just for debug */
841b2cca 1415 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG
1416 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1417 inta_mask, inta_fh);
4bc85c13
WYG
1418 }
1419#endif
1420
46bc8d4b 1421 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1422
1423 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1424 * atomic, make sure that inta covers all the interrupts that
1425 * we've discovered, even if FH interrupt came in just after
1426 * reading CSR_INT. */
1427 if (inta_fh & CSR39_FH_INT_RX_MASK)
1428 inta |= CSR_INT_BIT_FH_RX;
1429 if (inta_fh & CSR39_FH_INT_TX_MASK)
1430 inta |= CSR_INT_BIT_FH_TX;
1431
1432 /* Now service all interrupt bits discovered above. */
1433 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 1434 IL_ERR("Hardware error detected. Restarting.\n");
4bc85c13
WYG
1435
1436 /* Tell the device to stop sending interrupts */
46bc8d4b 1437 il_disable_interrupts(il);
4bc85c13 1438
46bc8d4b
SG
1439 il->isr_stats.hw++;
1440 il_irq_handle_error(il);
4bc85c13
WYG
1441
1442 handled |= CSR_INT_BIT_HW_ERR;
1443
1444 return;
1445 }
d3175167 1446#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1447 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4bc85c13
WYG
1448 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1449 if (inta & CSR_INT_BIT_SCD) {
58de00a4 1450 D_ISR("Scheduler finished to transmit "
e7392364 1451 "the frame/frames.\n");
46bc8d4b 1452 il->isr_stats.sch++;
4bc85c13
WYG
1453 }
1454
1455 /* Alive notification via Rx interrupt will do the real work */
1456 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 1457 D_ISR("Alive interrupt\n");
46bc8d4b 1458 il->isr_stats.alive++;
4bc85c13
WYG
1459 }
1460 }
1461#endif
1462 /* Safely ignore these bits for debug checks below */
1463 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1464
1465 /* Error detected by uCode */
1466 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG
1467 IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1468 inta);
46bc8d4b
SG
1469 il->isr_stats.sw++;
1470 il_irq_handle_error(il);
4bc85c13
WYG
1471 handled |= CSR_INT_BIT_SW_ERR;
1472 }
1473
1474 /* uCode wakes up after power-down sleep */
1475 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 1476 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG
1477 il_rx_queue_update_write_ptr(il, &il->rxq);
1478 il_txq_update_write_ptr(il, &il->txq[0]);
1479 il_txq_update_write_ptr(il, &il->txq[1]);
1480 il_txq_update_write_ptr(il, &il->txq[2]);
1481 il_txq_update_write_ptr(il, &il->txq[3]);
1482 il_txq_update_write_ptr(il, &il->txq[4]);
1483 il_txq_update_write_ptr(il, &il->txq[5]);
1484
1485 il->isr_stats.wakeup++;
4bc85c13
WYG
1486 handled |= CSR_INT_BIT_WAKEUP;
1487 }
1488
1489 /* All uCode command responses, including Tx command responses,
1490 * Rx "responses" (frame-received notification), and other
1491 * notifications from uCode come through here*/
1492 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG
1493 il3945_rx_handle(il);
1494 il->isr_stats.rx++;
4bc85c13
WYG
1495 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1496 }
1497
1498 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 1499 D_ISR("Tx interrupt\n");
46bc8d4b 1500 il->isr_stats.tx++;
4bc85c13 1501
841b2cca 1502 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
e7392364 1503 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
4bc85c13
WYG
1504 handled |= CSR_INT_BIT_FH_TX;
1505 }
1506
1507 if (inta & ~handled) {
9406f797 1508 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 1509 il->isr_stats.unhandled++;
4bc85c13
WYG
1510 }
1511
46bc8d4b 1512 if (inta & ~il->inta_mask) {
9406f797 1513 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 1514 inta & ~il->inta_mask);
53143a18 1515 IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
4bc85c13
WYG
1516 }
1517
1518 /* Re-enable all interrupts */
1519 /* only Re-enable if disabled by irq */
a6766ccd 1520 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 1521 il_enable_interrupts(il);
4bc85c13 1522
d3175167 1523#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1524 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG
1525 inta = _il_rd(il, CSR_INT);
1526 inta_mask = _il_rd(il, CSR_INT_MASK);
1527 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
58de00a4 1528 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
e7392364 1529 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4bc85c13
WYG
1530 }
1531#endif
1532}
1533
e7392364
SG
1534static int
1535il3945_get_channels_for_scan(struct il_priv *il, enum ieee80211_band band,
1536 u8 is_active, u8 n_probes,
1537 struct il3945_scan_channel *scan_ch,
1538 struct ieee80211_vif *vif)
4bc85c13
WYG
1539{
1540 struct ieee80211_channel *chan;
1541 const struct ieee80211_supported_band *sband;
e2ebc833 1542 const struct il_channel_info *ch_info;
4bc85c13
WYG
1543 u16 passive_dwell = 0;
1544 u16 active_dwell = 0;
1545 int added, i;
1546
46bc8d4b 1547 sband = il_get_hw_mode(il, band);
4bc85c13
WYG
1548 if (!sband)
1549 return 0;
1550
46bc8d4b
SG
1551 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1552 passive_dwell = il_get_passive_dwell_time(il, band, vif);
4bc85c13
WYG
1553
1554 if (passive_dwell <= active_dwell)
1555 passive_dwell = active_dwell + 1;
1556
46bc8d4b
SG
1557 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1558 chan = il->scan_request->channels[i];
4bc85c13
WYG
1559
1560 if (chan->band != band)
1561 continue;
1562
1563 scan_ch->channel = chan->hw_value;
1564
e7392364 1565 ch_info = il_get_channel_info(il, band, scan_ch->channel);
e2ebc833 1566 if (!il_is_channel_valid(ch_info)) {
e7392364 1567 D_SCAN("Channel %d is INVALID for this band.\n",
be663ab6 1568 scan_ch->channel);
4bc85c13
WYG
1569 continue;
1570 }
1571
1572 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1573 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1574 /* If passive , set up for auto-switch
1575 * and use long active_dwell time.
1576 */
e2ebc833 1577 if (!is_active || il_is_channel_passive(ch_info) ||
4bc85c13
WYG
1578 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
1579 scan_ch->type = 0; /* passive */
46bc8d4b 1580 if (IL_UCODE_API(il->ucode_ver) == 1)
e7392364
SG
1581 scan_ch->active_dwell =
1582 cpu_to_le16(passive_dwell - 1);
4bc85c13
WYG
1583 } else {
1584 scan_ch->type = 1; /* active */
1585 }
1586
1587 /* Set direct probe bits. These may be used both for active
1588 * scan channels (probes gets sent right away),
1589 * or for passive channels (probes get se sent only after
1590 * hearing clear Rx packet).*/
46bc8d4b 1591 if (IL_UCODE_API(il->ucode_ver) >= 2) {
4bc85c13 1592 if (n_probes)
d3175167 1593 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1594 } else {
1595 /* uCode v1 does not allow setting direct probe bits on
1596 * passive channel. */
1597 if ((scan_ch->type & 1) && n_probes)
d3175167 1598 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1599 }
1600
1601 /* Set txpower levels to defaults */
1602 scan_ch->tpc.dsp_atten = 110;
1603 /* scan_pwr_info->tpc.dsp_atten; */
1604
1605 /*scan_pwr_info->tpc.tx_gain; */
1606 if (band == IEEE80211_BAND_5GHZ)
1607 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1608 else {
1609 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1610 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1611 * power level:
1612 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
1613 */
1614 }
1615
e7392364
SG
1616 D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1617 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1618 (scan_ch->type & 1) ? active_dwell : passive_dwell);
4bc85c13
WYG
1619
1620 scan_ch++;
1621 added++;
1622 }
1623
58de00a4 1624 D_SCAN("total channels to scan %d\n", added);
4bc85c13
WYG
1625 return added;
1626}
1627
e7392364
SG
1628static void
1629il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
4bc85c13
WYG
1630{
1631 int i;
1632
2eb05816 1633 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
e2ebc833 1634 rates[i].bitrate = il3945_rates[i].ieee * 5;
e7392364 1635 rates[i].hw_value = i; /* Rate scaling will work on idxes */
4bc85c13
WYG
1636 rates[i].hw_value_short = i;
1637 rates[i].flags = 0;
d3175167 1638 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
4bc85c13
WYG
1639 /*
1640 * If CCK != 1M then set short preamble rate flag.
1641 */
e7392364
SG
1642 rates[i].flags |=
1643 (il3945_rates[i].plcp ==
1644 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4bc85c13
WYG
1645 }
1646 }
1647}
1648
1649/******************************************************************************
1650 *
1651 * uCode download functions
1652 *
1653 ******************************************************************************/
1654
e7392364
SG
1655static void
1656il3945_dealloc_ucode_pci(struct il_priv *il)
4bc85c13 1657{
46bc8d4b
SG
1658 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1659 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1660 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1661 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1662 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1663 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13
WYG
1664}
1665
1666/**
e2ebc833 1667 * il3945_verify_inst_full - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1668 * looking at all data.
1669 */
e7392364
SG
1670static int
1671il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
4bc85c13
WYG
1672{
1673 u32 val;
1674 u32 save_len = len;
1675 int rc = 0;
1676 u32 errcnt;
1677
58de00a4 1678 D_INFO("ucode inst image size is %u\n", len);
4bc85c13 1679
e7392364 1680 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
4bc85c13
WYG
1681
1682 errcnt = 0;
1683 for (; len > 0; len -= sizeof(u32), image++) {
1684 /* read data comes through single port, auto-incr addr */
1685 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1686 * if IL_DL_IO is set */
1c8cae57 1687 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13 1688 if (val != le32_to_cpu(*image)) {
9406f797 1689 IL_ERR("uCode INST section is invalid at "
e7392364
SG
1690 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1691 save_len - len, val, le32_to_cpu(*image));
4bc85c13
WYG
1692 rc = -EIO;
1693 errcnt++;
1694 if (errcnt >= 20)
1695 break;
1696 }
1697 }
1698
4bc85c13 1699 if (!errcnt)
e7392364 1700 D_INFO("ucode image in INSTRUCTION memory is good\n");
4bc85c13
WYG
1701
1702 return rc;
1703}
1704
4bc85c13 1705/**
e2ebc833 1706 * il3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1707 * using sample data 100 bytes apart. If these sample points are good,
1708 * it's a pretty good bet that everything between them is good, too.
1709 */
e7392364
SG
1710static int
1711il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
4bc85c13
WYG
1712{
1713 u32 val;
1714 int rc = 0;
1715 u32 errcnt = 0;
1716 u32 i;
1717
58de00a4 1718 D_INFO("ucode inst image size is %u\n", len);
4bc85c13 1719
e7392364 1720 for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
4bc85c13
WYG
1721 /* read data comes through single port, auto-incr addr */
1722 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1723 * if IL_DL_IO is set */
e7392364 1724 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1c8cae57 1725 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13 1726 if (val != le32_to_cpu(*image)) {
e7392364 1727#if 0 /* Enable this if you want to see details */
9406f797 1728 IL_ERR("uCode INST section is invalid at "
e7392364
SG
1729 "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1730 *image);
4bc85c13
WYG
1731#endif
1732 rc = -EIO;
1733 errcnt++;
1734 if (errcnt >= 3)
1735 break;
1736 }
1737 }
1738
1739 return rc;
1740}
1741
4bc85c13 1742/**
e2ebc833 1743 * il3945_verify_ucode - determine which instruction image is in SRAM,
4bc85c13
WYG
1744 * and verify its contents
1745 */
e7392364
SG
1746static int
1747il3945_verify_ucode(struct il_priv *il)
4bc85c13
WYG
1748{
1749 __le32 *image;
1750 u32 len;
1751 int rc = 0;
1752
1753 /* Try bootstrap */
e7392364 1754 image = (__le32 *) il->ucode_boot.v_addr;
46bc8d4b
SG
1755 len = il->ucode_boot.len;
1756 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1757 if (rc == 0) {
58de00a4 1758 D_INFO("Bootstrap uCode is good in inst SRAM\n");
4bc85c13
WYG
1759 return 0;
1760 }
1761
1762 /* Try initialize */
e7392364 1763 image = (__le32 *) il->ucode_init.v_addr;
46bc8d4b
SG
1764 len = il->ucode_init.len;
1765 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1766 if (rc == 0) {
58de00a4 1767 D_INFO("Initialize uCode is good in inst SRAM\n");
4bc85c13
WYG
1768 return 0;
1769 }
1770
1771 /* Try runtime/protocol */
e7392364 1772 image = (__le32 *) il->ucode_code.v_addr;
46bc8d4b
SG
1773 len = il->ucode_code.len;
1774 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1775 if (rc == 0) {
58de00a4 1776 D_INFO("Runtime uCode is good in inst SRAM\n");
4bc85c13
WYG
1777 return 0;
1778 }
1779
9406f797 1780 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
4bc85c13
WYG
1781
1782 /* Since nothing seems to match, show first several data entries in
1783 * instruction SRAM, so maybe visual inspection will give a clue.
1784 * Selection of bootstrap image (vs. other images) is arbitrary. */
e7392364 1785 image = (__le32 *) il->ucode_boot.v_addr;
46bc8d4b
SG
1786 len = il->ucode_boot.len;
1787 rc = il3945_verify_inst_full(il, image, len);
4bc85c13
WYG
1788
1789 return rc;
1790}
1791
e7392364
SG
1792static void
1793il3945_nic_start(struct il_priv *il)
4bc85c13
WYG
1794{
1795 /* Remove all resets to allow NIC to operate */
841b2cca 1796 _il_wr(il, CSR_RESET, 0);
4bc85c13
WYG
1797}
1798
d3175167 1799#define IL3945_UCODE_GET(item) \
e2ebc833 1800static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
4bc85c13 1801{ \
be663ab6 1802 return le32_to_cpu(ucode->v1.item); \
4bc85c13
WYG
1803}
1804
e7392364
SG
1805static u32
1806il3945_ucode_get_header_size(u32 api_ver)
4bc85c13
WYG
1807{
1808 return 24;
1809}
1810
e7392364
SG
1811static u8 *
1812il3945_ucode_get_data(const struct il_ucode_header *ucode)
4bc85c13 1813{
be663ab6 1814 return (u8 *) ucode->v1.data;
4bc85c13
WYG
1815}
1816
d3175167
SG
1817IL3945_UCODE_GET(inst_size);
1818IL3945_UCODE_GET(data_size);
1819IL3945_UCODE_GET(init_size);
1820IL3945_UCODE_GET(init_data_size);
1821IL3945_UCODE_GET(boot_size);
4bc85c13
WYG
1822
1823/**
e2ebc833 1824 * il3945_read_ucode - Read uCode images from disk file.
4bc85c13
WYG
1825 *
1826 * Copy into buffers for card to fetch via bus-mastering
1827 */
e7392364
SG
1828static int
1829il3945_read_ucode(struct il_priv *il)
4bc85c13 1830{
e2ebc833 1831 const struct il_ucode_header *ucode;
0c2c8852 1832 int ret = -EINVAL, idx;
4bc85c13
WYG
1833 const struct firmware *ucode_raw;
1834 /* firmware file name contains uCode/driver compatibility version */
46bc8d4b
SG
1835 const char *name_pre = il->cfg->fw_name_pre;
1836 const unsigned int api_max = il->cfg->ucode_api_max;
1837 const unsigned int api_min = il->cfg->ucode_api_min;
4bc85c13
WYG
1838 char buf[25];
1839 u8 *src;
1840 size_t len;
1841 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1842
1843 /* Ask kernel firmware_class module to get the boot firmware off disk.
1844 * request_firmware() is synchronous, file is in memory on return. */
0c2c8852
SG
1845 for (idx = api_max; idx >= api_min; idx--) {
1846 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
46bc8d4b 1847 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
4bc85c13 1848 if (ret < 0) {
e7392364 1849 IL_ERR("%s firmware file req failed: %d\n", buf, ret);
4bc85c13
WYG
1850 if (ret == -ENOENT)
1851 continue;
1852 else
1853 goto error;
1854 } else {
0c2c8852 1855 if (idx < api_max)
9406f797 1856 IL_ERR("Loaded firmware %s, "
e7392364
SG
1857 "which is deprecated. "
1858 " Please use API v%u instead.\n", buf,
1859 api_max);
58de00a4 1860 D_INFO("Got firmware '%s' file "
e7392364 1861 "(%zd bytes) from disk\n", buf, ucode_raw->size);
4bc85c13
WYG
1862 break;
1863 }
1864 }
1865
1866 if (ret < 0)
1867 goto error;
1868
1869 /* Make sure that we got at least our header! */
e7392364 1870 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
9406f797 1871 IL_ERR("File size way too small!\n");
4bc85c13
WYG
1872 ret = -EINVAL;
1873 goto err_release;
1874 }
1875
1876 /* Data from ucode file: header followed by uCode images */
e2ebc833 1877 ucode = (struct il_ucode_header *)ucode_raw->data;
4bc85c13 1878
46bc8d4b
SG
1879 il->ucode_ver = le32_to_cpu(ucode->ver);
1880 api_ver = IL_UCODE_API(il->ucode_ver);
e2ebc833
SG
1881 inst_size = il3945_ucode_get_inst_size(ucode);
1882 data_size = il3945_ucode_get_data_size(ucode);
1883 init_size = il3945_ucode_get_init_size(ucode);
1884 init_data_size = il3945_ucode_get_init_data_size(ucode);
1885 boot_size = il3945_ucode_get_boot_size(ucode);
1886 src = il3945_ucode_get_data(ucode);
4bc85c13
WYG
1887
1888 /* api_ver should match the api version forming part of the
1889 * firmware filename ... but we don't check for that and only rely
1890 * on the API version read from firmware header from here on forward */
1891
1892 if (api_ver < api_min || api_ver > api_max) {
9406f797 1893 IL_ERR("Driver unable to support your firmware API. "
e7392364
SG
1894 "Driver supports v%u, firmware is v%u.\n", api_max,
1895 api_ver);
46bc8d4b 1896 il->ucode_ver = 0;
4bc85c13
WYG
1897 ret = -EINVAL;
1898 goto err_release;
1899 }
1900 if (api_ver != api_max)
9406f797 1901 IL_ERR("Firmware has old API version. Expected %u, "
e7392364
SG
1902 "got %u. New firmware can be obtained "
1903 "from http://www.intellinuxwireless.org.\n", api_max,
1904 api_ver);
4bc85c13 1905
9406f797 1906 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG
1907 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1908 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
46bc8d4b 1909
e7392364
SG
1910 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1911 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1912 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1913 IL_UCODE_SERIAL(il->ucode_ver));
4bc85c13 1914
e7392364
SG
1915 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1916 D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1917 D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1918 D_INFO("f/w package hdr init inst size = %u\n", init_size);
1919 D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1920 D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
4bc85c13
WYG
1921
1922 /* Verify size of file vs. image size info in file's header */
e7392364
SG
1923 if (ucode_raw->size !=
1924 il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1925 init_size + init_data_size + boot_size) {
4bc85c13 1926
e7392364
SG
1927 D_INFO("uCode file size %zd does not match expected size\n",
1928 ucode_raw->size);
4bc85c13
WYG
1929 ret = -EINVAL;
1930 goto err_release;
1931 }
1932
1933 /* Verify that uCode images will fit in card's SRAM */
d3175167 1934 if (inst_size > IL39_MAX_INST_SIZE) {
e7392364 1935 D_INFO("uCode instr len %d too large to fit in\n", inst_size);
4bc85c13
WYG
1936 ret = -EINVAL;
1937 goto err_release;
1938 }
1939
d3175167 1940 if (data_size > IL39_MAX_DATA_SIZE) {
e7392364 1941 D_INFO("uCode data len %d too large to fit in\n", data_size);
4bc85c13
WYG
1942 ret = -EINVAL;
1943 goto err_release;
1944 }
d3175167 1945 if (init_size > IL39_MAX_INST_SIZE) {
e7392364
SG
1946 D_INFO("uCode init instr len %d too large to fit in\n",
1947 init_size);
4bc85c13
WYG
1948 ret = -EINVAL;
1949 goto err_release;
1950 }
d3175167 1951 if (init_data_size > IL39_MAX_DATA_SIZE) {
e7392364
SG
1952 D_INFO("uCode init data len %d too large to fit in\n",
1953 init_data_size);
4bc85c13
WYG
1954 ret = -EINVAL;
1955 goto err_release;
1956 }
d3175167 1957 if (boot_size > IL39_MAX_BSM_SIZE) {
e7392364
SG
1958 D_INFO("uCode boot instr len %d too large to fit in\n",
1959 boot_size);
4bc85c13
WYG
1960 ret = -EINVAL;
1961 goto err_release;
1962 }
1963
1964 /* Allocate ucode buffers for card's bus-master loading ... */
1965
1966 /* Runtime instructions and 2 copies of data:
1967 * 1) unmodified from disk
1968 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG
1969 il->ucode_code.len = inst_size;
1970 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4bc85c13 1971
46bc8d4b
SG
1972 il->ucode_data.len = data_size;
1973 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4bc85c13 1974
46bc8d4b
SG
1975 il->ucode_data_backup.len = data_size;
1976 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4bc85c13 1977
46bc8d4b
SG
1978 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1979 !il->ucode_data_backup.v_addr)
4bc85c13
WYG
1980 goto err_pci_alloc;
1981
1982 /* Initialization instructions and data */
1983 if (init_size && init_data_size) {
46bc8d4b
SG
1984 il->ucode_init.len = init_size;
1985 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4bc85c13 1986
46bc8d4b
SG
1987 il->ucode_init_data.len = init_data_size;
1988 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4bc85c13 1989
46bc8d4b 1990 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4bc85c13
WYG
1991 goto err_pci_alloc;
1992 }
1993
1994 /* Bootstrap (instructions only, no data) */
1995 if (boot_size) {
46bc8d4b
SG
1996 il->ucode_boot.len = boot_size;
1997 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13 1998
46bc8d4b 1999 if (!il->ucode_boot.v_addr)
4bc85c13
WYG
2000 goto err_pci_alloc;
2001 }
2002
2003 /* Copy images into buffers for card's bus-master reads ... */
2004
2005 /* Runtime instructions (first block of data in file) */
2006 len = inst_size;
e7392364 2007 D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
46bc8d4b 2008 memcpy(il->ucode_code.v_addr, src, len);
4bc85c13
WYG
2009 src += len;
2010
58de00a4 2011 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 2012 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4bc85c13
WYG
2013
2014 /* Runtime data (2nd block)
e2ebc833 2015 * NOTE: Copy into backup buffer will be done in il3945_up() */
4bc85c13 2016 len = data_size;
e7392364 2017 D_INFO("Copying (but not loading) uCode data len %zd\n", len);
46bc8d4b
SG
2018 memcpy(il->ucode_data.v_addr, src, len);
2019 memcpy(il->ucode_data_backup.v_addr, src, len);
4bc85c13
WYG
2020 src += len;
2021
2022 /* Initialization instructions (3rd block) */
2023 if (init_size) {
2024 len = init_size;
e7392364 2025 D_INFO("Copying (but not loading) init instr len %zd\n", len);
46bc8d4b 2026 memcpy(il->ucode_init.v_addr, src, len);
4bc85c13
WYG
2027 src += len;
2028 }
2029
2030 /* Initialization data (4th block) */
2031 if (init_data_size) {
2032 len = init_data_size;
e7392364 2033 D_INFO("Copying (but not loading) init data len %zd\n", len);
46bc8d4b 2034 memcpy(il->ucode_init_data.v_addr, src, len);
4bc85c13
WYG
2035 src += len;
2036 }
2037
2038 /* Bootstrap instructions (5th block) */
2039 len = boot_size;
e7392364 2040 D_INFO("Copying (but not loading) boot instr len %zd\n", len);
46bc8d4b 2041 memcpy(il->ucode_boot.v_addr, src, len);
4bc85c13
WYG
2042
2043 /* We have our copies now, allow OS release its copies */
2044 release_firmware(ucode_raw);
2045 return 0;
2046
e7392364 2047err_pci_alloc:
9406f797 2048 IL_ERR("failed to allocate pci memory\n");
4bc85c13 2049 ret = -ENOMEM;
46bc8d4b 2050 il3945_dealloc_ucode_pci(il);
4bc85c13 2051
e7392364 2052err_release:
4bc85c13
WYG
2053 release_firmware(ucode_raw);
2054
e7392364 2055error:
4bc85c13
WYG
2056 return ret;
2057}
2058
4bc85c13 2059/**
e2ebc833 2060 * il3945_set_ucode_ptrs - Set uCode address location
4bc85c13
WYG
2061 *
2062 * Tell initialization uCode where to find runtime uCode.
2063 *
2064 * BSM registers initially contain pointers to initialization uCode.
2065 * We need to replace them to load runtime uCode inst and data,
2066 * and to save runtime data when powering down.
2067 */
e7392364
SG
2068static int
2069il3945_set_ucode_ptrs(struct il_priv *il)
4bc85c13
WYG
2070{
2071 dma_addr_t pinst;
2072 dma_addr_t pdata;
2073
2074 /* bits 31:0 for 3945 */
46bc8d4b
SG
2075 pinst = il->ucode_code.p_addr;
2076 pdata = il->ucode_data_backup.p_addr;
4bc85c13
WYG
2077
2078 /* Tell bootstrap uCode where to find image to load */
db54eb57
SG
2079 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2080 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
e7392364 2081 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
4bc85c13
WYG
2082
2083 /* Inst byte count must be last to set up, bit 31 signals uCode
2084 * that all new ptr/size info is in place */
db54eb57 2085 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
e7392364 2086 il->ucode_code.len | BSM_DRAM_INST_LOAD);
4bc85c13 2087
58de00a4 2088 D_INFO("Runtime uCode pointers are set.\n");
4bc85c13
WYG
2089
2090 return 0;
2091}
2092
2093/**
4d69c752 2094 * il3945_init_alive_start - Called after N_ALIVE notification received
4bc85c13 2095 *
4d69c752 2096 * Called after N_ALIVE notification received from "initialize" uCode.
4bc85c13
WYG
2097 *
2098 * Tell "initialize" uCode to go ahead and load the runtime uCode.
2099 */
e7392364
SG
2100static void
2101il3945_init_alive_start(struct il_priv *il)
4bc85c13
WYG
2102{
2103 /* Check alive response for "valid" sign from uCode */
46bc8d4b 2104 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2105 /* We had an error bringing up the hardware, so take it
2106 * all the way back down so we can try again */
58de00a4 2107 D_INFO("Initialize Alive failed.\n");
4bc85c13
WYG
2108 goto restart;
2109 }
2110
2111 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2112 * This is a paranoid check, because we would not have gotten the
2113 * "initialize" alive if code weren't properly loaded. */
46bc8d4b 2114 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2115 /* Runtime instruction load was bad;
2116 * take it all the way back down so we can try again */
58de00a4 2117 D_INFO("Bad \"initialize\" uCode load.\n");
4bc85c13
WYG
2118 goto restart;
2119 }
2120
2121 /* Send pointers to protocol/runtime uCode image ... init code will
2122 * load and launch runtime uCode, which will send us another "Alive"
2123 * notification. */
58de00a4 2124 D_INFO("Initialization Alive received.\n");
46bc8d4b 2125 if (il3945_set_ucode_ptrs(il)) {
4bc85c13
WYG
2126 /* Runtime instruction load won't happen;
2127 * take it all the way back down so we can try again */
58de00a4 2128 D_INFO("Couldn't set up uCode pointers.\n");
4bc85c13
WYG
2129 goto restart;
2130 }
2131 return;
2132
e7392364 2133restart:
46bc8d4b 2134 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2135}
2136
2137/**
4d69c752 2138 * il3945_alive_start - called after N_ALIVE notification received
4bc85c13 2139 * from protocol/runtime uCode (initialization uCode's
e2ebc833 2140 * Alive gets handled by il3945_init_alive_start()).
4bc85c13 2141 */
e7392364
SG
2142static void
2143il3945_alive_start(struct il_priv *il)
4bc85c13
WYG
2144{
2145 int thermal_spin = 0;
2146 u32 rfkill;
4bc85c13 2147
58de00a4 2148 D_INFO("Runtime Alive received.\n");
4bc85c13 2149
46bc8d4b 2150 if (il->card_alive.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2151 /* We had an error bringing up the hardware, so take it
2152 * all the way back down so we can try again */
58de00a4 2153 D_INFO("Alive failed.\n");
4bc85c13
WYG
2154 goto restart;
2155 }
2156
2157 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2158 * This is a paranoid check, because we would not have gotten the
2159 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 2160 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2161 /* Runtime instruction load was bad;
2162 * take it all the way back down so we can try again */
58de00a4 2163 D_INFO("Bad runtime uCode load.\n");
4bc85c13
WYG
2164 goto restart;
2165 }
2166
db54eb57 2167 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
58de00a4 2168 D_INFO("RFKILL status: 0x%x\n", rfkill);
4bc85c13
WYG
2169
2170 if (rfkill & 0x1) {
bc269a8e 2171 clear_bit(S_RFKILL, &il->status);
4bc85c13
WYG
2172 /* if RFKILL is not on, then wait for thermal
2173 * sensor in adapter to kick in */
46bc8d4b 2174 while (il3945_hw_get_temperature(il) == 0) {
4bc85c13
WYG
2175 thermal_spin++;
2176 udelay(10);
2177 }
2178
2179 if (thermal_spin)
58de00a4 2180 D_INFO("Thermal calibration took %dus\n",
e7392364 2181 thermal_spin * 10);
4bc85c13 2182 } else
bc269a8e 2183 set_bit(S_RFKILL, &il->status);
4bc85c13
WYG
2184
2185 /* After the ALIVE response, we can send commands to 3945 uCode */
a6766ccd 2186 set_bit(S_ALIVE, &il->status);
4bc85c13
WYG
2187
2188 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 2189 il_setup_watchdog(il);
4bc85c13 2190
46bc8d4b 2191 if (il_is_rfkill(il))
4bc85c13
WYG
2192 return;
2193
46bc8d4b 2194 ieee80211_wake_queues(il->hw);
4bc85c13 2195
2eb05816 2196 il->active_rate = RATES_MASK_3945;
4bc85c13 2197
46bc8d4b 2198 il_power_update_mode(il, true);
4bc85c13 2199
7c2cde2e 2200 if (il_is_associated(il)) {
e2ebc833 2201 struct il3945_rxon_cmd *active_rxon =
c8b03958 2202 (struct il3945_rxon_cmd *)(&il->active);
4bc85c13 2203
c8b03958 2204 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
4bc85c13
WYG
2205 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2206 } else {
2207 /* Initialize our rx_config data */
83007196 2208 il_connection_init_rx_config(il);
4bc85c13
WYG
2209 }
2210
2211 /* Configure Bluetooth device coexistence support */
46bc8d4b 2212 il_send_bt_config(il);
4bc85c13 2213
a6766ccd 2214 set_bit(S_READY, &il->status);
4bc85c13
WYG
2215
2216 /* Configure the adapter for unassociated operation */
83007196 2217 il3945_commit_rxon(il);
4bc85c13 2218
46bc8d4b 2219 il3945_reg_txpower_periodic(il);
4bc85c13 2220
58de00a4 2221 D_INFO("ALIVE processing complete.\n");
46bc8d4b 2222 wake_up(&il->wait_command_queue);
4bc85c13
WYG
2223
2224 return;
2225
e7392364 2226restart:
46bc8d4b 2227 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2228}
2229
46bc8d4b 2230static void il3945_cancel_deferred_work(struct il_priv *il);
4bc85c13 2231
e7392364
SG
2232static void
2233__il3945_down(struct il_priv *il)
4bc85c13
WYG
2234{
2235 unsigned long flags;
2236 int exit_pending;
2237
58de00a4 2238 D_INFO(DRV_NAME " is going down\n");
4bc85c13 2239
46bc8d4b 2240 il_scan_cancel_timeout(il, 200);
4bc85c13 2241
a6766ccd 2242 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
4bc85c13 2243
a6766ccd 2244 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
4bc85c13 2245 * to prevent rearm timer */
46bc8d4b 2246 del_timer_sync(&il->watchdog);
4bc85c13
WYG
2247
2248 /* Station information will now be cleared in device */
83007196 2249 il_clear_ucode_stations(il);
46bc8d4b
SG
2250 il_dealloc_bcast_stations(il);
2251 il_clear_driver_stations(il);
4bc85c13
WYG
2252
2253 /* Unblock any waiting calls */
46bc8d4b 2254 wake_up_all(&il->wait_command_queue);
4bc85c13
WYG
2255
2256 /* Wipe out the EXIT_PENDING status bit if we are not actually
2257 * exiting the module */
2258 if (!exit_pending)
a6766ccd 2259 clear_bit(S_EXIT_PENDING, &il->status);
4bc85c13
WYG
2260
2261 /* stop and reset the on-board processor */
841b2cca 2262 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
2263
2264 /* tell the device to stop sending interrupts */
46bc8d4b
SG
2265 spin_lock_irqsave(&il->lock, flags);
2266 il_disable_interrupts(il);
2267 spin_unlock_irqrestore(&il->lock, flags);
2268 il3945_synchronize_irq(il);
4bc85c13 2269
46bc8d4b
SG
2270 if (il->mac80211_registered)
2271 ieee80211_stop_queues(il->hw);
4bc85c13 2272
e2ebc833 2273 /* If we have not previously called il3945_init() then
4bc85c13 2274 * clear all bits but the RF Kill bits and return */
46bc8d4b 2275 if (!il_is_init(il)) {
e7392364 2276 il->status =
bc269a8e 2277 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0 2278 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
e7392364 2279 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
4bc85c13
WYG
2280 goto exit;
2281 }
2282
2283 /* ...otherwise clear out all the status bits but the RF Kill
2284 * bit and continue taking the NIC down. */
e7392364 2285 il->status &=
bc269a8e 2286 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0
SG
2287 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2288 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
e7392364 2289 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
4bc85c13 2290
775ed8ab
SG
2291 /*
2292 * We disabled and synchronized interrupt, and priv->mutex is taken, so
2293 * here is the only thread which will program device registers, but
2294 * still have lockdep assertions, so we are taking reg_lock.
2295 */
2296 spin_lock_irq(&il->reg_lock);
2297 /* FIXME: il_grab_nic_access if rfkill is off ? */
2298
46bc8d4b
SG
2299 il3945_hw_txq_ctx_stop(il);
2300 il3945_hw_rxq_stop(il);
4bc85c13 2301 /* Power-down device's busmaster DMA clocks */
775ed8ab 2302 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
4bc85c13 2303 udelay(5);
4bc85c13 2304 /* Stop the device, and put it in low power state */
775ed8ab
SG
2305 _il_apm_stop(il);
2306
2307 spin_unlock_irq(&il->reg_lock);
4bc85c13 2308
775ed8ab 2309 il3945_hw_txq_ctx_free(il);
e7392364 2310exit:
46bc8d4b 2311 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
4bc85c13 2312
46bc8d4b
SG
2313 if (il->beacon_skb)
2314 dev_kfree_skb(il->beacon_skb);
2315 il->beacon_skb = NULL;
4bc85c13
WYG
2316
2317 /* clear out any free frames */
46bc8d4b 2318 il3945_clear_free_frames(il);
4bc85c13
WYG
2319}
2320
e7392364
SG
2321static void
2322il3945_down(struct il_priv *il)
4bc85c13 2323{
46bc8d4b
SG
2324 mutex_lock(&il->mutex);
2325 __il3945_down(il);
2326 mutex_unlock(&il->mutex);
4bc85c13 2327
46bc8d4b 2328 il3945_cancel_deferred_work(il);
4bc85c13
WYG
2329}
2330
2331#define MAX_HW_RESTARTS 5
2332
e7392364
SG
2333static int
2334il3945_alloc_bcast_station(struct il_priv *il)
4bc85c13 2335{
4bc85c13
WYG
2336 unsigned long flags;
2337 u8 sta_id;
2338
46bc8d4b 2339 spin_lock_irqsave(&il->sta_lock, flags);
83007196 2340 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
e2ebc833 2341 if (sta_id == IL_INVALID_STATION) {
9406f797 2342 IL_ERR("Unable to prepare broadcast station\n");
46bc8d4b 2343 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2344
2345 return -EINVAL;
2346 }
2347
46bc8d4b
SG
2348 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2349 il->stations[sta_id].used |= IL_STA_BCAST;
2350 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2351
2352 return 0;
2353}
2354
e7392364
SG
2355static int
2356__il3945_up(struct il_priv *il)
4bc85c13
WYG
2357{
2358 int rc, i;
2359
46bc8d4b 2360 rc = il3945_alloc_bcast_station(il);
4bc85c13
WYG
2361 if (rc)
2362 return rc;
2363
a6766ccd 2364 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 2365 IL_WARN("Exit pending; will not bring the NIC up\n");
4bc85c13
WYG
2366 return -EIO;
2367 }
2368
46bc8d4b 2369 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 2370 IL_ERR("ucode not available for device bring up\n");
4bc85c13
WYG
2371 return -EIO;
2372 }
2373
2374 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 2375 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 2376 clear_bit(S_RFKILL, &il->status);
4bc85c13 2377 else {
bc269a8e 2378 set_bit(S_RFKILL, &il->status);
9406f797 2379 IL_WARN("Radio disabled by HW RF Kill switch\n");
4bc85c13
WYG
2380 return -ENODEV;
2381 }
2382
841b2cca 2383 _il_wr(il, CSR_INT, 0xFFFFFFFF);
4bc85c13 2384
46bc8d4b 2385 rc = il3945_hw_nic_init(il);
4bc85c13 2386 if (rc) {
9406f797 2387 IL_ERR("Unable to int nic\n");
4bc85c13
WYG
2388 return rc;
2389 }
2390
2391 /* make sure rfkill handshake bits are cleared */
841b2cca 2392 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 2393 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4bc85c13
WYG
2394
2395 /* clear (again), then enable host interrupts */
841b2cca 2396 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 2397 il_enable_interrupts(il);
4bc85c13
WYG
2398
2399 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG
2400 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2401 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4bc85c13
WYG
2402
2403 /* Copy original ucode data image from disk into backup cache.
2404 * This will be used to initialize the on-board processor's
2405 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG
2406 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2407 il->ucode_data.len);
4bc85c13
WYG
2408
2409 /* We return success when we resume from suspend and rf_kill is on. */
bc269a8e 2410 if (test_bit(S_RFKILL, &il->status))
4bc85c13
WYG
2411 return 0;
2412
2413 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2414
2415 /* load bootstrap state machine,
2416 * load bootstrap program into processor's memory,
2417 * prepare to load the "initialize" uCode */
1600b875 2418 rc = il->ops->load_ucode(il);
4bc85c13
WYG
2419
2420 if (rc) {
e7392364 2421 IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
4bc85c13
WYG
2422 continue;
2423 }
2424
2425 /* start card; "initialize" will load runtime ucode */
46bc8d4b 2426 il3945_nic_start(il);
4bc85c13 2427
58de00a4 2428 D_INFO(DRV_NAME " is coming up\n");
4bc85c13
WYG
2429
2430 return 0;
2431 }
2432
a6766ccd 2433 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 2434 __il3945_down(il);
a6766ccd 2435 clear_bit(S_EXIT_PENDING, &il->status);
4bc85c13
WYG
2436
2437 /* tried to restart and config the device for as long as our
2438 * patience could withstand */
9406f797 2439 IL_ERR("Unable to initialize device after %d attempts.\n", i);
4bc85c13
WYG
2440 return -EIO;
2441}
2442
4bc85c13
WYG
2443/*****************************************************************************
2444 *
2445 * Workqueue callbacks
2446 *
2447 *****************************************************************************/
2448
e7392364
SG
2449static void
2450il3945_bg_init_alive_start(struct work_struct *data)
4bc85c13 2451{
46bc8d4b 2452 struct il_priv *il =
e2ebc833 2453 container_of(data, struct il_priv, init_alive_start.work);
4bc85c13 2454
46bc8d4b 2455 mutex_lock(&il->mutex);
a6766ccd 2456 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 2457 goto out;
4bc85c13 2458
46bc8d4b 2459 il3945_init_alive_start(il);
28a6e577 2460out:
46bc8d4b 2461 mutex_unlock(&il->mutex);
4bc85c13
WYG
2462}
2463
e7392364
SG
2464static void
2465il3945_bg_alive_start(struct work_struct *data)
4bc85c13 2466{
46bc8d4b 2467 struct il_priv *il =
e2ebc833 2468 container_of(data, struct il_priv, alive_start.work);
4bc85c13 2469
46bc8d4b 2470 mutex_lock(&il->mutex);
210787e8 2471 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
28a6e577 2472 goto out;
4bc85c13 2473
46bc8d4b 2474 il3945_alive_start(il);
28a6e577 2475out:
46bc8d4b 2476 mutex_unlock(&il->mutex);
4bc85c13
WYG
2477}
2478
2479/*
2480 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2481 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2482 * *is* readable even when device has been SW_RESET into low power mode
2483 * (e.g. during RF KILL).
2484 */
e7392364
SG
2485static void
2486il3945_rfkill_poll(struct work_struct *data)
4bc85c13 2487{
46bc8d4b 2488 struct il_priv *il =
e2ebc833 2489 container_of(data, struct il_priv, _3945.rfkill_poll.work);
bc269a8e 2490 bool old_rfkill = test_bit(S_RFKILL, &il->status);
e7392364
SG
2491 bool new_rfkill =
2492 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
4bc85c13
WYG
2493
2494 if (new_rfkill != old_rfkill) {
2495 if (new_rfkill)
bc269a8e 2496 set_bit(S_RFKILL, &il->status);
4bc85c13 2497 else
bc269a8e 2498 clear_bit(S_RFKILL, &il->status);
4bc85c13 2499
46bc8d4b 2500 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
4bc85c13 2501
58de00a4 2502 D_RF_KILL("RF_KILL bit toggled to %s.\n",
e7392364 2503 new_rfkill ? "disable radio" : "enable radio");
4bc85c13
WYG
2504 }
2505
2506 /* Keep this running, even if radio now enabled. This will be
2507 * cancelled in mac_start() if system decides to start again */
46bc8d4b 2508 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2509 round_jiffies_relative(2 * HZ));
2510
2511}
2512
e7392364
SG
2513int
2514il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
4bc85c13 2515{
e2ebc833 2516 struct il_host_cmd cmd = {
4d69c752 2517 .id = C_SCAN,
e2ebc833 2518 .len = sizeof(struct il3945_scan_cmd),
4bc85c13
WYG
2519 .flags = CMD_SIZE_HUGE,
2520 };
e2ebc833 2521 struct il3945_scan_cmd *scan;
4bc85c13
WYG
2522 u8 n_probes = 0;
2523 enum ieee80211_band band;
2524 bool is_active = false;
2525 int ret;
dd6d2a8a 2526 u16 len;
4bc85c13 2527
46bc8d4b 2528 lockdep_assert_held(&il->mutex);
4bc85c13 2529
46bc8d4b 2530 if (!il->scan_cmd) {
e7392364
SG
2531 il->scan_cmd =
2532 kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2533 GFP_KERNEL);
46bc8d4b 2534 if (!il->scan_cmd) {
58de00a4 2535 D_SCAN("Fail to allocate scan memory\n");
4bc85c13
WYG
2536 return -ENOMEM;
2537 }
2538 }
46bc8d4b 2539 scan = il->scan_cmd;
e2ebc833 2540 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
4bc85c13 2541
e2ebc833
SG
2542 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2543 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
4bc85c13 2544
7c2cde2e 2545 if (il_is_associated(il)) {
dd6d2a8a 2546 u16 interval;
4bc85c13
WYG
2547 u32 extra;
2548 u32 suspend_time = 100;
2549 u32 scan_suspend_time = 100;
2550
58de00a4 2551 D_INFO("Scanning while associated...\n");
4bc85c13 2552
dd6d2a8a 2553 interval = vif->bss_conf.beacon_int;
4bc85c13
WYG
2554
2555 scan->suspend_time = 0;
2556 scan->max_out_time = cpu_to_le32(200 * 1024);
2557 if (!interval)
2558 interval = suspend_time;
2559 /*
2560 * suspend time format:
2561 * 0-19: beacon interval in usec (time before exec.)
2562 * 20-23: 0
2563 * 24-31: number of beacons (suspend between channels)
2564 */
2565
2566 extra = (suspend_time / interval) << 24;
e7392364
SG
2567 scan_suspend_time =
2568 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
4bc85c13
WYG
2569
2570 scan->suspend_time = cpu_to_le32(scan_suspend_time);
58de00a4 2571 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 2572 scan_suspend_time, interval);
4bc85c13
WYG
2573 }
2574
46bc8d4b 2575 if (il->scan_request->n_ssids) {
4bc85c13 2576 int i, p = 0;
58de00a4 2577 D_SCAN("Kicking off active scan\n");
46bc8d4b 2578 for (i = 0; i < il->scan_request->n_ssids; i++) {
4bc85c13 2579 /* always does wildcard anyway */
46bc8d4b 2580 if (!il->scan_request->ssids[i].ssid_len)
4bc85c13
WYG
2581 continue;
2582 scan->direct_scan[p].id = WLAN_EID_SSID;
2583 scan->direct_scan[p].len =
e7392364 2584 il->scan_request->ssids[i].ssid_len;
4bc85c13 2585 memcpy(scan->direct_scan[p].ssid,
46bc8d4b
SG
2586 il->scan_request->ssids[i].ssid,
2587 il->scan_request->ssids[i].ssid_len);
4bc85c13
WYG
2588 n_probes++;
2589 p++;
2590 }
2591 is_active = true;
2592 } else
58de00a4 2593 D_SCAN("Kicking off passive scan.\n");
4bc85c13
WYG
2594
2595 /* We don't build a direct scan probe request; the uCode will do
2596 * that based on the direct_mask added to each channel entry */
2597 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 2598 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
4bc85c13
WYG
2599 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2600
2601 /* flags + rate selection */
2602
46bc8d4b 2603 switch (il->scan_band) {
4bc85c13
WYG
2604 case IEEE80211_BAND_2GHZ:
2605 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2eb05816 2606 scan->tx_cmd.rate = RATE_1M_PLCP;
4bc85c13
WYG
2607 band = IEEE80211_BAND_2GHZ;
2608 break;
2609 case IEEE80211_BAND_5GHZ:
2eb05816 2610 scan->tx_cmd.rate = RATE_6M_PLCP;
4bc85c13
WYG
2611 band = IEEE80211_BAND_5GHZ;
2612 break;
2613 default:
9406f797 2614 IL_WARN("Invalid scan band\n");
4bc85c13
WYG
2615 return -EIO;
2616 }
2617
2618 /*
68acc4af
SG
2619 * If active scaning is requested but a certain channel is marked
2620 * passive, we can do active scanning if we detect transmissions. For
2621 * passive only scanning disable switching to active on any channel.
4bc85c13 2622 */
e7392364 2623 scan->good_CRC_th =
68acc4af 2624 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
e7392364
SG
2625
2626 len =
2627 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2628 vif->addr, il->scan_request->ie,
2629 il->scan_request->ie_len,
2630 IL_MAX_SCAN_SIZE - sizeof(*scan));
dd6d2a8a
SG
2631 scan->tx_cmd.len = cpu_to_le16(len);
2632
4bc85c13 2633 /* select Rx antennas */
46bc8d4b 2634 scan->flags |= il3945_get_antenna_flags(il);
4bc85c13 2635
e7392364
SG
2636 scan->channel_count =
2637 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2638 (void *)&scan->data[len], vif);
4bc85c13 2639 if (scan->channel_count == 0) {
58de00a4 2640 D_SCAN("channel count %d\n", scan->channel_count);
4bc85c13
WYG
2641 return -EIO;
2642 }
2643
e7392364
SG
2644 cmd.len +=
2645 le16_to_cpu(scan->tx_cmd.len) +
e2ebc833 2646 scan->channel_count * sizeof(struct il3945_scan_channel);
4bc85c13
WYG
2647 cmd.data = scan;
2648 scan->len = cpu_to_le16(cmd.len);
2649
a6766ccd 2650 set_bit(S_SCAN_HW, &il->status);
46bc8d4b 2651 ret = il_send_cmd_sync(il, &cmd);
4bc85c13 2652 if (ret)
a6766ccd 2653 clear_bit(S_SCAN_HW, &il->status);
4bc85c13
WYG
2654 return ret;
2655}
2656
e7392364
SG
2657void
2658il3945_post_scan(struct il_priv *il)
4bc85c13 2659{
4bc85c13
WYG
2660 /*
2661 * Since setting the RXON may have been deferred while
2662 * performing the scan, fire one off if needed
2663 */
c8b03958 2664 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
83007196 2665 il3945_commit_rxon(il);
4bc85c13
WYG
2666}
2667
e7392364
SG
2668static void
2669il3945_bg_restart(struct work_struct *data)
4bc85c13 2670{
46bc8d4b 2671 struct il_priv *il = container_of(data, struct il_priv, restart);
4bc85c13 2672
a6766ccd 2673 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2674 return;
2675
a6766ccd 2676 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 2677 mutex_lock(&il->mutex);
46bc8d4b
SG
2678 il->is_open = 0;
2679 mutex_unlock(&il->mutex);
2680 il3945_down(il);
2681 ieee80211_restart_hw(il->hw);
4bc85c13 2682 } else {
46bc8d4b 2683 il3945_down(il);
4bc85c13 2684
46bc8d4b 2685 mutex_lock(&il->mutex);
a6766ccd 2686 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 2687 mutex_unlock(&il->mutex);
4bc85c13 2688 return;
28a6e577 2689 }
4bc85c13 2690
46bc8d4b
SG
2691 __il3945_up(il);
2692 mutex_unlock(&il->mutex);
4bc85c13
WYG
2693 }
2694}
2695
e7392364
SG
2696static void
2697il3945_bg_rx_replenish(struct work_struct *data)
4bc85c13 2698{
e7392364 2699 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
4bc85c13 2700
46bc8d4b 2701 mutex_lock(&il->mutex);
a6766ccd 2702 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 2703 goto out;
4bc85c13 2704
46bc8d4b 2705 il3945_rx_replenish(il);
28a6e577 2706out:
46bc8d4b 2707 mutex_unlock(&il->mutex);
4bc85c13
WYG
2708}
2709
e7392364
SG
2710void
2711il3945_post_associate(struct il_priv *il)
4bc85c13
WYG
2712{
2713 int rc = 0;
2714 struct ieee80211_conf *conf = NULL;
4bc85c13 2715
83007196 2716 if (!il->vif || !il->is_open)
4bc85c13
WYG
2717 return;
2718
83007196 2719 D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
c8b03958 2720 il->active.bssid_addr);
4bc85c13 2721
a6766ccd 2722 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2723 return;
2724
46bc8d4b 2725 il_scan_cancel_timeout(il, 200);
4bc85c13 2726
6278ddab 2727 conf = &il->hw->conf;
4bc85c13 2728
c8b03958 2729 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 2730 il3945_commit_rxon(il);
4bc85c13 2731
83007196 2732 rc = il_send_rxon_timing(il);
4bc85c13 2733 if (rc)
e7392364 2734 IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
4bc85c13 2735
c8b03958 2736 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
4bc85c13 2737
83007196 2738 il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
4bc85c13 2739
83007196
SG
2740 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2741 il->vif->bss_conf.beacon_int);
4bc85c13 2742
83007196 2743 if (il->vif->bss_conf.use_short_preamble)
c8b03958 2744 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2745 else
c8b03958 2746 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2747
c8b03958 2748 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
83007196 2749 if (il->vif->bss_conf.use_short_slot)
c8b03958 2750 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
4bc85c13 2751 else
c8b03958 2752 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
4bc85c13
WYG
2753 }
2754
83007196 2755 il3945_commit_rxon(il);
4bc85c13 2756
83007196 2757 switch (il->vif->type) {
4bc85c13 2758 case NL80211_IFTYPE_STATION:
46bc8d4b 2759 il3945_rate_scale_init(il->hw, IL_AP_ID);
4bc85c13
WYG
2760 break;
2761 case NL80211_IFTYPE_ADHOC:
46bc8d4b 2762 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2763 break;
2764 default:
e7392364 2765 IL_ERR("%s Should not be called in %d mode\n", __func__,
83007196 2766 il->vif->type);
4bc85c13
WYG
2767 break;
2768 }
2769}
2770
2771/*****************************************************************************
2772 *
2773 * mac80211 entry point functions
2774 *
2775 *****************************************************************************/
2776
2777#define UCODE_READY_TIMEOUT (2 * HZ)
2778
e7392364
SG
2779static int
2780il3945_mac_start(struct ieee80211_hw *hw)
4bc85c13 2781{
46bc8d4b 2782 struct il_priv *il = hw->priv;
4bc85c13
WYG
2783 int ret;
2784
4bc85c13 2785 /* we should be verifying the device is ready to be opened */
46bc8d4b 2786 mutex_lock(&il->mutex);
9ce7b73c 2787 D_MAC80211("enter\n");
4bc85c13
WYG
2788
2789 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2790 * ucode filename and max sizes are card-specific. */
2791
46bc8d4b
SG
2792 if (!il->ucode_code.len) {
2793 ret = il3945_read_ucode(il);
4bc85c13 2794 if (ret) {
9406f797 2795 IL_ERR("Could not read microcode: %d\n", ret);
46bc8d4b 2796 mutex_unlock(&il->mutex);
4bc85c13
WYG
2797 goto out_release_irq;
2798 }
2799 }
2800
46bc8d4b 2801 ret = __il3945_up(il);
4bc85c13 2802
46bc8d4b 2803 mutex_unlock(&il->mutex);
4bc85c13
WYG
2804
2805 if (ret)
2806 goto out_release_irq;
2807
58de00a4 2808 D_INFO("Start UP work.\n");
4bc85c13
WYG
2809
2810 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
2811 * mac80211 will not be run successfully. */
46bc8d4b 2812 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG
2813 test_bit(S_READY, &il->status),
2814 UCODE_READY_TIMEOUT);
4bc85c13 2815 if (!ret) {
a6766ccd 2816 if (!test_bit(S_READY, &il->status)) {
e7392364
SG
2817 IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2818 jiffies_to_msecs(UCODE_READY_TIMEOUT));
4bc85c13
WYG
2819 ret = -ETIMEDOUT;
2820 goto out_release_irq;
2821 }
2822 }
2823
2824 /* ucode is running and will send rfkill notifications,
2825 * no need to poll the killswitch state anymore */
46bc8d4b 2826 cancel_delayed_work(&il->_3945.rfkill_poll);
4bc85c13 2827
46bc8d4b 2828 il->is_open = 1;
58de00a4 2829 D_MAC80211("leave\n");
4bc85c13
WYG
2830 return 0;
2831
2832out_release_irq:
46bc8d4b 2833 il->is_open = 0;
58de00a4 2834 D_MAC80211("leave - failed\n");
4bc85c13
WYG
2835 return ret;
2836}
2837
e7392364
SG
2838static void
2839il3945_mac_stop(struct ieee80211_hw *hw)
4bc85c13 2840{
46bc8d4b 2841 struct il_priv *il = hw->priv;
4bc85c13 2842
58de00a4 2843 D_MAC80211("enter\n");
4bc85c13 2844
46bc8d4b 2845 if (!il->is_open) {
58de00a4 2846 D_MAC80211("leave - skip\n");
4bc85c13
WYG
2847 return;
2848 }
2849
46bc8d4b 2850 il->is_open = 0;
4bc85c13 2851
46bc8d4b 2852 il3945_down(il);
4bc85c13 2853
46bc8d4b 2854 flush_workqueue(il->workqueue);
4bc85c13
WYG
2855
2856 /* start polling the killswitch state again */
46bc8d4b 2857 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2858 round_jiffies_relative(2 * HZ));
2859
58de00a4 2860 D_MAC80211("leave\n");
4bc85c13
WYG
2861}
2862
e7392364 2863static void
36323f81
TH
2864il3945_mac_tx(struct ieee80211_hw *hw,
2865 struct ieee80211_tx_control *control,
2866 struct sk_buff *skb)
4bc85c13 2867{
46bc8d4b 2868 struct il_priv *il = hw->priv;
4bc85c13 2869
58de00a4 2870 D_MAC80211("enter\n");
4bc85c13 2871
58de00a4 2872 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 2873 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
4bc85c13 2874
36323f81 2875 if (il3945_tx_skb(il, control->sta, skb))
4bc85c13
WYG
2876 dev_kfree_skb_any(skb);
2877
58de00a4 2878 D_MAC80211("leave\n");
4bc85c13
WYG
2879}
2880
e7392364
SG
2881void
2882il3945_config_ap(struct il_priv *il)
4bc85c13 2883{
83007196 2884 struct ieee80211_vif *vif = il->vif;
4bc85c13
WYG
2885 int rc = 0;
2886
a6766ccd 2887 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2888 return;
2889
2890 /* The following should be done only at AP bring up */
7c2cde2e 2891 if (!(il_is_associated(il))) {
4bc85c13
WYG
2892
2893 /* RXON - unassoc (to set timing command) */
c8b03958 2894 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 2895 il3945_commit_rxon(il);
4bc85c13
WYG
2896
2897 /* RXON Timing */
83007196 2898 rc = il_send_rxon_timing(il);
4bc85c13 2899 if (rc)
4d69c752 2900 IL_WARN("C_RXON_TIMING failed - "
e7392364 2901 "Attempting to continue.\n");
4bc85c13 2902
c8b03958 2903 il->staging.assoc_id = 0;
4bc85c13
WYG
2904
2905 if (vif->bss_conf.use_short_preamble)
c8b03958 2906 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2907 else
c8b03958 2908 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2909
c8b03958 2910 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
4bc85c13 2911 if (vif->bss_conf.use_short_slot)
c8b03958 2912 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
4bc85c13 2913 else
c8b03958 2914 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
4bc85c13
WYG
2915 }
2916 /* restore RXON assoc */
c8b03958 2917 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
83007196 2918 il3945_commit_rxon(il);
4bc85c13 2919 }
46bc8d4b 2920 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2921}
2922
e7392364
SG
2923static int
2924il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2925 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2926 struct ieee80211_key_conf *key)
4bc85c13 2927{
46bc8d4b 2928 struct il_priv *il = hw->priv;
4bc85c13 2929 int ret = 0;
e2ebc833 2930 u8 sta_id = IL_INVALID_STATION;
4bc85c13
WYG
2931 u8 static_key;
2932
58de00a4 2933 D_MAC80211("enter\n");
4bc85c13 2934
e2ebc833 2935 if (il3945_mod_params.sw_crypto) {
58de00a4 2936 D_MAC80211("leave - hwcrypto disabled\n");
4bc85c13
WYG
2937 return -EOPNOTSUPP;
2938 }
2939
2940 /*
2941 * To support IBSS RSN, don't program group keys in IBSS, the
2942 * hardware will then not attempt to decrypt the frames.
2943 */
2944 if (vif->type == NL80211_IFTYPE_ADHOC &&
9ce7b73c
SG
2945 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2946 D_MAC80211("leave - IBSS RSN\n");
4bc85c13 2947 return -EOPNOTSUPP;
9ce7b73c 2948 }
4bc85c13 2949
7c2cde2e 2950 static_key = !il_is_associated(il);
4bc85c13
WYG
2951
2952 if (!static_key) {
83007196 2953 sta_id = il_sta_id_or_broadcast(il, sta);
9ce7b73c
SG
2954 if (sta_id == IL_INVALID_STATION) {
2955 D_MAC80211("leave - station not found\n");
4bc85c13 2956 return -EINVAL;
9ce7b73c 2957 }
4bc85c13
WYG
2958 }
2959
46bc8d4b
SG
2960 mutex_lock(&il->mutex);
2961 il_scan_cancel_timeout(il, 100);
4bc85c13
WYG
2962
2963 switch (cmd) {
2964 case SET_KEY:
2965 if (static_key)
46bc8d4b 2966 ret = il3945_set_static_key(il, key);
4bc85c13 2967 else
46bc8d4b 2968 ret = il3945_set_dynamic_key(il, key, sta_id);
58de00a4 2969 D_MAC80211("enable hwcrypto key\n");
4bc85c13
WYG
2970 break;
2971 case DISABLE_KEY:
2972 if (static_key)
46bc8d4b 2973 ret = il3945_remove_static_key(il);
4bc85c13 2974 else
46bc8d4b 2975 ret = il3945_clear_sta_key_info(il, sta_id);
58de00a4 2976 D_MAC80211("disable hwcrypto key\n");
4bc85c13
WYG
2977 break;
2978 default:
2979 ret = -EINVAL;
2980 }
2981
9ce7b73c 2982 D_MAC80211("leave ret %d\n", ret);
46bc8d4b 2983 mutex_unlock(&il->mutex);
4bc85c13
WYG
2984
2985 return ret;
2986}
2987
e7392364
SG
2988static int
2989il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2990 struct ieee80211_sta *sta)
4bc85c13 2991{
46bc8d4b 2992 struct il_priv *il = hw->priv;
e2ebc833 2993 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
4bc85c13
WYG
2994 int ret;
2995 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2996 u8 sta_id;
2997
46bc8d4b 2998 mutex_lock(&il->mutex);
9ce7b73c 2999 D_INFO("station %pM\n", sta->addr);
e2ebc833 3000 sta_priv->common.sta_id = IL_INVALID_STATION;
4bc85c13 3001
83007196 3002 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
4bc85c13 3003 if (ret) {
e7392364 3004 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
4bc85c13 3005 /* Should we return success if return code is EEXIST ? */
46bc8d4b 3006 mutex_unlock(&il->mutex);
4bc85c13
WYG
3007 return ret;
3008 }
3009
3010 sta_priv->common.sta_id = sta_id;
3011
3012 /* Initialize rate scaling */
e7392364 3013 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG
3014 il3945_rs_rate_init(il, sta, sta_id);
3015 mutex_unlock(&il->mutex);
4bc85c13
WYG
3016
3017 return 0;
3018}
3019
e7392364
SG
3020static void
3021il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3022 unsigned int *total_flags, u64 multicast)
4bc85c13 3023{
46bc8d4b 3024 struct il_priv *il = hw->priv;
4bc85c13 3025 __le32 filter_or = 0, filter_nand = 0;
4bc85c13
WYG
3026
3027#define CHK(test, flag) do { \
3028 if (*total_flags & (test)) \
3029 filter_or |= (flag); \
3030 else \
3031 filter_nand |= (flag); \
3032 } while (0)
3033
e7392364
SG
3034 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3035 *total_flags);
4bc85c13
WYG
3036
3037 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3038 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3039 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3040
3041#undef CHK
3042
46bc8d4b 3043 mutex_lock(&il->mutex);
4bc85c13 3044
c8b03958
SG
3045 il->staging.filter_flags &= ~filter_nand;
3046 il->staging.filter_flags |= filter_or;
4bc85c13
WYG
3047
3048 /*
3049 * Not committing directly because hardware can perform a scan,
3050 * but even if hw is ready, committing here breaks for some reason,
3051 * we'll eventually commit the filter flags change anyway.
3052 */
3053
46bc8d4b 3054 mutex_unlock(&il->mutex);
4bc85c13
WYG
3055
3056 /*
3057 * Receiving all multicast frames is always enabled by the
e2ebc833 3058 * default flags setup in il_connection_init_rx_config()
4bc85c13
WYG
3059 * since we currently do not support programming multicast
3060 * filters into the device.
3061 */
e7392364
SG
3062 *total_flags &=
3063 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3064 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4bc85c13
WYG
3065}
3066
4bc85c13
WYG
3067/*****************************************************************************
3068 *
3069 * sysfs attributes
3070 *
3071 *****************************************************************************/
3072
d3175167 3073#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3074
3075/*
3076 * The following adds a new attribute to the sysfs representation
3077 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3078 * used for controlling the debug level.
3079 *
3080 * See the level definitions in iwl for details.
3081 *
3082 * The debug_level being managed using sysfs below is a per device debug
3083 * level that is used instead of the global debug level if it (the per
3084 * device debug level) is set.
3085 */
e7392364
SG
3086static ssize_t
3087il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3088 char *buf)
4bc85c13 3089{
46bc8d4b
SG
3090 struct il_priv *il = dev_get_drvdata(d);
3091 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4bc85c13 3092}
e7392364
SG
3093
3094static ssize_t
3095il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3096 const char *buf, size_t count)
4bc85c13 3097{
46bc8d4b 3098 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3099 unsigned long val;
3100 int ret;
3101
3102 ret = strict_strtoul(buf, 0, &val);
3103 if (ret)
9406f797 3104 IL_INFO("%s is not in hex or decimal form.\n", buf);
288f9954 3105 else
46bc8d4b 3106 il->debug_level = val;
288f9954 3107
4bc85c13
WYG
3108 return strnlen(buf, count);
3109}
3110
e7392364
SG
3111static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il3945_show_debug_level,
3112 il3945_store_debug_level);
4bc85c13 3113
d3175167 3114#endif /* CONFIG_IWLEGACY_DEBUG */
4bc85c13 3115
e7392364
SG
3116static ssize_t
3117il3945_show_temperature(struct device *d, struct device_attribute *attr,
3118 char *buf)
4bc85c13 3119{
46bc8d4b 3120 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3121
46bc8d4b 3122 if (!il_is_alive(il))
4bc85c13
WYG
3123 return -EAGAIN;
3124
46bc8d4b 3125 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
4bc85c13
WYG
3126}
3127
e2ebc833 3128static DEVICE_ATTR(temperature, S_IRUGO, il3945_show_temperature, NULL);
4bc85c13 3129
e7392364
SG
3130static ssize_t
3131il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3132{
46bc8d4b
SG
3133 struct il_priv *il = dev_get_drvdata(d);
3134 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4bc85c13
WYG
3135}
3136
e7392364
SG
3137static ssize_t
3138il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3139 const char *buf, size_t count)
4bc85c13 3140{
46bc8d4b 3141 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3142 char *p = (char *)buf;
3143 u32 val;
3144
3145 val = simple_strtoul(p, &p, 10);
3146 if (p == buf)
9406f797 3147 IL_INFO(": %s is not in decimal form.\n", buf);
4bc85c13 3148 else
46bc8d4b 3149 il3945_hw_reg_set_txpower(il, val);
4bc85c13
WYG
3150
3151 return count;
3152}
3153
e7392364
SG
3154static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il3945_show_tx_power,
3155 il3945_store_tx_power);
4bc85c13 3156
e7392364
SG
3157static ssize_t
3158il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3159{
46bc8d4b 3160 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3161
c8b03958 3162 return sprintf(buf, "0x%04X\n", il->active.flags);
4bc85c13
WYG
3163}
3164
e7392364
SG
3165static ssize_t
3166il3945_store_flags(struct device *d, struct device_attribute *attr,
3167 const char *buf, size_t count)
4bc85c13 3168{
46bc8d4b 3169 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3170 u32 flags = simple_strtoul(buf, NULL, 0);
4bc85c13 3171
46bc8d4b 3172 mutex_lock(&il->mutex);
c8b03958 3173 if (le32_to_cpu(il->staging.flags) != flags) {
4bc85c13 3174 /* Cancel any currently running scans... */
46bc8d4b 3175 if (il_scan_cancel_timeout(il, 100))
9406f797 3176 IL_WARN("Could not cancel scan.\n");
4bc85c13 3177 else {
e7392364 3178 D_INFO("Committing rxon.flags = 0x%04X\n", flags);
c8b03958 3179 il->staging.flags = cpu_to_le32(flags);
83007196 3180 il3945_commit_rxon(il);
4bc85c13
WYG
3181 }
3182 }
46bc8d4b 3183 mutex_unlock(&il->mutex);
4bc85c13
WYG
3184
3185 return count;
3186}
3187
e7392364
SG
3188static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, il3945_show_flags,
3189 il3945_store_flags);
4bc85c13 3190
e7392364
SG
3191static ssize_t
3192il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3193 char *buf)
4bc85c13 3194{
46bc8d4b 3195 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3196
c8b03958 3197 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
4bc85c13
WYG
3198}
3199
e7392364
SG
3200static ssize_t
3201il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3202 const char *buf, size_t count)
4bc85c13 3203{
46bc8d4b 3204 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3205 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3206
46bc8d4b 3207 mutex_lock(&il->mutex);
c8b03958 3208 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
4bc85c13 3209 /* Cancel any currently running scans... */
46bc8d4b 3210 if (il_scan_cancel_timeout(il, 100))
9406f797 3211 IL_WARN("Could not cancel scan.\n");
4bc85c13 3212 else {
e7392364
SG
3213 D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3214 filter_flags);
c8b03958 3215 il->staging.filter_flags = cpu_to_le32(filter_flags);
83007196 3216 il3945_commit_rxon(il);
4bc85c13
WYG
3217 }
3218 }
46bc8d4b 3219 mutex_unlock(&il->mutex);
4bc85c13
WYG
3220
3221 return count;
3222}
3223
e2ebc833
SG
3224static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, il3945_show_filter_flags,
3225 il3945_store_filter_flags);
4bc85c13 3226
e7392364
SG
3227static ssize_t
3228il3945_show_measurement(struct device *d, struct device_attribute *attr,
3229 char *buf)
4bc85c13 3230{
46bc8d4b 3231 struct il_priv *il = dev_get_drvdata(d);
e2ebc833 3232 struct il_spectrum_notification measure_report;
4bc85c13 3233 u32 size = sizeof(measure_report), len = 0, ofs = 0;
1722f8e1 3234 u8 *data = (u8 *) &measure_report;
4bc85c13
WYG
3235 unsigned long flags;
3236
46bc8d4b
SG
3237 spin_lock_irqsave(&il->lock, flags);
3238 if (!(il->measurement_status & MEASUREMENT_READY)) {
3239 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
3240 return 0;
3241 }
46bc8d4b
SG
3242 memcpy(&measure_report, &il->measure_report, size);
3243 il->measurement_status = 0;
3244 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3245
232913b5 3246 while (size && PAGE_SIZE - len) {
4bc85c13
WYG
3247 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3248 PAGE_SIZE - len, 1);
3249 len = strlen(buf);
3250 if (PAGE_SIZE - len)
3251 buf[len++] = '\n';
3252
3253 ofs += 16;
3254 size -= min(size, 16U);
3255 }
3256
3257 return len;
3258}
3259
e7392364
SG
3260static ssize_t
3261il3945_store_measurement(struct device *d, struct device_attribute *attr,
3262 const char *buf, size_t count)
4bc85c13 3263{
46bc8d4b 3264 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3265 struct ieee80211_measurement_params params = {
c8b03958 3266 .channel = le16_to_cpu(il->active.channel),
46bc8d4b 3267 .start_time = cpu_to_le64(il->_3945.last_tsf),
4bc85c13
WYG
3268 .duration = cpu_to_le16(1),
3269 };
e2ebc833 3270 u8 type = IL_MEASURE_BASIC;
4bc85c13
WYG
3271 u8 buffer[32];
3272 u8 channel;
3273
3274 if (count) {
3275 char *p = buffer;
3276 strncpy(buffer, buf, min(sizeof(buffer), count));
3277 channel = simple_strtoul(p, NULL, 0);
3278 if (channel)
3279 params.channel = channel;
3280
3281 p = buffer;
3282 while (*p && *p != ' ')
3283 p++;
3284 if (*p)
3285 type = simple_strtoul(p + 1, NULL, 0);
3286 }
3287
e7392364
SG
3288 D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3289 type, params.channel, buf);
46bc8d4b 3290 il3945_get_measurement(il, &params, type);
4bc85c13
WYG
3291
3292 return count;
3293}
3294
e7392364
SG
3295static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, il3945_show_measurement,
3296 il3945_store_measurement);
4bc85c13 3297
e7392364
SG
3298static ssize_t
3299il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3300 const char *buf, size_t count)
4bc85c13 3301{
46bc8d4b 3302 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3303
46bc8d4b
SG
3304 il->retry_rate = simple_strtoul(buf, NULL, 0);
3305 if (il->retry_rate <= 0)
3306 il->retry_rate = 1;
4bc85c13
WYG
3307
3308 return count;
3309}
3310
e7392364
SG
3311static ssize_t
3312il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3313 char *buf)
4bc85c13 3314{
46bc8d4b
SG
3315 struct il_priv *il = dev_get_drvdata(d);
3316 return sprintf(buf, "%d", il->retry_rate);
4bc85c13
WYG
3317}
3318
e2ebc833
SG
3319static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, il3945_show_retry_rate,
3320 il3945_store_retry_rate);
4bc85c13 3321
e7392364
SG
3322static ssize_t
3323il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13
WYG
3324{
3325 /* all this shit doesn't belong into sysfs anyway */
3326 return 0;
3327}
3328
e2ebc833 3329static DEVICE_ATTR(channels, S_IRUSR, il3945_show_channels, NULL);
4bc85c13 3330
e7392364
SG
3331static ssize_t
3332il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3333{
46bc8d4b 3334 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3335
46bc8d4b 3336 if (!il_is_alive(il))
4bc85c13
WYG
3337 return -EAGAIN;
3338
e2ebc833 3339 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
4bc85c13
WYG
3340}
3341
e7392364
SG
3342static ssize_t
3343il3945_store_antenna(struct device *d, struct device_attribute *attr,
3344 const char *buf, size_t count)
4bc85c13 3345{
46bc8d4b 3346 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
4bc85c13
WYG
3347 int ant;
3348
3349 if (count == 0)
3350 return 0;
3351
3352 if (sscanf(buf, "%1i", &ant) != 1) {
58de00a4 3353 D_INFO("not in hex or decimal form.\n");
4bc85c13
WYG
3354 return count;
3355 }
3356
232913b5 3357 if (ant >= 0 && ant <= 2) {
58de00a4 3358 D_INFO("Setting antenna select to %d.\n", ant);
e2ebc833 3359 il3945_mod_params.antenna = (enum il3945_antenna)ant;
4bc85c13 3360 } else
58de00a4 3361 D_INFO("Bad antenna select value %d.\n", ant);
4bc85c13 3362
4bc85c13
WYG
3363 return count;
3364}
3365
e7392364
SG
3366static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, il3945_show_antenna,
3367 il3945_store_antenna);
4bc85c13 3368
e7392364
SG
3369static ssize_t
3370il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3371{
46bc8d4b
SG
3372 struct il_priv *il = dev_get_drvdata(d);
3373 if (!il_is_alive(il))
4bc85c13 3374 return -EAGAIN;
46bc8d4b 3375 return sprintf(buf, "0x%08x\n", (int)il->status);
4bc85c13
WYG
3376}
3377
e2ebc833 3378static DEVICE_ATTR(status, S_IRUGO, il3945_show_status, NULL);
4bc85c13 3379
e7392364
SG
3380static ssize_t
3381il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3382 const char *buf, size_t count)
4bc85c13 3383{
46bc8d4b 3384 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3385 char *p = (char *)buf;
3386
3387 if (p[0] == '1')
46bc8d4b 3388 il3945_dump_nic_error_log(il);
4bc85c13
WYG
3389
3390 return strnlen(buf, count);
3391}
3392
e2ebc833 3393static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, il3945_dump_error_log);
4bc85c13
WYG
3394
3395/*****************************************************************************
3396 *
3397 * driver setup and tear down
3398 *
3399 *****************************************************************************/
3400
e7392364
SG
3401static void
3402il3945_setup_deferred_work(struct il_priv *il)
4bc85c13 3403{
46bc8d4b 3404 il->workqueue = create_singlethread_workqueue(DRV_NAME);
4bc85c13 3405
46bc8d4b 3406 init_waitqueue_head(&il->wait_command_queue);
4bc85c13 3407
46bc8d4b
SG
3408 INIT_WORK(&il->restart, il3945_bg_restart);
3409 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3410 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3411 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3412 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
4bc85c13 3413
46bc8d4b 3414 il_setup_scan_deferred_work(il);
4bc85c13 3415
46bc8d4b 3416 il3945_hw_setup_deferred_work(il);
4bc85c13 3417
46bc8d4b
SG
3418 init_timer(&il->watchdog);
3419 il->watchdog.data = (unsigned long)il;
3420 il->watchdog.function = il_bg_watchdog;
4bc85c13 3421
e7392364
SG
3422 tasklet_init(&il->irq_tasklet,
3423 (void (*)(unsigned long))il3945_irq_tasklet,
3424 (unsigned long)il);
4bc85c13
WYG
3425}
3426
e7392364
SG
3427static void
3428il3945_cancel_deferred_work(struct il_priv *il)
4bc85c13 3429{
46bc8d4b 3430 il3945_hw_cancel_deferred_work(il);
4bc85c13 3431
46bc8d4b
SG
3432 cancel_delayed_work_sync(&il->init_alive_start);
3433 cancel_delayed_work(&il->alive_start);
4bc85c13 3434
46bc8d4b 3435 il_cancel_scan_deferred_work(il);
4bc85c13
WYG
3436}
3437
e2ebc833 3438static struct attribute *il3945_sysfs_entries[] = {
4bc85c13
WYG
3439 &dev_attr_antenna.attr,
3440 &dev_attr_channels.attr,
3441 &dev_attr_dump_errors.attr,
3442 &dev_attr_flags.attr,
3443 &dev_attr_filter_flags.attr,
3444 &dev_attr_measurement.attr,
3445 &dev_attr_retry_rate.attr,
3446 &dev_attr_status.attr,
3447 &dev_attr_temperature.attr,
3448 &dev_attr_tx_power.attr,
d3175167 3449#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3450 &dev_attr_debug_level.attr,
3451#endif
3452 NULL
3453};
3454
e2ebc833 3455static struct attribute_group il3945_attribute_group = {
4bc85c13 3456 .name = NULL, /* put in device directory */
e2ebc833 3457 .attrs = il3945_sysfs_entries,
4bc85c13
WYG
3458};
3459
c39ae9fd 3460struct ieee80211_ops il3945_mac_ops = {
e2ebc833
SG
3461 .tx = il3945_mac_tx,
3462 .start = il3945_mac_start,
3463 .stop = il3945_mac_stop,
3464 .add_interface = il_mac_add_interface,
3465 .remove_interface = il_mac_remove_interface,
3466 .change_interface = il_mac_change_interface,
3467 .config = il_mac_config,
3468 .configure_filter = il3945_configure_filter,
3469 .set_key = il3945_mac_set_key,
3470 .conf_tx = il_mac_conf_tx,
3471 .reset_tsf = il_mac_reset_tsf,
3472 .bss_info_changed = il_mac_bss_info_changed,
3473 .hw_scan = il_mac_hw_scan,
3474 .sta_add = il3945_mac_sta_add,
3475 .sta_remove = il_mac_sta_remove,
3476 .tx_last_beacon = il_mac_tx_last_beacon,
4bc85c13
WYG
3477};
3478
e7392364
SG
3479static int
3480il3945_init_drv(struct il_priv *il)
4bc85c13
WYG
3481{
3482 int ret;
46bc8d4b 3483 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 3484
46bc8d4b
SG
3485 il->retry_rate = 1;
3486 il->beacon_skb = NULL;
4bc85c13 3487
46bc8d4b
SG
3488 spin_lock_init(&il->sta_lock);
3489 spin_lock_init(&il->hcmd_lock);
4bc85c13 3490
46bc8d4b 3491 INIT_LIST_HEAD(&il->free_frames);
4bc85c13 3492
46bc8d4b 3493 mutex_init(&il->mutex);
4bc85c13 3494
46bc8d4b
SG
3495 il->ieee_channels = NULL;
3496 il->ieee_rates = NULL;
3497 il->band = IEEE80211_BAND_2GHZ;
4bc85c13 3498
46bc8d4b
SG
3499 il->iw_mode = NL80211_IFTYPE_STATION;
3500 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
4bc85c13
WYG
3501
3502 /* initialize force reset */
46bc8d4b 3503 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
4bc85c13 3504
4bc85c13 3505 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
9406f797 3506 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
e7392364 3507 eeprom->version);
4bc85c13
WYG
3508 ret = -EINVAL;
3509 goto err;
3510 }
46bc8d4b 3511 ret = il_init_channel_map(il);
4bc85c13 3512 if (ret) {
9406f797 3513 IL_ERR("initializing regulatory failed: %d\n", ret);
4bc85c13
WYG
3514 goto err;
3515 }
3516
3517 /* Set up txpower settings in driver for all channels */
46bc8d4b 3518 if (il3945_txpower_set_from_eeprom(il)) {
4bc85c13
WYG
3519 ret = -EIO;
3520 goto err_free_channel_map;
3521 }
3522
46bc8d4b 3523 ret = il_init_geos(il);
4bc85c13 3524 if (ret) {
9406f797 3525 IL_ERR("initializing geos failed: %d\n", ret);
4bc85c13
WYG
3526 goto err_free_channel_map;
3527 }
46bc8d4b 3528 il3945_init_hw_rates(il, il->ieee_rates);
4bc85c13
WYG
3529
3530 return 0;
3531
3532err_free_channel_map:
46bc8d4b 3533 il_free_channel_map(il);
4bc85c13
WYG
3534err:
3535 return ret;
3536}
3537
d3175167 3538#define IL3945_MAX_PROBE_REQUEST 200
4bc85c13 3539
e7392364
SG
3540static int
3541il3945_setup_mac(struct il_priv *il)
4bc85c13
WYG
3542{
3543 int ret;
46bc8d4b 3544 struct ieee80211_hw *hw = il->hw;
4bc85c13
WYG
3545
3546 hw->rate_control_algorithm = "iwl-3945-rs";
e2ebc833
SG
3547 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3548 hw->vif_data_size = sizeof(struct il_vif_priv);
4bc85c13
WYG
3549
3550 /* Tell mac80211 our characteristics */
e7392364 3551 hw->flags = IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_SPECTRUM_MGMT;
4bc85c13 3552
8c9c48d5
SG
3553 hw->wiphy->interface_modes =
3554 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
4bc85c13 3555
e7392364
SG
3556 hw->wiphy->flags |=
3557 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS |
3558 WIPHY_FLAG_IBSS_RSN;
4bc85c13
WYG
3559
3560 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3561 /* we create the 802.11 header and a zero-length SSID element */
d3175167 3562 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
4bc85c13
WYG
3563
3564 /* Default value; 4 EDCA QOS priorities */
3565 hw->queues = 4;
3566
46bc8d4b
SG
3567 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
3568 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 3569 &il->bands[IEEE80211_BAND_2GHZ];
4bc85c13 3570
46bc8d4b
SG
3571 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
3572 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 3573 &il->bands[IEEE80211_BAND_5GHZ];
4bc85c13 3574
46bc8d4b 3575 il_leds_init(il);
4bc85c13 3576
46bc8d4b 3577 ret = ieee80211_register_hw(il->hw);
4bc85c13 3578 if (ret) {
9406f797 3579 IL_ERR("Failed to register hw (error %d)\n", ret);
4bc85c13
WYG
3580 return ret;
3581 }
46bc8d4b 3582 il->mac80211_registered = 1;
4bc85c13
WYG
3583
3584 return 0;
3585}
3586
e7392364
SG
3587static int
3588il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4bc85c13 3589{
7c2cde2e 3590 int err = 0;
46bc8d4b 3591 struct il_priv *il;
4bc85c13 3592 struct ieee80211_hw *hw;
e2ebc833
SG
3593 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3594 struct il3945_eeprom *eeprom;
4bc85c13
WYG
3595 unsigned long flags;
3596
3597 /***********************
3598 * 1. Allocating HW data
3599 * ********************/
3600
c39ae9fd
SG
3601 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3602 if (!hw) {
4bc85c13
WYG
3603 err = -ENOMEM;
3604 goto out;
3605 }
46bc8d4b 3606 il = hw->priv;
c39ae9fd 3607 il->hw = hw;
4bc85c13
WYG
3608 SET_IEEE80211_DEV(hw, &pdev->dev);
3609
d3175167 3610 il->cmd_queue = IL39_CMD_QUEUE_NUM;
4bc85c13 3611
4bc85c13
WYG
3612 /*
3613 * Disabling hardware scan means that mac80211 will perform scans
3614 * "the hard way", rather than using device's scan.
3615 */
e2ebc833 3616 if (il3945_mod_params.disable_hw_scan) {
58de00a4 3617 D_INFO("Disabling hw_scan\n");
c39ae9fd 3618 il3945_mac_ops.hw_scan = NULL;
4bc85c13
WYG
3619 }
3620
58de00a4 3621 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 3622 il->cfg = cfg;
c39ae9fd 3623 il->ops = &il3945_ops;
93b7654e
SG
3624#ifdef CONFIG_IWLEGACY_DEBUGFS
3625 il->debugfs_ops = &il3945_debugfs_ops;
3626#endif
46bc8d4b
SG
3627 il->pci_dev = pdev;
3628 il->inta_mask = CSR_INI_SET_MASK;
4bc85c13 3629
4bc85c13
WYG
3630 /***************************
3631 * 2. Initializing PCI bus
3632 * *************************/
e7392364
SG
3633 pci_disable_link_state(pdev,
3634 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3635 PCIE_LINK_STATE_CLKPM);
4bc85c13
WYG
3636
3637 if (pci_enable_device(pdev)) {
3638 err = -ENODEV;
3639 goto out_ieee80211_free_hw;
3640 }
3641
3642 pci_set_master(pdev);
3643
3644 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3645 if (!err)
3646 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3647 if (err) {
9406f797 3648 IL_WARN("No suitable DMA available.\n");
4bc85c13
WYG
3649 goto out_pci_disable_device;
3650 }
3651
46bc8d4b 3652 pci_set_drvdata(pdev, il);
4bc85c13
WYG
3653 err = pci_request_regions(pdev, DRV_NAME);
3654 if (err)
3655 goto out_pci_disable_device;
3656
3657 /***********************
3658 * 3. Read REV Register
3659 * ********************/
a5f16137 3660 il->hw_base = pci_ioremap_bar(pdev, 0);
46bc8d4b 3661 if (!il->hw_base) {
4bc85c13
WYG
3662 err = -ENODEV;
3663 goto out_pci_release_regions;
3664 }
3665
58de00a4 3666 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 3667 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 3668 D_INFO("pci_resource_base = %p\n", il->hw_base);
4bc85c13
WYG
3669
3670 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3671 * PCI Tx retries from interfering with C3 CPU state */
3672 pci_write_config_byte(pdev, 0x41, 0x00);
3673
f03ee2a8 3674 /* these spin locks will be used in apm_init and EEPROM access
4bc85c13
WYG
3675 * we should init now
3676 */
46bc8d4b
SG
3677 spin_lock_init(&il->reg_lock);
3678 spin_lock_init(&il->lock);
4bc85c13
WYG
3679
3680 /*
3681 * stop and reset the on-board processor just in case it is in a
3682 * strange state ... like being left stranded by a primary kernel
3683 * and this is now the kdump kernel trying to start up
3684 */
841b2cca 3685 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
3686
3687 /***********************
3688 * 4. Read EEPROM
3689 * ********************/
3690
3691 /* Read the EEPROM */
46bc8d4b 3692 err = il_eeprom_init(il);
4bc85c13 3693 if (err) {
9406f797 3694 IL_ERR("Unable to init EEPROM\n");
4bc85c13
WYG
3695 goto out_iounmap;
3696 }
3697 /* MAC Address location in EEPROM same for 3945/4965 */
46bc8d4b 3698 eeprom = (struct il3945_eeprom *)il->eeprom;
58de00a4 3699 D_INFO("MAC address: %pM\n", eeprom->mac_address);
46bc8d4b 3700 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
4bc85c13
WYG
3701
3702 /***********************
3703 * 5. Setup HW Constants
3704 * ********************/
3705 /* Device-specific setup */
46bc8d4b 3706 if (il3945_hw_set_hw_params(il)) {
9406f797 3707 IL_ERR("failed to set hw settings\n");
4bc85c13
WYG
3708 goto out_eeprom_free;
3709 }
3710
3711 /***********************
46bc8d4b 3712 * 6. Setup il
4bc85c13
WYG
3713 * ********************/
3714
46bc8d4b 3715 err = il3945_init_drv(il);
4bc85c13 3716 if (err) {
9406f797 3717 IL_ERR("initializing driver failed\n");
4bc85c13
WYG
3718 goto out_unset_hw_params;
3719 }
3720
e7392364 3721 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
4bc85c13
WYG
3722
3723 /***********************
3724 * 7. Setup Services
3725 * ********************/
3726
46bc8d4b
SG
3727 spin_lock_irqsave(&il->lock, flags);
3728 il_disable_interrupts(il);
3729 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3730
46bc8d4b 3731 pci_enable_msi(il->pci_dev);
4bc85c13 3732
e7392364 3733 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
4bc85c13 3734 if (err) {
9406f797 3735 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
4bc85c13
WYG
3736 goto out_disable_msi;
3737 }
3738
e2ebc833 3739 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3740 if (err) {
9406f797 3741 IL_ERR("failed to create sysfs device attributes\n");
4bc85c13
WYG
3742 goto out_release_irq;
3743 }
3744
83007196 3745 il_set_rxon_channel(il, &il->bands[IEEE80211_BAND_2GHZ].channels[5]);
46bc8d4b 3746 il3945_setup_deferred_work(il);
d0c72347 3747 il3945_setup_handlers(il);
46bc8d4b 3748 il_power_initialize(il);
4bc85c13
WYG
3749
3750 /*********************************
3751 * 8. Setup and Register mac80211
3752 * *******************************/
3753
46bc8d4b 3754 il_enable_interrupts(il);
4bc85c13 3755
46bc8d4b 3756 err = il3945_setup_mac(il);
4bc85c13 3757 if (err)
e7392364 3758 goto out_remove_sysfs;
4bc85c13 3759
46bc8d4b 3760 err = il_dbgfs_register(il, DRV_NAME);
4bc85c13 3761 if (err)
e7392364
SG
3762 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
3763 err);
4bc85c13
WYG
3764
3765 /* Start monitoring the killswitch */
e7392364 3766 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
4bc85c13
WYG
3767
3768 return 0;
3769
e7392364 3770out_remove_sysfs:
46bc8d4b
SG
3771 destroy_workqueue(il->workqueue);
3772 il->workqueue = NULL;
e2ebc833 3773 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
e7392364 3774out_release_irq:
46bc8d4b 3775 free_irq(il->pci_dev->irq, il);
e7392364 3776out_disable_msi:
46bc8d4b
SG
3777 pci_disable_msi(il->pci_dev);
3778 il_free_geos(il);
3779 il_free_channel_map(il);
e7392364 3780out_unset_hw_params:
46bc8d4b 3781 il3945_unset_hw_params(il);
e7392364 3782out_eeprom_free:
46bc8d4b 3783 il_eeprom_free(il);
e7392364 3784out_iounmap:
a5f16137 3785 iounmap(il->hw_base);
e7392364 3786out_pci_release_regions:
4bc85c13 3787 pci_release_regions(pdev);
e7392364 3788out_pci_disable_device:
4bc85c13
WYG
3789 pci_set_drvdata(pdev, NULL);
3790 pci_disable_device(pdev);
e7392364 3791out_ieee80211_free_hw:
46bc8d4b 3792 ieee80211_free_hw(il->hw);
e7392364 3793out:
4bc85c13
WYG
3794 return err;
3795}
3796
e7392364
SG
3797static void __devexit
3798il3945_pci_remove(struct pci_dev *pdev)
4bc85c13 3799{
46bc8d4b 3800 struct il_priv *il = pci_get_drvdata(pdev);
4bc85c13
WYG
3801 unsigned long flags;
3802
46bc8d4b 3803 if (!il)
4bc85c13
WYG
3804 return;
3805
58de00a4 3806 D_INFO("*** UNLOAD DRIVER ***\n");
4bc85c13 3807
46bc8d4b 3808 il_dbgfs_unregister(il);
4bc85c13 3809
a6766ccd 3810 set_bit(S_EXIT_PENDING, &il->status);
4bc85c13 3811
46bc8d4b 3812 il_leds_exit(il);
4bc85c13 3813
46bc8d4b
SG
3814 if (il->mac80211_registered) {
3815 ieee80211_unregister_hw(il->hw);
3816 il->mac80211_registered = 0;
4bc85c13 3817 } else {
46bc8d4b 3818 il3945_down(il);
4bc85c13
WYG
3819 }
3820
3821 /*
3822 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG
3823 * This may be redundant with il_down(), but there are paths to
3824 * run il_down() without calling apm_ops.stop(), and there are
3825 * paths to avoid running il_down() at all before leaving driver.
4bc85c13
WYG
3826 * This (inexpensive) call *makes sure* device is reset.
3827 */
46bc8d4b 3828 il_apm_stop(il);
4bc85c13
WYG
3829
3830 /* make sure we flush any pending irq or
3831 * tasklet for the driver
3832 */
46bc8d4b
SG
3833 spin_lock_irqsave(&il->lock, flags);
3834 il_disable_interrupts(il);
3835 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3836
46bc8d4b 3837 il3945_synchronize_irq(il);
4bc85c13 3838
e2ebc833 3839 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3840
46bc8d4b 3841 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
4bc85c13 3842
46bc8d4b 3843 il3945_dealloc_ucode_pci(il);
4bc85c13 3844
46bc8d4b
SG
3845 if (il->rxq.bd)
3846 il3945_rx_queue_free(il, &il->rxq);
3847 il3945_hw_txq_ctx_free(il);
4bc85c13 3848
46bc8d4b 3849 il3945_unset_hw_params(il);
4bc85c13
WYG
3850
3851 /*netif_stop_queue(dev); */
46bc8d4b 3852 flush_workqueue(il->workqueue);
4bc85c13 3853
e2ebc833 3854 /* ieee80211_unregister_hw calls il3945_mac_stop, which flushes
46bc8d4b 3855 * il->workqueue... so we can't take down the workqueue
4bc85c13 3856 * until now... */
46bc8d4b
SG
3857 destroy_workqueue(il->workqueue);
3858 il->workqueue = NULL;
4bc85c13 3859
46bc8d4b 3860 free_irq(pdev->irq, il);
4bc85c13
WYG
3861 pci_disable_msi(pdev);
3862
a5f16137 3863 iounmap(il->hw_base);
4bc85c13
WYG
3864 pci_release_regions(pdev);
3865 pci_disable_device(pdev);
3866 pci_set_drvdata(pdev, NULL);
3867
46bc8d4b
SG
3868 il_free_channel_map(il);
3869 il_free_geos(il);
3870 kfree(il->scan_cmd);
3871 if (il->beacon_skb)
3872 dev_kfree_skb(il->beacon_skb);
4bc85c13 3873
46bc8d4b 3874 ieee80211_free_hw(il->hw);
4bc85c13
WYG
3875}
3876
4bc85c13
WYG
3877/*****************************************************************************
3878 *
3879 * driver and module entry point
3880 *
3881 *****************************************************************************/
3882
e2ebc833 3883static struct pci_driver il3945_driver = {
4bc85c13 3884 .name = DRV_NAME,
e2ebc833
SG
3885 .id_table = il3945_hw_card_ids,
3886 .probe = il3945_pci_probe,
3887 .remove = __devexit_p(il3945_pci_remove),
3888 .driver.pm = IL_LEGACY_PM_OPS,
4bc85c13
WYG
3889};
3890
e7392364
SG
3891static int __init
3892il3945_init(void)
4bc85c13
WYG
3893{
3894
3895 int ret;
3896 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3897 pr_info(DRV_COPYRIGHT "\n");
3898
e2ebc833 3899 ret = il3945_rate_control_register();
4bc85c13
WYG
3900 if (ret) {
3901 pr_err("Unable to register rate control algorithm: %d\n", ret);
3902 return ret;
3903 }
3904
e2ebc833 3905 ret = pci_register_driver(&il3945_driver);
4bc85c13
WYG
3906 if (ret) {
3907 pr_err("Unable to initialize PCI module\n");
3908 goto error_register;
3909 }
3910
3911 return ret;
3912
3913error_register:
e2ebc833 3914 il3945_rate_control_unregister();
4bc85c13
WYG
3915 return ret;
3916}
3917
e7392364
SG
3918static void __exit
3919il3945_exit(void)
4bc85c13 3920{
e2ebc833
SG
3921 pci_unregister_driver(&il3945_driver);
3922 il3945_rate_control_unregister();
4bc85c13
WYG
3923}
3924
d3175167 3925MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
4bc85c13 3926
e2ebc833 3927module_param_named(antenna, il3945_mod_params.antenna, int, S_IRUGO);
4bc85c13 3928MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
e2ebc833 3929module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, S_IRUGO);
e7392364
SG
3930MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3931module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3932 S_IRUGO);
0263aa45 3933MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
d3175167 3934#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 3935module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
4bc85c13
WYG
3936MODULE_PARM_DESC(debug, "debug output mask");
3937#endif
e2ebc833 3938module_param_named(fw_restart, il3945_mod_params.restart_fw, int, S_IRUGO);
be663ab6 3939MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4bc85c13 3940
e2ebc833
SG
3941module_exit(il3945_exit);
3942module_init(il3945_init);
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