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Merge tag 'uapi-prep-20121002' of git://git.infradead.org/users/dhowells/linux-headers
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
be663ab6
WYG		 43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
98613be0 53#include "common.h"
af038f40 54#include "4965.h"
be663ab6 55
be663ab6
WYG		 56/******************************************************************************
57 *
58 * module boiler plate
59 *
60 ******************************************************************************/
61
62/*
63 * module name, copyright, version, etc.
64 */
65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
66
d3175167 67#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 68#define VD "d"
69#else
70#define VD
71#endif
72
73#define DRV_VERSION IWLWIFI_VERSION VD
74
be663ab6
WYG		 75MODULE_DESCRIPTION(DRV_DESCRIPTION);
76MODULE_VERSION(DRV_VERSION);
77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78MODULE_LICENSE("GPL");
79MODULE_ALIAS("iwl4965");
80
e7392364
SG		 81void
82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
fcb74588
SG		 83{
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
a6766ccd 86 if (!test_bit(S_EXIT_PENDING, &il->status))
fcb74588
SG		 87 queue_work(il->workqueue, &il->tx_flush);
88 }
89}
90
91/*
92 * EEPROM
93 */
94struct il_mod_params il4965_mod_params = {
95 .amsdu_size_8K = 1,
96 .restart_fw = 1,
97 /* the rest are 0 by default */
98};
99
e7392364
SG		 100void
101il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 102{
103 unsigned long flags;
104 int i;
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 114 PAGE_SIZE << il->hw_params.rx_page_order,
115 PCI_DMA_FROMDEVICE);
fcb74588
SG		 116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
118 }
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
120 }
121
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
124
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
129 rxq->free_count = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
131}
132
e7392364
SG		 133int
134il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 135{
136 u32 rb_size;
e7392364 137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
fcb74588
SG		 138 u32 rb_timeout = 0;
139
140 if (il->cfg->mod_params->amsdu_size_8K)
9a95b370 141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
fcb74588 142 else
9a95b370 143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
fcb74588
SG		 144
145 /* Stop Rx DMA */
9a95b370 146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
fcb74588
SG		 147
148 /* Reset driver's Rx queue write idx */
9a95b370 149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
fcb74588
SG		 150
151 /* Tell device where to find RBD circular buffer in DRAM */
e7392364 152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
fcb74588
SG		 153
154 /* Tell device where in DRAM to update its Rx status */
e7392364 155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
fcb74588
SG		 156
157 /* Enable Rx DMA
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
160 * RB timeout 0x10
161 * 256 RBDs
162 */
9a95b370 163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
e7392364
SG		 164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
1722f8e1
SG		 166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
167 rb_size |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
fcb74588
SG		 170
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
173
174 return 0;
175}
176
e7392364
SG		 177static void
178il4965_set_pwr_vmain(struct il_priv *il)
fcb74588
SG		 179{
180/*
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
183
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
188 */
189
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
e7392364
SG		 191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
fcb74588
SG		 193}
194
e7392364
SG		 195int
196il4965_hw_nic_init(struct il_priv *il)
fcb74588
SG		 197{
198 unsigned long flags;
199 struct il_rx_queue *rxq = &il->rxq;
200 int ret;
201
fcb74588 202 spin_lock_irqsave(&il->lock, flags);
f03ee2a8 203 il_apm_init(il);
fcb74588
SG		 204 /* Set interrupt coalescing calibration timer to default (512 usecs) */
205 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
fcb74588
SG		 206 spin_unlock_irqrestore(&il->lock, flags);
207
208 il4965_set_pwr_vmain(il);
f03ee2a8 209 il4965_nic_config(il);
fcb74588
SG		 210
211 /* Allocate the RX queue, or reset if it is already allocated */
212 if (!rxq->bd) {
213 ret = il_rx_queue_alloc(il);
214 if (ret) {
215 IL_ERR("Unable to initialize Rx queue\n");
216 return -ENOMEM;
217 }
218 } else
219 il4965_rx_queue_reset(il, rxq);
220
221 il4965_rx_replenish(il);
222
223 il4965_rx_init(il, rxq);
224
225 spin_lock_irqsave(&il->lock, flags);
226
227 rxq->need_update = 1;
228 il_rx_queue_update_write_ptr(il, rxq);
229
230 spin_unlock_irqrestore(&il->lock, flags);
231
232 /* Allocate or reset and init all Tx and Command queues */
233 if (!il->txq) {
234 ret = il4965_txq_ctx_alloc(il);
235 if (ret)
236 return ret;
237 } else
238 il4965_txq_ctx_reset(il);
239
a6766ccd 240 set_bit(S_INIT, &il->status);
fcb74588
SG		 241
242 return 0;
243}
244
245/**
246 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
247 */
e7392364
SG		 248static inline __le32
249il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
fcb74588 250{
e7392364 251 return cpu_to_le32((u32) (dma_addr >> 8));
fcb74588
SG		 252}
253
254/**
255 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
256 *
257 * If there are slots in the RX queue that need to be restocked,
258 * and we have free pre-allocated buffers, fill the ranks as much
259 * as we can, pulling from rx_free.
260 *
261 * This moves the 'write' idx forward to catch up with 'processed', and
262 * also updates the memory address in the firmware to reference the new
263 * target buffer.
264 */
e7392364
SG		 265void
266il4965_rx_queue_restock(struct il_priv *il)
fcb74588
SG		 267{
268 struct il_rx_queue *rxq = &il->rxq;
269 struct list_head *element;
270 struct il_rx_buf *rxb;
271 unsigned long flags;
272
273 spin_lock_irqsave(&rxq->lock, flags);
274 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
275 /* The overwritten rxb must be a used one */
276 rxb = rxq->queue[rxq->write];
277 BUG_ON(rxb && rxb->page);
278
279 /* Get next free Rx buffer, remove from free list */
280 element = rxq->rx_free.next;
281 rxb = list_entry(element, struct il_rx_buf, list);
282 list_del(element);
283
284 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG		 285 rxq->bd[rxq->write] =
286 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
fcb74588
SG		 287 rxq->queue[rxq->write] = rxb;
288 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
289 rxq->free_count--;
290 }
291 spin_unlock_irqrestore(&rxq->lock, flags);
292 /* If the pre-allocated buffer pool is dropping low, schedule to
293 * refill it */
294 if (rxq->free_count <= RX_LOW_WATERMARK)
295 queue_work(il->workqueue, &il->rx_replenish);
296
fcb74588
SG		 297 /* If we've added more space for the firmware to place data, tell it.
298 * Increment device's write pointer in multiples of 8. */
299 if (rxq->write_actual != (rxq->write & ~0x7)) {
300 spin_lock_irqsave(&rxq->lock, flags);
301 rxq->need_update = 1;
302 spin_unlock_irqrestore(&rxq->lock, flags);
303 il_rx_queue_update_write_ptr(il, rxq);
304 }
305}
306
307/**
308 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
309 *
310 * When moving to rx_free an SKB is allocated for the slot.
311 *
312 * Also restock the Rx queue via il_rx_queue_restock.
313 * This is called as a scheduled work item (except for during initialization)
314 */
e7392364
SG		 315static void
316il4965_rx_allocate(struct il_priv *il, gfp_t priority)
fcb74588
SG		 317{
318 struct il_rx_queue *rxq = &il->rxq;
319 struct list_head *element;
320 struct il_rx_buf *rxb;
321 struct page *page;
322 unsigned long flags;
323 gfp_t gfp_mask = priority;
324
325 while (1) {
326 spin_lock_irqsave(&rxq->lock, flags);
327 if (list_empty(&rxq->rx_used)) {
328 spin_unlock_irqrestore(&rxq->lock, flags);
329 return;
330 }
331 spin_unlock_irqrestore(&rxq->lock, flags);
332
333 if (rxq->free_count > RX_LOW_WATERMARK)
334 gfp_mask |= __GFP_NOWARN;
335
336 if (il->hw_params.rx_page_order > 0)
337 gfp_mask |= __GFP_COMP;
338
339 /* Alloc a new receive buffer */
340 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
341 if (!page) {
342 if (net_ratelimit())
e7392364
SG		 343 D_INFO("alloc_pages failed, " "order: %d\n",
344 il->hw_params.rx_page_order);
fcb74588
SG		 345
346 if (rxq->free_count <= RX_LOW_WATERMARK &&
347 net_ratelimit())
e7392364
SG		 348 IL_ERR("Failed to alloc_pages with %s. "
349 "Only %u free buffers remaining.\n",
350 priority ==
351 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
352 rxq->free_count);
fcb74588
SG		 353 /* We don't reschedule replenish work here -- we will
354 * call the restock method and if it still needs
355 * more buffers it will schedule replenish */
356 return;
357 }
358
359 spin_lock_irqsave(&rxq->lock, flags);
360
361 if (list_empty(&rxq->rx_used)) {
362 spin_unlock_irqrestore(&rxq->lock, flags);
363 __free_pages(page, il->hw_params.rx_page_order);
364 return;
365 }
366 element = rxq->rx_used.next;
367 rxb = list_entry(element, struct il_rx_buf, list);
368 list_del(element);
369
370 spin_unlock_irqrestore(&rxq->lock, flags);
371
372 BUG_ON(rxb->page);
373 rxb->page = page;
374 /* Get physical address of the RB */
e7392364
SG		 375 rxb->page_dma =
376 pci_map_page(il->pci_dev, page, 0,
377 PAGE_SIZE << il->hw_params.rx_page_order,
378 PCI_DMA_FROMDEVICE);
fcb74588
SG		 379 /* dma address must be no more than 36 bits */
380 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
381 /* and also 256 byte aligned! */
382 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
383
384 spin_lock_irqsave(&rxq->lock, flags);
385
386 list_add_tail(&rxb->list, &rxq->rx_free);
387 rxq->free_count++;
388 il->alloc_rxb_page++;
389
390 spin_unlock_irqrestore(&rxq->lock, flags);
391 }
392}
393
e7392364
SG		 394void
395il4965_rx_replenish(struct il_priv *il)
fcb74588
SG		 396{
397 unsigned long flags;
398
399 il4965_rx_allocate(il, GFP_KERNEL);
400
401 spin_lock_irqsave(&il->lock, flags);
402 il4965_rx_queue_restock(il);
403 spin_unlock_irqrestore(&il->lock, flags);
404}
405
e7392364
SG		 406void
407il4965_rx_replenish_now(struct il_priv *il)
fcb74588
SG		 408{
409 il4965_rx_allocate(il, GFP_ATOMIC);
410
411 il4965_rx_queue_restock(il);
412}
413
414/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
415 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
416 * This free routine walks the list of POOL entries and if SKB is set to
417 * non NULL it is unmapped and freed
418 */
e7392364
SG		 419void
420il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 421{
422 int i;
423 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
424 if (rxq->pool[i].page != NULL) {
425 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 426 PAGE_SIZE << il->hw_params.rx_page_order,
427 PCI_DMA_FROMDEVICE);
fcb74588
SG		 428 __il_free_pages(il, rxq->pool[i].page);
429 rxq->pool[i].page = NULL;
430 }
431 }
432
433 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
434 rxq->bd_dma);
435 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
436 rxq->rb_stts, rxq->rb_stts_dma);
437 rxq->bd = NULL;
e7392364 438 rxq->rb_stts = NULL;
fcb74588
SG		 439}
440
e7392364
SG		 441int
442il4965_rxq_stop(struct il_priv *il)
fcb74588 443{
775ed8ab 444 int ret;
fcb74588 445
775ed8ab
SG		 446 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
447 ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
448 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
449 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
450 1000);
451 if (ret < 0)
452 IL_ERR("Can't stop Rx DMA.\n");
fcb74588
SG		 453
454 return 0;
455}
456
e7392364
SG		 457int
458il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
fcb74588
SG		 459{
460 int idx = 0;
461 int band_offset = 0;
462
463 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
464 if (rate_n_flags & RATE_MCS_HT_MSK) {
465 idx = (rate_n_flags & 0xff);
466 return idx;
e7392364 467 /* Legacy rate format, search for match in table */
fcb74588
SG		 468 } else {
469 if (band == IEEE80211_BAND_5GHZ)
470 band_offset = IL_FIRST_OFDM_RATE;
471 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
472 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
473 return idx - band_offset;
474 }
475
476 return -1;
477}
478
e7392364
SG		 479static int
480il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
fcb74588
SG		 481{
482 /* data from PHY/DSP regarding signal strength, etc.,
483 * contents are always there, not configurable by host. */
484 struct il4965_rx_non_cfg_phy *ncphy =
485 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
e7392364
SG		 486 u32 agc =
487 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
488 IL49_AGC_DB_POS;
fcb74588
SG		 489
490 u32 valid_antennae =
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
e7392364 492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
fcb74588
SG		 493 u8 max_rssi = 0;
494 u32 i;
495
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
504
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
507 max_rssi, agc);
508
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
512}
513
e7392364
SG		 514static u32
515il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
fcb74588
SG		 516{
517 u32 decrypt_out = 0;
518
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
e7392364
SG		 520 RX_RES_STATUS_STATION_FOUND)
521 decrypt_out |=
522 (RX_RES_STATUS_STATION_FOUND |
523 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
fcb74588
SG		 524
525 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
526
527 /* packet was not encrypted */
528 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 529 RX_RES_STATUS_SEC_TYPE_NONE)
fcb74588
SG		 530 return decrypt_out;
531
532 /* packet was encrypted with unknown alg */
533 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 534 RX_RES_STATUS_SEC_TYPE_ERR)
fcb74588
SG		 535 return decrypt_out;
536
537 /* decryption was not done in HW */
538 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
e7392364 539 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
fcb74588
SG		 540 return decrypt_out;
541
542 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
543
544 case RX_RES_STATUS_SEC_TYPE_CCMP:
545 /* alg is CCM: check MIC only */
546 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
547 /* Bad MIC */
548 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
549 else
550 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
551
552 break;
553
554 case RX_RES_STATUS_SEC_TYPE_TKIP:
555 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
556 /* Bad TTAK */
557 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
558 break;
559 }
560 /* fall through if TTAK OK */
561 default:
562 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
563 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
564 else
565 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
566 break;
567 }
568
e7392364 569 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
fcb74588
SG		 570
571 return decrypt_out;
572}
573
e7392364
SG		 574static void
575il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
576 u16 len, u32 ampdu_status, struct il_rx_buf *rxb,
577 struct ieee80211_rx_status *stats)
fcb74588
SG		 578{
579 struct sk_buff *skb;
580 __le16 fc = hdr->frame_control;
581
582 /* We only process data packets if the interface is open */
583 if (unlikely(!il->is_open)) {
e7392364 584 D_DROP("Dropping packet while interface is not open.\n");
fcb74588
SG		 585 return;
586 }
587
588 /* In case of HW accelerated crypto and bad decryption, drop */
589 if (!il->cfg->mod_params->sw_crypto &&
590 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
591 return;
592
593 skb = dev_alloc_skb(128);
594 if (!skb) {
595 IL_ERR("dev_alloc_skb failed\n");
596 return;
597 }
598
50269e19
ED		 599 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len,
600 len);
fcb74588
SG		 601
602 il_update_stats(il, false, fc, len);
603 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
604
605 ieee80211_rx(il->hw, skb);
606 il->alloc_rxb_page--;
607 rxb->page = NULL;
608}
609
4d69c752
SG		 610/* Called for N_RX (legacy ABG frames), or
611 * N_RX_MPDU (HT high-throughput N frames). */
e7392364
SG		 612void
613il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 614{
615 struct ieee80211_hdr *header;
616 struct ieee80211_rx_status rx_status;
617 struct il_rx_pkt *pkt = rxb_addr(rxb);
618 struct il_rx_phy_res *phy_res;
619 __le32 rx_pkt_status;
620 struct il_rx_mpdu_res_start *amsdu;
621 u32 len;
622 u32 ampdu_status;
623 u32 rate_n_flags;
624
625 /**
4d69c752
SG		 626 * N_RX and N_RX_MPDU are handled differently.
627 * N_RX: physical layer info is in this buffer
628 * N_RX_MPDU: physical layer info was sent in separate
fcb74588
SG		 629 * command and cached in il->last_phy_res
630 *
631 * Here we set up local variables depending on which command is
632 * received.
633 */
4d69c752 634 if (pkt->hdr.cmd == N_RX) {
fcb74588 635 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
e7392364
SG		 636 header =
637 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
638 phy_res->cfg_phy_cnt);
fcb74588
SG		 639
640 len = le16_to_cpu(phy_res->byte_count);
e7392364
SG		 641 rx_pkt_status =
642 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
643 phy_res->cfg_phy_cnt + len);
fcb74588
SG		 644 ampdu_status = le32_to_cpu(rx_pkt_status);
645 } else {
646 if (!il->_4965.last_phy_res_valid) {
647 IL_ERR("MPDU frame without cached PHY data\n");
648 return;
649 }
650 phy_res = &il->_4965.last_phy_res;
651 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
652 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
653 len = le16_to_cpu(amsdu->byte_count);
e7392364
SG		 654 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
655 ampdu_status =
656 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
fcb74588
SG		 657 }
658
659 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
660 D_DROP("dsp size out of range [0,20]: %d/n",
e7392364 661 phy_res->cfg_phy_cnt);
fcb74588
SG		 662 return;
663 }
664
665 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
666 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e7392364 667 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
fcb74588
SG		 668 return;
669 }
670
671 /* This will be used in several places later */
672 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
673
674 /* rx_status carries information about the packet to mac80211 */
675 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
e7392364
SG		 676 rx_status.band =
677 (phy_res->
678 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
679 IEEE80211_BAND_5GHZ;
fcb74588 680 rx_status.freq =
e7392364
SG		 681 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
682 rx_status.band);
fcb74588 683 rx_status.rate_idx =
e7392364 684 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
fcb74588
SG		 685 rx_status.flag = 0;
686
687 /* TSF isn't reliable. In order to allow smooth user experience,
688 * this W/A doesn't propagate it to the mac80211 */
e7392364 689 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU; */
fcb74588
SG		 690
691 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
692
693 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
694 rx_status.signal = il4965_calc_rssi(il, phy_res);
695
e7392364
SG		 696 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
697 (unsigned long long)rx_status.mactime);
fcb74588
SG		 698
699 /*
700 * "antenna number"
701 *
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
707 *
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
710 * as a bitmask.
711 */
712 rx_status.antenna =
e7392364
SG		 713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
714 RX_RES_PHY_FLAGS_ANTENNA_POS;
fcb74588
SG		 715
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
719
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
727
e7392364
SG		 728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
729 &rx_status);
fcb74588
SG		 730}
731
4d69c752 732/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
6e9848b4 733 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
e7392364
SG		 734void
735il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 736{
737 struct il_rx_pkt *pkt = rxb_addr(rxb);
738 il->_4965.last_phy_res_valid = true;
739 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
740 sizeof(struct il_rx_phy_res));
741}
742
e7392364
SG		 743static int
744il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
745 enum ieee80211_band band, u8 is_active,
746 u8 n_probes, struct il_scan_channel *scan_ch)
fcb74588
SG		 747{
748 struct ieee80211_channel *chan;
749 const struct ieee80211_supported_band *sband;
750 const struct il_channel_info *ch_info;
751 u16 passive_dwell = 0;
752 u16 active_dwell = 0;
753 int added, i;
754 u16 channel;
755
756 sband = il_get_hw_mode(il, band);
757 if (!sband)
758 return 0;
759
760 active_dwell = il_get_active_dwell_time(il, band, n_probes);
761 passive_dwell = il_get_passive_dwell_time(il, band, vif);
762
763 if (passive_dwell <= active_dwell)
764 passive_dwell = active_dwell + 1;
765
766 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
767 chan = il->scan_request->channels[i];
768
769 if (chan->band != band)
770 continue;
771
772 channel = chan->hw_value;
773 scan_ch->channel = cpu_to_le16(channel);
774
775 ch_info = il_get_channel_info(il, band, channel);
776 if (!il_is_channel_valid(ch_info)) {
e7392364
SG		 777 D_SCAN("Channel %d is INVALID for this band.\n",
778 channel);
fcb74588
SG		 779 continue;
780 }
781
782 if (!is_active || il_is_channel_passive(ch_info) ||
783 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
784 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
785 else
786 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
787
788 if (n_probes)
789 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
790
791 scan_ch->active_dwell = cpu_to_le16(active_dwell);
792 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
793
794 /* Set txpower levels to defaults */
795 scan_ch->dsp_atten = 110;
796
797 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
798 * power level:
799 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
800 */
801 if (band == IEEE80211_BAND_5GHZ)
802 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
803 else
804 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
805
e7392364
SG		 806 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
807 le32_to_cpu(scan_ch->type),
808 (scan_ch->
809 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
810 (scan_ch->
811 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
812 passive_dwell);
fcb74588
SG		 813
814 scan_ch++;
815 added++;
816 }
817
818 D_SCAN("total channels to scan %d\n", added);
819 return added;
820}
821
a0c1ef3b
SG		 822static void
823il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
824{
825 int i;
826 u8 ind = *ant;
827
828 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
829 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
830 if (valid & BIT(ind)) {
831 *ant = ind;
832 return;
833 }
834 }
835}
836
e7392364
SG		 837int
838il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
fcb74588
SG		 839{
840 struct il_host_cmd cmd = {
4d69c752 841 .id = C_SCAN,
fcb74588
SG		 842 .len = sizeof(struct il_scan_cmd),
843 .flags = CMD_SIZE_HUGE,
844 };
845 struct il_scan_cmd *scan;
fcb74588
SG		 846 u32 rate_flags = 0;
847 u16 cmd_len;
848 u16 rx_chain = 0;
849 enum ieee80211_band band;
850 u8 n_probes = 0;
851 u8 rx_ant = il->hw_params.valid_rx_ant;
852 u8 rate;
853 bool is_active = false;
e7392364 854 int chan_mod;
fcb74588
SG		 855 u8 active_chains;
856 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
857 int ret;
858
859 lockdep_assert_held(&il->mutex);
860
fcb74588 861 if (!il->scan_cmd) {
e7392364
SG		 862 il->scan_cmd =
863 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
864 GFP_KERNEL);
fcb74588 865 if (!il->scan_cmd) {
e7392364 866 D_SCAN("fail to allocate memory for scan\n");
fcb74588
SG		 867 return -ENOMEM;
868 }
869 }
870 scan = il->scan_cmd;
871 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
872
873 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
874 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
875
876 if (il_is_any_associated(il)) {
877 u16 interval;
878 u32 extra;
879 u32 suspend_time = 100;
880 u32 scan_suspend_time = 100;
881
882 D_INFO("Scanning while associated...\n");
883 interval = vif->bss_conf.beacon_int;
884
885 scan->suspend_time = 0;
886 scan->max_out_time = cpu_to_le32(200 * 1024);
887 if (!interval)
888 interval = suspend_time;
889
890 extra = (suspend_time / interval) << 22;
e7392364
SG		 891 scan_suspend_time =
892 (extra | ((suspend_time % interval) * 1024));
fcb74588
SG		 893 scan->suspend_time = cpu_to_le32(scan_suspend_time);
894 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 895 scan_suspend_time, interval);
fcb74588
SG		 896 }
897
898 if (il->scan_request->n_ssids) {
899 int i, p = 0;
900 D_SCAN("Kicking off active scan\n");
901 for (i = 0; i < il->scan_request->n_ssids; i++) {
902 /* always does wildcard anyway */
903 if (!il->scan_request->ssids[i].ssid_len)
904 continue;
905 scan->direct_scan[p].id = WLAN_EID_SSID;
906 scan->direct_scan[p].len =
e7392364 907 il->scan_request->ssids[i].ssid_len;
fcb74588
SG		 908 memcpy(scan->direct_scan[p].ssid,
909 il->scan_request->ssids[i].ssid,
910 il->scan_request->ssids[i].ssid_len);
911 n_probes++;
912 p++;
913 }
914 is_active = true;
915 } else
916 D_SCAN("Start passive scan.\n");
917
918 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 919 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
fcb74588
SG		 920 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
921
922 switch (il->scan_band) {
923 case IEEE80211_BAND_2GHZ:
924 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
e7392364 925 chan_mod =
c8b03958 926 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
e7392364 927 RXON_FLG_CHANNEL_MODE_POS;
fcb74588
SG		 928 if (chan_mod == CHANNEL_MODE_PURE_40) {
929 rate = RATE_6M_PLCP;
930 } else {
931 rate = RATE_1M_PLCP;
932 rate_flags = RATE_MCS_CCK_MSK;
933 }
934 break;
935 case IEEE80211_BAND_5GHZ:
936 rate = RATE_6M_PLCP;
937 break;
938 default:
939 IL_WARN("Invalid scan band\n");
940 return -EIO;
941 }
942
943 /*
944 * If active scanning is requested but a certain channel is
945 * marked passive, we can do active scanning if we detect
946 * transmissions.
947 *
948 * There is an issue with some firmware versions that triggers
949 * a sysassert on a "good CRC threshold" of zero (== disabled),
950 * on a radar channel even though this means that we should NOT
951 * send probes.
952 *
953 * The "good CRC threshold" is the number of frames that we
954 * need to receive during our dwell time on a channel before
955 * sending out probes -- setting this to a huge value will
956 * mean we never reach it, but at the same time work around
957 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
958 * here instead of IL_GOOD_CRC_TH_DISABLED.
959 */
e7392364
SG		 960 scan->good_CRC_th =
961 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
fcb74588
SG		 962
963 band = il->scan_band;
964
965 if (il->cfg->scan_rx_antennas[band])
966 rx_ant = il->cfg->scan_rx_antennas[band];
967
a0c1ef3b 968 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
616107ed
SG		 969 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
970 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
fcb74588
SG		 971
972 /* In power save mode use one chain, otherwise use all chains */
a6766ccd 973 if (test_bit(S_POWER_PMI, &il->status)) {
fcb74588 974 /* rx_ant has been set to all valid chains previously */
e7392364
SG		 975 active_chains =
976 rx_ant & ((u8) (il->chain_noise_data.active_chains));
fcb74588
SG		 977 if (!active_chains)
978 active_chains = rx_ant;
979
980 D_SCAN("chain_noise_data.active_chains: %u\n",
e7392364 981 il->chain_noise_data.active_chains);
fcb74588
SG		 982
983 rx_ant = il4965_first_antenna(active_chains);
984 }
985
986 /* MIMO is not used here, but value is required */
987 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
988 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
989 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
990 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
991 scan->rx_chain = cpu_to_le16(rx_chain);
992
e7392364
SG		 993 cmd_len =
994 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
995 vif->addr, il->scan_request->ie,
996 il->scan_request->ie_len,
997 IL_MAX_SCAN_SIZE - sizeof(*scan));
fcb74588
SG		 998 scan->tx_cmd.len = cpu_to_le16(cmd_len);
999
e7392364
SG		 1000 scan->filter_flags |=
1001 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
fcb74588 1002
e7392364
SG		 1003 scan->channel_count =
1004 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1005 (void *)&scan->data[cmd_len]);
fcb74588
SG		 1006 if (scan->channel_count == 0) {
1007 D_SCAN("channel count %d\n", scan->channel_count);
1008 return -EIO;
1009 }
1010
e7392364
SG		 1011 cmd.len +=
1012 le16_to_cpu(scan->tx_cmd.len) +
fcb74588
SG		 1013 scan->channel_count * sizeof(struct il_scan_channel);
1014 cmd.data = scan;
1015 scan->len = cpu_to_le16(cmd.len);
1016
a6766ccd 1017 set_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1018
1019 ret = il_send_cmd_sync(il, &cmd);
1020 if (ret)
a6766ccd 1021 clear_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1022
1023 return ret;
1024}
1025
e7392364
SG		 1026int
1027il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1028 bool add)
fcb74588
SG		 1029{
1030 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1031
1032 if (add)
83007196 1033 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
fcb74588
SG		 1034 &vif_priv->ibss_bssid_sta_id);
1035 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
e7392364 1036 vif->bss_conf.bssid);
fcb74588
SG		 1037}
1038
e7392364
SG		 1039void
1040il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
fcb74588
SG		 1041{
1042 lockdep_assert_held(&il->sta_lock);
1043
1044 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1045 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1046 else {
1047 D_TX("free more than tfds_in_queue (%u:%d)\n",
e7392364 1048 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
fcb74588
SG		 1049 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1050 }
1051}
1052
1053#define IL_TX_QUEUE_MSK 0xfffff
1054
e7392364
SG		 1055static bool
1056il4965_is_single_rx_stream(struct il_priv *il)
fcb74588
SG		 1057{
1058 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
e7392364 1059 il->current_ht_config.single_chain_sufficient;
fcb74588
SG		 1060}
1061
1062#define IL_NUM_RX_CHAINS_MULTIPLE 3
1063#define IL_NUM_RX_CHAINS_SINGLE 2
1064#define IL_NUM_IDLE_CHAINS_DUAL 2
1065#define IL_NUM_IDLE_CHAINS_SINGLE 1
1066
1067/*
1068 * Determine how many receiver/antenna chains to use.
1069 *
1070 * More provides better reception via diversity. Fewer saves power
1071 * at the expense of throughput, but only when not in powersave to
1072 * start with.
1073 *
1074 * MIMO (dual stream) requires at least 2, but works better with 3.
1075 * This does not determine *which* chains to use, just how many.
1076 */
e7392364
SG		 1077static int
1078il4965_get_active_rx_chain_count(struct il_priv *il)
fcb74588
SG		 1079{
1080 /* # of Rx chains to use when expecting MIMO. */
1081 if (il4965_is_single_rx_stream(il))
1082 return IL_NUM_RX_CHAINS_SINGLE;
1083 else
1084 return IL_NUM_RX_CHAINS_MULTIPLE;
1085}
1086
1087/*
1088 * When we are in power saving mode, unless device support spatial
1089 * multiplexing power save, use the active count for rx chain count.
1090 */
1091static int
1092il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1093{
1094 /* # Rx chains when idling, depending on SMPS mode */
1095 switch (il->current_ht_config.smps) {
1096 case IEEE80211_SMPS_STATIC:
1097 case IEEE80211_SMPS_DYNAMIC:
1098 return IL_NUM_IDLE_CHAINS_SINGLE;
1099 case IEEE80211_SMPS_OFF:
1100 return active_cnt;
1101 default:
e7392364 1102 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
fcb74588
SG		 1103 return active_cnt;
1104 }
1105}
1106
1107/* up to 4 chains */
e7392364
SG		 1108static u8
1109il4965_count_chain_bitmap(u32 chain_bitmap)
fcb74588
SG		 1110{
1111 u8 res;
1112 res = (chain_bitmap & BIT(0)) >> 0;
1113 res += (chain_bitmap & BIT(1)) >> 1;
1114 res += (chain_bitmap & BIT(2)) >> 2;
1115 res += (chain_bitmap & BIT(3)) >> 3;
1116 return res;
1117}
1118
1119/**
1120 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1121 *
1122 * Selects how many and which Rx receivers/antennas/chains to use.
1123 * This should not be used for scan command ... it puts data in wrong place.
1124 */
e7392364 1125void
83007196 1126il4965_set_rxon_chain(struct il_priv *il)
fcb74588
SG		 1127{
1128 bool is_single = il4965_is_single_rx_stream(il);
a6766ccd 1129 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
fcb74588
SG		 1130 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1131 u32 active_chains;
1132 u16 rx_chain;
1133
1134 /* Tell uCode which antennas are actually connected.
1135 * Before first association, we assume all antennas are connected.
1136 * Just after first association, il4965_chain_noise_calibration()
1137 * checks which antennas actually *are* connected. */
1138 if (il->chain_noise_data.active_chains)
1139 active_chains = il->chain_noise_data.active_chains;
1140 else
1141 active_chains = il->hw_params.valid_rx_ant;
1142
1143 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1144
1145 /* How many receivers should we use? */
1146 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1147 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1148
fcb74588
SG		 1149 /* correct rx chain count according hw settings
1150 * and chain noise calibration
1151 */
1152 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1153 if (valid_rx_cnt < active_rx_cnt)
1154 active_rx_cnt = valid_rx_cnt;
1155
1156 if (valid_rx_cnt < idle_rx_cnt)
1157 idle_rx_cnt = valid_rx_cnt;
1158
1159 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
e7392364 1160 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
fcb74588 1161
c8b03958 1162 il->staging.rx_chain = cpu_to_le16(rx_chain);
fcb74588
SG		 1163
1164 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
c8b03958 1165 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1166 else
c8b03958 1167 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1168
c8b03958 1169 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
e7392364 1170 active_rx_cnt, idle_rx_cnt);
fcb74588
SG		 1171
1172 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1173 active_rx_cnt < idle_rx_cnt);
1174}
1175
e7392364
SG		 1176static const char *
1177il4965_get_fh_string(int cmd)
fcb74588
SG		 1178{
1179 switch (cmd) {
e7392364
SG		 1180 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1181 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1182 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1183 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1184 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1185 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1186 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1187 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1188 IL_CMD(FH49_TSSR_TX_ERROR_REG);
fcb74588
SG		 1189 default:
1190 return "UNKNOWN";
1191 }
1192}
1193
e7392364
SG		 1194int
1195il4965_dump_fh(struct il_priv *il, char **buf, bool display)
fcb74588
SG		 1196{
1197 int i;
1198#ifdef CONFIG_IWLEGACY_DEBUG
1199 int pos = 0;
1200 size_t bufsz = 0;
1201#endif
1202 static const u32 fh_tbl[] = {
9a95b370
SG		 1203 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1204 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1205 FH49_RSCSR_CHNL0_WPTR,
1206 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1207 FH49_MEM_RSSR_SHARED_CTRL_REG,
1208 FH49_MEM_RSSR_RX_STATUS_REG,
1209 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1210 FH49_TSSR_TX_STATUS_REG,
1211 FH49_TSSR_TX_ERROR_REG
fcb74588
SG		 1212 };
1213#ifdef CONFIG_IWLEGACY_DEBUG
1214 if (display) {
1215 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1216 *buf = kmalloc(bufsz, GFP_KERNEL);
1217 if (!*buf)
1218 return -ENOMEM;
e7392364
SG		 1219 pos +=
1220 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
fcb74588 1221 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
e7392364
SG		 1222 pos +=
1223 scnprintf(*buf + pos, bufsz - pos,
1224 " %34s: 0X%08x\n",
1722f8e1
SG		 1225 il4965_get_fh_string(fh_tbl[i]),
1226 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1227 }
1228 return pos;
1229 }
1230#endif
1231 IL_ERR("FH register values:\n");
e7392364
SG		 1232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1233 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1234 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1235 }
1236 return 0;
1237}
a1751b22 1238
e7392364
SG		 1239void
1240il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1241{
1242 struct il_rx_pkt *pkt = rxb_addr(rxb);
1243 struct il_missed_beacon_notif *missed_beacon;
1244
1245 missed_beacon = &pkt->u.missed_beacon;
1246 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1247 il->missed_beacon_threshold) {
e7392364
SG		 1248 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1249 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1250 le32_to_cpu(missed_beacon->total_missed_becons),
1251 le32_to_cpu(missed_beacon->num_recvd_beacons),
1252 le32_to_cpu(missed_beacon->num_expected_beacons));
a6766ccd 1253 if (!test_bit(S_SCANNING, &il->status))
a1751b22
SG		 1254 il4965_init_sensitivity(il);
1255 }
1256}
1257
1258/* Calculate noise level, based on measurements during network silence just
1259 * before arriving beacon. This measurement can be done only if we know
1260 * exactly when to expect beacons, therefore only when we're associated. */
e7392364
SG		 1261static void
1262il4965_rx_calc_noise(struct il_priv *il)
a1751b22
SG		 1263{
1264 struct stats_rx_non_phy *rx_info;
1265 int num_active_rx = 0;
1266 int total_silence = 0;
1267 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1268 int last_rx_noise;
1269
1270 rx_info = &(il->_4965.stats.rx.general);
1271 bcn_silence_a =
e7392364 1272 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
a1751b22 1273 bcn_silence_b =
e7392364 1274 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
a1751b22 1275 bcn_silence_c =
e7392364 1276 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
a1751b22
SG		 1277
1278 if (bcn_silence_a) {
1279 total_silence += bcn_silence_a;
1280 num_active_rx++;
1281 }
1282 if (bcn_silence_b) {
1283 total_silence += bcn_silence_b;
1284 num_active_rx++;
1285 }
1286 if (bcn_silence_c) {
1287 total_silence += bcn_silence_c;
1288 num_active_rx++;
1289 }
1290
1291 /* Average among active antennas */
1292 if (num_active_rx)
1293 last_rx_noise = (total_silence / num_active_rx) - 107;
1294 else
1295 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1296
e7392364
SG		 1297 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1298 bcn_silence_b, bcn_silence_c, last_rx_noise);
a1751b22
SG		 1299}
1300
1301#ifdef CONFIG_IWLEGACY_DEBUGFS
1302/*
1303 * based on the assumption of all stats counter are in DWORD
1304 * FIXME: This function is for debugging, do not deal with
1305 * the case of counters roll-over.
1306 */
e7392364
SG		 1307static void
1308il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
a1751b22
SG		 1309{
1310 int i, size;
1311 __le32 *prev_stats;
1312 u32 *accum_stats;
1313 u32 *delta, *max_delta;
1314 struct stats_general_common *general, *accum_general;
1315 struct stats_tx *tx, *accum_tx;
1316
1722f8e1
SG		 1317 prev_stats = (__le32 *) &il->_4965.stats;
1318 accum_stats = (u32 *) &il->_4965.accum_stats;
a1751b22
SG		 1319 size = sizeof(struct il_notif_stats);
1320 general = &il->_4965.stats.general.common;
1321 accum_general = &il->_4965.accum_stats.general.common;
1322 tx = &il->_4965.stats.tx;
1323 accum_tx = &il->_4965.accum_stats.tx;
1722f8e1
SG		 1324 delta = (u32 *) &il->_4965.delta_stats;
1325 max_delta = (u32 *) &il->_4965.max_delta;
a1751b22
SG		 1326
1327 for (i = sizeof(__le32); i < size;
e7392364
SG		 1328 i +=
1329 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1330 accum_stats++) {
a1751b22 1331 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
e7392364
SG		 1332 *delta =
1333 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
a1751b22
SG		 1334 *accum_stats += *delta;
1335 if (*delta > *max_delta)
1336 *max_delta = *delta;
1337 }
1338 }
1339
1340 /* reset accumulative stats for "no-counter" type stats */
1341 accum_general->temperature = general->temperature;
1342 accum_general->ttl_timestamp = general->ttl_timestamp;
1343}
1344#endif
1345
e7392364
SG		 1346void
1347il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22 1348{
527901d0
SG		 1349 const int recalib_seconds = 60;
1350 bool change;
a1751b22
SG		 1351 struct il_rx_pkt *pkt = rxb_addr(rxb);
1352
e7392364
SG		 1353 D_RX("Statistics notification received (%d vs %d).\n",
1354 (int)sizeof(struct il_notif_stats),
1355 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1356
1357 change =
1358 ((il->_4965.stats.general.common.temperature !=
1359 pkt->u.stats.general.common.temperature) ||
1360 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1361 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
a1751b22 1362#ifdef CONFIG_IWLEGACY_DEBUGFS
1722f8e1 1363 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
a1751b22
SG		 1364#endif
1365
1366 /* TODO: reading some of stats is unneeded */
e7392364 1367 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
a1751b22 1368
db7746f7 1369 set_bit(S_STATS, &il->status);
a1751b22 1370
527901d0
SG		 1371 /*
1372 * Reschedule the stats timer to occur in recalib_seconds to ensure
1373 * we get a thermal update even if the uCode doesn't give us one
1374 */
e7392364 1375 mod_timer(&il->stats_periodic,
527901d0 1376 jiffies + msecs_to_jiffies(recalib_seconds * 1000));
a1751b22 1377
a6766ccd 1378 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
4d69c752 1379 (pkt->hdr.cmd == N_STATS)) {
a1751b22
SG		 1380 il4965_rx_calc_noise(il);
1381 queue_work(il->workqueue, &il->run_time_calib_work);
1382 }
527901d0
SG		 1383
1384 if (change)
1385 il4965_temperature_calib(il);
a1751b22
SG		 1386}
1387
e7392364
SG		 1388void
1389il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1390{
1391 struct il_rx_pkt *pkt = rxb_addr(rxb);
1392
db7746f7 1393 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
a1751b22
SG		 1394#ifdef CONFIG_IWLEGACY_DEBUGFS
1395 memset(&il->_4965.accum_stats, 0,
e7392364 1396 sizeof(struct il_notif_stats));
a1751b22 1397 memset(&il->_4965.delta_stats, 0,
e7392364
SG		 1398 sizeof(struct il_notif_stats));
1399 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
a1751b22
SG		 1400#endif
1401 D_RX("Statistics have been cleared\n");
1402 }
d2dfb33e 1403 il4965_hdl_stats(il, rxb);
a1751b22
SG		 1404}
1405
8f29b456
SG		 1406
1407/*
1408 * mac80211 queues, ACs, hardware queues, FIFOs.
1409 *
1410 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1411 *
1412 * Mac80211 uses the following numbers, which we get as from it
1413 * by way of skb_get_queue_mapping(skb):
1414 *
1415 * VO 0
1416 * VI 1
1417 * BE 2
1418 * BK 3
1419 *
1420 *
1421 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1422 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1423 * own queue per aggregation session (RA/TID combination), such queues are
1424 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1425 * order to map frames to the right queue, we also need an AC->hw queue
1426 * mapping. This is implemented here.
1427 *
1428 * Due to the way hw queues are set up (by the hw specific modules like
af038f40 1429 * 4965.c), the AC->hw queue mapping is the identity
8f29b456
SG		 1430 * mapping.
1431 */
1432
a1751b22
SG		 1433static const u8 tid_to_ac[] = {
1434 IEEE80211_AC_BE,
1435 IEEE80211_AC_BK,
1436 IEEE80211_AC_BK,
1437 IEEE80211_AC_BE,
1438 IEEE80211_AC_VI,
1439 IEEE80211_AC_VI,
1440 IEEE80211_AC_VO,
1441 IEEE80211_AC_VO
1442};
1443
e7392364
SG		 1444static inline int
1445il4965_get_ac_from_tid(u16 tid)
a1751b22
SG		 1446{
1447 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1448 return tid_to_ac[tid];
1449
1450 /* no support for TIDs 8-15 yet */
1451 return -EINVAL;
1452}
1453
1454static inline int
83007196 1455il4965_get_fifo_from_tid(u16 tid)
a1751b22 1456{
b75b3a70
SG		 1457 const u8 ac_to_fifo[] = {
1458 IL_TX_FIFO_VO,
1459 IL_TX_FIFO_VI,
1460 IL_TX_FIFO_BE,
1461 IL_TX_FIFO_BK,
1462 };
1463
a1751b22 1464 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
b75b3a70 1465 return ac_to_fifo[tid_to_ac[tid]];
a1751b22
SG		 1466
1467 /* no support for TIDs 8-15 yet */
1468 return -EINVAL;
1469}
1470
1471/*
4d69c752 1472 * handle build C_TX command notification.
a1751b22 1473 */
e7392364
SG		 1474static void
1475il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1476 struct il_tx_cmd *tx_cmd,
1477 struct ieee80211_tx_info *info,
1478 struct ieee80211_hdr *hdr, u8 std_id)
a1751b22
SG		 1479{
1480 __le16 fc = hdr->frame_control;
1481 __le32 tx_flags = tx_cmd->tx_flags;
1482
1483 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1484 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1485 tx_flags |= TX_CMD_FLG_ACK_MSK;
1486 if (ieee80211_is_mgmt(fc))
1487 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1488 if (ieee80211_is_probe_resp(fc) &&
1489 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1490 tx_flags |= TX_CMD_FLG_TSF_MSK;
1491 } else {
1492 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1493 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1494 }
1495
1496 if (ieee80211_is_back_req(fc))
1497 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1498
1499 tx_cmd->sta_id = std_id;
1500 if (ieee80211_has_morefrags(fc))
1501 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1502
1503 if (ieee80211_is_data_qos(fc)) {
1504 u8 *qc = ieee80211_get_qos_ctl(hdr);
1505 tx_cmd->tid_tspec = qc[0] & 0xf;
1506 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1507 } else {
1508 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1509 }
1510
1511 il_tx_cmd_protection(il, info, fc, &tx_flags);
1512
1513 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1514 if (ieee80211_is_mgmt(fc)) {
1515 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1516 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1517 else
1518 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1519 } else {
1520 tx_cmd->timeout.pm_frame_timeout = 0;
1521 }
1522
1523 tx_cmd->driver_txop = 0;
1524 tx_cmd->tx_flags = tx_flags;
1525 tx_cmd->next_frame_len = 0;
1526}
1527
e7392364 1528static void
36323f81
TH		 1529il4965_tx_cmd_build_rate(struct il_priv *il,
1530 struct il_tx_cmd *tx_cmd,
1531 struct ieee80211_tx_info *info,
1532 struct ieee80211_sta *sta,
1533 __le16 fc)
a1751b22 1534{
616107ed 1535 const u8 rts_retry_limit = 60;
a1751b22
SG		 1536 u32 rate_flags;
1537 int rate_idx;
a1751b22
SG		 1538 u8 data_retry_limit;
1539 u8 rate_plcp;
1540
e7392364 1541 /* Set retry limit on DATA packets and Probe Responses */
a1751b22
SG		 1542 if (ieee80211_is_probe_resp(fc))
1543 data_retry_limit = 3;
1544 else
1545 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1546 tx_cmd->data_retry_limit = data_retry_limit;
a1751b22 1547 /* Set retry limit on RTS packets */
616107ed 1548 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
a1751b22
SG		 1549
1550 /* DATA packets will use the uCode station table for rate/antenna
1551 * selection */
1552 if (ieee80211_is_data(fc)) {
1553 tx_cmd->initial_rate_idx = 0;
1554 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1555 return;
1556 }
1557
1558 /**
1559 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1560 * not really a TX rate. Thus, we use the lowest supported rate for
1561 * this band. Also use the lowest supported rate if the stored rate
1562 * idx is invalid.
1563 */
1564 rate_idx = info->control.rates[0].idx;
e7392364
SG		 1565 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1566 || rate_idx > RATE_COUNT_LEGACY)
36323f81 1567 rate_idx = rate_lowest_index(&il->bands[info->band], sta);
a1751b22
SG		 1568 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1569 if (info->band == IEEE80211_BAND_5GHZ)
1570 rate_idx += IL_FIRST_OFDM_RATE;
1571 /* Get PLCP rate for tx_cmd->rate_n_flags */
1572 rate_plcp = il_rates[rate_idx].plcp;
1573 /* Zero out flags for this packet */
1574 rate_flags = 0;
1575
1576 /* Set CCK flag as needed */
1577 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1578 rate_flags |= RATE_MCS_CCK_MSK;
1579
1580 /* Set up antennas */
a0c1ef3b 1581 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 1582 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
a1751b22
SG		 1583
1584 /* Set the rate in the TX cmd */
616107ed 1585 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
a1751b22
SG		 1586}
1587
e7392364
SG		 1588static void
1589il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1590 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1591 int sta_id)
a1751b22
SG		 1592{
1593 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1594
1595 switch (keyconf->cipher) {
1596 case WLAN_CIPHER_SUITE_CCMP:
1597 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1598 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1599 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1600 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1601 D_TX("tx_cmd with AES hwcrypto\n");
1602 break;
1603
1604 case WLAN_CIPHER_SUITE_TKIP:
1605 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1606 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1607 D_TX("tx_cmd with tkip hwcrypto\n");
1608 break;
1609
1610 case WLAN_CIPHER_SUITE_WEP104:
1611 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1612 /* fall through */
1613 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG		 1614 tx_cmd->sec_ctl |=
1615 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1616 TX_CMD_SEC_SHIFT);
a1751b22
SG		 1617
1618 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1619
e7392364
SG		 1620 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1621 keyconf->keyidx);
a1751b22
SG		 1622 break;
1623
1624 default:
1625 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1626 break;
1627 }
1628}
1629
1630/*
4d69c752 1631 * start C_TX command process
a1751b22 1632 */
e7392364 1633int
36323f81
TH		 1634il4965_tx_skb(struct il_priv *il,
1635 struct ieee80211_sta *sta,
1636 struct sk_buff *skb)
a1751b22
SG		 1637{
1638 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1639 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
a1751b22
SG		 1640 struct il_station_priv *sta_priv = NULL;
1641 struct il_tx_queue *txq;
1642 struct il_queue *q;
1643 struct il_device_cmd *out_cmd;
1644 struct il_cmd_meta *out_meta;
1645 struct il_tx_cmd *tx_cmd;
a1751b22
SG		 1646 int txq_id;
1647 dma_addr_t phys_addr;
1648 dma_addr_t txcmd_phys;
1649 dma_addr_t scratch_phys;
1650 u16 len, firstlen, secondlen;
1651 u16 seq_number = 0;
1652 __le16 fc;
1653 u8 hdr_len;
1654 u8 sta_id;
1655 u8 wait_write_ptr = 0;
1656 u8 tid = 0;
1657 u8 *qc = NULL;
1658 unsigned long flags;
1659 bool is_agg = false;
1660
a1751b22
SG		 1661 spin_lock_irqsave(&il->lock, flags);
1662 if (il_is_rfkill(il)) {
1663 D_DROP("Dropping - RF KILL\n");
1664 goto drop_unlock;
1665 }
1666
1667 fc = hdr->frame_control;
1668
1669#ifdef CONFIG_IWLEGACY_DEBUG
1670 if (ieee80211_is_auth(fc))
1671 D_TX("Sending AUTH frame\n");
1672 else if (ieee80211_is_assoc_req(fc))
1673 D_TX("Sending ASSOC frame\n");
1674 else if (ieee80211_is_reassoc_req(fc))
1675 D_TX("Sending REASSOC frame\n");
1676#endif
1677
1678 hdr_len = ieee80211_hdrlen(fc);
1679
1680 /* For management frames use broadcast id to do not break aggregation */
1681 if (!ieee80211_is_data(fc))
b16db50a 1682 sta_id = il->hw_params.bcast_id;
a1751b22
SG		 1683 else {
1684 /* Find idx into station table for destination station */
36323f81 1685 sta_id = il_sta_id_or_broadcast(il, sta);
a1751b22
SG		 1686
1687 if (sta_id == IL_INVALID_STATION) {
e7392364 1688 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
a1751b22
SG		 1689 goto drop_unlock;
1690 }
1691 }
1692
1693 D_TX("station Id %d\n", sta_id);
1694
1695 if (sta)
1696 sta_priv = (void *)sta->drv_priv;
1697
1698 if (sta_priv && sta_priv->asleep &&
02f2f1a9 1699 (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) {
a1751b22
SG		 1700 /*
1701 * This sends an asynchronous command to the device,
1702 * but we can rely on it being processed before the
1703 * next frame is processed -- and the next frame to
1704 * this station is the one that will consume this
1705 * counter.
1706 * For now set the counter to just 1 since we do not
1707 * support uAPSD yet.
1708 */
1709 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1710 }
1711
d1e14e94
SG		 1712 /* FIXME: remove me ? */
1713 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1714
eb123af3
SG		 1715 /* Access category (AC) is also the queue number */
1716 txq_id = skb_get_queue_mapping(skb);
a1751b22
SG		 1717
1718 /* irqs already disabled/saved above when locking il->lock */
1719 spin_lock(&il->sta_lock);
1720
1721 if (ieee80211_is_data_qos(fc)) {
1722 qc = ieee80211_get_qos_ctl(hdr);
1723 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1724 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1725 spin_unlock(&il->sta_lock);
1726 goto drop_unlock;
1727 }
1728 seq_number = il->stations[sta_id].tid[tid].seq_number;
1729 seq_number &= IEEE80211_SCTL_SEQ;
e7392364
SG		 1730 hdr->seq_ctrl =
1731 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
a1751b22
SG		 1732 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1733 seq_number += 0x10;
1734 /* aggregation is on for this <sta,tid> */
1735 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1736 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1737 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1738 is_agg = true;
1739 }
1740 }
1741
1742 txq = &il->txq[txq_id];
1743 q = &txq->q;
1744
1745 if (unlikely(il_queue_space(q) < q->high_mark)) {
1746 spin_unlock(&il->sta_lock);
1747 goto drop_unlock;
1748 }
1749
1750 if (ieee80211_is_data_qos(fc)) {
1751 il->stations[sta_id].tid[tid].tfds_in_queue++;
1752 if (!ieee80211_has_morefrags(fc))
1753 il->stations[sta_id].tid[tid].seq_number = seq_number;
1754 }
1755
1756 spin_unlock(&il->sta_lock);
1757
00ea99e1 1758 txq->skbs[q->write_ptr] = skb;
a1751b22
SG		 1759
1760 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1761 out_cmd = txq->cmd[q->write_ptr];
1762 out_meta = &txq->meta[q->write_ptr];
1763 tx_cmd = &out_cmd->cmd.tx;
1764 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1765 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1766
1767 /*
1768 * Set up the Tx-command (not MAC!) header.
1769 * Store the chosen Tx queue and TFD idx within the sequence field;
1770 * after Tx, uCode's Tx response will return this value so driver can
1771 * locate the frame within the tx queue and do post-tx processing.
1772 */
4d69c752 1773 out_cmd->hdr.cmd = C_TX;
e7392364
SG		 1774 out_cmd->hdr.sequence =
1775 cpu_to_le16((u16)
1776 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
a1751b22
SG		 1777
1778 /* Copy MAC header from skb into command buffer */
1779 memcpy(tx_cmd->hdr, hdr, hdr_len);
1780
a1751b22 1781 /* Total # bytes to be transmitted */
e7392364 1782 len = (u16) skb->len;
a1751b22
SG		 1783 tx_cmd->len = cpu_to_le16(len);
1784
1785 if (info->control.hw_key)
1786 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1787
1788 /* TODO need this for burst mode later on */
1789 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
a1751b22 1790
36323f81 1791 il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc);
a1751b22
SG		 1792
1793 il_update_stats(il, true, fc, len);
1794 /*
1795 * Use the first empty entry in this queue's command buffer array
1796 * to contain the Tx command and MAC header concatenated together
1797 * (payload data will be in another buffer).
1798 * Size of this varies, due to varying MAC header length.
1799 * If end is not dword aligned, we'll have 2 extra bytes at the end
1800 * of the MAC header (device reads on dword boundaries).
1801 * We'll tell device about this padding later.
1802 */
e7392364 1803 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
a1751b22
SG		 1804 firstlen = (len + 3) & ~3;
1805
1806 /* Tell NIC about any 2-byte padding after MAC header */
1807 if (firstlen != len)
1808 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1809
1810 /* Physical address of this Tx command's header (not MAC header!),
1811 * within command buffer array. */
e7392364
SG		 1812 txcmd_phys =
1813 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1814 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1815 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1816 dma_unmap_len_set(out_meta, len, firstlen);
1817 /* Add buffer containing Tx command and MAC(!) header to TFD's
1818 * first entry */
1600b875 1819 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
a1751b22
SG		 1820
1821 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1822 txq->need_update = 1;
1823 } else {
1824 wait_write_ptr = 1;
1825 txq->need_update = 0;
1826 }
1827
1828 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1829 * if any (802.11 null frames have no payload). */
1830 secondlen = skb->len - hdr_len;
1831 if (secondlen > 0) {
e7392364
SG		 1832 phys_addr =
1833 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1834 PCI_DMA_TODEVICE);
1600b875
SG		 1835 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen,
1836 0, 0);
a1751b22
SG		 1837 }
1838
e7392364
SG		 1839 scratch_phys =
1840 txcmd_phys + sizeof(struct il_cmd_header) +
1841 offsetof(struct il_tx_cmd, scratch);
a1751b22
SG		 1842
1843 /* take back ownership of DMA buffer to enable update */
e7392364
SG		 1844 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1845 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1846 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1847 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1848
e7392364 1849 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
a1751b22 1850 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
e7392364
SG		 1851 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1852 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
a1751b22
SG		 1853
1854 /* Set up entry for this TFD in Tx byte-count array */
1855 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1600b875 1856 il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len));
a1751b22 1857
e7392364
SG		 1858 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1859 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1860
1861 /* Tell device the write idx *just past* this latest filled TFD */
1862 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1863 il_txq_update_write_ptr(il, txq);
1864 spin_unlock_irqrestore(&il->lock, flags);
1865
1866 /*
1867 * At this point the frame is "transmitted" successfully
1868 * and we will get a TX status notification eventually,
1869 * regardless of the value of ret. "ret" only indicates
1870 * whether or not we should update the write pointer.
1871 */
1872
1873 /*
1874 * Avoid atomic ops if it isn't an associated client.
1875 * Also, if this is a packet for aggregation, don't
1876 * increase the counter because the ucode will stop
1877 * aggregation queues when their respective station
1878 * goes to sleep.
1879 */
1880 if (sta_priv && sta_priv->client && !is_agg)
1881 atomic_inc(&sta_priv->pending_frames);
1882
1883 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1884 if (wait_write_ptr) {
1885 spin_lock_irqsave(&il->lock, flags);
1886 txq->need_update = 1;
1887 il_txq_update_write_ptr(il, txq);
1888 spin_unlock_irqrestore(&il->lock, flags);
1889 } else {
1890 il_stop_queue(il, txq);
1891 }
1892 }
1893
1894 return 0;
1895
1896drop_unlock:
1897 spin_unlock_irqrestore(&il->lock, flags);
1898 return -1;
1899}
1900
e7392364
SG		 1901static inline int
1902il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
a1751b22 1903{
e7392364
SG		 1904 ptr->addr =
1905 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL);
a1751b22
SG		 1906 if (!ptr->addr)
1907 return -ENOMEM;
1908 ptr->size = size;
1909 return 0;
1910}
1911
e7392364
SG		 1912static inline void
1913il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
a1751b22
SG		 1914{
1915 if (unlikely(!ptr->addr))
1916 return;
1917
1918 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1919 memset(ptr, 0, sizeof(*ptr));
1920}
1921
1922/**
1923 * il4965_hw_txq_ctx_free - Free TXQ Context
1924 *
1925 * Destroy all TX DMA queues and structures
1926 */
e7392364
SG		 1927void
1928il4965_hw_txq_ctx_free(struct il_priv *il)
a1751b22
SG		 1929{
1930 int txq_id;
1931
1932 /* Tx queues */
1933 if (il->txq) {
1934 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1935 if (txq_id == il->cmd_queue)
1936 il_cmd_queue_free(il);
1937 else
1938 il_tx_queue_free(il, txq_id);
1939 }
1940 il4965_free_dma_ptr(il, &il->kw);
1941
1942 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1943
1944 /* free tx queue structure */
6668e4eb 1945 il_free_txq_mem(il);
a1751b22
SG		 1946}
1947
1948/**
1949 * il4965_txq_ctx_alloc - allocate TX queue context
1950 * Allocate all Tx DMA structures and initialize them
1951 *
1952 * @param il
1953 * @return error code
1954 */
e7392364
SG		 1955int
1956il4965_txq_ctx_alloc(struct il_priv *il)
a1751b22 1957{
d87c771f 1958 int ret, txq_id;
a1751b22
SG		 1959 unsigned long flags;
1960
1961 /* Free all tx/cmd queues and keep-warm buffer */
1962 il4965_hw_txq_ctx_free(il);
1963
e7392364
SG		 1964 ret =
1965 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1966 il->hw_params.scd_bc_tbls_size);
a1751b22
SG		 1967 if (ret) {
1968 IL_ERR("Scheduler BC Table allocation failed\n");
1969 goto error_bc_tbls;
1970 }
1971 /* Alloc keep-warm buffer */
1972 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1973 if (ret) {
1974 IL_ERR("Keep Warm allocation failed\n");
1975 goto error_kw;
1976 }
1977
1978 /* allocate tx queue structure */
1979 ret = il_alloc_txq_mem(il);
1980 if (ret)
1981 goto error;
1982
1983 spin_lock_irqsave(&il->lock, flags);
1984
1985 /* Turn off all Tx DMA fifos */
1986 il4965_txq_set_sched(il, 0);
1987
1988 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 1989 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 1990
1991 spin_unlock_irqrestore(&il->lock, flags);
1992
1993 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1994 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
d87c771f 1995 ret = il_tx_queue_init(il, txq_id);
a1751b22
SG		 1996 if (ret) {
1997 IL_ERR("Tx %d queue init failed\n", txq_id);
1998 goto error;
1999 }
2000 }
2001
2002 return ret;
2003
e7392364 2004error:
a1751b22
SG		 2005 il4965_hw_txq_ctx_free(il);
2006 il4965_free_dma_ptr(il, &il->kw);
e7392364 2007error_kw:
a1751b22 2008 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
e7392364 2009error_bc_tbls:
a1751b22
SG		 2010 return ret;
2011}
2012
e7392364
SG		 2013void
2014il4965_txq_ctx_reset(struct il_priv *il)
a1751b22 2015{
d87c771f 2016 int txq_id;
a1751b22
SG		 2017 unsigned long flags;
2018
2019 spin_lock_irqsave(&il->lock, flags);
2020
2021 /* Turn off all Tx DMA fifos */
2022 il4965_txq_set_sched(il, 0);
a1751b22 2023 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2024 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2025
2026 spin_unlock_irqrestore(&il->lock, flags);
2027
2028 /* Alloc and init all Tx queues, including the command queue (#4) */
d87c771f
SG		 2029 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2030 il_tx_queue_reset(il, txq_id);
a1751b22
SG		 2031}
2032
e7392364 2033void
775ed8ab 2034il4965_txq_ctx_unmap(struct il_priv *il)
a1751b22 2035{
775ed8ab 2036 int txq_id;
a1751b22
SG		 2037
2038 if (!il->txq)
2039 return;
2040
2041 /* Unmap DMA from host system and free skb's */
2042 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2043 if (txq_id == il->cmd_queue)
2044 il_cmd_queue_unmap(il);
2045 else
2046 il_tx_queue_unmap(il, txq_id);
2047}
2048
775ed8ab
SG		 2049/**
2050 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2051 */
2052void
2053il4965_txq_ctx_stop(struct il_priv *il)
2054{
2055 int ch, ret;
2056
2057 _il_wr_prph(il, IL49_SCD_TXFACT, 0);
2058
2059 /* Stop each Tx DMA channel, and wait for it to be idle */
2060 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2061 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2062 ret =
2063 _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
2064 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2065 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2066 1000);
2067 if (ret < 0)
2068 IL_ERR("Timeout stopping DMA channel %d [0x%08x]",
2069 ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
2070 }
2071}
2072
a1751b22
SG		 2073/*
2074 * Find first available (lowest unused) Tx Queue, mark it "active".
2075 * Called only when finding queue for aggregation.
2076 * Should never return anything < 7, because they should already
2077 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2078 */
e7392364
SG		 2079static int
2080il4965_txq_ctx_activate_free(struct il_priv *il)
a1751b22
SG		 2081{
2082 int txq_id;
2083
2084 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2085 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2086 return txq_id;
2087 return -1;
2088}
2089
2090/**
2091 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2092 */
e7392364
SG		 2093static void
2094il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
a1751b22
SG		 2095{
2096 /* Simply stop the queue, but don't change any configuration;
2097 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
e7392364 2098 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 2099 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2100 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
a1751b22
SG		 2101}
2102
2103/**
2104 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2105 */
e7392364
SG		 2106static int
2107il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
a1751b22
SG		 2108{
2109 u32 tbl_dw_addr;
2110 u32 tbl_dw;
2111 u16 scd_q2ratid;
2112
2113 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2114
e7392364
SG		 2115 tbl_dw_addr =
2116 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
a1751b22
SG		 2117
2118 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2119
2120 if (txq_id & 0x1)
2121 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2122 else
2123 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2124
2125 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2126
2127 return 0;
2128}
2129
2130/**
2131 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2132 *
2133 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2134 * i.e. it must be one of the higher queues used for aggregation
2135 */
e7392364
SG		 2136static int
2137il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2138 int tid, u16 ssn_idx)
a1751b22
SG		 2139{
2140 unsigned long flags;
2141 u16 ra_tid;
2142 int ret;
2143
2144 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2145 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2146 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2147 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2148 txq_id, IL49_FIRST_AMPDU_QUEUE,
2149 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2150 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2151 return -EINVAL;
2152 }
2153
2154 ra_tid = BUILD_RAxTID(sta_id, tid);
2155
2156 /* Modify device's station table to Tx this TID */
2157 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2158 if (ret)
2159 return ret;
2160
2161 spin_lock_irqsave(&il->lock, flags);
2162
2163 /* Stop this Tx queue before configuring it */
2164 il4965_tx_queue_stop_scheduler(il, txq_id);
2165
2166 /* Map receiver-address / traffic-ID to this queue */
2167 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2168
2169 /* Set this queue as a chain-building queue */
2170 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2171
2172 /* Place first TFD at idx corresponding to start sequence number.
2173 * Assumes that ssn_idx is valid (!= 0xFFF) */
2174 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2175 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2176 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2177
2178 /* Set up Tx win size and frame limit for this queue */
2179 il_write_targ_mem(il,
e7392364
SG		 2180 il->scd_base_addr +
2181 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2182 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2183 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
a1751b22 2184
e7392364
SG		 2185 il_write_targ_mem(il,
2186 il->scd_base_addr +
2187 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2188 (SCD_FRAME_LIMIT <<
2189 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2190 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
a1751b22
SG		 2191
2192 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2193
2194 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2195 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2196
2197 spin_unlock_irqrestore(&il->lock, flags);
2198
2199 return 0;
2200}
2201
e7392364
SG		 2202int
2203il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2204 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
a1751b22
SG		 2205{
2206 int sta_id;
2207 int tx_fifo;
2208 int txq_id;
2209 int ret;
2210 unsigned long flags;
2211 struct il_tid_data *tid_data;
2212
83007196
SG		 2213 /* FIXME: warning if tx fifo not found ? */
2214 tx_fifo = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2215 if (unlikely(tx_fifo < 0))
2216 return tx_fifo;
2217
53611e05 2218 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
a1751b22
SG		 2219
2220 sta_id = il_sta_id(sta);
2221 if (sta_id == IL_INVALID_STATION) {
2222 IL_ERR("Start AGG on invalid station\n");
2223 return -ENXIO;
2224 }
2225 if (unlikely(tid >= MAX_TID_COUNT))
2226 return -EINVAL;
2227
2228 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2229 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2230 return -ENXIO;
2231 }
2232
2233 txq_id = il4965_txq_ctx_activate_free(il);
2234 if (txq_id == -1) {
2235 IL_ERR("No free aggregation queue available\n");
2236 return -ENXIO;
2237 }
2238
2239 spin_lock_irqsave(&il->sta_lock, flags);
2240 tid_data = &il->stations[sta_id].tid[tid];
2241 *ssn = SEQ_TO_SN(tid_data->seq_number);
2242 tid_data->agg.txq_id = txq_id;
e7392364 2243 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
a1751b22
SG		 2244 spin_unlock_irqrestore(&il->sta_lock, flags);
2245
e7392364 2246 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
a1751b22
SG		 2247 if (ret)
2248 return ret;
2249
2250 spin_lock_irqsave(&il->sta_lock, flags);
2251 tid_data = &il->stations[sta_id].tid[tid];
2252 if (tid_data->tfds_in_queue == 0) {
2253 D_HT("HW queue is empty\n");
2254 tid_data->agg.state = IL_AGG_ON;
2255 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2256 } else {
e7392364
SG		 2257 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2258 tid_data->tfds_in_queue);
a1751b22
SG		 2259 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2260 }
2261 spin_unlock_irqrestore(&il->sta_lock, flags);
2262 return ret;
2263}
2264
2265/**
2266 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2267 * il->lock must be held by the caller
2268 */
e7392364
SG		 2269static int
2270il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
a1751b22
SG		 2271{
2272 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2273 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2274 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2275 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2276 txq_id, IL49_FIRST_AMPDU_QUEUE,
2277 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2278 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2279 return -EINVAL;
2280 }
2281
2282 il4965_tx_queue_stop_scheduler(il, txq_id);
2283
e7392364 2284 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
a1751b22
SG		 2285
2286 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2287 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2288 /* supposes that ssn_idx is valid (!= 0xFFF) */
2289 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2290
e7392364 2291 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
a1751b22
SG		 2292 il_txq_ctx_deactivate(il, txq_id);
2293 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2294
2295 return 0;
2296}
2297
e7392364
SG		 2298int
2299il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2300 struct ieee80211_sta *sta, u16 tid)
a1751b22
SG		 2301{
2302 int tx_fifo_id, txq_id, sta_id, ssn;
2303 struct il_tid_data *tid_data;
2304 int write_ptr, read_ptr;
2305 unsigned long flags;
2306
83007196
SG		 2307 /* FIXME: warning if tx_fifo_id not found ? */
2308 tx_fifo_id = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2309 if (unlikely(tx_fifo_id < 0))
2310 return tx_fifo_id;
2311
2312 sta_id = il_sta_id(sta);
2313
2314 if (sta_id == IL_INVALID_STATION) {
2315 IL_ERR("Invalid station for AGG tid %d\n", tid);
2316 return -ENXIO;
2317 }
2318
2319 spin_lock_irqsave(&il->sta_lock, flags);
2320
2321 tid_data = &il->stations[sta_id].tid[tid];
2322 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2323 txq_id = tid_data->agg.txq_id;
2324
2325 switch (il->stations[sta_id].tid[tid].agg.state) {
2326 case IL_EMPTYING_HW_QUEUE_ADDBA:
2327 /*
2328 * This can happen if the peer stops aggregation
2329 * again before we've had a chance to drain the
2330 * queue we selected previously, i.e. before the
2331 * session was really started completely.
2332 */
2333 D_HT("AGG stop before setup done\n");
2334 goto turn_off;
2335 case IL_AGG_ON:
2336 break;
2337 default:
2338 IL_WARN("Stopping AGG while state not ON or starting\n");
2339 }
2340
2341 write_ptr = il->txq[txq_id].q.write_ptr;
2342 read_ptr = il->txq[txq_id].q.read_ptr;
2343
2344 /* The queue is not empty */
2345 if (write_ptr != read_ptr) {
2346 D_HT("Stopping a non empty AGG HW QUEUE\n");
2347 il->stations[sta_id].tid[tid].agg.state =
e7392364 2348 IL_EMPTYING_HW_QUEUE_DELBA;
a1751b22
SG		 2349 spin_unlock_irqrestore(&il->sta_lock, flags);
2350 return 0;
2351 }
2352
2353 D_HT("HW queue is empty\n");
e7392364 2354turn_off:
a1751b22
SG		 2355 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2356
2357 /* do not restore/save irqs */
2358 spin_unlock(&il->sta_lock);
2359 spin_lock(&il->lock);
2360
2361 /*
2362 * the only reason this call can fail is queue number out of range,
2363 * which can happen if uCode is reloaded and all the station
2364 * information are lost. if it is outside the range, there is no need
2365 * to deactivate the uCode queue, just return "success" to allow
2366 * mac80211 to clean up it own data.
2367 */
2368 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2369 spin_unlock_irqrestore(&il->lock, flags);
2370
2371 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2372
2373 return 0;
2374}
2375
e7392364
SG		 2376int
2377il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
a1751b22
SG		 2378{
2379 struct il_queue *q = &il->txq[txq_id].q;
2380 u8 *addr = il->stations[sta_id].sta.sta.addr;
2381 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
a1751b22
SG		 2382
2383 lockdep_assert_held(&il->sta_lock);
2384
2385 switch (il->stations[sta_id].tid[tid].agg.state) {
2386 case IL_EMPTYING_HW_QUEUE_DELBA:
2387 /* We are reclaiming the last packet of the */
2388 /* aggregated HW queue */
e7392364 2389 if (txq_id == tid_data->agg.txq_id &&
a1751b22
SG		 2390 q->read_ptr == q->write_ptr) {
2391 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
83007196 2392 int tx_fifo = il4965_get_fifo_from_tid(tid);
e7392364 2393 D_HT("HW queue empty: continue DELBA flow\n");
a1751b22
SG		 2394 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2395 tid_data->agg.state = IL_AGG_OFF;
83007196 2396 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2397 }
2398 break;
2399 case IL_EMPTYING_HW_QUEUE_ADDBA:
2400 /* We are reclaiming the last packet of the queue */
2401 if (tid_data->tfds_in_queue == 0) {
e7392364 2402 D_HT("HW queue empty: continue ADDBA flow\n");
a1751b22 2403 tid_data->agg.state = IL_AGG_ON;
83007196 2404 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2405 }
2406 break;
2407 }
2408
2409 return 0;
2410}
2411
e7392364 2412static void
83007196 2413il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
a1751b22
SG		 2414{
2415 struct ieee80211_sta *sta;
2416 struct il_station_priv *sta_priv;
2417
2418 rcu_read_lock();
83007196 2419 sta = ieee80211_find_sta(il->vif, addr1);
a1751b22
SG		 2420 if (sta) {
2421 sta_priv = (void *)sta->drv_priv;
2422 /* avoid atomic ops if this isn't a client */
2423 if (sta_priv->client &&
2424 atomic_dec_return(&sta_priv->pending_frames) == 0)
2425 ieee80211_sta_block_awake(il->hw, sta, false);
2426 }
2427 rcu_read_unlock();
2428}
2429
2430static void
00ea99e1 2431il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
a1751b22 2432{
00ea99e1 2433 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
a1751b22
SG		 2434
2435 if (!is_agg)
83007196 2436 il4965_non_agg_tx_status(il, hdr->addr1);
a1751b22 2437
00ea99e1 2438 ieee80211_tx_status_irqsafe(il->hw, skb);
a1751b22
SG		 2439}
2440
e7392364
SG		 2441int
2442il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
a1751b22
SG		 2443{
2444 struct il_tx_queue *txq = &il->txq[txq_id];
2445 struct il_queue *q = &txq->q;
a1751b22
SG		 2446 int nfreed = 0;
2447 struct ieee80211_hdr *hdr;
00ea99e1 2448 struct sk_buff *skb;
a1751b22
SG		 2449
2450 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2451 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 2452 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2453 q->write_ptr, q->read_ptr);
a1751b22
SG		 2454 return 0;
2455 }
2456
e7392364 2457 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
a1751b22
SG		 2458 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2459
00ea99e1 2460 skb = txq->skbs[txq->q.read_ptr];
a1751b22 2461
00ea99e1 2462 if (WARN_ON_ONCE(skb == NULL))
a1751b22
SG		 2463 continue;
2464
00ea99e1 2465 hdr = (struct ieee80211_hdr *) skb->data;
a1751b22
SG		 2466 if (ieee80211_is_data_qos(hdr->frame_control))
2467 nfreed++;
2468
00ea99e1 2469 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
a1751b22 2470
00ea99e1 2471 txq->skbs[txq->q.read_ptr] = NULL;
1600b875 2472 il->ops->txq_free_tfd(il, txq);
a1751b22
SG		 2473 }
2474 return nfreed;
2475}
2476
2477/**
2478 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2479 *
2480 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2481 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2482 */
e7392364
SG		 2483static int
2484il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2485 struct il_compressed_ba_resp *ba_resp)
a1751b22
SG		 2486{
2487 int i, sh, ack;
2488 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2489 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2490 int successes = 0;
2491 struct ieee80211_tx_info *info;
2492 u64 bitmap, sent_bitmap;
2493
e7392364 2494 if (unlikely(!agg->wait_for_ba)) {
a1751b22
SG		 2495 if (unlikely(ba_resp->bitmap))
2496 IL_ERR("Received BA when not expected\n");
2497 return -EINVAL;
2498 }
2499
2500 /* Mark that the expected block-ack response arrived */
2501 agg->wait_for_ba = 0;
e7392364 2502 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
a1751b22
SG		 2503
2504 /* Calculate shift to align block-ack bits with our Tx win bits */
2505 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
e7392364 2506 if (sh < 0) /* tbw something is wrong with indices */
a1751b22
SG		 2507 sh += 0x100;
2508
2509 if (agg->frame_count > (64 - sh)) {
2510 D_TX_REPLY("more frames than bitmap size");
2511 return -1;
2512 }
2513
2514 /* don't use 64-bit values for now */
2515 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2516
2517 /* check for success or failure according to the
2518 * transmitted bitmap and block-ack bitmap */
2519 sent_bitmap = bitmap & agg->bitmap;
2520
2521 /* For each frame attempted in aggregation,
2522 * update driver's record of tx frame's status. */
2523 i = 0;
2524 while (sent_bitmap) {
2525 ack = sent_bitmap & 1ULL;
2526 successes += ack;
e7392364
SG		 2527 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2528 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
a1751b22
SG		 2529 sent_bitmap >>= 1;
2530 ++i;
2531 }
2532
e7392364 2533 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
a1751b22 2534
00ea99e1 2535 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
a1751b22
SG		 2536 memset(&info->status, 0, sizeof(info->status));
2537 info->flags |= IEEE80211_TX_STAT_ACK;
2538 info->flags |= IEEE80211_TX_STAT_AMPDU;
2539 info->status.ampdu_ack_len = successes;
2540 info->status.ampdu_len = agg->frame_count;
2541 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2542
2543 return 0;
2544}
2545
3dfea27d
SG		 2546static inline bool
2547il4965_is_tx_success(u32 status)
2548{
2549 status &= TX_STATUS_MSK;
2550 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2551}
2552
2553static u8
2554il4965_find_station(struct il_priv *il, const u8 *addr)
2555{
2556 int i;
2557 int start = 0;
2558 int ret = IL_INVALID_STATION;
2559 unsigned long flags;
2560
2561 if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2562 start = IL_STA_ID;
2563
2564 if (is_broadcast_ether_addr(addr))
2565 return il->hw_params.bcast_id;
2566
2567 spin_lock_irqsave(&il->sta_lock, flags);
2568 for (i = start; i < il->hw_params.max_stations; i++)
2569 if (il->stations[i].used &&
2e42e474 2570 ether_addr_equal(il->stations[i].sta.sta.addr, addr)) {
3dfea27d
SG		 2571 ret = i;
2572 goto out;
2573 }
2574
2575 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2576
2577out:
2578 /*
2579 * It may be possible that more commands interacting with stations
2580 * arrive before we completed processing the adding of
2581 * station
2582 */
2583 if (ret != IL_INVALID_STATION &&
2584 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2585 ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2586 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2587 IL_ERR("Requested station info for sta %d before ready.\n",
2588 ret);
2589 ret = IL_INVALID_STATION;
2590 }
2591 spin_unlock_irqrestore(&il->sta_lock, flags);
2592 return ret;
2593}
2594
2595static int
2596il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2597{
2598 if (il->iw_mode == NL80211_IFTYPE_STATION)
2599 return IL_AP_ID;
2600 else {
2601 u8 *da = ieee80211_get_DA(hdr);
2602
2603 return il4965_find_station(il, da);
2604 }
2605}
2606
2607static inline u32
2608il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2609{
2610 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
2611}
2612
2613static inline u32
2614il4965_tx_status_to_mac80211(u32 status)
2615{
2616 status &= TX_STATUS_MSK;
2617
2618 switch (status) {
2619 case TX_STATUS_SUCCESS:
2620 case TX_STATUS_DIRECT_DONE:
2621 return IEEE80211_TX_STAT_ACK;
2622 case TX_STATUS_FAIL_DEST_PS:
2623 return IEEE80211_TX_STAT_TX_FILTERED;
2624 default:
2625 return 0;
2626 }
2627}
2628
2629/**
2630 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2631 */
2632static int
2633il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2634 struct il4965_tx_resp *tx_resp, int txq_id,
2635 u16 start_idx)
2636{
2637 u16 status;
2638 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2639 struct ieee80211_tx_info *info = NULL;
2640 struct ieee80211_hdr *hdr = NULL;
2641 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2642 int i, sh, idx;
2643 u16 seq;
2644 if (agg->wait_for_ba)
2645 D_TX_REPLY("got tx response w/o block-ack\n");
2646
2647 agg->frame_count = tx_resp->frame_count;
2648 agg->start_idx = start_idx;
2649 agg->rate_n_flags = rate_n_flags;
2650 agg->bitmap = 0;
2651
2652 /* num frames attempted by Tx command */
2653 if (agg->frame_count == 1) {
2654 /* Only one frame was attempted; no block-ack will arrive */
2655 status = le16_to_cpu(frame_status[0].status);
2656 idx = start_idx;
2657
2658 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2659 agg->frame_count, agg->start_idx, idx);
2660
2661 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2662 info->status.rates[0].count = tx_resp->failure_frame + 1;
2663 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2664 info->flags |= il4965_tx_status_to_mac80211(status);
2665 il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2666
2667 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2668 tx_resp->failure_frame);
2669 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2670
2671 agg->wait_for_ba = 0;
2672 } else {
2673 /* Two or more frames were attempted; expect block-ack */
2674 u64 bitmap = 0;
2675 int start = agg->start_idx;
2676 struct sk_buff *skb;
2677
2678 /* Construct bit-map of pending frames within Tx win */
2679 for (i = 0; i < agg->frame_count; i++) {
2680 u16 sc;
2681 status = le16_to_cpu(frame_status[i].status);
2682 seq = le16_to_cpu(frame_status[i].sequence);
2683 idx = SEQ_TO_IDX(seq);
2684 txq_id = SEQ_TO_QUEUE(seq);
2685
2686 if (status &
2687 (AGG_TX_STATE_FEW_BYTES_MSK |
2688 AGG_TX_STATE_ABORT_MSK))
2689 continue;
2690
2691 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2692 agg->frame_count, txq_id, idx);
2693
2694 skb = il->txq[txq_id].skbs[idx];
2695 if (WARN_ON_ONCE(skb == NULL))
2696 return -1;
2697 hdr = (struct ieee80211_hdr *) skb->data;
2698
2699 sc = le16_to_cpu(hdr->seq_ctrl);
2700 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2701 IL_ERR("BUG_ON idx doesn't match seq control"
2702 " idx=%d, seq_idx=%d, seq=%d\n", idx,
2703 SEQ_TO_SN(sc), hdr->seq_ctrl);
2704 return -1;
2705 }
2706
2707 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
2708 SEQ_TO_SN(sc));
2709
2710 sh = idx - start;
2711 if (sh > 64) {
2712 sh = (start - idx) + 0xff;
2713 bitmap = bitmap << sh;
2714 sh = 0;
2715 start = idx;
2716 } else if (sh < -64)
2717 sh = 0xff - (start - idx);
2718 else if (sh < 0) {
2719 sh = start - idx;
2720 start = idx;
2721 bitmap = bitmap << sh;
2722 sh = 0;
2723 }
2724 bitmap |= 1ULL << sh;
2725 D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2726 (unsigned long long)bitmap);
2727 }
2728
2729 agg->bitmap = bitmap;
2730 agg->start_idx = start;
2731 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2732 agg->frame_count, agg->start_idx,
2733 (unsigned long long)agg->bitmap);
2734
2735 if (bitmap)
2736 agg->wait_for_ba = 1;
2737 }
2738 return 0;
2739}
2740
2741/**
2742 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2743 */
2744static void
2745il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2746{
2747 struct il_rx_pkt *pkt = rxb_addr(rxb);
2748 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2749 int txq_id = SEQ_TO_QUEUE(sequence);
2750 int idx = SEQ_TO_IDX(sequence);
2751 struct il_tx_queue *txq = &il->txq[txq_id];
2752 struct sk_buff *skb;
2753 struct ieee80211_hdr *hdr;
2754 struct ieee80211_tx_info *info;
2755 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2756 u32 status = le32_to_cpu(tx_resp->u.status);
2757 int uninitialized_var(tid);
2758 int sta_id;
2759 int freed;
2760 u8 *qc = NULL;
2761 unsigned long flags;
2762
2763 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2764 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2765 "is out of range [0-%d] %d %d\n", txq_id, idx,
2766 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2767 return;
2768 }
2769
2770 txq->time_stamp = jiffies;
2771
2772 skb = txq->skbs[txq->q.read_ptr];
2773 info = IEEE80211_SKB_CB(skb);
2774 memset(&info->status, 0, sizeof(info->status));
2775
2776 hdr = (struct ieee80211_hdr *) skb->data;
2777 if (ieee80211_is_data_qos(hdr->frame_control)) {
2778 qc = ieee80211_get_qos_ctl(hdr);
2779 tid = qc[0] & 0xf;
2780 }
2781
2782 sta_id = il4965_get_ra_sta_id(il, hdr);
2783 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2784 IL_ERR("Station not known\n");
2785 return;
2786 }
2787
2788 spin_lock_irqsave(&il->sta_lock, flags);
2789 if (txq->sched_retry) {
2790 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2791 struct il_ht_agg *agg = NULL;
2792 WARN_ON(!qc);
2793
2794 agg = &il->stations[sta_id].tid[tid].agg;
2795
2796 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2797
2798 /* check if BAR is needed */
2799 if (tx_resp->frame_count == 1 &&
2800 !il4965_is_tx_success(status))
2801 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2802
2803 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2804 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2805 D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2806 "%d idx %d\n", scd_ssn, idx);
2807 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2808 if (qc)
2809 il4965_free_tfds_in_queue(il, sta_id, tid,
2810 freed);
2811
2812 if (il->mac80211_registered &&
2813 il_queue_space(&txq->q) > txq->q.low_mark &&
2814 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2815 il_wake_queue(il, txq);
2816 }
2817 } else {
2818 info->status.rates[0].count = tx_resp->failure_frame + 1;
2819 info->flags |= il4965_tx_status_to_mac80211(status);
2820 il4965_hwrate_to_tx_control(il,
2821 le32_to_cpu(tx_resp->rate_n_flags),
2822 info);
2823
2824 D_TX_REPLY("TXQ %d status %s (0x%08x) "
2825 "rate_n_flags 0x%x retries %d\n", txq_id,
2826 il4965_get_tx_fail_reason(status), status,
2827 le32_to_cpu(tx_resp->rate_n_flags),
2828 tx_resp->failure_frame);
2829
2830 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2831 if (qc && likely(sta_id != IL_INVALID_STATION))
2832 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2833 else if (sta_id == IL_INVALID_STATION)
2834 D_TX_REPLY("Station not known\n");
2835
2836 if (il->mac80211_registered &&
2837 il_queue_space(&txq->q) > txq->q.low_mark)
2838 il_wake_queue(il, txq);
2839 }
2840 if (qc && likely(sta_id != IL_INVALID_STATION))
2841 il4965_txq_check_empty(il, sta_id, tid, txq_id);
2842
2843 il4965_check_abort_status(il, tx_resp->frame_count, status);
2844
2845 spin_unlock_irqrestore(&il->sta_lock, flags);
2846}
2847
a1751b22
SG		 2848/**
2849 * translate ucode response to mac80211 tx status control values
2850 */
e7392364
SG		 2851void
2852il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2853 struct ieee80211_tx_info *info)
a1751b22 2854{
d748b464 2855 struct ieee80211_tx_rate *r = &info->status.rates[0];
a1751b22 2856
d748b464 2857 info->status.antenna =
e7392364 2858 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
a1751b22
SG		 2859 if (rate_n_flags & RATE_MCS_HT_MSK)
2860 r->flags |= IEEE80211_TX_RC_MCS;
2861 if (rate_n_flags & RATE_MCS_GF_MSK)
2862 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2863 if (rate_n_flags & RATE_MCS_HT40_MSK)
2864 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2865 if (rate_n_flags & RATE_MCS_DUP_MSK)
2866 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2867 if (rate_n_flags & RATE_MCS_SGI_MSK)
2868 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2869 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2870}
2871
2872/**
6e9848b4 2873 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
a1751b22
SG		 2874 *
2875 * Handles block-acknowledge notification from device, which reports success
2876 * of frames sent via aggregation.
2877 */
e7392364
SG		 2878void
2879il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 2880{
2881 struct il_rx_pkt *pkt = rxb_addr(rxb);
2882 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2883 struct il_tx_queue *txq = NULL;
2884 struct il_ht_agg *agg;
2885 int idx;
2886 int sta_id;
2887 int tid;
2888 unsigned long flags;
2889
2890 /* "flow" corresponds to Tx queue */
2891 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2892
2893 /* "ssn" is start of block-ack Tx win, corresponds to idx
2894 * (in Tx queue's circular buffer) of first TFD/frame in win */
2895 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2896
2897 if (scd_flow >= il->hw_params.max_txq_num) {
e7392364 2898 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
a1751b22
SG		 2899 return;
2900 }
2901
2902 txq = &il->txq[scd_flow];
2903 sta_id = ba_resp->sta_id;
2904 tid = ba_resp->tid;
2905 agg = &il->stations[sta_id].tid[tid].agg;
2906 if (unlikely(agg->txq_id != scd_flow)) {
2907 /*
2908 * FIXME: this is a uCode bug which need to be addressed,
2909 * log the information and return for now!
2910 * since it is possible happen very often and in order
2911 * not to fill the syslog, don't enable the logging by default
2912 */
e7392364
SG		 2913 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2914 scd_flow, agg->txq_id);
a1751b22
SG		 2915 return;
2916 }
2917
2918 /* Find idx just before block-ack win */
2919 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2920
2921 spin_lock_irqsave(&il->sta_lock, flags);
2922
e7392364 2923 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
1722f8e1 2924 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
e7392364
SG		 2925 ba_resp->sta_id);
2926 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2927 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2928 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2929 ba_resp->scd_flow, ba_resp->scd_ssn);
2930 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2931 (unsigned long long)agg->bitmap);
a1751b22
SG		 2932
2933 /* Update driver's record of ACK vs. not for each frame in win */
2934 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2935
2936 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2937 * block-ack win (we assume that they've been successfully
2938 * transmitted ... if not, it's too late anyway). */
2939 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2940 /* calculate mac80211 ampdu sw queue to wake */
2941 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2942 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2943
2944 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2945 il->mac80211_registered &&
2946 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2947 il_wake_queue(il, txq);
2948
2949 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2950 }
2951
2952 spin_unlock_irqrestore(&il->sta_lock, flags);
2953}
2954
2955#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2956const char *
2957il4965_get_tx_fail_reason(u32 status)
a1751b22
SG		 2958{
2959#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2960#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2961
2962 switch (status & TX_STATUS_MSK) {
2963 case TX_STATUS_SUCCESS:
2964 return "SUCCESS";
e7392364
SG		 2965 TX_STATUS_POSTPONE(DELAY);
2966 TX_STATUS_POSTPONE(FEW_BYTES);
2967 TX_STATUS_POSTPONE(QUIET_PERIOD);
2968 TX_STATUS_POSTPONE(CALC_TTAK);
2969 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2970 TX_STATUS_FAIL(SHORT_LIMIT);
2971 TX_STATUS_FAIL(LONG_LIMIT);
2972 TX_STATUS_FAIL(FIFO_UNDERRUN);
2973 TX_STATUS_FAIL(DRAIN_FLOW);
2974 TX_STATUS_FAIL(RFKILL_FLUSH);
2975 TX_STATUS_FAIL(LIFE_EXPIRE);
2976 TX_STATUS_FAIL(DEST_PS);
2977 TX_STATUS_FAIL(HOST_ABORTED);
2978 TX_STATUS_FAIL(BT_RETRY);
2979 TX_STATUS_FAIL(STA_INVALID);
2980 TX_STATUS_FAIL(FRAG_DROPPED);
2981 TX_STATUS_FAIL(TID_DISABLE);
2982 TX_STATUS_FAIL(FIFO_FLUSHED);
2983 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
2984 TX_STATUS_FAIL(PASSIVE_NO_RX);
2985 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
a1751b22
SG		 2986 }
2987
2988 return "UNKNOWN";
2989
2990#undef TX_STATUS_FAIL
2991#undef TX_STATUS_POSTPONE
2992}
2993#endif /* CONFIG_IWLEGACY_DEBUG */
2994
eb3cdfb7
SG		 2995static struct il_link_quality_cmd *
2996il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
2997{
2998 int i, r;
2999 struct il_link_quality_cmd *link_cmd;
3000 u32 rate_flags = 0;
3001 __le32 rate_n_flags;
3002
3003 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3004 if (!link_cmd) {
3005 IL_ERR("Unable to allocate memory for LQ cmd.\n");
3006 return NULL;
3007 }
3008 /* Set up the rate scaling to start at selected rate, fall back
3009 * all the way down to 1M in IEEE order, and then spin on 1M */
3010 if (il->band == IEEE80211_BAND_5GHZ)
3011 r = RATE_6M_IDX;
3012 else
3013 r = RATE_1M_IDX;
3014
3015 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3016 rate_flags |= RATE_MCS_CCK_MSK;
3017
e7392364
SG		 3018 rate_flags |=
3019 il4965_first_antenna(il->hw_params.
3020 valid_tx_ant) << RATE_MCS_ANT_POS;
616107ed 3021 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
eb3cdfb7
SG		 3022 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3023 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3024
3025 link_cmd->general_params.single_stream_ant_msk =
e7392364 3026 il4965_first_antenna(il->hw_params.valid_tx_ant);
eb3cdfb7
SG		 3027
3028 link_cmd->general_params.dual_stream_ant_msk =
e7392364
SG		 3029 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3030 valid_tx_ant);
eb3cdfb7
SG		 3031 if (!link_cmd->general_params.dual_stream_ant_msk) {
3032 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3033 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3034 link_cmd->general_params.dual_stream_ant_msk =
e7392364 3035 il->hw_params.valid_tx_ant;
eb3cdfb7
SG		 3036 }
3037
3038 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3039 link_cmd->agg_params.agg_time_limit =
e7392364 3040 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
eb3cdfb7
SG		 3041
3042 link_cmd->sta_id = sta_id;
3043
3044 return link_cmd;
3045}
3046
3047/*
3048 * il4965_add_bssid_station - Add the special IBSS BSSID station
3049 *
3050 * Function sleeps.
3051 */
3052int
83007196 3053il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
eb3cdfb7
SG		 3054{
3055 int ret;
3056 u8 sta_id;
3057 struct il_link_quality_cmd *link_cmd;
3058 unsigned long flags;
3059
3060 if (sta_id_r)
3061 *sta_id_r = IL_INVALID_STATION;
3062
83007196 3063 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
eb3cdfb7
SG		 3064 if (ret) {
3065 IL_ERR("Unable to add station %pM\n", addr);
3066 return ret;
3067 }
3068
3069 if (sta_id_r)
3070 *sta_id_r = sta_id;
3071
3072 spin_lock_irqsave(&il->sta_lock, flags);
3073 il->stations[sta_id].used |= IL_STA_LOCAL;
3074 spin_unlock_irqrestore(&il->sta_lock, flags);
3075
3076 /* Set up default rate scaling table in device's station table */
3077 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3078 if (!link_cmd) {
e7392364
SG		 3079 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3080 addr);
eb3cdfb7
SG		 3081 return -ENOMEM;
3082 }
3083
83007196 3084 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
eb3cdfb7
SG		 3085 if (ret)
3086 IL_ERR("Link quality command failed (%d)\n", ret);
3087
3088 spin_lock_irqsave(&il->sta_lock, flags);
3089 il->stations[sta_id].lq = link_cmd;
3090 spin_unlock_irqrestore(&il->sta_lock, flags);
3091
3092 return 0;
3093}
3094
e7392364 3095static int
83007196 3096il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
eb3cdfb7 3097{
d735f921 3098 int i;
eb3cdfb7
SG		 3099 u8 buff[sizeof(struct il_wep_cmd) +
3100 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3101 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
e7392364 3102 size_t cmd_size = sizeof(struct il_wep_cmd);
eb3cdfb7 3103 struct il_host_cmd cmd = {
d98e2942 3104 .id = C_WEPKEY,
eb3cdfb7
SG		 3105 .data = wep_cmd,
3106 .flags = CMD_SYNC,
3107 };
d735f921 3108 bool not_empty = false;
eb3cdfb7
SG		 3109
3110 might_sleep();
3111
e7392364
SG		 3112 memset(wep_cmd, 0,
3113 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
eb3cdfb7 3114
e7392364 3115 for (i = 0; i < WEP_KEYS_MAX; i++) {
d735f921
SG		 3116 u8 key_size = il->_4965.wep_keys[i].key_size;
3117
eb3cdfb7 3118 wep_cmd->key[i].key_idx = i;
d735f921 3119 if (key_size) {
eb3cdfb7 3120 wep_cmd->key[i].key_offset = i;
d735f921
SG		 3121 not_empty = true;
3122 } else
eb3cdfb7 3123 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
eb3cdfb7 3124
d735f921
SG		 3125 wep_cmd->key[i].key_size = key_size;
3126 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
eb3cdfb7
SG		 3127 }
3128
3129 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3130 wep_cmd->num_keys = WEP_KEYS_MAX;
3131
3132 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
eb3cdfb7
SG		 3133 cmd.len = cmd_size;
3134
3135 if (not_empty || send_if_empty)
3136 return il_send_cmd(il, &cmd);
3137 else
3138 return 0;
3139}
3140
e7392364 3141int
83007196 3142il4965_restore_default_wep_keys(struct il_priv *il)
eb3cdfb7
SG		 3143{
3144 lockdep_assert_held(&il->mutex);
3145
83007196 3146 return il4965_static_wepkey_cmd(il, false);
eb3cdfb7
SG		 3147}
3148
e7392364 3149int
83007196 3150il4965_remove_default_wep_key(struct il_priv *il,
e7392364 3151 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3152{
3153 int ret;
d735f921 3154 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3155
3156 lockdep_assert_held(&il->mutex);
3157
d735f921 3158 D_WEP("Removing default WEP key: idx=%d\n", idx);
eb3cdfb7 3159
d735f921 3160 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
eb3cdfb7 3161 if (il_is_rfkill(il)) {
e7392364 3162 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
eb3cdfb7
SG		 3163 /* but keys in device are clear anyway so return success */
3164 return 0;
3165 }
83007196 3166 ret = il4965_static_wepkey_cmd(il, 1);
d735f921 3167 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
eb3cdfb7
SG		 3168
3169 return ret;
3170}
3171
e7392364 3172int
83007196 3173il4965_set_default_wep_key(struct il_priv *il,
e7392364 3174 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3175{
3176 int ret;
d735f921
SG		 3177 int len = keyconf->keylen;
3178 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3179
3180 lockdep_assert_held(&il->mutex);
3181
d735f921 3182 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
eb3cdfb7
SG		 3183 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3184 return -EINVAL;
3185 }
3186
3187 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3188 keyconf->hw_key_idx = HW_KEY_DEFAULT;
8f9e5645 3189 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
eb3cdfb7 3190
d735f921
SG		 3191 il->_4965.wep_keys[idx].key_size = len;
3192 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
eb3cdfb7 3193
83007196 3194 ret = il4965_static_wepkey_cmd(il, false);
eb3cdfb7 3195
d735f921 3196 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
eb3cdfb7
SG		 3197 return ret;
3198}
3199
e7392364 3200static int
83007196 3201il4965_set_wep_dynamic_key_info(struct il_priv *il,
e7392364 3202 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3203{
3204 unsigned long flags;
3205 __le16 key_flags = 0;
3206 struct il_addsta_cmd sta_cmd;
3207
3208 lockdep_assert_held(&il->mutex);
3209
3210 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3211
3212 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3213 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3214 key_flags &= ~STA_KEY_FLG_INVALID;
3215
3216 if (keyconf->keylen == WEP_KEY_LEN_128)
3217 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3218
b16db50a 3219 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3220 key_flags |= STA_KEY_MULTICAST_MSK;
3221
3222 spin_lock_irqsave(&il->sta_lock, flags);
3223
3224 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3225 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3226 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3227
e7392364 3228 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3229
e7392364
SG		 3230 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3231 keyconf->keylen);
eb3cdfb7 3232
e7392364
SG		 3233 if ((il->stations[sta_id].sta.key.
3234 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3235 il->stations[sta_id].sta.key.key_offset =
e7392364 3236 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3237 /* else, we are overriding an existing key => no need to allocated room
3238 * in uCode. */
3239
3240 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3241 "no space for a new key");
eb3cdfb7
SG		 3242
3243 il->stations[sta_id].sta.key.key_flags = key_flags;
3244 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3245 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3246
3247 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3248 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3249 spin_unlock_irqrestore(&il->sta_lock, flags);
3250
3251 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3252}
3253
e7392364
SG		 3254static int
3255il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
e7392364 3256 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3257{
3258 unsigned long flags;
3259 __le16 key_flags = 0;
3260 struct il_addsta_cmd sta_cmd;
3261
3262 lockdep_assert_held(&il->mutex);
3263
3264 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3265 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3266 key_flags &= ~STA_KEY_FLG_INVALID;
3267
b16db50a 3268 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3269 key_flags |= STA_KEY_MULTICAST_MSK;
3270
3271 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3272
3273 spin_lock_irqsave(&il->sta_lock, flags);
3274 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3275 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3276
e7392364 3277 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3278
e7392364 3279 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3280
e7392364
SG		 3281 if ((il->stations[sta_id].sta.key.
3282 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3283 il->stations[sta_id].sta.key.key_offset =
e7392364 3284 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3285 /* else, we are overriding an existing key => no need to allocated room
3286 * in uCode. */
3287
3288 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3289 "no space for a new key");
eb3cdfb7
SG		 3290
3291 il->stations[sta_id].sta.key.key_flags = key_flags;
3292 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3293 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3294
3295 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3296 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3297 spin_unlock_irqrestore(&il->sta_lock, flags);
3298
3299 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3300}
3301
e7392364
SG		 3302static int
3303il4965_set_tkip_dynamic_key_info(struct il_priv *il,
e7392364 3304 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3305{
3306 unsigned long flags;
3307 int ret = 0;
3308 __le16 key_flags = 0;
3309
3310 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3311 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3312 key_flags &= ~STA_KEY_FLG_INVALID;
3313
b16db50a 3314 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3315 key_flags |= STA_KEY_MULTICAST_MSK;
3316
3317 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3318 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3319
3320 spin_lock_irqsave(&il->sta_lock, flags);
3321
3322 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3323 il->stations[sta_id].keyinfo.keylen = 16;
3324
e7392364
SG		 3325 if ((il->stations[sta_id].sta.key.
3326 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3327 il->stations[sta_id].sta.key.key_offset =
e7392364 3328 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3329 /* else, we are overriding an existing key => no need to allocated room
3330 * in uCode. */
3331
3332 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3333 "no space for a new key");
eb3cdfb7
SG		 3334
3335 il->stations[sta_id].sta.key.key_flags = key_flags;
3336
eb3cdfb7
SG		 3337 /* This copy is acutally not needed: we get the key with each TX */
3338 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3339
3340 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3341
3342 spin_unlock_irqrestore(&il->sta_lock, flags);
3343
3344 return ret;
3345}
3346
e7392364 3347void
83007196
SG		 3348il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3349 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
eb3cdfb7
SG		 3350{
3351 u8 sta_id;
3352 unsigned long flags;
3353 int i;
3354
3355 if (il_scan_cancel(il)) {
3356 /* cancel scan failed, just live w/ bad key and rely
3357 briefly on SW decryption */
3358 return;
3359 }
3360
83007196 3361 sta_id = il_sta_id_or_broadcast(il, sta);
eb3cdfb7
SG		 3362 if (sta_id == IL_INVALID_STATION)
3363 return;
3364
3365 spin_lock_irqsave(&il->sta_lock, flags);
3366
3367 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3368
3369 for (i = 0; i < 5; i++)
3370 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
e7392364 3371 cpu_to_le16(phase1key[i]);
eb3cdfb7
SG		 3372
3373 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3374 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3375
3376 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3377
3378 spin_unlock_irqrestore(&il->sta_lock, flags);
eb3cdfb7
SG		 3379}
3380
e7392364 3381int
83007196 3382il4965_remove_dynamic_key(struct il_priv *il,
e7392364 3383 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3384{
3385 unsigned long flags;
3386 u16 key_flags;
3387 u8 keyidx;
3388 struct il_addsta_cmd sta_cmd;
3389
3390 lockdep_assert_held(&il->mutex);
3391
d735f921 3392 il->_4965.key_mapping_keys--;
eb3cdfb7
SG		 3393
3394 spin_lock_irqsave(&il->sta_lock, flags);
3395 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3396 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3397
e7392364 3398 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
eb3cdfb7
SG		 3399
3400 if (keyconf->keyidx != keyidx) {
3401 /* We need to remove a key with idx different that the one
3402 * in the uCode. This means that the key we need to remove has
3403 * been replaced by another one with different idx.
3404 * Don't do anything and return ok
3405 */
3406 spin_unlock_irqrestore(&il->sta_lock, flags);
3407 return 0;
3408 }
3409
b48d9665 3410 if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) {
e7392364
SG		 3411 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3412 key_flags);
eb3cdfb7
SG		 3413 spin_unlock_irqrestore(&il->sta_lock, flags);
3414 return 0;
3415 }
3416
e7392364
SG		 3417 if (!test_and_clear_bit
3418 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
eb3cdfb7 3419 IL_ERR("idx %d not used in uCode key table.\n",
e7392364
SG		 3420 il->stations[sta_id].sta.key.key_offset);
3421 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3422 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
eb3cdfb7 3423 il->stations[sta_id].sta.key.key_flags =
e7392364 3424 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
b48d9665 3425 il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx;
eb3cdfb7
SG		 3426 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3427 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3428
3429 if (il_is_rfkill(il)) {
e7392364
SG		 3430 D_WEP
3431 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
eb3cdfb7
SG		 3432 spin_unlock_irqrestore(&il->sta_lock, flags);
3433 return 0;
3434 }
3435 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3436 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3437 spin_unlock_irqrestore(&il->sta_lock, flags);
3438
3439 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3440}
3441
e7392364 3442int
83007196
SG		 3443il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3444 u8 sta_id)
eb3cdfb7
SG		 3445{
3446 int ret;
3447
3448 lockdep_assert_held(&il->mutex);
3449
d735f921 3450 il->_4965.key_mapping_keys++;
eb3cdfb7
SG		 3451 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3452
3453 switch (keyconf->cipher) {
3454 case WLAN_CIPHER_SUITE_CCMP:
e7392364 3455 ret =
83007196 3456 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3457 break;
3458 case WLAN_CIPHER_SUITE_TKIP:
e7392364 3459 ret =
83007196 3460 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3461 break;
3462 case WLAN_CIPHER_SUITE_WEP40:
3463 case WLAN_CIPHER_SUITE_WEP104:
83007196 3464 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3465 break;
3466 default:
e7392364
SG		 3467 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3468 keyconf->cipher);
eb3cdfb7
SG		 3469 ret = -EINVAL;
3470 }
3471
e7392364
SG		 3472 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3473 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
eb3cdfb7
SG		 3474
3475 return ret;
3476}
3477
3478/**
3479 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3480 *
3481 * This adds the broadcast station into the driver's station table
3482 * and marks it driver active, so that it will be restored to the
3483 * device at the next best time.
3484 */
e7392364 3485int
83007196 3486il4965_alloc_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3487{
3488 struct il_link_quality_cmd *link_cmd;
3489 unsigned long flags;
3490 u8 sta_id;
3491
3492 spin_lock_irqsave(&il->sta_lock, flags);
83007196 3493 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
eb3cdfb7
SG		 3494 if (sta_id == IL_INVALID_STATION) {
3495 IL_ERR("Unable to prepare broadcast station\n");
3496 spin_unlock_irqrestore(&il->sta_lock, flags);
3497
3498 return -EINVAL;
3499 }
3500
3501 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3502 il->stations[sta_id].used |= IL_STA_BCAST;
3503 spin_unlock_irqrestore(&il->sta_lock, flags);
3504
3505 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3506 if (!link_cmd) {
e7392364
SG		 3507 IL_ERR
3508 ("Unable to initialize rate scaling for bcast station.\n");
eb3cdfb7
SG		 3509 return -ENOMEM;
3510 }
3511
3512 spin_lock_irqsave(&il->sta_lock, flags);
3513 il->stations[sta_id].lq = link_cmd;
3514 spin_unlock_irqrestore(&il->sta_lock, flags);
3515
3516 return 0;
3517}
3518
3519/**
3520 * il4965_update_bcast_station - update broadcast station's LQ command
3521 *
3522 * Only used by iwl4965. Placed here to have all bcast station management
3523 * code together.
3524 */
e7392364 3525static int
83007196 3526il4965_update_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3527{
3528 unsigned long flags;
3529 struct il_link_quality_cmd *link_cmd;
b16db50a 3530 u8 sta_id = il->hw_params.bcast_id;
eb3cdfb7
SG		 3531
3532 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3533 if (!link_cmd) {
1722f8e1 3534 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
eb3cdfb7
SG		 3535 return -ENOMEM;
3536 }
3537
3538 spin_lock_irqsave(&il->sta_lock, flags);
3539 if (il->stations[sta_id].lq)
3540 kfree(il->stations[sta_id].lq);
3541 else
1722f8e1 3542 D_INFO("Bcast sta rate scaling has not been initialized.\n");
eb3cdfb7
SG		 3543 il->stations[sta_id].lq = link_cmd;
3544 spin_unlock_irqrestore(&il->sta_lock, flags);
3545
3546 return 0;
3547}
3548
e7392364
SG		 3549int
3550il4965_update_bcast_stations(struct il_priv *il)
eb3cdfb7 3551{
83007196 3552 return il4965_update_bcast_station(il);
eb3cdfb7
SG		 3553}
3554
3555/**
3556 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3557 */
e7392364
SG		 3558int
3559il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
eb3cdfb7
SG		 3560{
3561 unsigned long flags;
3562 struct il_addsta_cmd sta_cmd;
3563
3564 lockdep_assert_held(&il->mutex);
3565
3566 /* Remove "disable" flag, to enable Tx for this TID */
3567 spin_lock_irqsave(&il->sta_lock, flags);
3568 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3569 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3570 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3571 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3572 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3573 spin_unlock_irqrestore(&il->sta_lock, flags);
3574
3575 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3576}
3577
e7392364
SG		 3578int
3579il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3580 u16 ssn)
eb3cdfb7
SG		 3581{
3582 unsigned long flags;
3583 int sta_id;
3584 struct il_addsta_cmd sta_cmd;
3585
3586 lockdep_assert_held(&il->mutex);
3587
3588 sta_id = il_sta_id(sta);
3589 if (sta_id == IL_INVALID_STATION)
3590 return -ENXIO;
3591
3592 spin_lock_irqsave(&il->sta_lock, flags);
3593 il->stations[sta_id].sta.station_flags_msk = 0;
3594 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
e7392364 3595 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3596 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3597 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3598 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3599 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3600 spin_unlock_irqrestore(&il->sta_lock, flags);
3601
3602 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3603}
3604
e7392364
SG		 3605int
3606il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
eb3cdfb7
SG		 3607{
3608 unsigned long flags;
3609 int sta_id;
3610 struct il_addsta_cmd sta_cmd;
3611
3612 lockdep_assert_held(&il->mutex);
3613
3614 sta_id = il_sta_id(sta);
3615 if (sta_id == IL_INVALID_STATION) {
3616 IL_ERR("Invalid station for AGG tid %d\n", tid);
3617 return -ENXIO;
3618 }
3619
3620 spin_lock_irqsave(&il->sta_lock, flags);
3621 il->stations[sta_id].sta.station_flags_msk = 0;
3622 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
e7392364 3623 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3624 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3625 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3626 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3627 spin_unlock_irqrestore(&il->sta_lock, flags);
3628
3629 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3630}
3631
3632void
3633il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3634{
3635 unsigned long flags;
3636
3637 spin_lock_irqsave(&il->sta_lock, flags);
3638 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3639 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3640 il->stations[sta_id].sta.sta.modify_mask =
e7392364 3641 STA_MODIFY_SLEEP_TX_COUNT_MSK;
eb3cdfb7
SG		 3642 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3643 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364 3644 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
eb3cdfb7
SG		 3645 spin_unlock_irqrestore(&il->sta_lock, flags);
3646
3647}
3648
e7392364
SG		 3649void
3650il4965_update_chain_flags(struct il_priv *il)
be663ab6 3651{
c9363551
SG		 3652 if (il->ops->set_rxon_chain) {
3653 il->ops->set_rxon_chain(il);
c8b03958 3654 if (il->active.rx_chain != il->staging.rx_chain)
83007196 3655 il_commit_rxon(il);
be663ab6
WYG		 3656 }
3657}
3658
e7392364
SG		 3659static void
3660il4965_clear_free_frames(struct il_priv *il)
be663ab6
WYG		 3661{
3662 struct list_head *element;
3663
e7392364 3664 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
be663ab6 3665
46bc8d4b
SG		 3666 while (!list_empty(&il->free_frames)) {
3667 element = il->free_frames.next;
be663ab6 3668 list_del(element);
e2ebc833 3669 kfree(list_entry(element, struct il_frame, list));
46bc8d4b 3670 il->frames_count--;
be663ab6
WYG		 3671 }
3672
46bc8d4b 3673 if (il->frames_count) {
9406f797 3674 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 3675 il->frames_count);
46bc8d4b 3676 il->frames_count = 0;
be663ab6
WYG		 3677 }
3678}
3679
e7392364
SG		 3680static struct il_frame *
3681il4965_get_free_frame(struct il_priv *il)
be663ab6 3682{
e2ebc833 3683 struct il_frame *frame;
be663ab6 3684 struct list_head *element;
46bc8d4b 3685 if (list_empty(&il->free_frames)) {
be663ab6
WYG		 3686 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3687 if (!frame) {
9406f797 3688 IL_ERR("Could not allocate frame!\n");
be663ab6
WYG		 3689 return NULL;
3690 }
3691
46bc8d4b 3692 il->frames_count++;
be663ab6
WYG		 3693 return frame;
3694 }
3695
46bc8d4b 3696 element = il->free_frames.next;
be663ab6 3697 list_del(element);
e2ebc833 3698 return list_entry(element, struct il_frame, list);
be663ab6
WYG		 3699}
3700
e7392364
SG		 3701static void
3702il4965_free_frame(struct il_priv *il, struct il_frame *frame)
be663ab6
WYG		 3703{
3704 memset(frame, 0, sizeof(*frame));
46bc8d4b 3705 list_add(&frame->list, &il->free_frames);
be663ab6
WYG		 3706}
3707
e7392364
SG		 3708static u32
3709il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3710 int left)
be663ab6 3711{
46bc8d4b 3712 lockdep_assert_held(&il->mutex);
be663ab6 3713
46bc8d4b 3714 if (!il->beacon_skb)
be663ab6
WYG		 3715 return 0;
3716
46bc8d4b 3717 if (il->beacon_skb->len > left)
be663ab6
WYG		 3718 return 0;
3719
46bc8d4b 3720 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
be663ab6 3721
46bc8d4b 3722 return il->beacon_skb->len;
be663ab6
WYG		 3723}
3724
3725/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
e7392364
SG		 3726static void
3727il4965_set_beacon_tim(struct il_priv *il,
3728 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3729 u32 frame_size)
be663ab6
WYG		 3730{
3731 u16 tim_idx;
3732 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3733
3734 /*
0c2c8852 3735 * The idx is relative to frame start but we start looking at the
be663ab6
WYG		 3736 * variable-length part of the beacon.
3737 */
3738 tim_idx = mgmt->u.beacon.variable - beacon;
3739
3740 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3741 while ((tim_idx < (frame_size - 2)) &&
e7392364
SG		 3742 (beacon[tim_idx] != WLAN_EID_TIM))
3743 tim_idx += beacon[tim_idx + 1] + 2;
be663ab6
WYG		 3744
3745 /* If TIM field was found, set variables */
3746 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3747 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
e7392364 3748 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
be663ab6 3749 } else
9406f797 3750 IL_WARN("Unable to find TIM Element in beacon\n");
be663ab6
WYG		 3751}
3752
e7392364
SG		 3753static unsigned int
3754il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
be663ab6 3755{
e2ebc833 3756 struct il_tx_beacon_cmd *tx_beacon_cmd;
be663ab6
WYG		 3757 u32 frame_size;
3758 u32 rate_flags;
3759 u32 rate;
3760 /*
3761 * We have to set up the TX command, the TX Beacon command, and the
3762 * beacon contents.
3763 */
3764
46bc8d4b 3765 lockdep_assert_held(&il->mutex);
be663ab6 3766
83007196
SG		 3767 if (!il->beacon_enabled) {
3768 IL_ERR("Trying to build beacon without beaconing enabled\n");
be663ab6
WYG		 3769 return 0;
3770 }
3771
3772 /* Initialize memory */
3773 tx_beacon_cmd = &frame->u.beacon;
3774 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3775
3776 /* Set up TX beacon contents */
e7392364
SG		 3777 frame_size =
3778 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3779 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
be663ab6
WYG		 3780 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3781 return 0;
3782 if (!frame_size)
3783 return 0;
3784
3785 /* Set up TX command fields */
e7392364 3786 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
b16db50a 3787 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
be663ab6 3788 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e7392364
SG		 3789 tx_beacon_cmd->tx.tx_flags =
3790 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3791 TX_CMD_FLG_STA_RATE_MSK;
be663ab6
WYG		 3792
3793 /* Set up TX beacon command fields */
e7392364
SG		 3794 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3795 frame_size);
be663ab6
WYG		 3796
3797 /* Set up packet rate and flags */
83007196 3798 rate = il_get_lowest_plcp(il);
a0c1ef3b 3799 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 3800 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
e2ebc833 3801 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
be663ab6 3802 rate_flags |= RATE_MCS_CCK_MSK;
616107ed 3803 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
be663ab6
WYG		 3804
3805 return sizeof(*tx_beacon_cmd) + frame_size;
3806}
3807
e7392364
SG		 3808int
3809il4965_send_beacon_cmd(struct il_priv *il)
be663ab6 3810{
e2ebc833 3811 struct il_frame *frame;
be663ab6
WYG		 3812 unsigned int frame_size;
3813 int rc;
3814
46bc8d4b 3815 frame = il4965_get_free_frame(il);
be663ab6 3816 if (!frame) {
9406f797 3817 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 3818 "command.\n");
be663ab6
WYG		 3819 return -ENOMEM;
3820 }
3821
46bc8d4b 3822 frame_size = il4965_hw_get_beacon_cmd(il, frame);
be663ab6 3823 if (!frame_size) {
9406f797 3824 IL_ERR("Error configuring the beacon command\n");
46bc8d4b 3825 il4965_free_frame(il, frame);
be663ab6
WYG		 3826 return -EINVAL;
3827 }
3828
e7392364 3829 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
be663ab6 3830
46bc8d4b 3831 il4965_free_frame(il, frame);
be663ab6
WYG		 3832
3833 return rc;
3834}
3835
e7392364
SG		 3836static inline dma_addr_t
3837il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
be663ab6 3838{
e2ebc833 3839 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3840
3841 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3842 if (sizeof(dma_addr_t) > sizeof(u32))
3843 addr |=
e7392364
SG		 3844 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3845 16;
be663ab6
WYG		 3846
3847 return addr;
3848}
3849
e7392364
SG		 3850static inline u16
3851il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
be663ab6 3852{
e2ebc833 3853 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3854
3855 return le16_to_cpu(tb->hi_n_len) >> 4;
3856}
3857
e7392364
SG		 3858static inline void
3859il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
be663ab6 3860{
e2ebc833 3861 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3862 u16 hi_n_len = len << 4;
3863
3864 put_unaligned_le32(addr, &tb->lo);
3865 if (sizeof(dma_addr_t) > sizeof(u32))
3866 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3867
3868 tb->hi_n_len = cpu_to_le16(hi_n_len);
3869
3870 tfd->num_tbs = idx + 1;
3871}
3872
e7392364
SG		 3873static inline u8
3874il4965_tfd_get_num_tbs(struct il_tfd *tfd)
be663ab6
WYG		 3875{
3876 return tfd->num_tbs & 0x1f;
3877}
3878
3879/**
e2ebc833 3880 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
46bc8d4b 3881 * @il - driver ilate data
be663ab6
WYG		 3882 * @txq - tx queue
3883 *
0c2c8852 3884 * Does NOT advance any TFD circular buffer read/write idxes
be663ab6
WYG		 3885 * Does NOT free the TFD itself (which is within circular buffer)
3886 */
e7392364
SG		 3887void
3888il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
be663ab6 3889{
e2ebc833
SG		 3890 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3891 struct il_tfd *tfd;
46bc8d4b 3892 struct pci_dev *dev = il->pci_dev;
0c2c8852 3893 int idx = txq->q.read_ptr;
be663ab6
WYG		 3894 int i;
3895 int num_tbs;
3896
0c2c8852 3897 tfd = &tfd_tmp[idx];
be663ab6
WYG		 3898
3899 /* Sanity check on number of chunks */
e2ebc833 3900 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6 3901
e2ebc833 3902 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3903 IL_ERR("Too many chunks: %i\n", num_tbs);
be663ab6
WYG		 3904 /* @todo issue fatal error, it is quite serious situation */
3905 return;
3906 }
3907
3908 /* Unmap tx_cmd */
3909 if (num_tbs)
e7392364
SG		 3910 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3911 dma_unmap_len(&txq->meta[idx], len),
3912 PCI_DMA_BIDIRECTIONAL);
be663ab6
WYG		 3913
3914 /* Unmap chunks, if any. */
3915 for (i = 1; i < num_tbs; i++)
e2ebc833 3916 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
e7392364
SG		 3917 il4965_tfd_tb_get_len(tfd, i),
3918 PCI_DMA_TODEVICE);
be663ab6
WYG		 3919
3920 /* free SKB */
00ea99e1
SG		 3921 if (txq->skbs) {
3922 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
be663ab6
WYG		 3923
3924 /* can be called from irqs-disabled context */
3925 if (skb) {
3926 dev_kfree_skb_any(skb);
00ea99e1 3927 txq->skbs[txq->q.read_ptr] = NULL;
be663ab6
WYG		 3928 }
3929 }
3930}
3931
e7392364
SG		 3932int
3933il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3934 dma_addr_t addr, u16 len, u8 reset, u8 pad)
be663ab6 3935{
e2ebc833
SG		 3936 struct il_queue *q;
3937 struct il_tfd *tfd, *tfd_tmp;
be663ab6
WYG		 3938 u32 num_tbs;
3939
3940 q = &txq->q;
e2ebc833 3941 tfd_tmp = (struct il_tfd *)txq->tfds;
be663ab6
WYG		 3942 tfd = &tfd_tmp[q->write_ptr];
3943
3944 if (reset)
3945 memset(tfd, 0, sizeof(*tfd));
3946
e2ebc833 3947 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6
WYG		 3948
3949 /* Each TFD can point to a maximum 20 Tx buffers */
e2ebc833 3950 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3951 IL_ERR("Error can not send more than %d chunks\n",
e7392364 3952 IL_NUM_OF_TBS);
be663ab6
WYG		 3953 return -EINVAL;
3954 }
3955
3956 BUG_ON(addr & ~DMA_BIT_MASK(36));
e2ebc833 3957 if (unlikely(addr & ~IL_TX_DMA_MASK))
e7392364 3958 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
be663ab6 3959
e2ebc833 3960 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
be663ab6
WYG		 3961
3962 return 0;
3963}
3964
3965/*
3966 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3967 * given Tx queue, and enable the DMA channel used for that queue.
3968 *
3969 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3970 * channels supported in hardware.
3971 */
e7392364
SG		 3972int
3973il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
be663ab6
WYG		 3974{
3975 int txq_id = txq->q.id;
3976
3977 /* Circular buffer (TFD queue in DRAM) physical base address */
e7392364 3978 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
be663ab6
WYG		 3979
3980 return 0;
3981}
3982
3983/******************************************************************************
3984 *
3985 * Generic RX handler implementations
3986 *
3987 ******************************************************************************/
e7392364
SG		 3988static void
3989il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 3990{
dcae1c64 3991 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 3992 struct il_alive_resp *palive;
be663ab6
WYG		 3993 struct delayed_work *pwork;
3994
3995 palive = &pkt->u.alive_frame;
3996
e7392364
SG		 3997 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
3998 palive->is_valid, palive->ver_type, palive->ver_subtype);
be663ab6
WYG		 3999
4000 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 4001 D_INFO("Initialization Alive received.\n");
e7392364 4002 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 4003 sizeof(struct il_init_alive_resp));
46bc8d4b 4004 pwork = &il->init_alive_start;
be663ab6 4005 } else {
58de00a4 4006 D_INFO("Runtime Alive received.\n");
46bc8d4b 4007 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 4008 sizeof(struct il_alive_resp));
46bc8d4b 4009 pwork = &il->alive_start;
be663ab6
WYG		 4010 }
4011
4012 /* We delay the ALIVE response by 5ms to
4013 * give the HW RF Kill time to activate... */
4014 if (palive->is_valid == UCODE_VALID_OK)
e7392364 4015 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
be663ab6 4016 else
9406f797 4017 IL_WARN("uCode did not respond OK.\n");
be663ab6
WYG		 4018}
4019
4020/**
ebf0d90d 4021 * il4965_bg_stats_periodic - Timer callback to queue stats
be663ab6 4022 *
ebf0d90d 4023 * This callback is provided in order to send a stats request.
be663ab6
WYG		 4024 *
4025 * This timer function is continually reset to execute within
527901d0
SG		 4026 * 60 seconds since the last N_STATS was received. We need to
4027 * ensure we receive the stats in order to update the temperature
4028 * used for calibrating the TXPOWER.
be663ab6 4029 */
e7392364
SG		 4030static void
4031il4965_bg_stats_periodic(unsigned long data)
be663ab6 4032{
46bc8d4b 4033 struct il_priv *il = (struct il_priv *)data;
be663ab6 4034
a6766ccd 4035 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4036 return;
4037
4038 /* dont send host command if rf-kill is on */
46bc8d4b 4039 if (!il_is_ready_rf(il))
be663ab6
WYG		 4040 return;
4041
ebf0d90d 4042 il_send_stats_request(il, CMD_ASYNC, false);
be663ab6
WYG		 4043}
4044
e7392364
SG		 4045static void
4046il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4047{
dcae1c64 4048 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4049 struct il4965_beacon_notif *beacon =
e7392364 4050 (struct il4965_beacon_notif *)pkt->u.raw;
d3175167 4051#ifdef CONFIG_IWLEGACY_DEBUG
e2ebc833 4052 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
be663ab6 4053
5bf0dac4 4054 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
e7392364
SG		 4055 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4056 beacon->beacon_notify_hdr.failure_frame,
4057 le32_to_cpu(beacon->ibss_mgr_status),
4058 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
be663ab6 4059#endif
46bc8d4b 4060 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
be663ab6
WYG		 4061}
4062
e7392364
SG		 4063static void
4064il4965_perform_ct_kill_task(struct il_priv *il)
be663ab6
WYG		 4065{
4066 unsigned long flags;
4067
58de00a4 4068 D_POWER("Stop all queues\n");
be663ab6 4069
46bc8d4b
SG		 4070 if (il->mac80211_registered)
4071 ieee80211_stop_queues(il->hw);
be663ab6 4072
841b2cca 4073 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4074 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
841b2cca 4075 _il_rd(il, CSR_UCODE_DRV_GP1);
be663ab6 4076
46bc8d4b 4077 spin_lock_irqsave(&il->reg_lock, flags);
1e0f32a4 4078 if (likely(_il_grab_nic_access(il)))
13882269 4079 _il_release_nic_access(il);
46bc8d4b 4080 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6
WYG		 4081}
4082
4083/* Handle notification from uCode that card's power state is changing
4084 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG		 4085static void
4086il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4087{
dcae1c64 4088 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4089 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 4090 unsigned long status = il->status;
be663ab6 4091
58de00a4 4092 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
e7392364
SG		 4093 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4094 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4095 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
be663ab6 4096
e7392364 4097 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
be663ab6 4098
841b2cca 4099 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4100 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6 4101
e7392364 4102 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4103
4104 if (!(flags & RXON_CARD_DISABLED)) {
841b2cca 4105 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 4106 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0c1a94e2 4107 il_wr(il, HBUS_TARG_MBX_C,
e7392364 4108 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4109 }
4110 }
4111
4112 if (flags & CT_CARD_DISABLED)
46bc8d4b 4113 il4965_perform_ct_kill_task(il);
be663ab6
WYG		 4114
4115 if (flags & HW_CARD_DISABLED)
bc269a8e 4116 set_bit(S_RFKILL, &il->status);
be663ab6 4117 else
bc269a8e 4118 clear_bit(S_RFKILL, &il->status);
be663ab6
WYG		 4119
4120 if (!(flags & RXON_CARD_DISABLED))
46bc8d4b 4121 il_scan_cancel(il);
be663ab6 4122
bc269a8e
SG		 4123 if ((test_bit(S_RFKILL, &status) !=
4124 test_bit(S_RFKILL, &il->status)))
46bc8d4b 4125 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 4126 test_bit(S_RFKILL, &il->status));
be663ab6 4127 else
46bc8d4b 4128 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4129}
4130
4131/**
d0c72347 4132 * il4965_setup_handlers - Initialize Rx handler callbacks
be663ab6
WYG		 4133 *
4134 * Setup the RX handlers for each of the reply types sent from the uCode
4135 * to the host.
4136 *
4137 * This function chains into the hardware specific files for them to setup
4138 * any hardware specific handlers as well.
4139 */
e7392364
SG		 4140static void
4141il4965_setup_handlers(struct il_priv *il)
be663ab6 4142{
6e9848b4
SG		 4143 il->handlers[N_ALIVE] = il4965_hdl_alive;
4144 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 4145 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 4146 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 4147 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 4148 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 4149 il->handlers[N_BEACON] = il4965_hdl_beacon;
be663ab6
WYG		 4150
4151 /*
4152 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG		 4153 * stats request from the host as well as for the periodic
4154 * stats notifications (after received beacons) from the uCode.
be663ab6 4155 */
d2dfb33e
SG		 4156 il->handlers[C_STATS] = il4965_hdl_c_stats;
4157 il->handlers[N_STATS] = il4965_hdl_stats;
be663ab6 4158
46bc8d4b 4159 il_setup_rx_scan_handlers(il);
be663ab6
WYG		 4160
4161 /* status change handler */
e7392364 4162 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
be663ab6 4163
e7392364 4164 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
be663ab6 4165 /* Rx handlers */
6e9848b4
SG		 4166 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4167 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
3dfea27d 4168 il->handlers[N_RX] = il4965_hdl_rx;
be663ab6 4169 /* block ack */
6e9848b4 4170 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
3dfea27d
SG		 4171 /* Tx response */
4172 il->handlers[C_TX] = il4965_hdl_tx;
be663ab6
WYG		 4173}
4174
4175/**
e2ebc833 4176 * il4965_rx_handle - Main entry function for receiving responses from uCode
be663ab6 4177 *
d0c72347 4178 * Uses the il->handlers callback function array to invoke
be663ab6
WYG		 4179 * the appropriate handlers, including command responses,
4180 * frame-received notifications, and other notifications.
4181 */
e7392364
SG		 4182void
4183il4965_rx_handle(struct il_priv *il)
be663ab6 4184{
b73bb5f1 4185 struct il_rx_buf *rxb;
dcae1c64 4186 struct il_rx_pkt *pkt;
46bc8d4b 4187 struct il_rx_queue *rxq = &il->rxq;
be663ab6
WYG		 4188 u32 r, i;
4189 int reclaim;
4190 unsigned long flags;
4191 u8 fill_rx = 0;
4192 u32 count = 8;
4193 int total_empty;
4194
0c2c8852 4195 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
be663ab6 4196 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 4197 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
be663ab6
WYG		 4198 i = rxq->read;
4199
4200 /* Rx interrupt, but nothing sent from uCode */
4201 if (i == r)
58de00a4 4202 D_RX("r = %d, i = %d\n", r, i);
be663ab6
WYG		 4203
4204 /* calculate total frames need to be restock after handling RX */
4205 total_empty = r - rxq->write_actual;
4206 if (total_empty < 0)
4207 total_empty += RX_QUEUE_SIZE;
4208
4209 if (total_empty > (RX_QUEUE_SIZE / 2))
4210 fill_rx = 1;
4211
4212 while (i != r) {
4213 int len;
4214
4215 rxb = rxq->queue[i];
4216
4217 /* If an RXB doesn't have a Rx queue slot associated with it,
4218 * then a bug has been introduced in the queue refilling
4219 * routines -- catch it here */
4220 BUG_ON(rxb == NULL);
4221
4222 rxq->queue[i] = NULL;
4223
46bc8d4b
SG		 4224 pci_unmap_page(il->pci_dev, rxb->page_dma,
4225 PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 4226 PCI_DMA_FROMDEVICE);
4227 pkt = rxb_addr(rxb);
4228
e94a4099 4229 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 4230 len += sizeof(u32); /* account for status word */
be663ab6
WYG		 4231
4232 /* Reclaim a command buffer only if this packet is a response
4233 * to a (driver-originated) command.
4234 * If the packet (e.g. Rx frame) originated from uCode,
4235 * there is no command buffer to reclaim.
4236 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4237 * but apparently a few don't get set; catch them here. */
4238 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364
SG		 4239 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
4240 (pkt->hdr.cmd != N_RX_MPDU) &&
4241 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
4242 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
be663ab6
WYG		 4243
4244 /* Based on type of command response or notification,
4245 * handle those that need handling via function in
d0c72347
SG		 4246 * handlers table. See il4965_setup_handlers() */
4247 if (il->handlers[pkt->hdr.cmd]) {
e7392364
SG		 4248 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4249 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG		 4250 il->isr_stats.handlers[pkt->hdr.cmd]++;
4251 il->handlers[pkt->hdr.cmd] (il, rxb);
be663ab6
WYG		 4252 } else {
4253 /* No handling needed */
e7392364
SG		 4254 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4255 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
be663ab6
WYG		 4256 }
4257
4258 /*
4259 * XXX: After here, we should always check rxb->page
4260 * against NULL before touching it or its virtual
d0c72347 4261 * memory (pkt). Because some handler might have
be663ab6
WYG		 4262 * already taken or freed the pages.
4263 */
4264
4265 if (reclaim) {
4266 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 4267 * and fire off the (possibly) blocking il_send_cmd()
be663ab6
WYG		 4268 * as we reclaim the driver command queue */
4269 if (rxb->page)
46bc8d4b 4270 il_tx_cmd_complete(il, rxb);
be663ab6 4271 else
9406f797 4272 IL_WARN("Claim null rxb?\n");
be663ab6
WYG		 4273 }
4274
4275 /* Reuse the page if possible. For notification packets and
4276 * SKBs that fail to Rx correctly, add them back into the
4277 * rx_free list for reuse later. */
4278 spin_lock_irqsave(&rxq->lock, flags);
4279 if (rxb->page != NULL) {
e7392364
SG		 4280 rxb->page_dma =
4281 pci_map_page(il->pci_dev, rxb->page, 0,
4282 PAGE_SIZE << il->hw_params.
4283 rx_page_order, PCI_DMA_FROMDEVICE);
be663ab6
WYG		 4284 list_add_tail(&rxb->list, &rxq->rx_free);
4285 rxq->free_count++;
4286 } else
4287 list_add_tail(&rxb->list, &rxq->rx_used);
4288
4289 spin_unlock_irqrestore(&rxq->lock, flags);
4290
4291 i = (i + 1) & RX_QUEUE_MASK;
4292 /* If there are a lot of unused frames,
4293 * restock the Rx queue so ucode wont assert. */
4294 if (fill_rx) {
4295 count++;
4296 if (count >= 8) {
4297 rxq->read = i;
46bc8d4b 4298 il4965_rx_replenish_now(il);
be663ab6
WYG		 4299 count = 0;
4300 }
4301 }
4302 }
4303
4304 /* Backtrack one entry */
4305 rxq->read = i;
4306 if (fill_rx)
46bc8d4b 4307 il4965_rx_replenish_now(il);
be663ab6 4308 else
46bc8d4b 4309 il4965_rx_queue_restock(il);
be663ab6
WYG		 4310}
4311
4312/* call this function to flush any scheduled tasklet */
e7392364
SG		 4313static inline void
4314il4965_synchronize_irq(struct il_priv *il)
be663ab6 4315{
e7392364 4316 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG		 4317 synchronize_irq(il->pci_dev->irq);
4318 tasklet_kill(&il->irq_tasklet);
be663ab6
WYG		 4319}
4320
e7392364
SG		 4321static void
4322il4965_irq_tasklet(struct il_priv *il)
be663ab6
WYG		 4323{
4324 u32 inta, handled = 0;
4325 u32 inta_fh;
4326 unsigned long flags;
4327 u32 i;
d3175167 4328#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4329 u32 inta_mask;
4330#endif
4331
46bc8d4b 4332 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4333
4334 /* Ack/clear/reset pending uCode interrupts.
4335 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4336 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG		 4337 inta = _il_rd(il, CSR_INT);
4338 _il_wr(il, CSR_INT, inta);
be663ab6
WYG		 4339
4340 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4341 * Any new interrupts that happen after this, either while we're
4342 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG		 4343 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4344 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
be663ab6 4345
d3175167 4346#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4347 if (il_get_debug_level(il) & IL_DL_ISR) {
be663ab6 4348 /* just for debug */
841b2cca 4349 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG		 4350 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4351 inta_mask, inta_fh);
be663ab6
WYG		 4352 }
4353#endif
4354
46bc8d4b 4355 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4356
4357 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4358 * atomic, make sure that inta covers all the interrupts that
4359 * we've discovered, even if FH interrupt came in just after
4360 * reading CSR_INT. */
4361 if (inta_fh & CSR49_FH_INT_RX_MASK)
4362 inta |= CSR_INT_BIT_FH_RX;
4363 if (inta_fh & CSR49_FH_INT_TX_MASK)
4364 inta |= CSR_INT_BIT_FH_TX;
4365
4366 /* Now service all interrupt bits discovered above. */
4367 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 4368 IL_ERR("Hardware error detected. Restarting.\n");
be663ab6
WYG		 4369
4370 /* Tell the device to stop sending interrupts */
46bc8d4b 4371 il_disable_interrupts(il);
be663ab6 4372
46bc8d4b
SG		 4373 il->isr_stats.hw++;
4374 il_irq_handle_error(il);
be663ab6
WYG		 4375
4376 handled |= CSR_INT_BIT_HW_ERR;
4377
4378 return;
4379 }
d3175167 4380#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4381 if (il_get_debug_level(il) & (IL_DL_ISR)) {
be663ab6
WYG		 4382 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4383 if (inta & CSR_INT_BIT_SCD) {
58de00a4 4384 D_ISR("Scheduler finished to transmit "
e7392364 4385 "the frame/frames.\n");
46bc8d4b 4386 il->isr_stats.sch++;
be663ab6
WYG		 4387 }
4388
4389 /* Alive notification via Rx interrupt will do the real work */
4390 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 4391 D_ISR("Alive interrupt\n");
46bc8d4b 4392 il->isr_stats.alive++;
be663ab6
WYG		 4393 }
4394 }
4395#endif
4396 /* Safely ignore these bits for debug checks below */
4397 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4398
4399 /* HW RF KILL switch toggled */
4400 if (inta & CSR_INT_BIT_RF_KILL) {
4401 int hw_rf_kill = 0;
c9363551
SG		 4402
4403 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4404 hw_rf_kill = 1;
4405
9406f797 4406 IL_WARN("RF_KILL bit toggled to %s.\n",
e7392364 4407 hw_rf_kill ? "disable radio" : "enable radio");
be663ab6 4408
46bc8d4b 4409 il->isr_stats.rfkill++;
be663ab6
WYG		 4410
4411 /* driver only loads ucode once setting the interface up.
4412 * the driver allows loading the ucode even if the radio
4413 * is killed. Hence update the killswitch state here. The
4414 * rfkill handler will care about restarting if needed.
4415 */
a6766ccd 4416 if (!test_bit(S_ALIVE, &il->status)) {
be663ab6 4417 if (hw_rf_kill)
bc269a8e 4418 set_bit(S_RFKILL, &il->status);
be663ab6 4419 else
bc269a8e 4420 clear_bit(S_RFKILL, &il->status);
46bc8d4b 4421 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
be663ab6
WYG		 4422 }
4423
4424 handled |= CSR_INT_BIT_RF_KILL;
4425 }
4426
4427 /* Chip got too hot and stopped itself */
4428 if (inta & CSR_INT_BIT_CT_KILL) {
9406f797 4429 IL_ERR("Microcode CT kill error detected.\n");
46bc8d4b 4430 il->isr_stats.ctkill++;
be663ab6
WYG		 4431 handled |= CSR_INT_BIT_CT_KILL;
4432 }
4433
4434 /* Error detected by uCode */
4435 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG		 4436 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4437 inta);
46bc8d4b
SG		 4438 il->isr_stats.sw++;
4439 il_irq_handle_error(il);
be663ab6
WYG		 4440 handled |= CSR_INT_BIT_SW_ERR;
4441 }
4442
4443 /*
4444 * uCode wakes up after power-down sleep.
4445 * Tell device about any new tx or host commands enqueued,
4446 * and about any Rx buffers made available while asleep.
4447 */
4448 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 4449 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG		 4450 il_rx_queue_update_write_ptr(il, &il->rxq);
4451 for (i = 0; i < il->hw_params.max_txq_num; i++)
4452 il_txq_update_write_ptr(il, &il->txq[i]);
4453 il->isr_stats.wakeup++;
be663ab6
WYG		 4454 handled |= CSR_INT_BIT_WAKEUP;
4455 }
4456
4457 /* All uCode command responses, including Tx command responses,
4458 * Rx "responses" (frame-received notification), and other
4459 * notifications from uCode come through here*/
4460 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG		 4461 il4965_rx_handle(il);
4462 il->isr_stats.rx++;
be663ab6
WYG		 4463 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4464 }
4465
4466 /* This "Tx" DMA channel is used only for loading uCode */
4467 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 4468 D_ISR("uCode load interrupt\n");
46bc8d4b 4469 il->isr_stats.tx++;
be663ab6
WYG		 4470 handled |= CSR_INT_BIT_FH_TX;
4471 /* Wake up uCode load routine, now that load is complete */
46bc8d4b
SG		 4472 il->ucode_write_complete = 1;
4473 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4474 }
4475
4476 if (inta & ~handled) {
9406f797 4477 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 4478 il->isr_stats.unhandled++;
be663ab6
WYG		 4479 }
4480
46bc8d4b 4481 if (inta & ~(il->inta_mask)) {
9406f797 4482 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 4483 inta & ~il->inta_mask);
9a95b370 4484 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
be663ab6
WYG		 4485 }
4486
4487 /* Re-enable all interrupts */
93fd74e3 4488 /* only Re-enable if disabled by irq */
a6766ccd 4489 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 4490 il_enable_interrupts(il);
a078a1fd
SG		 4491 /* Re-enable RF_KILL if it occurred */
4492 else if (handled & CSR_INT_BIT_RF_KILL)
46bc8d4b 4493 il_enable_rfkill_int(il);
be663ab6 4494
d3175167 4495#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4496 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG		 4497 inta = _il_rd(il, CSR_INT);
4498 inta_mask = _il_rd(il, CSR_INT_MASK);
4499 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
e7392364
SG		 4500 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4501 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
be663ab6
WYG		 4502 }
4503#endif
4504}
4505
4506/*****************************************************************************
4507 *
4508 * sysfs attributes
4509 *
4510 *****************************************************************************/
4511
d3175167 4512#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4513
4514/*
4515 * The following adds a new attribute to the sysfs representation
4516 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4517 * used for controlling the debug level.
4518 *
4519 * See the level definitions in iwl for details.
4520 *
4521 * The debug_level being managed using sysfs below is a per device debug
4522 * level that is used instead of the global debug level if it (the per
4523 * device debug level) is set.
4524 */
e7392364
SG		 4525static ssize_t
4526il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4527 char *buf)
be663ab6 4528{
46bc8d4b
SG		 4529 struct il_priv *il = dev_get_drvdata(d);
4530 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
be663ab6 4531}
e7392364
SG		 4532
4533static ssize_t
4534il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4535 const char *buf, size_t count)
be663ab6 4536{
46bc8d4b 4537 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4538 unsigned long val;
4539 int ret;
4540
4541 ret = strict_strtoul(buf, 0, &val);
4542 if (ret)
9406f797 4543 IL_ERR("%s is not in hex or decimal form.\n", buf);
288f9954 4544 else
46bc8d4b 4545 il->debug_level = val;
288f9954 4546
be663ab6
WYG		 4547 return strnlen(buf, count);
4548}
4549
e7392364
SG		 4550static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4551 il4965_store_debug_level);
be663ab6 4552
d3175167 4553#endif /* CONFIG_IWLEGACY_DEBUG */
be663ab6 4554
e7392364
SG		 4555static ssize_t
4556il4965_show_temperature(struct device *d, struct device_attribute *attr,
4557 char *buf)
be663ab6 4558{
46bc8d4b 4559 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4560
46bc8d4b 4561 if (!il_is_alive(il))
be663ab6
WYG		 4562 return -EAGAIN;
4563
46bc8d4b 4564 return sprintf(buf, "%d\n", il->temperature);
be663ab6
WYG		 4565}
4566
e2ebc833 4567static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
be663ab6 4568
e7392364
SG		 4569static ssize_t
4570il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
be663ab6 4571{
46bc8d4b 4572 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4573
46bc8d4b 4574 if (!il_is_ready_rf(il))
be663ab6
WYG		 4575 return sprintf(buf, "off\n");
4576 else
46bc8d4b 4577 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
be663ab6
WYG		 4578}
4579
e7392364
SG		 4580static ssize_t
4581il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4582 const char *buf, size_t count)
be663ab6 4583{
46bc8d4b 4584 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4585 unsigned long val;
4586 int ret;
4587
4588 ret = strict_strtoul(buf, 10, &val);
4589 if (ret)
9406f797 4590 IL_INFO("%s is not in decimal form.\n", buf);
be663ab6 4591 else {
46bc8d4b 4592 ret = il_set_tx_power(il, val, false);
be663ab6 4593 if (ret)
e7392364 4594 IL_ERR("failed setting tx power (0x%d).\n", ret);
be663ab6
WYG		 4595 else
4596 ret = count;
4597 }
4598 return ret;
4599}
4600
e7392364
SG		 4601static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4602 il4965_store_tx_power);
be663ab6 4603
e2ebc833 4604static struct attribute *il_sysfs_entries[] = {
be663ab6
WYG		 4605 &dev_attr_temperature.attr,
4606 &dev_attr_tx_power.attr,
d3175167 4607#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4608 &dev_attr_debug_level.attr,
4609#endif
4610 NULL
4611};
4612
e2ebc833 4613static struct attribute_group il_attribute_group = {
be663ab6 4614 .name = NULL, /* put in device directory */
e2ebc833 4615 .attrs = il_sysfs_entries,
be663ab6
WYG		 4616};
4617
4618/******************************************************************************
4619 *
4620 * uCode download functions
4621 *
4622 ******************************************************************************/
4623
e7392364
SG		 4624static void
4625il4965_dealloc_ucode_pci(struct il_priv *il)
be663ab6 4626{
46bc8d4b
SG		 4627 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4628 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4629 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4630 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4631 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4632 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6
WYG		 4633}
4634
e7392364
SG		 4635static void
4636il4965_nic_start(struct il_priv *il)
be663ab6
WYG		 4637{
4638 /* Remove all resets to allow NIC to operate */
841b2cca 4639 _il_wr(il, CSR_RESET, 0);
be663ab6
WYG		 4640}
4641
e2ebc833 4642static void il4965_ucode_callback(const struct firmware *ucode_raw,
e7392364
SG		 4643 void *context);
4644static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
be663ab6 4645
e7392364
SG		 4646static int __must_check
4647il4965_request_firmware(struct il_priv *il, bool first)
be663ab6 4648{
46bc8d4b 4649 const char *name_pre = il->cfg->fw_name_pre;
be663ab6
WYG		 4650 char tag[8];
4651
4652 if (first) {
0c2c8852
SG		 4653 il->fw_idx = il->cfg->ucode_api_max;
4654 sprintf(tag, "%d", il->fw_idx);
be663ab6 4655 } else {
0c2c8852
SG		 4656 il->fw_idx--;
4657 sprintf(tag, "%d", il->fw_idx);
be663ab6
WYG		 4658 }
4659
0c2c8852 4660 if (il->fw_idx < il->cfg->ucode_api_min) {
9406f797 4661 IL_ERR("no suitable firmware found!\n");
be663ab6
WYG		 4662 return -ENOENT;
4663 }
4664
46bc8d4b 4665 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
be663ab6 4666
e7392364 4667 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
be663ab6 4668
46bc8d4b
SG		 4669 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4670 &il->pci_dev->dev, GFP_KERNEL, il,
e2ebc833 4671 il4965_ucode_callback);
be663ab6
WYG		 4672}
4673
e2ebc833 4674struct il4965_firmware_pieces {
be663ab6
WYG		 4675 const void *inst, *data, *init, *init_data, *boot;
4676 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4677};
4678
e7392364
SG		 4679static int
4680il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4681 struct il4965_firmware_pieces *pieces)
be663ab6 4682{
e2ebc833 4683 struct il_ucode_header *ucode = (void *)ucode_raw->data;
be663ab6
WYG		 4684 u32 api_ver, hdr_size;
4685 const u8 *src;
4686
46bc8d4b
SG		 4687 il->ucode_ver = le32_to_cpu(ucode->ver);
4688 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4689
4690 switch (api_ver) {
4691 default:
4692 case 0:
4693 case 1:
4694 case 2:
4695 hdr_size = 24;
4696 if (ucode_raw->size < hdr_size) {
9406f797 4697 IL_ERR("File size too small!\n");
be663ab6
WYG		 4698 return -EINVAL;
4699 }
4700 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4701 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4702 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
e7392364 4703 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
be663ab6
WYG		 4704 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4705 src = ucode->v1.data;
4706 break;
4707 }
4708
4709 /* Verify size of file vs. image size info in file's header */
e7392364
SG		 4710 if (ucode_raw->size !=
4711 hdr_size + pieces->inst_size + pieces->data_size +
4712 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
be663ab6 4713
e7392364
SG		 4714 IL_ERR("uCode file size %d does not match expected size\n",
4715 (int)ucode_raw->size);
be663ab6
WYG		 4716 return -EINVAL;
4717 }
4718
4719 pieces->inst = src;
4720 src += pieces->inst_size;
4721 pieces->data = src;
4722 src += pieces->data_size;
4723 pieces->init = src;
4724 src += pieces->init_size;
4725 pieces->init_data = src;
4726 src += pieces->init_data_size;
4727 pieces->boot = src;
4728 src += pieces->boot_size;
4729
4730 return 0;
4731}
4732
4733/**
e2ebc833 4734 * il4965_ucode_callback - callback when firmware was loaded
be663ab6
WYG		 4735 *
4736 * If loaded successfully, copies the firmware into buffers
4737 * for the card to fetch (via DMA).
4738 */
4739static void
e2ebc833 4740il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
be663ab6 4741{
46bc8d4b 4742 struct il_priv *il = context;
e2ebc833 4743 struct il_ucode_header *ucode;
be663ab6 4744 int err;
e2ebc833 4745 struct il4965_firmware_pieces pieces;
46bc8d4b
SG		 4746 const unsigned int api_max = il->cfg->ucode_api_max;
4747 const unsigned int api_min = il->cfg->ucode_api_min;
be663ab6
WYG		 4748 u32 api_ver;
4749
4750 u32 max_probe_length = 200;
4751 u32 standard_phy_calibration_size =
e7392364 4752 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
be663ab6
WYG		 4753
4754 memset(&pieces, 0, sizeof(pieces));
4755
4756 if (!ucode_raw) {
0c2c8852 4757 if (il->fw_idx <= il->cfg->ucode_api_max)
e7392364
SG		 4758 IL_ERR("request for firmware file '%s' failed.\n",
4759 il->firmware_name);
be663ab6
WYG		 4760 goto try_again;
4761 }
4762
e7392364
SG		 4763 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4764 ucode_raw->size);
be663ab6
WYG		 4765
4766 /* Make sure that we got at least the API version number */
4767 if (ucode_raw->size < 4) {
9406f797 4768 IL_ERR("File size way too small!\n");
be663ab6
WYG		 4769 goto try_again;
4770 }
4771
4772 /* Data from ucode file: header followed by uCode images */
e2ebc833 4773 ucode = (struct il_ucode_header *)ucode_raw->data;
be663ab6 4774
46bc8d4b 4775 err = il4965_load_firmware(il, ucode_raw, &pieces);
be663ab6
WYG		 4776
4777 if (err)
4778 goto try_again;
4779
46bc8d4b 4780 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4781
4782 /*
4783 * api_ver should match the api version forming part of the
4784 * firmware filename ... but we don't check for that and only rely
4785 * on the API version read from firmware header from here on forward
4786 */
4787 if (api_ver < api_min || api_ver > api_max) {
e7392364
SG		 4788 IL_ERR("Driver unable to support your firmware API. "
4789 "Driver supports v%u, firmware is v%u.\n", api_max,
4790 api_ver);
be663ab6
WYG		 4791 goto try_again;
4792 }
4793
4794 if (api_ver != api_max)
e7392364
SG		 4795 IL_ERR("Firmware has old API version. Expected v%u, "
4796 "got v%u. New firmware can be obtained "
4797 "from http://www.intellinuxwireless.org.\n", api_max,
4798 api_ver);
be663ab6 4799
9406f797 4800 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG		 4801 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4802 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
be663ab6 4803
e7392364
SG		 4804 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4805 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4806 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
46bc8d4b 4807 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6
WYG		 4808
4809 /*
4810 * For any of the failures below (before allocating pci memory)
4811 * we will try to load a version with a smaller API -- maybe the
4812 * user just got a corrupted version of the latest API.
4813 */
4814
e7392364
SG		 4815 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4816 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4817 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4818 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4819 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4820 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
be663ab6
WYG		 4821
4822 /* Verify that uCode images will fit in card's SRAM */
46bc8d4b 4823 if (pieces.inst_size > il->hw_params.max_inst_size) {
9406f797 4824 IL_ERR("uCode instr len %Zd too large to fit in\n",
e7392364 4825 pieces.inst_size);
be663ab6
WYG		 4826 goto try_again;
4827 }
4828
46bc8d4b 4829 if (pieces.data_size > il->hw_params.max_data_size) {
9406f797 4830 IL_ERR("uCode data len %Zd too large to fit in\n",
e7392364 4831 pieces.data_size);
be663ab6
WYG		 4832 goto try_again;
4833 }
4834
46bc8d4b 4835 if (pieces.init_size > il->hw_params.max_inst_size) {
9406f797 4836 IL_ERR("uCode init instr len %Zd too large to fit in\n",
e7392364 4837 pieces.init_size);
be663ab6
WYG		 4838 goto try_again;
4839 }
4840
46bc8d4b 4841 if (pieces.init_data_size > il->hw_params.max_data_size) {
9406f797 4842 IL_ERR("uCode init data len %Zd too large to fit in\n",
e7392364 4843 pieces.init_data_size);
be663ab6
WYG		 4844 goto try_again;
4845 }
4846
46bc8d4b 4847 if (pieces.boot_size > il->hw_params.max_bsm_size) {
9406f797 4848 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
e7392364 4849 pieces.boot_size);
be663ab6
WYG		 4850 goto try_again;
4851 }
4852
4853 /* Allocate ucode buffers for card's bus-master loading ... */
4854
4855 /* Runtime instructions and 2 copies of data:
4856 * 1) unmodified from disk
4857 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG		 4858 il->ucode_code.len = pieces.inst_size;
4859 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
be663ab6 4860
46bc8d4b
SG		 4861 il->ucode_data.len = pieces.data_size;
4862 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
be663ab6 4863
46bc8d4b
SG		 4864 il->ucode_data_backup.len = pieces.data_size;
4865 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
be663ab6 4866
46bc8d4b
SG		 4867 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4868 !il->ucode_data_backup.v_addr)
be663ab6
WYG		 4869 goto err_pci_alloc;
4870
4871 /* Initialization instructions and data */
4872 if (pieces.init_size && pieces.init_data_size) {
46bc8d4b
SG		 4873 il->ucode_init.len = pieces.init_size;
4874 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
be663ab6 4875
46bc8d4b
SG		 4876 il->ucode_init_data.len = pieces.init_data_size;
4877 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
be663ab6 4878
46bc8d4b 4879 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
be663ab6
WYG		 4880 goto err_pci_alloc;
4881 }
4882
4883 /* Bootstrap (instructions only, no data) */
4884 if (pieces.boot_size) {
46bc8d4b
SG		 4885 il->ucode_boot.len = pieces.boot_size;
4886 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6 4887
46bc8d4b 4888 if (!il->ucode_boot.v_addr)
be663ab6
WYG		 4889 goto err_pci_alloc;
4890 }
4891
4892 /* Now that we can no longer fail, copy information */
4893
46bc8d4b 4894 il->sta_key_max_num = STA_KEY_MAX_NUM;
be663ab6
WYG		 4895
4896 /* Copy images into buffers for card's bus-master reads ... */
4897
4898 /* Runtime instructions (first block of data in file) */
58de00a4 4899 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
e7392364 4900 pieces.inst_size);
46bc8d4b 4901 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
be663ab6 4902
58de00a4 4903 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 4904 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
be663ab6
WYG		 4905
4906 /*
4907 * Runtime data
e2ebc833 4908 * NOTE: Copy into backup buffer will be done in il_up()
be663ab6 4909 */
58de00a4 4910 D_INFO("Copying (but not loading) uCode data len %Zd\n",
e7392364 4911 pieces.data_size);
46bc8d4b
SG		 4912 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4913 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
be663ab6
WYG		 4914
4915 /* Initialization instructions */
4916 if (pieces.init_size) {
e7392364
SG		 4917 D_INFO("Copying (but not loading) init instr len %Zd\n",
4918 pieces.init_size);
46bc8d4b 4919 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
be663ab6
WYG		 4920 }
4921
4922 /* Initialization data */
4923 if (pieces.init_data_size) {
e7392364
SG		 4924 D_INFO("Copying (but not loading) init data len %Zd\n",
4925 pieces.init_data_size);
46bc8d4b 4926 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
be663ab6
WYG		 4927 pieces.init_data_size);
4928 }
4929
4930 /* Bootstrap instructions */
58de00a4 4931 D_INFO("Copying (but not loading) boot instr len %Zd\n",
e7392364 4932 pieces.boot_size);
46bc8d4b 4933 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
be663ab6
WYG		 4934
4935 /*
4936 * figure out the offset of chain noise reset and gain commands
4937 * base on the size of standard phy calibration commands table size
4938 */
46bc8d4b 4939 il->_4965.phy_calib_chain_noise_reset_cmd =
e7392364 4940 standard_phy_calibration_size;
46bc8d4b 4941 il->_4965.phy_calib_chain_noise_gain_cmd =
e7392364 4942 standard_phy_calibration_size + 1;
be663ab6
WYG		 4943
4944 /**************************************************
4945 * This is still part of probe() in a sense...
4946 *
4947 * 9. Setup and register with mac80211 and debugfs
4948 **************************************************/
46bc8d4b 4949 err = il4965_mac_setup_register(il, max_probe_length);
be663ab6
WYG		 4950 if (err)
4951 goto out_unbind;
4952
46bc8d4b 4953 err = il_dbgfs_register(il, DRV_NAME);
be663ab6 4954 if (err)
e7392364
SG		 4955 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4956 err);
be663ab6 4957
e7392364 4958 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
be663ab6 4959 if (err) {
9406f797 4960 IL_ERR("failed to create sysfs device attributes\n");
be663ab6
WYG		 4961 goto out_unbind;
4962 }
4963
4964 /* We have our copies now, allow OS release its copies */
4965 release_firmware(ucode_raw);
46bc8d4b 4966 complete(&il->_4965.firmware_loading_complete);
be663ab6
WYG		 4967 return;
4968
e7392364 4969try_again:
be663ab6 4970 /* try next, if any */
46bc8d4b 4971 if (il4965_request_firmware(il, false))
be663ab6
WYG		 4972 goto out_unbind;
4973 release_firmware(ucode_raw);
4974 return;
4975
e7392364 4976err_pci_alloc:
9406f797 4977 IL_ERR("failed to allocate pci memory\n");
46bc8d4b 4978 il4965_dealloc_ucode_pci(il);
e7392364 4979out_unbind:
46bc8d4b
SG		 4980 complete(&il->_4965.firmware_loading_complete);
4981 device_release_driver(&il->pci_dev->dev);
be663ab6
WYG		 4982 release_firmware(ucode_raw);
4983}
4984
e7392364 4985static const char *const desc_lookup_text[] = {
be663ab6
WYG		 4986 "OK",
4987 "FAIL",
4988 "BAD_PARAM",
4989 "BAD_CHECKSUM",
4990 "NMI_INTERRUPT_WDG",
4991 "SYSASSERT",
4992 "FATAL_ERROR",
4993 "BAD_COMMAND",
4994 "HW_ERROR_TUNE_LOCK",
4995 "HW_ERROR_TEMPERATURE",
4996 "ILLEGAL_CHAN_FREQ",
3b98c7f4 4997 "VCC_NOT_STBL",
9a95b370 4998 "FH49_ERROR",
be663ab6
WYG		 4999 "NMI_INTERRUPT_HOST",
5000 "NMI_INTERRUPT_ACTION_PT",
5001 "NMI_INTERRUPT_UNKNOWN",
5002 "UCODE_VERSION_MISMATCH",
5003 "HW_ERROR_ABS_LOCK",
5004 "HW_ERROR_CAL_LOCK_FAIL",
5005 "NMI_INTERRUPT_INST_ACTION_PT",
5006 "NMI_INTERRUPT_DATA_ACTION_PT",
5007 "NMI_TRM_HW_ER",
5008 "NMI_INTERRUPT_TRM",
861d9c3f 5009 "NMI_INTERRUPT_BREAK_POINT",
be663ab6
WYG		 5010 "DEBUG_0",
5011 "DEBUG_1",
5012 "DEBUG_2",
5013 "DEBUG_3",
5014};
5015
e7392364
SG		 5016static struct {
5017 char *name;
5018 u8 num;
5019} advanced_lookup[] = {
5020 {
5021 "NMI_INTERRUPT_WDG", 0x34}, {
5022 "SYSASSERT", 0x35}, {
5023 "UCODE_VERSION_MISMATCH", 0x37}, {
5024 "BAD_COMMAND", 0x38}, {
5025 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5026 "FATAL_ERROR", 0x3D}, {
5027 "NMI_TRM_HW_ERR", 0x46}, {
5028 "NMI_INTERRUPT_TRM", 0x4C}, {
5029 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5030 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5031 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5032 "NMI_INTERRUPT_HOST", 0x66}, {
5033 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5034 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5035 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5036"ADVANCED_SYSASSERT", 0},};
5037
5038static const char *
5039il4965_desc_lookup(u32 num)
be663ab6
WYG		 5040{
5041 int i;
5042 int max = ARRAY_SIZE(desc_lookup_text);
5043
5044 if (num < max)
5045 return desc_lookup_text[num];
5046
5047 max = ARRAY_SIZE(advanced_lookup) - 1;
5048 for (i = 0; i < max; i++) {
5049 if (advanced_lookup[i].num == num)
5050 break;
5051 }
5052 return advanced_lookup[i].name;
5053}
5054
5055#define ERROR_START_OFFSET (1 * sizeof(u32))
5056#define ERROR_ELEM_SIZE (7 * sizeof(u32))
5057
e7392364
SG		 5058void
5059il4965_dump_nic_error_log(struct il_priv *il)
be663ab6
WYG		 5060{
5061 u32 data2, line;
5062 u32 desc, time, count, base, data1;
5063 u32 blink1, blink2, ilink1, ilink2;
5064 u32 pc, hcmd;
5065
1722f8e1 5066 if (il->ucode_type == UCODE_INIT)
46bc8d4b 5067 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
1722f8e1 5068 else
46bc8d4b 5069 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
be663ab6 5070
1600b875 5071 if (!il->ops->is_valid_rtc_data_addr(base)) {
e7392364
SG		 5072 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5073 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
be663ab6
WYG		 5074 return;
5075 }
5076
46bc8d4b 5077 count = il_read_targ_mem(il, base);
be663ab6
WYG		 5078
5079 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 5080 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 5081 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
46bc8d4b
SG		 5082 }
5083
5084 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5085 il->isr_stats.err_code = desc;
5086 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5087 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5088 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5089 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5090 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5091 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5092 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5093 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5094 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5095 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5096
9406f797 5097 IL_ERR("Desc Time "
e7392364 5098 "data1 data2 line\n");
9406f797 5099 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
e7392364 5100 il4965_desc_lookup(desc), desc, time, data1, data2, line);
9406f797 5101 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
e7392364
SG		 5102 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5103 blink2, ilink1, ilink2, hcmd);
be663ab6
WYG		 5104}
5105
e7392364
SG		 5106static void
5107il4965_rf_kill_ct_config(struct il_priv *il)
be663ab6 5108{
e2ebc833 5109 struct il_ct_kill_config cmd;
be663ab6
WYG		 5110 unsigned long flags;
5111 int ret = 0;
5112
46bc8d4b 5113 spin_lock_irqsave(&il->lock, flags);
841b2cca 5114 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 5115 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
46bc8d4b 5116 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5117
5118 cmd.critical_temperature_R =
e7392364 5119 cpu_to_le32(il->hw_params.ct_kill_threshold);
be663ab6 5120
e7392364 5121 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
be663ab6 5122 if (ret)
4d69c752 5123 IL_ERR("C_CT_KILL_CONFIG failed\n");
be663ab6 5124 else
e7392364
SG		 5125 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5126 "critical temperature is %d\n",
5127 il->hw_params.ct_kill_threshold);
be663ab6
WYG		 5128}
5129
5130static const s8 default_queue_to_tx_fifo[] = {
e2ebc833
SG		 5131 IL_TX_FIFO_VO,
5132 IL_TX_FIFO_VI,
5133 IL_TX_FIFO_BE,
5134 IL_TX_FIFO_BK,
d3175167 5135 IL49_CMD_FIFO_NUM,
e2ebc833
SG		 5136 IL_TX_FIFO_UNUSED,
5137 IL_TX_FIFO_UNUSED,
be663ab6
WYG		 5138};
5139
e53aac42
SG		 5140#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5141
e7392364
SG		 5142static int
5143il4965_alive_notify(struct il_priv *il)
be663ab6
WYG		 5144{
5145 u32 a;
5146 unsigned long flags;
5147 int i, chan;
5148 u32 reg_val;
5149
46bc8d4b 5150 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5151
5152 /* Clear 4965's internal Tx Scheduler data base */
e7392364 5153 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
d3175167
SG		 5154 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5155 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
46bc8d4b 5156 il_write_targ_mem(il, a, 0);
d3175167 5157 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
46bc8d4b 5158 il_write_targ_mem(il, a, 0);
e7392364
SG		 5159 for (;
5160 a <
5161 il->scd_base_addr +
5162 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5163 a += 4)
46bc8d4b 5164 il_write_targ_mem(il, a, 0);
be663ab6
WYG		 5165
5166 /* Tel 4965 where to find Tx byte count tables */
e7392364 5167 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
be663ab6
WYG		 5168
5169 /* Enable DMA channel */
e7392364
SG		 5170 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5171 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5172 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5173 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
be663ab6
WYG		 5174
5175 /* Update FH chicken bits */
9a95b370
SG		 5176 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5177 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
e7392364 5178 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
be663ab6
WYG		 5179
5180 /* Disable chain mode for all queues */
d3175167 5181 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
be663ab6
WYG		 5182
5183 /* Initialize each Tx queue (including the command queue) */
46bc8d4b 5184 for (i = 0; i < il->hw_params.max_txq_num; i++) {
be663ab6 5185
0c2c8852 5186 /* TFD circular buffer read/write idxes */
d3175167 5187 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
0c1a94e2 5188 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
be663ab6
WYG		 5189
5190 /* Max Tx Window size for Scheduler-ACK mode */
e7392364
SG		 5191 il_write_targ_mem(il,
5192 il->scd_base_addr +
5193 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5194 (SCD_WIN_SIZE <<
5195 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5196 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
be663ab6
WYG		 5197
5198 /* Frame limit */
e7392364
SG		 5199 il_write_targ_mem(il,
5200 il->scd_base_addr +
5201 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5202 sizeof(u32),
5203 (SCD_FRAME_LIMIT <<
5204 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5205 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
be663ab6
WYG		 5206
5207 }
d3175167 5208 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
e7392364 5209 (1 << il->hw_params.max_txq_num) - 1);
be663ab6
WYG		 5210
5211 /* Activate all Tx DMA/FIFO channels */
46bc8d4b 5212 il4965_txq_set_sched(il, IL_MASK(0, 6));
be663ab6 5213
46bc8d4b 5214 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
be663ab6
WYG		 5215
5216 /* make sure all queue are not stopped */
46bc8d4b 5217 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
be663ab6 5218 for (i = 0; i < 4; i++)
46bc8d4b 5219 atomic_set(&il->queue_stop_count[i], 0);
be663ab6
WYG		 5220
5221 /* reset to 0 to enable all the queue first */
46bc8d4b 5222 il->txq_ctx_active_msk = 0;
be663ab6
WYG		 5223 /* Map each Tx/cmd queue to its corresponding fifo */
5224 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5225
5226 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5227 int ac = default_queue_to_tx_fifo[i];
5228
46bc8d4b 5229 il_txq_ctx_activate(il, i);
be663ab6 5230
e2ebc833 5231 if (ac == IL_TX_FIFO_UNUSED)
be663ab6
WYG		 5232 continue;
5233
46bc8d4b 5234 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
be663ab6
WYG		 5235 }
5236
46bc8d4b 5237 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5238
5239 return 0;
5240}
5241
5242/**
4d69c752 5243 * il4965_alive_start - called after N_ALIVE notification received
be663ab6 5244 * from protocol/runtime uCode (initialization uCode's
e2ebc833 5245 * Alive gets handled by il_init_alive_start()).
be663ab6 5246 */
e7392364
SG		 5247static void
5248il4965_alive_start(struct il_priv *il)
be663ab6
WYG		 5249{
5250 int ret = 0;
be663ab6 5251
58de00a4 5252 D_INFO("Runtime Alive received.\n");
be663ab6 5253
46bc8d4b 5254 if (il->card_alive.is_valid != UCODE_VALID_OK) {
be663ab6
WYG		 5255 /* We had an error bringing up the hardware, so take it
5256 * all the way back down so we can try again */
58de00a4 5257 D_INFO("Alive failed.\n");
be663ab6
WYG		 5258 goto restart;
5259 }
5260
5261 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5262 * This is a paranoid check, because we would not have gotten the
5263 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 5264 if (il4965_verify_ucode(il)) {
be663ab6
WYG		 5265 /* Runtime instruction load was bad;
5266 * take it all the way back down so we can try again */
58de00a4 5267 D_INFO("Bad runtime uCode load.\n");
be663ab6
WYG		 5268 goto restart;
5269 }
5270
46bc8d4b 5271 ret = il4965_alive_notify(il);
be663ab6 5272 if (ret) {
e7392364 5273 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
be663ab6
WYG		 5274 goto restart;
5275 }
5276
be663ab6 5277 /* After the ALIVE response, we can send host commands to the uCode */
a6766ccd 5278 set_bit(S_ALIVE, &il->status);
be663ab6
WYG		 5279
5280 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 5281 il_setup_watchdog(il);
be663ab6 5282
46bc8d4b 5283 if (il_is_rfkill(il))
be663ab6
WYG		 5284 return;
5285
46bc8d4b 5286 ieee80211_wake_queues(il->hw);
be663ab6 5287
2eb05816 5288 il->active_rate = RATES_MASK;
be663ab6 5289
c8b03958 5290 if (il_is_associated(il)) {
e2ebc833 5291 struct il_rxon_cmd *active_rxon =
c8b03958 5292 (struct il_rxon_cmd *)&il->active;
be663ab6 5293 /* apply any changes in staging */
c8b03958 5294 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5295 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5296 } else {
be663ab6 5297 /* Initialize our rx_config data */
83007196 5298 il_connection_init_rx_config(il);
be663ab6 5299
c9363551
SG		 5300 if (il->ops->set_rxon_chain)
5301 il->ops->set_rxon_chain(il);
be663ab6
WYG		 5302 }
5303
5304 /* Configure bluetooth coexistence if enabled */
46bc8d4b 5305 il_send_bt_config(il);
be663ab6 5306
46bc8d4b 5307 il4965_reset_run_time_calib(il);
be663ab6 5308
a6766ccd 5309 set_bit(S_READY, &il->status);
be663ab6
WYG		 5310
5311 /* Configure the adapter for unassociated operation */
83007196 5312 il_commit_rxon(il);
be663ab6
WYG		 5313
5314 /* At this point, the NIC is initialized and operational */
46bc8d4b 5315 il4965_rf_kill_ct_config(il);
be663ab6 5316
58de00a4 5317 D_INFO("ALIVE processing complete.\n");
46bc8d4b 5318 wake_up(&il->wait_command_queue);
be663ab6 5319
46bc8d4b 5320 il_power_update_mode(il, true);
58de00a4 5321 D_INFO("Updated power mode\n");
be663ab6
WYG		 5322
5323 return;
5324
e7392364 5325restart:
46bc8d4b 5326 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 5327}
5328
46bc8d4b 5329static void il4965_cancel_deferred_work(struct il_priv *il);
be663ab6 5330
e7392364
SG		 5331static void
5332__il4965_down(struct il_priv *il)
be663ab6
WYG		 5333{
5334 unsigned long flags;
ab42b404 5335 int exit_pending;
be663ab6 5336
58de00a4 5337 D_INFO(DRV_NAME " is going down\n");
be663ab6 5338
46bc8d4b 5339 il_scan_cancel_timeout(il, 200);
be663ab6 5340
a6766ccd 5341 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
be663ab6 5342
a6766ccd 5343 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
be663ab6 5344 * to prevent rearm timer */
46bc8d4b 5345 del_timer_sync(&il->watchdog);
be663ab6 5346
83007196 5347 il_clear_ucode_stations(il);
d735f921
SG		 5348
5349 /* FIXME: race conditions ? */
5350 spin_lock_irq(&il->sta_lock);
5351 /*
5352 * Remove all key information that is not stored as part
5353 * of station information since mac80211 may not have had
5354 * a chance to remove all the keys. When device is
5355 * reconfigured by mac80211 after an error all keys will
5356 * be reconfigured.
5357 */
5358 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5359 il->_4965.key_mapping_keys = 0;
5360 spin_unlock_irq(&il->sta_lock);
5361
46bc8d4b
SG		 5362 il_dealloc_bcast_stations(il);
5363 il_clear_driver_stations(il);
be663ab6
WYG		 5364
5365 /* Unblock any waiting calls */
46bc8d4b 5366 wake_up_all(&il->wait_command_queue);
be663ab6
WYG		 5367
5368 /* Wipe out the EXIT_PENDING status bit if we are not actually
5369 * exiting the module */
5370 if (!exit_pending)
a6766ccd 5371 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5372
5373 /* stop and reset the on-board processor */
841b2cca 5374 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6
WYG		 5375
5376 /* tell the device to stop sending interrupts */
46bc8d4b
SG		 5377 spin_lock_irqsave(&il->lock, flags);
5378 il_disable_interrupts(il);
5379 spin_unlock_irqrestore(&il->lock, flags);
5380 il4965_synchronize_irq(il);
be663ab6 5381
46bc8d4b
SG		 5382 if (il->mac80211_registered)
5383 ieee80211_stop_queues(il->hw);
be663ab6 5384
e2ebc833 5385 /* If we have not previously called il_init() then
be663ab6 5386 * clear all bits but the RF Kill bit and return */
46bc8d4b 5387 if (!il_is_init(il)) {
e7392364 5388 il->status =
bc269a8e 5389 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0 5390 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
e7392364 5391 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6
WYG		 5392 goto exit;
5393 }
5394
5395 /* ...otherwise clear out all the status bits but the RF Kill
5396 * bit and continue taking the NIC down. */
e7392364 5397 il->status &=
bc269a8e 5398 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0
SG		 5399 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5400 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
e7392364 5401 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6 5402
775ed8ab
SG		 5403 /*
5404 * We disabled and synchronized interrupt, and priv->mutex is taken, so
5405 * here is the only thread which will program device registers, but
5406 * still have lockdep assertions, so we are taking reg_lock.
5407 */
5408 spin_lock_irq(&il->reg_lock);
5409 /* FIXME: il_grab_nic_access if rfkill is off ? */
5410
46bc8d4b
SG		 5411 il4965_txq_ctx_stop(il);
5412 il4965_rxq_stop(il);
be663ab6 5413 /* Power-down device's busmaster DMA clocks */
775ed8ab 5414 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6 5415 udelay(5);
be663ab6 5416 /* Make sure (redundant) we've released our request to stay awake */
775ed8ab 5417 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
be663ab6 5418 /* Stop the device, and put it in low power state */
775ed8ab
SG		 5419 _il_apm_stop(il);
5420
5421 spin_unlock_irq(&il->reg_lock);
be663ab6 5422
775ed8ab 5423 il4965_txq_ctx_unmap(il);
e7392364 5424exit:
46bc8d4b 5425 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
be663ab6 5426
46bc8d4b
SG		 5427 dev_kfree_skb(il->beacon_skb);
5428 il->beacon_skb = NULL;
be663ab6
WYG		 5429
5430 /* clear out any free frames */
46bc8d4b 5431 il4965_clear_free_frames(il);
be663ab6
WYG		 5432}
5433
e7392364
SG		 5434static void
5435il4965_down(struct il_priv *il)
be663ab6 5436{
46bc8d4b
SG		 5437 mutex_lock(&il->mutex);
5438 __il4965_down(il);
5439 mutex_unlock(&il->mutex);
be663ab6 5440
46bc8d4b 5441 il4965_cancel_deferred_work(il);
be663ab6
WYG		 5442}
5443
be663ab6 5444
71e0c6c2 5445static void
e7392364 5446il4965_set_hw_ready(struct il_priv *il)
be663ab6 5447{
71e0c6c2 5448 int ret;
be663ab6 5449
46bc8d4b 5450 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 5451 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
be663ab6
WYG		 5452
5453 /* See if we got it */
71e0c6c2
SG		 5454 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5455 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5456 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5457 100);
5458 if (ret >= 0)
46bc8d4b 5459 il->hw_ready = true;
be663ab6 5460
71e0c6c2 5461 D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not");
be663ab6
WYG		 5462}
5463
71e0c6c2 5464static void
e7392364 5465il4965_prepare_card_hw(struct il_priv *il)
be663ab6 5466{
71e0c6c2 5467 int ret;
be663ab6 5468
71e0c6c2 5469 il->hw_ready = false;
be663ab6 5470
71e0c6c2 5471 il4965_set_hw_ready(il);
46bc8d4b 5472 if (il->hw_ready)
71e0c6c2 5473 return;
be663ab6
WYG		 5474
5475 /* If HW is not ready, prepare the conditions to check again */
e7392364 5476 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
be663ab6 5477
e7392364
SG		 5478 ret =
5479 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5480 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5481 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
be663ab6
WYG		 5482
5483 /* HW should be ready by now, check again. */
5484 if (ret != -ETIMEDOUT)
46bc8d4b 5485 il4965_set_hw_ready(il);
be663ab6
WYG		 5486}
5487
5488#define MAX_HW_RESTARTS 5
5489
e7392364
SG		 5490static int
5491__il4965_up(struct il_priv *il)
be663ab6 5492{
be663ab6
WYG		 5493 int i;
5494 int ret;
5495
a6766ccd 5496 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 5497 IL_WARN("Exit pending; will not bring the NIC up\n");
be663ab6
WYG		 5498 return -EIO;
5499 }
5500
46bc8d4b 5501 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 5502 IL_ERR("ucode not available for device bringup\n");
be663ab6
WYG		 5503 return -EIO;
5504 }
5505
83007196 5506 ret = il4965_alloc_bcast_station(il);
17d6e557
SG		 5507 if (ret) {
5508 il_dealloc_bcast_stations(il);
5509 return ret;
be663ab6
WYG		 5510 }
5511
46bc8d4b 5512 il4965_prepare_card_hw(il);
46bc8d4b 5513 if (!il->hw_ready) {
71e0c6c2 5514 IL_ERR("HW not ready\n");
be663ab6
WYG		 5515 return -EIO;
5516 }
5517
5518 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 5519 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 5520 clear_bit(S_RFKILL, &il->status);
3976b451 5521 else {
bc269a8e 5522 set_bit(S_RFKILL, &il->status);
46bc8d4b 5523 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
be663ab6 5524
3976b451 5525 il_enable_rfkill_int(il);
9406f797 5526 IL_WARN("Radio disabled by HW RF Kill switch\n");
be663ab6
WYG		 5527 return 0;
5528 }
5529
841b2cca 5530 _il_wr(il, CSR_INT, 0xFFFFFFFF);
be663ab6 5531
e2ebc833 5532 /* must be initialised before il_hw_nic_init */
46bc8d4b 5533 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
be663ab6 5534
46bc8d4b 5535 ret = il4965_hw_nic_init(il);
be663ab6 5536 if (ret) {
9406f797 5537 IL_ERR("Unable to init nic\n");
be663ab6
WYG		 5538 return ret;
5539 }
5540
5541 /* make sure rfkill handshake bits are cleared */
841b2cca 5542 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 5543 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6
WYG		 5544
5545 /* clear (again), then enable host interrupts */
841b2cca 5546 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5547 il_enable_interrupts(il);
be663ab6
WYG		 5548
5549 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG		 5550 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5551 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
be663ab6
WYG		 5552
5553 /* Copy original ucode data image from disk into backup cache.
5554 * This will be used to initialize the on-board processor's
5555 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG		 5556 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5557 il->ucode_data.len);
be663ab6
WYG		 5558
5559 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5560
5561 /* load bootstrap state machine,
5562 * load bootstrap program into processor's memory,
5563 * prepare to load the "initialize" uCode */
1600b875 5564 ret = il->ops->load_ucode(il);
be663ab6
WYG		 5565
5566 if (ret) {
e7392364 5567 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
be663ab6
WYG		 5568 continue;
5569 }
5570
5571 /* start card; "initialize" will load runtime ucode */
46bc8d4b 5572 il4965_nic_start(il);
be663ab6 5573
58de00a4 5574 D_INFO(DRV_NAME " is coming up\n");
be663ab6
WYG		 5575
5576 return 0;
5577 }
5578
a6766ccd 5579 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 5580 __il4965_down(il);
a6766ccd 5581 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5582
5583 /* tried to restart and config the device for as long as our
5584 * patience could withstand */
9406f797 5585 IL_ERR("Unable to initialize device after %d attempts.\n", i);
be663ab6
WYG		 5586 return -EIO;
5587}
5588
be663ab6
WYG		 5589/*****************************************************************************
5590 *
5591 * Workqueue callbacks
5592 *
5593 *****************************************************************************/
5594
e7392364
SG		 5595static void
5596il4965_bg_init_alive_start(struct work_struct *data)
be663ab6 5597{
46bc8d4b 5598 struct il_priv *il =
e2ebc833 5599 container_of(data, struct il_priv, init_alive_start.work);
be663ab6 5600
46bc8d4b 5601 mutex_lock(&il->mutex);
a6766ccd 5602 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5603 goto out;
be663ab6 5604
1600b875 5605 il->ops->init_alive_start(il);
28a6e577 5606out:
46bc8d4b 5607 mutex_unlock(&il->mutex);
be663ab6
WYG		 5608}
5609
e7392364
SG		 5610static void
5611il4965_bg_alive_start(struct work_struct *data)
be663ab6 5612{
46bc8d4b 5613 struct il_priv *il =
e2ebc833 5614 container_of(data, struct il_priv, alive_start.work);
be663ab6 5615
46bc8d4b 5616 mutex_lock(&il->mutex);
a6766ccd 5617 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5618 goto out;
be663ab6 5619
46bc8d4b 5620 il4965_alive_start(il);
28a6e577 5621out:
46bc8d4b 5622 mutex_unlock(&il->mutex);
be663ab6
WYG		 5623}
5624
e7392364
SG		 5625static void
5626il4965_bg_run_time_calib_work(struct work_struct *work)
be663ab6 5627{
46bc8d4b 5628 struct il_priv *il = container_of(work, struct il_priv,
e7392364 5629 run_time_calib_work);
be663ab6 5630
46bc8d4b 5631 mutex_lock(&il->mutex);
be663ab6 5632
a6766ccd
SG		 5633 if (test_bit(S_EXIT_PENDING, &il->status) ||
5634 test_bit(S_SCANNING, &il->status)) {
46bc8d4b 5635 mutex_unlock(&il->mutex);
be663ab6
WYG		 5636 return;
5637 }
5638
46bc8d4b 5639 if (il->start_calib) {
e7392364
SG		 5640 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5641 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
be663ab6
WYG		 5642 }
5643
46bc8d4b 5644 mutex_unlock(&il->mutex);
be663ab6
WYG		 5645}
5646
e7392364
SG		 5647static void
5648il4965_bg_restart(struct work_struct *data)
be663ab6 5649{
46bc8d4b 5650 struct il_priv *il = container_of(data, struct il_priv, restart);
be663ab6 5651
a6766ccd 5652 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5653 return;
5654
a6766ccd 5655 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 5656 mutex_lock(&il->mutex);
46bc8d4b 5657 il->is_open = 0;
be663ab6 5658
46bc8d4b 5659 __il4965_down(il);
be663ab6 5660
46bc8d4b
SG		 5661 mutex_unlock(&il->mutex);
5662 il4965_cancel_deferred_work(il);
5663 ieee80211_restart_hw(il->hw);
be663ab6 5664 } else {
46bc8d4b 5665 il4965_down(il);
be663ab6 5666
46bc8d4b 5667 mutex_lock(&il->mutex);
a6766ccd 5668 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 5669 mutex_unlock(&il->mutex);
be663ab6 5670 return;
28a6e577 5671 }
be663ab6 5672
46bc8d4b
SG		 5673 __il4965_up(il);
5674 mutex_unlock(&il->mutex);
be663ab6
WYG		 5675 }
5676}
5677
e7392364
SG		 5678static void
5679il4965_bg_rx_replenish(struct work_struct *data)
be663ab6 5680{
e7392364 5681 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
be663ab6 5682
a6766ccd 5683 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5684 return;
5685
46bc8d4b
SG		 5686 mutex_lock(&il->mutex);
5687 il4965_rx_replenish(il);
5688 mutex_unlock(&il->mutex);
be663ab6
WYG		 5689}
5690
5691/*****************************************************************************
5692 *
5693 * mac80211 entry point functions
5694 *
5695 *****************************************************************************/
5696
5697#define UCODE_READY_TIMEOUT (4 * HZ)
5698
5699/*
5700 * Not a mac80211 entry point function, but it fits in with all the
5701 * other mac80211 functions grouped here.
5702 */
e7392364
SG		 5703static int
5704il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
be663ab6
WYG		 5705{
5706 int ret;
46bc8d4b 5707 struct ieee80211_hw *hw = il->hw;
be663ab6
WYG		 5708
5709 hw->rate_control_algorithm = "iwl-4965-rs";
5710
5711 /* Tell mac80211 our characteristics */
e7392364
SG		 5712 hw->flags =
5713 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
5714 IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT |
5715 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
be663ab6 5716
46bc8d4b 5717 if (il->cfg->sku & IL_SKU_N)
e7392364
SG		 5718 hw->flags |=
5719 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5720 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
be663ab6 5721
e2ebc833
SG		 5722 hw->sta_data_size = sizeof(struct il_station_priv);
5723 hw->vif_data_size = sizeof(struct il_vif_priv);
be663ab6 5724
8c9c48d5
SG		 5725 hw->wiphy->interface_modes =
5726 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
be663ab6 5727
e7392364 5728 hw->wiphy->flags |=
d7fbcada
SG		 5729 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS |
5730 WIPHY_FLAG_IBSS_RSN;
be663ab6
WYG		 5731
5732 /*
5733 * For now, disable PS by default because it affects
5734 * RX performance significantly.
5735 */
5736 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5737
5738 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5739 /* we create the 802.11 header and a zero-length SSID element */
5740 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5741
5742 /* Default value; 4 EDCA QOS priorities */
5743 hw->queues = 4;
5744
e2ebc833 5745 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
be663ab6 5746
46bc8d4b
SG		 5747 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5748 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 5749 &il->bands[IEEE80211_BAND_2GHZ];
46bc8d4b
SG		 5750 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5751 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 5752 &il->bands[IEEE80211_BAND_5GHZ];
be663ab6 5753
46bc8d4b 5754 il_leds_init(il);
be663ab6 5755
46bc8d4b 5756 ret = ieee80211_register_hw(il->hw);
be663ab6 5757 if (ret) {
9406f797 5758 IL_ERR("Failed to register hw (error %d)\n", ret);
be663ab6
WYG		 5759 return ret;
5760 }
46bc8d4b 5761 il->mac80211_registered = 1;
be663ab6
WYG		 5762
5763 return 0;
5764}
5765
e7392364
SG		 5766int
5767il4965_mac_start(struct ieee80211_hw *hw)
be663ab6 5768{
46bc8d4b 5769 struct il_priv *il = hw->priv;
be663ab6
WYG		 5770 int ret;
5771
58de00a4 5772 D_MAC80211("enter\n");
be663ab6
WYG		 5773
5774 /* we should be verifying the device is ready to be opened */
46bc8d4b
SG		 5775 mutex_lock(&il->mutex);
5776 ret = __il4965_up(il);
5777 mutex_unlock(&il->mutex);
be663ab6
WYG		 5778
5779 if (ret)
5780 return ret;
5781
46bc8d4b 5782 if (il_is_rfkill(il))
be663ab6
WYG		 5783 goto out;
5784
58de00a4 5785 D_INFO("Start UP work done.\n");
be663ab6
WYG		 5786
5787 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5788 * mac80211 will not be run successfully. */
46bc8d4b 5789 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 5790 test_bit(S_READY, &il->status),
5791 UCODE_READY_TIMEOUT);
be663ab6 5792 if (!ret) {
a6766ccd 5793 if (!test_bit(S_READY, &il->status)) {
9406f797 5794 IL_ERR("START_ALIVE timeout after %dms.\n",
be663ab6
WYG		 5795 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5796 return -ETIMEDOUT;
5797 }
5798 }
5799
46bc8d4b 5800 il4965_led_enable(il);
be663ab6
WYG		 5801
5802out:
46bc8d4b 5803 il->is_open = 1;
58de00a4 5804 D_MAC80211("leave\n");
be663ab6
WYG		 5805 return 0;
5806}
5807
e7392364
SG		 5808void
5809il4965_mac_stop(struct ieee80211_hw *hw)
be663ab6 5810{
46bc8d4b 5811 struct il_priv *il = hw->priv;
be663ab6 5812
58de00a4 5813 D_MAC80211("enter\n");
be663ab6 5814
46bc8d4b 5815 if (!il->is_open)
be663ab6
WYG		 5816 return;
5817
46bc8d4b 5818 il->is_open = 0;
be663ab6 5819
46bc8d4b 5820 il4965_down(il);
be663ab6 5821
46bc8d4b 5822 flush_workqueue(il->workqueue);
be663ab6 5823
a078a1fd
SG		 5824 /* User space software may expect getting rfkill changes
5825 * even if interface is down */
841b2cca 5826 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5827 il_enable_rfkill_int(il);
be663ab6 5828
58de00a4 5829 D_MAC80211("leave\n");
be663ab6
WYG		 5830}
5831
e7392364 5832void
36323f81
TH		 5833il4965_mac_tx(struct ieee80211_hw *hw,
5834 struct ieee80211_tx_control *control,
5835 struct sk_buff *skb)
be663ab6 5836{
46bc8d4b 5837 struct il_priv *il = hw->priv;
be663ab6 5838
58de00a4 5839 D_MACDUMP("enter\n");
be663ab6 5840
58de00a4 5841 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 5842 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
be663ab6 5843
36323f81 5844 if (il4965_tx_skb(il, control->sta, skb))
be663ab6
WYG		 5845 dev_kfree_skb_any(skb);
5846
58de00a4 5847 D_MACDUMP("leave\n");
be663ab6
WYG		 5848}
5849
e7392364
SG		 5850void
5851il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5852 struct ieee80211_key_conf *keyconf,
5853 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
be663ab6 5854{
46bc8d4b 5855 struct il_priv *il = hw->priv;
be663ab6 5856
58de00a4 5857 D_MAC80211("enter\n");
be663ab6 5858
83007196 5859 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
be663ab6 5860
58de00a4 5861 D_MAC80211("leave\n");
be663ab6
WYG		 5862}
5863
e7392364
SG		 5864int
5865il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5866 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5867 struct ieee80211_key_conf *key)
be663ab6 5868{
46bc8d4b 5869 struct il_priv *il = hw->priv;
be663ab6
WYG		 5870 int ret;
5871 u8 sta_id;
5872 bool is_default_wep_key = false;
5873
58de00a4 5874 D_MAC80211("enter\n");
be663ab6 5875
46bc8d4b 5876 if (il->cfg->mod_params->sw_crypto) {
58de00a4 5877 D_MAC80211("leave - hwcrypto disabled\n");
be663ab6
WYG		 5878 return -EOPNOTSUPP;
5879 }
5880
d7fbcada
SG		 5881 /*
5882 * To support IBSS RSN, don't program group keys in IBSS, the
5883 * hardware will then not attempt to decrypt the frames.
5884 */
5885 if (vif->type == NL80211_IFTYPE_ADHOC &&
5886 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
5887 D_MAC80211("leave - ad-hoc group key\n");
5888 return -EOPNOTSUPP;
5889 }
5890
83007196 5891 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 5892 if (sta_id == IL_INVALID_STATION)
be663ab6
WYG		 5893 return -EINVAL;
5894
46bc8d4b
SG		 5895 mutex_lock(&il->mutex);
5896 il_scan_cancel_timeout(il, 100);
be663ab6
WYG		 5897
5898 /*
5899 * If we are getting WEP group key and we didn't receive any key mapping
5900 * so far, we are in legacy wep mode (group key only), otherwise we are
5901 * in 1X mode.
5902 * In legacy wep mode, we use another host command to the uCode.
5903 */
5904 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
e7392364 5905 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
be663ab6 5906 if (cmd == SET_KEY)
d735f921 5907 is_default_wep_key = !il->_4965.key_mapping_keys;
be663ab6
WYG		 5908 else
5909 is_default_wep_key =
e7392364 5910 (key->hw_key_idx == HW_KEY_DEFAULT);
be663ab6
WYG		 5911 }
5912
5913 switch (cmd) {
5914 case SET_KEY:
5915 if (is_default_wep_key)
83007196 5916 ret = il4965_set_default_wep_key(il, key);
be663ab6 5917 else
83007196 5918 ret = il4965_set_dynamic_key(il, key, sta_id);
be663ab6 5919
58de00a4 5920 D_MAC80211("enable hwcrypto key\n");
be663ab6
WYG		 5921 break;
5922 case DISABLE_KEY:
5923 if (is_default_wep_key)
83007196 5924 ret = il4965_remove_default_wep_key(il, key);
be663ab6 5925 else
83007196 5926 ret = il4965_remove_dynamic_key(il, key, sta_id);
be663ab6 5927
58de00a4 5928 D_MAC80211("disable hwcrypto key\n");
be663ab6
WYG		 5929 break;
5930 default:
5931 ret = -EINVAL;
5932 }
5933
46bc8d4b 5934 mutex_unlock(&il->mutex);
58de00a4 5935 D_MAC80211("leave\n");
be663ab6
WYG		 5936
5937 return ret;
5938}
5939
e7392364
SG		 5940int
5941il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5942 enum ieee80211_ampdu_mlme_action action,
5943 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5944 u8 buf_size)
be663ab6 5945{
46bc8d4b 5946 struct il_priv *il = hw->priv;
be663ab6
WYG		 5947 int ret = -EINVAL;
5948
e7392364 5949 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
be663ab6 5950
46bc8d4b 5951 if (!(il->cfg->sku & IL_SKU_N))
be663ab6
WYG		 5952 return -EACCES;
5953
46bc8d4b 5954 mutex_lock(&il->mutex);
be663ab6
WYG		 5955
5956 switch (action) {
5957 case IEEE80211_AMPDU_RX_START:
58de00a4 5958 D_HT("start Rx\n");
46bc8d4b 5959 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
be663ab6
WYG		 5960 break;
5961 case IEEE80211_AMPDU_RX_STOP:
58de00a4 5962 D_HT("stop Rx\n");
46bc8d4b 5963 ret = il4965_sta_rx_agg_stop(il, sta, tid);
a6766ccd 5964 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5965 ret = 0;
5966 break;
5967 case IEEE80211_AMPDU_TX_START:
58de00a4 5968 D_HT("start Tx\n");
46bc8d4b 5969 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
be663ab6
WYG		 5970 break;
5971 case IEEE80211_AMPDU_TX_STOP:
58de00a4 5972 D_HT("stop Tx\n");
46bc8d4b 5973 ret = il4965_tx_agg_stop(il, vif, sta, tid);
a6766ccd 5974 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5975 ret = 0;
5976 break;
5977 case IEEE80211_AMPDU_TX_OPERATIONAL:
5978 ret = 0;
5979 break;
5980 }
46bc8d4b 5981 mutex_unlock(&il->mutex);
be663ab6
WYG		 5982
5983 return ret;
5984}
5985
e7392364
SG		 5986int
5987il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5988 struct ieee80211_sta *sta)
be663ab6 5989{
46bc8d4b 5990 struct il_priv *il = hw->priv;
e2ebc833 5991 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
be663ab6
WYG		 5992 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
5993 int ret;
5994 u8 sta_id;
5995
e7392364 5996 D_INFO("received request to add station %pM\n", sta->addr);
46bc8d4b 5997 mutex_lock(&il->mutex);
e7392364 5998 D_INFO("proceeding to add station %pM\n", sta->addr);
e2ebc833 5999 sta_priv->common.sta_id = IL_INVALID_STATION;
be663ab6
WYG		 6000
6001 atomic_set(&sta_priv->pending_frames, 0);
6002
e7392364 6003 ret =
83007196 6004 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
be663ab6 6005 if (ret) {
e7392364 6006 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
be663ab6 6007 /* Should we return success if return code is EEXIST ? */
46bc8d4b 6008 mutex_unlock(&il->mutex);
be663ab6
WYG		 6009 return ret;
6010 }
6011
6012 sta_priv->common.sta_id = sta_id;
6013
6014 /* Initialize rate scaling */
e7392364 6015 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG		 6016 il4965_rs_rate_init(il, sta, sta_id);
6017 mutex_unlock(&il->mutex);
be663ab6
WYG		 6018
6019 return 0;
6020}
6021
e7392364
SG		 6022void
6023il4965_mac_channel_switch(struct ieee80211_hw *hw,
6024 struct ieee80211_channel_switch *ch_switch)
be663ab6 6025{
46bc8d4b 6026 struct il_priv *il = hw->priv;
e2ebc833 6027 const struct il_channel_info *ch_info;
be663ab6
WYG		 6028 struct ieee80211_conf *conf = &hw->conf;
6029 struct ieee80211_channel *channel = ch_switch->channel;
46bc8d4b 6030 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6 6031 u16 ch;
be663ab6 6032
58de00a4 6033 D_MAC80211("enter\n");
be663ab6 6034
46bc8d4b 6035 mutex_lock(&il->mutex);
28a6e577 6036
46bc8d4b 6037 if (il_is_rfkill(il))
28a6e577 6038 goto out;
be663ab6 6039
a6766ccd
SG		 6040 if (test_bit(S_EXIT_PENDING, &il->status) ||
6041 test_bit(S_SCANNING, &il->status) ||
6042 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
28a6e577 6043 goto out;
be663ab6 6044
c8b03958 6045 if (!il_is_associated(il))
28a6e577 6046 goto out;
be663ab6 6047
1600b875 6048 if (!il->ops->set_channel_switch)
7f1f9742 6049 goto out;
be663ab6 6050
7f1f9742 6051 ch = channel->hw_value;
c8b03958 6052 if (le16_to_cpu(il->active.channel) == ch)
7f1f9742
SG		 6053 goto out;
6054
46bc8d4b 6055 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 6056 if (!il_is_channel_valid(ch_info)) {
58de00a4 6057 D_MAC80211("invalid channel\n");
7f1f9742
SG		 6058 goto out;
6059 }
6060
46bc8d4b 6061 spin_lock_irq(&il->lock);
7f1f9742 6062
46bc8d4b 6063 il->current_ht_config.smps = conf->smps_mode;
7f1f9742
SG		 6064
6065 /* Configure HT40 channels */
1c03c462
SG		 6066 il->ht.enabled = conf_is_ht(conf);
6067 if (il->ht.enabled) {
7f1f9742 6068 if (conf_is_ht40_minus(conf)) {
1c03c462 6069 il->ht.extension_chan_offset =
e7392364 6070 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 6071 il->ht.is_40mhz = true;
7f1f9742 6072 } else if (conf_is_ht40_plus(conf)) {
1c03c462 6073 il->ht.extension_chan_offset =
e7392364 6074 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 6075 il->ht.is_40mhz = true;
7f1f9742 6076 } else {
1c03c462 6077 il->ht.extension_chan_offset =
e7392364 6078 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 6079 il->ht.is_40mhz = false;
be663ab6 6080 }
7f1f9742 6081 } else
1c03c462 6082 il->ht.is_40mhz = false;
7f1f9742 6083
c8b03958
SG		 6084 if ((le16_to_cpu(il->staging.channel) != ch))
6085 il->staging.flags = 0;
7f1f9742 6086
83007196 6087 il_set_rxon_channel(il, channel);
46bc8d4b 6088 il_set_rxon_ht(il, ht_conf);
83007196 6089 il_set_flags_for_band(il, channel->band, il->vif);
7f1f9742 6090
46bc8d4b 6091 spin_unlock_irq(&il->lock);
7f1f9742 6092
46bc8d4b 6093 il_set_rate(il);
7f1f9742
SG		 6094 /*
6095 * at this point, staging_rxon has the
6096 * configuration for channel switch
6097 */
a6766ccd 6098 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6099 il->switch_channel = cpu_to_le16(ch);
1600b875 6100 if (il->ops->set_channel_switch(il, ch_switch)) {
a6766ccd 6101 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6102 il->switch_channel = 0;
83007196 6103 ieee80211_chswitch_done(il->vif, false);
be663ab6 6104 }
7f1f9742 6105
be663ab6 6106out:
46bc8d4b 6107 mutex_unlock(&il->mutex);
58de00a4 6108 D_MAC80211("leave\n");
be663ab6
WYG		 6109}
6110
e7392364
SG		 6111void
6112il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6113 unsigned int *total_flags, u64 multicast)
be663ab6 6114{
46bc8d4b 6115 struct il_priv *il = hw->priv;
be663ab6 6116 __le32 filter_or = 0, filter_nand = 0;
be663ab6
WYG		 6117
6118#define CHK(test, flag) do { \
6119 if (*total_flags & (test)) \
6120 filter_or |= (flag); \
6121 else \
6122 filter_nand |= (flag); \
6123 } while (0)
6124
e7392364
SG		 6125 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6126 *total_flags);
be663ab6
WYG		 6127
6128 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
6129 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6130 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6131 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6132
6133#undef CHK
6134
46bc8d4b 6135 mutex_lock(&il->mutex);
be663ab6 6136
c8b03958
SG		 6137 il->staging.filter_flags &= ~filter_nand;
6138 il->staging.filter_flags |= filter_or;
be663ab6 6139
17d6e557
SG		 6140 /*
6141 * Not committing directly because hardware can perform a scan,
6142 * but we'll eventually commit the filter flags change anyway.
6143 */
be663ab6 6144
46bc8d4b 6145 mutex_unlock(&il->mutex);
be663ab6
WYG		 6146
6147 /*
6148 * Receiving all multicast frames is always enabled by the
e2ebc833 6149 * default flags setup in il_connection_init_rx_config()
be663ab6
WYG		 6150 * since we currently do not support programming multicast
6151 * filters into the device.
6152 */
e7392364
SG		 6153 *total_flags &=
6154 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
6155 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
be663ab6
WYG		 6156}
6157
6158/*****************************************************************************
6159 *
6160 * driver setup and teardown
6161 *
6162 *****************************************************************************/
6163
e7392364
SG		 6164static void
6165il4965_bg_txpower_work(struct work_struct *work)
be663ab6 6166{
46bc8d4b 6167 struct il_priv *il = container_of(work, struct il_priv,
e7392364 6168 txpower_work);
be663ab6 6169
46bc8d4b 6170 mutex_lock(&il->mutex);
f325757a 6171
be663ab6 6172 /* If a scan happened to start before we got here
ebf0d90d 6173 * then just return; the stats notification will
be663ab6
WYG		 6174 * kick off another scheduled work to compensate for
6175 * any temperature delta we missed here. */
a6766ccd
SG		 6176 if (test_bit(S_EXIT_PENDING, &il->status) ||
6177 test_bit(S_SCANNING, &il->status))
f325757a 6178 goto out;
be663ab6
WYG		 6179
6180 /* Regardless of if we are associated, we must reconfigure the
6181 * TX power since frames can be sent on non-radar channels while
6182 * not associated */
1600b875 6183 il->ops->send_tx_power(il);
be663ab6
WYG		 6184
6185 /* Update last_temperature to keep is_calib_needed from running
6186 * when it isn't needed... */
46bc8d4b 6187 il->last_temperature = il->temperature;
f325757a 6188out:
46bc8d4b 6189 mutex_unlock(&il->mutex);
be663ab6
WYG		 6190}
6191
e7392364
SG		 6192static void
6193il4965_setup_deferred_work(struct il_priv *il)
be663ab6 6194{
46bc8d4b 6195 il->workqueue = create_singlethread_workqueue(DRV_NAME);
be663ab6 6196
46bc8d4b 6197 init_waitqueue_head(&il->wait_command_queue);
be663ab6 6198
46bc8d4b
SG		 6199 INIT_WORK(&il->restart, il4965_bg_restart);
6200 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6201 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6202 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6203 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
be663ab6 6204
46bc8d4b 6205 il_setup_scan_deferred_work(il);
be663ab6 6206
46bc8d4b 6207 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
be663ab6 6208
ebf0d90d
SG		 6209 init_timer(&il->stats_periodic);
6210 il->stats_periodic.data = (unsigned long)il;
6211 il->stats_periodic.function = il4965_bg_stats_periodic;
be663ab6 6212
46bc8d4b
SG		 6213 init_timer(&il->watchdog);
6214 il->watchdog.data = (unsigned long)il;
6215 il->watchdog.function = il_bg_watchdog;
be663ab6 6216
e7392364
SG		 6217 tasklet_init(&il->irq_tasklet,
6218 (void (*)(unsigned long))il4965_irq_tasklet,
6219 (unsigned long)il);
be663ab6
WYG		 6220}
6221
e7392364
SG		 6222static void
6223il4965_cancel_deferred_work(struct il_priv *il)
be663ab6 6224{
46bc8d4b
SG		 6225 cancel_work_sync(&il->txpower_work);
6226 cancel_delayed_work_sync(&il->init_alive_start);
6227 cancel_delayed_work(&il->alive_start);
6228 cancel_work_sync(&il->run_time_calib_work);
be663ab6 6229
46bc8d4b 6230 il_cancel_scan_deferred_work(il);
be663ab6 6231
ebf0d90d 6232 del_timer_sync(&il->stats_periodic);
be663ab6
WYG		 6233}
6234
e7392364
SG		 6235static void
6236il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
be663ab6
WYG		 6237{
6238 int i;
6239
2eb05816 6240 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
d2ddf621 6241 rates[i].bitrate = il_rates[i].ieee * 5;
e7392364 6242 rates[i].hw_value = i; /* Rate scaling will work on idxes */
be663ab6
WYG		 6243 rates[i].hw_value_short = i;
6244 rates[i].flags = 0;
e2ebc833 6245 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
be663ab6
WYG		 6246 /*
6247 * If CCK != 1M then set short preamble rate flag.
6248 */
6249 rates[i].flags |=
e7392364
SG		 6250 (il_rates[i].plcp ==
6251 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
be663ab6
WYG		 6252 }
6253 }
6254}
e7392364 6255
be663ab6 6256/*
46bc8d4b 6257 * Acquire il->lock before calling this function !
be663ab6 6258 */
e7392364
SG		 6259void
6260il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
be663ab6 6261{
e7392364 6262 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
0c2c8852 6263 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
be663ab6
WYG		 6264}
6265
e7392364
SG		 6266void
6267il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6268 int tx_fifo_id, int scd_retry)
be663ab6
WYG		 6269{
6270 int txq_id = txq->q.id;
6271
6272 /* Find out whether to activate Tx queue */
46bc8d4b 6273 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
be663ab6
WYG		 6274
6275 /* Set up and activate */
d3175167 6276 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 6277 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6278 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6279 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6280 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6281 IL49_SCD_QUEUE_STTS_REG_MSK);
be663ab6
WYG		 6282
6283 txq->sched_retry = scd_retry;
6284
e7392364
SG		 6285 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6286 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
be663ab6
WYG		 6287}
6288
c39ae9fd
SG		 6289const struct ieee80211_ops il4965_mac_ops = {
6290 .tx = il4965_mac_tx,
6291 .start = il4965_mac_start,
6292 .stop = il4965_mac_stop,
6293 .add_interface = il_mac_add_interface,
6294 .remove_interface = il_mac_remove_interface,
6295 .change_interface = il_mac_change_interface,
6296 .config = il_mac_config,
6297 .configure_filter = il4965_configure_filter,
6298 .set_key = il4965_mac_set_key,
6299 .update_tkip_key = il4965_mac_update_tkip_key,
6300 .conf_tx = il_mac_conf_tx,
6301 .reset_tsf = il_mac_reset_tsf,
6302 .bss_info_changed = il_mac_bss_info_changed,
6303 .ampdu_action = il4965_mac_ampdu_action,
6304 .hw_scan = il_mac_hw_scan,
6305 .sta_add = il4965_mac_sta_add,
6306 .sta_remove = il_mac_sta_remove,
6307 .channel_switch = il4965_mac_channel_switch,
6308 .tx_last_beacon = il_mac_tx_last_beacon,
6309};
6310
e7392364
SG		 6311static int
6312il4965_init_drv(struct il_priv *il)
be663ab6
WYG		 6313{
6314 int ret;
6315
46bc8d4b
SG		 6316 spin_lock_init(&il->sta_lock);
6317 spin_lock_init(&il->hcmd_lock);
be663ab6 6318
46bc8d4b 6319 INIT_LIST_HEAD(&il->free_frames);
be663ab6 6320
46bc8d4b 6321 mutex_init(&il->mutex);
be663ab6 6322
46bc8d4b
SG		 6323 il->ieee_channels = NULL;
6324 il->ieee_rates = NULL;
6325 il->band = IEEE80211_BAND_2GHZ;
be663ab6 6326
46bc8d4b
SG		 6327 il->iw_mode = NL80211_IFTYPE_STATION;
6328 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6329 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
be663ab6
WYG		 6330
6331 /* initialize force reset */
46bc8d4b 6332 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
be663ab6
WYG		 6333
6334 /* Choose which receivers/antennas to use */
c9363551
SG		 6335 if (il->ops->set_rxon_chain)
6336 il->ops->set_rxon_chain(il);
be663ab6 6337
46bc8d4b 6338 il_init_scan_params(il);
be663ab6 6339
46bc8d4b 6340 ret = il_init_channel_map(il);
be663ab6 6341 if (ret) {
9406f797 6342 IL_ERR("initializing regulatory failed: %d\n", ret);
be663ab6
WYG		 6343 goto err;
6344 }
6345
46bc8d4b 6346 ret = il_init_geos(il);
be663ab6 6347 if (ret) {
9406f797 6348 IL_ERR("initializing geos failed: %d\n", ret);
be663ab6
WYG		 6349 goto err_free_channel_map;
6350 }
46bc8d4b 6351 il4965_init_hw_rates(il, il->ieee_rates);
be663ab6
WYG		 6352
6353 return 0;
6354
6355err_free_channel_map:
46bc8d4b 6356 il_free_channel_map(il);
be663ab6
WYG		 6357err:
6358 return ret;
6359}
6360
e7392364
SG		 6361static void
6362il4965_uninit_drv(struct il_priv *il)
be663ab6 6363{
46bc8d4b
SG		 6364 il_free_geos(il);
6365 il_free_channel_map(il);
6366 kfree(il->scan_cmd);
be663ab6
WYG		 6367}
6368
e7392364
SG		 6369static void
6370il4965_hw_detect(struct il_priv *il)
be663ab6 6371{
841b2cca
SG		 6372 il->hw_rev = _il_rd(il, CSR_HW_REV);
6373 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
46bc8d4b 6374 il->rev_id = il->pci_dev->revision;
58de00a4 6375 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
be663ab6
WYG		 6376}
6377
1023f3bc
SG		 6378static struct il_sensitivity_ranges il4965_sensitivity = {
6379 .min_nrg_cck = 97,
6380 .max_nrg_cck = 0, /* not used, set to 0 */
6381
6382 .auto_corr_min_ofdm = 85,
6383 .auto_corr_min_ofdm_mrc = 170,
6384 .auto_corr_min_ofdm_x1 = 105,
6385 .auto_corr_min_ofdm_mrc_x1 = 220,
6386
6387 .auto_corr_max_ofdm = 120,
6388 .auto_corr_max_ofdm_mrc = 210,
6389 .auto_corr_max_ofdm_x1 = 140,
6390 .auto_corr_max_ofdm_mrc_x1 = 270,
6391
6392 .auto_corr_min_cck = 125,
6393 .auto_corr_max_cck = 200,
6394 .auto_corr_min_cck_mrc = 200,
6395 .auto_corr_max_cck_mrc = 400,
6396
6397 .nrg_th_cck = 100,
6398 .nrg_th_ofdm = 100,
6399
6400 .barker_corr_th_min = 190,
6401 .barker_corr_th_min_mrc = 390,
6402 .nrg_th_cca = 62,
6403};
6404
6405static void
e7392364 6406il4965_set_hw_params(struct il_priv *il)
be663ab6 6407{
b16db50a 6408 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
46bc8d4b
SG		 6409 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6410 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6411 if (il->cfg->mod_params->amsdu_size_8K)
6412 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
be663ab6 6413 else
46bc8d4b 6414 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
be663ab6 6415
46bc8d4b 6416 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
be663ab6 6417
46bc8d4b
SG		 6418 if (il->cfg->mod_params->disable_11n)
6419 il->cfg->sku &= ~IL_SKU_N;
be663ab6 6420
1023f3bc
SG		 6421 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6422 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6423 il->cfg->num_of_queues =
6424 il->cfg->mod_params->num_of_queues;
6425
6426 il->hw_params.max_txq_num = il->cfg->num_of_queues;
6427 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6428 il->hw_params.scd_bc_tbls_size =
6429 il->cfg->num_of_queues *
6430 sizeof(struct il4965_scd_bc_tbl);
6431
6432 il->hw_params.tfd_size = sizeof(struct il_tfd);
6433 il->hw_params.max_stations = IL4965_STATION_COUNT;
6434 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6435 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6436 il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6437 il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
6438
6439 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6440
6441 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6442 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6443 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6444 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6445
6446 il->hw_params.ct_kill_threshold =
6447 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6448
6449 il->hw_params.sens = &il4965_sensitivity;
6450 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
be663ab6
WYG		 6451}
6452
be663ab6 6453static int
e2ebc833 6454il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
be663ab6 6455{
7c2cde2e 6456 int err = 0;
46bc8d4b 6457 struct il_priv *il;
be663ab6 6458 struct ieee80211_hw *hw;
e2ebc833 6459 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
be663ab6
WYG		 6460 unsigned long flags;
6461 u16 pci_cmd;
6462
6463 /************************
6464 * 1. Allocating HW data
6465 ************************/
6466
c39ae9fd 6467 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
be663ab6
WYG		 6468 if (!hw) {
6469 err = -ENOMEM;
6470 goto out;
6471 }
46bc8d4b 6472 il = hw->priv;
c39ae9fd 6473 il->hw = hw;
be663ab6
WYG		 6474 SET_IEEE80211_DEV(hw, &pdev->dev);
6475
58de00a4 6476 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 6477 il->cfg = cfg;
c39ae9fd 6478 il->ops = &il4965_ops;
93b7654e
SG		 6479#ifdef CONFIG_IWLEGACY_DEBUGFS
6480 il->debugfs_ops = &il4965_debugfs_ops;
6481#endif
46bc8d4b
SG		 6482 il->pci_dev = pdev;
6483 il->inta_mask = CSR_INI_SET_MASK;
be663ab6 6484
be663ab6
WYG		 6485 /**************************
6486 * 2. Initializing PCI bus
6487 **************************/
e7392364
SG		 6488 pci_disable_link_state(pdev,
6489 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6490 PCIE_LINK_STATE_CLKPM);
be663ab6
WYG		 6491
6492 if (pci_enable_device(pdev)) {
6493 err = -ENODEV;
6494 goto out_ieee80211_free_hw;
6495 }
6496
6497 pci_set_master(pdev);
6498
6499 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6500 if (!err)
6501 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6502 if (err) {
6503 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6504 if (!err)
e7392364
SG		 6505 err =
6506 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
be663ab6
WYG		 6507 /* both attempts failed: */
6508 if (err) {
9406f797 6509 IL_WARN("No suitable DMA available.\n");
be663ab6
WYG		 6510 goto out_pci_disable_device;
6511 }
6512 }
6513
6514 err = pci_request_regions(pdev, DRV_NAME);
6515 if (err)
6516 goto out_pci_disable_device;
6517
46bc8d4b 6518 pci_set_drvdata(pdev, il);
be663ab6 6519
be663ab6
WYG		 6520 /***********************
6521 * 3. Read REV register
6522 ***********************/
a5f16137 6523 il->hw_base = pci_ioremap_bar(pdev, 0);
46bc8d4b 6524 if (!il->hw_base) {
be663ab6
WYG		 6525 err = -ENODEV;
6526 goto out_pci_release_regions;
6527 }
6528
58de00a4 6529 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 6530 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 6531 D_INFO("pci_resource_base = %p\n", il->hw_base);
be663ab6
WYG		 6532
6533 /* these spin locks will be used in apm_ops.init and EEPROM access
6534 * we should init now
6535 */
46bc8d4b
SG		 6536 spin_lock_init(&il->reg_lock);
6537 spin_lock_init(&il->lock);
be663ab6
WYG		 6538
6539 /*
6540 * stop and reset the on-board processor just in case it is in a
6541 * strange state ... like being left stranded by a primary kernel
6542 * and this is now the kdump kernel trying to start up
6543 */
841b2cca 6544 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6 6545
46bc8d4b 6546 il4965_hw_detect(il);
e7392364 6547 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
be663ab6
WYG		 6548
6549 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6550 * PCI Tx retries from interfering with C3 CPU state */
6551 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6552
46bc8d4b
SG		 6553 il4965_prepare_card_hw(il);
6554 if (!il->hw_ready) {
9406f797 6555 IL_WARN("Failed, HW not ready\n");
be663ab6
WYG		 6556 goto out_iounmap;
6557 }
6558
6559 /*****************
6560 * 4. Read EEPROM
6561 *****************/
6562 /* Read the EEPROM */
46bc8d4b 6563 err = il_eeprom_init(il);
be663ab6 6564 if (err) {
9406f797 6565 IL_ERR("Unable to init EEPROM\n");
be663ab6
WYG		 6566 goto out_iounmap;
6567 }
46bc8d4b 6568 err = il4965_eeprom_check_version(il);
be663ab6
WYG		 6569 if (err)
6570 goto out_free_eeprom;
6571
6572 if (err)
6573 goto out_free_eeprom;
6574
6575 /* extract MAC Address */
46bc8d4b 6576 il4965_eeprom_get_mac(il, il->addresses[0].addr);
58de00a4 6577 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
46bc8d4b
SG		 6578 il->hw->wiphy->addresses = il->addresses;
6579 il->hw->wiphy->n_addresses = 1;
be663ab6
WYG		 6580
6581 /************************
6582 * 5. Setup HW constants
6583 ************************/
1023f3bc 6584 il4965_set_hw_params(il);
be663ab6
WYG		 6585
6586 /*******************
46bc8d4b 6587 * 6. Setup il
be663ab6
WYG		 6588 *******************/
6589
46bc8d4b 6590 err = il4965_init_drv(il);
be663ab6
WYG		 6591 if (err)
6592 goto out_free_eeprom;
46bc8d4b 6593 /* At this point both hw and il are initialized. */
be663ab6
WYG		 6594
6595 /********************
6596 * 7. Setup services
6597 ********************/
46bc8d4b
SG		 6598 spin_lock_irqsave(&il->lock, flags);
6599 il_disable_interrupts(il);
6600 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6601
46bc8d4b 6602 pci_enable_msi(il->pci_dev);
be663ab6 6603
e7392364 6604 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
be663ab6 6605 if (err) {
9406f797 6606 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
be663ab6
WYG		 6607 goto out_disable_msi;
6608 }
6609
46bc8d4b 6610 il4965_setup_deferred_work(il);
d0c72347 6611 il4965_setup_handlers(il);
be663ab6
WYG		 6612
6613 /*********************************************
6614 * 8. Enable interrupts and read RFKILL state
6615 *********************************************/
6616
a078a1fd 6617 /* enable rfkill interrupt: hw bug w/a */
46bc8d4b 6618 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
be663ab6
WYG		 6619 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6620 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
46bc8d4b 6621 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
be663ab6
WYG		 6622 }
6623
46bc8d4b 6624 il_enable_rfkill_int(il);
be663ab6
WYG		 6625
6626 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 6627 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 6628 clear_bit(S_RFKILL, &il->status);
be663ab6 6629 else
bc269a8e 6630 set_bit(S_RFKILL, &il->status);
be663ab6 6631
46bc8d4b 6632 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 6633 test_bit(S_RFKILL, &il->status));
be663ab6 6634
46bc8d4b 6635 il_power_initialize(il);
be663ab6 6636
46bc8d4b 6637 init_completion(&il->_4965.firmware_loading_complete);
be663ab6 6638
46bc8d4b 6639 err = il4965_request_firmware(il, true);
be663ab6
WYG		 6640 if (err)
6641 goto out_destroy_workqueue;
6642
6643 return 0;
6644
e7392364 6645out_destroy_workqueue:
46bc8d4b
SG		 6646 destroy_workqueue(il->workqueue);
6647 il->workqueue = NULL;
6648 free_irq(il->pci_dev->irq, il);
e7392364 6649out_disable_msi:
46bc8d4b
SG		 6650 pci_disable_msi(il->pci_dev);
6651 il4965_uninit_drv(il);
e7392364 6652out_free_eeprom:
46bc8d4b 6653 il_eeprom_free(il);
e7392364 6654out_iounmap:
a5f16137 6655 iounmap(il->hw_base);
e7392364 6656out_pci_release_regions:
be663ab6
WYG		 6657 pci_set_drvdata(pdev, NULL);
6658 pci_release_regions(pdev);
e7392364 6659out_pci_disable_device:
be663ab6 6660 pci_disable_device(pdev);
e7392364 6661out_ieee80211_free_hw:
46bc8d4b 6662 ieee80211_free_hw(il->hw);
e7392364 6663out:
be663ab6
WYG		 6664 return err;
6665}
6666
e7392364
SG		 6667static void __devexit
6668il4965_pci_remove(struct pci_dev *pdev)
be663ab6 6669{
46bc8d4b 6670 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 6671 unsigned long flags;
6672
46bc8d4b 6673 if (!il)
be663ab6
WYG		 6674 return;
6675
46bc8d4b 6676 wait_for_completion(&il->_4965.firmware_loading_complete);
be663ab6 6677
58de00a4 6678 D_INFO("*** UNLOAD DRIVER ***\n");
be663ab6 6679
46bc8d4b 6680 il_dbgfs_unregister(il);
e2ebc833 6681 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
be663ab6 6682
e2ebc833
SG		 6683 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6684 * to be called and il4965_down since we are removing the device
a6766ccd 6685 * we need to set S_EXIT_PENDING bit.
be663ab6 6686 */
a6766ccd 6687 set_bit(S_EXIT_PENDING, &il->status);
be663ab6 6688
46bc8d4b 6689 il_leds_exit(il);
be663ab6 6690
46bc8d4b
SG		 6691 if (il->mac80211_registered) {
6692 ieee80211_unregister_hw(il->hw);
6693 il->mac80211_registered = 0;
be663ab6 6694 } else {
46bc8d4b 6695 il4965_down(il);
be663ab6
WYG		 6696 }
6697
6698 /*
6699 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG		 6700 * This may be redundant with il4965_down(), but there are paths to
6701 * run il4965_down() without calling apm_ops.stop(), and there are
6702 * paths to avoid running il4965_down() at all before leaving driver.
be663ab6
WYG		 6703 * This (inexpensive) call *makes sure* device is reset.
6704 */
46bc8d4b 6705 il_apm_stop(il);
be663ab6
WYG		 6706
6707 /* make sure we flush any pending irq or
6708 * tasklet for the driver
6709 */
46bc8d4b
SG		 6710 spin_lock_irqsave(&il->lock, flags);
6711 il_disable_interrupts(il);
6712 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6713
46bc8d4b 6714 il4965_synchronize_irq(il);
be663ab6 6715
46bc8d4b 6716 il4965_dealloc_ucode_pci(il);
be663ab6 6717
46bc8d4b
SG		 6718 if (il->rxq.bd)
6719 il4965_rx_queue_free(il, &il->rxq);
6720 il4965_hw_txq_ctx_free(il);
be663ab6 6721
46bc8d4b 6722 il_eeprom_free(il);
be663ab6 6723
be663ab6 6724 /*netif_stop_queue(dev); */
46bc8d4b 6725 flush_workqueue(il->workqueue);
be663ab6 6726
e2ebc833 6727 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
46bc8d4b 6728 * il->workqueue... so we can't take down the workqueue
be663ab6 6729 * until now... */
46bc8d4b
SG		 6730 destroy_workqueue(il->workqueue);
6731 il->workqueue = NULL;
be663ab6 6732
46bc8d4b
SG		 6733 free_irq(il->pci_dev->irq, il);
6734 pci_disable_msi(il->pci_dev);
a5f16137 6735 iounmap(il->hw_base);
be663ab6
WYG		 6736 pci_release_regions(pdev);
6737 pci_disable_device(pdev);
6738 pci_set_drvdata(pdev, NULL);
6739
46bc8d4b 6740 il4965_uninit_drv(il);
be663ab6 6741
46bc8d4b 6742 dev_kfree_skb(il->beacon_skb);
be663ab6 6743
46bc8d4b 6744 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6745}
6746
6747/*
6748 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
46bc8d4b 6749 * must be called under il->lock and mac access
be663ab6 6750 */
e7392364
SG		 6751void
6752il4965_txq_set_sched(struct il_priv *il, u32 mask)
be663ab6 6753{
d3175167 6754 il_wr_prph(il, IL49_SCD_TXFACT, mask);
be663ab6
WYG		 6755}
6756
6757/*****************************************************************************
6758 *
6759 * driver and module entry point
6760 *
6761 *****************************************************************************/
6762
6763/* Hardware specific file defines the PCI IDs table for that hardware module */
e2ebc833 6764static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
e2ebc833
SG		 6765 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6766 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
be663ab6
WYG		 6767 {0}
6768};
e2ebc833 6769MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
be663ab6 6770
e2ebc833 6771static struct pci_driver il4965_driver = {
be663ab6 6772 .name = DRV_NAME,
e2ebc833
SG		 6773 .id_table = il4965_hw_card_ids,
6774 .probe = il4965_pci_probe,
6775 .remove = __devexit_p(il4965_pci_remove),
6776 .driver.pm = IL_LEGACY_PM_OPS,
be663ab6
WYG		 6777};
6778
e7392364
SG		 6779static int __init
6780il4965_init(void)
be663ab6
WYG		 6781{
6782
6783 int ret;
6784 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6785 pr_info(DRV_COPYRIGHT "\n");
6786
e2ebc833 6787 ret = il4965_rate_control_register();
be663ab6
WYG		 6788 if (ret) {
6789 pr_err("Unable to register rate control algorithm: %d\n", ret);
6790 return ret;
6791 }
6792
e2ebc833 6793 ret = pci_register_driver(&il4965_driver);
be663ab6
WYG		 6794 if (ret) {
6795 pr_err("Unable to initialize PCI module\n");
6796 goto error_register;
6797 }
6798
6799 return ret;
6800
6801error_register:
e2ebc833 6802 il4965_rate_control_unregister();
be663ab6
WYG		 6803 return ret;
6804}
6805
e7392364
SG		 6806static void __exit
6807il4965_exit(void)
be663ab6 6808{
e2ebc833
SG		 6809 pci_unregister_driver(&il4965_driver);
6810 il4965_rate_control_unregister();
be663ab6
WYG		 6811}
6812
e2ebc833
SG		 6813module_exit(il4965_exit);
6814module_init(il4965_init);
be663ab6 6815
d3175167 6816#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 6817module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
be663ab6
WYG		 6818MODULE_PARM_DESC(debug, "debug output mask");
6819#endif
6820
e2ebc833 6821module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
be663ab6 6822MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
e2ebc833 6823module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
be663ab6 6824MODULE_PARM_DESC(queues_num, "number of hw queues.");
e2ebc833 6825module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
be663ab6 6826MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
e7392364
SG		 6827module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6828 S_IRUGO);
be663ab6 6829MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
e2ebc833 6830module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
be663ab6 6831MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
Linux kernel - Deliverables
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