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mac80211: allow channel switch with multiple channel contexts
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
be663ab6
WYG		 43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
98613be0 53#include "common.h"
af038f40 54#include "4965.h"
be663ab6 55
be663ab6
WYG		 56/******************************************************************************
57 *
58 * module boiler plate
59 *
60 ******************************************************************************/
61
62/*
63 * module name, copyright, version, etc.
64 */
65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
66
d3175167 67#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 68#define VD "d"
69#else
70#define VD
71#endif
72
73#define DRV_VERSION IWLWIFI_VERSION VD
74
be663ab6
WYG		 75MODULE_DESCRIPTION(DRV_DESCRIPTION);
76MODULE_VERSION(DRV_VERSION);
77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78MODULE_LICENSE("GPL");
79MODULE_ALIAS("iwl4965");
80
e7392364
SG		 81void
82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
fcb74588
SG		 83{
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
a6766ccd 86 if (!test_bit(S_EXIT_PENDING, &il->status))
fcb74588
SG		 87 queue_work(il->workqueue, &il->tx_flush);
88 }
89}
90
91/*
92 * EEPROM
93 */
94struct il_mod_params il4965_mod_params = {
fcb74588
SG		 95 .restart_fw = 1,
96 /* the rest are 0 by default */
97};
98
e7392364
SG		 99void
100il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 101{
102 unsigned long flags;
103 int i;
104 spin_lock_irqsave(&rxq->lock, flags);
105 INIT_LIST_HEAD(&rxq->rx_free);
106 INIT_LIST_HEAD(&rxq->rx_used);
107 /* Fill the rx_used queue with _all_ of the Rx buffers */
108 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
109 /* In the reset function, these buffers may have been allocated
110 * to an SKB, so we need to unmap and free potential storage */
111 if (rxq->pool[i].page != NULL) {
112 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 113 PAGE_SIZE << il->hw_params.rx_page_order,
114 PCI_DMA_FROMDEVICE);
fcb74588
SG		 115 __il_free_pages(il, rxq->pool[i].page);
116 rxq->pool[i].page = NULL;
117 }
118 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
119 }
120
121 for (i = 0; i < RX_QUEUE_SIZE; i++)
122 rxq->queue[i] = NULL;
123
124 /* Set us so that we have processed and used all buffers, but have
125 * not restocked the Rx queue with fresh buffers */
126 rxq->read = rxq->write = 0;
127 rxq->write_actual = 0;
128 rxq->free_count = 0;
129 spin_unlock_irqrestore(&rxq->lock, flags);
130}
131
e7392364
SG		 132int
133il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 134{
135 u32 rb_size;
e7392364 136 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
fcb74588
SG		 137 u32 rb_timeout = 0;
138
139 if (il->cfg->mod_params->amsdu_size_8K)
9a95b370 140 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
fcb74588 141 else
9a95b370 142 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
fcb74588
SG		 143
144 /* Stop Rx DMA */
9a95b370 145 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
fcb74588
SG		 146
147 /* Reset driver's Rx queue write idx */
9a95b370 148 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
fcb74588
SG		 149
150 /* Tell device where to find RBD circular buffer in DRAM */
e7392364 151 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
fcb74588
SG		 152
153 /* Tell device where in DRAM to update its Rx status */
e7392364 154 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
fcb74588
SG		 155
156 /* Enable Rx DMA
157 * Direct rx interrupts to hosts
158 * Rx buffer size 4 or 8k
159 * RB timeout 0x10
160 * 256 RBDs
161 */
9a95b370 162 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
e7392364
SG		 163 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
164 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
1722f8e1
SG		 165 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
166 rb_size |
167 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
168 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
fcb74588
SG		 169
170 /* Set interrupt coalescing timer to default (2048 usecs) */
171 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
172
173 return 0;
174}
175
e7392364
SG		 176static void
177il4965_set_pwr_vmain(struct il_priv *il)
fcb74588
SG		 178{
179/*
180 * (for documentation purposes)
181 * to set power to V_AUX, do:
182
183 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
184 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
185 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
186 ~APMG_PS_CTRL_MSK_PWR_SRC);
187 */
188
189 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
e7392364
SG		 190 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
191 ~APMG_PS_CTRL_MSK_PWR_SRC);
fcb74588
SG		 192}
193
e7392364
SG		 194int
195il4965_hw_nic_init(struct il_priv *il)
fcb74588
SG		 196{
197 unsigned long flags;
198 struct il_rx_queue *rxq = &il->rxq;
199 int ret;
200
fcb74588 201 spin_lock_irqsave(&il->lock, flags);
f03ee2a8 202 il_apm_init(il);
fcb74588
SG		 203 /* Set interrupt coalescing calibration timer to default (512 usecs) */
204 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
fcb74588
SG		 205 spin_unlock_irqrestore(&il->lock, flags);
206
207 il4965_set_pwr_vmain(il);
f03ee2a8 208 il4965_nic_config(il);
fcb74588
SG		 209
210 /* Allocate the RX queue, or reset if it is already allocated */
211 if (!rxq->bd) {
212 ret = il_rx_queue_alloc(il);
213 if (ret) {
214 IL_ERR("Unable to initialize Rx queue\n");
215 return -ENOMEM;
216 }
217 } else
218 il4965_rx_queue_reset(il, rxq);
219
220 il4965_rx_replenish(il);
221
222 il4965_rx_init(il, rxq);
223
224 spin_lock_irqsave(&il->lock, flags);
225
226 rxq->need_update = 1;
227 il_rx_queue_update_write_ptr(il, rxq);
228
229 spin_unlock_irqrestore(&il->lock, flags);
230
231 /* Allocate or reset and init all Tx and Command queues */
232 if (!il->txq) {
233 ret = il4965_txq_ctx_alloc(il);
234 if (ret)
235 return ret;
236 } else
237 il4965_txq_ctx_reset(il);
238
a6766ccd 239 set_bit(S_INIT, &il->status);
fcb74588
SG		 240
241 return 0;
242}
243
244/**
245 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
246 */
e7392364
SG		 247static inline __le32
248il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
fcb74588 249{
e7392364 250 return cpu_to_le32((u32) (dma_addr >> 8));
fcb74588
SG		 251}
252
253/**
254 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
255 *
256 * If there are slots in the RX queue that need to be restocked,
257 * and we have free pre-allocated buffers, fill the ranks as much
258 * as we can, pulling from rx_free.
259 *
260 * This moves the 'write' idx forward to catch up with 'processed', and
261 * also updates the memory address in the firmware to reference the new
262 * target buffer.
263 */
e7392364
SG		 264void
265il4965_rx_queue_restock(struct il_priv *il)
fcb74588
SG		 266{
267 struct il_rx_queue *rxq = &il->rxq;
268 struct list_head *element;
269 struct il_rx_buf *rxb;
270 unsigned long flags;
271
272 spin_lock_irqsave(&rxq->lock, flags);
273 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
274 /* The overwritten rxb must be a used one */
275 rxb = rxq->queue[rxq->write];
276 BUG_ON(rxb && rxb->page);
277
278 /* Get next free Rx buffer, remove from free list */
279 element = rxq->rx_free.next;
280 rxb = list_entry(element, struct il_rx_buf, list);
281 list_del(element);
282
283 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG		 284 rxq->bd[rxq->write] =
285 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
fcb74588
SG		 286 rxq->queue[rxq->write] = rxb;
287 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
288 rxq->free_count--;
289 }
290 spin_unlock_irqrestore(&rxq->lock, flags);
291 /* If the pre-allocated buffer pool is dropping low, schedule to
292 * refill it */
293 if (rxq->free_count <= RX_LOW_WATERMARK)
294 queue_work(il->workqueue, &il->rx_replenish);
295
fcb74588
SG		 296 /* If we've added more space for the firmware to place data, tell it.
297 * Increment device's write pointer in multiples of 8. */
298 if (rxq->write_actual != (rxq->write & ~0x7)) {
299 spin_lock_irqsave(&rxq->lock, flags);
300 rxq->need_update = 1;
301 spin_unlock_irqrestore(&rxq->lock, flags);
302 il_rx_queue_update_write_ptr(il, rxq);
303 }
304}
305
306/**
307 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
308 *
309 * When moving to rx_free an SKB is allocated for the slot.
310 *
311 * Also restock the Rx queue via il_rx_queue_restock.
312 * This is called as a scheduled work item (except for during initialization)
313 */
e7392364
SG		 314static void
315il4965_rx_allocate(struct il_priv *il, gfp_t priority)
fcb74588
SG		 316{
317 struct il_rx_queue *rxq = &il->rxq;
318 struct list_head *element;
319 struct il_rx_buf *rxb;
320 struct page *page;
96ebbe8d 321 dma_addr_t page_dma;
fcb74588
SG		 322 unsigned long flags;
323 gfp_t gfp_mask = priority;
324
325 while (1) {
326 spin_lock_irqsave(&rxq->lock, flags);
327 if (list_empty(&rxq->rx_used)) {
328 spin_unlock_irqrestore(&rxq->lock, flags);
329 return;
330 }
331 spin_unlock_irqrestore(&rxq->lock, flags);
332
333 if (rxq->free_count > RX_LOW_WATERMARK)
334 gfp_mask |= __GFP_NOWARN;
335
336 if (il->hw_params.rx_page_order > 0)
337 gfp_mask |= __GFP_COMP;
338
339 /* Alloc a new receive buffer */
340 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
341 if (!page) {
342 if (net_ratelimit())
e7392364
SG		 343 D_INFO("alloc_pages failed, " "order: %d\n",
344 il->hw_params.rx_page_order);
fcb74588
SG		 345
346 if (rxq->free_count <= RX_LOW_WATERMARK &&
347 net_ratelimit())
e7392364
SG		 348 IL_ERR("Failed to alloc_pages with %s. "
349 "Only %u free buffers remaining.\n",
350 priority ==
351 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
352 rxq->free_count);
fcb74588
SG		 353 /* We don't reschedule replenish work here -- we will
354 * call the restock method and if it still needs
355 * more buffers it will schedule replenish */
356 return;
357 }
358
96ebbe8d
SG		 359 /* Get physical address of the RB */
360 page_dma =
361 pci_map_page(il->pci_dev, page, 0,
362 PAGE_SIZE << il->hw_params.rx_page_order,
363 PCI_DMA_FROMDEVICE);
364 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
365 __free_pages(page, il->hw_params.rx_page_order);
366 break;
367 }
368
fcb74588
SG		 369 spin_lock_irqsave(&rxq->lock, flags);
370
371 if (list_empty(&rxq->rx_used)) {
372 spin_unlock_irqrestore(&rxq->lock, flags);
96ebbe8d
SG		 373 pci_unmap_page(il->pci_dev, page_dma,
374 PAGE_SIZE << il->hw_params.rx_page_order,
375 PCI_DMA_FROMDEVICE);
fcb74588
SG		 376 __free_pages(page, il->hw_params.rx_page_order);
377 return;
378 }
96ebbe8d 379
fcb74588
SG		 380 element = rxq->rx_used.next;
381 rxb = list_entry(element, struct il_rx_buf, list);
382 list_del(element);
383
fcb74588 384 BUG_ON(rxb->page);
fcb74588 385
96ebbe8d
SG		 386 rxb->page = page;
387 rxb->page_dma = page_dma;
fcb74588
SG		 388 list_add_tail(&rxb->list, &rxq->rx_free);
389 rxq->free_count++;
390 il->alloc_rxb_page++;
391
392 spin_unlock_irqrestore(&rxq->lock, flags);
393 }
394}
395
e7392364
SG		 396void
397il4965_rx_replenish(struct il_priv *il)
fcb74588
SG		 398{
399 unsigned long flags;
400
401 il4965_rx_allocate(il, GFP_KERNEL);
402
403 spin_lock_irqsave(&il->lock, flags);
404 il4965_rx_queue_restock(il);
405 spin_unlock_irqrestore(&il->lock, flags);
406}
407
e7392364
SG		 408void
409il4965_rx_replenish_now(struct il_priv *il)
fcb74588
SG		 410{
411 il4965_rx_allocate(il, GFP_ATOMIC);
412
413 il4965_rx_queue_restock(il);
414}
415
416/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
417 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
418 * This free routine walks the list of POOL entries and if SKB is set to
419 * non NULL it is unmapped and freed
420 */
e7392364
SG		 421void
422il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 423{
424 int i;
425 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
426 if (rxq->pool[i].page != NULL) {
427 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 428 PAGE_SIZE << il->hw_params.rx_page_order,
429 PCI_DMA_FROMDEVICE);
fcb74588
SG		 430 __il_free_pages(il, rxq->pool[i].page);
431 rxq->pool[i].page = NULL;
432 }
433 }
434
435 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
436 rxq->bd_dma);
437 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
438 rxq->rb_stts, rxq->rb_stts_dma);
439 rxq->bd = NULL;
e7392364 440 rxq->rb_stts = NULL;
fcb74588
SG		 441}
442
e7392364
SG		 443int
444il4965_rxq_stop(struct il_priv *il)
fcb74588 445{
775ed8ab 446 int ret;
fcb74588 447
775ed8ab
SG		 448 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
449 ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
450 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
451 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
452 1000);
453 if (ret < 0)
454 IL_ERR("Can't stop Rx DMA.\n");
fcb74588
SG		 455
456 return 0;
457}
458
e7392364
SG		 459int
460il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
fcb74588
SG		 461{
462 int idx = 0;
463 int band_offset = 0;
464
465 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
466 if (rate_n_flags & RATE_MCS_HT_MSK) {
467 idx = (rate_n_flags & 0xff);
468 return idx;
e7392364 469 /* Legacy rate format, search for match in table */
fcb74588
SG		 470 } else {
471 if (band == IEEE80211_BAND_5GHZ)
472 band_offset = IL_FIRST_OFDM_RATE;
473 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
474 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
475 return idx - band_offset;
476 }
477
478 return -1;
479}
480
e7392364
SG		 481static int
482il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
fcb74588
SG		 483{
484 /* data from PHY/DSP regarding signal strength, etc.,
485 * contents are always there, not configurable by host. */
486 struct il4965_rx_non_cfg_phy *ncphy =
487 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
e7392364
SG		 488 u32 agc =
489 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
490 IL49_AGC_DB_POS;
fcb74588
SG		 491
492 u32 valid_antennae =
493 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
e7392364 494 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
fcb74588
SG		 495 u8 max_rssi = 0;
496 u32 i;
497
498 /* Find max rssi among 3 possible receivers.
499 * These values are measured by the digital signal processor (DSP).
500 * They should stay fairly constant even as the signal strength varies,
501 * if the radio's automatic gain control (AGC) is working right.
502 * AGC value (see below) will provide the "interesting" info. */
503 for (i = 0; i < 3; i++)
504 if (valid_antennae & (1 << i))
505 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
506
507 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
508 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
509 max_rssi, agc);
510
511 /* dBm = max_rssi dB - agc dB - constant.
512 * Higher AGC (higher radio gain) means lower signal. */
513 return max_rssi - agc - IL4965_RSSI_OFFSET;
514}
515
e7392364
SG		 516static u32
517il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
fcb74588
SG		 518{
519 u32 decrypt_out = 0;
520
521 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
e7392364
SG		 522 RX_RES_STATUS_STATION_FOUND)
523 decrypt_out |=
524 (RX_RES_STATUS_STATION_FOUND |
525 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
fcb74588
SG		 526
527 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
528
529 /* packet was not encrypted */
530 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 531 RX_RES_STATUS_SEC_TYPE_NONE)
fcb74588
SG		 532 return decrypt_out;
533
534 /* packet was encrypted with unknown alg */
535 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 536 RX_RES_STATUS_SEC_TYPE_ERR)
fcb74588
SG		 537 return decrypt_out;
538
539 /* decryption was not done in HW */
540 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
e7392364 541 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
fcb74588
SG		 542 return decrypt_out;
543
544 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
545
546 case RX_RES_STATUS_SEC_TYPE_CCMP:
547 /* alg is CCM: check MIC only */
548 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
549 /* Bad MIC */
550 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
551 else
552 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
553
554 break;
555
556 case RX_RES_STATUS_SEC_TYPE_TKIP:
557 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
558 /* Bad TTAK */
559 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
560 break;
561 }
562 /* fall through if TTAK OK */
563 default:
564 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
565 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
566 else
567 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
568 break;
569 }
570
e7392364 571 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
fcb74588
SG		 572
573 return decrypt_out;
574}
575
c1de4a95
SG		 576#define SMALL_PACKET_SIZE 256
577
e7392364
SG		 578static void
579il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
c1de4a95 580 u32 len, u32 ampdu_status, struct il_rx_buf *rxb,
e7392364 581 struct ieee80211_rx_status *stats)
fcb74588
SG		 582{
583 struct sk_buff *skb;
584 __le16 fc = hdr->frame_control;
585
586 /* We only process data packets if the interface is open */
587 if (unlikely(!il->is_open)) {
e7392364 588 D_DROP("Dropping packet while interface is not open.\n");
fcb74588
SG		 589 return;
590 }
591
8cdbab7f
SG		 592 if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) {
593 il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
594 D_INFO("Woke queues - frame received on passive channel\n");
595 }
596
fcb74588
SG		 597 /* In case of HW accelerated crypto and bad decryption, drop */
598 if (!il->cfg->mod_params->sw_crypto &&
599 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
600 return;
601
c1de4a95 602 skb = dev_alloc_skb(SMALL_PACKET_SIZE);
fcb74588
SG		 603 if (!skb) {
604 IL_ERR("dev_alloc_skb failed\n");
605 return;
606 }
607
c1de4a95
SG		 608 if (len <= SMALL_PACKET_SIZE) {
609 memcpy(skb_put(skb, len), hdr, len);
610 } else {
611 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb),
612 len, PAGE_SIZE << il->hw_params.rx_page_order);
613 il->alloc_rxb_page--;
614 rxb->page = NULL;
615 }
fcb74588
SG		 616
617 il_update_stats(il, false, fc, len);
618 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
619
620 ieee80211_rx(il->hw, skb);
fcb74588
SG		 621}
622
4d69c752
SG		 623/* Called for N_RX (legacy ABG frames), or
624 * N_RX_MPDU (HT high-throughput N frames). */
60c46bf8 625static void
e7392364 626il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 627{
628 struct ieee80211_hdr *header;
d369167f 629 struct ieee80211_rx_status rx_status = {};
fcb74588
SG		 630 struct il_rx_pkt *pkt = rxb_addr(rxb);
631 struct il_rx_phy_res *phy_res;
632 __le32 rx_pkt_status;
633 struct il_rx_mpdu_res_start *amsdu;
634 u32 len;
635 u32 ampdu_status;
636 u32 rate_n_flags;
637
638 /**
4d69c752
SG		 639 * N_RX and N_RX_MPDU are handled differently.
640 * N_RX: physical layer info is in this buffer
641 * N_RX_MPDU: physical layer info was sent in separate
fcb74588
SG		 642 * command and cached in il->last_phy_res
643 *
644 * Here we set up local variables depending on which command is
645 * received.
646 */
4d69c752 647 if (pkt->hdr.cmd == N_RX) {
fcb74588 648 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
e7392364
SG		 649 header =
650 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
651 phy_res->cfg_phy_cnt);
fcb74588
SG		 652
653 len = le16_to_cpu(phy_res->byte_count);
e7392364
SG		 654 rx_pkt_status =
655 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
656 phy_res->cfg_phy_cnt + len);
fcb74588
SG		 657 ampdu_status = le32_to_cpu(rx_pkt_status);
658 } else {
659 if (!il->_4965.last_phy_res_valid) {
660 IL_ERR("MPDU frame without cached PHY data\n");
661 return;
662 }
663 phy_res = &il->_4965.last_phy_res;
664 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
665 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
666 len = le16_to_cpu(amsdu->byte_count);
e7392364
SG		 667 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
668 ampdu_status =
669 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
fcb74588
SG		 670 }
671
672 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
45eeeaf6 673 D_DROP("dsp size out of range [0,20]: %d\n",
e7392364 674 phy_res->cfg_phy_cnt);
fcb74588
SG		 675 return;
676 }
677
678 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
679 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e7392364 680 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
fcb74588
SG		 681 return;
682 }
683
684 /* This will be used in several places later */
685 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
686
687 /* rx_status carries information about the packet to mac80211 */
688 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
e7392364
SG		 689 rx_status.band =
690 (phy_res->
691 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
692 IEEE80211_BAND_5GHZ;
fcb74588 693 rx_status.freq =
e7392364
SG		 694 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
695 rx_status.band);
fcb74588 696 rx_status.rate_idx =
e7392364 697 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
fcb74588
SG		 698 rx_status.flag = 0;
699
700 /* TSF isn't reliable. In order to allow smooth user experience,
701 * this W/A doesn't propagate it to the mac80211 */
f4bda337 702 /*rx_status.flag |= RX_FLAG_MACTIME_START; */
fcb74588
SG		 703
704 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
705
706 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
707 rx_status.signal = il4965_calc_rssi(il, phy_res);
708
e7392364
SG		 709 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
710 (unsigned long long)rx_status.mactime);
fcb74588
SG		 711
712 /*
713 * "antenna number"
714 *
715 * It seems that the antenna field in the phy flags value
716 * is actually a bit field. This is undefined by radiotap,
717 * it wants an actual antenna number but I always get "7"
718 * for most legacy frames I receive indicating that the
719 * same frame was received on all three RX chains.
720 *
721 * I think this field should be removed in favor of a
722 * new 802.11n radiotap field "RX chains" that is defined
723 * as a bitmask.
724 */
725 rx_status.antenna =
e7392364
SG		 726 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
727 RX_RES_PHY_FLAGS_ANTENNA_POS;
fcb74588
SG		 728
729 /* set the preamble flag if appropriate */
730 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
731 rx_status.flag |= RX_FLAG_SHORTPRE;
732
733 /* Set up the HT phy flags */
734 if (rate_n_flags & RATE_MCS_HT_MSK)
735 rx_status.flag |= RX_FLAG_HT;
736 if (rate_n_flags & RATE_MCS_HT40_MSK)
737 rx_status.flag |= RX_FLAG_40MHZ;
738 if (rate_n_flags & RATE_MCS_SGI_MSK)
739 rx_status.flag |= RX_FLAG_SHORT_GI;
740
0255beda
CL		 741 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) {
742 /* We know which subframes of an A-MPDU belong
743 * together since we get a single PHY response
744 * from the firmware for all of them.
745 */
746
747 rx_status.flag |= RX_FLAG_AMPDU_DETAILS;
748 rx_status.ampdu_reference = il->_4965.ampdu_ref;
749 }
750
e7392364
SG		 751 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
752 &rx_status);
fcb74588
SG		 753}
754
4d69c752 755/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
6e9848b4 756 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
60c46bf8 757static void
e7392364 758il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 759{
760 struct il_rx_pkt *pkt = rxb_addr(rxb);
761 il->_4965.last_phy_res_valid = true;
0255beda 762 il->_4965.ampdu_ref++;
fcb74588
SG		 763 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
764 sizeof(struct il_rx_phy_res));
765}
766
e7392364
SG		 767static int
768il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
769 enum ieee80211_band band, u8 is_active,
770 u8 n_probes, struct il_scan_channel *scan_ch)
fcb74588
SG		 771{
772 struct ieee80211_channel *chan;
773 const struct ieee80211_supported_band *sband;
774 const struct il_channel_info *ch_info;
775 u16 passive_dwell = 0;
776 u16 active_dwell = 0;
777 int added, i;
778 u16 channel;
779
780 sband = il_get_hw_mode(il, band);
781 if (!sband)
782 return 0;
783
784 active_dwell = il_get_active_dwell_time(il, band, n_probes);
785 passive_dwell = il_get_passive_dwell_time(il, band, vif);
786
787 if (passive_dwell <= active_dwell)
788 passive_dwell = active_dwell + 1;
789
790 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
791 chan = il->scan_request->channels[i];
792
793 if (chan->band != band)
794 continue;
795
796 channel = chan->hw_value;
797 scan_ch->channel = cpu_to_le16(channel);
798
799 ch_info = il_get_channel_info(il, band, channel);
800 if (!il_is_channel_valid(ch_info)) {
e7392364
SG		 801 D_SCAN("Channel %d is INVALID for this band.\n",
802 channel);
fcb74588
SG		 803 continue;
804 }
805
806 if (!is_active || il_is_channel_passive(ch_info) ||
8fe02e16 807 (chan->flags & IEEE80211_CHAN_NO_IR))
fcb74588
SG		 808 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
809 else
810 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
811
812 if (n_probes)
813 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
814
815 scan_ch->active_dwell = cpu_to_le16(active_dwell);
816 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
817
818 /* Set txpower levels to defaults */
819 scan_ch->dsp_atten = 110;
820
821 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
822 * power level:
823 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
824 */
825 if (band == IEEE80211_BAND_5GHZ)
826 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
827 else
828 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
829
e7392364
SG		 830 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
831 le32_to_cpu(scan_ch->type),
832 (scan_ch->
833 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
834 (scan_ch->
835 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
836 passive_dwell);
fcb74588
SG		 837
838 scan_ch++;
839 added++;
840 }
841
842 D_SCAN("total channels to scan %d\n", added);
843 return added;
844}
845
a0c1ef3b
SG		 846static void
847il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
848{
849 int i;
850 u8 ind = *ant;
851
852 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
853 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
854 if (valid & BIT(ind)) {
855 *ant = ind;
856 return;
857 }
858 }
859}
860
e7392364
SG		 861int
862il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
fcb74588
SG		 863{
864 struct il_host_cmd cmd = {
4d69c752 865 .id = C_SCAN,
fcb74588
SG		 866 .len = sizeof(struct il_scan_cmd),
867 .flags = CMD_SIZE_HUGE,
868 };
869 struct il_scan_cmd *scan;
fcb74588
SG		 870 u32 rate_flags = 0;
871 u16 cmd_len;
872 u16 rx_chain = 0;
873 enum ieee80211_band band;
874 u8 n_probes = 0;
875 u8 rx_ant = il->hw_params.valid_rx_ant;
876 u8 rate;
877 bool is_active = false;
e7392364 878 int chan_mod;
fcb74588
SG		 879 u8 active_chains;
880 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
881 int ret;
882
883 lockdep_assert_held(&il->mutex);
884
fcb74588 885 if (!il->scan_cmd) {
e7392364
SG		 886 il->scan_cmd =
887 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
888 GFP_KERNEL);
fcb74588 889 if (!il->scan_cmd) {
e7392364 890 D_SCAN("fail to allocate memory for scan\n");
fcb74588
SG		 891 return -ENOMEM;
892 }
893 }
894 scan = il->scan_cmd;
895 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
896
897 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
898 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
899
900 if (il_is_any_associated(il)) {
901 u16 interval;
902 u32 extra;
903 u32 suspend_time = 100;
904 u32 scan_suspend_time = 100;
905
906 D_INFO("Scanning while associated...\n");
907 interval = vif->bss_conf.beacon_int;
908
909 scan->suspend_time = 0;
910 scan->max_out_time = cpu_to_le32(200 * 1024);
911 if (!interval)
912 interval = suspend_time;
913
914 extra = (suspend_time / interval) << 22;
e7392364
SG		 915 scan_suspend_time =
916 (extra | ((suspend_time % interval) * 1024));
fcb74588
SG		 917 scan->suspend_time = cpu_to_le32(scan_suspend_time);
918 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 919 scan_suspend_time, interval);
fcb74588
SG		 920 }
921
922 if (il->scan_request->n_ssids) {
923 int i, p = 0;
924 D_SCAN("Kicking off active scan\n");
925 for (i = 0; i < il->scan_request->n_ssids; i++) {
926 /* always does wildcard anyway */
927 if (!il->scan_request->ssids[i].ssid_len)
928 continue;
929 scan->direct_scan[p].id = WLAN_EID_SSID;
930 scan->direct_scan[p].len =
e7392364 931 il->scan_request->ssids[i].ssid_len;
fcb74588
SG		 932 memcpy(scan->direct_scan[p].ssid,
933 il->scan_request->ssids[i].ssid,
934 il->scan_request->ssids[i].ssid_len);
935 n_probes++;
936 p++;
937 }
938 is_active = true;
939 } else
940 D_SCAN("Start passive scan.\n");
941
942 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 943 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
fcb74588
SG		 944 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
945
946 switch (il->scan_band) {
947 case IEEE80211_BAND_2GHZ:
948 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
e7392364 949 chan_mod =
c8b03958 950 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
e7392364 951 RXON_FLG_CHANNEL_MODE_POS;
fcb74588
SG		 952 if (chan_mod == CHANNEL_MODE_PURE_40) {
953 rate = RATE_6M_PLCP;
954 } else {
955 rate = RATE_1M_PLCP;
956 rate_flags = RATE_MCS_CCK_MSK;
957 }
958 break;
959 case IEEE80211_BAND_5GHZ:
960 rate = RATE_6M_PLCP;
961 break;
962 default:
963 IL_WARN("Invalid scan band\n");
964 return -EIO;
965 }
966
967 /*
968 * If active scanning is requested but a certain channel is
969 * marked passive, we can do active scanning if we detect
970 * transmissions.
971 *
972 * There is an issue with some firmware versions that triggers
973 * a sysassert on a "good CRC threshold" of zero (== disabled),
974 * on a radar channel even though this means that we should NOT
975 * send probes.
976 *
977 * The "good CRC threshold" is the number of frames that we
978 * need to receive during our dwell time on a channel before
979 * sending out probes -- setting this to a huge value will
980 * mean we never reach it, but at the same time work around
981 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
982 * here instead of IL_GOOD_CRC_TH_DISABLED.
983 */
e7392364
SG		 984 scan->good_CRC_th =
985 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
fcb74588
SG		 986
987 band = il->scan_band;
988
989 if (il->cfg->scan_rx_antennas[band])
990 rx_ant = il->cfg->scan_rx_antennas[band];
991
a0c1ef3b 992 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
616107ed
SG		 993 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
994 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
fcb74588
SG		 995
996 /* In power save mode use one chain, otherwise use all chains */
a6766ccd 997 if (test_bit(S_POWER_PMI, &il->status)) {
fcb74588 998 /* rx_ant has been set to all valid chains previously */
e7392364
SG		 999 active_chains =
1000 rx_ant & ((u8) (il->chain_noise_data.active_chains));
fcb74588
SG		 1001 if (!active_chains)
1002 active_chains = rx_ant;
1003
1004 D_SCAN("chain_noise_data.active_chains: %u\n",
e7392364 1005 il->chain_noise_data.active_chains);
fcb74588
SG		 1006
1007 rx_ant = il4965_first_antenna(active_chains);
1008 }
1009
1010 /* MIMO is not used here, but value is required */
1011 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1012 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1013 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1014 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1015 scan->rx_chain = cpu_to_le16(rx_chain);
1016
e7392364
SG		 1017 cmd_len =
1018 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
1019 vif->addr, il->scan_request->ie,
1020 il->scan_request->ie_len,
1021 IL_MAX_SCAN_SIZE - sizeof(*scan));
fcb74588
SG		 1022 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1023
e7392364
SG		 1024 scan->filter_flags |=
1025 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
fcb74588 1026
e7392364
SG		 1027 scan->channel_count =
1028 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1029 (void *)&scan->data[cmd_len]);
fcb74588
SG		 1030 if (scan->channel_count == 0) {
1031 D_SCAN("channel count %d\n", scan->channel_count);
1032 return -EIO;
1033 }
1034
e7392364
SG		 1035 cmd.len +=
1036 le16_to_cpu(scan->tx_cmd.len) +
fcb74588
SG		 1037 scan->channel_count * sizeof(struct il_scan_channel);
1038 cmd.data = scan;
1039 scan->len = cpu_to_le16(cmd.len);
1040
a6766ccd 1041 set_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1042
1043 ret = il_send_cmd_sync(il, &cmd);
1044 if (ret)
a6766ccd 1045 clear_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1046
1047 return ret;
1048}
1049
e7392364
SG		 1050int
1051il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1052 bool add)
fcb74588
SG		 1053{
1054 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1055
1056 if (add)
83007196 1057 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
fcb74588
SG		 1058 &vif_priv->ibss_bssid_sta_id);
1059 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
e7392364 1060 vif->bss_conf.bssid);
fcb74588
SG		 1061}
1062
e7392364
SG		 1063void
1064il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
fcb74588
SG		 1065{
1066 lockdep_assert_held(&il->sta_lock);
1067
1068 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1069 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1070 else {
1071 D_TX("free more than tfds_in_queue (%u:%d)\n",
e7392364 1072 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
fcb74588
SG		 1073 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1074 }
1075}
1076
1077#define IL_TX_QUEUE_MSK 0xfffff
1078
e7392364
SG		 1079static bool
1080il4965_is_single_rx_stream(struct il_priv *il)
fcb74588
SG		 1081{
1082 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
e7392364 1083 il->current_ht_config.single_chain_sufficient;
fcb74588
SG		 1084}
1085
1086#define IL_NUM_RX_CHAINS_MULTIPLE 3
1087#define IL_NUM_RX_CHAINS_SINGLE 2
1088#define IL_NUM_IDLE_CHAINS_DUAL 2
1089#define IL_NUM_IDLE_CHAINS_SINGLE 1
1090
1091/*
1092 * Determine how many receiver/antenna chains to use.
1093 *
1094 * More provides better reception via diversity. Fewer saves power
1095 * at the expense of throughput, but only when not in powersave to
1096 * start with.
1097 *
1098 * MIMO (dual stream) requires at least 2, but works better with 3.
1099 * This does not determine *which* chains to use, just how many.
1100 */
e7392364
SG		 1101static int
1102il4965_get_active_rx_chain_count(struct il_priv *il)
fcb74588
SG		 1103{
1104 /* # of Rx chains to use when expecting MIMO. */
1105 if (il4965_is_single_rx_stream(il))
1106 return IL_NUM_RX_CHAINS_SINGLE;
1107 else
1108 return IL_NUM_RX_CHAINS_MULTIPLE;
1109}
1110
1111/*
1112 * When we are in power saving mode, unless device support spatial
1113 * multiplexing power save, use the active count for rx chain count.
1114 */
1115static int
1116il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1117{
1118 /* # Rx chains when idling, depending on SMPS mode */
1119 switch (il->current_ht_config.smps) {
1120 case IEEE80211_SMPS_STATIC:
1121 case IEEE80211_SMPS_DYNAMIC:
1122 return IL_NUM_IDLE_CHAINS_SINGLE;
1123 case IEEE80211_SMPS_OFF:
1124 return active_cnt;
1125 default:
e7392364 1126 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
fcb74588
SG		 1127 return active_cnt;
1128 }
1129}
1130
1131/* up to 4 chains */
e7392364
SG		 1132static u8
1133il4965_count_chain_bitmap(u32 chain_bitmap)
fcb74588
SG		 1134{
1135 u8 res;
1136 res = (chain_bitmap & BIT(0)) >> 0;
1137 res += (chain_bitmap & BIT(1)) >> 1;
1138 res += (chain_bitmap & BIT(2)) >> 2;
1139 res += (chain_bitmap & BIT(3)) >> 3;
1140 return res;
1141}
1142
1143/**
1144 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1145 *
1146 * Selects how many and which Rx receivers/antennas/chains to use.
1147 * This should not be used for scan command ... it puts data in wrong place.
1148 */
e7392364 1149void
83007196 1150il4965_set_rxon_chain(struct il_priv *il)
fcb74588
SG		 1151{
1152 bool is_single = il4965_is_single_rx_stream(il);
a6766ccd 1153 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
fcb74588
SG		 1154 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1155 u32 active_chains;
1156 u16 rx_chain;
1157
1158 /* Tell uCode which antennas are actually connected.
1159 * Before first association, we assume all antennas are connected.
1160 * Just after first association, il4965_chain_noise_calibration()
1161 * checks which antennas actually *are* connected. */
1162 if (il->chain_noise_data.active_chains)
1163 active_chains = il->chain_noise_data.active_chains;
1164 else
1165 active_chains = il->hw_params.valid_rx_ant;
1166
1167 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1168
1169 /* How many receivers should we use? */
1170 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1171 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1172
fcb74588
SG		 1173 /* correct rx chain count according hw settings
1174 * and chain noise calibration
1175 */
1176 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1177 if (valid_rx_cnt < active_rx_cnt)
1178 active_rx_cnt = valid_rx_cnt;
1179
1180 if (valid_rx_cnt < idle_rx_cnt)
1181 idle_rx_cnt = valid_rx_cnt;
1182
1183 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
e7392364 1184 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
fcb74588 1185
c8b03958 1186 il->staging.rx_chain = cpu_to_le16(rx_chain);
fcb74588
SG		 1187
1188 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
c8b03958 1189 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1190 else
c8b03958 1191 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1192
c8b03958 1193 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
e7392364 1194 active_rx_cnt, idle_rx_cnt);
fcb74588
SG		 1195
1196 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1197 active_rx_cnt < idle_rx_cnt);
1198}
1199
e7392364
SG		 1200static const char *
1201il4965_get_fh_string(int cmd)
fcb74588
SG		 1202{
1203 switch (cmd) {
e7392364
SG		 1204 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1205 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1206 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1207 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1208 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1209 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1210 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1211 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1212 IL_CMD(FH49_TSSR_TX_ERROR_REG);
fcb74588
SG		 1213 default:
1214 return "UNKNOWN";
1215 }
1216}
1217
e7392364
SG		 1218int
1219il4965_dump_fh(struct il_priv *il, char **buf, bool display)
fcb74588
SG		 1220{
1221 int i;
1222#ifdef CONFIG_IWLEGACY_DEBUG
1223 int pos = 0;
1224 size_t bufsz = 0;
1225#endif
1226 static const u32 fh_tbl[] = {
9a95b370
SG		 1227 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1228 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1229 FH49_RSCSR_CHNL0_WPTR,
1230 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1231 FH49_MEM_RSSR_SHARED_CTRL_REG,
1232 FH49_MEM_RSSR_RX_STATUS_REG,
1233 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1234 FH49_TSSR_TX_STATUS_REG,
1235 FH49_TSSR_TX_ERROR_REG
fcb74588
SG		 1236 };
1237#ifdef CONFIG_IWLEGACY_DEBUG
1238 if (display) {
1239 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1240 *buf = kmalloc(bufsz, GFP_KERNEL);
1241 if (!*buf)
1242 return -ENOMEM;
e7392364
SG		 1243 pos +=
1244 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
fcb74588 1245 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
e7392364
SG		 1246 pos +=
1247 scnprintf(*buf + pos, bufsz - pos,
1248 " %34s: 0X%08x\n",
1722f8e1
SG		 1249 il4965_get_fh_string(fh_tbl[i]),
1250 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1251 }
1252 return pos;
1253 }
1254#endif
1255 IL_ERR("FH register values:\n");
e7392364
SG		 1256 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1257 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1258 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1259 }
1260 return 0;
1261}
a1751b22 1262
60c46bf8 1263static void
e7392364 1264il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1265{
1266 struct il_rx_pkt *pkt = rxb_addr(rxb);
1267 struct il_missed_beacon_notif *missed_beacon;
1268
1269 missed_beacon = &pkt->u.missed_beacon;
1270 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1271 il->missed_beacon_threshold) {
e7392364
SG		 1272 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1273 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1274 le32_to_cpu(missed_beacon->total_missed_becons),
1275 le32_to_cpu(missed_beacon->num_recvd_beacons),
1276 le32_to_cpu(missed_beacon->num_expected_beacons));
a6766ccd 1277 if (!test_bit(S_SCANNING, &il->status))
a1751b22
SG		 1278 il4965_init_sensitivity(il);
1279 }
1280}
1281
1282/* Calculate noise level, based on measurements during network silence just
1283 * before arriving beacon. This measurement can be done only if we know
1284 * exactly when to expect beacons, therefore only when we're associated. */
e7392364
SG		 1285static void
1286il4965_rx_calc_noise(struct il_priv *il)
a1751b22
SG		 1287{
1288 struct stats_rx_non_phy *rx_info;
1289 int num_active_rx = 0;
1290 int total_silence = 0;
1291 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1292 int last_rx_noise;
1293
1294 rx_info = &(il->_4965.stats.rx.general);
1295 bcn_silence_a =
e7392364 1296 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
a1751b22 1297 bcn_silence_b =
e7392364 1298 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
a1751b22 1299 bcn_silence_c =
e7392364 1300 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
a1751b22
SG		 1301
1302 if (bcn_silence_a) {
1303 total_silence += bcn_silence_a;
1304 num_active_rx++;
1305 }
1306 if (bcn_silence_b) {
1307 total_silence += bcn_silence_b;
1308 num_active_rx++;
1309 }
1310 if (bcn_silence_c) {
1311 total_silence += bcn_silence_c;
1312 num_active_rx++;
1313 }
1314
1315 /* Average among active antennas */
1316 if (num_active_rx)
1317 last_rx_noise = (total_silence / num_active_rx) - 107;
1318 else
1319 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1320
e7392364
SG		 1321 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1322 bcn_silence_b, bcn_silence_c, last_rx_noise);
a1751b22
SG		 1323}
1324
1325#ifdef CONFIG_IWLEGACY_DEBUGFS
1326/*
1327 * based on the assumption of all stats counter are in DWORD
1328 * FIXME: This function is for debugging, do not deal with
1329 * the case of counters roll-over.
1330 */
e7392364
SG		 1331static void
1332il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
a1751b22
SG		 1333{
1334 int i, size;
1335 __le32 *prev_stats;
1336 u32 *accum_stats;
1337 u32 *delta, *max_delta;
1338 struct stats_general_common *general, *accum_general;
1339 struct stats_tx *tx, *accum_tx;
1340
1722f8e1
SG		 1341 prev_stats = (__le32 *) &il->_4965.stats;
1342 accum_stats = (u32 *) &il->_4965.accum_stats;
a1751b22
SG		 1343 size = sizeof(struct il_notif_stats);
1344 general = &il->_4965.stats.general.common;
1345 accum_general = &il->_4965.accum_stats.general.common;
1346 tx = &il->_4965.stats.tx;
1347 accum_tx = &il->_4965.accum_stats.tx;
1722f8e1
SG		 1348 delta = (u32 *) &il->_4965.delta_stats;
1349 max_delta = (u32 *) &il->_4965.max_delta;
a1751b22
SG		 1350
1351 for (i = sizeof(__le32); i < size;
e7392364
SG		 1352 i +=
1353 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1354 accum_stats++) {
a1751b22 1355 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
e7392364
SG		 1356 *delta =
1357 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
a1751b22
SG		 1358 *accum_stats += *delta;
1359 if (*delta > *max_delta)
1360 *max_delta = *delta;
1361 }
1362 }
1363
1364 /* reset accumulative stats for "no-counter" type stats */
1365 accum_general->temperature = general->temperature;
1366 accum_general->ttl_timestamp = general->ttl_timestamp;
1367}
1368#endif
1369
60c46bf8 1370static void
e7392364 1371il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22 1372{
527901d0
SG		 1373 const int recalib_seconds = 60;
1374 bool change;
a1751b22
SG		 1375 struct il_rx_pkt *pkt = rxb_addr(rxb);
1376
e7392364
SG		 1377 D_RX("Statistics notification received (%d vs %d).\n",
1378 (int)sizeof(struct il_notif_stats),
1379 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1380
1381 change =
1382 ((il->_4965.stats.general.common.temperature !=
1383 pkt->u.stats.general.common.temperature) ||
1384 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1385 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
a1751b22 1386#ifdef CONFIG_IWLEGACY_DEBUGFS
1722f8e1 1387 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
a1751b22
SG		 1388#endif
1389
1390 /* TODO: reading some of stats is unneeded */
e7392364 1391 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
a1751b22 1392
db7746f7 1393 set_bit(S_STATS, &il->status);
a1751b22 1394
527901d0
SG		 1395 /*
1396 * Reschedule the stats timer to occur in recalib_seconds to ensure
1397 * we get a thermal update even if the uCode doesn't give us one
1398 */
e7392364 1399 mod_timer(&il->stats_periodic,
527901d0 1400 jiffies + msecs_to_jiffies(recalib_seconds * 1000));
a1751b22 1401
a6766ccd 1402 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
4d69c752 1403 (pkt->hdr.cmd == N_STATS)) {
a1751b22
SG		 1404 il4965_rx_calc_noise(il);
1405 queue_work(il->workqueue, &il->run_time_calib_work);
1406 }
527901d0
SG		 1407
1408 if (change)
1409 il4965_temperature_calib(il);
a1751b22
SG		 1410}
1411
60c46bf8 1412static void
e7392364 1413il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1414{
1415 struct il_rx_pkt *pkt = rxb_addr(rxb);
1416
db7746f7 1417 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
a1751b22
SG		 1418#ifdef CONFIG_IWLEGACY_DEBUGFS
1419 memset(&il->_4965.accum_stats, 0,
e7392364 1420 sizeof(struct il_notif_stats));
a1751b22 1421 memset(&il->_4965.delta_stats, 0,
e7392364
SG		 1422 sizeof(struct il_notif_stats));
1423 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
a1751b22
SG		 1424#endif
1425 D_RX("Statistics have been cleared\n");
1426 }
d2dfb33e 1427 il4965_hdl_stats(il, rxb);
a1751b22
SG		 1428}
1429
8f29b456
SG		 1430
1431/*
1432 * mac80211 queues, ACs, hardware queues, FIFOs.
1433 *
1434 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1435 *
1436 * Mac80211 uses the following numbers, which we get as from it
1437 * by way of skb_get_queue_mapping(skb):
1438 *
1439 * VO 0
1440 * VI 1
1441 * BE 2
1442 * BK 3
1443 *
1444 *
1445 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1446 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1447 * own queue per aggregation session (RA/TID combination), such queues are
1448 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1449 * order to map frames to the right queue, we also need an AC->hw queue
1450 * mapping. This is implemented here.
1451 *
1452 * Due to the way hw queues are set up (by the hw specific modules like
af038f40 1453 * 4965.c), the AC->hw queue mapping is the identity
8f29b456
SG		 1454 * mapping.
1455 */
1456
a1751b22
SG		 1457static const u8 tid_to_ac[] = {
1458 IEEE80211_AC_BE,
1459 IEEE80211_AC_BK,
1460 IEEE80211_AC_BK,
1461 IEEE80211_AC_BE,
1462 IEEE80211_AC_VI,
1463 IEEE80211_AC_VI,
1464 IEEE80211_AC_VO,
1465 IEEE80211_AC_VO
1466};
1467
e7392364
SG		 1468static inline int
1469il4965_get_ac_from_tid(u16 tid)
a1751b22
SG		 1470{
1471 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1472 return tid_to_ac[tid];
1473
1474 /* no support for TIDs 8-15 yet */
1475 return -EINVAL;
1476}
1477
1478static inline int
83007196 1479il4965_get_fifo_from_tid(u16 tid)
a1751b22 1480{
b75b3a70
SG		 1481 const u8 ac_to_fifo[] = {
1482 IL_TX_FIFO_VO,
1483 IL_TX_FIFO_VI,
1484 IL_TX_FIFO_BE,
1485 IL_TX_FIFO_BK,
1486 };
1487
a1751b22 1488 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
b75b3a70 1489 return ac_to_fifo[tid_to_ac[tid]];
a1751b22
SG		 1490
1491 /* no support for TIDs 8-15 yet */
1492 return -EINVAL;
1493}
1494
1495/*
4d69c752 1496 * handle build C_TX command notification.
a1751b22 1497 */
e7392364
SG		 1498static void
1499il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1500 struct il_tx_cmd *tx_cmd,
1501 struct ieee80211_tx_info *info,
1502 struct ieee80211_hdr *hdr, u8 std_id)
a1751b22
SG		 1503{
1504 __le16 fc = hdr->frame_control;
1505 __le32 tx_flags = tx_cmd->tx_flags;
1506
1507 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1508 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1509 tx_flags |= TX_CMD_FLG_ACK_MSK;
1510 if (ieee80211_is_mgmt(fc))
1511 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1512 if (ieee80211_is_probe_resp(fc) &&
1513 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1514 tx_flags |= TX_CMD_FLG_TSF_MSK;
1515 } else {
1516 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1517 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1518 }
1519
1520 if (ieee80211_is_back_req(fc))
1521 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1522
1523 tx_cmd->sta_id = std_id;
1524 if (ieee80211_has_morefrags(fc))
1525 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1526
1527 if (ieee80211_is_data_qos(fc)) {
1528 u8 *qc = ieee80211_get_qos_ctl(hdr);
1529 tx_cmd->tid_tspec = qc[0] & 0xf;
1530 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1531 } else {
1532 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1533 }
1534
1535 il_tx_cmd_protection(il, info, fc, &tx_flags);
1536
1537 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1538 if (ieee80211_is_mgmt(fc)) {
1539 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1540 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1541 else
1542 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1543 } else {
1544 tx_cmd->timeout.pm_frame_timeout = 0;
1545 }
1546
1547 tx_cmd->driver_txop = 0;
1548 tx_cmd->tx_flags = tx_flags;
1549 tx_cmd->next_frame_len = 0;
1550}
1551
e7392364 1552static void
36323f81
TH		 1553il4965_tx_cmd_build_rate(struct il_priv *il,
1554 struct il_tx_cmd *tx_cmd,
1555 struct ieee80211_tx_info *info,
1556 struct ieee80211_sta *sta,
1557 __le16 fc)
a1751b22 1558{
616107ed 1559 const u8 rts_retry_limit = 60;
a1751b22
SG		 1560 u32 rate_flags;
1561 int rate_idx;
a1751b22
SG		 1562 u8 data_retry_limit;
1563 u8 rate_plcp;
1564
e7392364 1565 /* Set retry limit on DATA packets and Probe Responses */
a1751b22
SG		 1566 if (ieee80211_is_probe_resp(fc))
1567 data_retry_limit = 3;
1568 else
1569 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1570 tx_cmd->data_retry_limit = data_retry_limit;
a1751b22 1571 /* Set retry limit on RTS packets */
616107ed 1572 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
a1751b22
SG		 1573
1574 /* DATA packets will use the uCode station table for rate/antenna
1575 * selection */
1576 if (ieee80211_is_data(fc)) {
1577 tx_cmd->initial_rate_idx = 0;
1578 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1579 return;
1580 }
1581
1582 /**
1583 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1584 * not really a TX rate. Thus, we use the lowest supported rate for
1585 * this band. Also use the lowest supported rate if the stored rate
1586 * idx is invalid.
1587 */
1588 rate_idx = info->control.rates[0].idx;
e7392364
SG		 1589 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1590 || rate_idx > RATE_COUNT_LEGACY)
36323f81 1591 rate_idx = rate_lowest_index(&il->bands[info->band], sta);
a1751b22
SG		 1592 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1593 if (info->band == IEEE80211_BAND_5GHZ)
1594 rate_idx += IL_FIRST_OFDM_RATE;
1595 /* Get PLCP rate for tx_cmd->rate_n_flags */
1596 rate_plcp = il_rates[rate_idx].plcp;
1597 /* Zero out flags for this packet */
1598 rate_flags = 0;
1599
1600 /* Set CCK flag as needed */
1601 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1602 rate_flags |= RATE_MCS_CCK_MSK;
1603
1604 /* Set up antennas */
a0c1ef3b 1605 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 1606 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
a1751b22
SG		 1607
1608 /* Set the rate in the TX cmd */
616107ed 1609 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
a1751b22
SG		 1610}
1611
e7392364
SG		 1612static void
1613il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1614 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1615 int sta_id)
a1751b22
SG		 1616{
1617 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1618
1619 switch (keyconf->cipher) {
1620 case WLAN_CIPHER_SUITE_CCMP:
1621 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1622 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1623 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1624 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1625 D_TX("tx_cmd with AES hwcrypto\n");
1626 break;
1627
1628 case WLAN_CIPHER_SUITE_TKIP:
1629 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1630 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1631 D_TX("tx_cmd with tkip hwcrypto\n");
1632 break;
1633
1634 case WLAN_CIPHER_SUITE_WEP104:
1635 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1636 /* fall through */
1637 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG		 1638 tx_cmd->sec_ctl |=
1639 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1640 TX_CMD_SEC_SHIFT);
a1751b22
SG		 1641
1642 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1643
e7392364
SG		 1644 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1645 keyconf->keyidx);
a1751b22
SG		 1646 break;
1647
1648 default:
1649 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1650 break;
1651 }
1652}
1653
1654/*
4d69c752 1655 * start C_TX command process
a1751b22 1656 */
e7392364 1657int
36323f81
TH		 1658il4965_tx_skb(struct il_priv *il,
1659 struct ieee80211_sta *sta,
1660 struct sk_buff *skb)
a1751b22
SG		 1661{
1662 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1663 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
a1751b22
SG		 1664 struct il_station_priv *sta_priv = NULL;
1665 struct il_tx_queue *txq;
1666 struct il_queue *q;
1667 struct il_device_cmd *out_cmd;
1668 struct il_cmd_meta *out_meta;
1669 struct il_tx_cmd *tx_cmd;
a1751b22
SG		 1670 int txq_id;
1671 dma_addr_t phys_addr;
1672 dma_addr_t txcmd_phys;
1673 dma_addr_t scratch_phys;
1674 u16 len, firstlen, secondlen;
1675 u16 seq_number = 0;
1676 __le16 fc;
1677 u8 hdr_len;
1678 u8 sta_id;
1679 u8 wait_write_ptr = 0;
1680 u8 tid = 0;
1681 u8 *qc = NULL;
1682 unsigned long flags;
1683 bool is_agg = false;
1684
a1751b22
SG		 1685 spin_lock_irqsave(&il->lock, flags);
1686 if (il_is_rfkill(il)) {
1687 D_DROP("Dropping - RF KILL\n");
1688 goto drop_unlock;
1689 }
1690
1691 fc = hdr->frame_control;
1692
1693#ifdef CONFIG_IWLEGACY_DEBUG
1694 if (ieee80211_is_auth(fc))
1695 D_TX("Sending AUTH frame\n");
1696 else if (ieee80211_is_assoc_req(fc))
1697 D_TX("Sending ASSOC frame\n");
1698 else if (ieee80211_is_reassoc_req(fc))
1699 D_TX("Sending REASSOC frame\n");
1700#endif
1701
1702 hdr_len = ieee80211_hdrlen(fc);
1703
1704 /* For management frames use broadcast id to do not break aggregation */
1705 if (!ieee80211_is_data(fc))
b16db50a 1706 sta_id = il->hw_params.bcast_id;
a1751b22
SG		 1707 else {
1708 /* Find idx into station table for destination station */
36323f81 1709 sta_id = il_sta_id_or_broadcast(il, sta);
a1751b22
SG		 1710
1711 if (sta_id == IL_INVALID_STATION) {
e7392364 1712 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
a1751b22
SG		 1713 goto drop_unlock;
1714 }
1715 }
1716
1717 D_TX("station Id %d\n", sta_id);
1718
1719 if (sta)
1720 sta_priv = (void *)sta->drv_priv;
1721
1722 if (sta_priv && sta_priv->asleep &&
02f2f1a9 1723 (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) {
a1751b22
SG		 1724 /*
1725 * This sends an asynchronous command to the device,
1726 * but we can rely on it being processed before the
1727 * next frame is processed -- and the next frame to
1728 * this station is the one that will consume this
1729 * counter.
1730 * For now set the counter to just 1 since we do not
1731 * support uAPSD yet.
1732 */
1733 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1734 }
1735
d1e14e94
SG		 1736 /* FIXME: remove me ? */
1737 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1738
eb123af3
SG		 1739 /* Access category (AC) is also the queue number */
1740 txq_id = skb_get_queue_mapping(skb);
a1751b22
SG		 1741
1742 /* irqs already disabled/saved above when locking il->lock */
1743 spin_lock(&il->sta_lock);
1744
1745 if (ieee80211_is_data_qos(fc)) {
1746 qc = ieee80211_get_qos_ctl(hdr);
1747 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1748 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1749 spin_unlock(&il->sta_lock);
1750 goto drop_unlock;
1751 }
1752 seq_number = il->stations[sta_id].tid[tid].seq_number;
1753 seq_number &= IEEE80211_SCTL_SEQ;
e7392364
SG		 1754 hdr->seq_ctrl =
1755 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
a1751b22
SG		 1756 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1757 seq_number += 0x10;
1758 /* aggregation is on for this <sta,tid> */
1759 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1760 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1761 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1762 is_agg = true;
1763 }
1764 }
1765
1766 txq = &il->txq[txq_id];
1767 q = &txq->q;
1768
1769 if (unlikely(il_queue_space(q) < q->high_mark)) {
1770 spin_unlock(&il->sta_lock);
1771 goto drop_unlock;
1772 }
1773
1774 if (ieee80211_is_data_qos(fc)) {
1775 il->stations[sta_id].tid[tid].tfds_in_queue++;
1776 if (!ieee80211_has_morefrags(fc))
1777 il->stations[sta_id].tid[tid].seq_number = seq_number;
1778 }
1779
1780 spin_unlock(&il->sta_lock);
1781
00ea99e1 1782 txq->skbs[q->write_ptr] = skb;
a1751b22
SG		 1783
1784 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1785 out_cmd = txq->cmd[q->write_ptr];
1786 out_meta = &txq->meta[q->write_ptr];
1787 tx_cmd = &out_cmd->cmd.tx;
1788 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1789 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1790
1791 /*
1792 * Set up the Tx-command (not MAC!) header.
1793 * Store the chosen Tx queue and TFD idx within the sequence field;
1794 * after Tx, uCode's Tx response will return this value so driver can
1795 * locate the frame within the tx queue and do post-tx processing.
1796 */
4d69c752 1797 out_cmd->hdr.cmd = C_TX;
e7392364
SG		 1798 out_cmd->hdr.sequence =
1799 cpu_to_le16((u16)
1800 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
a1751b22
SG		 1801
1802 /* Copy MAC header from skb into command buffer */
1803 memcpy(tx_cmd->hdr, hdr, hdr_len);
1804
a1751b22 1805 /* Total # bytes to be transmitted */
bdb084b2 1806 tx_cmd->len = cpu_to_le16((u16) skb->len);
a1751b22
SG		 1807
1808 if (info->control.hw_key)
1809 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1810
1811 /* TODO need this for burst mode later on */
1812 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
a1751b22 1813
36323f81 1814 il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc);
a1751b22 1815
a1751b22
SG		 1816 /*
1817 * Use the first empty entry in this queue's command buffer array
1818 * to contain the Tx command and MAC header concatenated together
1819 * (payload data will be in another buffer).
1820 * Size of this varies, due to varying MAC header length.
1821 * If end is not dword aligned, we'll have 2 extra bytes at the end
1822 * of the MAC header (device reads on dword boundaries).
1823 * We'll tell device about this padding later.
1824 */
e7392364 1825 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
a1751b22
SG		 1826 firstlen = (len + 3) & ~3;
1827
1828 /* Tell NIC about any 2-byte padding after MAC header */
1829 if (firstlen != len)
1830 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1831
1832 /* Physical address of this Tx command's header (not MAC header!),
1833 * within command buffer array. */
e7392364
SG		 1834 txcmd_phys =
1835 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1836 PCI_DMA_BIDIRECTIONAL);
bdb084b2
SG		 1837 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
1838 goto drop_unlock;
a1751b22
SG		 1839
1840 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1841 * if any (802.11 null frames have no payload). */
1842 secondlen = skb->len - hdr_len;
1843 if (secondlen > 0) {
e7392364
SG		 1844 phys_addr =
1845 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1846 PCI_DMA_TODEVICE);
bdb084b2
SG		 1847 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
1848 goto drop_unlock;
1849 }
1850
1851 /* Add buffer containing Tx command and MAC(!) header to TFD's
1852 * first entry */
1853 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
1854 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1855 dma_unmap_len_set(out_meta, len, firstlen);
1856 if (secondlen)
1600b875
SG		 1857 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen,
1858 0, 0);
bdb084b2
SG		 1859
1860 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1861 txq->need_update = 1;
1862 } else {
1863 wait_write_ptr = 1;
1864 txq->need_update = 0;
a1751b22
SG		 1865 }
1866
e7392364
SG		 1867 scratch_phys =
1868 txcmd_phys + sizeof(struct il_cmd_header) +
1869 offsetof(struct il_tx_cmd, scratch);
a1751b22
SG		 1870
1871 /* take back ownership of DMA buffer to enable update */
e7392364
SG		 1872 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1873 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1874 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1875 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1876
bdb084b2
SG		 1877 il_update_stats(il, true, fc, skb->len);
1878
e7392364 1879 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
a1751b22 1880 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
e7392364
SG		 1881 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1882 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
a1751b22
SG		 1883
1884 /* Set up entry for this TFD in Tx byte-count array */
1885 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1600b875 1886 il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len));
a1751b22 1887
e7392364
SG		 1888 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1889 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1890
1891 /* Tell device the write idx *just past* this latest filled TFD */
1892 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1893 il_txq_update_write_ptr(il, txq);
1894 spin_unlock_irqrestore(&il->lock, flags);
1895
1896 /*
1897 * At this point the frame is "transmitted" successfully
1898 * and we will get a TX status notification eventually,
1899 * regardless of the value of ret. "ret" only indicates
1900 * whether or not we should update the write pointer.
1901 */
1902
1903 /*
1904 * Avoid atomic ops if it isn't an associated client.
1905 * Also, if this is a packet for aggregation, don't
1906 * increase the counter because the ucode will stop
1907 * aggregation queues when their respective station
1908 * goes to sleep.
1909 */
1910 if (sta_priv && sta_priv->client && !is_agg)
1911 atomic_inc(&sta_priv->pending_frames);
1912
1913 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1914 if (wait_write_ptr) {
1915 spin_lock_irqsave(&il->lock, flags);
1916 txq->need_update = 1;
1917 il_txq_update_write_ptr(il, txq);
1918 spin_unlock_irqrestore(&il->lock, flags);
1919 } else {
1920 il_stop_queue(il, txq);
1921 }
1922 }
1923
1924 return 0;
1925
1926drop_unlock:
1927 spin_unlock_irqrestore(&il->lock, flags);
1928 return -1;
1929}
1930
e7392364
SG		 1931static inline int
1932il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
a1751b22 1933{
1f9061d2
JP		 1934 ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma,
1935 GFP_KERNEL);
a1751b22
SG		 1936 if (!ptr->addr)
1937 return -ENOMEM;
1938 ptr->size = size;
1939 return 0;
1940}
1941
e7392364
SG		 1942static inline void
1943il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
a1751b22
SG		 1944{
1945 if (unlikely(!ptr->addr))
1946 return;
1947
1948 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1949 memset(ptr, 0, sizeof(*ptr));
1950}
1951
1952/**
1953 * il4965_hw_txq_ctx_free - Free TXQ Context
1954 *
1955 * Destroy all TX DMA queues and structures
1956 */
e7392364
SG		 1957void
1958il4965_hw_txq_ctx_free(struct il_priv *il)
a1751b22
SG		 1959{
1960 int txq_id;
1961
1962 /* Tx queues */
1963 if (il->txq) {
1964 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1965 if (txq_id == il->cmd_queue)
1966 il_cmd_queue_free(il);
1967 else
1968 il_tx_queue_free(il, txq_id);
1969 }
1970 il4965_free_dma_ptr(il, &il->kw);
1971
1972 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1973
1974 /* free tx queue structure */
6668e4eb 1975 il_free_txq_mem(il);
a1751b22
SG		 1976}
1977
1978/**
1979 * il4965_txq_ctx_alloc - allocate TX queue context
1980 * Allocate all Tx DMA structures and initialize them
1981 *
1982 * @param il
1983 * @return error code
1984 */
e7392364
SG		 1985int
1986il4965_txq_ctx_alloc(struct il_priv *il)
a1751b22 1987{
d87c771f 1988 int ret, txq_id;
a1751b22
SG		 1989 unsigned long flags;
1990
1991 /* Free all tx/cmd queues and keep-warm buffer */
1992 il4965_hw_txq_ctx_free(il);
1993
e7392364
SG		 1994 ret =
1995 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1996 il->hw_params.scd_bc_tbls_size);
a1751b22
SG		 1997 if (ret) {
1998 IL_ERR("Scheduler BC Table allocation failed\n");
1999 goto error_bc_tbls;
2000 }
2001 /* Alloc keep-warm buffer */
2002 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
2003 if (ret) {
2004 IL_ERR("Keep Warm allocation failed\n");
2005 goto error_kw;
2006 }
2007
2008 /* allocate tx queue structure */
2009 ret = il_alloc_txq_mem(il);
2010 if (ret)
2011 goto error;
2012
2013 spin_lock_irqsave(&il->lock, flags);
2014
2015 /* Turn off all Tx DMA fifos */
2016 il4965_txq_set_sched(il, 0);
2017
2018 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2019 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2020
2021 spin_unlock_irqrestore(&il->lock, flags);
2022
2023 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
2024 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
d87c771f 2025 ret = il_tx_queue_init(il, txq_id);
a1751b22
SG		 2026 if (ret) {
2027 IL_ERR("Tx %d queue init failed\n", txq_id);
2028 goto error;
2029 }
2030 }
2031
2032 return ret;
2033
e7392364 2034error:
a1751b22
SG		 2035 il4965_hw_txq_ctx_free(il);
2036 il4965_free_dma_ptr(il, &il->kw);
e7392364 2037error_kw:
a1751b22 2038 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
e7392364 2039error_bc_tbls:
a1751b22
SG		 2040 return ret;
2041}
2042
e7392364
SG		 2043void
2044il4965_txq_ctx_reset(struct il_priv *il)
a1751b22 2045{
d87c771f 2046 int txq_id;
a1751b22
SG		 2047 unsigned long flags;
2048
2049 spin_lock_irqsave(&il->lock, flags);
2050
2051 /* Turn off all Tx DMA fifos */
2052 il4965_txq_set_sched(il, 0);
a1751b22 2053 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2054 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2055
2056 spin_unlock_irqrestore(&il->lock, flags);
2057
2058 /* Alloc and init all Tx queues, including the command queue (#4) */
d87c771f
SG		 2059 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2060 il_tx_queue_reset(il, txq_id);
a1751b22
SG		 2061}
2062
60c46bf8 2063static void
775ed8ab 2064il4965_txq_ctx_unmap(struct il_priv *il)
a1751b22 2065{
775ed8ab 2066 int txq_id;
a1751b22
SG		 2067
2068 if (!il->txq)
2069 return;
2070
2071 /* Unmap DMA from host system and free skb's */
2072 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2073 if (txq_id == il->cmd_queue)
2074 il_cmd_queue_unmap(il);
2075 else
2076 il_tx_queue_unmap(il, txq_id);
2077}
2078
775ed8ab
SG		 2079/**
2080 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2081 */
2082void
2083il4965_txq_ctx_stop(struct il_priv *il)
2084{
2085 int ch, ret;
2086
2087 _il_wr_prph(il, IL49_SCD_TXFACT, 0);
2088
2089 /* Stop each Tx DMA channel, and wait for it to be idle */
2090 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2091 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2092 ret =
2093 _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
2094 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2095 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2096 1000);
2097 if (ret < 0)
2098 IL_ERR("Timeout stopping DMA channel %d [0x%08x]",
2099 ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
2100 }
2101}
2102
a1751b22
SG		 2103/*
2104 * Find first available (lowest unused) Tx Queue, mark it "active".
2105 * Called only when finding queue for aggregation.
2106 * Should never return anything < 7, because they should already
2107 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2108 */
e7392364
SG		 2109static int
2110il4965_txq_ctx_activate_free(struct il_priv *il)
a1751b22
SG		 2111{
2112 int txq_id;
2113
2114 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2115 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2116 return txq_id;
2117 return -1;
2118}
2119
2120/**
2121 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2122 */
e7392364
SG		 2123static void
2124il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
a1751b22
SG		 2125{
2126 /* Simply stop the queue, but don't change any configuration;
2127 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
e7392364 2128 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 2129 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2130 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
a1751b22
SG		 2131}
2132
2133/**
2134 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2135 */
e7392364
SG		 2136static int
2137il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
a1751b22
SG		 2138{
2139 u32 tbl_dw_addr;
2140 u32 tbl_dw;
2141 u16 scd_q2ratid;
2142
2143 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2144
e7392364
SG		 2145 tbl_dw_addr =
2146 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
a1751b22
SG		 2147
2148 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2149
2150 if (txq_id & 0x1)
2151 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2152 else
2153 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2154
2155 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2156
2157 return 0;
2158}
2159
2160/**
2161 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2162 *
2163 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2164 * i.e. it must be one of the higher queues used for aggregation
2165 */
e7392364
SG		 2166static int
2167il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2168 int tid, u16 ssn_idx)
a1751b22
SG		 2169{
2170 unsigned long flags;
2171 u16 ra_tid;
2172 int ret;
2173
2174 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2175 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2176 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2177 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2178 txq_id, IL49_FIRST_AMPDU_QUEUE,
2179 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2180 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2181 return -EINVAL;
2182 }
2183
2184 ra_tid = BUILD_RAxTID(sta_id, tid);
2185
2186 /* Modify device's station table to Tx this TID */
2187 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2188 if (ret)
2189 return ret;
2190
2191 spin_lock_irqsave(&il->lock, flags);
2192
2193 /* Stop this Tx queue before configuring it */
2194 il4965_tx_queue_stop_scheduler(il, txq_id);
2195
2196 /* Map receiver-address / traffic-ID to this queue */
2197 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2198
2199 /* Set this queue as a chain-building queue */
2200 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2201
2202 /* Place first TFD at idx corresponding to start sequence number.
2203 * Assumes that ssn_idx is valid (!= 0xFFF) */
2204 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2205 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2206 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2207
2208 /* Set up Tx win size and frame limit for this queue */
2209 il_write_targ_mem(il,
e7392364
SG		 2210 il->scd_base_addr +
2211 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2212 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2213 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
a1751b22 2214
e7392364
SG		 2215 il_write_targ_mem(il,
2216 il->scd_base_addr +
2217 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2218 (SCD_FRAME_LIMIT <<
2219 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2220 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
a1751b22
SG		 2221
2222 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2223
2224 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2225 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2226
2227 spin_unlock_irqrestore(&il->lock, flags);
2228
2229 return 0;
2230}
2231
e7392364
SG		 2232int
2233il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2234 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
a1751b22
SG		 2235{
2236 int sta_id;
2237 int tx_fifo;
2238 int txq_id;
2239 int ret;
2240 unsigned long flags;
2241 struct il_tid_data *tid_data;
2242
83007196
SG		 2243 /* FIXME: warning if tx fifo not found ? */
2244 tx_fifo = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2245 if (unlikely(tx_fifo < 0))
2246 return tx_fifo;
2247
53611e05 2248 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
a1751b22
SG		 2249
2250 sta_id = il_sta_id(sta);
2251 if (sta_id == IL_INVALID_STATION) {
2252 IL_ERR("Start AGG on invalid station\n");
2253 return -ENXIO;
2254 }
2255 if (unlikely(tid >= MAX_TID_COUNT))
2256 return -EINVAL;
2257
2258 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2259 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2260 return -ENXIO;
2261 }
2262
2263 txq_id = il4965_txq_ctx_activate_free(il);
2264 if (txq_id == -1) {
2265 IL_ERR("No free aggregation queue available\n");
2266 return -ENXIO;
2267 }
2268
2269 spin_lock_irqsave(&il->sta_lock, flags);
2270 tid_data = &il->stations[sta_id].tid[tid];
9a886586 2271 *ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
a1751b22 2272 tid_data->agg.txq_id = txq_id;
e7392364 2273 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
a1751b22
SG		 2274 spin_unlock_irqrestore(&il->sta_lock, flags);
2275
e7392364 2276 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
a1751b22
SG		 2277 if (ret)
2278 return ret;
2279
2280 spin_lock_irqsave(&il->sta_lock, flags);
2281 tid_data = &il->stations[sta_id].tid[tid];
2282 if (tid_data->tfds_in_queue == 0) {
2283 D_HT("HW queue is empty\n");
2284 tid_data->agg.state = IL_AGG_ON;
2285 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2286 } else {
e7392364
SG		 2287 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2288 tid_data->tfds_in_queue);
a1751b22
SG		 2289 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2290 }
2291 spin_unlock_irqrestore(&il->sta_lock, flags);
2292 return ret;
2293}
2294
2295/**
2296 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2297 * il->lock must be held by the caller
2298 */
e7392364
SG		 2299static int
2300il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
a1751b22
SG		 2301{
2302 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2303 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2304 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2305 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2306 txq_id, IL49_FIRST_AMPDU_QUEUE,
2307 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2308 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2309 return -EINVAL;
2310 }
2311
2312 il4965_tx_queue_stop_scheduler(il, txq_id);
2313
e7392364 2314 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
a1751b22
SG		 2315
2316 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2317 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2318 /* supposes that ssn_idx is valid (!= 0xFFF) */
2319 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2320
e7392364 2321 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
a1751b22
SG		 2322 il_txq_ctx_deactivate(il, txq_id);
2323 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2324
2325 return 0;
2326}
2327
e7392364
SG		 2328int
2329il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2330 struct ieee80211_sta *sta, u16 tid)
a1751b22
SG		 2331{
2332 int tx_fifo_id, txq_id, sta_id, ssn;
2333 struct il_tid_data *tid_data;
2334 int write_ptr, read_ptr;
2335 unsigned long flags;
2336
83007196
SG		 2337 /* FIXME: warning if tx_fifo_id not found ? */
2338 tx_fifo_id = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2339 if (unlikely(tx_fifo_id < 0))
2340 return tx_fifo_id;
2341
2342 sta_id = il_sta_id(sta);
2343
2344 if (sta_id == IL_INVALID_STATION) {
2345 IL_ERR("Invalid station for AGG tid %d\n", tid);
2346 return -ENXIO;
2347 }
2348
2349 spin_lock_irqsave(&il->sta_lock, flags);
2350
2351 tid_data = &il->stations[sta_id].tid[tid];
2352 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2353 txq_id = tid_data->agg.txq_id;
2354
2355 switch (il->stations[sta_id].tid[tid].agg.state) {
2356 case IL_EMPTYING_HW_QUEUE_ADDBA:
2357 /*
2358 * This can happen if the peer stops aggregation
2359 * again before we've had a chance to drain the
2360 * queue we selected previously, i.e. before the
2361 * session was really started completely.
2362 */
2363 D_HT("AGG stop before setup done\n");
2364 goto turn_off;
2365 case IL_AGG_ON:
2366 break;
2367 default:
2368 IL_WARN("Stopping AGG while state not ON or starting\n");
2369 }
2370
2371 write_ptr = il->txq[txq_id].q.write_ptr;
2372 read_ptr = il->txq[txq_id].q.read_ptr;
2373
2374 /* The queue is not empty */
2375 if (write_ptr != read_ptr) {
2376 D_HT("Stopping a non empty AGG HW QUEUE\n");
2377 il->stations[sta_id].tid[tid].agg.state =
e7392364 2378 IL_EMPTYING_HW_QUEUE_DELBA;
a1751b22
SG		 2379 spin_unlock_irqrestore(&il->sta_lock, flags);
2380 return 0;
2381 }
2382
2383 D_HT("HW queue is empty\n");
e7392364 2384turn_off:
a1751b22
SG		 2385 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2386
2387 /* do not restore/save irqs */
2388 spin_unlock(&il->sta_lock);
2389 spin_lock(&il->lock);
2390
2391 /*
2392 * the only reason this call can fail is queue number out of range,
2393 * which can happen if uCode is reloaded and all the station
2394 * information are lost. if it is outside the range, there is no need
2395 * to deactivate the uCode queue, just return "success" to allow
2396 * mac80211 to clean up it own data.
2397 */
2398 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2399 spin_unlock_irqrestore(&il->lock, flags);
2400
2401 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2402
2403 return 0;
2404}
2405
e7392364
SG		 2406int
2407il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
a1751b22
SG		 2408{
2409 struct il_queue *q = &il->txq[txq_id].q;
2410 u8 *addr = il->stations[sta_id].sta.sta.addr;
2411 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
a1751b22
SG		 2412
2413 lockdep_assert_held(&il->sta_lock);
2414
2415 switch (il->stations[sta_id].tid[tid].agg.state) {
2416 case IL_EMPTYING_HW_QUEUE_DELBA:
2417 /* We are reclaiming the last packet of the */
2418 /* aggregated HW queue */
e7392364 2419 if (txq_id == tid_data->agg.txq_id &&
a1751b22 2420 q->read_ptr == q->write_ptr) {
9a886586 2421 u16 ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
83007196 2422 int tx_fifo = il4965_get_fifo_from_tid(tid);
e7392364 2423 D_HT("HW queue empty: continue DELBA flow\n");
a1751b22
SG		 2424 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2425 tid_data->agg.state = IL_AGG_OFF;
83007196 2426 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2427 }
2428 break;
2429 case IL_EMPTYING_HW_QUEUE_ADDBA:
2430 /* We are reclaiming the last packet of the queue */
2431 if (tid_data->tfds_in_queue == 0) {
e7392364 2432 D_HT("HW queue empty: continue ADDBA flow\n");
a1751b22 2433 tid_data->agg.state = IL_AGG_ON;
83007196 2434 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2435 }
2436 break;
2437 }
2438
2439 return 0;
2440}
2441
e7392364 2442static void
83007196 2443il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
a1751b22
SG		 2444{
2445 struct ieee80211_sta *sta;
2446 struct il_station_priv *sta_priv;
2447
2448 rcu_read_lock();
83007196 2449 sta = ieee80211_find_sta(il->vif, addr1);
a1751b22
SG		 2450 if (sta) {
2451 sta_priv = (void *)sta->drv_priv;
2452 /* avoid atomic ops if this isn't a client */
2453 if (sta_priv->client &&
2454 atomic_dec_return(&sta_priv->pending_frames) == 0)
2455 ieee80211_sta_block_awake(il->hw, sta, false);
2456 }
2457 rcu_read_unlock();
2458}
2459
2460static void
00ea99e1 2461il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
a1751b22 2462{
00ea99e1 2463 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
a1751b22
SG		 2464
2465 if (!is_agg)
83007196 2466 il4965_non_agg_tx_status(il, hdr->addr1);
a1751b22 2467
00ea99e1 2468 ieee80211_tx_status_irqsafe(il->hw, skb);
a1751b22
SG		 2469}
2470
e7392364
SG		 2471int
2472il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
a1751b22
SG		 2473{
2474 struct il_tx_queue *txq = &il->txq[txq_id];
2475 struct il_queue *q = &txq->q;
a1751b22
SG		 2476 int nfreed = 0;
2477 struct ieee80211_hdr *hdr;
00ea99e1 2478 struct sk_buff *skb;
a1751b22
SG		 2479
2480 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2481 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 2482 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2483 q->write_ptr, q->read_ptr);
a1751b22
SG		 2484 return 0;
2485 }
2486
e7392364 2487 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
a1751b22
SG		 2488 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2489
00ea99e1 2490 skb = txq->skbs[txq->q.read_ptr];
a1751b22 2491
00ea99e1 2492 if (WARN_ON_ONCE(skb == NULL))
a1751b22
SG		 2493 continue;
2494
00ea99e1 2495 hdr = (struct ieee80211_hdr *) skb->data;
a1751b22
SG		 2496 if (ieee80211_is_data_qos(hdr->frame_control))
2497 nfreed++;
2498
00ea99e1 2499 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
a1751b22 2500
00ea99e1 2501 txq->skbs[txq->q.read_ptr] = NULL;
1600b875 2502 il->ops->txq_free_tfd(il, txq);
a1751b22
SG		 2503 }
2504 return nfreed;
2505}
2506
2507/**
2508 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2509 *
2510 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2511 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2512 */
e7392364
SG		 2513static int
2514il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2515 struct il_compressed_ba_resp *ba_resp)
a1751b22
SG		 2516{
2517 int i, sh, ack;
2518 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2519 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2520 int successes = 0;
2521 struct ieee80211_tx_info *info;
2522 u64 bitmap, sent_bitmap;
2523
e7392364 2524 if (unlikely(!agg->wait_for_ba)) {
a1751b22
SG		 2525 if (unlikely(ba_resp->bitmap))
2526 IL_ERR("Received BA when not expected\n");
2527 return -EINVAL;
2528 }
2529
2530 /* Mark that the expected block-ack response arrived */
2531 agg->wait_for_ba = 0;
e7392364 2532 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
a1751b22
SG		 2533
2534 /* Calculate shift to align block-ack bits with our Tx win bits */
2535 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
e7392364 2536 if (sh < 0) /* tbw something is wrong with indices */
a1751b22
SG		 2537 sh += 0x100;
2538
2539 if (agg->frame_count > (64 - sh)) {
2540 D_TX_REPLY("more frames than bitmap size");
2541 return -1;
2542 }
2543
2544 /* don't use 64-bit values for now */
2545 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2546
2547 /* check for success or failure according to the
2548 * transmitted bitmap and block-ack bitmap */
2549 sent_bitmap = bitmap & agg->bitmap;
2550
2551 /* For each frame attempted in aggregation,
2552 * update driver's record of tx frame's status. */
2553 i = 0;
2554 while (sent_bitmap) {
2555 ack = sent_bitmap & 1ULL;
2556 successes += ack;
e7392364
SG		 2557 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2558 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
a1751b22
SG		 2559 sent_bitmap >>= 1;
2560 ++i;
2561 }
2562
e7392364 2563 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
a1751b22 2564
00ea99e1 2565 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
a1751b22
SG		 2566 memset(&info->status, 0, sizeof(info->status));
2567 info->flags |= IEEE80211_TX_STAT_ACK;
2568 info->flags |= IEEE80211_TX_STAT_AMPDU;
2569 info->status.ampdu_ack_len = successes;
2570 info->status.ampdu_len = agg->frame_count;
2571 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2572
2573 return 0;
2574}
2575
3dfea27d
SG		 2576static inline bool
2577il4965_is_tx_success(u32 status)
2578{
2579 status &= TX_STATUS_MSK;
2580 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2581}
2582
2583static u8
2584il4965_find_station(struct il_priv *il, const u8 *addr)
2585{
2586 int i;
2587 int start = 0;
2588 int ret = IL_INVALID_STATION;
2589 unsigned long flags;
2590
2591 if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2592 start = IL_STA_ID;
2593
2594 if (is_broadcast_ether_addr(addr))
2595 return il->hw_params.bcast_id;
2596
2597 spin_lock_irqsave(&il->sta_lock, flags);
2598 for (i = start; i < il->hw_params.max_stations; i++)
2599 if (il->stations[i].used &&
2e42e474 2600 ether_addr_equal(il->stations[i].sta.sta.addr, addr)) {
3dfea27d
SG		 2601 ret = i;
2602 goto out;
2603 }
2604
2605 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2606
2607out:
2608 /*
2609 * It may be possible that more commands interacting with stations
2610 * arrive before we completed processing the adding of
2611 * station
2612 */
2613 if (ret != IL_INVALID_STATION &&
2614 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2615 ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2616 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2617 IL_ERR("Requested station info for sta %d before ready.\n",
2618 ret);
2619 ret = IL_INVALID_STATION;
2620 }
2621 spin_unlock_irqrestore(&il->sta_lock, flags);
2622 return ret;
2623}
2624
2625static int
2626il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2627{
2628 if (il->iw_mode == NL80211_IFTYPE_STATION)
2629 return IL_AP_ID;
2630 else {
2631 u8 *da = ieee80211_get_DA(hdr);
2632
2633 return il4965_find_station(il, da);
2634 }
2635}
2636
2637static inline u32
2638il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2639{
9a886586
JB		 2640 return le32_to_cpup(&tx_resp->u.status +
2641 tx_resp->frame_count) & IEEE80211_MAX_SN;
3dfea27d
SG		 2642}
2643
2644static inline u32
2645il4965_tx_status_to_mac80211(u32 status)
2646{
2647 status &= TX_STATUS_MSK;
2648
2649 switch (status) {
2650 case TX_STATUS_SUCCESS:
2651 case TX_STATUS_DIRECT_DONE:
2652 return IEEE80211_TX_STAT_ACK;
2653 case TX_STATUS_FAIL_DEST_PS:
2654 return IEEE80211_TX_STAT_TX_FILTERED;
2655 default:
2656 return 0;
2657 }
2658}
2659
2660/**
2661 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2662 */
2663static int
2664il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2665 struct il4965_tx_resp *tx_resp, int txq_id,
2666 u16 start_idx)
2667{
2668 u16 status;
2669 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2670 struct ieee80211_tx_info *info = NULL;
2671 struct ieee80211_hdr *hdr = NULL;
2672 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2673 int i, sh, idx;
2674 u16 seq;
2675 if (agg->wait_for_ba)
2676 D_TX_REPLY("got tx response w/o block-ack\n");
2677
2678 agg->frame_count = tx_resp->frame_count;
2679 agg->start_idx = start_idx;
2680 agg->rate_n_flags = rate_n_flags;
2681 agg->bitmap = 0;
2682
2683 /* num frames attempted by Tx command */
2684 if (agg->frame_count == 1) {
2685 /* Only one frame was attempted; no block-ack will arrive */
2686 status = le16_to_cpu(frame_status[0].status);
2687 idx = start_idx;
2688
2689 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2690 agg->frame_count, agg->start_idx, idx);
2691
2692 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2693 info->status.rates[0].count = tx_resp->failure_frame + 1;
2694 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2695 info->flags |= il4965_tx_status_to_mac80211(status);
2696 il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2697
2698 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2699 tx_resp->failure_frame);
2700 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2701
2702 agg->wait_for_ba = 0;
2703 } else {
2704 /* Two or more frames were attempted; expect block-ack */
2705 u64 bitmap = 0;
2706 int start = agg->start_idx;
2707 struct sk_buff *skb;
2708
2709 /* Construct bit-map of pending frames within Tx win */
2710 for (i = 0; i < agg->frame_count; i++) {
2711 u16 sc;
2712 status = le16_to_cpu(frame_status[i].status);
2713 seq = le16_to_cpu(frame_status[i].sequence);
2714 idx = SEQ_TO_IDX(seq);
2715 txq_id = SEQ_TO_QUEUE(seq);
2716
2717 if (status &
2718 (AGG_TX_STATE_FEW_BYTES_MSK |
2719 AGG_TX_STATE_ABORT_MSK))
2720 continue;
2721
2722 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2723 agg->frame_count, txq_id, idx);
2724
2725 skb = il->txq[txq_id].skbs[idx];
2726 if (WARN_ON_ONCE(skb == NULL))
2727 return -1;
2728 hdr = (struct ieee80211_hdr *) skb->data;
2729
2730 sc = le16_to_cpu(hdr->seq_ctrl);
9a886586 2731 if (idx != (IEEE80211_SEQ_TO_SN(sc) & 0xff)) {
3dfea27d
SG		 2732 IL_ERR("BUG_ON idx doesn't match seq control"
2733 " idx=%d, seq_idx=%d, seq=%d\n", idx,
9a886586 2734 IEEE80211_SEQ_TO_SN(sc), hdr->seq_ctrl);
3dfea27d
SG		 2735 return -1;
2736 }
2737
2738 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
9a886586 2739 IEEE80211_SEQ_TO_SN(sc));
3dfea27d
SG		 2740
2741 sh = idx - start;
2742 if (sh > 64) {
2743 sh = (start - idx) + 0xff;
2744 bitmap = bitmap << sh;
2745 sh = 0;
2746 start = idx;
2747 } else if (sh < -64)
2748 sh = 0xff - (start - idx);
2749 else if (sh < 0) {
2750 sh = start - idx;
2751 start = idx;
2752 bitmap = bitmap << sh;
2753 sh = 0;
2754 }
2755 bitmap |= 1ULL << sh;
2756 D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2757 (unsigned long long)bitmap);
2758 }
2759
2760 agg->bitmap = bitmap;
2761 agg->start_idx = start;
2762 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2763 agg->frame_count, agg->start_idx,
2764 (unsigned long long)agg->bitmap);
2765
2766 if (bitmap)
2767 agg->wait_for_ba = 1;
2768 }
2769 return 0;
2770}
2771
2772/**
2773 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2774 */
2775static void
2776il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2777{
2778 struct il_rx_pkt *pkt = rxb_addr(rxb);
2779 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2780 int txq_id = SEQ_TO_QUEUE(sequence);
2781 int idx = SEQ_TO_IDX(sequence);
2782 struct il_tx_queue *txq = &il->txq[txq_id];
2783 struct sk_buff *skb;
2784 struct ieee80211_hdr *hdr;
2785 struct ieee80211_tx_info *info;
2786 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2787 u32 status = le32_to_cpu(tx_resp->u.status);
2788 int uninitialized_var(tid);
2789 int sta_id;
2790 int freed;
2791 u8 *qc = NULL;
2792 unsigned long flags;
2793
2794 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2795 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2796 "is out of range [0-%d] %d %d\n", txq_id, idx,
2797 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2798 return;
2799 }
2800
2801 txq->time_stamp = jiffies;
2802
2803 skb = txq->skbs[txq->q.read_ptr];
2804 info = IEEE80211_SKB_CB(skb);
2805 memset(&info->status, 0, sizeof(info->status));
2806
2807 hdr = (struct ieee80211_hdr *) skb->data;
2808 if (ieee80211_is_data_qos(hdr->frame_control)) {
2809 qc = ieee80211_get_qos_ctl(hdr);
2810 tid = qc[0] & 0xf;
2811 }
2812
2813 sta_id = il4965_get_ra_sta_id(il, hdr);
2814 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2815 IL_ERR("Station not known\n");
2816 return;
2817 }
2818
8cdbab7f
SG		 2819 /*
2820 * Firmware will not transmit frame on passive channel, if it not yet
2821 * received some valid frame on that channel. When this error happen
2822 * we have to wait until firmware will unblock itself i.e. when we
2823 * note received beacon or other frame. We unblock queues in
2824 * il4965_pass_packet_to_mac80211 or in il_mac_bss_info_changed.
2825 */
2826 if (unlikely((status & TX_STATUS_MSK) == TX_STATUS_FAIL_PASSIVE_NO_RX) &&
2827 il->iw_mode == NL80211_IFTYPE_STATION) {
2828 il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
2829 D_INFO("Stopped queues - RX waiting on passive channel\n");
2830 }
2831
3dfea27d
SG		 2832 spin_lock_irqsave(&il->sta_lock, flags);
2833 if (txq->sched_retry) {
2834 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2835 struct il_ht_agg *agg = NULL;
2836 WARN_ON(!qc);
2837
2838 agg = &il->stations[sta_id].tid[tid].agg;
2839
2840 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2841
2842 /* check if BAR is needed */
2843 if (tx_resp->frame_count == 1 &&
2844 !il4965_is_tx_success(status))
2845 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2846
2847 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2848 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2849 D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2850 "%d idx %d\n", scd_ssn, idx);
2851 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2852 if (qc)
2853 il4965_free_tfds_in_queue(il, sta_id, tid,
2854 freed);
2855
2856 if (il->mac80211_registered &&
2857 il_queue_space(&txq->q) > txq->q.low_mark &&
2858 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2859 il_wake_queue(il, txq);
2860 }
2861 } else {
2862 info->status.rates[0].count = tx_resp->failure_frame + 1;
2863 info->flags |= il4965_tx_status_to_mac80211(status);
2864 il4965_hwrate_to_tx_control(il,
2865 le32_to_cpu(tx_resp->rate_n_flags),
2866 info);
2867
2868 D_TX_REPLY("TXQ %d status %s (0x%08x) "
2869 "rate_n_flags 0x%x retries %d\n", txq_id,
2870 il4965_get_tx_fail_reason(status), status,
2871 le32_to_cpu(tx_resp->rate_n_flags),
2872 tx_resp->failure_frame);
2873
2874 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2875 if (qc && likely(sta_id != IL_INVALID_STATION))
2876 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2877 else if (sta_id == IL_INVALID_STATION)
2878 D_TX_REPLY("Station not known\n");
2879
2880 if (il->mac80211_registered &&
2881 il_queue_space(&txq->q) > txq->q.low_mark)
2882 il_wake_queue(il, txq);
2883 }
2884 if (qc && likely(sta_id != IL_INVALID_STATION))
2885 il4965_txq_check_empty(il, sta_id, tid, txq_id);
2886
2887 il4965_check_abort_status(il, tx_resp->frame_count, status);
2888
2889 spin_unlock_irqrestore(&il->sta_lock, flags);
2890}
2891
a1751b22
SG		 2892/**
2893 * translate ucode response to mac80211 tx status control values
2894 */
e7392364
SG		 2895void
2896il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2897 struct ieee80211_tx_info *info)
a1751b22 2898{
d748b464 2899 struct ieee80211_tx_rate *r = &info->status.rates[0];
a1751b22 2900
d748b464 2901 info->status.antenna =
e7392364 2902 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
a1751b22
SG		 2903 if (rate_n_flags & RATE_MCS_HT_MSK)
2904 r->flags |= IEEE80211_TX_RC_MCS;
2905 if (rate_n_flags & RATE_MCS_GF_MSK)
2906 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2907 if (rate_n_flags & RATE_MCS_HT40_MSK)
2908 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2909 if (rate_n_flags & RATE_MCS_DUP_MSK)
2910 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2911 if (rate_n_flags & RATE_MCS_SGI_MSK)
2912 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2913 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2914}
2915
2916/**
6e9848b4 2917 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
a1751b22
SG		 2918 *
2919 * Handles block-acknowledge notification from device, which reports success
2920 * of frames sent via aggregation.
2921 */
60c46bf8 2922static void
e7392364 2923il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 2924{
2925 struct il_rx_pkt *pkt = rxb_addr(rxb);
2926 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2927 struct il_tx_queue *txq = NULL;
2928 struct il_ht_agg *agg;
2929 int idx;
2930 int sta_id;
2931 int tid;
2932 unsigned long flags;
2933
2934 /* "flow" corresponds to Tx queue */
2935 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2936
2937 /* "ssn" is start of block-ack Tx win, corresponds to idx
2938 * (in Tx queue's circular buffer) of first TFD/frame in win */
2939 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2940
2941 if (scd_flow >= il->hw_params.max_txq_num) {
e7392364 2942 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
a1751b22
SG		 2943 return;
2944 }
2945
2946 txq = &il->txq[scd_flow];
2947 sta_id = ba_resp->sta_id;
2948 tid = ba_resp->tid;
2949 agg = &il->stations[sta_id].tid[tid].agg;
2950 if (unlikely(agg->txq_id != scd_flow)) {
2951 /*
2952 * FIXME: this is a uCode bug which need to be addressed,
2953 * log the information and return for now!
2954 * since it is possible happen very often and in order
2955 * not to fill the syslog, don't enable the logging by default
2956 */
e7392364
SG		 2957 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2958 scd_flow, agg->txq_id);
a1751b22
SG		 2959 return;
2960 }
2961
2962 /* Find idx just before block-ack win */
2963 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2964
2965 spin_lock_irqsave(&il->sta_lock, flags);
2966
e7392364 2967 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
1722f8e1 2968 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
e7392364
SG		 2969 ba_resp->sta_id);
2970 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2971 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2972 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2973 ba_resp->scd_flow, ba_resp->scd_ssn);
2974 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2975 (unsigned long long)agg->bitmap);
a1751b22
SG		 2976
2977 /* Update driver's record of ACK vs. not for each frame in win */
2978 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2979
2980 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2981 * block-ack win (we assume that they've been successfully
2982 * transmitted ... if not, it's too late anyway). */
2983 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2984 /* calculate mac80211 ampdu sw queue to wake */
2985 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2986 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2987
2988 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2989 il->mac80211_registered &&
2990 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2991 il_wake_queue(il, txq);
2992
2993 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2994 }
2995
2996 spin_unlock_irqrestore(&il->sta_lock, flags);
2997}
2998
2999#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 3000const char *
3001il4965_get_tx_fail_reason(u32 status)
a1751b22
SG		 3002{
3003#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
3004#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
3005
3006 switch (status & TX_STATUS_MSK) {
3007 case TX_STATUS_SUCCESS:
3008 return "SUCCESS";
e7392364
SG		 3009 TX_STATUS_POSTPONE(DELAY);
3010 TX_STATUS_POSTPONE(FEW_BYTES);
3011 TX_STATUS_POSTPONE(QUIET_PERIOD);
3012 TX_STATUS_POSTPONE(CALC_TTAK);
3013 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
3014 TX_STATUS_FAIL(SHORT_LIMIT);
3015 TX_STATUS_FAIL(LONG_LIMIT);
3016 TX_STATUS_FAIL(FIFO_UNDERRUN);
3017 TX_STATUS_FAIL(DRAIN_FLOW);
3018 TX_STATUS_FAIL(RFKILL_FLUSH);
3019 TX_STATUS_FAIL(LIFE_EXPIRE);
3020 TX_STATUS_FAIL(DEST_PS);
3021 TX_STATUS_FAIL(HOST_ABORTED);
3022 TX_STATUS_FAIL(BT_RETRY);
3023 TX_STATUS_FAIL(STA_INVALID);
3024 TX_STATUS_FAIL(FRAG_DROPPED);
3025 TX_STATUS_FAIL(TID_DISABLE);
3026 TX_STATUS_FAIL(FIFO_FLUSHED);
3027 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
3028 TX_STATUS_FAIL(PASSIVE_NO_RX);
3029 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
a1751b22
SG		 3030 }
3031
3032 return "UNKNOWN";
3033
3034#undef TX_STATUS_FAIL
3035#undef TX_STATUS_POSTPONE
3036}
3037#endif /* CONFIG_IWLEGACY_DEBUG */
3038
eb3cdfb7
SG		 3039static struct il_link_quality_cmd *
3040il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
3041{
3042 int i, r;
3043 struct il_link_quality_cmd *link_cmd;
3044 u32 rate_flags = 0;
3045 __le32 rate_n_flags;
3046
3047 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3048 if (!link_cmd) {
3049 IL_ERR("Unable to allocate memory for LQ cmd.\n");
3050 return NULL;
3051 }
3052 /* Set up the rate scaling to start at selected rate, fall back
3053 * all the way down to 1M in IEEE order, and then spin on 1M */
3054 if (il->band == IEEE80211_BAND_5GHZ)
3055 r = RATE_6M_IDX;
3056 else
3057 r = RATE_1M_IDX;
3058
3059 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3060 rate_flags |= RATE_MCS_CCK_MSK;
3061
e7392364
SG		 3062 rate_flags |=
3063 il4965_first_antenna(il->hw_params.
3064 valid_tx_ant) << RATE_MCS_ANT_POS;
616107ed 3065 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
eb3cdfb7
SG		 3066 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3067 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3068
3069 link_cmd->general_params.single_stream_ant_msk =
e7392364 3070 il4965_first_antenna(il->hw_params.valid_tx_ant);
eb3cdfb7
SG		 3071
3072 link_cmd->general_params.dual_stream_ant_msk =
e7392364
SG		 3073 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3074 valid_tx_ant);
eb3cdfb7
SG		 3075 if (!link_cmd->general_params.dual_stream_ant_msk) {
3076 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3077 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3078 link_cmd->general_params.dual_stream_ant_msk =
e7392364 3079 il->hw_params.valid_tx_ant;
eb3cdfb7
SG		 3080 }
3081
3082 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3083 link_cmd->agg_params.agg_time_limit =
e7392364 3084 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
eb3cdfb7
SG		 3085
3086 link_cmd->sta_id = sta_id;
3087
3088 return link_cmd;
3089}
3090
3091/*
3092 * il4965_add_bssid_station - Add the special IBSS BSSID station
3093 *
3094 * Function sleeps.
3095 */
3096int
83007196 3097il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
eb3cdfb7
SG		 3098{
3099 int ret;
3100 u8 sta_id;
3101 struct il_link_quality_cmd *link_cmd;
3102 unsigned long flags;
3103
3104 if (sta_id_r)
3105 *sta_id_r = IL_INVALID_STATION;
3106
83007196 3107 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
eb3cdfb7
SG		 3108 if (ret) {
3109 IL_ERR("Unable to add station %pM\n", addr);
3110 return ret;
3111 }
3112
3113 if (sta_id_r)
3114 *sta_id_r = sta_id;
3115
3116 spin_lock_irqsave(&il->sta_lock, flags);
3117 il->stations[sta_id].used |= IL_STA_LOCAL;
3118 spin_unlock_irqrestore(&il->sta_lock, flags);
3119
3120 /* Set up default rate scaling table in device's station table */
3121 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3122 if (!link_cmd) {
e7392364
SG		 3123 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3124 addr);
eb3cdfb7
SG		 3125 return -ENOMEM;
3126 }
3127
83007196 3128 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
eb3cdfb7
SG		 3129 if (ret)
3130 IL_ERR("Link quality command failed (%d)\n", ret);
3131
3132 spin_lock_irqsave(&il->sta_lock, flags);
3133 il->stations[sta_id].lq = link_cmd;
3134 spin_unlock_irqrestore(&il->sta_lock, flags);
3135
3136 return 0;
3137}
3138
e7392364 3139static int
83007196 3140il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
eb3cdfb7 3141{
d735f921 3142 int i;
eb3cdfb7
SG		 3143 u8 buff[sizeof(struct il_wep_cmd) +
3144 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3145 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
e7392364 3146 size_t cmd_size = sizeof(struct il_wep_cmd);
eb3cdfb7 3147 struct il_host_cmd cmd = {
d98e2942 3148 .id = C_WEPKEY,
eb3cdfb7
SG		 3149 .data = wep_cmd,
3150 .flags = CMD_SYNC,
3151 };
d735f921 3152 bool not_empty = false;
eb3cdfb7
SG		 3153
3154 might_sleep();
3155
e7392364
SG		 3156 memset(wep_cmd, 0,
3157 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
eb3cdfb7 3158
e7392364 3159 for (i = 0; i < WEP_KEYS_MAX; i++) {
d735f921
SG		 3160 u8 key_size = il->_4965.wep_keys[i].key_size;
3161
eb3cdfb7 3162 wep_cmd->key[i].key_idx = i;
d735f921 3163 if (key_size) {
eb3cdfb7 3164 wep_cmd->key[i].key_offset = i;
d735f921
SG		 3165 not_empty = true;
3166 } else
eb3cdfb7 3167 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
eb3cdfb7 3168
d735f921
SG		 3169 wep_cmd->key[i].key_size = key_size;
3170 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
eb3cdfb7
SG		 3171 }
3172
3173 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3174 wep_cmd->num_keys = WEP_KEYS_MAX;
3175
3176 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
eb3cdfb7
SG		 3177 cmd.len = cmd_size;
3178
3179 if (not_empty || send_if_empty)
3180 return il_send_cmd(il, &cmd);
3181 else
3182 return 0;
3183}
3184
e7392364 3185int
83007196 3186il4965_restore_default_wep_keys(struct il_priv *il)
eb3cdfb7
SG		 3187{
3188 lockdep_assert_held(&il->mutex);
3189
83007196 3190 return il4965_static_wepkey_cmd(il, false);
eb3cdfb7
SG		 3191}
3192
e7392364 3193int
83007196 3194il4965_remove_default_wep_key(struct il_priv *il,
e7392364 3195 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3196{
3197 int ret;
d735f921 3198 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3199
3200 lockdep_assert_held(&il->mutex);
3201
d735f921 3202 D_WEP("Removing default WEP key: idx=%d\n", idx);
eb3cdfb7 3203
d735f921 3204 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
eb3cdfb7 3205 if (il_is_rfkill(il)) {
e7392364 3206 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
eb3cdfb7
SG		 3207 /* but keys in device are clear anyway so return success */
3208 return 0;
3209 }
83007196 3210 ret = il4965_static_wepkey_cmd(il, 1);
d735f921 3211 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
eb3cdfb7
SG		 3212
3213 return ret;
3214}
3215
e7392364 3216int
83007196 3217il4965_set_default_wep_key(struct il_priv *il,
e7392364 3218 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3219{
3220 int ret;
d735f921
SG		 3221 int len = keyconf->keylen;
3222 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3223
3224 lockdep_assert_held(&il->mutex);
3225
d735f921 3226 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
eb3cdfb7
SG		 3227 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3228 return -EINVAL;
3229 }
3230
3231 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3232 keyconf->hw_key_idx = HW_KEY_DEFAULT;
8f9e5645 3233 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
eb3cdfb7 3234
d735f921
SG		 3235 il->_4965.wep_keys[idx].key_size = len;
3236 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
eb3cdfb7 3237
83007196 3238 ret = il4965_static_wepkey_cmd(il, false);
eb3cdfb7 3239
d735f921 3240 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
eb3cdfb7
SG		 3241 return ret;
3242}
3243
e7392364 3244static int
83007196 3245il4965_set_wep_dynamic_key_info(struct il_priv *il,
e7392364 3246 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3247{
3248 unsigned long flags;
3249 __le16 key_flags = 0;
3250 struct il_addsta_cmd sta_cmd;
3251
3252 lockdep_assert_held(&il->mutex);
3253
3254 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3255
3256 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3257 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3258 key_flags &= ~STA_KEY_FLG_INVALID;
3259
3260 if (keyconf->keylen == WEP_KEY_LEN_128)
3261 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3262
b16db50a 3263 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3264 key_flags |= STA_KEY_MULTICAST_MSK;
3265
3266 spin_lock_irqsave(&il->sta_lock, flags);
3267
3268 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3269 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3270 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3271
e7392364 3272 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3273
e7392364
SG		 3274 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3275 keyconf->keylen);
eb3cdfb7 3276
e7392364
SG		 3277 if ((il->stations[sta_id].sta.key.
3278 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3279 il->stations[sta_id].sta.key.key_offset =
e7392364 3280 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3281 /* else, we are overriding an existing key => no need to allocated room
3282 * in uCode. */
3283
3284 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3285 "no space for a new key");
eb3cdfb7
SG		 3286
3287 il->stations[sta_id].sta.key.key_flags = key_flags;
3288 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3289 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3290
3291 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3292 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3293 spin_unlock_irqrestore(&il->sta_lock, flags);
3294
3295 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3296}
3297
e7392364
SG		 3298static int
3299il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
e7392364 3300 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3301{
3302 unsigned long flags;
3303 __le16 key_flags = 0;
3304 struct il_addsta_cmd sta_cmd;
3305
3306 lockdep_assert_held(&il->mutex);
3307
3308 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3309 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3310 key_flags &= ~STA_KEY_FLG_INVALID;
3311
b16db50a 3312 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3313 key_flags |= STA_KEY_MULTICAST_MSK;
3314
3315 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3316
3317 spin_lock_irqsave(&il->sta_lock, flags);
3318 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3319 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3320
e7392364 3321 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3322
e7392364 3323 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3324
e7392364
SG		 3325 if ((il->stations[sta_id].sta.key.
3326 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3327 il->stations[sta_id].sta.key.key_offset =
e7392364 3328 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3329 /* else, we are overriding an existing key => no need to allocated room
3330 * in uCode. */
3331
3332 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3333 "no space for a new key");
eb3cdfb7
SG		 3334
3335 il->stations[sta_id].sta.key.key_flags = key_flags;
3336 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3337 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3338
3339 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3340 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3341 spin_unlock_irqrestore(&il->sta_lock, flags);
3342
3343 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3344}
3345
e7392364
SG		 3346static int
3347il4965_set_tkip_dynamic_key_info(struct il_priv *il,
e7392364 3348 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3349{
3350 unsigned long flags;
3351 int ret = 0;
3352 __le16 key_flags = 0;
3353
3354 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3355 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3356 key_flags &= ~STA_KEY_FLG_INVALID;
3357
b16db50a 3358 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3359 key_flags |= STA_KEY_MULTICAST_MSK;
3360
3361 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3362 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3363
3364 spin_lock_irqsave(&il->sta_lock, flags);
3365
3366 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3367 il->stations[sta_id].keyinfo.keylen = 16;
3368
e7392364
SG		 3369 if ((il->stations[sta_id].sta.key.
3370 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3371 il->stations[sta_id].sta.key.key_offset =
e7392364 3372 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3373 /* else, we are overriding an existing key => no need to allocated room
3374 * in uCode. */
3375
3376 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3377 "no space for a new key");
eb3cdfb7
SG		 3378
3379 il->stations[sta_id].sta.key.key_flags = key_flags;
3380
eb3cdfb7
SG		 3381 /* This copy is acutally not needed: we get the key with each TX */
3382 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3383
3384 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3385
3386 spin_unlock_irqrestore(&il->sta_lock, flags);
3387
3388 return ret;
3389}
3390
e7392364 3391void
83007196
SG		 3392il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3393 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
eb3cdfb7
SG		 3394{
3395 u8 sta_id;
3396 unsigned long flags;
3397 int i;
3398
3399 if (il_scan_cancel(il)) {
3400 /* cancel scan failed, just live w/ bad key and rely
3401 briefly on SW decryption */
3402 return;
3403 }
3404
83007196 3405 sta_id = il_sta_id_or_broadcast(il, sta);
eb3cdfb7
SG		 3406 if (sta_id == IL_INVALID_STATION)
3407 return;
3408
3409 spin_lock_irqsave(&il->sta_lock, flags);
3410
3411 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3412
3413 for (i = 0; i < 5; i++)
3414 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
e7392364 3415 cpu_to_le16(phase1key[i]);
eb3cdfb7
SG		 3416
3417 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3418 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3419
3420 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3421
3422 spin_unlock_irqrestore(&il->sta_lock, flags);
eb3cdfb7
SG		 3423}
3424
e7392364 3425int
83007196 3426il4965_remove_dynamic_key(struct il_priv *il,
e7392364 3427 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3428{
3429 unsigned long flags;
3430 u16 key_flags;
3431 u8 keyidx;
3432 struct il_addsta_cmd sta_cmd;
3433
3434 lockdep_assert_held(&il->mutex);
3435
d735f921 3436 il->_4965.key_mapping_keys--;
eb3cdfb7
SG		 3437
3438 spin_lock_irqsave(&il->sta_lock, flags);
3439 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3440 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3441
e7392364 3442 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
eb3cdfb7
SG		 3443
3444 if (keyconf->keyidx != keyidx) {
3445 /* We need to remove a key with idx different that the one
3446 * in the uCode. This means that the key we need to remove has
3447 * been replaced by another one with different idx.
3448 * Don't do anything and return ok
3449 */
3450 spin_unlock_irqrestore(&il->sta_lock, flags);
3451 return 0;
3452 }
3453
b48d9665 3454 if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) {
e7392364
SG		 3455 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3456 key_flags);
eb3cdfb7
SG		 3457 spin_unlock_irqrestore(&il->sta_lock, flags);
3458 return 0;
3459 }
3460
e7392364
SG		 3461 if (!test_and_clear_bit
3462 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
eb3cdfb7 3463 IL_ERR("idx %d not used in uCode key table.\n",
e7392364
SG		 3464 il->stations[sta_id].sta.key.key_offset);
3465 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3466 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
eb3cdfb7 3467 il->stations[sta_id].sta.key.key_flags =
e7392364 3468 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
b48d9665 3469 il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx;
eb3cdfb7
SG		 3470 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3471 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3472
3473 if (il_is_rfkill(il)) {
e7392364
SG		 3474 D_WEP
3475 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
eb3cdfb7
SG		 3476 spin_unlock_irqrestore(&il->sta_lock, flags);
3477 return 0;
3478 }
3479 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3480 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3481 spin_unlock_irqrestore(&il->sta_lock, flags);
3482
3483 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3484}
3485
e7392364 3486int
83007196
SG		 3487il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3488 u8 sta_id)
eb3cdfb7
SG		 3489{
3490 int ret;
3491
3492 lockdep_assert_held(&il->mutex);
3493
d735f921 3494 il->_4965.key_mapping_keys++;
eb3cdfb7
SG		 3495 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3496
3497 switch (keyconf->cipher) {
3498 case WLAN_CIPHER_SUITE_CCMP:
e7392364 3499 ret =
83007196 3500 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3501 break;
3502 case WLAN_CIPHER_SUITE_TKIP:
e7392364 3503 ret =
83007196 3504 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3505 break;
3506 case WLAN_CIPHER_SUITE_WEP40:
3507 case WLAN_CIPHER_SUITE_WEP104:
83007196 3508 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3509 break;
3510 default:
e7392364
SG		 3511 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3512 keyconf->cipher);
eb3cdfb7
SG		 3513 ret = -EINVAL;
3514 }
3515
e7392364
SG		 3516 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3517 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
eb3cdfb7
SG		 3518
3519 return ret;
3520}
3521
3522/**
3523 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3524 *
3525 * This adds the broadcast station into the driver's station table
3526 * and marks it driver active, so that it will be restored to the
3527 * device at the next best time.
3528 */
e7392364 3529int
83007196 3530il4965_alloc_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3531{
3532 struct il_link_quality_cmd *link_cmd;
3533 unsigned long flags;
3534 u8 sta_id;
3535
3536 spin_lock_irqsave(&il->sta_lock, flags);
83007196 3537 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
eb3cdfb7
SG		 3538 if (sta_id == IL_INVALID_STATION) {
3539 IL_ERR("Unable to prepare broadcast station\n");
3540 spin_unlock_irqrestore(&il->sta_lock, flags);
3541
3542 return -EINVAL;
3543 }
3544
3545 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3546 il->stations[sta_id].used |= IL_STA_BCAST;
3547 spin_unlock_irqrestore(&il->sta_lock, flags);
3548
3549 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3550 if (!link_cmd) {
e7392364
SG		 3551 IL_ERR
3552 ("Unable to initialize rate scaling for bcast station.\n");
eb3cdfb7
SG		 3553 return -ENOMEM;
3554 }
3555
3556 spin_lock_irqsave(&il->sta_lock, flags);
3557 il->stations[sta_id].lq = link_cmd;
3558 spin_unlock_irqrestore(&il->sta_lock, flags);
3559
3560 return 0;
3561}
3562
3563/**
3564 * il4965_update_bcast_station - update broadcast station's LQ command
3565 *
3566 * Only used by iwl4965. Placed here to have all bcast station management
3567 * code together.
3568 */
e7392364 3569static int
83007196 3570il4965_update_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3571{
3572 unsigned long flags;
3573 struct il_link_quality_cmd *link_cmd;
b16db50a 3574 u8 sta_id = il->hw_params.bcast_id;
eb3cdfb7
SG		 3575
3576 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3577 if (!link_cmd) {
1722f8e1 3578 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
eb3cdfb7
SG		 3579 return -ENOMEM;
3580 }
3581
3582 spin_lock_irqsave(&il->sta_lock, flags);
3583 if (il->stations[sta_id].lq)
3584 kfree(il->stations[sta_id].lq);
3585 else
1722f8e1 3586 D_INFO("Bcast sta rate scaling has not been initialized.\n");
eb3cdfb7
SG		 3587 il->stations[sta_id].lq = link_cmd;
3588 spin_unlock_irqrestore(&il->sta_lock, flags);
3589
3590 return 0;
3591}
3592
e7392364
SG		 3593int
3594il4965_update_bcast_stations(struct il_priv *il)
eb3cdfb7 3595{
83007196 3596 return il4965_update_bcast_station(il);
eb3cdfb7
SG		 3597}
3598
3599/**
3600 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3601 */
e7392364
SG		 3602int
3603il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
eb3cdfb7
SG		 3604{
3605 unsigned long flags;
3606 struct il_addsta_cmd sta_cmd;
3607
3608 lockdep_assert_held(&il->mutex);
3609
3610 /* Remove "disable" flag, to enable Tx for this TID */
3611 spin_lock_irqsave(&il->sta_lock, flags);
3612 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3613 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3614 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3615 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3616 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3617 spin_unlock_irqrestore(&il->sta_lock, flags);
3618
3619 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3620}
3621
e7392364
SG		 3622int
3623il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3624 u16 ssn)
eb3cdfb7
SG		 3625{
3626 unsigned long flags;
3627 int sta_id;
3628 struct il_addsta_cmd sta_cmd;
3629
3630 lockdep_assert_held(&il->mutex);
3631
3632 sta_id = il_sta_id(sta);
3633 if (sta_id == IL_INVALID_STATION)
3634 return -ENXIO;
3635
3636 spin_lock_irqsave(&il->sta_lock, flags);
3637 il->stations[sta_id].sta.station_flags_msk = 0;
3638 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
e7392364 3639 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3640 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3641 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3642 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3643 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3644 spin_unlock_irqrestore(&il->sta_lock, flags);
3645
3646 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3647}
3648
e7392364
SG		 3649int
3650il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
eb3cdfb7
SG		 3651{
3652 unsigned long flags;
3653 int sta_id;
3654 struct il_addsta_cmd sta_cmd;
3655
3656 lockdep_assert_held(&il->mutex);
3657
3658 sta_id = il_sta_id(sta);
3659 if (sta_id == IL_INVALID_STATION) {
3660 IL_ERR("Invalid station for AGG tid %d\n", tid);
3661 return -ENXIO;
3662 }
3663
3664 spin_lock_irqsave(&il->sta_lock, flags);
3665 il->stations[sta_id].sta.station_flags_msk = 0;
3666 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
e7392364 3667 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3668 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3669 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3670 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3671 spin_unlock_irqrestore(&il->sta_lock, flags);
3672
3673 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3674}
3675
3676void
3677il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3678{
3679 unsigned long flags;
3680
3681 spin_lock_irqsave(&il->sta_lock, flags);
3682 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3683 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3684 il->stations[sta_id].sta.sta.modify_mask =
e7392364 3685 STA_MODIFY_SLEEP_TX_COUNT_MSK;
eb3cdfb7
SG		 3686 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3687 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364 3688 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
eb3cdfb7
SG		 3689 spin_unlock_irqrestore(&il->sta_lock, flags);
3690
3691}
3692
e7392364
SG		 3693void
3694il4965_update_chain_flags(struct il_priv *il)
be663ab6 3695{
c9363551
SG		 3696 if (il->ops->set_rxon_chain) {
3697 il->ops->set_rxon_chain(il);
c8b03958 3698 if (il->active.rx_chain != il->staging.rx_chain)
83007196 3699 il_commit_rxon(il);
be663ab6
WYG		 3700 }
3701}
3702
e7392364
SG		 3703static void
3704il4965_clear_free_frames(struct il_priv *il)
be663ab6
WYG		 3705{
3706 struct list_head *element;
3707
e7392364 3708 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
be663ab6 3709
46bc8d4b
SG		 3710 while (!list_empty(&il->free_frames)) {
3711 element = il->free_frames.next;
be663ab6 3712 list_del(element);
e2ebc833 3713 kfree(list_entry(element, struct il_frame, list));
46bc8d4b 3714 il->frames_count--;
be663ab6
WYG		 3715 }
3716
46bc8d4b 3717 if (il->frames_count) {
9406f797 3718 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 3719 il->frames_count);
46bc8d4b 3720 il->frames_count = 0;
be663ab6
WYG		 3721 }
3722}
3723
e7392364
SG		 3724static struct il_frame *
3725il4965_get_free_frame(struct il_priv *il)
be663ab6 3726{
e2ebc833 3727 struct il_frame *frame;
be663ab6 3728 struct list_head *element;
46bc8d4b 3729 if (list_empty(&il->free_frames)) {
be663ab6
WYG		 3730 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3731 if (!frame) {
9406f797 3732 IL_ERR("Could not allocate frame!\n");
be663ab6
WYG		 3733 return NULL;
3734 }
3735
46bc8d4b 3736 il->frames_count++;
be663ab6
WYG		 3737 return frame;
3738 }
3739
46bc8d4b 3740 element = il->free_frames.next;
be663ab6 3741 list_del(element);
e2ebc833 3742 return list_entry(element, struct il_frame, list);
be663ab6
WYG		 3743}
3744
e7392364
SG		 3745static void
3746il4965_free_frame(struct il_priv *il, struct il_frame *frame)
be663ab6
WYG		 3747{
3748 memset(frame, 0, sizeof(*frame));
46bc8d4b 3749 list_add(&frame->list, &il->free_frames);
be663ab6
WYG		 3750}
3751
e7392364
SG		 3752static u32
3753il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3754 int left)
be663ab6 3755{
46bc8d4b 3756 lockdep_assert_held(&il->mutex);
be663ab6 3757
46bc8d4b 3758 if (!il->beacon_skb)
be663ab6
WYG		 3759 return 0;
3760
46bc8d4b 3761 if (il->beacon_skb->len > left)
be663ab6
WYG		 3762 return 0;
3763
46bc8d4b 3764 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
be663ab6 3765
46bc8d4b 3766 return il->beacon_skb->len;
be663ab6
WYG		 3767}
3768
3769/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
e7392364
SG		 3770static void
3771il4965_set_beacon_tim(struct il_priv *il,
3772 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3773 u32 frame_size)
be663ab6
WYG		 3774{
3775 u16 tim_idx;
3776 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3777
3778 /*
0c2c8852 3779 * The idx is relative to frame start but we start looking at the
be663ab6
WYG		 3780 * variable-length part of the beacon.
3781 */
3782 tim_idx = mgmt->u.beacon.variable - beacon;
3783
3784 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3785 while ((tim_idx < (frame_size - 2)) &&
e7392364
SG		 3786 (beacon[tim_idx] != WLAN_EID_TIM))
3787 tim_idx += beacon[tim_idx + 1] + 2;
be663ab6
WYG		 3788
3789 /* If TIM field was found, set variables */
3790 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3791 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
e7392364 3792 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
be663ab6 3793 } else
9406f797 3794 IL_WARN("Unable to find TIM Element in beacon\n");
be663ab6
WYG		 3795}
3796
e7392364
SG		 3797static unsigned int
3798il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
be663ab6 3799{
e2ebc833 3800 struct il_tx_beacon_cmd *tx_beacon_cmd;
be663ab6
WYG		 3801 u32 frame_size;
3802 u32 rate_flags;
3803 u32 rate;
3804 /*
3805 * We have to set up the TX command, the TX Beacon command, and the
3806 * beacon contents.
3807 */
3808
46bc8d4b 3809 lockdep_assert_held(&il->mutex);
be663ab6 3810
83007196
SG		 3811 if (!il->beacon_enabled) {
3812 IL_ERR("Trying to build beacon without beaconing enabled\n");
be663ab6
WYG		 3813 return 0;
3814 }
3815
3816 /* Initialize memory */
3817 tx_beacon_cmd = &frame->u.beacon;
3818 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3819
3820 /* Set up TX beacon contents */
e7392364
SG		 3821 frame_size =
3822 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3823 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
be663ab6
WYG		 3824 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3825 return 0;
3826 if (!frame_size)
3827 return 0;
3828
3829 /* Set up TX command fields */
e7392364 3830 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
b16db50a 3831 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
be663ab6 3832 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e7392364
SG		 3833 tx_beacon_cmd->tx.tx_flags =
3834 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3835 TX_CMD_FLG_STA_RATE_MSK;
be663ab6
WYG		 3836
3837 /* Set up TX beacon command fields */
e7392364
SG		 3838 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3839 frame_size);
be663ab6
WYG		 3840
3841 /* Set up packet rate and flags */
83007196 3842 rate = il_get_lowest_plcp(il);
a0c1ef3b 3843 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 3844 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
e2ebc833 3845 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
be663ab6 3846 rate_flags |= RATE_MCS_CCK_MSK;
616107ed 3847 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
be663ab6
WYG		 3848
3849 return sizeof(*tx_beacon_cmd) + frame_size;
3850}
3851
e7392364
SG		 3852int
3853il4965_send_beacon_cmd(struct il_priv *il)
be663ab6 3854{
e2ebc833 3855 struct il_frame *frame;
be663ab6
WYG		 3856 unsigned int frame_size;
3857 int rc;
3858
46bc8d4b 3859 frame = il4965_get_free_frame(il);
be663ab6 3860 if (!frame) {
9406f797 3861 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 3862 "command.\n");
be663ab6
WYG		 3863 return -ENOMEM;
3864 }
3865
46bc8d4b 3866 frame_size = il4965_hw_get_beacon_cmd(il, frame);
be663ab6 3867 if (!frame_size) {
9406f797 3868 IL_ERR("Error configuring the beacon command\n");
46bc8d4b 3869 il4965_free_frame(il, frame);
be663ab6
WYG		 3870 return -EINVAL;
3871 }
3872
e7392364 3873 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
be663ab6 3874
46bc8d4b 3875 il4965_free_frame(il, frame);
be663ab6
WYG		 3876
3877 return rc;
3878}
3879
e7392364
SG		 3880static inline dma_addr_t
3881il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
be663ab6 3882{
e2ebc833 3883 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3884
3885 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3886 if (sizeof(dma_addr_t) > sizeof(u32))
3887 addr |=
e7392364
SG		 3888 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3889 16;
be663ab6
WYG		 3890
3891 return addr;
3892}
3893
e7392364
SG		 3894static inline u16
3895il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
be663ab6 3896{
e2ebc833 3897 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3898
3899 return le16_to_cpu(tb->hi_n_len) >> 4;
3900}
3901
e7392364
SG		 3902static inline void
3903il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
be663ab6 3904{
e2ebc833 3905 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3906 u16 hi_n_len = len << 4;
3907
3908 put_unaligned_le32(addr, &tb->lo);
3909 if (sizeof(dma_addr_t) > sizeof(u32))
3910 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3911
3912 tb->hi_n_len = cpu_to_le16(hi_n_len);
3913
3914 tfd->num_tbs = idx + 1;
3915}
3916
e7392364
SG		 3917static inline u8
3918il4965_tfd_get_num_tbs(struct il_tfd *tfd)
be663ab6
WYG		 3919{
3920 return tfd->num_tbs & 0x1f;
3921}
3922
3923/**
e2ebc833 3924 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
46bc8d4b 3925 * @il - driver ilate data
be663ab6
WYG		 3926 * @txq - tx queue
3927 *
0c2c8852 3928 * Does NOT advance any TFD circular buffer read/write idxes
be663ab6
WYG		 3929 * Does NOT free the TFD itself (which is within circular buffer)
3930 */
e7392364
SG		 3931void
3932il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
be663ab6 3933{
e2ebc833
SG		 3934 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3935 struct il_tfd *tfd;
46bc8d4b 3936 struct pci_dev *dev = il->pci_dev;
0c2c8852 3937 int idx = txq->q.read_ptr;
be663ab6
WYG		 3938 int i;
3939 int num_tbs;
3940
0c2c8852 3941 tfd = &tfd_tmp[idx];
be663ab6
WYG		 3942
3943 /* Sanity check on number of chunks */
e2ebc833 3944 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6 3945
e2ebc833 3946 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3947 IL_ERR("Too many chunks: %i\n", num_tbs);
be663ab6
WYG		 3948 /* @todo issue fatal error, it is quite serious situation */
3949 return;
3950 }
3951
3952 /* Unmap tx_cmd */
3953 if (num_tbs)
e7392364
SG		 3954 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3955 dma_unmap_len(&txq->meta[idx], len),
3956 PCI_DMA_BIDIRECTIONAL);
be663ab6
WYG		 3957
3958 /* Unmap chunks, if any. */
3959 for (i = 1; i < num_tbs; i++)
e2ebc833 3960 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
e7392364
SG		 3961 il4965_tfd_tb_get_len(tfd, i),
3962 PCI_DMA_TODEVICE);
be663ab6
WYG		 3963
3964 /* free SKB */
00ea99e1
SG		 3965 if (txq->skbs) {
3966 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
be663ab6
WYG		 3967
3968 /* can be called from irqs-disabled context */
3969 if (skb) {
3970 dev_kfree_skb_any(skb);
00ea99e1 3971 txq->skbs[txq->q.read_ptr] = NULL;
be663ab6
WYG		 3972 }
3973 }
3974}
3975
e7392364
SG		 3976int
3977il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3978 dma_addr_t addr, u16 len, u8 reset, u8 pad)
be663ab6 3979{
e2ebc833
SG		 3980 struct il_queue *q;
3981 struct il_tfd *tfd, *tfd_tmp;
be663ab6
WYG		 3982 u32 num_tbs;
3983
3984 q = &txq->q;
e2ebc833 3985 tfd_tmp = (struct il_tfd *)txq->tfds;
be663ab6
WYG		 3986 tfd = &tfd_tmp[q->write_ptr];
3987
3988 if (reset)
3989 memset(tfd, 0, sizeof(*tfd));
3990
e2ebc833 3991 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6
WYG		 3992
3993 /* Each TFD can point to a maximum 20 Tx buffers */
e2ebc833 3994 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3995 IL_ERR("Error can not send more than %d chunks\n",
e7392364 3996 IL_NUM_OF_TBS);
be663ab6
WYG		 3997 return -EINVAL;
3998 }
3999
4000 BUG_ON(addr & ~DMA_BIT_MASK(36));
e2ebc833 4001 if (unlikely(addr & ~IL_TX_DMA_MASK))
e7392364 4002 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
be663ab6 4003
e2ebc833 4004 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
be663ab6
WYG		 4005
4006 return 0;
4007}
4008
4009/*
4010 * Tell nic where to find circular buffer of Tx Frame Descriptors for
4011 * given Tx queue, and enable the DMA channel used for that queue.
4012 *
4013 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
4014 * channels supported in hardware.
4015 */
e7392364
SG		 4016int
4017il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
be663ab6
WYG		 4018{
4019 int txq_id = txq->q.id;
4020
4021 /* Circular buffer (TFD queue in DRAM) physical base address */
e7392364 4022 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
be663ab6
WYG		 4023
4024 return 0;
4025}
4026
4027/******************************************************************************
4028 *
4029 * Generic RX handler implementations
4030 *
4031 ******************************************************************************/
e7392364
SG		 4032static void
4033il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4034{
dcae1c64 4035 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4036 struct il_alive_resp *palive;
be663ab6
WYG		 4037 struct delayed_work *pwork;
4038
4039 palive = &pkt->u.alive_frame;
4040
e7392364
SG		 4041 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
4042 palive->is_valid, palive->ver_type, palive->ver_subtype);
be663ab6
WYG		 4043
4044 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 4045 D_INFO("Initialization Alive received.\n");
e7392364 4046 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 4047 sizeof(struct il_init_alive_resp));
46bc8d4b 4048 pwork = &il->init_alive_start;
be663ab6 4049 } else {
58de00a4 4050 D_INFO("Runtime Alive received.\n");
46bc8d4b 4051 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 4052 sizeof(struct il_alive_resp));
46bc8d4b 4053 pwork = &il->alive_start;
be663ab6
WYG		 4054 }
4055
4056 /* We delay the ALIVE response by 5ms to
4057 * give the HW RF Kill time to activate... */
4058 if (palive->is_valid == UCODE_VALID_OK)
e7392364 4059 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
be663ab6 4060 else
9406f797 4061 IL_WARN("uCode did not respond OK.\n");
be663ab6
WYG		 4062}
4063
4064/**
ebf0d90d 4065 * il4965_bg_stats_periodic - Timer callback to queue stats
be663ab6 4066 *
ebf0d90d 4067 * This callback is provided in order to send a stats request.
be663ab6
WYG		 4068 *
4069 * This timer function is continually reset to execute within
527901d0
SG		 4070 * 60 seconds since the last N_STATS was received. We need to
4071 * ensure we receive the stats in order to update the temperature
4072 * used for calibrating the TXPOWER.
be663ab6 4073 */
e7392364
SG		 4074static void
4075il4965_bg_stats_periodic(unsigned long data)
be663ab6 4076{
46bc8d4b 4077 struct il_priv *il = (struct il_priv *)data;
be663ab6 4078
a6766ccd 4079 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4080 return;
4081
4082 /* dont send host command if rf-kill is on */
46bc8d4b 4083 if (!il_is_ready_rf(il))
be663ab6
WYG		 4084 return;
4085
ebf0d90d 4086 il_send_stats_request(il, CMD_ASYNC, false);
be663ab6
WYG		 4087}
4088
e7392364
SG		 4089static void
4090il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4091{
dcae1c64 4092 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4093 struct il4965_beacon_notif *beacon =
e7392364 4094 (struct il4965_beacon_notif *)pkt->u.raw;
d3175167 4095#ifdef CONFIG_IWLEGACY_DEBUG
e2ebc833 4096 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
be663ab6 4097
5bf0dac4 4098 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
e7392364
SG		 4099 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4100 beacon->beacon_notify_hdr.failure_frame,
4101 le32_to_cpu(beacon->ibss_mgr_status),
4102 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
be663ab6 4103#endif
46bc8d4b 4104 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
be663ab6
WYG		 4105}
4106
e7392364
SG		 4107static void
4108il4965_perform_ct_kill_task(struct il_priv *il)
be663ab6
WYG		 4109{
4110 unsigned long flags;
4111
58de00a4 4112 D_POWER("Stop all queues\n");
be663ab6 4113
46bc8d4b
SG		 4114 if (il->mac80211_registered)
4115 ieee80211_stop_queues(il->hw);
be663ab6 4116
841b2cca 4117 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4118 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
841b2cca 4119 _il_rd(il, CSR_UCODE_DRV_GP1);
be663ab6 4120
46bc8d4b 4121 spin_lock_irqsave(&il->reg_lock, flags);
1e0f32a4 4122 if (likely(_il_grab_nic_access(il)))
13882269 4123 _il_release_nic_access(il);
46bc8d4b 4124 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6
WYG		 4125}
4126
4127/* Handle notification from uCode that card's power state is changing
4128 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG		 4129static void
4130il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4131{
dcae1c64 4132 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4133 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 4134 unsigned long status = il->status;
be663ab6 4135
58de00a4 4136 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
e7392364
SG		 4137 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4138 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4139 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
be663ab6 4140
e7392364 4141 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
be663ab6 4142
841b2cca 4143 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4144 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6 4145
e7392364 4146 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4147
4148 if (!(flags & RXON_CARD_DISABLED)) {
841b2cca 4149 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 4150 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0c1a94e2 4151 il_wr(il, HBUS_TARG_MBX_C,
e7392364 4152 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4153 }
4154 }
4155
4156 if (flags & CT_CARD_DISABLED)
46bc8d4b 4157 il4965_perform_ct_kill_task(il);
be663ab6
WYG		 4158
4159 if (flags & HW_CARD_DISABLED)
bc269a8e 4160 set_bit(S_RFKILL, &il->status);
be663ab6 4161 else
bc269a8e 4162 clear_bit(S_RFKILL, &il->status);
be663ab6
WYG		 4163
4164 if (!(flags & RXON_CARD_DISABLED))
46bc8d4b 4165 il_scan_cancel(il);
be663ab6 4166
bc269a8e
SG		 4167 if ((test_bit(S_RFKILL, &status) !=
4168 test_bit(S_RFKILL, &il->status)))
46bc8d4b 4169 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 4170 test_bit(S_RFKILL, &il->status));
be663ab6 4171 else
46bc8d4b 4172 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4173}
4174
4175/**
d0c72347 4176 * il4965_setup_handlers - Initialize Rx handler callbacks
be663ab6
WYG		 4177 *
4178 * Setup the RX handlers for each of the reply types sent from the uCode
4179 * to the host.
4180 *
4181 * This function chains into the hardware specific files for them to setup
4182 * any hardware specific handlers as well.
4183 */
e7392364
SG		 4184static void
4185il4965_setup_handlers(struct il_priv *il)
be663ab6 4186{
6e9848b4
SG		 4187 il->handlers[N_ALIVE] = il4965_hdl_alive;
4188 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 4189 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 4190 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 4191 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 4192 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 4193 il->handlers[N_BEACON] = il4965_hdl_beacon;
be663ab6
WYG		 4194
4195 /*
4196 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG		 4197 * stats request from the host as well as for the periodic
4198 * stats notifications (after received beacons) from the uCode.
be663ab6 4199 */
d2dfb33e
SG		 4200 il->handlers[C_STATS] = il4965_hdl_c_stats;
4201 il->handlers[N_STATS] = il4965_hdl_stats;
be663ab6 4202
46bc8d4b 4203 il_setup_rx_scan_handlers(il);
be663ab6
WYG		 4204
4205 /* status change handler */
e7392364 4206 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
be663ab6 4207
e7392364 4208 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
be663ab6 4209 /* Rx handlers */
6e9848b4
SG		 4210 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4211 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
3dfea27d 4212 il->handlers[N_RX] = il4965_hdl_rx;
be663ab6 4213 /* block ack */
6e9848b4 4214 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
3dfea27d
SG		 4215 /* Tx response */
4216 il->handlers[C_TX] = il4965_hdl_tx;
be663ab6
WYG		 4217}
4218
4219/**
e2ebc833 4220 * il4965_rx_handle - Main entry function for receiving responses from uCode
be663ab6 4221 *
d0c72347 4222 * Uses the il->handlers callback function array to invoke
be663ab6
WYG		 4223 * the appropriate handlers, including command responses,
4224 * frame-received notifications, and other notifications.
4225 */
e7392364
SG		 4226void
4227il4965_rx_handle(struct il_priv *il)
be663ab6 4228{
b73bb5f1 4229 struct il_rx_buf *rxb;
dcae1c64 4230 struct il_rx_pkt *pkt;
46bc8d4b 4231 struct il_rx_queue *rxq = &il->rxq;
be663ab6
WYG		 4232 u32 r, i;
4233 int reclaim;
4234 unsigned long flags;
4235 u8 fill_rx = 0;
4236 u32 count = 8;
4237 int total_empty;
4238
0c2c8852 4239 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
be663ab6 4240 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 4241 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
be663ab6
WYG		 4242 i = rxq->read;
4243
4244 /* Rx interrupt, but nothing sent from uCode */
4245 if (i == r)
58de00a4 4246 D_RX("r = %d, i = %d\n", r, i);
be663ab6
WYG		 4247
4248 /* calculate total frames need to be restock after handling RX */
4249 total_empty = r - rxq->write_actual;
4250 if (total_empty < 0)
4251 total_empty += RX_QUEUE_SIZE;
4252
4253 if (total_empty > (RX_QUEUE_SIZE / 2))
4254 fill_rx = 1;
4255
4256 while (i != r) {
4257 int len;
4258
4259 rxb = rxq->queue[i];
4260
4261 /* If an RXB doesn't have a Rx queue slot associated with it,
4262 * then a bug has been introduced in the queue refilling
4263 * routines -- catch it here */
4264 BUG_ON(rxb == NULL);
4265
4266 rxq->queue[i] = NULL;
4267
46bc8d4b
SG		 4268 pci_unmap_page(il->pci_dev, rxb->page_dma,
4269 PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 4270 PCI_DMA_FROMDEVICE);
4271 pkt = rxb_addr(rxb);
4272
e94a4099 4273 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 4274 len += sizeof(u32); /* account for status word */
be663ab6 4275
8e67427a 4276 reclaim = il_need_reclaim(il, pkt);
be663ab6
WYG		 4277
4278 /* Based on type of command response or notification,
4279 * handle those that need handling via function in
d0c72347
SG		 4280 * handlers table. See il4965_setup_handlers() */
4281 if (il->handlers[pkt->hdr.cmd]) {
e7392364
SG		 4282 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4283 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG		 4284 il->isr_stats.handlers[pkt->hdr.cmd]++;
4285 il->handlers[pkt->hdr.cmd] (il, rxb);
be663ab6
WYG		 4286 } else {
4287 /* No handling needed */
e7392364
SG		 4288 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4289 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
be663ab6
WYG		 4290 }
4291
4292 /*
4293 * XXX: After here, we should always check rxb->page
4294 * against NULL before touching it or its virtual
d0c72347 4295 * memory (pkt). Because some handler might have
be663ab6
WYG		 4296 * already taken or freed the pages.
4297 */
4298
4299 if (reclaim) {
4300 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 4301 * and fire off the (possibly) blocking il_send_cmd()
be663ab6
WYG		 4302 * as we reclaim the driver command queue */
4303 if (rxb->page)
46bc8d4b 4304 il_tx_cmd_complete(il, rxb);
be663ab6 4305 else
9406f797 4306 IL_WARN("Claim null rxb?\n");
be663ab6
WYG		 4307 }
4308
4309 /* Reuse the page if possible. For notification packets and
4310 * SKBs that fail to Rx correctly, add them back into the
4311 * rx_free list for reuse later. */
4312 spin_lock_irqsave(&rxq->lock, flags);
4313 if (rxb->page != NULL) {
e7392364
SG		 4314 rxb->page_dma =
4315 pci_map_page(il->pci_dev, rxb->page, 0,
4316 PAGE_SIZE << il->hw_params.
4317 rx_page_order, PCI_DMA_FROMDEVICE);
96ebbe8d
SG		 4318
4319 if (unlikely(pci_dma_mapping_error(il->pci_dev,
4320 rxb->page_dma))) {
4321 __il_free_pages(il, rxb->page);
4322 rxb->page = NULL;
4323 list_add_tail(&rxb->list, &rxq->rx_used);
4324 } else {
4325 list_add_tail(&rxb->list, &rxq->rx_free);
4326 rxq->free_count++;
4327 }
be663ab6
WYG		 4328 } else
4329 list_add_tail(&rxb->list, &rxq->rx_used);
4330
4331 spin_unlock_irqrestore(&rxq->lock, flags);
4332
4333 i = (i + 1) & RX_QUEUE_MASK;
4334 /* If there are a lot of unused frames,
4335 * restock the Rx queue so ucode wont assert. */
4336 if (fill_rx) {
4337 count++;
4338 if (count >= 8) {
4339 rxq->read = i;
46bc8d4b 4340 il4965_rx_replenish_now(il);
be663ab6
WYG		 4341 count = 0;
4342 }
4343 }
4344 }
4345
4346 /* Backtrack one entry */
4347 rxq->read = i;
4348 if (fill_rx)
46bc8d4b 4349 il4965_rx_replenish_now(il);
be663ab6 4350 else
46bc8d4b 4351 il4965_rx_queue_restock(il);
be663ab6
WYG		 4352}
4353
4354/* call this function to flush any scheduled tasklet */
e7392364
SG		 4355static inline void
4356il4965_synchronize_irq(struct il_priv *il)
be663ab6 4357{
e7392364 4358 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG		 4359 synchronize_irq(il->pci_dev->irq);
4360 tasklet_kill(&il->irq_tasklet);
be663ab6
WYG		 4361}
4362
e7392364
SG		 4363static void
4364il4965_irq_tasklet(struct il_priv *il)
be663ab6
WYG		 4365{
4366 u32 inta, handled = 0;
4367 u32 inta_fh;
4368 unsigned long flags;
4369 u32 i;
d3175167 4370#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4371 u32 inta_mask;
4372#endif
4373
46bc8d4b 4374 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4375
4376 /* Ack/clear/reset pending uCode interrupts.
4377 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4378 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG		 4379 inta = _il_rd(il, CSR_INT);
4380 _il_wr(il, CSR_INT, inta);
be663ab6
WYG		 4381
4382 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4383 * Any new interrupts that happen after this, either while we're
4384 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG		 4385 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4386 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
be663ab6 4387
d3175167 4388#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4389 if (il_get_debug_level(il) & IL_DL_ISR) {
be663ab6 4390 /* just for debug */
841b2cca 4391 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG		 4392 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4393 inta_mask, inta_fh);
be663ab6
WYG		 4394 }
4395#endif
4396
46bc8d4b 4397 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4398
4399 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4400 * atomic, make sure that inta covers all the interrupts that
4401 * we've discovered, even if FH interrupt came in just after
4402 * reading CSR_INT. */
4403 if (inta_fh & CSR49_FH_INT_RX_MASK)
4404 inta |= CSR_INT_BIT_FH_RX;
4405 if (inta_fh & CSR49_FH_INT_TX_MASK)
4406 inta |= CSR_INT_BIT_FH_TX;
4407
4408 /* Now service all interrupt bits discovered above. */
4409 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 4410 IL_ERR("Hardware error detected. Restarting.\n");
be663ab6
WYG		 4411
4412 /* Tell the device to stop sending interrupts */
46bc8d4b 4413 il_disable_interrupts(il);
be663ab6 4414
46bc8d4b
SG		 4415 il->isr_stats.hw++;
4416 il_irq_handle_error(il);
be663ab6
WYG		 4417
4418 handled |= CSR_INT_BIT_HW_ERR;
4419
4420 return;
4421 }
d3175167 4422#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4423 if (il_get_debug_level(il) & (IL_DL_ISR)) {
be663ab6
WYG		 4424 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4425 if (inta & CSR_INT_BIT_SCD) {
58de00a4 4426 D_ISR("Scheduler finished to transmit "
e7392364 4427 "the frame/frames.\n");
46bc8d4b 4428 il->isr_stats.sch++;
be663ab6
WYG		 4429 }
4430
4431 /* Alive notification via Rx interrupt will do the real work */
4432 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 4433 D_ISR("Alive interrupt\n");
46bc8d4b 4434 il->isr_stats.alive++;
be663ab6
WYG		 4435 }
4436 }
4437#endif
4438 /* Safely ignore these bits for debug checks below */
4439 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4440
4441 /* HW RF KILL switch toggled */
4442 if (inta & CSR_INT_BIT_RF_KILL) {
4443 int hw_rf_kill = 0;
c9363551
SG		 4444
4445 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4446 hw_rf_kill = 1;
4447
9406f797 4448 IL_WARN("RF_KILL bit toggled to %s.\n",
e7392364 4449 hw_rf_kill ? "disable radio" : "enable radio");
be663ab6 4450
46bc8d4b 4451 il->isr_stats.rfkill++;
be663ab6
WYG		 4452
4453 /* driver only loads ucode once setting the interface up.
4454 * the driver allows loading the ucode even if the radio
4455 * is killed. Hence update the killswitch state here. The
4456 * rfkill handler will care about restarting if needed.
4457 */
788f7a56
SG		 4458 if (hw_rf_kill) {
4459 set_bit(S_RFKILL, &il->status);
4460 } else {
4461 clear_bit(S_RFKILL, &il->status);
788f7a56 4462 il_force_reset(il, true);
be663ab6 4463 }
b2fcc0ae 4464 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
be663ab6
WYG		 4465
4466 handled |= CSR_INT_BIT_RF_KILL;
4467 }
4468
4469 /* Chip got too hot and stopped itself */
4470 if (inta & CSR_INT_BIT_CT_KILL) {
9406f797 4471 IL_ERR("Microcode CT kill error detected.\n");
46bc8d4b 4472 il->isr_stats.ctkill++;
be663ab6
WYG		 4473 handled |= CSR_INT_BIT_CT_KILL;
4474 }
4475
4476 /* Error detected by uCode */
4477 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG		 4478 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4479 inta);
46bc8d4b
SG		 4480 il->isr_stats.sw++;
4481 il_irq_handle_error(il);
be663ab6
WYG		 4482 handled |= CSR_INT_BIT_SW_ERR;
4483 }
4484
4485 /*
4486 * uCode wakes up after power-down sleep.
4487 * Tell device about any new tx or host commands enqueued,
4488 * and about any Rx buffers made available while asleep.
4489 */
4490 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 4491 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG		 4492 il_rx_queue_update_write_ptr(il, &il->rxq);
4493 for (i = 0; i < il->hw_params.max_txq_num; i++)
4494 il_txq_update_write_ptr(il, &il->txq[i]);
4495 il->isr_stats.wakeup++;
be663ab6
WYG		 4496 handled |= CSR_INT_BIT_WAKEUP;
4497 }
4498
4499 /* All uCode command responses, including Tx command responses,
4500 * Rx "responses" (frame-received notification), and other
4501 * notifications from uCode come through here*/
4502 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG		 4503 il4965_rx_handle(il);
4504 il->isr_stats.rx++;
be663ab6
WYG		 4505 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4506 }
4507
4508 /* This "Tx" DMA channel is used only for loading uCode */
4509 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 4510 D_ISR("uCode load interrupt\n");
46bc8d4b 4511 il->isr_stats.tx++;
be663ab6
WYG		 4512 handled |= CSR_INT_BIT_FH_TX;
4513 /* Wake up uCode load routine, now that load is complete */
46bc8d4b
SG		 4514 il->ucode_write_complete = 1;
4515 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4516 }
4517
4518 if (inta & ~handled) {
9406f797 4519 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 4520 il->isr_stats.unhandled++;
be663ab6
WYG		 4521 }
4522
46bc8d4b 4523 if (inta & ~(il->inta_mask)) {
9406f797 4524 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 4525 inta & ~il->inta_mask);
9a95b370 4526 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
be663ab6
WYG		 4527 }
4528
4529 /* Re-enable all interrupts */
93fd74e3 4530 /* only Re-enable if disabled by irq */
a6766ccd 4531 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 4532 il_enable_interrupts(il);
a078a1fd
SG		 4533 /* Re-enable RF_KILL if it occurred */
4534 else if (handled & CSR_INT_BIT_RF_KILL)
46bc8d4b 4535 il_enable_rfkill_int(il);
be663ab6 4536
d3175167 4537#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4538 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG		 4539 inta = _il_rd(il, CSR_INT);
4540 inta_mask = _il_rd(il, CSR_INT_MASK);
4541 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
e7392364
SG		 4542 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4543 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
be663ab6
WYG		 4544 }
4545#endif
4546}
4547
4548/*****************************************************************************
4549 *
4550 * sysfs attributes
4551 *
4552 *****************************************************************************/
4553
d3175167 4554#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4555
4556/*
4557 * The following adds a new attribute to the sysfs representation
4558 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4559 * used for controlling the debug level.
4560 *
4561 * See the level definitions in iwl for details.
4562 *
4563 * The debug_level being managed using sysfs below is a per device debug
4564 * level that is used instead of the global debug level if it (the per
4565 * device debug level) is set.
4566 */
e7392364
SG		 4567static ssize_t
4568il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4569 char *buf)
be663ab6 4570{
46bc8d4b
SG		 4571 struct il_priv *il = dev_get_drvdata(d);
4572 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
be663ab6 4573}
e7392364
SG		 4574
4575static ssize_t
4576il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4577 const char *buf, size_t count)
be663ab6 4578{
46bc8d4b 4579 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4580 unsigned long val;
4581 int ret;
4582
27d7f477 4583 ret = kstrtoul(buf, 0, &val);
be663ab6 4584 if (ret)
9406f797 4585 IL_ERR("%s is not in hex or decimal form.\n", buf);
288f9954 4586 else
46bc8d4b 4587 il->debug_level = val;
288f9954 4588
be663ab6
WYG		 4589 return strnlen(buf, count);
4590}
4591
e7392364
SG		 4592static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4593 il4965_store_debug_level);
be663ab6 4594
d3175167 4595#endif /* CONFIG_IWLEGACY_DEBUG */
be663ab6 4596
e7392364
SG		 4597static ssize_t
4598il4965_show_temperature(struct device *d, struct device_attribute *attr,
4599 char *buf)
be663ab6 4600{
46bc8d4b 4601 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4602
46bc8d4b 4603 if (!il_is_alive(il))
be663ab6
WYG		 4604 return -EAGAIN;
4605
46bc8d4b 4606 return sprintf(buf, "%d\n", il->temperature);
be663ab6
WYG		 4607}
4608
e2ebc833 4609static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
be663ab6 4610
e7392364
SG		 4611static ssize_t
4612il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
be663ab6 4613{
46bc8d4b 4614 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4615
46bc8d4b 4616 if (!il_is_ready_rf(il))
be663ab6
WYG		 4617 return sprintf(buf, "off\n");
4618 else
46bc8d4b 4619 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
be663ab6
WYG		 4620}
4621
e7392364
SG		 4622static ssize_t
4623il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4624 const char *buf, size_t count)
be663ab6 4625{
46bc8d4b 4626 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4627 unsigned long val;
4628 int ret;
4629
27d7f477 4630 ret = kstrtoul(buf, 10, &val);
be663ab6 4631 if (ret)
9406f797 4632 IL_INFO("%s is not in decimal form.\n", buf);
be663ab6 4633 else {
46bc8d4b 4634 ret = il_set_tx_power(il, val, false);
be663ab6 4635 if (ret)
595a23fe 4636 IL_ERR("failed setting tx power (0x%08x).\n", ret);
be663ab6
WYG		 4637 else
4638 ret = count;
4639 }
4640 return ret;
4641}
4642
e7392364
SG		 4643static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4644 il4965_store_tx_power);
be663ab6 4645
e2ebc833 4646static struct attribute *il_sysfs_entries[] = {
be663ab6
WYG		 4647 &dev_attr_temperature.attr,
4648 &dev_attr_tx_power.attr,
d3175167 4649#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4650 &dev_attr_debug_level.attr,
4651#endif
4652 NULL
4653};
4654
e2ebc833 4655static struct attribute_group il_attribute_group = {
be663ab6 4656 .name = NULL, /* put in device directory */
e2ebc833 4657 .attrs = il_sysfs_entries,
be663ab6
WYG		 4658};
4659
4660/******************************************************************************
4661 *
4662 * uCode download functions
4663 *
4664 ******************************************************************************/
4665
e7392364
SG		 4666static void
4667il4965_dealloc_ucode_pci(struct il_priv *il)
be663ab6 4668{
46bc8d4b
SG		 4669 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4670 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4671 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4672 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4673 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4674 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6
WYG		 4675}
4676
e7392364
SG		 4677static void
4678il4965_nic_start(struct il_priv *il)
be663ab6
WYG		 4679{
4680 /* Remove all resets to allow NIC to operate */
841b2cca 4681 _il_wr(il, CSR_RESET, 0);
be663ab6
WYG		 4682}
4683
e2ebc833 4684static void il4965_ucode_callback(const struct firmware *ucode_raw,
e7392364
SG		 4685 void *context);
4686static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
be663ab6 4687
e7392364
SG		 4688static int __must_check
4689il4965_request_firmware(struct il_priv *il, bool first)
be663ab6 4690{
46bc8d4b 4691 const char *name_pre = il->cfg->fw_name_pre;
be663ab6
WYG		 4692 char tag[8];
4693
4694 if (first) {
0c2c8852
SG		 4695 il->fw_idx = il->cfg->ucode_api_max;
4696 sprintf(tag, "%d", il->fw_idx);
be663ab6 4697 } else {
0c2c8852
SG		 4698 il->fw_idx--;
4699 sprintf(tag, "%d", il->fw_idx);
be663ab6
WYG		 4700 }
4701
0c2c8852 4702 if (il->fw_idx < il->cfg->ucode_api_min) {
9406f797 4703 IL_ERR("no suitable firmware found!\n");
be663ab6
WYG		 4704 return -ENOENT;
4705 }
4706
46bc8d4b 4707 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
be663ab6 4708
e7392364 4709 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
be663ab6 4710
46bc8d4b
SG		 4711 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4712 &il->pci_dev->dev, GFP_KERNEL, il,
e2ebc833 4713 il4965_ucode_callback);
be663ab6
WYG		 4714}
4715
e2ebc833 4716struct il4965_firmware_pieces {
be663ab6
WYG		 4717 const void *inst, *data, *init, *init_data, *boot;
4718 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4719};
4720
e7392364
SG		 4721static int
4722il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4723 struct il4965_firmware_pieces *pieces)
be663ab6 4724{
e2ebc833 4725 struct il_ucode_header *ucode = (void *)ucode_raw->data;
be663ab6
WYG		 4726 u32 api_ver, hdr_size;
4727 const u8 *src;
4728
46bc8d4b
SG		 4729 il->ucode_ver = le32_to_cpu(ucode->ver);
4730 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4731
4732 switch (api_ver) {
4733 default:
4734 case 0:
4735 case 1:
4736 case 2:
4737 hdr_size = 24;
4738 if (ucode_raw->size < hdr_size) {
9406f797 4739 IL_ERR("File size too small!\n");
be663ab6
WYG		 4740 return -EINVAL;
4741 }
4742 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4743 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4744 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
e7392364 4745 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
be663ab6
WYG		 4746 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4747 src = ucode->v1.data;
4748 break;
4749 }
4750
4751 /* Verify size of file vs. image size info in file's header */
e7392364
SG		 4752 if (ucode_raw->size !=
4753 hdr_size + pieces->inst_size + pieces->data_size +
4754 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
be663ab6 4755
e7392364
SG		 4756 IL_ERR("uCode file size %d does not match expected size\n",
4757 (int)ucode_raw->size);
be663ab6
WYG		 4758 return -EINVAL;
4759 }
4760
4761 pieces->inst = src;
4762 src += pieces->inst_size;
4763 pieces->data = src;
4764 src += pieces->data_size;
4765 pieces->init = src;
4766 src += pieces->init_size;
4767 pieces->init_data = src;
4768 src += pieces->init_data_size;
4769 pieces->boot = src;
4770 src += pieces->boot_size;
4771
4772 return 0;
4773}
4774
4775/**
e2ebc833 4776 * il4965_ucode_callback - callback when firmware was loaded
be663ab6
WYG		 4777 *
4778 * If loaded successfully, copies the firmware into buffers
4779 * for the card to fetch (via DMA).
4780 */
4781static void
e2ebc833 4782il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
be663ab6 4783{
46bc8d4b 4784 struct il_priv *il = context;
e2ebc833 4785 struct il_ucode_header *ucode;
be663ab6 4786 int err;
e2ebc833 4787 struct il4965_firmware_pieces pieces;
46bc8d4b
SG		 4788 const unsigned int api_max = il->cfg->ucode_api_max;
4789 const unsigned int api_min = il->cfg->ucode_api_min;
be663ab6
WYG		 4790 u32 api_ver;
4791
4792 u32 max_probe_length = 200;
4793 u32 standard_phy_calibration_size =
e7392364 4794 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
be663ab6
WYG		 4795
4796 memset(&pieces, 0, sizeof(pieces));
4797
4798 if (!ucode_raw) {
0c2c8852 4799 if (il->fw_idx <= il->cfg->ucode_api_max)
e7392364
SG		 4800 IL_ERR("request for firmware file '%s' failed.\n",
4801 il->firmware_name);
be663ab6
WYG		 4802 goto try_again;
4803 }
4804
e7392364
SG		 4805 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4806 ucode_raw->size);
be663ab6
WYG		 4807
4808 /* Make sure that we got at least the API version number */
4809 if (ucode_raw->size < 4) {
9406f797 4810 IL_ERR("File size way too small!\n");
be663ab6
WYG		 4811 goto try_again;
4812 }
4813
4814 /* Data from ucode file: header followed by uCode images */
e2ebc833 4815 ucode = (struct il_ucode_header *)ucode_raw->data;
be663ab6 4816
46bc8d4b 4817 err = il4965_load_firmware(il, ucode_raw, &pieces);
be663ab6
WYG		 4818
4819 if (err)
4820 goto try_again;
4821
46bc8d4b 4822 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4823
4824 /*
4825 * api_ver should match the api version forming part of the
4826 * firmware filename ... but we don't check for that and only rely
4827 * on the API version read from firmware header from here on forward
4828 */
4829 if (api_ver < api_min || api_ver > api_max) {
e7392364
SG		 4830 IL_ERR("Driver unable to support your firmware API. "
4831 "Driver supports v%u, firmware is v%u.\n", api_max,
4832 api_ver);
be663ab6
WYG		 4833 goto try_again;
4834 }
4835
4836 if (api_ver != api_max)
e7392364
SG		 4837 IL_ERR("Firmware has old API version. Expected v%u, "
4838 "got v%u. New firmware can be obtained "
4839 "from http://www.intellinuxwireless.org.\n", api_max,
4840 api_ver);
be663ab6 4841
9406f797 4842 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG		 4843 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4844 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
be663ab6 4845
e7392364
SG		 4846 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4847 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4848 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
46bc8d4b 4849 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6
WYG		 4850
4851 /*
4852 * For any of the failures below (before allocating pci memory)
4853 * we will try to load a version with a smaller API -- maybe the
4854 * user just got a corrupted version of the latest API.
4855 */
4856
e7392364
SG		 4857 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4858 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4859 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4860 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4861 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4862 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
be663ab6
WYG		 4863
4864 /* Verify that uCode images will fit in card's SRAM */
46bc8d4b 4865 if (pieces.inst_size > il->hw_params.max_inst_size) {
9406f797 4866 IL_ERR("uCode instr len %Zd too large to fit in\n",
e7392364 4867 pieces.inst_size);
be663ab6
WYG		 4868 goto try_again;
4869 }
4870
46bc8d4b 4871 if (pieces.data_size > il->hw_params.max_data_size) {
9406f797 4872 IL_ERR("uCode data len %Zd too large to fit in\n",
e7392364 4873 pieces.data_size);
be663ab6
WYG		 4874 goto try_again;
4875 }
4876
46bc8d4b 4877 if (pieces.init_size > il->hw_params.max_inst_size) {
9406f797 4878 IL_ERR("uCode init instr len %Zd too large to fit in\n",
e7392364 4879 pieces.init_size);
be663ab6
WYG		 4880 goto try_again;
4881 }
4882
46bc8d4b 4883 if (pieces.init_data_size > il->hw_params.max_data_size) {
9406f797 4884 IL_ERR("uCode init data len %Zd too large to fit in\n",
e7392364 4885 pieces.init_data_size);
be663ab6
WYG		 4886 goto try_again;
4887 }
4888
46bc8d4b 4889 if (pieces.boot_size > il->hw_params.max_bsm_size) {
9406f797 4890 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
e7392364 4891 pieces.boot_size);
be663ab6
WYG		 4892 goto try_again;
4893 }
4894
4895 /* Allocate ucode buffers for card's bus-master loading ... */
4896
4897 /* Runtime instructions and 2 copies of data:
4898 * 1) unmodified from disk
4899 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG		 4900 il->ucode_code.len = pieces.inst_size;
4901 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
be663ab6 4902
46bc8d4b
SG		 4903 il->ucode_data.len = pieces.data_size;
4904 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
be663ab6 4905
46bc8d4b
SG		 4906 il->ucode_data_backup.len = pieces.data_size;
4907 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
be663ab6 4908
46bc8d4b
SG		 4909 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4910 !il->ucode_data_backup.v_addr)
be663ab6
WYG		 4911 goto err_pci_alloc;
4912
4913 /* Initialization instructions and data */
4914 if (pieces.init_size && pieces.init_data_size) {
46bc8d4b
SG		 4915 il->ucode_init.len = pieces.init_size;
4916 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
be663ab6 4917
46bc8d4b
SG		 4918 il->ucode_init_data.len = pieces.init_data_size;
4919 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
be663ab6 4920
46bc8d4b 4921 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
be663ab6
WYG		 4922 goto err_pci_alloc;
4923 }
4924
4925 /* Bootstrap (instructions only, no data) */
4926 if (pieces.boot_size) {
46bc8d4b
SG		 4927 il->ucode_boot.len = pieces.boot_size;
4928 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6 4929
46bc8d4b 4930 if (!il->ucode_boot.v_addr)
be663ab6
WYG		 4931 goto err_pci_alloc;
4932 }
4933
4934 /* Now that we can no longer fail, copy information */
4935
46bc8d4b 4936 il->sta_key_max_num = STA_KEY_MAX_NUM;
be663ab6
WYG		 4937
4938 /* Copy images into buffers for card's bus-master reads ... */
4939
4940 /* Runtime instructions (first block of data in file) */
58de00a4 4941 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
e7392364 4942 pieces.inst_size);
46bc8d4b 4943 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
be663ab6 4944
58de00a4 4945 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 4946 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
be663ab6
WYG		 4947
4948 /*
4949 * Runtime data
e2ebc833 4950 * NOTE: Copy into backup buffer will be done in il_up()
be663ab6 4951 */
58de00a4 4952 D_INFO("Copying (but not loading) uCode data len %Zd\n",
e7392364 4953 pieces.data_size);
46bc8d4b
SG		 4954 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4955 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
be663ab6
WYG		 4956
4957 /* Initialization instructions */
4958 if (pieces.init_size) {
e7392364
SG		 4959 D_INFO("Copying (but not loading) init instr len %Zd\n",
4960 pieces.init_size);
46bc8d4b 4961 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
be663ab6
WYG		 4962 }
4963
4964 /* Initialization data */
4965 if (pieces.init_data_size) {
e7392364
SG		 4966 D_INFO("Copying (but not loading) init data len %Zd\n",
4967 pieces.init_data_size);
46bc8d4b 4968 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
be663ab6
WYG		 4969 pieces.init_data_size);
4970 }
4971
4972 /* Bootstrap instructions */
58de00a4 4973 D_INFO("Copying (but not loading) boot instr len %Zd\n",
e7392364 4974 pieces.boot_size);
46bc8d4b 4975 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
be663ab6
WYG		 4976
4977 /*
4978 * figure out the offset of chain noise reset and gain commands
4979 * base on the size of standard phy calibration commands table size
4980 */
46bc8d4b 4981 il->_4965.phy_calib_chain_noise_reset_cmd =
e7392364 4982 standard_phy_calibration_size;
46bc8d4b 4983 il->_4965.phy_calib_chain_noise_gain_cmd =
e7392364 4984 standard_phy_calibration_size + 1;
be663ab6
WYG		 4985
4986 /**************************************************
4987 * This is still part of probe() in a sense...
4988 *
4989 * 9. Setup and register with mac80211 and debugfs
4990 **************************************************/
46bc8d4b 4991 err = il4965_mac_setup_register(il, max_probe_length);
be663ab6
WYG		 4992 if (err)
4993 goto out_unbind;
4994
46bc8d4b 4995 err = il_dbgfs_register(il, DRV_NAME);
be663ab6 4996 if (err)
e7392364
SG		 4997 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4998 err);
be663ab6 4999
e7392364 5000 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
be663ab6 5001 if (err) {
9406f797 5002 IL_ERR("failed to create sysfs device attributes\n");
be663ab6
WYG		 5003 goto out_unbind;
5004 }
5005
5006 /* We have our copies now, allow OS release its copies */
5007 release_firmware(ucode_raw);
46bc8d4b 5008 complete(&il->_4965.firmware_loading_complete);
be663ab6
WYG		 5009 return;
5010
e7392364 5011try_again:
be663ab6 5012 /* try next, if any */
46bc8d4b 5013 if (il4965_request_firmware(il, false))
be663ab6
WYG		 5014 goto out_unbind;
5015 release_firmware(ucode_raw);
5016 return;
5017
e7392364 5018err_pci_alloc:
9406f797 5019 IL_ERR("failed to allocate pci memory\n");
46bc8d4b 5020 il4965_dealloc_ucode_pci(il);
e7392364 5021out_unbind:
46bc8d4b
SG		 5022 complete(&il->_4965.firmware_loading_complete);
5023 device_release_driver(&il->pci_dev->dev);
be663ab6
WYG		 5024 release_firmware(ucode_raw);
5025}
5026
e7392364 5027static const char *const desc_lookup_text[] = {
be663ab6
WYG		 5028 "OK",
5029 "FAIL",
5030 "BAD_PARAM",
5031 "BAD_CHECKSUM",
5032 "NMI_INTERRUPT_WDG",
5033 "SYSASSERT",
5034 "FATAL_ERROR",
5035 "BAD_COMMAND",
5036 "HW_ERROR_TUNE_LOCK",
5037 "HW_ERROR_TEMPERATURE",
5038 "ILLEGAL_CHAN_FREQ",
3b98c7f4 5039 "VCC_NOT_STBL",
9a95b370 5040 "FH49_ERROR",
be663ab6
WYG		 5041 "NMI_INTERRUPT_HOST",
5042 "NMI_INTERRUPT_ACTION_PT",
5043 "NMI_INTERRUPT_UNKNOWN",
5044 "UCODE_VERSION_MISMATCH",
5045 "HW_ERROR_ABS_LOCK",
5046 "HW_ERROR_CAL_LOCK_FAIL",
5047 "NMI_INTERRUPT_INST_ACTION_PT",
5048 "NMI_INTERRUPT_DATA_ACTION_PT",
5049 "NMI_TRM_HW_ER",
5050 "NMI_INTERRUPT_TRM",
861d9c3f 5051 "NMI_INTERRUPT_BREAK_POINT",
be663ab6
WYG		 5052 "DEBUG_0",
5053 "DEBUG_1",
5054 "DEBUG_2",
5055 "DEBUG_3",
5056};
5057
e7392364
SG		 5058static struct {
5059 char *name;
5060 u8 num;
5061} advanced_lookup[] = {
5062 {
5063 "NMI_INTERRUPT_WDG", 0x34}, {
5064 "SYSASSERT", 0x35}, {
5065 "UCODE_VERSION_MISMATCH", 0x37}, {
5066 "BAD_COMMAND", 0x38}, {
5067 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5068 "FATAL_ERROR", 0x3D}, {
5069 "NMI_TRM_HW_ERR", 0x46}, {
5070 "NMI_INTERRUPT_TRM", 0x4C}, {
5071 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5072 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5073 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5074 "NMI_INTERRUPT_HOST", 0x66}, {
5075 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5076 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5077 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5078"ADVANCED_SYSASSERT", 0},};
5079
5080static const char *
5081il4965_desc_lookup(u32 num)
be663ab6
WYG		 5082{
5083 int i;
5084 int max = ARRAY_SIZE(desc_lookup_text);
5085
5086 if (num < max)
5087 return desc_lookup_text[num];
5088
5089 max = ARRAY_SIZE(advanced_lookup) - 1;
5090 for (i = 0; i < max; i++) {
5091 if (advanced_lookup[i].num == num)
5092 break;
5093 }
5094 return advanced_lookup[i].name;
5095}
5096
5097#define ERROR_START_OFFSET (1 * sizeof(u32))
5098#define ERROR_ELEM_SIZE (7 * sizeof(u32))
5099
e7392364
SG		 5100void
5101il4965_dump_nic_error_log(struct il_priv *il)
be663ab6
WYG		 5102{
5103 u32 data2, line;
5104 u32 desc, time, count, base, data1;
5105 u32 blink1, blink2, ilink1, ilink2;
5106 u32 pc, hcmd;
5107
1722f8e1 5108 if (il->ucode_type == UCODE_INIT)
46bc8d4b 5109 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
1722f8e1 5110 else
46bc8d4b 5111 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
be663ab6 5112
1600b875 5113 if (!il->ops->is_valid_rtc_data_addr(base)) {
e7392364
SG		 5114 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5115 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
be663ab6
WYG		 5116 return;
5117 }
5118
46bc8d4b 5119 count = il_read_targ_mem(il, base);
be663ab6
WYG		 5120
5121 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 5122 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 5123 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
46bc8d4b
SG		 5124 }
5125
5126 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5127 il->isr_stats.err_code = desc;
5128 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5129 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5130 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5131 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5132 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5133 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5134 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5135 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5136 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5137 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5138
9406f797 5139 IL_ERR("Desc Time "
e7392364 5140 "data1 data2 line\n");
9406f797 5141 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
e7392364 5142 il4965_desc_lookup(desc), desc, time, data1, data2, line);
9406f797 5143 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
e7392364
SG		 5144 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5145 blink2, ilink1, ilink2, hcmd);
be663ab6
WYG		 5146}
5147
e7392364
SG		 5148static void
5149il4965_rf_kill_ct_config(struct il_priv *il)
be663ab6 5150{
e2ebc833 5151 struct il_ct_kill_config cmd;
be663ab6
WYG		 5152 unsigned long flags;
5153 int ret = 0;
5154
46bc8d4b 5155 spin_lock_irqsave(&il->lock, flags);
841b2cca 5156 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 5157 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
46bc8d4b 5158 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5159
5160 cmd.critical_temperature_R =
e7392364 5161 cpu_to_le32(il->hw_params.ct_kill_threshold);
be663ab6 5162
e7392364 5163 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
be663ab6 5164 if (ret)
4d69c752 5165 IL_ERR("C_CT_KILL_CONFIG failed\n");
be663ab6 5166 else
e7392364
SG		 5167 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5168 "critical temperature is %d\n",
5169 il->hw_params.ct_kill_threshold);
be663ab6
WYG		 5170}
5171
5172static const s8 default_queue_to_tx_fifo[] = {
e2ebc833
SG		 5173 IL_TX_FIFO_VO,
5174 IL_TX_FIFO_VI,
5175 IL_TX_FIFO_BE,
5176 IL_TX_FIFO_BK,
d3175167 5177 IL49_CMD_FIFO_NUM,
e2ebc833
SG		 5178 IL_TX_FIFO_UNUSED,
5179 IL_TX_FIFO_UNUSED,
be663ab6
WYG		 5180};
5181
e53aac42
SG		 5182#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5183
e7392364
SG		 5184static int
5185il4965_alive_notify(struct il_priv *il)
be663ab6
WYG		 5186{
5187 u32 a;
5188 unsigned long flags;
5189 int i, chan;
5190 u32 reg_val;
5191
46bc8d4b 5192 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5193
5194 /* Clear 4965's internal Tx Scheduler data base */
e7392364 5195 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
d3175167
SG		 5196 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5197 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
46bc8d4b 5198 il_write_targ_mem(il, a, 0);
d3175167 5199 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
46bc8d4b 5200 il_write_targ_mem(il, a, 0);
e7392364
SG		 5201 for (;
5202 a <
5203 il->scd_base_addr +
5204 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5205 a += 4)
46bc8d4b 5206 il_write_targ_mem(il, a, 0);
be663ab6
WYG		 5207
5208 /* Tel 4965 where to find Tx byte count tables */
e7392364 5209 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
be663ab6
WYG		 5210
5211 /* Enable DMA channel */
e7392364
SG		 5212 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5213 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5214 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5215 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
be663ab6
WYG		 5216
5217 /* Update FH chicken bits */
9a95b370
SG		 5218 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5219 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
e7392364 5220 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
be663ab6
WYG		 5221
5222 /* Disable chain mode for all queues */
d3175167 5223 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
be663ab6
WYG		 5224
5225 /* Initialize each Tx queue (including the command queue) */
46bc8d4b 5226 for (i = 0; i < il->hw_params.max_txq_num; i++) {
be663ab6 5227
0c2c8852 5228 /* TFD circular buffer read/write idxes */
d3175167 5229 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
0c1a94e2 5230 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
be663ab6
WYG		 5231
5232 /* Max Tx Window size for Scheduler-ACK mode */
e7392364
SG		 5233 il_write_targ_mem(il,
5234 il->scd_base_addr +
5235 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5236 (SCD_WIN_SIZE <<
5237 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5238 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
be663ab6
WYG		 5239
5240 /* Frame limit */
e7392364
SG		 5241 il_write_targ_mem(il,
5242 il->scd_base_addr +
5243 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5244 sizeof(u32),
5245 (SCD_FRAME_LIMIT <<
5246 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5247 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
be663ab6
WYG		 5248
5249 }
d3175167 5250 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
e7392364 5251 (1 << il->hw_params.max_txq_num) - 1);
be663ab6
WYG		 5252
5253 /* Activate all Tx DMA/FIFO channels */
46bc8d4b 5254 il4965_txq_set_sched(il, IL_MASK(0, 6));
be663ab6 5255
46bc8d4b 5256 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
be663ab6
WYG		 5257
5258 /* make sure all queue are not stopped */
46bc8d4b 5259 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
be663ab6 5260 for (i = 0; i < 4; i++)
46bc8d4b 5261 atomic_set(&il->queue_stop_count[i], 0);
be663ab6
WYG		 5262
5263 /* reset to 0 to enable all the queue first */
46bc8d4b 5264 il->txq_ctx_active_msk = 0;
be663ab6
WYG		 5265 /* Map each Tx/cmd queue to its corresponding fifo */
5266 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5267
5268 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5269 int ac = default_queue_to_tx_fifo[i];
5270
46bc8d4b 5271 il_txq_ctx_activate(il, i);
be663ab6 5272
e2ebc833 5273 if (ac == IL_TX_FIFO_UNUSED)
be663ab6
WYG		 5274 continue;
5275
46bc8d4b 5276 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
be663ab6
WYG		 5277 }
5278
46bc8d4b 5279 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5280
5281 return 0;
5282}
5283
5284/**
4d69c752 5285 * il4965_alive_start - called after N_ALIVE notification received
be663ab6 5286 * from protocol/runtime uCode (initialization uCode's
e2ebc833 5287 * Alive gets handled by il_init_alive_start()).
be663ab6 5288 */
e7392364
SG		 5289static void
5290il4965_alive_start(struct il_priv *il)
be663ab6
WYG		 5291{
5292 int ret = 0;
be663ab6 5293
58de00a4 5294 D_INFO("Runtime Alive received.\n");
be663ab6 5295
46bc8d4b 5296 if (il->card_alive.is_valid != UCODE_VALID_OK) {
be663ab6
WYG		 5297 /* We had an error bringing up the hardware, so take it
5298 * all the way back down so we can try again */
58de00a4 5299 D_INFO("Alive failed.\n");
be663ab6
WYG		 5300 goto restart;
5301 }
5302
5303 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5304 * This is a paranoid check, because we would not have gotten the
5305 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 5306 if (il4965_verify_ucode(il)) {
be663ab6
WYG		 5307 /* Runtime instruction load was bad;
5308 * take it all the way back down so we can try again */
58de00a4 5309 D_INFO("Bad runtime uCode load.\n");
be663ab6
WYG		 5310 goto restart;
5311 }
5312
46bc8d4b 5313 ret = il4965_alive_notify(il);
be663ab6 5314 if (ret) {
e7392364 5315 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
be663ab6
WYG		 5316 goto restart;
5317 }
5318
be663ab6 5319 /* After the ALIVE response, we can send host commands to the uCode */
a6766ccd 5320 set_bit(S_ALIVE, &il->status);
be663ab6
WYG		 5321
5322 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 5323 il_setup_watchdog(il);
be663ab6 5324
46bc8d4b 5325 if (il_is_rfkill(il))
be663ab6
WYG		 5326 return;
5327
46bc8d4b 5328 ieee80211_wake_queues(il->hw);
be663ab6 5329
2eb05816 5330 il->active_rate = RATES_MASK;
be663ab6 5331
eca396d7
SG		 5332 il_power_update_mode(il, true);
5333 D_INFO("Updated power mode\n");
5334
c8b03958 5335 if (il_is_associated(il)) {
e2ebc833 5336 struct il_rxon_cmd *active_rxon =
c8b03958 5337 (struct il_rxon_cmd *)&il->active;
be663ab6 5338 /* apply any changes in staging */
c8b03958 5339 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5340 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5341 } else {
be663ab6 5342 /* Initialize our rx_config data */
83007196 5343 il_connection_init_rx_config(il);
be663ab6 5344
c9363551
SG		 5345 if (il->ops->set_rxon_chain)
5346 il->ops->set_rxon_chain(il);
be663ab6
WYG		 5347 }
5348
5349 /* Configure bluetooth coexistence if enabled */
46bc8d4b 5350 il_send_bt_config(il);
be663ab6 5351
46bc8d4b 5352 il4965_reset_run_time_calib(il);
be663ab6 5353
a6766ccd 5354 set_bit(S_READY, &il->status);
be663ab6
WYG		 5355
5356 /* Configure the adapter for unassociated operation */
83007196 5357 il_commit_rxon(il);
be663ab6
WYG		 5358
5359 /* At this point, the NIC is initialized and operational */
46bc8d4b 5360 il4965_rf_kill_ct_config(il);
be663ab6 5361
58de00a4 5362 D_INFO("ALIVE processing complete.\n");
46bc8d4b 5363 wake_up(&il->wait_command_queue);
be663ab6 5364
be663ab6
WYG		 5365 return;
5366
e7392364 5367restart:
46bc8d4b 5368 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 5369}
5370
46bc8d4b 5371static void il4965_cancel_deferred_work(struct il_priv *il);
be663ab6 5372
e7392364
SG		 5373static void
5374__il4965_down(struct il_priv *il)
be663ab6
WYG		 5375{
5376 unsigned long flags;
ab42b404 5377 int exit_pending;
be663ab6 5378
58de00a4 5379 D_INFO(DRV_NAME " is going down\n");
be663ab6 5380
46bc8d4b 5381 il_scan_cancel_timeout(il, 200);
be663ab6 5382
a6766ccd 5383 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
be663ab6 5384
a6766ccd 5385 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
be663ab6 5386 * to prevent rearm timer */
46bc8d4b 5387 del_timer_sync(&il->watchdog);
be663ab6 5388
83007196 5389 il_clear_ucode_stations(il);
d735f921
SG		 5390
5391 /* FIXME: race conditions ? */
5392 spin_lock_irq(&il->sta_lock);
5393 /*
5394 * Remove all key information that is not stored as part
5395 * of station information since mac80211 may not have had
5396 * a chance to remove all the keys. When device is
5397 * reconfigured by mac80211 after an error all keys will
5398 * be reconfigured.
5399 */
5400 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5401 il->_4965.key_mapping_keys = 0;
5402 spin_unlock_irq(&il->sta_lock);
5403
46bc8d4b
SG		 5404 il_dealloc_bcast_stations(il);
5405 il_clear_driver_stations(il);
be663ab6
WYG		 5406
5407 /* Unblock any waiting calls */
46bc8d4b 5408 wake_up_all(&il->wait_command_queue);
be663ab6
WYG		 5409
5410 /* Wipe out the EXIT_PENDING status bit if we are not actually
5411 * exiting the module */
5412 if (!exit_pending)
a6766ccd 5413 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5414
5415 /* stop and reset the on-board processor */
841b2cca 5416 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6
WYG		 5417
5418 /* tell the device to stop sending interrupts */
46bc8d4b
SG		 5419 spin_lock_irqsave(&il->lock, flags);
5420 il_disable_interrupts(il);
5421 spin_unlock_irqrestore(&il->lock, flags);
5422 il4965_synchronize_irq(il);
be663ab6 5423
46bc8d4b
SG		 5424 if (il->mac80211_registered)
5425 ieee80211_stop_queues(il->hw);
be663ab6 5426
e2ebc833 5427 /* If we have not previously called il_init() then
be663ab6 5428 * clear all bits but the RF Kill bit and return */
46bc8d4b 5429 if (!il_is_init(il)) {
e7392364 5430 il->status =
bc269a8e 5431 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0 5432 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
e7392364 5433 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6
WYG		 5434 goto exit;
5435 }
5436
5437 /* ...otherwise clear out all the status bits but the RF Kill
5438 * bit and continue taking the NIC down. */
e7392364 5439 il->status &=
bc269a8e 5440 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0
SG		 5441 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5442 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
e7392364 5443 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6 5444
775ed8ab
SG		 5445 /*
5446 * We disabled and synchronized interrupt, and priv->mutex is taken, so
5447 * here is the only thread which will program device registers, but
5448 * still have lockdep assertions, so we are taking reg_lock.
5449 */
5450 spin_lock_irq(&il->reg_lock);
5451 /* FIXME: il_grab_nic_access if rfkill is off ? */
5452
46bc8d4b
SG		 5453 il4965_txq_ctx_stop(il);
5454 il4965_rxq_stop(il);
be663ab6 5455 /* Power-down device's busmaster DMA clocks */
775ed8ab 5456 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6 5457 udelay(5);
be663ab6 5458 /* Make sure (redundant) we've released our request to stay awake */
775ed8ab 5459 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
be663ab6 5460 /* Stop the device, and put it in low power state */
775ed8ab
SG		 5461 _il_apm_stop(il);
5462
5463 spin_unlock_irq(&il->reg_lock);
be663ab6 5464
775ed8ab 5465 il4965_txq_ctx_unmap(il);
e7392364 5466exit:
46bc8d4b 5467 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
be663ab6 5468
46bc8d4b
SG		 5469 dev_kfree_skb(il->beacon_skb);
5470 il->beacon_skb = NULL;
be663ab6
WYG		 5471
5472 /* clear out any free frames */
46bc8d4b 5473 il4965_clear_free_frames(il);
be663ab6
WYG		 5474}
5475
e7392364
SG		 5476static void
5477il4965_down(struct il_priv *il)
be663ab6 5478{
46bc8d4b
SG		 5479 mutex_lock(&il->mutex);
5480 __il4965_down(il);
5481 mutex_unlock(&il->mutex);
be663ab6 5482
46bc8d4b 5483 il4965_cancel_deferred_work(il);
be663ab6
WYG		 5484}
5485
be663ab6 5486
71e0c6c2 5487static void
e7392364 5488il4965_set_hw_ready(struct il_priv *il)
be663ab6 5489{
71e0c6c2 5490 int ret;
be663ab6 5491
46bc8d4b 5492 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 5493 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
be663ab6
WYG		 5494
5495 /* See if we got it */
71e0c6c2
SG		 5496 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5497 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5498 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5499 100);
5500 if (ret >= 0)
46bc8d4b 5501 il->hw_ready = true;
be663ab6 5502
71e0c6c2 5503 D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not");
be663ab6
WYG		 5504}
5505
71e0c6c2 5506static void
e7392364 5507il4965_prepare_card_hw(struct il_priv *il)
be663ab6 5508{
71e0c6c2 5509 int ret;
be663ab6 5510
71e0c6c2 5511 il->hw_ready = false;
be663ab6 5512
71e0c6c2 5513 il4965_set_hw_ready(il);
46bc8d4b 5514 if (il->hw_ready)
71e0c6c2 5515 return;
be663ab6
WYG		 5516
5517 /* If HW is not ready, prepare the conditions to check again */
e7392364 5518 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
be663ab6 5519
e7392364
SG		 5520 ret =
5521 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5522 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5523 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
be663ab6
WYG		 5524
5525 /* HW should be ready by now, check again. */
5526 if (ret != -ETIMEDOUT)
46bc8d4b 5527 il4965_set_hw_ready(il);
be663ab6
WYG		 5528}
5529
5530#define MAX_HW_RESTARTS 5
5531
e7392364
SG		 5532static int
5533__il4965_up(struct il_priv *il)
be663ab6 5534{
be663ab6
WYG		 5535 int i;
5536 int ret;
5537
a6766ccd 5538 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 5539 IL_WARN("Exit pending; will not bring the NIC up\n");
be663ab6
WYG		 5540 return -EIO;
5541 }
5542
46bc8d4b 5543 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 5544 IL_ERR("ucode not available for device bringup\n");
be663ab6
WYG		 5545 return -EIO;
5546 }
5547
83007196 5548 ret = il4965_alloc_bcast_station(il);
17d6e557
SG		 5549 if (ret) {
5550 il_dealloc_bcast_stations(il);
5551 return ret;
be663ab6
WYG		 5552 }
5553
46bc8d4b 5554 il4965_prepare_card_hw(il);
46bc8d4b 5555 if (!il->hw_ready) {
71e0c6c2 5556 IL_ERR("HW not ready\n");
be663ab6
WYG		 5557 return -EIO;
5558 }
5559
5560 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 5561 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 5562 clear_bit(S_RFKILL, &il->status);
3976b451 5563 else {
bc269a8e 5564 set_bit(S_RFKILL, &il->status);
46bc8d4b 5565 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
be663ab6 5566
3976b451 5567 il_enable_rfkill_int(il);
9406f797 5568 IL_WARN("Radio disabled by HW RF Kill switch\n");
be663ab6
WYG		 5569 return 0;
5570 }
5571
841b2cca 5572 _il_wr(il, CSR_INT, 0xFFFFFFFF);
be663ab6 5573
e2ebc833 5574 /* must be initialised before il_hw_nic_init */
46bc8d4b 5575 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
be663ab6 5576
46bc8d4b 5577 ret = il4965_hw_nic_init(il);
be663ab6 5578 if (ret) {
9406f797 5579 IL_ERR("Unable to init nic\n");
be663ab6
WYG		 5580 return ret;
5581 }
5582
5583 /* make sure rfkill handshake bits are cleared */
841b2cca 5584 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 5585 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6
WYG		 5586
5587 /* clear (again), then enable host interrupts */
841b2cca 5588 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5589 il_enable_interrupts(il);
be663ab6
WYG		 5590
5591 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG		 5592 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5593 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
be663ab6
WYG		 5594
5595 /* Copy original ucode data image from disk into backup cache.
5596 * This will be used to initialize the on-board processor's
5597 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG		 5598 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5599 il->ucode_data.len);
be663ab6
WYG		 5600
5601 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5602
5603 /* load bootstrap state machine,
5604 * load bootstrap program into processor's memory,
5605 * prepare to load the "initialize" uCode */
1600b875 5606 ret = il->ops->load_ucode(il);
be663ab6
WYG		 5607
5608 if (ret) {
e7392364 5609 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
be663ab6
WYG		 5610 continue;
5611 }
5612
5613 /* start card; "initialize" will load runtime ucode */
46bc8d4b 5614 il4965_nic_start(il);
be663ab6 5615
58de00a4 5616 D_INFO(DRV_NAME " is coming up\n");
be663ab6
WYG		 5617
5618 return 0;
5619 }
5620
a6766ccd 5621 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 5622 __il4965_down(il);
a6766ccd 5623 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5624
5625 /* tried to restart and config the device for as long as our
5626 * patience could withstand */
9406f797 5627 IL_ERR("Unable to initialize device after %d attempts.\n", i);
be663ab6
WYG		 5628 return -EIO;
5629}
5630
be663ab6
WYG		 5631/*****************************************************************************
5632 *
5633 * Workqueue callbacks
5634 *
5635 *****************************************************************************/
5636
e7392364
SG		 5637static void
5638il4965_bg_init_alive_start(struct work_struct *data)
be663ab6 5639{
46bc8d4b 5640 struct il_priv *il =
e2ebc833 5641 container_of(data, struct il_priv, init_alive_start.work);
be663ab6 5642
46bc8d4b 5643 mutex_lock(&il->mutex);
a6766ccd 5644 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5645 goto out;
be663ab6 5646
1600b875 5647 il->ops->init_alive_start(il);
28a6e577 5648out:
46bc8d4b 5649 mutex_unlock(&il->mutex);
be663ab6
WYG		 5650}
5651
e7392364
SG		 5652static void
5653il4965_bg_alive_start(struct work_struct *data)
be663ab6 5654{
46bc8d4b 5655 struct il_priv *il =
e2ebc833 5656 container_of(data, struct il_priv, alive_start.work);
be663ab6 5657
46bc8d4b 5658 mutex_lock(&il->mutex);
a6766ccd 5659 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5660 goto out;
be663ab6 5661
46bc8d4b 5662 il4965_alive_start(il);
28a6e577 5663out:
46bc8d4b 5664 mutex_unlock(&il->mutex);
be663ab6
WYG		 5665}
5666
e7392364
SG		 5667static void
5668il4965_bg_run_time_calib_work(struct work_struct *work)
be663ab6 5669{
46bc8d4b 5670 struct il_priv *il = container_of(work, struct il_priv,
e7392364 5671 run_time_calib_work);
be663ab6 5672
46bc8d4b 5673 mutex_lock(&il->mutex);
be663ab6 5674
a6766ccd
SG		 5675 if (test_bit(S_EXIT_PENDING, &il->status) ||
5676 test_bit(S_SCANNING, &il->status)) {
46bc8d4b 5677 mutex_unlock(&il->mutex);
be663ab6
WYG		 5678 return;
5679 }
5680
46bc8d4b 5681 if (il->start_calib) {
e7392364
SG		 5682 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5683 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
be663ab6
WYG		 5684 }
5685
46bc8d4b 5686 mutex_unlock(&il->mutex);
be663ab6
WYG		 5687}
5688
e7392364
SG		 5689static void
5690il4965_bg_restart(struct work_struct *data)
be663ab6 5691{
46bc8d4b 5692 struct il_priv *il = container_of(data, struct il_priv, restart);
be663ab6 5693
a6766ccd 5694 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5695 return;
5696
a6766ccd 5697 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 5698 mutex_lock(&il->mutex);
46bc8d4b 5699 il->is_open = 0;
be663ab6 5700
46bc8d4b 5701 __il4965_down(il);
be663ab6 5702
46bc8d4b
SG		 5703 mutex_unlock(&il->mutex);
5704 il4965_cancel_deferred_work(il);
5705 ieee80211_restart_hw(il->hw);
be663ab6 5706 } else {
46bc8d4b 5707 il4965_down(il);
be663ab6 5708
46bc8d4b 5709 mutex_lock(&il->mutex);
a6766ccd 5710 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 5711 mutex_unlock(&il->mutex);
be663ab6 5712 return;
28a6e577 5713 }
be663ab6 5714
46bc8d4b
SG		 5715 __il4965_up(il);
5716 mutex_unlock(&il->mutex);
be663ab6
WYG		 5717 }
5718}
5719
e7392364
SG		 5720static void
5721il4965_bg_rx_replenish(struct work_struct *data)
be663ab6 5722{
e7392364 5723 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
be663ab6 5724
a6766ccd 5725 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5726 return;
5727
46bc8d4b
SG		 5728 mutex_lock(&il->mutex);
5729 il4965_rx_replenish(il);
5730 mutex_unlock(&il->mutex);
be663ab6
WYG		 5731}
5732
5733/*****************************************************************************
5734 *
5735 * mac80211 entry point functions
5736 *
5737 *****************************************************************************/
5738
5739#define UCODE_READY_TIMEOUT (4 * HZ)
5740
5741/*
5742 * Not a mac80211 entry point function, but it fits in with all the
5743 * other mac80211 functions grouped here.
5744 */
e7392364
SG		 5745static int
5746il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
be663ab6
WYG		 5747{
5748 int ret;
46bc8d4b 5749 struct ieee80211_hw *hw = il->hw;
be663ab6
WYG		 5750
5751 hw->rate_control_algorithm = "iwl-4965-rs";
5752
5753 /* Tell mac80211 our characteristics */
e7392364
SG		 5754 hw->flags =
5755 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
c65dd147 5756 IEEE80211_HW_NEED_DTIM_BEFORE_ASSOC | IEEE80211_HW_SPECTRUM_MGMT |
d5346171
SG		 5757 IEEE80211_HW_REPORTS_TX_ACK_STATUS | IEEE80211_HW_SUPPORTS_PS |
5758 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
46bc8d4b 5759 if (il->cfg->sku & IL_SKU_N)
0d8614b4
EP		 5760 hw->wiphy->features |= NL80211_FEATURE_DYNAMIC_SMPS |
5761 NL80211_FEATURE_STATIC_SMPS;
be663ab6 5762
e2ebc833
SG		 5763 hw->sta_data_size = sizeof(struct il_station_priv);
5764 hw->vif_data_size = sizeof(struct il_vif_priv);
be663ab6 5765
8c9c48d5
SG		 5766 hw->wiphy->interface_modes =
5767 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
be663ab6 5768
a2f73b6c
LR		 5769 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5770 hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
5771 REGULATORY_DISABLE_BEACON_HINTS;
be663ab6
WYG		 5772
5773 /*
5774 * For now, disable PS by default because it affects
5775 * RX performance significantly.
5776 */
5777 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5778
5779 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5780 /* we create the 802.11 header and a zero-length SSID element */
5781 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5782
5783 /* Default value; 4 EDCA QOS priorities */
5784 hw->queues = 4;
5785
e2ebc833 5786 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
be663ab6 5787
46bc8d4b
SG		 5788 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5789 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 5790 &il->bands[IEEE80211_BAND_2GHZ];
46bc8d4b
SG		 5791 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5792 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 5793 &il->bands[IEEE80211_BAND_5GHZ];
be663ab6 5794
46bc8d4b 5795 il_leds_init(il);
be663ab6 5796
46bc8d4b 5797 ret = ieee80211_register_hw(il->hw);
be663ab6 5798 if (ret) {
9406f797 5799 IL_ERR("Failed to register hw (error %d)\n", ret);
be663ab6
WYG		 5800 return ret;
5801 }
46bc8d4b 5802 il->mac80211_registered = 1;
be663ab6
WYG		 5803
5804 return 0;
5805}
5806
e7392364
SG		 5807int
5808il4965_mac_start(struct ieee80211_hw *hw)
be663ab6 5809{
46bc8d4b 5810 struct il_priv *il = hw->priv;
be663ab6
WYG		 5811 int ret;
5812
58de00a4 5813 D_MAC80211("enter\n");
be663ab6
WYG		 5814
5815 /* we should be verifying the device is ready to be opened */
46bc8d4b
SG		 5816 mutex_lock(&il->mutex);
5817 ret = __il4965_up(il);
5818 mutex_unlock(&il->mutex);
be663ab6
WYG		 5819
5820 if (ret)
5821 return ret;
5822
46bc8d4b 5823 if (il_is_rfkill(il))
be663ab6
WYG		 5824 goto out;
5825
58de00a4 5826 D_INFO("Start UP work done.\n");
be663ab6
WYG		 5827
5828 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5829 * mac80211 will not be run successfully. */
46bc8d4b 5830 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 5831 test_bit(S_READY, &il->status),
5832 UCODE_READY_TIMEOUT);
be663ab6 5833 if (!ret) {
a6766ccd 5834 if (!test_bit(S_READY, &il->status)) {
9406f797 5835 IL_ERR("START_ALIVE timeout after %dms.\n",
be663ab6
WYG		 5836 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5837 return -ETIMEDOUT;
5838 }
5839 }
5840
46bc8d4b 5841 il4965_led_enable(il);
be663ab6
WYG		 5842
5843out:
46bc8d4b 5844 il->is_open = 1;
58de00a4 5845 D_MAC80211("leave\n");
be663ab6
WYG		 5846 return 0;
5847}
5848
e7392364
SG		 5849void
5850il4965_mac_stop(struct ieee80211_hw *hw)
be663ab6 5851{
46bc8d4b 5852 struct il_priv *il = hw->priv;
be663ab6 5853
58de00a4 5854 D_MAC80211("enter\n");
be663ab6 5855
46bc8d4b 5856 if (!il->is_open)
be663ab6
WYG		 5857 return;
5858
46bc8d4b 5859 il->is_open = 0;
be663ab6 5860
46bc8d4b 5861 il4965_down(il);
be663ab6 5862
46bc8d4b 5863 flush_workqueue(il->workqueue);
be663ab6 5864
a078a1fd
SG		 5865 /* User space software may expect getting rfkill changes
5866 * even if interface is down */
841b2cca 5867 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5868 il_enable_rfkill_int(il);
be663ab6 5869
58de00a4 5870 D_MAC80211("leave\n");
be663ab6
WYG		 5871}
5872
e7392364 5873void
36323f81
TH		 5874il4965_mac_tx(struct ieee80211_hw *hw,
5875 struct ieee80211_tx_control *control,
5876 struct sk_buff *skb)
be663ab6 5877{
46bc8d4b 5878 struct il_priv *il = hw->priv;
be663ab6 5879
58de00a4 5880 D_MACDUMP("enter\n");
be663ab6 5881
58de00a4 5882 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 5883 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
be663ab6 5884
36323f81 5885 if (il4965_tx_skb(il, control->sta, skb))
be663ab6
WYG		 5886 dev_kfree_skb_any(skb);
5887
58de00a4 5888 D_MACDUMP("leave\n");
be663ab6
WYG		 5889}
5890
e7392364
SG		 5891void
5892il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5893 struct ieee80211_key_conf *keyconf,
5894 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
be663ab6 5895{
46bc8d4b 5896 struct il_priv *il = hw->priv;
be663ab6 5897
58de00a4 5898 D_MAC80211("enter\n");
be663ab6 5899
83007196 5900 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
be663ab6 5901
58de00a4 5902 D_MAC80211("leave\n");
be663ab6
WYG		 5903}
5904
e7392364
SG		 5905int
5906il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5907 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5908 struct ieee80211_key_conf *key)
be663ab6 5909{
46bc8d4b 5910 struct il_priv *il = hw->priv;
be663ab6
WYG		 5911 int ret;
5912 u8 sta_id;
5913 bool is_default_wep_key = false;
5914
58de00a4 5915 D_MAC80211("enter\n");
be663ab6 5916
46bc8d4b 5917 if (il->cfg->mod_params->sw_crypto) {
58de00a4 5918 D_MAC80211("leave - hwcrypto disabled\n");
be663ab6
WYG		 5919 return -EOPNOTSUPP;
5920 }
5921
d7fbcada
SG		 5922 /*
5923 * To support IBSS RSN, don't program group keys in IBSS, the
5924 * hardware will then not attempt to decrypt the frames.
5925 */
5926 if (vif->type == NL80211_IFTYPE_ADHOC &&
5927 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
5928 D_MAC80211("leave - ad-hoc group key\n");
5929 return -EOPNOTSUPP;
5930 }
5931
83007196 5932 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 5933 if (sta_id == IL_INVALID_STATION)
be663ab6
WYG		 5934 return -EINVAL;
5935
46bc8d4b
SG		 5936 mutex_lock(&il->mutex);
5937 il_scan_cancel_timeout(il, 100);
be663ab6
WYG		 5938
5939 /*
5940 * If we are getting WEP group key and we didn't receive any key mapping
5941 * so far, we are in legacy wep mode (group key only), otherwise we are
5942 * in 1X mode.
5943 * In legacy wep mode, we use another host command to the uCode.
5944 */
5945 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
e7392364 5946 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
be663ab6 5947 if (cmd == SET_KEY)
d735f921 5948 is_default_wep_key = !il->_4965.key_mapping_keys;
be663ab6
WYG		 5949 else
5950 is_default_wep_key =
e7392364 5951 (key->hw_key_idx == HW_KEY_DEFAULT);
be663ab6
WYG		 5952 }
5953
5954 switch (cmd) {
5955 case SET_KEY:
5956 if (is_default_wep_key)
83007196 5957 ret = il4965_set_default_wep_key(il, key);
be663ab6 5958 else
83007196 5959 ret = il4965_set_dynamic_key(il, key, sta_id);
be663ab6 5960
58de00a4 5961 D_MAC80211("enable hwcrypto key\n");
be663ab6
WYG		 5962 break;
5963 case DISABLE_KEY:
5964 if (is_default_wep_key)
83007196 5965 ret = il4965_remove_default_wep_key(il, key);
be663ab6 5966 else
83007196 5967 ret = il4965_remove_dynamic_key(il, key, sta_id);
be663ab6 5968
58de00a4 5969 D_MAC80211("disable hwcrypto key\n");
be663ab6
WYG		 5970 break;
5971 default:
5972 ret = -EINVAL;
5973 }
5974
46bc8d4b 5975 mutex_unlock(&il->mutex);
58de00a4 5976 D_MAC80211("leave\n");
be663ab6
WYG		 5977
5978 return ret;
5979}
5980
e7392364
SG		 5981int
5982il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5983 enum ieee80211_ampdu_mlme_action action,
5984 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5985 u8 buf_size)
be663ab6 5986{
46bc8d4b 5987 struct il_priv *il = hw->priv;
be663ab6
WYG		 5988 int ret = -EINVAL;
5989
e7392364 5990 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
be663ab6 5991
46bc8d4b 5992 if (!(il->cfg->sku & IL_SKU_N))
be663ab6
WYG		 5993 return -EACCES;
5994
46bc8d4b 5995 mutex_lock(&il->mutex);
be663ab6
WYG		 5996
5997 switch (action) {
5998 case IEEE80211_AMPDU_RX_START:
58de00a4 5999 D_HT("start Rx\n");
46bc8d4b 6000 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
be663ab6
WYG		 6001 break;
6002 case IEEE80211_AMPDU_RX_STOP:
58de00a4 6003 D_HT("stop Rx\n");
46bc8d4b 6004 ret = il4965_sta_rx_agg_stop(il, sta, tid);
a6766ccd 6005 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 6006 ret = 0;
6007 break;
6008 case IEEE80211_AMPDU_TX_START:
58de00a4 6009 D_HT("start Tx\n");
46bc8d4b 6010 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
be663ab6 6011 break;
18b559d5
JB		 6012 case IEEE80211_AMPDU_TX_STOP_CONT:
6013 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6014 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
58de00a4 6015 D_HT("stop Tx\n");
46bc8d4b 6016 ret = il4965_tx_agg_stop(il, vif, sta, tid);
a6766ccd 6017 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 6018 ret = 0;
6019 break;
6020 case IEEE80211_AMPDU_TX_OPERATIONAL:
6021 ret = 0;
6022 break;
6023 }
46bc8d4b 6024 mutex_unlock(&il->mutex);
be663ab6
WYG		 6025
6026 return ret;
6027}
6028
e7392364
SG		 6029int
6030il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6031 struct ieee80211_sta *sta)
be663ab6 6032{
46bc8d4b 6033 struct il_priv *il = hw->priv;
e2ebc833 6034 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
be663ab6
WYG		 6035 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
6036 int ret;
6037 u8 sta_id;
6038
e7392364 6039 D_INFO("received request to add station %pM\n", sta->addr);
46bc8d4b 6040 mutex_lock(&il->mutex);
e7392364 6041 D_INFO("proceeding to add station %pM\n", sta->addr);
e2ebc833 6042 sta_priv->common.sta_id = IL_INVALID_STATION;
be663ab6
WYG		 6043
6044 atomic_set(&sta_priv->pending_frames, 0);
6045
e7392364 6046 ret =
83007196 6047 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
be663ab6 6048 if (ret) {
e7392364 6049 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
be663ab6 6050 /* Should we return success if return code is EEXIST ? */
46bc8d4b 6051 mutex_unlock(&il->mutex);
be663ab6
WYG		 6052 return ret;
6053 }
6054
6055 sta_priv->common.sta_id = sta_id;
6056
6057 /* Initialize rate scaling */
e7392364 6058 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG		 6059 il4965_rs_rate_init(il, sta, sta_id);
6060 mutex_unlock(&il->mutex);
be663ab6
WYG		 6061
6062 return 0;
6063}
6064
e7392364 6065void
0f791eb4 6066il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
e7392364 6067 struct ieee80211_channel_switch *ch_switch)
be663ab6 6068{
46bc8d4b 6069 struct il_priv *il = hw->priv;
e2ebc833 6070 const struct il_channel_info *ch_info;
be663ab6 6071 struct ieee80211_conf *conf = &hw->conf;
85220d71 6072 struct ieee80211_channel *channel = ch_switch->chandef.chan;
46bc8d4b 6073 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6 6074 u16 ch;
be663ab6 6075
58de00a4 6076 D_MAC80211("enter\n");
be663ab6 6077
46bc8d4b 6078 mutex_lock(&il->mutex);
28a6e577 6079
46bc8d4b 6080 if (il_is_rfkill(il))
28a6e577 6081 goto out;
be663ab6 6082
a6766ccd
SG		 6083 if (test_bit(S_EXIT_PENDING, &il->status) ||
6084 test_bit(S_SCANNING, &il->status) ||
6085 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
28a6e577 6086 goto out;
be663ab6 6087
c8b03958 6088 if (!il_is_associated(il))
28a6e577 6089 goto out;
be663ab6 6090
1600b875 6091 if (!il->ops->set_channel_switch)
7f1f9742 6092 goto out;
be663ab6 6093
7f1f9742 6094 ch = channel->hw_value;
c8b03958 6095 if (le16_to_cpu(il->active.channel) == ch)
7f1f9742
SG		 6096 goto out;
6097
46bc8d4b 6098 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 6099 if (!il_is_channel_valid(ch_info)) {
58de00a4 6100 D_MAC80211("invalid channel\n");
7f1f9742
SG		 6101 goto out;
6102 }
6103
46bc8d4b 6104 spin_lock_irq(&il->lock);
7f1f9742 6105
46bc8d4b 6106 il->current_ht_config.smps = conf->smps_mode;
7f1f9742
SG		 6107
6108 /* Configure HT40 channels */
85220d71
JB		 6109 switch (cfg80211_get_chandef_type(&ch_switch->chandef)) {
6110 case NL80211_CHAN_NO_HT:
6111 case NL80211_CHAN_HT20:
1c03c462 6112 il->ht.is_40mhz = false;
85220d71
JB		 6113 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
6114 break;
6115 case NL80211_CHAN_HT40MINUS:
6116 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
6117 il->ht.is_40mhz = true;
6118 break;
6119 case NL80211_CHAN_HT40PLUS:
6120 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
6121 il->ht.is_40mhz = true;
6122 break;
6123 }
7f1f9742 6124
c8b03958
SG		 6125 if ((le16_to_cpu(il->staging.channel) != ch))
6126 il->staging.flags = 0;
7f1f9742 6127
83007196 6128 il_set_rxon_channel(il, channel);
46bc8d4b 6129 il_set_rxon_ht(il, ht_conf);
83007196 6130 il_set_flags_for_band(il, channel->band, il->vif);
7f1f9742 6131
46bc8d4b 6132 spin_unlock_irq(&il->lock);
7f1f9742 6133
46bc8d4b 6134 il_set_rate(il);
7f1f9742
SG		 6135 /*
6136 * at this point, staging_rxon has the
6137 * configuration for channel switch
6138 */
a6766ccd 6139 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6140 il->switch_channel = cpu_to_le16(ch);
1600b875 6141 if (il->ops->set_channel_switch(il, ch_switch)) {
a6766ccd 6142 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6143 il->switch_channel = 0;
83007196 6144 ieee80211_chswitch_done(il->vif, false);
be663ab6 6145 }
7f1f9742 6146
be663ab6 6147out:
46bc8d4b 6148 mutex_unlock(&il->mutex);
58de00a4 6149 D_MAC80211("leave\n");
be663ab6
WYG		 6150}
6151
e7392364
SG		 6152void
6153il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6154 unsigned int *total_flags, u64 multicast)
be663ab6 6155{
46bc8d4b 6156 struct il_priv *il = hw->priv;
be663ab6 6157 __le32 filter_or = 0, filter_nand = 0;
be663ab6
WYG		 6158
6159#define CHK(test, flag) do { \
6160 if (*total_flags & (test)) \
6161 filter_or |= (flag); \
6162 else \
6163 filter_nand |= (flag); \
6164 } while (0)
6165
e7392364
SG		 6166 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6167 *total_flags);
be663ab6
WYG		 6168
6169 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
6170 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6171 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6172 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6173
6174#undef CHK
6175
46bc8d4b 6176 mutex_lock(&il->mutex);
be663ab6 6177
c8b03958
SG		 6178 il->staging.filter_flags &= ~filter_nand;
6179 il->staging.filter_flags |= filter_or;
be663ab6 6180
17d6e557
SG		 6181 /*
6182 * Not committing directly because hardware can perform a scan,
6183 * but we'll eventually commit the filter flags change anyway.
6184 */
be663ab6 6185
46bc8d4b 6186 mutex_unlock(&il->mutex);
be663ab6
WYG		 6187
6188 /*
6189 * Receiving all multicast frames is always enabled by the
e2ebc833 6190 * default flags setup in il_connection_init_rx_config()
be663ab6
WYG		 6191 * since we currently do not support programming multicast
6192 * filters into the device.
6193 */
e7392364
SG		 6194 *total_flags &=
6195 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
6196 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
be663ab6
WYG		 6197}
6198
6199/*****************************************************************************
6200 *
6201 * driver setup and teardown
6202 *
6203 *****************************************************************************/
6204
e7392364
SG		 6205static void
6206il4965_bg_txpower_work(struct work_struct *work)
be663ab6 6207{
46bc8d4b 6208 struct il_priv *il = container_of(work, struct il_priv,
e7392364 6209 txpower_work);
be663ab6 6210
46bc8d4b 6211 mutex_lock(&il->mutex);
f325757a 6212
be663ab6 6213 /* If a scan happened to start before we got here
ebf0d90d 6214 * then just return; the stats notification will
be663ab6
WYG		 6215 * kick off another scheduled work to compensate for
6216 * any temperature delta we missed here. */
a6766ccd
SG		 6217 if (test_bit(S_EXIT_PENDING, &il->status) ||
6218 test_bit(S_SCANNING, &il->status))
f325757a 6219 goto out;
be663ab6
WYG		 6220
6221 /* Regardless of if we are associated, we must reconfigure the
6222 * TX power since frames can be sent on non-radar channels while
6223 * not associated */
1600b875 6224 il->ops->send_tx_power(il);
be663ab6
WYG		 6225
6226 /* Update last_temperature to keep is_calib_needed from running
6227 * when it isn't needed... */
46bc8d4b 6228 il->last_temperature = il->temperature;
f325757a 6229out:
46bc8d4b 6230 mutex_unlock(&il->mutex);
be663ab6
WYG		 6231}
6232
e7392364
SG		 6233static void
6234il4965_setup_deferred_work(struct il_priv *il)
be663ab6 6235{
46bc8d4b 6236 il->workqueue = create_singlethread_workqueue(DRV_NAME);
be663ab6 6237
46bc8d4b 6238 init_waitqueue_head(&il->wait_command_queue);
be663ab6 6239
46bc8d4b
SG		 6240 INIT_WORK(&il->restart, il4965_bg_restart);
6241 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6242 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6243 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6244 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
be663ab6 6245
46bc8d4b 6246 il_setup_scan_deferred_work(il);
be663ab6 6247
46bc8d4b 6248 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
be663ab6 6249
ebf0d90d
SG		 6250 init_timer(&il->stats_periodic);
6251 il->stats_periodic.data = (unsigned long)il;
6252 il->stats_periodic.function = il4965_bg_stats_periodic;
be663ab6 6253
46bc8d4b
SG		 6254 init_timer(&il->watchdog);
6255 il->watchdog.data = (unsigned long)il;
6256 il->watchdog.function = il_bg_watchdog;
be663ab6 6257
e7392364
SG		 6258 tasklet_init(&il->irq_tasklet,
6259 (void (*)(unsigned long))il4965_irq_tasklet,
6260 (unsigned long)il);
be663ab6
WYG		 6261}
6262
e7392364
SG		 6263static void
6264il4965_cancel_deferred_work(struct il_priv *il)
be663ab6 6265{
46bc8d4b
SG		 6266 cancel_work_sync(&il->txpower_work);
6267 cancel_delayed_work_sync(&il->init_alive_start);
6268 cancel_delayed_work(&il->alive_start);
6269 cancel_work_sync(&il->run_time_calib_work);
be663ab6 6270
46bc8d4b 6271 il_cancel_scan_deferred_work(il);
be663ab6 6272
ebf0d90d 6273 del_timer_sync(&il->stats_periodic);
be663ab6
WYG		 6274}
6275
e7392364
SG		 6276static void
6277il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
be663ab6
WYG		 6278{
6279 int i;
6280
2eb05816 6281 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
d2ddf621 6282 rates[i].bitrate = il_rates[i].ieee * 5;
e7392364 6283 rates[i].hw_value = i; /* Rate scaling will work on idxes */
be663ab6
WYG		 6284 rates[i].hw_value_short = i;
6285 rates[i].flags = 0;
e2ebc833 6286 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
be663ab6
WYG		 6287 /*
6288 * If CCK != 1M then set short preamble rate flag.
6289 */
6290 rates[i].flags |=
e7392364
SG		 6291 (il_rates[i].plcp ==
6292 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
be663ab6
WYG		 6293 }
6294 }
6295}
e7392364 6296
be663ab6 6297/*
46bc8d4b 6298 * Acquire il->lock before calling this function !
be663ab6 6299 */
e7392364
SG		 6300void
6301il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
be663ab6 6302{
e7392364 6303 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
0c2c8852 6304 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
be663ab6
WYG		 6305}
6306
e7392364
SG		 6307void
6308il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6309 int tx_fifo_id, int scd_retry)
be663ab6
WYG		 6310{
6311 int txq_id = txq->q.id;
6312
6313 /* Find out whether to activate Tx queue */
46bc8d4b 6314 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
be663ab6
WYG		 6315
6316 /* Set up and activate */
d3175167 6317 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 6318 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6319 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6320 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6321 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6322 IL49_SCD_QUEUE_STTS_REG_MSK);
be663ab6
WYG		 6323
6324 txq->sched_retry = scd_retry;
6325
e7392364
SG		 6326 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6327 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
be663ab6
WYG		 6328}
6329
60c46bf8 6330static const struct ieee80211_ops il4965_mac_ops = {
c39ae9fd
SG		 6331 .tx = il4965_mac_tx,
6332 .start = il4965_mac_start,
6333 .stop = il4965_mac_stop,
6334 .add_interface = il_mac_add_interface,
6335 .remove_interface = il_mac_remove_interface,
6336 .change_interface = il_mac_change_interface,
6337 .config = il_mac_config,
6338 .configure_filter = il4965_configure_filter,
6339 .set_key = il4965_mac_set_key,
6340 .update_tkip_key = il4965_mac_update_tkip_key,
6341 .conf_tx = il_mac_conf_tx,
6342 .reset_tsf = il_mac_reset_tsf,
6343 .bss_info_changed = il_mac_bss_info_changed,
6344 .ampdu_action = il4965_mac_ampdu_action,
6345 .hw_scan = il_mac_hw_scan,
6346 .sta_add = il4965_mac_sta_add,
6347 .sta_remove = il_mac_sta_remove,
6348 .channel_switch = il4965_mac_channel_switch,
6349 .tx_last_beacon = il_mac_tx_last_beacon,
70277f47 6350 .flush = il_mac_flush,
c39ae9fd
SG		 6351};
6352
e7392364
SG		 6353static int
6354il4965_init_drv(struct il_priv *il)
be663ab6
WYG		 6355{
6356 int ret;
6357
46bc8d4b
SG		 6358 spin_lock_init(&il->sta_lock);
6359 spin_lock_init(&il->hcmd_lock);
be663ab6 6360
46bc8d4b 6361 INIT_LIST_HEAD(&il->free_frames);
be663ab6 6362
46bc8d4b 6363 mutex_init(&il->mutex);
be663ab6 6364
46bc8d4b
SG		 6365 il->ieee_channels = NULL;
6366 il->ieee_rates = NULL;
6367 il->band = IEEE80211_BAND_2GHZ;
be663ab6 6368
46bc8d4b
SG		 6369 il->iw_mode = NL80211_IFTYPE_STATION;
6370 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6371 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
be663ab6
WYG		 6372
6373 /* initialize force reset */
46bc8d4b 6374 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
be663ab6
WYG		 6375
6376 /* Choose which receivers/antennas to use */
c9363551
SG		 6377 if (il->ops->set_rxon_chain)
6378 il->ops->set_rxon_chain(il);
be663ab6 6379
46bc8d4b 6380 il_init_scan_params(il);
be663ab6 6381
46bc8d4b 6382 ret = il_init_channel_map(il);
be663ab6 6383 if (ret) {
9406f797 6384 IL_ERR("initializing regulatory failed: %d\n", ret);
be663ab6
WYG		 6385 goto err;
6386 }
6387
46bc8d4b 6388 ret = il_init_geos(il);
be663ab6 6389 if (ret) {
9406f797 6390 IL_ERR("initializing geos failed: %d\n", ret);
be663ab6
WYG		 6391 goto err_free_channel_map;
6392 }
46bc8d4b 6393 il4965_init_hw_rates(il, il->ieee_rates);
be663ab6
WYG		 6394
6395 return 0;
6396
6397err_free_channel_map:
46bc8d4b 6398 il_free_channel_map(il);
be663ab6
WYG		 6399err:
6400 return ret;
6401}
6402
e7392364
SG		 6403static void
6404il4965_uninit_drv(struct il_priv *il)
be663ab6 6405{
46bc8d4b
SG		 6406 il_free_geos(il);
6407 il_free_channel_map(il);
6408 kfree(il->scan_cmd);
be663ab6
WYG		 6409}
6410
e7392364
SG		 6411static void
6412il4965_hw_detect(struct il_priv *il)
be663ab6 6413{
841b2cca
SG		 6414 il->hw_rev = _il_rd(il, CSR_HW_REV);
6415 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
46bc8d4b 6416 il->rev_id = il->pci_dev->revision;
58de00a4 6417 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
be663ab6
WYG		 6418}
6419
1023f3bc
SG		 6420static struct il_sensitivity_ranges il4965_sensitivity = {
6421 .min_nrg_cck = 97,
6422 .max_nrg_cck = 0, /* not used, set to 0 */
6423
6424 .auto_corr_min_ofdm = 85,
6425 .auto_corr_min_ofdm_mrc = 170,
6426 .auto_corr_min_ofdm_x1 = 105,
6427 .auto_corr_min_ofdm_mrc_x1 = 220,
6428
6429 .auto_corr_max_ofdm = 120,
6430 .auto_corr_max_ofdm_mrc = 210,
6431 .auto_corr_max_ofdm_x1 = 140,
6432 .auto_corr_max_ofdm_mrc_x1 = 270,
6433
6434 .auto_corr_min_cck = 125,
6435 .auto_corr_max_cck = 200,
6436 .auto_corr_min_cck_mrc = 200,
6437 .auto_corr_max_cck_mrc = 400,
6438
6439 .nrg_th_cck = 100,
6440 .nrg_th_ofdm = 100,
6441
6442 .barker_corr_th_min = 190,
6443 .barker_corr_th_min_mrc = 390,
6444 .nrg_th_cca = 62,
6445};
6446
6447static void
e7392364 6448il4965_set_hw_params(struct il_priv *il)
be663ab6 6449{
b16db50a 6450 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
46bc8d4b
SG		 6451 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6452 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6453 if (il->cfg->mod_params->amsdu_size_8K)
6454 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
be663ab6 6455 else
46bc8d4b 6456 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
be663ab6 6457
46bc8d4b 6458 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
be663ab6 6459
46bc8d4b
SG		 6460 if (il->cfg->mod_params->disable_11n)
6461 il->cfg->sku &= ~IL_SKU_N;
be663ab6 6462
1023f3bc
SG		 6463 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6464 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6465 il->cfg->num_of_queues =
6466 il->cfg->mod_params->num_of_queues;
6467
6468 il->hw_params.max_txq_num = il->cfg->num_of_queues;
6469 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6470 il->hw_params.scd_bc_tbls_size =
6471 il->cfg->num_of_queues *
6472 sizeof(struct il4965_scd_bc_tbl);
6473
6474 il->hw_params.tfd_size = sizeof(struct il_tfd);
6475 il->hw_params.max_stations = IL4965_STATION_COUNT;
6476 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6477 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6478 il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6479 il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
6480
6481 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6482
6483 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6484 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6485 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6486 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6487
6488 il->hw_params.ct_kill_threshold =
6489 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6490
6491 il->hw_params.sens = &il4965_sensitivity;
6492 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
be663ab6
WYG		 6493}
6494
be663ab6 6495static int
e2ebc833 6496il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
be663ab6 6497{
7c2cde2e 6498 int err = 0;
46bc8d4b 6499 struct il_priv *il;
be663ab6 6500 struct ieee80211_hw *hw;
e2ebc833 6501 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
be663ab6
WYG		 6502 unsigned long flags;
6503 u16 pci_cmd;
6504
6505 /************************
6506 * 1. Allocating HW data
6507 ************************/
6508
c39ae9fd 6509 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
be663ab6
WYG		 6510 if (!hw) {
6511 err = -ENOMEM;
6512 goto out;
6513 }
46bc8d4b 6514 il = hw->priv;
c39ae9fd 6515 il->hw = hw;
be663ab6
WYG		 6516 SET_IEEE80211_DEV(hw, &pdev->dev);
6517
58de00a4 6518 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 6519 il->cfg = cfg;
c39ae9fd 6520 il->ops = &il4965_ops;
93b7654e
SG		 6521#ifdef CONFIG_IWLEGACY_DEBUGFS
6522 il->debugfs_ops = &il4965_debugfs_ops;
6523#endif
46bc8d4b
SG		 6524 il->pci_dev = pdev;
6525 il->inta_mask = CSR_INI_SET_MASK;
be663ab6 6526
be663ab6
WYG		 6527 /**************************
6528 * 2. Initializing PCI bus
6529 **************************/
e7392364
SG		 6530 pci_disable_link_state(pdev,
6531 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6532 PCIE_LINK_STATE_CLKPM);
be663ab6
WYG		 6533
6534 if (pci_enable_device(pdev)) {
6535 err = -ENODEV;
6536 goto out_ieee80211_free_hw;
6537 }
6538
6539 pci_set_master(pdev);
6540
6541 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6542 if (!err)
6543 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6544 if (err) {
6545 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6546 if (!err)
e7392364
SG		 6547 err =
6548 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
be663ab6
WYG		 6549 /* both attempts failed: */
6550 if (err) {
9406f797 6551 IL_WARN("No suitable DMA available.\n");
be663ab6
WYG		 6552 goto out_pci_disable_device;
6553 }
6554 }
6555
6556 err = pci_request_regions(pdev, DRV_NAME);
6557 if (err)
6558 goto out_pci_disable_device;
6559
46bc8d4b 6560 pci_set_drvdata(pdev, il);
be663ab6 6561
be663ab6
WYG		 6562 /***********************
6563 * 3. Read REV register
6564 ***********************/
a5f16137 6565 il->hw_base = pci_ioremap_bar(pdev, 0);
46bc8d4b 6566 if (!il->hw_base) {
be663ab6
WYG		 6567 err = -ENODEV;
6568 goto out_pci_release_regions;
6569 }
6570
58de00a4 6571 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 6572 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 6573 D_INFO("pci_resource_base = %p\n", il->hw_base);
be663ab6
WYG		 6574
6575 /* these spin locks will be used in apm_ops.init and EEPROM access
6576 * we should init now
6577 */
46bc8d4b
SG		 6578 spin_lock_init(&il->reg_lock);
6579 spin_lock_init(&il->lock);
be663ab6
WYG		 6580
6581 /*
6582 * stop and reset the on-board processor just in case it is in a
6583 * strange state ... like being left stranded by a primary kernel
6584 * and this is now the kdump kernel trying to start up
6585 */
841b2cca 6586 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6 6587
46bc8d4b 6588 il4965_hw_detect(il);
e7392364 6589 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
be663ab6
WYG		 6590
6591 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6592 * PCI Tx retries from interfering with C3 CPU state */
6593 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6594
46bc8d4b
SG		 6595 il4965_prepare_card_hw(il);
6596 if (!il->hw_ready) {
9406f797 6597 IL_WARN("Failed, HW not ready\n");
66284505 6598 err = -EIO;
be663ab6
WYG		 6599 goto out_iounmap;
6600 }
6601
6602 /*****************
6603 * 4. Read EEPROM
6604 *****************/
6605 /* Read the EEPROM */
46bc8d4b 6606 err = il_eeprom_init(il);
be663ab6 6607 if (err) {
9406f797 6608 IL_ERR("Unable to init EEPROM\n");
be663ab6
WYG		 6609 goto out_iounmap;
6610 }
46bc8d4b 6611 err = il4965_eeprom_check_version(il);
be663ab6
WYG		 6612 if (err)
6613 goto out_free_eeprom;
6614
be663ab6 6615 /* extract MAC Address */
46bc8d4b 6616 il4965_eeprom_get_mac(il, il->addresses[0].addr);
58de00a4 6617 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
46bc8d4b
SG		 6618 il->hw->wiphy->addresses = il->addresses;
6619 il->hw->wiphy->n_addresses = 1;
be663ab6
WYG		 6620
6621 /************************
6622 * 5. Setup HW constants
6623 ************************/
1023f3bc 6624 il4965_set_hw_params(il);
be663ab6
WYG		 6625
6626 /*******************
46bc8d4b 6627 * 6. Setup il
be663ab6
WYG		 6628 *******************/
6629
46bc8d4b 6630 err = il4965_init_drv(il);
be663ab6
WYG		 6631 if (err)
6632 goto out_free_eeprom;
46bc8d4b 6633 /* At this point both hw and il are initialized. */
be663ab6
WYG		 6634
6635 /********************
6636 * 7. Setup services
6637 ********************/
46bc8d4b
SG		 6638 spin_lock_irqsave(&il->lock, flags);
6639 il_disable_interrupts(il);
6640 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6641
46bc8d4b 6642 pci_enable_msi(il->pci_dev);
be663ab6 6643
e7392364 6644 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
be663ab6 6645 if (err) {
9406f797 6646 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
be663ab6
WYG		 6647 goto out_disable_msi;
6648 }
6649
46bc8d4b 6650 il4965_setup_deferred_work(il);
d0c72347 6651 il4965_setup_handlers(il);
be663ab6
WYG		 6652
6653 /*********************************************
6654 * 8. Enable interrupts and read RFKILL state
6655 *********************************************/
6656
a078a1fd 6657 /* enable rfkill interrupt: hw bug w/a */
46bc8d4b 6658 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
be663ab6
WYG		 6659 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6660 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
46bc8d4b 6661 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
be663ab6
WYG		 6662 }
6663
46bc8d4b 6664 il_enable_rfkill_int(il);
be663ab6
WYG		 6665
6666 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 6667 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 6668 clear_bit(S_RFKILL, &il->status);
be663ab6 6669 else
bc269a8e 6670 set_bit(S_RFKILL, &il->status);
be663ab6 6671
46bc8d4b 6672 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 6673 test_bit(S_RFKILL, &il->status));
be663ab6 6674
46bc8d4b 6675 il_power_initialize(il);
be663ab6 6676
46bc8d4b 6677 init_completion(&il->_4965.firmware_loading_complete);
be663ab6 6678
46bc8d4b 6679 err = il4965_request_firmware(il, true);
be663ab6
WYG		 6680 if (err)
6681 goto out_destroy_workqueue;
6682
6683 return 0;
6684
e7392364 6685out_destroy_workqueue:
46bc8d4b
SG		 6686 destroy_workqueue(il->workqueue);
6687 il->workqueue = NULL;
6688 free_irq(il->pci_dev->irq, il);
e7392364 6689out_disable_msi:
46bc8d4b
SG		 6690 pci_disable_msi(il->pci_dev);
6691 il4965_uninit_drv(il);
e7392364 6692out_free_eeprom:
46bc8d4b 6693 il_eeprom_free(il);
e7392364 6694out_iounmap:
a5f16137 6695 iounmap(il->hw_base);
e7392364 6696out_pci_release_regions:
be663ab6 6697 pci_release_regions(pdev);
e7392364 6698out_pci_disable_device:
be663ab6 6699 pci_disable_device(pdev);
e7392364 6700out_ieee80211_free_hw:
46bc8d4b 6701 ieee80211_free_hw(il->hw);
e7392364 6702out:
be663ab6
WYG		 6703 return err;
6704}
6705
a027cb88 6706static void
e7392364 6707il4965_pci_remove(struct pci_dev *pdev)
be663ab6 6708{
46bc8d4b 6709 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 6710 unsigned long flags;
6711
46bc8d4b 6712 if (!il)
be663ab6
WYG		 6713 return;
6714
46bc8d4b 6715 wait_for_completion(&il->_4965.firmware_loading_complete);
be663ab6 6716
58de00a4 6717 D_INFO("*** UNLOAD DRIVER ***\n");
be663ab6 6718
46bc8d4b 6719 il_dbgfs_unregister(il);
e2ebc833 6720 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
be663ab6 6721
e2ebc833
SG		 6722 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6723 * to be called and il4965_down since we are removing the device
a6766ccd 6724 * we need to set S_EXIT_PENDING bit.
be663ab6 6725 */
a6766ccd 6726 set_bit(S_EXIT_PENDING, &il->status);
be663ab6 6727
46bc8d4b 6728 il_leds_exit(il);
be663ab6 6729
46bc8d4b
SG		 6730 if (il->mac80211_registered) {
6731 ieee80211_unregister_hw(il->hw);
6732 il->mac80211_registered = 0;
be663ab6 6733 } else {
46bc8d4b 6734 il4965_down(il);
be663ab6
WYG		 6735 }
6736
6737 /*
6738 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG		 6739 * This may be redundant with il4965_down(), but there are paths to
6740 * run il4965_down() without calling apm_ops.stop(), and there are
6741 * paths to avoid running il4965_down() at all before leaving driver.
be663ab6
WYG		 6742 * This (inexpensive) call *makes sure* device is reset.
6743 */
46bc8d4b 6744 il_apm_stop(il);
be663ab6
WYG		 6745
6746 /* make sure we flush any pending irq or
6747 * tasklet for the driver
6748 */
46bc8d4b
SG		 6749 spin_lock_irqsave(&il->lock, flags);
6750 il_disable_interrupts(il);
6751 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6752
46bc8d4b 6753 il4965_synchronize_irq(il);
be663ab6 6754
46bc8d4b 6755 il4965_dealloc_ucode_pci(il);
be663ab6 6756
46bc8d4b
SG		 6757 if (il->rxq.bd)
6758 il4965_rx_queue_free(il, &il->rxq);
6759 il4965_hw_txq_ctx_free(il);
be663ab6 6760
46bc8d4b 6761 il_eeprom_free(il);
be663ab6 6762
be663ab6 6763 /*netif_stop_queue(dev); */
46bc8d4b 6764 flush_workqueue(il->workqueue);
be663ab6 6765
e2ebc833 6766 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
46bc8d4b 6767 * il->workqueue... so we can't take down the workqueue
be663ab6 6768 * until now... */
46bc8d4b
SG		 6769 destroy_workqueue(il->workqueue);
6770 il->workqueue = NULL;
be663ab6 6771
46bc8d4b
SG		 6772 free_irq(il->pci_dev->irq, il);
6773 pci_disable_msi(il->pci_dev);
a5f16137 6774 iounmap(il->hw_base);
be663ab6
WYG		 6775 pci_release_regions(pdev);
6776 pci_disable_device(pdev);
be663ab6 6777
46bc8d4b 6778 il4965_uninit_drv(il);
be663ab6 6779
46bc8d4b 6780 dev_kfree_skb(il->beacon_skb);
be663ab6 6781
46bc8d4b 6782 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6783}
6784
6785/*
6786 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
46bc8d4b 6787 * must be called under il->lock and mac access
be663ab6 6788 */
e7392364
SG		 6789void
6790il4965_txq_set_sched(struct il_priv *il, u32 mask)
be663ab6 6791{
d3175167 6792 il_wr_prph(il, IL49_SCD_TXFACT, mask);
be663ab6
WYG		 6793}
6794
6795/*****************************************************************************
6796 *
6797 * driver and module entry point
6798 *
6799 *****************************************************************************/
6800
6801/* Hardware specific file defines the PCI IDs table for that hardware module */
9baa3c34 6802static const struct pci_device_id il4965_hw_card_ids[] = {
e2ebc833
SG		 6803 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6804 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
be663ab6
WYG		 6805 {0}
6806};
e2ebc833 6807MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
be663ab6 6808
e2ebc833 6809static struct pci_driver il4965_driver = {
be663ab6 6810 .name = DRV_NAME,
e2ebc833
SG		 6811 .id_table = il4965_hw_card_ids,
6812 .probe = il4965_pci_probe,
a027cb88 6813 .remove = il4965_pci_remove,
e2ebc833 6814 .driver.pm = IL_LEGACY_PM_OPS,
be663ab6
WYG		 6815};
6816
e7392364
SG		 6817static int __init
6818il4965_init(void)
be663ab6
WYG		 6819{
6820
6821 int ret;
6822 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6823 pr_info(DRV_COPYRIGHT "\n");
6824
e2ebc833 6825 ret = il4965_rate_control_register();
be663ab6
WYG		 6826 if (ret) {
6827 pr_err("Unable to register rate control algorithm: %d\n", ret);
6828 return ret;
6829 }
6830
e2ebc833 6831 ret = pci_register_driver(&il4965_driver);
be663ab6
WYG		 6832 if (ret) {
6833 pr_err("Unable to initialize PCI module\n");
6834 goto error_register;
6835 }
6836
6837 return ret;
6838
6839error_register:
e2ebc833 6840 il4965_rate_control_unregister();
be663ab6
WYG		 6841 return ret;
6842}
6843
e7392364
SG		 6844static void __exit
6845il4965_exit(void)
be663ab6 6846{
e2ebc833
SG		 6847 pci_unregister_driver(&il4965_driver);
6848 il4965_rate_control_unregister();
be663ab6
WYG		 6849}
6850
e2ebc833
SG		 6851module_exit(il4965_exit);
6852module_init(il4965_init);
be663ab6 6853
d3175167 6854#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 6855module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
be663ab6
WYG		 6856MODULE_PARM_DESC(debug, "debug output mask");
6857#endif
6858
e2ebc833 6859module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
be663ab6 6860MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
e2ebc833 6861module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
be663ab6 6862MODULE_PARM_DESC(queues_num, "number of hw queues.");
e2ebc833 6863module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
be663ab6 6864MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
e7392364
SG		 6865module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6866 S_IRUGO);
997bc71a 6867MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size (default 0 [disabled])");
e2ebc833 6868module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
be663ab6 6869MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
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