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bcma: Xflash: reorder includes to make pr_fmt work
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
be663ab6
WYG		 43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
98613be0 53#include "common.h"
af038f40 54#include "4965.h"
be663ab6 55
be663ab6
WYG		 56/******************************************************************************
57 *
58 * module boiler plate
59 *
60 ******************************************************************************/
61
62/*
63 * module name, copyright, version, etc.
64 */
65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
66
d3175167 67#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 68#define VD "d"
69#else
70#define VD
71#endif
72
73#define DRV_VERSION IWLWIFI_VERSION VD
74
be663ab6
WYG		 75MODULE_DESCRIPTION(DRV_DESCRIPTION);
76MODULE_VERSION(DRV_VERSION);
77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78MODULE_LICENSE("GPL");
79MODULE_ALIAS("iwl4965");
80
e7392364
SG		 81void
82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
fcb74588
SG		 83{
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
a6766ccd 86 if (!test_bit(S_EXIT_PENDING, &il->status))
fcb74588
SG		 87 queue_work(il->workqueue, &il->tx_flush);
88 }
89}
90
91/*
92 * EEPROM
93 */
94struct il_mod_params il4965_mod_params = {
95 .amsdu_size_8K = 1,
96 .restart_fw = 1,
97 /* the rest are 0 by default */
98};
99
e7392364
SG		 100void
101il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 102{
103 unsigned long flags;
104 int i;
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 114 PAGE_SIZE << il->hw_params.rx_page_order,
115 PCI_DMA_FROMDEVICE);
fcb74588
SG		 116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
118 }
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
120 }
121
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
124
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
129 rxq->free_count = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
131}
132
e7392364
SG		 133int
134il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 135{
136 u32 rb_size;
e7392364 137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
fcb74588
SG		 138 u32 rb_timeout = 0;
139
140 if (il->cfg->mod_params->amsdu_size_8K)
9a95b370 141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
fcb74588 142 else
9a95b370 143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
fcb74588
SG		 144
145 /* Stop Rx DMA */
9a95b370 146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
fcb74588
SG		 147
148 /* Reset driver's Rx queue write idx */
9a95b370 149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
fcb74588
SG		 150
151 /* Tell device where to find RBD circular buffer in DRAM */
e7392364 152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
fcb74588
SG		 153
154 /* Tell device where in DRAM to update its Rx status */
e7392364 155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
fcb74588
SG		 156
157 /* Enable Rx DMA
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
160 * RB timeout 0x10
161 * 256 RBDs
162 */
9a95b370 163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
e7392364
SG		 164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
1722f8e1
SG		 166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
167 rb_size |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
fcb74588
SG		 170
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
173
174 return 0;
175}
176
e7392364
SG		 177static void
178il4965_set_pwr_vmain(struct il_priv *il)
fcb74588
SG		 179{
180/*
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
183
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
188 */
189
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
e7392364
SG		 191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
fcb74588
SG		 193}
194
e7392364
SG		 195int
196il4965_hw_nic_init(struct il_priv *il)
fcb74588
SG		 197{
198 unsigned long flags;
199 struct il_rx_queue *rxq = &il->rxq;
200 int ret;
201
fcb74588 202 spin_lock_irqsave(&il->lock, flags);
f03ee2a8 203 il_apm_init(il);
fcb74588
SG		 204 /* Set interrupt coalescing calibration timer to default (512 usecs) */
205 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
fcb74588
SG		 206 spin_unlock_irqrestore(&il->lock, flags);
207
208 il4965_set_pwr_vmain(il);
f03ee2a8 209 il4965_nic_config(il);
fcb74588
SG		 210
211 /* Allocate the RX queue, or reset if it is already allocated */
212 if (!rxq->bd) {
213 ret = il_rx_queue_alloc(il);
214 if (ret) {
215 IL_ERR("Unable to initialize Rx queue\n");
216 return -ENOMEM;
217 }
218 } else
219 il4965_rx_queue_reset(il, rxq);
220
221 il4965_rx_replenish(il);
222
223 il4965_rx_init(il, rxq);
224
225 spin_lock_irqsave(&il->lock, flags);
226
227 rxq->need_update = 1;
228 il_rx_queue_update_write_ptr(il, rxq);
229
230 spin_unlock_irqrestore(&il->lock, flags);
231
232 /* Allocate or reset and init all Tx and Command queues */
233 if (!il->txq) {
234 ret = il4965_txq_ctx_alloc(il);
235 if (ret)
236 return ret;
237 } else
238 il4965_txq_ctx_reset(il);
239
a6766ccd 240 set_bit(S_INIT, &il->status);
fcb74588
SG		 241
242 return 0;
243}
244
245/**
246 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
247 */
e7392364
SG		 248static inline __le32
249il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
fcb74588 250{
e7392364 251 return cpu_to_le32((u32) (dma_addr >> 8));
fcb74588
SG		 252}
253
254/**
255 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
256 *
257 * If there are slots in the RX queue that need to be restocked,
258 * and we have free pre-allocated buffers, fill the ranks as much
259 * as we can, pulling from rx_free.
260 *
261 * This moves the 'write' idx forward to catch up with 'processed', and
262 * also updates the memory address in the firmware to reference the new
263 * target buffer.
264 */
e7392364
SG		 265void
266il4965_rx_queue_restock(struct il_priv *il)
fcb74588
SG		 267{
268 struct il_rx_queue *rxq = &il->rxq;
269 struct list_head *element;
270 struct il_rx_buf *rxb;
271 unsigned long flags;
272
273 spin_lock_irqsave(&rxq->lock, flags);
274 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
275 /* The overwritten rxb must be a used one */
276 rxb = rxq->queue[rxq->write];
277 BUG_ON(rxb && rxb->page);
278
279 /* Get next free Rx buffer, remove from free list */
280 element = rxq->rx_free.next;
281 rxb = list_entry(element, struct il_rx_buf, list);
282 list_del(element);
283
284 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG		 285 rxq->bd[rxq->write] =
286 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
fcb74588
SG		 287 rxq->queue[rxq->write] = rxb;
288 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
289 rxq->free_count--;
290 }
291 spin_unlock_irqrestore(&rxq->lock, flags);
292 /* If the pre-allocated buffer pool is dropping low, schedule to
293 * refill it */
294 if (rxq->free_count <= RX_LOW_WATERMARK)
295 queue_work(il->workqueue, &il->rx_replenish);
296
fcb74588
SG		 297 /* If we've added more space for the firmware to place data, tell it.
298 * Increment device's write pointer in multiples of 8. */
299 if (rxq->write_actual != (rxq->write & ~0x7)) {
300 spin_lock_irqsave(&rxq->lock, flags);
301 rxq->need_update = 1;
302 spin_unlock_irqrestore(&rxq->lock, flags);
303 il_rx_queue_update_write_ptr(il, rxq);
304 }
305}
306
307/**
308 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
309 *
310 * When moving to rx_free an SKB is allocated for the slot.
311 *
312 * Also restock the Rx queue via il_rx_queue_restock.
313 * This is called as a scheduled work item (except for during initialization)
314 */
e7392364
SG		 315static void
316il4965_rx_allocate(struct il_priv *il, gfp_t priority)
fcb74588
SG		 317{
318 struct il_rx_queue *rxq = &il->rxq;
319 struct list_head *element;
320 struct il_rx_buf *rxb;
321 struct page *page;
322 unsigned long flags;
323 gfp_t gfp_mask = priority;
324
325 while (1) {
326 spin_lock_irqsave(&rxq->lock, flags);
327 if (list_empty(&rxq->rx_used)) {
328 spin_unlock_irqrestore(&rxq->lock, flags);
329 return;
330 }
331 spin_unlock_irqrestore(&rxq->lock, flags);
332
333 if (rxq->free_count > RX_LOW_WATERMARK)
334 gfp_mask |= __GFP_NOWARN;
335
336 if (il->hw_params.rx_page_order > 0)
337 gfp_mask |= __GFP_COMP;
338
339 /* Alloc a new receive buffer */
340 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
341 if (!page) {
342 if (net_ratelimit())
e7392364
SG		 343 D_INFO("alloc_pages failed, " "order: %d\n",
344 il->hw_params.rx_page_order);
fcb74588
SG		 345
346 if (rxq->free_count <= RX_LOW_WATERMARK &&
347 net_ratelimit())
e7392364
SG		 348 IL_ERR("Failed to alloc_pages with %s. "
349 "Only %u free buffers remaining.\n",
350 priority ==
351 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
352 rxq->free_count);
fcb74588
SG		 353 /* We don't reschedule replenish work here -- we will
354 * call the restock method and if it still needs
355 * more buffers it will schedule replenish */
356 return;
357 }
358
359 spin_lock_irqsave(&rxq->lock, flags);
360
361 if (list_empty(&rxq->rx_used)) {
362 spin_unlock_irqrestore(&rxq->lock, flags);
363 __free_pages(page, il->hw_params.rx_page_order);
364 return;
365 }
366 element = rxq->rx_used.next;
367 rxb = list_entry(element, struct il_rx_buf, list);
368 list_del(element);
369
370 spin_unlock_irqrestore(&rxq->lock, flags);
371
372 BUG_ON(rxb->page);
373 rxb->page = page;
374 /* Get physical address of the RB */
e7392364
SG		 375 rxb->page_dma =
376 pci_map_page(il->pci_dev, page, 0,
377 PAGE_SIZE << il->hw_params.rx_page_order,
378 PCI_DMA_FROMDEVICE);
fcb74588
SG		 379 /* dma address must be no more than 36 bits */
380 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
381 /* and also 256 byte aligned! */
382 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
383
384 spin_lock_irqsave(&rxq->lock, flags);
385
386 list_add_tail(&rxb->list, &rxq->rx_free);
387 rxq->free_count++;
388 il->alloc_rxb_page++;
389
390 spin_unlock_irqrestore(&rxq->lock, flags);
391 }
392}
393
e7392364
SG		 394void
395il4965_rx_replenish(struct il_priv *il)
fcb74588
SG		 396{
397 unsigned long flags;
398
399 il4965_rx_allocate(il, GFP_KERNEL);
400
401 spin_lock_irqsave(&il->lock, flags);
402 il4965_rx_queue_restock(il);
403 spin_unlock_irqrestore(&il->lock, flags);
404}
405
e7392364
SG		 406void
407il4965_rx_replenish_now(struct il_priv *il)
fcb74588
SG		 408{
409 il4965_rx_allocate(il, GFP_ATOMIC);
410
411 il4965_rx_queue_restock(il);
412}
413
414/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
415 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
416 * This free routine walks the list of POOL entries and if SKB is set to
417 * non NULL it is unmapped and freed
418 */
e7392364
SG		 419void
420il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 421{
422 int i;
423 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
424 if (rxq->pool[i].page != NULL) {
425 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 426 PAGE_SIZE << il->hw_params.rx_page_order,
427 PCI_DMA_FROMDEVICE);
fcb74588
SG		 428 __il_free_pages(il, rxq->pool[i].page);
429 rxq->pool[i].page = NULL;
430 }
431 }
432
433 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
434 rxq->bd_dma);
435 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
436 rxq->rb_stts, rxq->rb_stts_dma);
437 rxq->bd = NULL;
e7392364 438 rxq->rb_stts = NULL;
fcb74588
SG		 439}
440
e7392364
SG		 441int
442il4965_rxq_stop(struct il_priv *il)
fcb74588 443{
775ed8ab 444 int ret;
fcb74588 445
775ed8ab
SG		 446 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
447 ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
448 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
449 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
450 1000);
451 if (ret < 0)
452 IL_ERR("Can't stop Rx DMA.\n");
fcb74588
SG		 453
454 return 0;
455}
456
e7392364
SG		 457int
458il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
fcb74588
SG		 459{
460 int idx = 0;
461 int band_offset = 0;
462
463 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
464 if (rate_n_flags & RATE_MCS_HT_MSK) {
465 idx = (rate_n_flags & 0xff);
466 return idx;
e7392364 467 /* Legacy rate format, search for match in table */
fcb74588
SG		 468 } else {
469 if (band == IEEE80211_BAND_5GHZ)
470 band_offset = IL_FIRST_OFDM_RATE;
471 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
472 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
473 return idx - band_offset;
474 }
475
476 return -1;
477}
478
e7392364
SG		 479static int
480il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
fcb74588
SG		 481{
482 /* data from PHY/DSP regarding signal strength, etc.,
483 * contents are always there, not configurable by host. */
484 struct il4965_rx_non_cfg_phy *ncphy =
485 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
e7392364
SG		 486 u32 agc =
487 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
488 IL49_AGC_DB_POS;
fcb74588
SG		 489
490 u32 valid_antennae =
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
e7392364 492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
fcb74588
SG		 493 u8 max_rssi = 0;
494 u32 i;
495
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
504
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
507 max_rssi, agc);
508
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
512}
513
e7392364
SG		 514static u32
515il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
fcb74588
SG		 516{
517 u32 decrypt_out = 0;
518
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
e7392364
SG		 520 RX_RES_STATUS_STATION_FOUND)
521 decrypt_out |=
522 (RX_RES_STATUS_STATION_FOUND |
523 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
fcb74588
SG		 524
525 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
526
527 /* packet was not encrypted */
528 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 529 RX_RES_STATUS_SEC_TYPE_NONE)
fcb74588
SG		 530 return decrypt_out;
531
532 /* packet was encrypted with unknown alg */
533 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 534 RX_RES_STATUS_SEC_TYPE_ERR)
fcb74588
SG		 535 return decrypt_out;
536
537 /* decryption was not done in HW */
538 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
e7392364 539 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
fcb74588
SG		 540 return decrypt_out;
541
542 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
543
544 case RX_RES_STATUS_SEC_TYPE_CCMP:
545 /* alg is CCM: check MIC only */
546 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
547 /* Bad MIC */
548 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
549 else
550 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
551
552 break;
553
554 case RX_RES_STATUS_SEC_TYPE_TKIP:
555 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
556 /* Bad TTAK */
557 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
558 break;
559 }
560 /* fall through if TTAK OK */
561 default:
562 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
563 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
564 else
565 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
566 break;
567 }
568
e7392364 569 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
fcb74588
SG		 570
571 return decrypt_out;
572}
573
e7392364
SG		 574static void
575il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
576 u16 len, u32 ampdu_status, struct il_rx_buf *rxb,
577 struct ieee80211_rx_status *stats)
fcb74588
SG		 578{
579 struct sk_buff *skb;
580 __le16 fc = hdr->frame_control;
581
582 /* We only process data packets if the interface is open */
583 if (unlikely(!il->is_open)) {
e7392364 584 D_DROP("Dropping packet while interface is not open.\n");
fcb74588
SG		 585 return;
586 }
587
588 /* In case of HW accelerated crypto and bad decryption, drop */
589 if (!il->cfg->mod_params->sw_crypto &&
590 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
591 return;
592
593 skb = dev_alloc_skb(128);
594 if (!skb) {
595 IL_ERR("dev_alloc_skb failed\n");
596 return;
597 }
598
50269e19
ED		 599 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len,
600 len);
fcb74588
SG		 601
602 il_update_stats(il, false, fc, len);
603 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
604
605 ieee80211_rx(il->hw, skb);
606 il->alloc_rxb_page--;
607 rxb->page = NULL;
608}
609
4d69c752
SG		 610/* Called for N_RX (legacy ABG frames), or
611 * N_RX_MPDU (HT high-throughput N frames). */
e7392364
SG		 612void
613il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 614{
615 struct ieee80211_hdr *header;
d369167f 616 struct ieee80211_rx_status rx_status = {};
fcb74588
SG		 617 struct il_rx_pkt *pkt = rxb_addr(rxb);
618 struct il_rx_phy_res *phy_res;
619 __le32 rx_pkt_status;
620 struct il_rx_mpdu_res_start *amsdu;
621 u32 len;
622 u32 ampdu_status;
623 u32 rate_n_flags;
624
625 /**
4d69c752
SG		 626 * N_RX and N_RX_MPDU are handled differently.
627 * N_RX: physical layer info is in this buffer
628 * N_RX_MPDU: physical layer info was sent in separate
fcb74588
SG		 629 * command and cached in il->last_phy_res
630 *
631 * Here we set up local variables depending on which command is
632 * received.
633 */
4d69c752 634 if (pkt->hdr.cmd == N_RX) {
fcb74588 635 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
e7392364
SG		 636 header =
637 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
638 phy_res->cfg_phy_cnt);
fcb74588
SG		 639
640 len = le16_to_cpu(phy_res->byte_count);
e7392364
SG		 641 rx_pkt_status =
642 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
643 phy_res->cfg_phy_cnt + len);
fcb74588
SG		 644 ampdu_status = le32_to_cpu(rx_pkt_status);
645 } else {
646 if (!il->_4965.last_phy_res_valid) {
647 IL_ERR("MPDU frame without cached PHY data\n");
648 return;
649 }
650 phy_res = &il->_4965.last_phy_res;
651 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
652 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
653 len = le16_to_cpu(amsdu->byte_count);
e7392364
SG		 654 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
655 ampdu_status =
656 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
fcb74588
SG		 657 }
658
659 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
660 D_DROP("dsp size out of range [0,20]: %d/n",
e7392364 661 phy_res->cfg_phy_cnt);
fcb74588
SG		 662 return;
663 }
664
665 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
666 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e7392364 667 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
fcb74588
SG		 668 return;
669 }
670
671 /* This will be used in several places later */
672 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
673
674 /* rx_status carries information about the packet to mac80211 */
675 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
e7392364
SG		 676 rx_status.band =
677 (phy_res->
678 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
679 IEEE80211_BAND_5GHZ;
fcb74588 680 rx_status.freq =
e7392364
SG		 681 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
682 rx_status.band);
fcb74588 683 rx_status.rate_idx =
e7392364 684 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
fcb74588
SG		 685 rx_status.flag = 0;
686
687 /* TSF isn't reliable. In order to allow smooth user experience,
688 * this W/A doesn't propagate it to the mac80211 */
f4bda337 689 /*rx_status.flag |= RX_FLAG_MACTIME_START; */
fcb74588
SG		 690
691 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
692
693 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
694 rx_status.signal = il4965_calc_rssi(il, phy_res);
695
e7392364
SG		 696 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
697 (unsigned long long)rx_status.mactime);
fcb74588
SG		 698
699 /*
700 * "antenna number"
701 *
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
707 *
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
710 * as a bitmask.
711 */
712 rx_status.antenna =
e7392364
SG		 713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
714 RX_RES_PHY_FLAGS_ANTENNA_POS;
fcb74588
SG		 715
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
719
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
727
0255beda
CL		 728 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) {
729 /* We know which subframes of an A-MPDU belong
730 * together since we get a single PHY response
731 * from the firmware for all of them.
732 */
733
734 rx_status.flag |= RX_FLAG_AMPDU_DETAILS;
735 rx_status.ampdu_reference = il->_4965.ampdu_ref;
736 }
737
e7392364
SG		 738 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
739 &rx_status);
fcb74588
SG		 740}
741
4d69c752 742/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
6e9848b4 743 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
e7392364
SG		 744void
745il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 746{
747 struct il_rx_pkt *pkt = rxb_addr(rxb);
748 il->_4965.last_phy_res_valid = true;
0255beda 749 il->_4965.ampdu_ref++;
fcb74588
SG		 750 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
751 sizeof(struct il_rx_phy_res));
752}
753
e7392364
SG		 754static int
755il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
756 enum ieee80211_band band, u8 is_active,
757 u8 n_probes, struct il_scan_channel *scan_ch)
fcb74588
SG		 758{
759 struct ieee80211_channel *chan;
760 const struct ieee80211_supported_band *sband;
761 const struct il_channel_info *ch_info;
762 u16 passive_dwell = 0;
763 u16 active_dwell = 0;
764 int added, i;
765 u16 channel;
766
767 sband = il_get_hw_mode(il, band);
768 if (!sband)
769 return 0;
770
771 active_dwell = il_get_active_dwell_time(il, band, n_probes);
772 passive_dwell = il_get_passive_dwell_time(il, band, vif);
773
774 if (passive_dwell <= active_dwell)
775 passive_dwell = active_dwell + 1;
776
777 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
778 chan = il->scan_request->channels[i];
779
780 if (chan->band != band)
781 continue;
782
783 channel = chan->hw_value;
784 scan_ch->channel = cpu_to_le16(channel);
785
786 ch_info = il_get_channel_info(il, band, channel);
787 if (!il_is_channel_valid(ch_info)) {
e7392364
SG		 788 D_SCAN("Channel %d is INVALID for this band.\n",
789 channel);
fcb74588
SG		 790 continue;
791 }
792
793 if (!is_active || il_is_channel_passive(ch_info) ||
794 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
795 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
796 else
797 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
798
799 if (n_probes)
800 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
801
802 scan_ch->active_dwell = cpu_to_le16(active_dwell);
803 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
804
805 /* Set txpower levels to defaults */
806 scan_ch->dsp_atten = 110;
807
808 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
809 * power level:
810 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
811 */
812 if (band == IEEE80211_BAND_5GHZ)
813 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
814 else
815 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
816
e7392364
SG		 817 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
818 le32_to_cpu(scan_ch->type),
819 (scan_ch->
820 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
821 (scan_ch->
822 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
823 passive_dwell);
fcb74588
SG		 824
825 scan_ch++;
826 added++;
827 }
828
829 D_SCAN("total channels to scan %d\n", added);
830 return added;
831}
832
a0c1ef3b
SG		 833static void
834il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
835{
836 int i;
837 u8 ind = *ant;
838
839 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
840 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
841 if (valid & BIT(ind)) {
842 *ant = ind;
843 return;
844 }
845 }
846}
847
e7392364
SG		 848int
849il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
fcb74588
SG		 850{
851 struct il_host_cmd cmd = {
4d69c752 852 .id = C_SCAN,
fcb74588
SG		 853 .len = sizeof(struct il_scan_cmd),
854 .flags = CMD_SIZE_HUGE,
855 };
856 struct il_scan_cmd *scan;
fcb74588
SG		 857 u32 rate_flags = 0;
858 u16 cmd_len;
859 u16 rx_chain = 0;
860 enum ieee80211_band band;
861 u8 n_probes = 0;
862 u8 rx_ant = il->hw_params.valid_rx_ant;
863 u8 rate;
864 bool is_active = false;
e7392364 865 int chan_mod;
fcb74588
SG		 866 u8 active_chains;
867 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
868 int ret;
869
870 lockdep_assert_held(&il->mutex);
871
fcb74588 872 if (!il->scan_cmd) {
e7392364
SG		 873 il->scan_cmd =
874 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
875 GFP_KERNEL);
fcb74588 876 if (!il->scan_cmd) {
e7392364 877 D_SCAN("fail to allocate memory for scan\n");
fcb74588
SG		 878 return -ENOMEM;
879 }
880 }
881 scan = il->scan_cmd;
882 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
883
884 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
885 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
886
887 if (il_is_any_associated(il)) {
888 u16 interval;
889 u32 extra;
890 u32 suspend_time = 100;
891 u32 scan_suspend_time = 100;
892
893 D_INFO("Scanning while associated...\n");
894 interval = vif->bss_conf.beacon_int;
895
896 scan->suspend_time = 0;
897 scan->max_out_time = cpu_to_le32(200 * 1024);
898 if (!interval)
899 interval = suspend_time;
900
901 extra = (suspend_time / interval) << 22;
e7392364
SG		 902 scan_suspend_time =
903 (extra | ((suspend_time % interval) * 1024));
fcb74588
SG		 904 scan->suspend_time = cpu_to_le32(scan_suspend_time);
905 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 906 scan_suspend_time, interval);
fcb74588
SG		 907 }
908
909 if (il->scan_request->n_ssids) {
910 int i, p = 0;
911 D_SCAN("Kicking off active scan\n");
912 for (i = 0; i < il->scan_request->n_ssids; i++) {
913 /* always does wildcard anyway */
914 if (!il->scan_request->ssids[i].ssid_len)
915 continue;
916 scan->direct_scan[p].id = WLAN_EID_SSID;
917 scan->direct_scan[p].len =
e7392364 918 il->scan_request->ssids[i].ssid_len;
fcb74588
SG		 919 memcpy(scan->direct_scan[p].ssid,
920 il->scan_request->ssids[i].ssid,
921 il->scan_request->ssids[i].ssid_len);
922 n_probes++;
923 p++;
924 }
925 is_active = true;
926 } else
927 D_SCAN("Start passive scan.\n");
928
929 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 930 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
fcb74588
SG		 931 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
932
933 switch (il->scan_band) {
934 case IEEE80211_BAND_2GHZ:
935 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
e7392364 936 chan_mod =
c8b03958 937 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
e7392364 938 RXON_FLG_CHANNEL_MODE_POS;
fcb74588
SG		 939 if (chan_mod == CHANNEL_MODE_PURE_40) {
940 rate = RATE_6M_PLCP;
941 } else {
942 rate = RATE_1M_PLCP;
943 rate_flags = RATE_MCS_CCK_MSK;
944 }
945 break;
946 case IEEE80211_BAND_5GHZ:
947 rate = RATE_6M_PLCP;
948 break;
949 default:
950 IL_WARN("Invalid scan band\n");
951 return -EIO;
952 }
953
954 /*
955 * If active scanning is requested but a certain channel is
956 * marked passive, we can do active scanning if we detect
957 * transmissions.
958 *
959 * There is an issue with some firmware versions that triggers
960 * a sysassert on a "good CRC threshold" of zero (== disabled),
961 * on a radar channel even though this means that we should NOT
962 * send probes.
963 *
964 * The "good CRC threshold" is the number of frames that we
965 * need to receive during our dwell time on a channel before
966 * sending out probes -- setting this to a huge value will
967 * mean we never reach it, but at the same time work around
968 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
969 * here instead of IL_GOOD_CRC_TH_DISABLED.
970 */
e7392364
SG		 971 scan->good_CRC_th =
972 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
fcb74588
SG		 973
974 band = il->scan_band;
975
976 if (il->cfg->scan_rx_antennas[band])
977 rx_ant = il->cfg->scan_rx_antennas[band];
978
a0c1ef3b 979 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
616107ed
SG		 980 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
981 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
fcb74588
SG		 982
983 /* In power save mode use one chain, otherwise use all chains */
a6766ccd 984 if (test_bit(S_POWER_PMI, &il->status)) {
fcb74588 985 /* rx_ant has been set to all valid chains previously */
e7392364
SG		 986 active_chains =
987 rx_ant & ((u8) (il->chain_noise_data.active_chains));
fcb74588
SG		 988 if (!active_chains)
989 active_chains = rx_ant;
990
991 D_SCAN("chain_noise_data.active_chains: %u\n",
e7392364 992 il->chain_noise_data.active_chains);
fcb74588
SG		 993
994 rx_ant = il4965_first_antenna(active_chains);
995 }
996
997 /* MIMO is not used here, but value is required */
998 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
999 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1000 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1001 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1002 scan->rx_chain = cpu_to_le16(rx_chain);
1003
e7392364
SG		 1004 cmd_len =
1005 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
1006 vif->addr, il->scan_request->ie,
1007 il->scan_request->ie_len,
1008 IL_MAX_SCAN_SIZE - sizeof(*scan));
fcb74588
SG		 1009 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1010
e7392364
SG		 1011 scan->filter_flags |=
1012 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
fcb74588 1013
e7392364
SG		 1014 scan->channel_count =
1015 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1016 (void *)&scan->data[cmd_len]);
fcb74588
SG		 1017 if (scan->channel_count == 0) {
1018 D_SCAN("channel count %d\n", scan->channel_count);
1019 return -EIO;
1020 }
1021
e7392364
SG		 1022 cmd.len +=
1023 le16_to_cpu(scan->tx_cmd.len) +
fcb74588
SG		 1024 scan->channel_count * sizeof(struct il_scan_channel);
1025 cmd.data = scan;
1026 scan->len = cpu_to_le16(cmd.len);
1027
a6766ccd 1028 set_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1029
1030 ret = il_send_cmd_sync(il, &cmd);
1031 if (ret)
a6766ccd 1032 clear_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1033
1034 return ret;
1035}
1036
e7392364
SG		 1037int
1038il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1039 bool add)
fcb74588
SG		 1040{
1041 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1042
1043 if (add)
83007196 1044 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
fcb74588
SG		 1045 &vif_priv->ibss_bssid_sta_id);
1046 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
e7392364 1047 vif->bss_conf.bssid);
fcb74588
SG		 1048}
1049
e7392364
SG		 1050void
1051il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
fcb74588
SG		 1052{
1053 lockdep_assert_held(&il->sta_lock);
1054
1055 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1056 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1057 else {
1058 D_TX("free more than tfds_in_queue (%u:%d)\n",
e7392364 1059 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
fcb74588
SG		 1060 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1061 }
1062}
1063
1064#define IL_TX_QUEUE_MSK 0xfffff
1065
e7392364
SG		 1066static bool
1067il4965_is_single_rx_stream(struct il_priv *il)
fcb74588
SG		 1068{
1069 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
e7392364 1070 il->current_ht_config.single_chain_sufficient;
fcb74588
SG		 1071}
1072
1073#define IL_NUM_RX_CHAINS_MULTIPLE 3
1074#define IL_NUM_RX_CHAINS_SINGLE 2
1075#define IL_NUM_IDLE_CHAINS_DUAL 2
1076#define IL_NUM_IDLE_CHAINS_SINGLE 1
1077
1078/*
1079 * Determine how many receiver/antenna chains to use.
1080 *
1081 * More provides better reception via diversity. Fewer saves power
1082 * at the expense of throughput, but only when not in powersave to
1083 * start with.
1084 *
1085 * MIMO (dual stream) requires at least 2, but works better with 3.
1086 * This does not determine *which* chains to use, just how many.
1087 */
e7392364
SG		 1088static int
1089il4965_get_active_rx_chain_count(struct il_priv *il)
fcb74588
SG		 1090{
1091 /* # of Rx chains to use when expecting MIMO. */
1092 if (il4965_is_single_rx_stream(il))
1093 return IL_NUM_RX_CHAINS_SINGLE;
1094 else
1095 return IL_NUM_RX_CHAINS_MULTIPLE;
1096}
1097
1098/*
1099 * When we are in power saving mode, unless device support spatial
1100 * multiplexing power save, use the active count for rx chain count.
1101 */
1102static int
1103il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1104{
1105 /* # Rx chains when idling, depending on SMPS mode */
1106 switch (il->current_ht_config.smps) {
1107 case IEEE80211_SMPS_STATIC:
1108 case IEEE80211_SMPS_DYNAMIC:
1109 return IL_NUM_IDLE_CHAINS_SINGLE;
1110 case IEEE80211_SMPS_OFF:
1111 return active_cnt;
1112 default:
e7392364 1113 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
fcb74588
SG		 1114 return active_cnt;
1115 }
1116}
1117
1118/* up to 4 chains */
e7392364
SG		 1119static u8
1120il4965_count_chain_bitmap(u32 chain_bitmap)
fcb74588
SG		 1121{
1122 u8 res;
1123 res = (chain_bitmap & BIT(0)) >> 0;
1124 res += (chain_bitmap & BIT(1)) >> 1;
1125 res += (chain_bitmap & BIT(2)) >> 2;
1126 res += (chain_bitmap & BIT(3)) >> 3;
1127 return res;
1128}
1129
1130/**
1131 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1132 *
1133 * Selects how many and which Rx receivers/antennas/chains to use.
1134 * This should not be used for scan command ... it puts data in wrong place.
1135 */
e7392364 1136void
83007196 1137il4965_set_rxon_chain(struct il_priv *il)
fcb74588
SG		 1138{
1139 bool is_single = il4965_is_single_rx_stream(il);
a6766ccd 1140 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
fcb74588
SG		 1141 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1142 u32 active_chains;
1143 u16 rx_chain;
1144
1145 /* Tell uCode which antennas are actually connected.
1146 * Before first association, we assume all antennas are connected.
1147 * Just after first association, il4965_chain_noise_calibration()
1148 * checks which antennas actually *are* connected. */
1149 if (il->chain_noise_data.active_chains)
1150 active_chains = il->chain_noise_data.active_chains;
1151 else
1152 active_chains = il->hw_params.valid_rx_ant;
1153
1154 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1155
1156 /* How many receivers should we use? */
1157 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1158 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1159
fcb74588
SG		 1160 /* correct rx chain count according hw settings
1161 * and chain noise calibration
1162 */
1163 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1164 if (valid_rx_cnt < active_rx_cnt)
1165 active_rx_cnt = valid_rx_cnt;
1166
1167 if (valid_rx_cnt < idle_rx_cnt)
1168 idle_rx_cnt = valid_rx_cnt;
1169
1170 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
e7392364 1171 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
fcb74588 1172
c8b03958 1173 il->staging.rx_chain = cpu_to_le16(rx_chain);
fcb74588
SG		 1174
1175 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
c8b03958 1176 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1177 else
c8b03958 1178 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1179
c8b03958 1180 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
e7392364 1181 active_rx_cnt, idle_rx_cnt);
fcb74588
SG		 1182
1183 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1184 active_rx_cnt < idle_rx_cnt);
1185}
1186
e7392364
SG		 1187static const char *
1188il4965_get_fh_string(int cmd)
fcb74588
SG		 1189{
1190 switch (cmd) {
e7392364
SG		 1191 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1192 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1193 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1194 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1195 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1196 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1197 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1198 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1199 IL_CMD(FH49_TSSR_TX_ERROR_REG);
fcb74588
SG		 1200 default:
1201 return "UNKNOWN";
1202 }
1203}
1204
e7392364
SG		 1205int
1206il4965_dump_fh(struct il_priv *il, char **buf, bool display)
fcb74588
SG		 1207{
1208 int i;
1209#ifdef CONFIG_IWLEGACY_DEBUG
1210 int pos = 0;
1211 size_t bufsz = 0;
1212#endif
1213 static const u32 fh_tbl[] = {
9a95b370
SG		 1214 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1215 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1216 FH49_RSCSR_CHNL0_WPTR,
1217 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1218 FH49_MEM_RSSR_SHARED_CTRL_REG,
1219 FH49_MEM_RSSR_RX_STATUS_REG,
1220 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1221 FH49_TSSR_TX_STATUS_REG,
1222 FH49_TSSR_TX_ERROR_REG
fcb74588
SG		 1223 };
1224#ifdef CONFIG_IWLEGACY_DEBUG
1225 if (display) {
1226 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1227 *buf = kmalloc(bufsz, GFP_KERNEL);
1228 if (!*buf)
1229 return -ENOMEM;
e7392364
SG		 1230 pos +=
1231 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
fcb74588 1232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
e7392364
SG		 1233 pos +=
1234 scnprintf(*buf + pos, bufsz - pos,
1235 " %34s: 0X%08x\n",
1722f8e1
SG		 1236 il4965_get_fh_string(fh_tbl[i]),
1237 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1238 }
1239 return pos;
1240 }
1241#endif
1242 IL_ERR("FH register values:\n");
e7392364
SG		 1243 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1244 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1245 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1246 }
1247 return 0;
1248}
a1751b22 1249
e7392364
SG		 1250void
1251il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1252{
1253 struct il_rx_pkt *pkt = rxb_addr(rxb);
1254 struct il_missed_beacon_notif *missed_beacon;
1255
1256 missed_beacon = &pkt->u.missed_beacon;
1257 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1258 il->missed_beacon_threshold) {
e7392364
SG		 1259 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1260 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1261 le32_to_cpu(missed_beacon->total_missed_becons),
1262 le32_to_cpu(missed_beacon->num_recvd_beacons),
1263 le32_to_cpu(missed_beacon->num_expected_beacons));
a6766ccd 1264 if (!test_bit(S_SCANNING, &il->status))
a1751b22
SG		 1265 il4965_init_sensitivity(il);
1266 }
1267}
1268
1269/* Calculate noise level, based on measurements during network silence just
1270 * before arriving beacon. This measurement can be done only if we know
1271 * exactly when to expect beacons, therefore only when we're associated. */
e7392364
SG		 1272static void
1273il4965_rx_calc_noise(struct il_priv *il)
a1751b22
SG		 1274{
1275 struct stats_rx_non_phy *rx_info;
1276 int num_active_rx = 0;
1277 int total_silence = 0;
1278 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1279 int last_rx_noise;
1280
1281 rx_info = &(il->_4965.stats.rx.general);
1282 bcn_silence_a =
e7392364 1283 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
a1751b22 1284 bcn_silence_b =
e7392364 1285 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
a1751b22 1286 bcn_silence_c =
e7392364 1287 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
a1751b22
SG		 1288
1289 if (bcn_silence_a) {
1290 total_silence += bcn_silence_a;
1291 num_active_rx++;
1292 }
1293 if (bcn_silence_b) {
1294 total_silence += bcn_silence_b;
1295 num_active_rx++;
1296 }
1297 if (bcn_silence_c) {
1298 total_silence += bcn_silence_c;
1299 num_active_rx++;
1300 }
1301
1302 /* Average among active antennas */
1303 if (num_active_rx)
1304 last_rx_noise = (total_silence / num_active_rx) - 107;
1305 else
1306 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1307
e7392364
SG		 1308 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1309 bcn_silence_b, bcn_silence_c, last_rx_noise);
a1751b22
SG		 1310}
1311
1312#ifdef CONFIG_IWLEGACY_DEBUGFS
1313/*
1314 * based on the assumption of all stats counter are in DWORD
1315 * FIXME: This function is for debugging, do not deal with
1316 * the case of counters roll-over.
1317 */
e7392364
SG		 1318static void
1319il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
a1751b22
SG		 1320{
1321 int i, size;
1322 __le32 *prev_stats;
1323 u32 *accum_stats;
1324 u32 *delta, *max_delta;
1325 struct stats_general_common *general, *accum_general;
1326 struct stats_tx *tx, *accum_tx;
1327
1722f8e1
SG		 1328 prev_stats = (__le32 *) &il->_4965.stats;
1329 accum_stats = (u32 *) &il->_4965.accum_stats;
a1751b22
SG		 1330 size = sizeof(struct il_notif_stats);
1331 general = &il->_4965.stats.general.common;
1332 accum_general = &il->_4965.accum_stats.general.common;
1333 tx = &il->_4965.stats.tx;
1334 accum_tx = &il->_4965.accum_stats.tx;
1722f8e1
SG		 1335 delta = (u32 *) &il->_4965.delta_stats;
1336 max_delta = (u32 *) &il->_4965.max_delta;
a1751b22
SG		 1337
1338 for (i = sizeof(__le32); i < size;
e7392364
SG		 1339 i +=
1340 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1341 accum_stats++) {
a1751b22 1342 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
e7392364
SG		 1343 *delta =
1344 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
a1751b22
SG		 1345 *accum_stats += *delta;
1346 if (*delta > *max_delta)
1347 *max_delta = *delta;
1348 }
1349 }
1350
1351 /* reset accumulative stats for "no-counter" type stats */
1352 accum_general->temperature = general->temperature;
1353 accum_general->ttl_timestamp = general->ttl_timestamp;
1354}
1355#endif
1356
e7392364
SG		 1357void
1358il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22 1359{
527901d0
SG		 1360 const int recalib_seconds = 60;
1361 bool change;
a1751b22
SG		 1362 struct il_rx_pkt *pkt = rxb_addr(rxb);
1363
e7392364
SG		 1364 D_RX("Statistics notification received (%d vs %d).\n",
1365 (int)sizeof(struct il_notif_stats),
1366 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1367
1368 change =
1369 ((il->_4965.stats.general.common.temperature !=
1370 pkt->u.stats.general.common.temperature) ||
1371 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1372 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
a1751b22 1373#ifdef CONFIG_IWLEGACY_DEBUGFS
1722f8e1 1374 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
a1751b22
SG		 1375#endif
1376
1377 /* TODO: reading some of stats is unneeded */
e7392364 1378 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
a1751b22 1379
db7746f7 1380 set_bit(S_STATS, &il->status);
a1751b22 1381
527901d0
SG		 1382 /*
1383 * Reschedule the stats timer to occur in recalib_seconds to ensure
1384 * we get a thermal update even if the uCode doesn't give us one
1385 */
e7392364 1386 mod_timer(&il->stats_periodic,
527901d0 1387 jiffies + msecs_to_jiffies(recalib_seconds * 1000));
a1751b22 1388
a6766ccd 1389 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
4d69c752 1390 (pkt->hdr.cmd == N_STATS)) {
a1751b22
SG		 1391 il4965_rx_calc_noise(il);
1392 queue_work(il->workqueue, &il->run_time_calib_work);
1393 }
527901d0
SG		 1394
1395 if (change)
1396 il4965_temperature_calib(il);
a1751b22
SG		 1397}
1398
e7392364
SG		 1399void
1400il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1401{
1402 struct il_rx_pkt *pkt = rxb_addr(rxb);
1403
db7746f7 1404 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
a1751b22
SG		 1405#ifdef CONFIG_IWLEGACY_DEBUGFS
1406 memset(&il->_4965.accum_stats, 0,
e7392364 1407 sizeof(struct il_notif_stats));
a1751b22 1408 memset(&il->_4965.delta_stats, 0,
e7392364
SG		 1409 sizeof(struct il_notif_stats));
1410 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
a1751b22
SG		 1411#endif
1412 D_RX("Statistics have been cleared\n");
1413 }
d2dfb33e 1414 il4965_hdl_stats(il, rxb);
a1751b22
SG		 1415}
1416
8f29b456
SG		 1417
1418/*
1419 * mac80211 queues, ACs, hardware queues, FIFOs.
1420 *
1421 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1422 *
1423 * Mac80211 uses the following numbers, which we get as from it
1424 * by way of skb_get_queue_mapping(skb):
1425 *
1426 * VO 0
1427 * VI 1
1428 * BE 2
1429 * BK 3
1430 *
1431 *
1432 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1433 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1434 * own queue per aggregation session (RA/TID combination), such queues are
1435 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1436 * order to map frames to the right queue, we also need an AC->hw queue
1437 * mapping. This is implemented here.
1438 *
1439 * Due to the way hw queues are set up (by the hw specific modules like
af038f40 1440 * 4965.c), the AC->hw queue mapping is the identity
8f29b456
SG		 1441 * mapping.
1442 */
1443
a1751b22
SG		 1444static const u8 tid_to_ac[] = {
1445 IEEE80211_AC_BE,
1446 IEEE80211_AC_BK,
1447 IEEE80211_AC_BK,
1448 IEEE80211_AC_BE,
1449 IEEE80211_AC_VI,
1450 IEEE80211_AC_VI,
1451 IEEE80211_AC_VO,
1452 IEEE80211_AC_VO
1453};
1454
e7392364
SG		 1455static inline int
1456il4965_get_ac_from_tid(u16 tid)
a1751b22
SG		 1457{
1458 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1459 return tid_to_ac[tid];
1460
1461 /* no support for TIDs 8-15 yet */
1462 return -EINVAL;
1463}
1464
1465static inline int
83007196 1466il4965_get_fifo_from_tid(u16 tid)
a1751b22 1467{
b75b3a70
SG		 1468 const u8 ac_to_fifo[] = {
1469 IL_TX_FIFO_VO,
1470 IL_TX_FIFO_VI,
1471 IL_TX_FIFO_BE,
1472 IL_TX_FIFO_BK,
1473 };
1474
a1751b22 1475 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
b75b3a70 1476 return ac_to_fifo[tid_to_ac[tid]];
a1751b22
SG		 1477
1478 /* no support for TIDs 8-15 yet */
1479 return -EINVAL;
1480}
1481
1482/*
4d69c752 1483 * handle build C_TX command notification.
a1751b22 1484 */
e7392364
SG		 1485static void
1486il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1487 struct il_tx_cmd *tx_cmd,
1488 struct ieee80211_tx_info *info,
1489 struct ieee80211_hdr *hdr, u8 std_id)
a1751b22
SG		 1490{
1491 __le16 fc = hdr->frame_control;
1492 __le32 tx_flags = tx_cmd->tx_flags;
1493
1494 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1495 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1496 tx_flags |= TX_CMD_FLG_ACK_MSK;
1497 if (ieee80211_is_mgmt(fc))
1498 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1499 if (ieee80211_is_probe_resp(fc) &&
1500 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1501 tx_flags |= TX_CMD_FLG_TSF_MSK;
1502 } else {
1503 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1504 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1505 }
1506
1507 if (ieee80211_is_back_req(fc))
1508 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1509
1510 tx_cmd->sta_id = std_id;
1511 if (ieee80211_has_morefrags(fc))
1512 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1513
1514 if (ieee80211_is_data_qos(fc)) {
1515 u8 *qc = ieee80211_get_qos_ctl(hdr);
1516 tx_cmd->tid_tspec = qc[0] & 0xf;
1517 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1518 } else {
1519 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1520 }
1521
1522 il_tx_cmd_protection(il, info, fc, &tx_flags);
1523
1524 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1525 if (ieee80211_is_mgmt(fc)) {
1526 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1527 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1528 else
1529 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1530 } else {
1531 tx_cmd->timeout.pm_frame_timeout = 0;
1532 }
1533
1534 tx_cmd->driver_txop = 0;
1535 tx_cmd->tx_flags = tx_flags;
1536 tx_cmd->next_frame_len = 0;
1537}
1538
e7392364 1539static void
36323f81
TH		 1540il4965_tx_cmd_build_rate(struct il_priv *il,
1541 struct il_tx_cmd *tx_cmd,
1542 struct ieee80211_tx_info *info,
1543 struct ieee80211_sta *sta,
1544 __le16 fc)
a1751b22 1545{
616107ed 1546 const u8 rts_retry_limit = 60;
a1751b22
SG		 1547 u32 rate_flags;
1548 int rate_idx;
a1751b22
SG		 1549 u8 data_retry_limit;
1550 u8 rate_plcp;
1551
e7392364 1552 /* Set retry limit on DATA packets and Probe Responses */
a1751b22
SG		 1553 if (ieee80211_is_probe_resp(fc))
1554 data_retry_limit = 3;
1555 else
1556 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1557 tx_cmd->data_retry_limit = data_retry_limit;
a1751b22 1558 /* Set retry limit on RTS packets */
616107ed 1559 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
a1751b22
SG		 1560
1561 /* DATA packets will use the uCode station table for rate/antenna
1562 * selection */
1563 if (ieee80211_is_data(fc)) {
1564 tx_cmd->initial_rate_idx = 0;
1565 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1566 return;
1567 }
1568
1569 /**
1570 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1571 * not really a TX rate. Thus, we use the lowest supported rate for
1572 * this band. Also use the lowest supported rate if the stored rate
1573 * idx is invalid.
1574 */
1575 rate_idx = info->control.rates[0].idx;
e7392364
SG		 1576 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1577 || rate_idx > RATE_COUNT_LEGACY)
36323f81 1578 rate_idx = rate_lowest_index(&il->bands[info->band], sta);
a1751b22
SG		 1579 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1580 if (info->band == IEEE80211_BAND_5GHZ)
1581 rate_idx += IL_FIRST_OFDM_RATE;
1582 /* Get PLCP rate for tx_cmd->rate_n_flags */
1583 rate_plcp = il_rates[rate_idx].plcp;
1584 /* Zero out flags for this packet */
1585 rate_flags = 0;
1586
1587 /* Set CCK flag as needed */
1588 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1589 rate_flags |= RATE_MCS_CCK_MSK;
1590
1591 /* Set up antennas */
a0c1ef3b 1592 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 1593 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
a1751b22
SG		 1594
1595 /* Set the rate in the TX cmd */
616107ed 1596 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
a1751b22
SG		 1597}
1598
e7392364
SG		 1599static void
1600il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1601 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1602 int sta_id)
a1751b22
SG		 1603{
1604 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1605
1606 switch (keyconf->cipher) {
1607 case WLAN_CIPHER_SUITE_CCMP:
1608 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1609 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1610 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1611 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1612 D_TX("tx_cmd with AES hwcrypto\n");
1613 break;
1614
1615 case WLAN_CIPHER_SUITE_TKIP:
1616 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1617 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1618 D_TX("tx_cmd with tkip hwcrypto\n");
1619 break;
1620
1621 case WLAN_CIPHER_SUITE_WEP104:
1622 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1623 /* fall through */
1624 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG		 1625 tx_cmd->sec_ctl |=
1626 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1627 TX_CMD_SEC_SHIFT);
a1751b22
SG		 1628
1629 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1630
e7392364
SG		 1631 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1632 keyconf->keyidx);
a1751b22
SG		 1633 break;
1634
1635 default:
1636 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1637 break;
1638 }
1639}
1640
1641/*
4d69c752 1642 * start C_TX command process
a1751b22 1643 */
e7392364 1644int
36323f81
TH		 1645il4965_tx_skb(struct il_priv *il,
1646 struct ieee80211_sta *sta,
1647 struct sk_buff *skb)
a1751b22
SG		 1648{
1649 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1650 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
a1751b22
SG		 1651 struct il_station_priv *sta_priv = NULL;
1652 struct il_tx_queue *txq;
1653 struct il_queue *q;
1654 struct il_device_cmd *out_cmd;
1655 struct il_cmd_meta *out_meta;
1656 struct il_tx_cmd *tx_cmd;
a1751b22
SG		 1657 int txq_id;
1658 dma_addr_t phys_addr;
1659 dma_addr_t txcmd_phys;
1660 dma_addr_t scratch_phys;
1661 u16 len, firstlen, secondlen;
1662 u16 seq_number = 0;
1663 __le16 fc;
1664 u8 hdr_len;
1665 u8 sta_id;
1666 u8 wait_write_ptr = 0;
1667 u8 tid = 0;
1668 u8 *qc = NULL;
1669 unsigned long flags;
1670 bool is_agg = false;
1671
a1751b22
SG		 1672 spin_lock_irqsave(&il->lock, flags);
1673 if (il_is_rfkill(il)) {
1674 D_DROP("Dropping - RF KILL\n");
1675 goto drop_unlock;
1676 }
1677
1678 fc = hdr->frame_control;
1679
1680#ifdef CONFIG_IWLEGACY_DEBUG
1681 if (ieee80211_is_auth(fc))
1682 D_TX("Sending AUTH frame\n");
1683 else if (ieee80211_is_assoc_req(fc))
1684 D_TX("Sending ASSOC frame\n");
1685 else if (ieee80211_is_reassoc_req(fc))
1686 D_TX("Sending REASSOC frame\n");
1687#endif
1688
1689 hdr_len = ieee80211_hdrlen(fc);
1690
1691 /* For management frames use broadcast id to do not break aggregation */
1692 if (!ieee80211_is_data(fc))
b16db50a 1693 sta_id = il->hw_params.bcast_id;
a1751b22
SG		 1694 else {
1695 /* Find idx into station table for destination station */
36323f81 1696 sta_id = il_sta_id_or_broadcast(il, sta);
a1751b22
SG		 1697
1698 if (sta_id == IL_INVALID_STATION) {
e7392364 1699 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
a1751b22
SG		 1700 goto drop_unlock;
1701 }
1702 }
1703
1704 D_TX("station Id %d\n", sta_id);
1705
1706 if (sta)
1707 sta_priv = (void *)sta->drv_priv;
1708
1709 if (sta_priv && sta_priv->asleep &&
02f2f1a9 1710 (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) {
a1751b22
SG		 1711 /*
1712 * This sends an asynchronous command to the device,
1713 * but we can rely on it being processed before the
1714 * next frame is processed -- and the next frame to
1715 * this station is the one that will consume this
1716 * counter.
1717 * For now set the counter to just 1 since we do not
1718 * support uAPSD yet.
1719 */
1720 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1721 }
1722
d1e14e94
SG		 1723 /* FIXME: remove me ? */
1724 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1725
eb123af3
SG		 1726 /* Access category (AC) is also the queue number */
1727 txq_id = skb_get_queue_mapping(skb);
a1751b22
SG		 1728
1729 /* irqs already disabled/saved above when locking il->lock */
1730 spin_lock(&il->sta_lock);
1731
1732 if (ieee80211_is_data_qos(fc)) {
1733 qc = ieee80211_get_qos_ctl(hdr);
1734 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1735 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1736 spin_unlock(&il->sta_lock);
1737 goto drop_unlock;
1738 }
1739 seq_number = il->stations[sta_id].tid[tid].seq_number;
1740 seq_number &= IEEE80211_SCTL_SEQ;
e7392364
SG		 1741 hdr->seq_ctrl =
1742 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
a1751b22
SG		 1743 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1744 seq_number += 0x10;
1745 /* aggregation is on for this <sta,tid> */
1746 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1747 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1748 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1749 is_agg = true;
1750 }
1751 }
1752
1753 txq = &il->txq[txq_id];
1754 q = &txq->q;
1755
1756 if (unlikely(il_queue_space(q) < q->high_mark)) {
1757 spin_unlock(&il->sta_lock);
1758 goto drop_unlock;
1759 }
1760
1761 if (ieee80211_is_data_qos(fc)) {
1762 il->stations[sta_id].tid[tid].tfds_in_queue++;
1763 if (!ieee80211_has_morefrags(fc))
1764 il->stations[sta_id].tid[tid].seq_number = seq_number;
1765 }
1766
1767 spin_unlock(&il->sta_lock);
1768
00ea99e1 1769 txq->skbs[q->write_ptr] = skb;
a1751b22
SG		 1770
1771 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1772 out_cmd = txq->cmd[q->write_ptr];
1773 out_meta = &txq->meta[q->write_ptr];
1774 tx_cmd = &out_cmd->cmd.tx;
1775 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1776 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1777
1778 /*
1779 * Set up the Tx-command (not MAC!) header.
1780 * Store the chosen Tx queue and TFD idx within the sequence field;
1781 * after Tx, uCode's Tx response will return this value so driver can
1782 * locate the frame within the tx queue and do post-tx processing.
1783 */
4d69c752 1784 out_cmd->hdr.cmd = C_TX;
e7392364
SG		 1785 out_cmd->hdr.sequence =
1786 cpu_to_le16((u16)
1787 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
a1751b22
SG		 1788
1789 /* Copy MAC header from skb into command buffer */
1790 memcpy(tx_cmd->hdr, hdr, hdr_len);
1791
a1751b22 1792 /* Total # bytes to be transmitted */
e7392364 1793 len = (u16) skb->len;
a1751b22
SG		 1794 tx_cmd->len = cpu_to_le16(len);
1795
1796 if (info->control.hw_key)
1797 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1798
1799 /* TODO need this for burst mode later on */
1800 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
a1751b22 1801
36323f81 1802 il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc);
a1751b22
SG		 1803
1804 il_update_stats(il, true, fc, len);
1805 /*
1806 * Use the first empty entry in this queue's command buffer array
1807 * to contain the Tx command and MAC header concatenated together
1808 * (payload data will be in another buffer).
1809 * Size of this varies, due to varying MAC header length.
1810 * If end is not dword aligned, we'll have 2 extra bytes at the end
1811 * of the MAC header (device reads on dword boundaries).
1812 * We'll tell device about this padding later.
1813 */
e7392364 1814 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
a1751b22
SG		 1815 firstlen = (len + 3) & ~3;
1816
1817 /* Tell NIC about any 2-byte padding after MAC header */
1818 if (firstlen != len)
1819 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1820
1821 /* Physical address of this Tx command's header (not MAC header!),
1822 * within command buffer array. */
e7392364
SG		 1823 txcmd_phys =
1824 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1825 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1826 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1827 dma_unmap_len_set(out_meta, len, firstlen);
1828 /* Add buffer containing Tx command and MAC(!) header to TFD's
1829 * first entry */
1600b875 1830 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
a1751b22
SG		 1831
1832 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1833 txq->need_update = 1;
1834 } else {
1835 wait_write_ptr = 1;
1836 txq->need_update = 0;
1837 }
1838
1839 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1840 * if any (802.11 null frames have no payload). */
1841 secondlen = skb->len - hdr_len;
1842 if (secondlen > 0) {
e7392364
SG		 1843 phys_addr =
1844 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1845 PCI_DMA_TODEVICE);
1600b875
SG		 1846 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen,
1847 0, 0);
a1751b22
SG		 1848 }
1849
e7392364
SG		 1850 scratch_phys =
1851 txcmd_phys + sizeof(struct il_cmd_header) +
1852 offsetof(struct il_tx_cmd, scratch);
a1751b22
SG		 1853
1854 /* take back ownership of DMA buffer to enable update */
e7392364
SG		 1855 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1856 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1857 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1858 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1859
e7392364 1860 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
a1751b22 1861 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
e7392364
SG		 1862 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1863 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
a1751b22
SG		 1864
1865 /* Set up entry for this TFD in Tx byte-count array */
1866 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1600b875 1867 il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len));
a1751b22 1868
e7392364
SG		 1869 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1870 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1871
1872 /* Tell device the write idx *just past* this latest filled TFD */
1873 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1874 il_txq_update_write_ptr(il, txq);
1875 spin_unlock_irqrestore(&il->lock, flags);
1876
1877 /*
1878 * At this point the frame is "transmitted" successfully
1879 * and we will get a TX status notification eventually,
1880 * regardless of the value of ret. "ret" only indicates
1881 * whether or not we should update the write pointer.
1882 */
1883
1884 /*
1885 * Avoid atomic ops if it isn't an associated client.
1886 * Also, if this is a packet for aggregation, don't
1887 * increase the counter because the ucode will stop
1888 * aggregation queues when their respective station
1889 * goes to sleep.
1890 */
1891 if (sta_priv && sta_priv->client && !is_agg)
1892 atomic_inc(&sta_priv->pending_frames);
1893
1894 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1895 if (wait_write_ptr) {
1896 spin_lock_irqsave(&il->lock, flags);
1897 txq->need_update = 1;
1898 il_txq_update_write_ptr(il, txq);
1899 spin_unlock_irqrestore(&il->lock, flags);
1900 } else {
1901 il_stop_queue(il, txq);
1902 }
1903 }
1904
1905 return 0;
1906
1907drop_unlock:
1908 spin_unlock_irqrestore(&il->lock, flags);
1909 return -1;
1910}
1911
e7392364
SG		 1912static inline int
1913il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
a1751b22 1914{
e7392364
SG		 1915 ptr->addr =
1916 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL);
a1751b22
SG		 1917 if (!ptr->addr)
1918 return -ENOMEM;
1919 ptr->size = size;
1920 return 0;
1921}
1922
e7392364
SG		 1923static inline void
1924il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
a1751b22
SG		 1925{
1926 if (unlikely(!ptr->addr))
1927 return;
1928
1929 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1930 memset(ptr, 0, sizeof(*ptr));
1931}
1932
1933/**
1934 * il4965_hw_txq_ctx_free - Free TXQ Context
1935 *
1936 * Destroy all TX DMA queues and structures
1937 */
e7392364
SG		 1938void
1939il4965_hw_txq_ctx_free(struct il_priv *il)
a1751b22
SG		 1940{
1941 int txq_id;
1942
1943 /* Tx queues */
1944 if (il->txq) {
1945 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1946 if (txq_id == il->cmd_queue)
1947 il_cmd_queue_free(il);
1948 else
1949 il_tx_queue_free(il, txq_id);
1950 }
1951 il4965_free_dma_ptr(il, &il->kw);
1952
1953 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1954
1955 /* free tx queue structure */
6668e4eb 1956 il_free_txq_mem(il);
a1751b22
SG		 1957}
1958
1959/**
1960 * il4965_txq_ctx_alloc - allocate TX queue context
1961 * Allocate all Tx DMA structures and initialize them
1962 *
1963 * @param il
1964 * @return error code
1965 */
e7392364
SG		 1966int
1967il4965_txq_ctx_alloc(struct il_priv *il)
a1751b22 1968{
d87c771f 1969 int ret, txq_id;
a1751b22
SG		 1970 unsigned long flags;
1971
1972 /* Free all tx/cmd queues and keep-warm buffer */
1973 il4965_hw_txq_ctx_free(il);
1974
e7392364
SG		 1975 ret =
1976 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1977 il->hw_params.scd_bc_tbls_size);
a1751b22
SG		 1978 if (ret) {
1979 IL_ERR("Scheduler BC Table allocation failed\n");
1980 goto error_bc_tbls;
1981 }
1982 /* Alloc keep-warm buffer */
1983 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1984 if (ret) {
1985 IL_ERR("Keep Warm allocation failed\n");
1986 goto error_kw;
1987 }
1988
1989 /* allocate tx queue structure */
1990 ret = il_alloc_txq_mem(il);
1991 if (ret)
1992 goto error;
1993
1994 spin_lock_irqsave(&il->lock, flags);
1995
1996 /* Turn off all Tx DMA fifos */
1997 il4965_txq_set_sched(il, 0);
1998
1999 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2000 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2001
2002 spin_unlock_irqrestore(&il->lock, flags);
2003
2004 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
2005 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
d87c771f 2006 ret = il_tx_queue_init(il, txq_id);
a1751b22
SG		 2007 if (ret) {
2008 IL_ERR("Tx %d queue init failed\n", txq_id);
2009 goto error;
2010 }
2011 }
2012
2013 return ret;
2014
e7392364 2015error:
a1751b22
SG		 2016 il4965_hw_txq_ctx_free(il);
2017 il4965_free_dma_ptr(il, &il->kw);
e7392364 2018error_kw:
a1751b22 2019 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
e7392364 2020error_bc_tbls:
a1751b22
SG		 2021 return ret;
2022}
2023
e7392364
SG		 2024void
2025il4965_txq_ctx_reset(struct il_priv *il)
a1751b22 2026{
d87c771f 2027 int txq_id;
a1751b22
SG		 2028 unsigned long flags;
2029
2030 spin_lock_irqsave(&il->lock, flags);
2031
2032 /* Turn off all Tx DMA fifos */
2033 il4965_txq_set_sched(il, 0);
a1751b22 2034 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2035 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2036
2037 spin_unlock_irqrestore(&il->lock, flags);
2038
2039 /* Alloc and init all Tx queues, including the command queue (#4) */
d87c771f
SG		 2040 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2041 il_tx_queue_reset(il, txq_id);
a1751b22
SG		 2042}
2043
e7392364 2044void
775ed8ab 2045il4965_txq_ctx_unmap(struct il_priv *il)
a1751b22 2046{
775ed8ab 2047 int txq_id;
a1751b22
SG		 2048
2049 if (!il->txq)
2050 return;
2051
2052 /* Unmap DMA from host system and free skb's */
2053 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2054 if (txq_id == il->cmd_queue)
2055 il_cmd_queue_unmap(il);
2056 else
2057 il_tx_queue_unmap(il, txq_id);
2058}
2059
775ed8ab
SG		 2060/**
2061 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2062 */
2063void
2064il4965_txq_ctx_stop(struct il_priv *il)
2065{
2066 int ch, ret;
2067
2068 _il_wr_prph(il, IL49_SCD_TXFACT, 0);
2069
2070 /* Stop each Tx DMA channel, and wait for it to be idle */
2071 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2072 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2073 ret =
2074 _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
2075 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2076 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2077 1000);
2078 if (ret < 0)
2079 IL_ERR("Timeout stopping DMA channel %d [0x%08x]",
2080 ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
2081 }
2082}
2083
a1751b22
SG		 2084/*
2085 * Find first available (lowest unused) Tx Queue, mark it "active".
2086 * Called only when finding queue for aggregation.
2087 * Should never return anything < 7, because they should already
2088 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2089 */
e7392364
SG		 2090static int
2091il4965_txq_ctx_activate_free(struct il_priv *il)
a1751b22
SG		 2092{
2093 int txq_id;
2094
2095 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2096 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2097 return txq_id;
2098 return -1;
2099}
2100
2101/**
2102 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2103 */
e7392364
SG		 2104static void
2105il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
a1751b22
SG		 2106{
2107 /* Simply stop the queue, but don't change any configuration;
2108 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
e7392364 2109 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 2110 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2111 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
a1751b22
SG		 2112}
2113
2114/**
2115 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2116 */
e7392364
SG		 2117static int
2118il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
a1751b22
SG		 2119{
2120 u32 tbl_dw_addr;
2121 u32 tbl_dw;
2122 u16 scd_q2ratid;
2123
2124 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2125
e7392364
SG		 2126 tbl_dw_addr =
2127 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
a1751b22
SG		 2128
2129 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2130
2131 if (txq_id & 0x1)
2132 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2133 else
2134 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2135
2136 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2137
2138 return 0;
2139}
2140
2141/**
2142 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2143 *
2144 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2145 * i.e. it must be one of the higher queues used for aggregation
2146 */
e7392364
SG		 2147static int
2148il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2149 int tid, u16 ssn_idx)
a1751b22
SG		 2150{
2151 unsigned long flags;
2152 u16 ra_tid;
2153 int ret;
2154
2155 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2156 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2157 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2158 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2159 txq_id, IL49_FIRST_AMPDU_QUEUE,
2160 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2161 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2162 return -EINVAL;
2163 }
2164
2165 ra_tid = BUILD_RAxTID(sta_id, tid);
2166
2167 /* Modify device's station table to Tx this TID */
2168 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2169 if (ret)
2170 return ret;
2171
2172 spin_lock_irqsave(&il->lock, flags);
2173
2174 /* Stop this Tx queue before configuring it */
2175 il4965_tx_queue_stop_scheduler(il, txq_id);
2176
2177 /* Map receiver-address / traffic-ID to this queue */
2178 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2179
2180 /* Set this queue as a chain-building queue */
2181 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2182
2183 /* Place first TFD at idx corresponding to start sequence number.
2184 * Assumes that ssn_idx is valid (!= 0xFFF) */
2185 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2186 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2187 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2188
2189 /* Set up Tx win size and frame limit for this queue */
2190 il_write_targ_mem(il,
e7392364
SG		 2191 il->scd_base_addr +
2192 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2193 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2194 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
a1751b22 2195
e7392364
SG		 2196 il_write_targ_mem(il,
2197 il->scd_base_addr +
2198 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2199 (SCD_FRAME_LIMIT <<
2200 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2201 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
a1751b22
SG		 2202
2203 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2204
2205 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2206 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2207
2208 spin_unlock_irqrestore(&il->lock, flags);
2209
2210 return 0;
2211}
2212
e7392364
SG		 2213int
2214il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2215 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
a1751b22
SG		 2216{
2217 int sta_id;
2218 int tx_fifo;
2219 int txq_id;
2220 int ret;
2221 unsigned long flags;
2222 struct il_tid_data *tid_data;
2223
83007196
SG		 2224 /* FIXME: warning if tx fifo not found ? */
2225 tx_fifo = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2226 if (unlikely(tx_fifo < 0))
2227 return tx_fifo;
2228
53611e05 2229 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
a1751b22
SG		 2230
2231 sta_id = il_sta_id(sta);
2232 if (sta_id == IL_INVALID_STATION) {
2233 IL_ERR("Start AGG on invalid station\n");
2234 return -ENXIO;
2235 }
2236 if (unlikely(tid >= MAX_TID_COUNT))
2237 return -EINVAL;
2238
2239 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2240 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2241 return -ENXIO;
2242 }
2243
2244 txq_id = il4965_txq_ctx_activate_free(il);
2245 if (txq_id == -1) {
2246 IL_ERR("No free aggregation queue available\n");
2247 return -ENXIO;
2248 }
2249
2250 spin_lock_irqsave(&il->sta_lock, flags);
2251 tid_data = &il->stations[sta_id].tid[tid];
2252 *ssn = SEQ_TO_SN(tid_data->seq_number);
2253 tid_data->agg.txq_id = txq_id;
e7392364 2254 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
a1751b22
SG		 2255 spin_unlock_irqrestore(&il->sta_lock, flags);
2256
e7392364 2257 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
a1751b22
SG		 2258 if (ret)
2259 return ret;
2260
2261 spin_lock_irqsave(&il->sta_lock, flags);
2262 tid_data = &il->stations[sta_id].tid[tid];
2263 if (tid_data->tfds_in_queue == 0) {
2264 D_HT("HW queue is empty\n");
2265 tid_data->agg.state = IL_AGG_ON;
2266 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2267 } else {
e7392364
SG		 2268 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2269 tid_data->tfds_in_queue);
a1751b22
SG		 2270 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2271 }
2272 spin_unlock_irqrestore(&il->sta_lock, flags);
2273 return ret;
2274}
2275
2276/**
2277 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2278 * il->lock must be held by the caller
2279 */
e7392364
SG		 2280static int
2281il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
a1751b22
SG		 2282{
2283 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2284 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2285 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2286 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2287 txq_id, IL49_FIRST_AMPDU_QUEUE,
2288 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2289 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2290 return -EINVAL;
2291 }
2292
2293 il4965_tx_queue_stop_scheduler(il, txq_id);
2294
e7392364 2295 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
a1751b22
SG		 2296
2297 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2298 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2299 /* supposes that ssn_idx is valid (!= 0xFFF) */
2300 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2301
e7392364 2302 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
a1751b22
SG		 2303 il_txq_ctx_deactivate(il, txq_id);
2304 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2305
2306 return 0;
2307}
2308
e7392364
SG		 2309int
2310il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2311 struct ieee80211_sta *sta, u16 tid)
a1751b22
SG		 2312{
2313 int tx_fifo_id, txq_id, sta_id, ssn;
2314 struct il_tid_data *tid_data;
2315 int write_ptr, read_ptr;
2316 unsigned long flags;
2317
83007196
SG		 2318 /* FIXME: warning if tx_fifo_id not found ? */
2319 tx_fifo_id = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2320 if (unlikely(tx_fifo_id < 0))
2321 return tx_fifo_id;
2322
2323 sta_id = il_sta_id(sta);
2324
2325 if (sta_id == IL_INVALID_STATION) {
2326 IL_ERR("Invalid station for AGG tid %d\n", tid);
2327 return -ENXIO;
2328 }
2329
2330 spin_lock_irqsave(&il->sta_lock, flags);
2331
2332 tid_data = &il->stations[sta_id].tid[tid];
2333 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2334 txq_id = tid_data->agg.txq_id;
2335
2336 switch (il->stations[sta_id].tid[tid].agg.state) {
2337 case IL_EMPTYING_HW_QUEUE_ADDBA:
2338 /*
2339 * This can happen if the peer stops aggregation
2340 * again before we've had a chance to drain the
2341 * queue we selected previously, i.e. before the
2342 * session was really started completely.
2343 */
2344 D_HT("AGG stop before setup done\n");
2345 goto turn_off;
2346 case IL_AGG_ON:
2347 break;
2348 default:
2349 IL_WARN("Stopping AGG while state not ON or starting\n");
2350 }
2351
2352 write_ptr = il->txq[txq_id].q.write_ptr;
2353 read_ptr = il->txq[txq_id].q.read_ptr;
2354
2355 /* The queue is not empty */
2356 if (write_ptr != read_ptr) {
2357 D_HT("Stopping a non empty AGG HW QUEUE\n");
2358 il->stations[sta_id].tid[tid].agg.state =
e7392364 2359 IL_EMPTYING_HW_QUEUE_DELBA;
a1751b22
SG		 2360 spin_unlock_irqrestore(&il->sta_lock, flags);
2361 return 0;
2362 }
2363
2364 D_HT("HW queue is empty\n");
e7392364 2365turn_off:
a1751b22
SG		 2366 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2367
2368 /* do not restore/save irqs */
2369 spin_unlock(&il->sta_lock);
2370 spin_lock(&il->lock);
2371
2372 /*
2373 * the only reason this call can fail is queue number out of range,
2374 * which can happen if uCode is reloaded and all the station
2375 * information are lost. if it is outside the range, there is no need
2376 * to deactivate the uCode queue, just return "success" to allow
2377 * mac80211 to clean up it own data.
2378 */
2379 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2380 spin_unlock_irqrestore(&il->lock, flags);
2381
2382 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2383
2384 return 0;
2385}
2386
e7392364
SG		 2387int
2388il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
a1751b22
SG		 2389{
2390 struct il_queue *q = &il->txq[txq_id].q;
2391 u8 *addr = il->stations[sta_id].sta.sta.addr;
2392 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
a1751b22
SG		 2393
2394 lockdep_assert_held(&il->sta_lock);
2395
2396 switch (il->stations[sta_id].tid[tid].agg.state) {
2397 case IL_EMPTYING_HW_QUEUE_DELBA:
2398 /* We are reclaiming the last packet of the */
2399 /* aggregated HW queue */
e7392364 2400 if (txq_id == tid_data->agg.txq_id &&
a1751b22
SG		 2401 q->read_ptr == q->write_ptr) {
2402 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
83007196 2403 int tx_fifo = il4965_get_fifo_from_tid(tid);
e7392364 2404 D_HT("HW queue empty: continue DELBA flow\n");
a1751b22
SG		 2405 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2406 tid_data->agg.state = IL_AGG_OFF;
83007196 2407 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2408 }
2409 break;
2410 case IL_EMPTYING_HW_QUEUE_ADDBA:
2411 /* We are reclaiming the last packet of the queue */
2412 if (tid_data->tfds_in_queue == 0) {
e7392364 2413 D_HT("HW queue empty: continue ADDBA flow\n");
a1751b22 2414 tid_data->agg.state = IL_AGG_ON;
83007196 2415 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2416 }
2417 break;
2418 }
2419
2420 return 0;
2421}
2422
e7392364 2423static void
83007196 2424il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
a1751b22
SG		 2425{
2426 struct ieee80211_sta *sta;
2427 struct il_station_priv *sta_priv;
2428
2429 rcu_read_lock();
83007196 2430 sta = ieee80211_find_sta(il->vif, addr1);
a1751b22
SG		 2431 if (sta) {
2432 sta_priv = (void *)sta->drv_priv;
2433 /* avoid atomic ops if this isn't a client */
2434 if (sta_priv->client &&
2435 atomic_dec_return(&sta_priv->pending_frames) == 0)
2436 ieee80211_sta_block_awake(il->hw, sta, false);
2437 }
2438 rcu_read_unlock();
2439}
2440
2441static void
00ea99e1 2442il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
a1751b22 2443{
00ea99e1 2444 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
a1751b22
SG		 2445
2446 if (!is_agg)
83007196 2447 il4965_non_agg_tx_status(il, hdr->addr1);
a1751b22 2448
00ea99e1 2449 ieee80211_tx_status_irqsafe(il->hw, skb);
a1751b22
SG		 2450}
2451
e7392364
SG		 2452int
2453il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
a1751b22
SG		 2454{
2455 struct il_tx_queue *txq = &il->txq[txq_id];
2456 struct il_queue *q = &txq->q;
a1751b22
SG		 2457 int nfreed = 0;
2458 struct ieee80211_hdr *hdr;
00ea99e1 2459 struct sk_buff *skb;
a1751b22
SG		 2460
2461 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2462 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 2463 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2464 q->write_ptr, q->read_ptr);
a1751b22
SG		 2465 return 0;
2466 }
2467
e7392364 2468 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
a1751b22
SG		 2469 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2470
00ea99e1 2471 skb = txq->skbs[txq->q.read_ptr];
a1751b22 2472
00ea99e1 2473 if (WARN_ON_ONCE(skb == NULL))
a1751b22
SG		 2474 continue;
2475
00ea99e1 2476 hdr = (struct ieee80211_hdr *) skb->data;
a1751b22
SG		 2477 if (ieee80211_is_data_qos(hdr->frame_control))
2478 nfreed++;
2479
00ea99e1 2480 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
a1751b22 2481
00ea99e1 2482 txq->skbs[txq->q.read_ptr] = NULL;
1600b875 2483 il->ops->txq_free_tfd(il, txq);
a1751b22
SG		 2484 }
2485 return nfreed;
2486}
2487
2488/**
2489 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2490 *
2491 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2492 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2493 */
e7392364
SG		 2494static int
2495il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2496 struct il_compressed_ba_resp *ba_resp)
a1751b22
SG		 2497{
2498 int i, sh, ack;
2499 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2500 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2501 int successes = 0;
2502 struct ieee80211_tx_info *info;
2503 u64 bitmap, sent_bitmap;
2504
e7392364 2505 if (unlikely(!agg->wait_for_ba)) {
a1751b22
SG		 2506 if (unlikely(ba_resp->bitmap))
2507 IL_ERR("Received BA when not expected\n");
2508 return -EINVAL;
2509 }
2510
2511 /* Mark that the expected block-ack response arrived */
2512 agg->wait_for_ba = 0;
e7392364 2513 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
a1751b22
SG		 2514
2515 /* Calculate shift to align block-ack bits with our Tx win bits */
2516 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
e7392364 2517 if (sh < 0) /* tbw something is wrong with indices */
a1751b22
SG		 2518 sh += 0x100;
2519
2520 if (agg->frame_count > (64 - sh)) {
2521 D_TX_REPLY("more frames than bitmap size");
2522 return -1;
2523 }
2524
2525 /* don't use 64-bit values for now */
2526 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2527
2528 /* check for success or failure according to the
2529 * transmitted bitmap and block-ack bitmap */
2530 sent_bitmap = bitmap & agg->bitmap;
2531
2532 /* For each frame attempted in aggregation,
2533 * update driver's record of tx frame's status. */
2534 i = 0;
2535 while (sent_bitmap) {
2536 ack = sent_bitmap & 1ULL;
2537 successes += ack;
e7392364
SG		 2538 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2539 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
a1751b22
SG		 2540 sent_bitmap >>= 1;
2541 ++i;
2542 }
2543
e7392364 2544 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
a1751b22 2545
00ea99e1 2546 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
a1751b22
SG		 2547 memset(&info->status, 0, sizeof(info->status));
2548 info->flags |= IEEE80211_TX_STAT_ACK;
2549 info->flags |= IEEE80211_TX_STAT_AMPDU;
2550 info->status.ampdu_ack_len = successes;
2551 info->status.ampdu_len = agg->frame_count;
2552 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2553
2554 return 0;
2555}
2556
3dfea27d
SG		 2557static inline bool
2558il4965_is_tx_success(u32 status)
2559{
2560 status &= TX_STATUS_MSK;
2561 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2562}
2563
2564static u8
2565il4965_find_station(struct il_priv *il, const u8 *addr)
2566{
2567 int i;
2568 int start = 0;
2569 int ret = IL_INVALID_STATION;
2570 unsigned long flags;
2571
2572 if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2573 start = IL_STA_ID;
2574
2575 if (is_broadcast_ether_addr(addr))
2576 return il->hw_params.bcast_id;
2577
2578 spin_lock_irqsave(&il->sta_lock, flags);
2579 for (i = start; i < il->hw_params.max_stations; i++)
2580 if (il->stations[i].used &&
2e42e474 2581 ether_addr_equal(il->stations[i].sta.sta.addr, addr)) {
3dfea27d
SG		 2582 ret = i;
2583 goto out;
2584 }
2585
2586 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2587
2588out:
2589 /*
2590 * It may be possible that more commands interacting with stations
2591 * arrive before we completed processing the adding of
2592 * station
2593 */
2594 if (ret != IL_INVALID_STATION &&
2595 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2596 ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2597 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2598 IL_ERR("Requested station info for sta %d before ready.\n",
2599 ret);
2600 ret = IL_INVALID_STATION;
2601 }
2602 spin_unlock_irqrestore(&il->sta_lock, flags);
2603 return ret;
2604}
2605
2606static int
2607il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2608{
2609 if (il->iw_mode == NL80211_IFTYPE_STATION)
2610 return IL_AP_ID;
2611 else {
2612 u8 *da = ieee80211_get_DA(hdr);
2613
2614 return il4965_find_station(il, da);
2615 }
2616}
2617
2618static inline u32
2619il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2620{
2621 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
2622}
2623
2624static inline u32
2625il4965_tx_status_to_mac80211(u32 status)
2626{
2627 status &= TX_STATUS_MSK;
2628
2629 switch (status) {
2630 case TX_STATUS_SUCCESS:
2631 case TX_STATUS_DIRECT_DONE:
2632 return IEEE80211_TX_STAT_ACK;
2633 case TX_STATUS_FAIL_DEST_PS:
2634 return IEEE80211_TX_STAT_TX_FILTERED;
2635 default:
2636 return 0;
2637 }
2638}
2639
2640/**
2641 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2642 */
2643static int
2644il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2645 struct il4965_tx_resp *tx_resp, int txq_id,
2646 u16 start_idx)
2647{
2648 u16 status;
2649 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2650 struct ieee80211_tx_info *info = NULL;
2651 struct ieee80211_hdr *hdr = NULL;
2652 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2653 int i, sh, idx;
2654 u16 seq;
2655 if (agg->wait_for_ba)
2656 D_TX_REPLY("got tx response w/o block-ack\n");
2657
2658 agg->frame_count = tx_resp->frame_count;
2659 agg->start_idx = start_idx;
2660 agg->rate_n_flags = rate_n_flags;
2661 agg->bitmap = 0;
2662
2663 /* num frames attempted by Tx command */
2664 if (agg->frame_count == 1) {
2665 /* Only one frame was attempted; no block-ack will arrive */
2666 status = le16_to_cpu(frame_status[0].status);
2667 idx = start_idx;
2668
2669 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2670 agg->frame_count, agg->start_idx, idx);
2671
2672 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2673 info->status.rates[0].count = tx_resp->failure_frame + 1;
2674 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2675 info->flags |= il4965_tx_status_to_mac80211(status);
2676 il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2677
2678 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2679 tx_resp->failure_frame);
2680 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2681
2682 agg->wait_for_ba = 0;
2683 } else {
2684 /* Two or more frames were attempted; expect block-ack */
2685 u64 bitmap = 0;
2686 int start = agg->start_idx;
2687 struct sk_buff *skb;
2688
2689 /* Construct bit-map of pending frames within Tx win */
2690 for (i = 0; i < agg->frame_count; i++) {
2691 u16 sc;
2692 status = le16_to_cpu(frame_status[i].status);
2693 seq = le16_to_cpu(frame_status[i].sequence);
2694 idx = SEQ_TO_IDX(seq);
2695 txq_id = SEQ_TO_QUEUE(seq);
2696
2697 if (status &
2698 (AGG_TX_STATE_FEW_BYTES_MSK |
2699 AGG_TX_STATE_ABORT_MSK))
2700 continue;
2701
2702 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2703 agg->frame_count, txq_id, idx);
2704
2705 skb = il->txq[txq_id].skbs[idx];
2706 if (WARN_ON_ONCE(skb == NULL))
2707 return -1;
2708 hdr = (struct ieee80211_hdr *) skb->data;
2709
2710 sc = le16_to_cpu(hdr->seq_ctrl);
2711 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2712 IL_ERR("BUG_ON idx doesn't match seq control"
2713 " idx=%d, seq_idx=%d, seq=%d\n", idx,
2714 SEQ_TO_SN(sc), hdr->seq_ctrl);
2715 return -1;
2716 }
2717
2718 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
2719 SEQ_TO_SN(sc));
2720
2721 sh = idx - start;
2722 if (sh > 64) {
2723 sh = (start - idx) + 0xff;
2724 bitmap = bitmap << sh;
2725 sh = 0;
2726 start = idx;
2727 } else if (sh < -64)
2728 sh = 0xff - (start - idx);
2729 else if (sh < 0) {
2730 sh = start - idx;
2731 start = idx;
2732 bitmap = bitmap << sh;
2733 sh = 0;
2734 }
2735 bitmap |= 1ULL << sh;
2736 D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2737 (unsigned long long)bitmap);
2738 }
2739
2740 agg->bitmap = bitmap;
2741 agg->start_idx = start;
2742 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2743 agg->frame_count, agg->start_idx,
2744 (unsigned long long)agg->bitmap);
2745
2746 if (bitmap)
2747 agg->wait_for_ba = 1;
2748 }
2749 return 0;
2750}
2751
2752/**
2753 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2754 */
2755static void
2756il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2757{
2758 struct il_rx_pkt *pkt = rxb_addr(rxb);
2759 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2760 int txq_id = SEQ_TO_QUEUE(sequence);
2761 int idx = SEQ_TO_IDX(sequence);
2762 struct il_tx_queue *txq = &il->txq[txq_id];
2763 struct sk_buff *skb;
2764 struct ieee80211_hdr *hdr;
2765 struct ieee80211_tx_info *info;
2766 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2767 u32 status = le32_to_cpu(tx_resp->u.status);
2768 int uninitialized_var(tid);
2769 int sta_id;
2770 int freed;
2771 u8 *qc = NULL;
2772 unsigned long flags;
2773
2774 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2775 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2776 "is out of range [0-%d] %d %d\n", txq_id, idx,
2777 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2778 return;
2779 }
2780
2781 txq->time_stamp = jiffies;
2782
2783 skb = txq->skbs[txq->q.read_ptr];
2784 info = IEEE80211_SKB_CB(skb);
2785 memset(&info->status, 0, sizeof(info->status));
2786
2787 hdr = (struct ieee80211_hdr *) skb->data;
2788 if (ieee80211_is_data_qos(hdr->frame_control)) {
2789 qc = ieee80211_get_qos_ctl(hdr);
2790 tid = qc[0] & 0xf;
2791 }
2792
2793 sta_id = il4965_get_ra_sta_id(il, hdr);
2794 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2795 IL_ERR("Station not known\n");
2796 return;
2797 }
2798
2799 spin_lock_irqsave(&il->sta_lock, flags);
2800 if (txq->sched_retry) {
2801 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2802 struct il_ht_agg *agg = NULL;
2803 WARN_ON(!qc);
2804
2805 agg = &il->stations[sta_id].tid[tid].agg;
2806
2807 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2808
2809 /* check if BAR is needed */
2810 if (tx_resp->frame_count == 1 &&
2811 !il4965_is_tx_success(status))
2812 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2813
2814 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2815 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2816 D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2817 "%d idx %d\n", scd_ssn, idx);
2818 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2819 if (qc)
2820 il4965_free_tfds_in_queue(il, sta_id, tid,
2821 freed);
2822
2823 if (il->mac80211_registered &&
2824 il_queue_space(&txq->q) > txq->q.low_mark &&
2825 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2826 il_wake_queue(il, txq);
2827 }
2828 } else {
2829 info->status.rates[0].count = tx_resp->failure_frame + 1;
2830 info->flags |= il4965_tx_status_to_mac80211(status);
2831 il4965_hwrate_to_tx_control(il,
2832 le32_to_cpu(tx_resp->rate_n_flags),
2833 info);
2834
2835 D_TX_REPLY("TXQ %d status %s (0x%08x) "
2836 "rate_n_flags 0x%x retries %d\n", txq_id,
2837 il4965_get_tx_fail_reason(status), status,
2838 le32_to_cpu(tx_resp->rate_n_flags),
2839 tx_resp->failure_frame);
2840
2841 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2842 if (qc && likely(sta_id != IL_INVALID_STATION))
2843 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2844 else if (sta_id == IL_INVALID_STATION)
2845 D_TX_REPLY("Station not known\n");
2846
2847 if (il->mac80211_registered &&
2848 il_queue_space(&txq->q) > txq->q.low_mark)
2849 il_wake_queue(il, txq);
2850 }
2851 if (qc && likely(sta_id != IL_INVALID_STATION))
2852 il4965_txq_check_empty(il, sta_id, tid, txq_id);
2853
2854 il4965_check_abort_status(il, tx_resp->frame_count, status);
2855
2856 spin_unlock_irqrestore(&il->sta_lock, flags);
2857}
2858
a1751b22
SG		 2859/**
2860 * translate ucode response to mac80211 tx status control values
2861 */
e7392364
SG		 2862void
2863il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2864 struct ieee80211_tx_info *info)
a1751b22 2865{
d748b464 2866 struct ieee80211_tx_rate *r = &info->status.rates[0];
a1751b22 2867
d748b464 2868 info->status.antenna =
e7392364 2869 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
a1751b22
SG		 2870 if (rate_n_flags & RATE_MCS_HT_MSK)
2871 r->flags |= IEEE80211_TX_RC_MCS;
2872 if (rate_n_flags & RATE_MCS_GF_MSK)
2873 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2874 if (rate_n_flags & RATE_MCS_HT40_MSK)
2875 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2876 if (rate_n_flags & RATE_MCS_DUP_MSK)
2877 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2878 if (rate_n_flags & RATE_MCS_SGI_MSK)
2879 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2880 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2881}
2882
2883/**
6e9848b4 2884 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
a1751b22
SG		 2885 *
2886 * Handles block-acknowledge notification from device, which reports success
2887 * of frames sent via aggregation.
2888 */
e7392364
SG		 2889void
2890il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 2891{
2892 struct il_rx_pkt *pkt = rxb_addr(rxb);
2893 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2894 struct il_tx_queue *txq = NULL;
2895 struct il_ht_agg *agg;
2896 int idx;
2897 int sta_id;
2898 int tid;
2899 unsigned long flags;
2900
2901 /* "flow" corresponds to Tx queue */
2902 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2903
2904 /* "ssn" is start of block-ack Tx win, corresponds to idx
2905 * (in Tx queue's circular buffer) of first TFD/frame in win */
2906 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2907
2908 if (scd_flow >= il->hw_params.max_txq_num) {
e7392364 2909 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
a1751b22
SG		 2910 return;
2911 }
2912
2913 txq = &il->txq[scd_flow];
2914 sta_id = ba_resp->sta_id;
2915 tid = ba_resp->tid;
2916 agg = &il->stations[sta_id].tid[tid].agg;
2917 if (unlikely(agg->txq_id != scd_flow)) {
2918 /*
2919 * FIXME: this is a uCode bug which need to be addressed,
2920 * log the information and return for now!
2921 * since it is possible happen very often and in order
2922 * not to fill the syslog, don't enable the logging by default
2923 */
e7392364
SG		 2924 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2925 scd_flow, agg->txq_id);
a1751b22
SG		 2926 return;
2927 }
2928
2929 /* Find idx just before block-ack win */
2930 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2931
2932 spin_lock_irqsave(&il->sta_lock, flags);
2933
e7392364 2934 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
1722f8e1 2935 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
e7392364
SG		 2936 ba_resp->sta_id);
2937 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2938 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2939 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2940 ba_resp->scd_flow, ba_resp->scd_ssn);
2941 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2942 (unsigned long long)agg->bitmap);
a1751b22
SG		 2943
2944 /* Update driver's record of ACK vs. not for each frame in win */
2945 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2946
2947 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2948 * block-ack win (we assume that they've been successfully
2949 * transmitted ... if not, it's too late anyway). */
2950 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2951 /* calculate mac80211 ampdu sw queue to wake */
2952 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2953 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2954
2955 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2956 il->mac80211_registered &&
2957 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2958 il_wake_queue(il, txq);
2959
2960 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2961 }
2962
2963 spin_unlock_irqrestore(&il->sta_lock, flags);
2964}
2965
2966#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2967const char *
2968il4965_get_tx_fail_reason(u32 status)
a1751b22
SG		 2969{
2970#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2971#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2972
2973 switch (status & TX_STATUS_MSK) {
2974 case TX_STATUS_SUCCESS:
2975 return "SUCCESS";
e7392364
SG		 2976 TX_STATUS_POSTPONE(DELAY);
2977 TX_STATUS_POSTPONE(FEW_BYTES);
2978 TX_STATUS_POSTPONE(QUIET_PERIOD);
2979 TX_STATUS_POSTPONE(CALC_TTAK);
2980 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2981 TX_STATUS_FAIL(SHORT_LIMIT);
2982 TX_STATUS_FAIL(LONG_LIMIT);
2983 TX_STATUS_FAIL(FIFO_UNDERRUN);
2984 TX_STATUS_FAIL(DRAIN_FLOW);
2985 TX_STATUS_FAIL(RFKILL_FLUSH);
2986 TX_STATUS_FAIL(LIFE_EXPIRE);
2987 TX_STATUS_FAIL(DEST_PS);
2988 TX_STATUS_FAIL(HOST_ABORTED);
2989 TX_STATUS_FAIL(BT_RETRY);
2990 TX_STATUS_FAIL(STA_INVALID);
2991 TX_STATUS_FAIL(FRAG_DROPPED);
2992 TX_STATUS_FAIL(TID_DISABLE);
2993 TX_STATUS_FAIL(FIFO_FLUSHED);
2994 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
2995 TX_STATUS_FAIL(PASSIVE_NO_RX);
2996 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
a1751b22
SG		 2997 }
2998
2999 return "UNKNOWN";
3000
3001#undef TX_STATUS_FAIL
3002#undef TX_STATUS_POSTPONE
3003}
3004#endif /* CONFIG_IWLEGACY_DEBUG */
3005
eb3cdfb7
SG		 3006static struct il_link_quality_cmd *
3007il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
3008{
3009 int i, r;
3010 struct il_link_quality_cmd *link_cmd;
3011 u32 rate_flags = 0;
3012 __le32 rate_n_flags;
3013
3014 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3015 if (!link_cmd) {
3016 IL_ERR("Unable to allocate memory for LQ cmd.\n");
3017 return NULL;
3018 }
3019 /* Set up the rate scaling to start at selected rate, fall back
3020 * all the way down to 1M in IEEE order, and then spin on 1M */
3021 if (il->band == IEEE80211_BAND_5GHZ)
3022 r = RATE_6M_IDX;
3023 else
3024 r = RATE_1M_IDX;
3025
3026 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3027 rate_flags |= RATE_MCS_CCK_MSK;
3028
e7392364
SG		 3029 rate_flags |=
3030 il4965_first_antenna(il->hw_params.
3031 valid_tx_ant) << RATE_MCS_ANT_POS;
616107ed 3032 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
eb3cdfb7
SG		 3033 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3034 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3035
3036 link_cmd->general_params.single_stream_ant_msk =
e7392364 3037 il4965_first_antenna(il->hw_params.valid_tx_ant);
eb3cdfb7
SG		 3038
3039 link_cmd->general_params.dual_stream_ant_msk =
e7392364
SG		 3040 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3041 valid_tx_ant);
eb3cdfb7
SG		 3042 if (!link_cmd->general_params.dual_stream_ant_msk) {
3043 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3044 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3045 link_cmd->general_params.dual_stream_ant_msk =
e7392364 3046 il->hw_params.valid_tx_ant;
eb3cdfb7
SG		 3047 }
3048
3049 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3050 link_cmd->agg_params.agg_time_limit =
e7392364 3051 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
eb3cdfb7
SG		 3052
3053 link_cmd->sta_id = sta_id;
3054
3055 return link_cmd;
3056}
3057
3058/*
3059 * il4965_add_bssid_station - Add the special IBSS BSSID station
3060 *
3061 * Function sleeps.
3062 */
3063int
83007196 3064il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
eb3cdfb7
SG		 3065{
3066 int ret;
3067 u8 sta_id;
3068 struct il_link_quality_cmd *link_cmd;
3069 unsigned long flags;
3070
3071 if (sta_id_r)
3072 *sta_id_r = IL_INVALID_STATION;
3073
83007196 3074 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
eb3cdfb7
SG		 3075 if (ret) {
3076 IL_ERR("Unable to add station %pM\n", addr);
3077 return ret;
3078 }
3079
3080 if (sta_id_r)
3081 *sta_id_r = sta_id;
3082
3083 spin_lock_irqsave(&il->sta_lock, flags);
3084 il->stations[sta_id].used |= IL_STA_LOCAL;
3085 spin_unlock_irqrestore(&il->sta_lock, flags);
3086
3087 /* Set up default rate scaling table in device's station table */
3088 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3089 if (!link_cmd) {
e7392364
SG		 3090 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3091 addr);
eb3cdfb7
SG		 3092 return -ENOMEM;
3093 }
3094
83007196 3095 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
eb3cdfb7
SG		 3096 if (ret)
3097 IL_ERR("Link quality command failed (%d)\n", ret);
3098
3099 spin_lock_irqsave(&il->sta_lock, flags);
3100 il->stations[sta_id].lq = link_cmd;
3101 spin_unlock_irqrestore(&il->sta_lock, flags);
3102
3103 return 0;
3104}
3105
e7392364 3106static int
83007196 3107il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
eb3cdfb7 3108{
d735f921 3109 int i;
eb3cdfb7
SG		 3110 u8 buff[sizeof(struct il_wep_cmd) +
3111 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3112 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
e7392364 3113 size_t cmd_size = sizeof(struct il_wep_cmd);
eb3cdfb7 3114 struct il_host_cmd cmd = {
d98e2942 3115 .id = C_WEPKEY,
eb3cdfb7
SG		 3116 .data = wep_cmd,
3117 .flags = CMD_SYNC,
3118 };
d735f921 3119 bool not_empty = false;
eb3cdfb7
SG		 3120
3121 might_sleep();
3122
e7392364
SG		 3123 memset(wep_cmd, 0,
3124 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
eb3cdfb7 3125
e7392364 3126 for (i = 0; i < WEP_KEYS_MAX; i++) {
d735f921
SG		 3127 u8 key_size = il->_4965.wep_keys[i].key_size;
3128
eb3cdfb7 3129 wep_cmd->key[i].key_idx = i;
d735f921 3130 if (key_size) {
eb3cdfb7 3131 wep_cmd->key[i].key_offset = i;
d735f921
SG		 3132 not_empty = true;
3133 } else
eb3cdfb7 3134 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
eb3cdfb7 3135
d735f921
SG		 3136 wep_cmd->key[i].key_size = key_size;
3137 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
eb3cdfb7
SG		 3138 }
3139
3140 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3141 wep_cmd->num_keys = WEP_KEYS_MAX;
3142
3143 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
eb3cdfb7
SG		 3144 cmd.len = cmd_size;
3145
3146 if (not_empty || send_if_empty)
3147 return il_send_cmd(il, &cmd);
3148 else
3149 return 0;
3150}
3151
e7392364 3152int
83007196 3153il4965_restore_default_wep_keys(struct il_priv *il)
eb3cdfb7
SG		 3154{
3155 lockdep_assert_held(&il->mutex);
3156
83007196 3157 return il4965_static_wepkey_cmd(il, false);
eb3cdfb7
SG		 3158}
3159
e7392364 3160int
83007196 3161il4965_remove_default_wep_key(struct il_priv *il,
e7392364 3162 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3163{
3164 int ret;
d735f921 3165 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3166
3167 lockdep_assert_held(&il->mutex);
3168
d735f921 3169 D_WEP("Removing default WEP key: idx=%d\n", idx);
eb3cdfb7 3170
d735f921 3171 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
eb3cdfb7 3172 if (il_is_rfkill(il)) {
e7392364 3173 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
eb3cdfb7
SG		 3174 /* but keys in device are clear anyway so return success */
3175 return 0;
3176 }
83007196 3177 ret = il4965_static_wepkey_cmd(il, 1);
d735f921 3178 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
eb3cdfb7
SG		 3179
3180 return ret;
3181}
3182
e7392364 3183int
83007196 3184il4965_set_default_wep_key(struct il_priv *il,
e7392364 3185 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3186{
3187 int ret;
d735f921
SG		 3188 int len = keyconf->keylen;
3189 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3190
3191 lockdep_assert_held(&il->mutex);
3192
d735f921 3193 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
eb3cdfb7
SG		 3194 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3195 return -EINVAL;
3196 }
3197
3198 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3199 keyconf->hw_key_idx = HW_KEY_DEFAULT;
8f9e5645 3200 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
eb3cdfb7 3201
d735f921
SG		 3202 il->_4965.wep_keys[idx].key_size = len;
3203 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
eb3cdfb7 3204
83007196 3205 ret = il4965_static_wepkey_cmd(il, false);
eb3cdfb7 3206
d735f921 3207 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
eb3cdfb7
SG		 3208 return ret;
3209}
3210
e7392364 3211static int
83007196 3212il4965_set_wep_dynamic_key_info(struct il_priv *il,
e7392364 3213 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3214{
3215 unsigned long flags;
3216 __le16 key_flags = 0;
3217 struct il_addsta_cmd sta_cmd;
3218
3219 lockdep_assert_held(&il->mutex);
3220
3221 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3222
3223 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3224 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3225 key_flags &= ~STA_KEY_FLG_INVALID;
3226
3227 if (keyconf->keylen == WEP_KEY_LEN_128)
3228 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3229
b16db50a 3230 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3231 key_flags |= STA_KEY_MULTICAST_MSK;
3232
3233 spin_lock_irqsave(&il->sta_lock, flags);
3234
3235 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3236 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3237 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3238
e7392364 3239 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3240
e7392364
SG		 3241 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3242 keyconf->keylen);
eb3cdfb7 3243
e7392364
SG		 3244 if ((il->stations[sta_id].sta.key.
3245 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3246 il->stations[sta_id].sta.key.key_offset =
e7392364 3247 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3248 /* else, we are overriding an existing key => no need to allocated room
3249 * in uCode. */
3250
3251 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3252 "no space for a new key");
eb3cdfb7
SG		 3253
3254 il->stations[sta_id].sta.key.key_flags = key_flags;
3255 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3256 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3257
3258 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3259 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3260 spin_unlock_irqrestore(&il->sta_lock, flags);
3261
3262 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3263}
3264
e7392364
SG		 3265static int
3266il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
e7392364 3267 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3268{
3269 unsigned long flags;
3270 __le16 key_flags = 0;
3271 struct il_addsta_cmd sta_cmd;
3272
3273 lockdep_assert_held(&il->mutex);
3274
3275 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3276 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3277 key_flags &= ~STA_KEY_FLG_INVALID;
3278
b16db50a 3279 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3280 key_flags |= STA_KEY_MULTICAST_MSK;
3281
3282 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3283
3284 spin_lock_irqsave(&il->sta_lock, flags);
3285 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3286 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3287
e7392364 3288 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3289
e7392364 3290 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3291
e7392364
SG		 3292 if ((il->stations[sta_id].sta.key.
3293 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3294 il->stations[sta_id].sta.key.key_offset =
e7392364 3295 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3296 /* else, we are overriding an existing key => no need to allocated room
3297 * in uCode. */
3298
3299 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3300 "no space for a new key");
eb3cdfb7
SG		 3301
3302 il->stations[sta_id].sta.key.key_flags = key_flags;
3303 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3304 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3305
3306 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3307 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3308 spin_unlock_irqrestore(&il->sta_lock, flags);
3309
3310 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3311}
3312
e7392364
SG		 3313static int
3314il4965_set_tkip_dynamic_key_info(struct il_priv *il,
e7392364 3315 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3316{
3317 unsigned long flags;
3318 int ret = 0;
3319 __le16 key_flags = 0;
3320
3321 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3322 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3323 key_flags &= ~STA_KEY_FLG_INVALID;
3324
b16db50a 3325 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3326 key_flags |= STA_KEY_MULTICAST_MSK;
3327
3328 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3329 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3330
3331 spin_lock_irqsave(&il->sta_lock, flags);
3332
3333 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3334 il->stations[sta_id].keyinfo.keylen = 16;
3335
e7392364
SG		 3336 if ((il->stations[sta_id].sta.key.
3337 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3338 il->stations[sta_id].sta.key.key_offset =
e7392364 3339 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3340 /* else, we are overriding an existing key => no need to allocated room
3341 * in uCode. */
3342
3343 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3344 "no space for a new key");
eb3cdfb7
SG		 3345
3346 il->stations[sta_id].sta.key.key_flags = key_flags;
3347
eb3cdfb7
SG		 3348 /* This copy is acutally not needed: we get the key with each TX */
3349 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3350
3351 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3352
3353 spin_unlock_irqrestore(&il->sta_lock, flags);
3354
3355 return ret;
3356}
3357
e7392364 3358void
83007196
SG		 3359il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3360 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
eb3cdfb7
SG		 3361{
3362 u8 sta_id;
3363 unsigned long flags;
3364 int i;
3365
3366 if (il_scan_cancel(il)) {
3367 /* cancel scan failed, just live w/ bad key and rely
3368 briefly on SW decryption */
3369 return;
3370 }
3371
83007196 3372 sta_id = il_sta_id_or_broadcast(il, sta);
eb3cdfb7
SG		 3373 if (sta_id == IL_INVALID_STATION)
3374 return;
3375
3376 spin_lock_irqsave(&il->sta_lock, flags);
3377
3378 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3379
3380 for (i = 0; i < 5; i++)
3381 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
e7392364 3382 cpu_to_le16(phase1key[i]);
eb3cdfb7
SG		 3383
3384 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3385 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3386
3387 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3388
3389 spin_unlock_irqrestore(&il->sta_lock, flags);
eb3cdfb7
SG		 3390}
3391
e7392364 3392int
83007196 3393il4965_remove_dynamic_key(struct il_priv *il,
e7392364 3394 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3395{
3396 unsigned long flags;
3397 u16 key_flags;
3398 u8 keyidx;
3399 struct il_addsta_cmd sta_cmd;
3400
3401 lockdep_assert_held(&il->mutex);
3402
d735f921 3403 il->_4965.key_mapping_keys--;
eb3cdfb7
SG		 3404
3405 spin_lock_irqsave(&il->sta_lock, flags);
3406 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3407 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3408
e7392364 3409 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
eb3cdfb7
SG		 3410
3411 if (keyconf->keyidx != keyidx) {
3412 /* We need to remove a key with idx different that the one
3413 * in the uCode. This means that the key we need to remove has
3414 * been replaced by another one with different idx.
3415 * Don't do anything and return ok
3416 */
3417 spin_unlock_irqrestore(&il->sta_lock, flags);
3418 return 0;
3419 }
3420
b48d9665 3421 if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) {
e7392364
SG		 3422 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3423 key_flags);
eb3cdfb7
SG		 3424 spin_unlock_irqrestore(&il->sta_lock, flags);
3425 return 0;
3426 }
3427
e7392364
SG		 3428 if (!test_and_clear_bit
3429 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
eb3cdfb7 3430 IL_ERR("idx %d not used in uCode key table.\n",
e7392364
SG		 3431 il->stations[sta_id].sta.key.key_offset);
3432 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3433 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
eb3cdfb7 3434 il->stations[sta_id].sta.key.key_flags =
e7392364 3435 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
b48d9665 3436 il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx;
eb3cdfb7
SG		 3437 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3438 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3439
3440 if (il_is_rfkill(il)) {
e7392364
SG		 3441 D_WEP
3442 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
eb3cdfb7
SG		 3443 spin_unlock_irqrestore(&il->sta_lock, flags);
3444 return 0;
3445 }
3446 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3447 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3448 spin_unlock_irqrestore(&il->sta_lock, flags);
3449
3450 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3451}
3452
e7392364 3453int
83007196
SG		 3454il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3455 u8 sta_id)
eb3cdfb7
SG		 3456{
3457 int ret;
3458
3459 lockdep_assert_held(&il->mutex);
3460
d735f921 3461 il->_4965.key_mapping_keys++;
eb3cdfb7
SG		 3462 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3463
3464 switch (keyconf->cipher) {
3465 case WLAN_CIPHER_SUITE_CCMP:
e7392364 3466 ret =
83007196 3467 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3468 break;
3469 case WLAN_CIPHER_SUITE_TKIP:
e7392364 3470 ret =
83007196 3471 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3472 break;
3473 case WLAN_CIPHER_SUITE_WEP40:
3474 case WLAN_CIPHER_SUITE_WEP104:
83007196 3475 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3476 break;
3477 default:
e7392364
SG		 3478 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3479 keyconf->cipher);
eb3cdfb7
SG		 3480 ret = -EINVAL;
3481 }
3482
e7392364
SG		 3483 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3484 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
eb3cdfb7
SG		 3485
3486 return ret;
3487}
3488
3489/**
3490 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3491 *
3492 * This adds the broadcast station into the driver's station table
3493 * and marks it driver active, so that it will be restored to the
3494 * device at the next best time.
3495 */
e7392364 3496int
83007196 3497il4965_alloc_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3498{
3499 struct il_link_quality_cmd *link_cmd;
3500 unsigned long flags;
3501 u8 sta_id;
3502
3503 spin_lock_irqsave(&il->sta_lock, flags);
83007196 3504 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
eb3cdfb7
SG		 3505 if (sta_id == IL_INVALID_STATION) {
3506 IL_ERR("Unable to prepare broadcast station\n");
3507 spin_unlock_irqrestore(&il->sta_lock, flags);
3508
3509 return -EINVAL;
3510 }
3511
3512 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3513 il->stations[sta_id].used |= IL_STA_BCAST;
3514 spin_unlock_irqrestore(&il->sta_lock, flags);
3515
3516 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3517 if (!link_cmd) {
e7392364
SG		 3518 IL_ERR
3519 ("Unable to initialize rate scaling for bcast station.\n");
eb3cdfb7
SG		 3520 return -ENOMEM;
3521 }
3522
3523 spin_lock_irqsave(&il->sta_lock, flags);
3524 il->stations[sta_id].lq = link_cmd;
3525 spin_unlock_irqrestore(&il->sta_lock, flags);
3526
3527 return 0;
3528}
3529
3530/**
3531 * il4965_update_bcast_station - update broadcast station's LQ command
3532 *
3533 * Only used by iwl4965. Placed here to have all bcast station management
3534 * code together.
3535 */
e7392364 3536static int
83007196 3537il4965_update_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3538{
3539 unsigned long flags;
3540 struct il_link_quality_cmd *link_cmd;
b16db50a 3541 u8 sta_id = il->hw_params.bcast_id;
eb3cdfb7
SG		 3542
3543 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3544 if (!link_cmd) {
1722f8e1 3545 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
eb3cdfb7
SG		 3546 return -ENOMEM;
3547 }
3548
3549 spin_lock_irqsave(&il->sta_lock, flags);
3550 if (il->stations[sta_id].lq)
3551 kfree(il->stations[sta_id].lq);
3552 else
1722f8e1 3553 D_INFO("Bcast sta rate scaling has not been initialized.\n");
eb3cdfb7
SG		 3554 il->stations[sta_id].lq = link_cmd;
3555 spin_unlock_irqrestore(&il->sta_lock, flags);
3556
3557 return 0;
3558}
3559
e7392364
SG		 3560int
3561il4965_update_bcast_stations(struct il_priv *il)
eb3cdfb7 3562{
83007196 3563 return il4965_update_bcast_station(il);
eb3cdfb7
SG		 3564}
3565
3566/**
3567 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3568 */
e7392364
SG		 3569int
3570il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
eb3cdfb7
SG		 3571{
3572 unsigned long flags;
3573 struct il_addsta_cmd sta_cmd;
3574
3575 lockdep_assert_held(&il->mutex);
3576
3577 /* Remove "disable" flag, to enable Tx for this TID */
3578 spin_lock_irqsave(&il->sta_lock, flags);
3579 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3580 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3581 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3582 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3583 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3584 spin_unlock_irqrestore(&il->sta_lock, flags);
3585
3586 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3587}
3588
e7392364
SG		 3589int
3590il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3591 u16 ssn)
eb3cdfb7
SG		 3592{
3593 unsigned long flags;
3594 int sta_id;
3595 struct il_addsta_cmd sta_cmd;
3596
3597 lockdep_assert_held(&il->mutex);
3598
3599 sta_id = il_sta_id(sta);
3600 if (sta_id == IL_INVALID_STATION)
3601 return -ENXIO;
3602
3603 spin_lock_irqsave(&il->sta_lock, flags);
3604 il->stations[sta_id].sta.station_flags_msk = 0;
3605 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
e7392364 3606 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3607 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3608 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3609 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3610 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3611 spin_unlock_irqrestore(&il->sta_lock, flags);
3612
3613 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3614}
3615
e7392364
SG		 3616int
3617il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
eb3cdfb7
SG		 3618{
3619 unsigned long flags;
3620 int sta_id;
3621 struct il_addsta_cmd sta_cmd;
3622
3623 lockdep_assert_held(&il->mutex);
3624
3625 sta_id = il_sta_id(sta);
3626 if (sta_id == IL_INVALID_STATION) {
3627 IL_ERR("Invalid station for AGG tid %d\n", tid);
3628 return -ENXIO;
3629 }
3630
3631 spin_lock_irqsave(&il->sta_lock, flags);
3632 il->stations[sta_id].sta.station_flags_msk = 0;
3633 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
e7392364 3634 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3635 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3636 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3637 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3638 spin_unlock_irqrestore(&il->sta_lock, flags);
3639
3640 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3641}
3642
3643void
3644il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3645{
3646 unsigned long flags;
3647
3648 spin_lock_irqsave(&il->sta_lock, flags);
3649 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3650 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3651 il->stations[sta_id].sta.sta.modify_mask =
e7392364 3652 STA_MODIFY_SLEEP_TX_COUNT_MSK;
eb3cdfb7
SG		 3653 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3654 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364 3655 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
eb3cdfb7
SG		 3656 spin_unlock_irqrestore(&il->sta_lock, flags);
3657
3658}
3659
e7392364
SG		 3660void
3661il4965_update_chain_flags(struct il_priv *il)
be663ab6 3662{
c9363551
SG		 3663 if (il->ops->set_rxon_chain) {
3664 il->ops->set_rxon_chain(il);
c8b03958 3665 if (il->active.rx_chain != il->staging.rx_chain)
83007196 3666 il_commit_rxon(il);
be663ab6
WYG		 3667 }
3668}
3669
e7392364
SG		 3670static void
3671il4965_clear_free_frames(struct il_priv *il)
be663ab6
WYG		 3672{
3673 struct list_head *element;
3674
e7392364 3675 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
be663ab6 3676
46bc8d4b
SG		 3677 while (!list_empty(&il->free_frames)) {
3678 element = il->free_frames.next;
be663ab6 3679 list_del(element);
e2ebc833 3680 kfree(list_entry(element, struct il_frame, list));
46bc8d4b 3681 il->frames_count--;
be663ab6
WYG		 3682 }
3683
46bc8d4b 3684 if (il->frames_count) {
9406f797 3685 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 3686 il->frames_count);
46bc8d4b 3687 il->frames_count = 0;
be663ab6
WYG		 3688 }
3689}
3690
e7392364
SG		 3691static struct il_frame *
3692il4965_get_free_frame(struct il_priv *il)
be663ab6 3693{
e2ebc833 3694 struct il_frame *frame;
be663ab6 3695 struct list_head *element;
46bc8d4b 3696 if (list_empty(&il->free_frames)) {
be663ab6
WYG		 3697 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3698 if (!frame) {
9406f797 3699 IL_ERR("Could not allocate frame!\n");
be663ab6
WYG		 3700 return NULL;
3701 }
3702
46bc8d4b 3703 il->frames_count++;
be663ab6
WYG		 3704 return frame;
3705 }
3706
46bc8d4b 3707 element = il->free_frames.next;
be663ab6 3708 list_del(element);
e2ebc833 3709 return list_entry(element, struct il_frame, list);
be663ab6
WYG		 3710}
3711
e7392364
SG		 3712static void
3713il4965_free_frame(struct il_priv *il, struct il_frame *frame)
be663ab6
WYG		 3714{
3715 memset(frame, 0, sizeof(*frame));
46bc8d4b 3716 list_add(&frame->list, &il->free_frames);
be663ab6
WYG		 3717}
3718
e7392364
SG		 3719static u32
3720il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3721 int left)
be663ab6 3722{
46bc8d4b 3723 lockdep_assert_held(&il->mutex);
be663ab6 3724
46bc8d4b 3725 if (!il->beacon_skb)
be663ab6
WYG		 3726 return 0;
3727
46bc8d4b 3728 if (il->beacon_skb->len > left)
be663ab6
WYG		 3729 return 0;
3730
46bc8d4b 3731 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
be663ab6 3732
46bc8d4b 3733 return il->beacon_skb->len;
be663ab6
WYG		 3734}
3735
3736/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
e7392364
SG		 3737static void
3738il4965_set_beacon_tim(struct il_priv *il,
3739 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3740 u32 frame_size)
be663ab6
WYG		 3741{
3742 u16 tim_idx;
3743 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3744
3745 /*
0c2c8852 3746 * The idx is relative to frame start but we start looking at the
be663ab6
WYG		 3747 * variable-length part of the beacon.
3748 */
3749 tim_idx = mgmt->u.beacon.variable - beacon;
3750
3751 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3752 while ((tim_idx < (frame_size - 2)) &&
e7392364
SG		 3753 (beacon[tim_idx] != WLAN_EID_TIM))
3754 tim_idx += beacon[tim_idx + 1] + 2;
be663ab6
WYG		 3755
3756 /* If TIM field was found, set variables */
3757 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3758 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
e7392364 3759 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
be663ab6 3760 } else
9406f797 3761 IL_WARN("Unable to find TIM Element in beacon\n");
be663ab6
WYG		 3762}
3763
e7392364
SG		 3764static unsigned int
3765il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
be663ab6 3766{
e2ebc833 3767 struct il_tx_beacon_cmd *tx_beacon_cmd;
be663ab6
WYG		 3768 u32 frame_size;
3769 u32 rate_flags;
3770 u32 rate;
3771 /*
3772 * We have to set up the TX command, the TX Beacon command, and the
3773 * beacon contents.
3774 */
3775
46bc8d4b 3776 lockdep_assert_held(&il->mutex);
be663ab6 3777
83007196
SG		 3778 if (!il->beacon_enabled) {
3779 IL_ERR("Trying to build beacon without beaconing enabled\n");
be663ab6
WYG		 3780 return 0;
3781 }
3782
3783 /* Initialize memory */
3784 tx_beacon_cmd = &frame->u.beacon;
3785 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3786
3787 /* Set up TX beacon contents */
e7392364
SG		 3788 frame_size =
3789 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3790 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
be663ab6
WYG		 3791 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3792 return 0;
3793 if (!frame_size)
3794 return 0;
3795
3796 /* Set up TX command fields */
e7392364 3797 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
b16db50a 3798 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
be663ab6 3799 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e7392364
SG		 3800 tx_beacon_cmd->tx.tx_flags =
3801 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3802 TX_CMD_FLG_STA_RATE_MSK;
be663ab6
WYG		 3803
3804 /* Set up TX beacon command fields */
e7392364
SG		 3805 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3806 frame_size);
be663ab6
WYG		 3807
3808 /* Set up packet rate and flags */
83007196 3809 rate = il_get_lowest_plcp(il);
a0c1ef3b 3810 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 3811 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
e2ebc833 3812 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
be663ab6 3813 rate_flags |= RATE_MCS_CCK_MSK;
616107ed 3814 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
be663ab6
WYG		 3815
3816 return sizeof(*tx_beacon_cmd) + frame_size;
3817}
3818
e7392364
SG		 3819int
3820il4965_send_beacon_cmd(struct il_priv *il)
be663ab6 3821{
e2ebc833 3822 struct il_frame *frame;
be663ab6
WYG		 3823 unsigned int frame_size;
3824 int rc;
3825
46bc8d4b 3826 frame = il4965_get_free_frame(il);
be663ab6 3827 if (!frame) {
9406f797 3828 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 3829 "command.\n");
be663ab6
WYG		 3830 return -ENOMEM;
3831 }
3832
46bc8d4b 3833 frame_size = il4965_hw_get_beacon_cmd(il, frame);
be663ab6 3834 if (!frame_size) {
9406f797 3835 IL_ERR("Error configuring the beacon command\n");
46bc8d4b 3836 il4965_free_frame(il, frame);
be663ab6
WYG		 3837 return -EINVAL;
3838 }
3839
e7392364 3840 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
be663ab6 3841
46bc8d4b 3842 il4965_free_frame(il, frame);
be663ab6
WYG		 3843
3844 return rc;
3845}
3846
e7392364
SG		 3847static inline dma_addr_t
3848il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
be663ab6 3849{
e2ebc833 3850 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3851
3852 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3853 if (sizeof(dma_addr_t) > sizeof(u32))
3854 addr |=
e7392364
SG		 3855 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3856 16;
be663ab6
WYG		 3857
3858 return addr;
3859}
3860
e7392364
SG		 3861static inline u16
3862il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
be663ab6 3863{
e2ebc833 3864 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3865
3866 return le16_to_cpu(tb->hi_n_len) >> 4;
3867}
3868
e7392364
SG		 3869static inline void
3870il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
be663ab6 3871{
e2ebc833 3872 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3873 u16 hi_n_len = len << 4;
3874
3875 put_unaligned_le32(addr, &tb->lo);
3876 if (sizeof(dma_addr_t) > sizeof(u32))
3877 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3878
3879 tb->hi_n_len = cpu_to_le16(hi_n_len);
3880
3881 tfd->num_tbs = idx + 1;
3882}
3883
e7392364
SG		 3884static inline u8
3885il4965_tfd_get_num_tbs(struct il_tfd *tfd)
be663ab6
WYG		 3886{
3887 return tfd->num_tbs & 0x1f;
3888}
3889
3890/**
e2ebc833 3891 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
46bc8d4b 3892 * @il - driver ilate data
be663ab6
WYG		 3893 * @txq - tx queue
3894 *
0c2c8852 3895 * Does NOT advance any TFD circular buffer read/write idxes
be663ab6
WYG		 3896 * Does NOT free the TFD itself (which is within circular buffer)
3897 */
e7392364
SG		 3898void
3899il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
be663ab6 3900{
e2ebc833
SG		 3901 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3902 struct il_tfd *tfd;
46bc8d4b 3903 struct pci_dev *dev = il->pci_dev;
0c2c8852 3904 int idx = txq->q.read_ptr;
be663ab6
WYG		 3905 int i;
3906 int num_tbs;
3907
0c2c8852 3908 tfd = &tfd_tmp[idx];
be663ab6
WYG		 3909
3910 /* Sanity check on number of chunks */
e2ebc833 3911 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6 3912
e2ebc833 3913 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3914 IL_ERR("Too many chunks: %i\n", num_tbs);
be663ab6
WYG		 3915 /* @todo issue fatal error, it is quite serious situation */
3916 return;
3917 }
3918
3919 /* Unmap tx_cmd */
3920 if (num_tbs)
e7392364
SG		 3921 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3922 dma_unmap_len(&txq->meta[idx], len),
3923 PCI_DMA_BIDIRECTIONAL);
be663ab6
WYG		 3924
3925 /* Unmap chunks, if any. */
3926 for (i = 1; i < num_tbs; i++)
e2ebc833 3927 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
e7392364
SG		 3928 il4965_tfd_tb_get_len(tfd, i),
3929 PCI_DMA_TODEVICE);
be663ab6
WYG		 3930
3931 /* free SKB */
00ea99e1
SG		 3932 if (txq->skbs) {
3933 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
be663ab6
WYG		 3934
3935 /* can be called from irqs-disabled context */
3936 if (skb) {
3937 dev_kfree_skb_any(skb);
00ea99e1 3938 txq->skbs[txq->q.read_ptr] = NULL;
be663ab6
WYG		 3939 }
3940 }
3941}
3942
e7392364
SG		 3943int
3944il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3945 dma_addr_t addr, u16 len, u8 reset, u8 pad)
be663ab6 3946{
e2ebc833
SG		 3947 struct il_queue *q;
3948 struct il_tfd *tfd, *tfd_tmp;
be663ab6
WYG		 3949 u32 num_tbs;
3950
3951 q = &txq->q;
e2ebc833 3952 tfd_tmp = (struct il_tfd *)txq->tfds;
be663ab6
WYG		 3953 tfd = &tfd_tmp[q->write_ptr];
3954
3955 if (reset)
3956 memset(tfd, 0, sizeof(*tfd));
3957
e2ebc833 3958 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6
WYG		 3959
3960 /* Each TFD can point to a maximum 20 Tx buffers */
e2ebc833 3961 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3962 IL_ERR("Error can not send more than %d chunks\n",
e7392364 3963 IL_NUM_OF_TBS);
be663ab6
WYG		 3964 return -EINVAL;
3965 }
3966
3967 BUG_ON(addr & ~DMA_BIT_MASK(36));
e2ebc833 3968 if (unlikely(addr & ~IL_TX_DMA_MASK))
e7392364 3969 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
be663ab6 3970
e2ebc833 3971 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
be663ab6
WYG		 3972
3973 return 0;
3974}
3975
3976/*
3977 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3978 * given Tx queue, and enable the DMA channel used for that queue.
3979 *
3980 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3981 * channels supported in hardware.
3982 */
e7392364
SG		 3983int
3984il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
be663ab6
WYG		 3985{
3986 int txq_id = txq->q.id;
3987
3988 /* Circular buffer (TFD queue in DRAM) physical base address */
e7392364 3989 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
be663ab6
WYG		 3990
3991 return 0;
3992}
3993
3994/******************************************************************************
3995 *
3996 * Generic RX handler implementations
3997 *
3998 ******************************************************************************/
e7392364
SG		 3999static void
4000il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4001{
dcae1c64 4002 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4003 struct il_alive_resp *palive;
be663ab6
WYG		 4004 struct delayed_work *pwork;
4005
4006 palive = &pkt->u.alive_frame;
4007
e7392364
SG		 4008 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
4009 palive->is_valid, palive->ver_type, palive->ver_subtype);
be663ab6
WYG		 4010
4011 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 4012 D_INFO("Initialization Alive received.\n");
e7392364 4013 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 4014 sizeof(struct il_init_alive_resp));
46bc8d4b 4015 pwork = &il->init_alive_start;
be663ab6 4016 } else {
58de00a4 4017 D_INFO("Runtime Alive received.\n");
46bc8d4b 4018 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 4019 sizeof(struct il_alive_resp));
46bc8d4b 4020 pwork = &il->alive_start;
be663ab6
WYG		 4021 }
4022
4023 /* We delay the ALIVE response by 5ms to
4024 * give the HW RF Kill time to activate... */
4025 if (palive->is_valid == UCODE_VALID_OK)
e7392364 4026 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
be663ab6 4027 else
9406f797 4028 IL_WARN("uCode did not respond OK.\n");
be663ab6
WYG		 4029}
4030
4031/**
ebf0d90d 4032 * il4965_bg_stats_periodic - Timer callback to queue stats
be663ab6 4033 *
ebf0d90d 4034 * This callback is provided in order to send a stats request.
be663ab6
WYG		 4035 *
4036 * This timer function is continually reset to execute within
527901d0
SG		 4037 * 60 seconds since the last N_STATS was received. We need to
4038 * ensure we receive the stats in order to update the temperature
4039 * used for calibrating the TXPOWER.
be663ab6 4040 */
e7392364
SG		 4041static void
4042il4965_bg_stats_periodic(unsigned long data)
be663ab6 4043{
46bc8d4b 4044 struct il_priv *il = (struct il_priv *)data;
be663ab6 4045
a6766ccd 4046 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4047 return;
4048
4049 /* dont send host command if rf-kill is on */
46bc8d4b 4050 if (!il_is_ready_rf(il))
be663ab6
WYG		 4051 return;
4052
ebf0d90d 4053 il_send_stats_request(il, CMD_ASYNC, false);
be663ab6
WYG		 4054}
4055
e7392364
SG		 4056static void
4057il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4058{
dcae1c64 4059 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4060 struct il4965_beacon_notif *beacon =
e7392364 4061 (struct il4965_beacon_notif *)pkt->u.raw;
d3175167 4062#ifdef CONFIG_IWLEGACY_DEBUG
e2ebc833 4063 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
be663ab6 4064
5bf0dac4 4065 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
e7392364
SG		 4066 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4067 beacon->beacon_notify_hdr.failure_frame,
4068 le32_to_cpu(beacon->ibss_mgr_status),
4069 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
be663ab6 4070#endif
46bc8d4b 4071 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
be663ab6
WYG		 4072}
4073
e7392364
SG		 4074static void
4075il4965_perform_ct_kill_task(struct il_priv *il)
be663ab6
WYG		 4076{
4077 unsigned long flags;
4078
58de00a4 4079 D_POWER("Stop all queues\n");
be663ab6 4080
46bc8d4b
SG		 4081 if (il->mac80211_registered)
4082 ieee80211_stop_queues(il->hw);
be663ab6 4083
841b2cca 4084 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4085 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
841b2cca 4086 _il_rd(il, CSR_UCODE_DRV_GP1);
be663ab6 4087
46bc8d4b 4088 spin_lock_irqsave(&il->reg_lock, flags);
1e0f32a4 4089 if (likely(_il_grab_nic_access(il)))
13882269 4090 _il_release_nic_access(il);
46bc8d4b 4091 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6
WYG		 4092}
4093
4094/* Handle notification from uCode that card's power state is changing
4095 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG		 4096static void
4097il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4098{
dcae1c64 4099 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4100 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 4101 unsigned long status = il->status;
be663ab6 4102
58de00a4 4103 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
e7392364
SG		 4104 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4105 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4106 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
be663ab6 4107
e7392364 4108 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
be663ab6 4109
841b2cca 4110 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4111 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6 4112
e7392364 4113 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4114
4115 if (!(flags & RXON_CARD_DISABLED)) {
841b2cca 4116 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 4117 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0c1a94e2 4118 il_wr(il, HBUS_TARG_MBX_C,
e7392364 4119 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4120 }
4121 }
4122
4123 if (flags & CT_CARD_DISABLED)
46bc8d4b 4124 il4965_perform_ct_kill_task(il);
be663ab6
WYG		 4125
4126 if (flags & HW_CARD_DISABLED)
bc269a8e 4127 set_bit(S_RFKILL, &il->status);
be663ab6 4128 else
bc269a8e 4129 clear_bit(S_RFKILL, &il->status);
be663ab6
WYG		 4130
4131 if (!(flags & RXON_CARD_DISABLED))
46bc8d4b 4132 il_scan_cancel(il);
be663ab6 4133
bc269a8e
SG		 4134 if ((test_bit(S_RFKILL, &status) !=
4135 test_bit(S_RFKILL, &il->status)))
46bc8d4b 4136 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 4137 test_bit(S_RFKILL, &il->status));
be663ab6 4138 else
46bc8d4b 4139 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4140}
4141
4142/**
d0c72347 4143 * il4965_setup_handlers - Initialize Rx handler callbacks
be663ab6
WYG		 4144 *
4145 * Setup the RX handlers for each of the reply types sent from the uCode
4146 * to the host.
4147 *
4148 * This function chains into the hardware specific files for them to setup
4149 * any hardware specific handlers as well.
4150 */
e7392364
SG		 4151static void
4152il4965_setup_handlers(struct il_priv *il)
be663ab6 4153{
6e9848b4
SG		 4154 il->handlers[N_ALIVE] = il4965_hdl_alive;
4155 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 4156 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 4157 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 4158 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 4159 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 4160 il->handlers[N_BEACON] = il4965_hdl_beacon;
be663ab6
WYG		 4161
4162 /*
4163 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG		 4164 * stats request from the host as well as for the periodic
4165 * stats notifications (after received beacons) from the uCode.
be663ab6 4166 */
d2dfb33e
SG		 4167 il->handlers[C_STATS] = il4965_hdl_c_stats;
4168 il->handlers[N_STATS] = il4965_hdl_stats;
be663ab6 4169
46bc8d4b 4170 il_setup_rx_scan_handlers(il);
be663ab6
WYG		 4171
4172 /* status change handler */
e7392364 4173 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
be663ab6 4174
e7392364 4175 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
be663ab6 4176 /* Rx handlers */
6e9848b4
SG		 4177 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4178 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
3dfea27d 4179 il->handlers[N_RX] = il4965_hdl_rx;
be663ab6 4180 /* block ack */
6e9848b4 4181 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
3dfea27d
SG		 4182 /* Tx response */
4183 il->handlers[C_TX] = il4965_hdl_tx;
be663ab6
WYG		 4184}
4185
4186/**
e2ebc833 4187 * il4965_rx_handle - Main entry function for receiving responses from uCode
be663ab6 4188 *
d0c72347 4189 * Uses the il->handlers callback function array to invoke
be663ab6
WYG		 4190 * the appropriate handlers, including command responses,
4191 * frame-received notifications, and other notifications.
4192 */
e7392364
SG		 4193void
4194il4965_rx_handle(struct il_priv *il)
be663ab6 4195{
b73bb5f1 4196 struct il_rx_buf *rxb;
dcae1c64 4197 struct il_rx_pkt *pkt;
46bc8d4b 4198 struct il_rx_queue *rxq = &il->rxq;
be663ab6
WYG		 4199 u32 r, i;
4200 int reclaim;
4201 unsigned long flags;
4202 u8 fill_rx = 0;
4203 u32 count = 8;
4204 int total_empty;
4205
0c2c8852 4206 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
be663ab6 4207 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 4208 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
be663ab6
WYG		 4209 i = rxq->read;
4210
4211 /* Rx interrupt, but nothing sent from uCode */
4212 if (i == r)
58de00a4 4213 D_RX("r = %d, i = %d\n", r, i);
be663ab6
WYG		 4214
4215 /* calculate total frames need to be restock after handling RX */
4216 total_empty = r - rxq->write_actual;
4217 if (total_empty < 0)
4218 total_empty += RX_QUEUE_SIZE;
4219
4220 if (total_empty > (RX_QUEUE_SIZE / 2))
4221 fill_rx = 1;
4222
4223 while (i != r) {
4224 int len;
4225
4226 rxb = rxq->queue[i];
4227
4228 /* If an RXB doesn't have a Rx queue slot associated with it,
4229 * then a bug has been introduced in the queue refilling
4230 * routines -- catch it here */
4231 BUG_ON(rxb == NULL);
4232
4233 rxq->queue[i] = NULL;
4234
46bc8d4b
SG		 4235 pci_unmap_page(il->pci_dev, rxb->page_dma,
4236 PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 4237 PCI_DMA_FROMDEVICE);
4238 pkt = rxb_addr(rxb);
4239
e94a4099 4240 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 4241 len += sizeof(u32); /* account for status word */
be663ab6
WYG		 4242
4243 /* Reclaim a command buffer only if this packet is a response
4244 * to a (driver-originated) command.
4245 * If the packet (e.g. Rx frame) originated from uCode,
4246 * there is no command buffer to reclaim.
4247 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4248 * but apparently a few don't get set; catch them here. */
4249 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364
SG		 4250 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
4251 (pkt->hdr.cmd != N_RX_MPDU) &&
4252 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
4253 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
be663ab6
WYG		 4254
4255 /* Based on type of command response or notification,
4256 * handle those that need handling via function in
d0c72347
SG		 4257 * handlers table. See il4965_setup_handlers() */
4258 if (il->handlers[pkt->hdr.cmd]) {
e7392364
SG		 4259 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4260 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG		 4261 il->isr_stats.handlers[pkt->hdr.cmd]++;
4262 il->handlers[pkt->hdr.cmd] (il, rxb);
be663ab6
WYG		 4263 } else {
4264 /* No handling needed */
e7392364
SG		 4265 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4266 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
be663ab6
WYG		 4267 }
4268
4269 /*
4270 * XXX: After here, we should always check rxb->page
4271 * against NULL before touching it or its virtual
d0c72347 4272 * memory (pkt). Because some handler might have
be663ab6
WYG		 4273 * already taken or freed the pages.
4274 */
4275
4276 if (reclaim) {
4277 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 4278 * and fire off the (possibly) blocking il_send_cmd()
be663ab6
WYG		 4279 * as we reclaim the driver command queue */
4280 if (rxb->page)
46bc8d4b 4281 il_tx_cmd_complete(il, rxb);
be663ab6 4282 else
9406f797 4283 IL_WARN("Claim null rxb?\n");
be663ab6
WYG		 4284 }
4285
4286 /* Reuse the page if possible. For notification packets and
4287 * SKBs that fail to Rx correctly, add them back into the
4288 * rx_free list for reuse later. */
4289 spin_lock_irqsave(&rxq->lock, flags);
4290 if (rxb->page != NULL) {
e7392364
SG		 4291 rxb->page_dma =
4292 pci_map_page(il->pci_dev, rxb->page, 0,
4293 PAGE_SIZE << il->hw_params.
4294 rx_page_order, PCI_DMA_FROMDEVICE);
be663ab6
WYG		 4295 list_add_tail(&rxb->list, &rxq->rx_free);
4296 rxq->free_count++;
4297 } else
4298 list_add_tail(&rxb->list, &rxq->rx_used);
4299
4300 spin_unlock_irqrestore(&rxq->lock, flags);
4301
4302 i = (i + 1) & RX_QUEUE_MASK;
4303 /* If there are a lot of unused frames,
4304 * restock the Rx queue so ucode wont assert. */
4305 if (fill_rx) {
4306 count++;
4307 if (count >= 8) {
4308 rxq->read = i;
46bc8d4b 4309 il4965_rx_replenish_now(il);
be663ab6
WYG		 4310 count = 0;
4311 }
4312 }
4313 }
4314
4315 /* Backtrack one entry */
4316 rxq->read = i;
4317 if (fill_rx)
46bc8d4b 4318 il4965_rx_replenish_now(il);
be663ab6 4319 else
46bc8d4b 4320 il4965_rx_queue_restock(il);
be663ab6
WYG		 4321}
4322
4323/* call this function to flush any scheduled tasklet */
e7392364
SG		 4324static inline void
4325il4965_synchronize_irq(struct il_priv *il)
be663ab6 4326{
e7392364 4327 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG		 4328 synchronize_irq(il->pci_dev->irq);
4329 tasklet_kill(&il->irq_tasklet);
be663ab6
WYG		 4330}
4331
e7392364
SG		 4332static void
4333il4965_irq_tasklet(struct il_priv *il)
be663ab6
WYG		 4334{
4335 u32 inta, handled = 0;
4336 u32 inta_fh;
4337 unsigned long flags;
4338 u32 i;
d3175167 4339#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4340 u32 inta_mask;
4341#endif
4342
46bc8d4b 4343 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4344
4345 /* Ack/clear/reset pending uCode interrupts.
4346 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4347 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG		 4348 inta = _il_rd(il, CSR_INT);
4349 _il_wr(il, CSR_INT, inta);
be663ab6
WYG		 4350
4351 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4352 * Any new interrupts that happen after this, either while we're
4353 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG		 4354 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4355 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
be663ab6 4356
d3175167 4357#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4358 if (il_get_debug_level(il) & IL_DL_ISR) {
be663ab6 4359 /* just for debug */
841b2cca 4360 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG		 4361 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4362 inta_mask, inta_fh);
be663ab6
WYG		 4363 }
4364#endif
4365
46bc8d4b 4366 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4367
4368 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4369 * atomic, make sure that inta covers all the interrupts that
4370 * we've discovered, even if FH interrupt came in just after
4371 * reading CSR_INT. */
4372 if (inta_fh & CSR49_FH_INT_RX_MASK)
4373 inta |= CSR_INT_BIT_FH_RX;
4374 if (inta_fh & CSR49_FH_INT_TX_MASK)
4375 inta |= CSR_INT_BIT_FH_TX;
4376
4377 /* Now service all interrupt bits discovered above. */
4378 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 4379 IL_ERR("Hardware error detected. Restarting.\n");
be663ab6
WYG		 4380
4381 /* Tell the device to stop sending interrupts */
46bc8d4b 4382 il_disable_interrupts(il);
be663ab6 4383
46bc8d4b
SG		 4384 il->isr_stats.hw++;
4385 il_irq_handle_error(il);
be663ab6
WYG		 4386
4387 handled |= CSR_INT_BIT_HW_ERR;
4388
4389 return;
4390 }
d3175167 4391#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4392 if (il_get_debug_level(il) & (IL_DL_ISR)) {
be663ab6
WYG		 4393 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4394 if (inta & CSR_INT_BIT_SCD) {
58de00a4 4395 D_ISR("Scheduler finished to transmit "
e7392364 4396 "the frame/frames.\n");
46bc8d4b 4397 il->isr_stats.sch++;
be663ab6
WYG		 4398 }
4399
4400 /* Alive notification via Rx interrupt will do the real work */
4401 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 4402 D_ISR("Alive interrupt\n");
46bc8d4b 4403 il->isr_stats.alive++;
be663ab6
WYG		 4404 }
4405 }
4406#endif
4407 /* Safely ignore these bits for debug checks below */
4408 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4409
4410 /* HW RF KILL switch toggled */
4411 if (inta & CSR_INT_BIT_RF_KILL) {
4412 int hw_rf_kill = 0;
c9363551
SG		 4413
4414 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4415 hw_rf_kill = 1;
4416
9406f797 4417 IL_WARN("RF_KILL bit toggled to %s.\n",
e7392364 4418 hw_rf_kill ? "disable radio" : "enable radio");
be663ab6 4419
46bc8d4b 4420 il->isr_stats.rfkill++;
be663ab6
WYG		 4421
4422 /* driver only loads ucode once setting the interface up.
4423 * the driver allows loading the ucode even if the radio
4424 * is killed. Hence update the killswitch state here. The
4425 * rfkill handler will care about restarting if needed.
4426 */
a6766ccd 4427 if (!test_bit(S_ALIVE, &il->status)) {
be663ab6 4428 if (hw_rf_kill)
bc269a8e 4429 set_bit(S_RFKILL, &il->status);
be663ab6 4430 else
bc269a8e 4431 clear_bit(S_RFKILL, &il->status);
46bc8d4b 4432 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
be663ab6
WYG		 4433 }
4434
4435 handled |= CSR_INT_BIT_RF_KILL;
4436 }
4437
4438 /* Chip got too hot and stopped itself */
4439 if (inta & CSR_INT_BIT_CT_KILL) {
9406f797 4440 IL_ERR("Microcode CT kill error detected.\n");
46bc8d4b 4441 il->isr_stats.ctkill++;
be663ab6
WYG		 4442 handled |= CSR_INT_BIT_CT_KILL;
4443 }
4444
4445 /* Error detected by uCode */
4446 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG		 4447 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4448 inta);
46bc8d4b
SG		 4449 il->isr_stats.sw++;
4450 il_irq_handle_error(il);
be663ab6
WYG		 4451 handled |= CSR_INT_BIT_SW_ERR;
4452 }
4453
4454 /*
4455 * uCode wakes up after power-down sleep.
4456 * Tell device about any new tx or host commands enqueued,
4457 * and about any Rx buffers made available while asleep.
4458 */
4459 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 4460 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG		 4461 il_rx_queue_update_write_ptr(il, &il->rxq);
4462 for (i = 0; i < il->hw_params.max_txq_num; i++)
4463 il_txq_update_write_ptr(il, &il->txq[i]);
4464 il->isr_stats.wakeup++;
be663ab6
WYG		 4465 handled |= CSR_INT_BIT_WAKEUP;
4466 }
4467
4468 /* All uCode command responses, including Tx command responses,
4469 * Rx "responses" (frame-received notification), and other
4470 * notifications from uCode come through here*/
4471 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG		 4472 il4965_rx_handle(il);
4473 il->isr_stats.rx++;
be663ab6
WYG		 4474 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4475 }
4476
4477 /* This "Tx" DMA channel is used only for loading uCode */
4478 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 4479 D_ISR("uCode load interrupt\n");
46bc8d4b 4480 il->isr_stats.tx++;
be663ab6
WYG		 4481 handled |= CSR_INT_BIT_FH_TX;
4482 /* Wake up uCode load routine, now that load is complete */
46bc8d4b
SG		 4483 il->ucode_write_complete = 1;
4484 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4485 }
4486
4487 if (inta & ~handled) {
9406f797 4488 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 4489 il->isr_stats.unhandled++;
be663ab6
WYG		 4490 }
4491
46bc8d4b 4492 if (inta & ~(il->inta_mask)) {
9406f797 4493 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 4494 inta & ~il->inta_mask);
9a95b370 4495 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
be663ab6
WYG		 4496 }
4497
4498 /* Re-enable all interrupts */
93fd74e3 4499 /* only Re-enable if disabled by irq */
a6766ccd 4500 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 4501 il_enable_interrupts(il);
a078a1fd
SG		 4502 /* Re-enable RF_KILL if it occurred */
4503 else if (handled & CSR_INT_BIT_RF_KILL)
46bc8d4b 4504 il_enable_rfkill_int(il);
be663ab6 4505
d3175167 4506#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4507 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG		 4508 inta = _il_rd(il, CSR_INT);
4509 inta_mask = _il_rd(il, CSR_INT_MASK);
4510 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
e7392364
SG		 4511 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4512 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
be663ab6
WYG		 4513 }
4514#endif
4515}
4516
4517/*****************************************************************************
4518 *
4519 * sysfs attributes
4520 *
4521 *****************************************************************************/
4522
d3175167 4523#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4524
4525/*
4526 * The following adds a new attribute to the sysfs representation
4527 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4528 * used for controlling the debug level.
4529 *
4530 * See the level definitions in iwl for details.
4531 *
4532 * The debug_level being managed using sysfs below is a per device debug
4533 * level that is used instead of the global debug level if it (the per
4534 * device debug level) is set.
4535 */
e7392364
SG		 4536static ssize_t
4537il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4538 char *buf)
be663ab6 4539{
46bc8d4b
SG		 4540 struct il_priv *il = dev_get_drvdata(d);
4541 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
be663ab6 4542}
e7392364
SG		 4543
4544static ssize_t
4545il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4546 const char *buf, size_t count)
be663ab6 4547{
46bc8d4b 4548 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4549 unsigned long val;
4550 int ret;
4551
4552 ret = strict_strtoul(buf, 0, &val);
4553 if (ret)
9406f797 4554 IL_ERR("%s is not in hex or decimal form.\n", buf);
288f9954 4555 else
46bc8d4b 4556 il->debug_level = val;
288f9954 4557
be663ab6
WYG		 4558 return strnlen(buf, count);
4559}
4560
e7392364
SG		 4561static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4562 il4965_store_debug_level);
be663ab6 4563
d3175167 4564#endif /* CONFIG_IWLEGACY_DEBUG */
be663ab6 4565
e7392364
SG		 4566static ssize_t
4567il4965_show_temperature(struct device *d, struct device_attribute *attr,
4568 char *buf)
be663ab6 4569{
46bc8d4b 4570 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4571
46bc8d4b 4572 if (!il_is_alive(il))
be663ab6
WYG		 4573 return -EAGAIN;
4574
46bc8d4b 4575 return sprintf(buf, "%d\n", il->temperature);
be663ab6
WYG		 4576}
4577
e2ebc833 4578static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
be663ab6 4579
e7392364
SG		 4580static ssize_t
4581il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
be663ab6 4582{
46bc8d4b 4583 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4584
46bc8d4b 4585 if (!il_is_ready_rf(il))
be663ab6
WYG		 4586 return sprintf(buf, "off\n");
4587 else
46bc8d4b 4588 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
be663ab6
WYG		 4589}
4590
e7392364
SG		 4591static ssize_t
4592il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4593 const char *buf, size_t count)
be663ab6 4594{
46bc8d4b 4595 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4596 unsigned long val;
4597 int ret;
4598
4599 ret = strict_strtoul(buf, 10, &val);
4600 if (ret)
9406f797 4601 IL_INFO("%s is not in decimal form.\n", buf);
be663ab6 4602 else {
46bc8d4b 4603 ret = il_set_tx_power(il, val, false);
be663ab6 4604 if (ret)
e7392364 4605 IL_ERR("failed setting tx power (0x%d).\n", ret);
be663ab6
WYG		 4606 else
4607 ret = count;
4608 }
4609 return ret;
4610}
4611
e7392364
SG		 4612static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4613 il4965_store_tx_power);
be663ab6 4614
e2ebc833 4615static struct attribute *il_sysfs_entries[] = {
be663ab6
WYG		 4616 &dev_attr_temperature.attr,
4617 &dev_attr_tx_power.attr,
d3175167 4618#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4619 &dev_attr_debug_level.attr,
4620#endif
4621 NULL
4622};
4623
e2ebc833 4624static struct attribute_group il_attribute_group = {
be663ab6 4625 .name = NULL, /* put in device directory */
e2ebc833 4626 .attrs = il_sysfs_entries,
be663ab6
WYG		 4627};
4628
4629/******************************************************************************
4630 *
4631 * uCode download functions
4632 *
4633 ******************************************************************************/
4634
e7392364
SG		 4635static void
4636il4965_dealloc_ucode_pci(struct il_priv *il)
be663ab6 4637{
46bc8d4b
SG		 4638 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4639 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4640 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4641 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4642 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4643 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6
WYG		 4644}
4645
e7392364
SG		 4646static void
4647il4965_nic_start(struct il_priv *il)
be663ab6
WYG		 4648{
4649 /* Remove all resets to allow NIC to operate */
841b2cca 4650 _il_wr(il, CSR_RESET, 0);
be663ab6
WYG		 4651}
4652
e2ebc833 4653static void il4965_ucode_callback(const struct firmware *ucode_raw,
e7392364
SG		 4654 void *context);
4655static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
be663ab6 4656
e7392364
SG		 4657static int __must_check
4658il4965_request_firmware(struct il_priv *il, bool first)
be663ab6 4659{
46bc8d4b 4660 const char *name_pre = il->cfg->fw_name_pre;
be663ab6
WYG		 4661 char tag[8];
4662
4663 if (first) {
0c2c8852
SG		 4664 il->fw_idx = il->cfg->ucode_api_max;
4665 sprintf(tag, "%d", il->fw_idx);
be663ab6 4666 } else {
0c2c8852
SG		 4667 il->fw_idx--;
4668 sprintf(tag, "%d", il->fw_idx);
be663ab6
WYG		 4669 }
4670
0c2c8852 4671 if (il->fw_idx < il->cfg->ucode_api_min) {
9406f797 4672 IL_ERR("no suitable firmware found!\n");
be663ab6
WYG		 4673 return -ENOENT;
4674 }
4675
46bc8d4b 4676 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
be663ab6 4677
e7392364 4678 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
be663ab6 4679
46bc8d4b
SG		 4680 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4681 &il->pci_dev->dev, GFP_KERNEL, il,
e2ebc833 4682 il4965_ucode_callback);
be663ab6
WYG		 4683}
4684
e2ebc833 4685struct il4965_firmware_pieces {
be663ab6
WYG		 4686 const void *inst, *data, *init, *init_data, *boot;
4687 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4688};
4689
e7392364
SG		 4690static int
4691il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4692 struct il4965_firmware_pieces *pieces)
be663ab6 4693{
e2ebc833 4694 struct il_ucode_header *ucode = (void *)ucode_raw->data;
be663ab6
WYG		 4695 u32 api_ver, hdr_size;
4696 const u8 *src;
4697
46bc8d4b
SG		 4698 il->ucode_ver = le32_to_cpu(ucode->ver);
4699 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4700
4701 switch (api_ver) {
4702 default:
4703 case 0:
4704 case 1:
4705 case 2:
4706 hdr_size = 24;
4707 if (ucode_raw->size < hdr_size) {
9406f797 4708 IL_ERR("File size too small!\n");
be663ab6
WYG		 4709 return -EINVAL;
4710 }
4711 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4712 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4713 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
e7392364 4714 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
be663ab6
WYG		 4715 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4716 src = ucode->v1.data;
4717 break;
4718 }
4719
4720 /* Verify size of file vs. image size info in file's header */
e7392364
SG		 4721 if (ucode_raw->size !=
4722 hdr_size + pieces->inst_size + pieces->data_size +
4723 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
be663ab6 4724
e7392364
SG		 4725 IL_ERR("uCode file size %d does not match expected size\n",
4726 (int)ucode_raw->size);
be663ab6
WYG		 4727 return -EINVAL;
4728 }
4729
4730 pieces->inst = src;
4731 src += pieces->inst_size;
4732 pieces->data = src;
4733 src += pieces->data_size;
4734 pieces->init = src;
4735 src += pieces->init_size;
4736 pieces->init_data = src;
4737 src += pieces->init_data_size;
4738 pieces->boot = src;
4739 src += pieces->boot_size;
4740
4741 return 0;
4742}
4743
4744/**
e2ebc833 4745 * il4965_ucode_callback - callback when firmware was loaded
be663ab6
WYG		 4746 *
4747 * If loaded successfully, copies the firmware into buffers
4748 * for the card to fetch (via DMA).
4749 */
4750static void
e2ebc833 4751il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
be663ab6 4752{
46bc8d4b 4753 struct il_priv *il = context;
e2ebc833 4754 struct il_ucode_header *ucode;
be663ab6 4755 int err;
e2ebc833 4756 struct il4965_firmware_pieces pieces;
46bc8d4b
SG		 4757 const unsigned int api_max = il->cfg->ucode_api_max;
4758 const unsigned int api_min = il->cfg->ucode_api_min;
be663ab6
WYG		 4759 u32 api_ver;
4760
4761 u32 max_probe_length = 200;
4762 u32 standard_phy_calibration_size =
e7392364 4763 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
be663ab6
WYG		 4764
4765 memset(&pieces, 0, sizeof(pieces));
4766
4767 if (!ucode_raw) {
0c2c8852 4768 if (il->fw_idx <= il->cfg->ucode_api_max)
e7392364
SG		 4769 IL_ERR("request for firmware file '%s' failed.\n",
4770 il->firmware_name);
be663ab6
WYG		 4771 goto try_again;
4772 }
4773
e7392364
SG		 4774 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4775 ucode_raw->size);
be663ab6
WYG		 4776
4777 /* Make sure that we got at least the API version number */
4778 if (ucode_raw->size < 4) {
9406f797 4779 IL_ERR("File size way too small!\n");
be663ab6
WYG		 4780 goto try_again;
4781 }
4782
4783 /* Data from ucode file: header followed by uCode images */
e2ebc833 4784 ucode = (struct il_ucode_header *)ucode_raw->data;
be663ab6 4785
46bc8d4b 4786 err = il4965_load_firmware(il, ucode_raw, &pieces);
be663ab6
WYG		 4787
4788 if (err)
4789 goto try_again;
4790
46bc8d4b 4791 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4792
4793 /*
4794 * api_ver should match the api version forming part of the
4795 * firmware filename ... but we don't check for that and only rely
4796 * on the API version read from firmware header from here on forward
4797 */
4798 if (api_ver < api_min || api_ver > api_max) {
e7392364
SG		 4799 IL_ERR("Driver unable to support your firmware API. "
4800 "Driver supports v%u, firmware is v%u.\n", api_max,
4801 api_ver);
be663ab6
WYG		 4802 goto try_again;
4803 }
4804
4805 if (api_ver != api_max)
e7392364
SG		 4806 IL_ERR("Firmware has old API version. Expected v%u, "
4807 "got v%u. New firmware can be obtained "
4808 "from http://www.intellinuxwireless.org.\n", api_max,
4809 api_ver);
be663ab6 4810
9406f797 4811 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG		 4812 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4813 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
be663ab6 4814
e7392364
SG		 4815 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4816 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4817 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
46bc8d4b 4818 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6
WYG		 4819
4820 /*
4821 * For any of the failures below (before allocating pci memory)
4822 * we will try to load a version with a smaller API -- maybe the
4823 * user just got a corrupted version of the latest API.
4824 */
4825
e7392364
SG		 4826 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4827 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4828 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4829 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4830 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4831 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
be663ab6
WYG		 4832
4833 /* Verify that uCode images will fit in card's SRAM */
46bc8d4b 4834 if (pieces.inst_size > il->hw_params.max_inst_size) {
9406f797 4835 IL_ERR("uCode instr len %Zd too large to fit in\n",
e7392364 4836 pieces.inst_size);
be663ab6
WYG		 4837 goto try_again;
4838 }
4839
46bc8d4b 4840 if (pieces.data_size > il->hw_params.max_data_size) {
9406f797 4841 IL_ERR("uCode data len %Zd too large to fit in\n",
e7392364 4842 pieces.data_size);
be663ab6
WYG		 4843 goto try_again;
4844 }
4845
46bc8d4b 4846 if (pieces.init_size > il->hw_params.max_inst_size) {
9406f797 4847 IL_ERR("uCode init instr len %Zd too large to fit in\n",
e7392364 4848 pieces.init_size);
be663ab6
WYG		 4849 goto try_again;
4850 }
4851
46bc8d4b 4852 if (pieces.init_data_size > il->hw_params.max_data_size) {
9406f797 4853 IL_ERR("uCode init data len %Zd too large to fit in\n",
e7392364 4854 pieces.init_data_size);
be663ab6
WYG		 4855 goto try_again;
4856 }
4857
46bc8d4b 4858 if (pieces.boot_size > il->hw_params.max_bsm_size) {
9406f797 4859 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
e7392364 4860 pieces.boot_size);
be663ab6
WYG		 4861 goto try_again;
4862 }
4863
4864 /* Allocate ucode buffers for card's bus-master loading ... */
4865
4866 /* Runtime instructions and 2 copies of data:
4867 * 1) unmodified from disk
4868 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG		 4869 il->ucode_code.len = pieces.inst_size;
4870 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
be663ab6 4871
46bc8d4b
SG		 4872 il->ucode_data.len = pieces.data_size;
4873 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
be663ab6 4874
46bc8d4b
SG		 4875 il->ucode_data_backup.len = pieces.data_size;
4876 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
be663ab6 4877
46bc8d4b
SG		 4878 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4879 !il->ucode_data_backup.v_addr)
be663ab6
WYG		 4880 goto err_pci_alloc;
4881
4882 /* Initialization instructions and data */
4883 if (pieces.init_size && pieces.init_data_size) {
46bc8d4b
SG		 4884 il->ucode_init.len = pieces.init_size;
4885 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
be663ab6 4886
46bc8d4b
SG		 4887 il->ucode_init_data.len = pieces.init_data_size;
4888 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
be663ab6 4889
46bc8d4b 4890 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
be663ab6
WYG		 4891 goto err_pci_alloc;
4892 }
4893
4894 /* Bootstrap (instructions only, no data) */
4895 if (pieces.boot_size) {
46bc8d4b
SG		 4896 il->ucode_boot.len = pieces.boot_size;
4897 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6 4898
46bc8d4b 4899 if (!il->ucode_boot.v_addr)
be663ab6
WYG		 4900 goto err_pci_alloc;
4901 }
4902
4903 /* Now that we can no longer fail, copy information */
4904
46bc8d4b 4905 il->sta_key_max_num = STA_KEY_MAX_NUM;
be663ab6
WYG		 4906
4907 /* Copy images into buffers for card's bus-master reads ... */
4908
4909 /* Runtime instructions (first block of data in file) */
58de00a4 4910 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
e7392364 4911 pieces.inst_size);
46bc8d4b 4912 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
be663ab6 4913
58de00a4 4914 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 4915 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
be663ab6
WYG		 4916
4917 /*
4918 * Runtime data
e2ebc833 4919 * NOTE: Copy into backup buffer will be done in il_up()
be663ab6 4920 */
58de00a4 4921 D_INFO("Copying (but not loading) uCode data len %Zd\n",
e7392364 4922 pieces.data_size);
46bc8d4b
SG		 4923 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4924 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
be663ab6
WYG		 4925
4926 /* Initialization instructions */
4927 if (pieces.init_size) {
e7392364
SG		 4928 D_INFO("Copying (but not loading) init instr len %Zd\n",
4929 pieces.init_size);
46bc8d4b 4930 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
be663ab6
WYG		 4931 }
4932
4933 /* Initialization data */
4934 if (pieces.init_data_size) {
e7392364
SG		 4935 D_INFO("Copying (but not loading) init data len %Zd\n",
4936 pieces.init_data_size);
46bc8d4b 4937 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
be663ab6
WYG		 4938 pieces.init_data_size);
4939 }
4940
4941 /* Bootstrap instructions */
58de00a4 4942 D_INFO("Copying (but not loading) boot instr len %Zd\n",
e7392364 4943 pieces.boot_size);
46bc8d4b 4944 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
be663ab6
WYG		 4945
4946 /*
4947 * figure out the offset of chain noise reset and gain commands
4948 * base on the size of standard phy calibration commands table size
4949 */
46bc8d4b 4950 il->_4965.phy_calib_chain_noise_reset_cmd =
e7392364 4951 standard_phy_calibration_size;
46bc8d4b 4952 il->_4965.phy_calib_chain_noise_gain_cmd =
e7392364 4953 standard_phy_calibration_size + 1;
be663ab6
WYG		 4954
4955 /**************************************************
4956 * This is still part of probe() in a sense...
4957 *
4958 * 9. Setup and register with mac80211 and debugfs
4959 **************************************************/
46bc8d4b 4960 err = il4965_mac_setup_register(il, max_probe_length);
be663ab6
WYG		 4961 if (err)
4962 goto out_unbind;
4963
46bc8d4b 4964 err = il_dbgfs_register(il, DRV_NAME);
be663ab6 4965 if (err)
e7392364
SG		 4966 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4967 err);
be663ab6 4968
e7392364 4969 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
be663ab6 4970 if (err) {
9406f797 4971 IL_ERR("failed to create sysfs device attributes\n");
be663ab6
WYG		 4972 goto out_unbind;
4973 }
4974
4975 /* We have our copies now, allow OS release its copies */
4976 release_firmware(ucode_raw);
46bc8d4b 4977 complete(&il->_4965.firmware_loading_complete);
be663ab6
WYG		 4978 return;
4979
e7392364 4980try_again:
be663ab6 4981 /* try next, if any */
46bc8d4b 4982 if (il4965_request_firmware(il, false))
be663ab6
WYG		 4983 goto out_unbind;
4984 release_firmware(ucode_raw);
4985 return;
4986
e7392364 4987err_pci_alloc:
9406f797 4988 IL_ERR("failed to allocate pci memory\n");
46bc8d4b 4989 il4965_dealloc_ucode_pci(il);
e7392364 4990out_unbind:
46bc8d4b
SG		 4991 complete(&il->_4965.firmware_loading_complete);
4992 device_release_driver(&il->pci_dev->dev);
be663ab6
WYG		 4993 release_firmware(ucode_raw);
4994}
4995
e7392364 4996static const char *const desc_lookup_text[] = {
be663ab6
WYG		 4997 "OK",
4998 "FAIL",
4999 "BAD_PARAM",
5000 "BAD_CHECKSUM",
5001 "NMI_INTERRUPT_WDG",
5002 "SYSASSERT",
5003 "FATAL_ERROR",
5004 "BAD_COMMAND",
5005 "HW_ERROR_TUNE_LOCK",
5006 "HW_ERROR_TEMPERATURE",
5007 "ILLEGAL_CHAN_FREQ",
3b98c7f4 5008 "VCC_NOT_STBL",
9a95b370 5009 "FH49_ERROR",
be663ab6
WYG		 5010 "NMI_INTERRUPT_HOST",
5011 "NMI_INTERRUPT_ACTION_PT",
5012 "NMI_INTERRUPT_UNKNOWN",
5013 "UCODE_VERSION_MISMATCH",
5014 "HW_ERROR_ABS_LOCK",
5015 "HW_ERROR_CAL_LOCK_FAIL",
5016 "NMI_INTERRUPT_INST_ACTION_PT",
5017 "NMI_INTERRUPT_DATA_ACTION_PT",
5018 "NMI_TRM_HW_ER",
5019 "NMI_INTERRUPT_TRM",
861d9c3f 5020 "NMI_INTERRUPT_BREAK_POINT",
be663ab6
WYG		 5021 "DEBUG_0",
5022 "DEBUG_1",
5023 "DEBUG_2",
5024 "DEBUG_3",
5025};
5026
e7392364
SG		 5027static struct {
5028 char *name;
5029 u8 num;
5030} advanced_lookup[] = {
5031 {
5032 "NMI_INTERRUPT_WDG", 0x34}, {
5033 "SYSASSERT", 0x35}, {
5034 "UCODE_VERSION_MISMATCH", 0x37}, {
5035 "BAD_COMMAND", 0x38}, {
5036 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5037 "FATAL_ERROR", 0x3D}, {
5038 "NMI_TRM_HW_ERR", 0x46}, {
5039 "NMI_INTERRUPT_TRM", 0x4C}, {
5040 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5041 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5042 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5043 "NMI_INTERRUPT_HOST", 0x66}, {
5044 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5045 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5046 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5047"ADVANCED_SYSASSERT", 0},};
5048
5049static const char *
5050il4965_desc_lookup(u32 num)
be663ab6
WYG		 5051{
5052 int i;
5053 int max = ARRAY_SIZE(desc_lookup_text);
5054
5055 if (num < max)
5056 return desc_lookup_text[num];
5057
5058 max = ARRAY_SIZE(advanced_lookup) - 1;
5059 for (i = 0; i < max; i++) {
5060 if (advanced_lookup[i].num == num)
5061 break;
5062 }
5063 return advanced_lookup[i].name;
5064}
5065
5066#define ERROR_START_OFFSET (1 * sizeof(u32))
5067#define ERROR_ELEM_SIZE (7 * sizeof(u32))
5068
e7392364
SG		 5069void
5070il4965_dump_nic_error_log(struct il_priv *il)
be663ab6
WYG		 5071{
5072 u32 data2, line;
5073 u32 desc, time, count, base, data1;
5074 u32 blink1, blink2, ilink1, ilink2;
5075 u32 pc, hcmd;
5076
1722f8e1 5077 if (il->ucode_type == UCODE_INIT)
46bc8d4b 5078 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
1722f8e1 5079 else
46bc8d4b 5080 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
be663ab6 5081
1600b875 5082 if (!il->ops->is_valid_rtc_data_addr(base)) {
e7392364
SG		 5083 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5084 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
be663ab6
WYG		 5085 return;
5086 }
5087
46bc8d4b 5088 count = il_read_targ_mem(il, base);
be663ab6
WYG		 5089
5090 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 5091 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 5092 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
46bc8d4b
SG		 5093 }
5094
5095 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5096 il->isr_stats.err_code = desc;
5097 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5098 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5099 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5100 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5101 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5102 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5103 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5104 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5105 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5106 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5107
9406f797 5108 IL_ERR("Desc Time "
e7392364 5109 "data1 data2 line\n");
9406f797 5110 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
e7392364 5111 il4965_desc_lookup(desc), desc, time, data1, data2, line);
9406f797 5112 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
e7392364
SG		 5113 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5114 blink2, ilink1, ilink2, hcmd);
be663ab6
WYG		 5115}
5116
e7392364
SG		 5117static void
5118il4965_rf_kill_ct_config(struct il_priv *il)
be663ab6 5119{
e2ebc833 5120 struct il_ct_kill_config cmd;
be663ab6
WYG		 5121 unsigned long flags;
5122 int ret = 0;
5123
46bc8d4b 5124 spin_lock_irqsave(&il->lock, flags);
841b2cca 5125 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 5126 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
46bc8d4b 5127 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5128
5129 cmd.critical_temperature_R =
e7392364 5130 cpu_to_le32(il->hw_params.ct_kill_threshold);
be663ab6 5131
e7392364 5132 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
be663ab6 5133 if (ret)
4d69c752 5134 IL_ERR("C_CT_KILL_CONFIG failed\n");
be663ab6 5135 else
e7392364
SG		 5136 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5137 "critical temperature is %d\n",
5138 il->hw_params.ct_kill_threshold);
be663ab6
WYG		 5139}
5140
5141static const s8 default_queue_to_tx_fifo[] = {
e2ebc833
SG		 5142 IL_TX_FIFO_VO,
5143 IL_TX_FIFO_VI,
5144 IL_TX_FIFO_BE,
5145 IL_TX_FIFO_BK,
d3175167 5146 IL49_CMD_FIFO_NUM,
e2ebc833
SG		 5147 IL_TX_FIFO_UNUSED,
5148 IL_TX_FIFO_UNUSED,
be663ab6
WYG		 5149};
5150
e53aac42
SG		 5151#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5152
e7392364
SG		 5153static int
5154il4965_alive_notify(struct il_priv *il)
be663ab6
WYG		 5155{
5156 u32 a;
5157 unsigned long flags;
5158 int i, chan;
5159 u32 reg_val;
5160
46bc8d4b 5161 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5162
5163 /* Clear 4965's internal Tx Scheduler data base */
e7392364 5164 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
d3175167
SG		 5165 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5166 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
46bc8d4b 5167 il_write_targ_mem(il, a, 0);
d3175167 5168 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
46bc8d4b 5169 il_write_targ_mem(il, a, 0);
e7392364
SG		 5170 for (;
5171 a <
5172 il->scd_base_addr +
5173 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5174 a += 4)
46bc8d4b 5175 il_write_targ_mem(il, a, 0);
be663ab6
WYG		 5176
5177 /* Tel 4965 where to find Tx byte count tables */
e7392364 5178 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
be663ab6
WYG		 5179
5180 /* Enable DMA channel */
e7392364
SG		 5181 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5182 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5183 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5184 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
be663ab6
WYG		 5185
5186 /* Update FH chicken bits */
9a95b370
SG		 5187 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5188 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
e7392364 5189 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
be663ab6
WYG		 5190
5191 /* Disable chain mode for all queues */
d3175167 5192 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
be663ab6
WYG		 5193
5194 /* Initialize each Tx queue (including the command queue) */
46bc8d4b 5195 for (i = 0; i < il->hw_params.max_txq_num; i++) {
be663ab6 5196
0c2c8852 5197 /* TFD circular buffer read/write idxes */
d3175167 5198 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
0c1a94e2 5199 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
be663ab6
WYG		 5200
5201 /* Max Tx Window size for Scheduler-ACK mode */
e7392364
SG		 5202 il_write_targ_mem(il,
5203 il->scd_base_addr +
5204 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5205 (SCD_WIN_SIZE <<
5206 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5207 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
be663ab6
WYG		 5208
5209 /* Frame limit */
e7392364
SG		 5210 il_write_targ_mem(il,
5211 il->scd_base_addr +
5212 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5213 sizeof(u32),
5214 (SCD_FRAME_LIMIT <<
5215 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5216 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
be663ab6
WYG		 5217
5218 }
d3175167 5219 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
e7392364 5220 (1 << il->hw_params.max_txq_num) - 1);
be663ab6
WYG		 5221
5222 /* Activate all Tx DMA/FIFO channels */
46bc8d4b 5223 il4965_txq_set_sched(il, IL_MASK(0, 6));
be663ab6 5224
46bc8d4b 5225 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
be663ab6
WYG		 5226
5227 /* make sure all queue are not stopped */
46bc8d4b 5228 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
be663ab6 5229 for (i = 0; i < 4; i++)
46bc8d4b 5230 atomic_set(&il->queue_stop_count[i], 0);
be663ab6
WYG		 5231
5232 /* reset to 0 to enable all the queue first */
46bc8d4b 5233 il->txq_ctx_active_msk = 0;
be663ab6
WYG		 5234 /* Map each Tx/cmd queue to its corresponding fifo */
5235 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5236
5237 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5238 int ac = default_queue_to_tx_fifo[i];
5239
46bc8d4b 5240 il_txq_ctx_activate(il, i);
be663ab6 5241
e2ebc833 5242 if (ac == IL_TX_FIFO_UNUSED)
be663ab6
WYG		 5243 continue;
5244
46bc8d4b 5245 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
be663ab6
WYG		 5246 }
5247
46bc8d4b 5248 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5249
5250 return 0;
5251}
5252
5253/**
4d69c752 5254 * il4965_alive_start - called after N_ALIVE notification received
be663ab6 5255 * from protocol/runtime uCode (initialization uCode's
e2ebc833 5256 * Alive gets handled by il_init_alive_start()).
be663ab6 5257 */
e7392364
SG		 5258static void
5259il4965_alive_start(struct il_priv *il)
be663ab6
WYG		 5260{
5261 int ret = 0;
be663ab6 5262
58de00a4 5263 D_INFO("Runtime Alive received.\n");
be663ab6 5264
46bc8d4b 5265 if (il->card_alive.is_valid != UCODE_VALID_OK) {
be663ab6
WYG		 5266 /* We had an error bringing up the hardware, so take it
5267 * all the way back down so we can try again */
58de00a4 5268 D_INFO("Alive failed.\n");
be663ab6
WYG		 5269 goto restart;
5270 }
5271
5272 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5273 * This is a paranoid check, because we would not have gotten the
5274 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 5275 if (il4965_verify_ucode(il)) {
be663ab6
WYG		 5276 /* Runtime instruction load was bad;
5277 * take it all the way back down so we can try again */
58de00a4 5278 D_INFO("Bad runtime uCode load.\n");
be663ab6
WYG		 5279 goto restart;
5280 }
5281
46bc8d4b 5282 ret = il4965_alive_notify(il);
be663ab6 5283 if (ret) {
e7392364 5284 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
be663ab6
WYG		 5285 goto restart;
5286 }
5287
be663ab6 5288 /* After the ALIVE response, we can send host commands to the uCode */
a6766ccd 5289 set_bit(S_ALIVE, &il->status);
be663ab6
WYG		 5290
5291 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 5292 il_setup_watchdog(il);
be663ab6 5293
46bc8d4b 5294 if (il_is_rfkill(il))
be663ab6
WYG		 5295 return;
5296
46bc8d4b 5297 ieee80211_wake_queues(il->hw);
be663ab6 5298
2eb05816 5299 il->active_rate = RATES_MASK;
be663ab6 5300
c8b03958 5301 if (il_is_associated(il)) {
e2ebc833 5302 struct il_rxon_cmd *active_rxon =
c8b03958 5303 (struct il_rxon_cmd *)&il->active;
be663ab6 5304 /* apply any changes in staging */
c8b03958 5305 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5306 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5307 } else {
be663ab6 5308 /* Initialize our rx_config data */
83007196 5309 il_connection_init_rx_config(il);
be663ab6 5310
c9363551
SG		 5311 if (il->ops->set_rxon_chain)
5312 il->ops->set_rxon_chain(il);
be663ab6
WYG		 5313 }
5314
5315 /* Configure bluetooth coexistence if enabled */
46bc8d4b 5316 il_send_bt_config(il);
be663ab6 5317
46bc8d4b 5318 il4965_reset_run_time_calib(il);
be663ab6 5319
a6766ccd 5320 set_bit(S_READY, &il->status);
be663ab6
WYG		 5321
5322 /* Configure the adapter for unassociated operation */
83007196 5323 il_commit_rxon(il);
be663ab6
WYG		 5324
5325 /* At this point, the NIC is initialized and operational */
46bc8d4b 5326 il4965_rf_kill_ct_config(il);
be663ab6 5327
58de00a4 5328 D_INFO("ALIVE processing complete.\n");
46bc8d4b 5329 wake_up(&il->wait_command_queue);
be663ab6 5330
46bc8d4b 5331 il_power_update_mode(il, true);
58de00a4 5332 D_INFO("Updated power mode\n");
be663ab6
WYG		 5333
5334 return;
5335
e7392364 5336restart:
46bc8d4b 5337 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 5338}
5339
46bc8d4b 5340static void il4965_cancel_deferred_work(struct il_priv *il);
be663ab6 5341
e7392364
SG		 5342static void
5343__il4965_down(struct il_priv *il)
be663ab6
WYG		 5344{
5345 unsigned long flags;
ab42b404 5346 int exit_pending;
be663ab6 5347
58de00a4 5348 D_INFO(DRV_NAME " is going down\n");
be663ab6 5349
46bc8d4b 5350 il_scan_cancel_timeout(il, 200);
be663ab6 5351
a6766ccd 5352 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
be663ab6 5353
a6766ccd 5354 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
be663ab6 5355 * to prevent rearm timer */
46bc8d4b 5356 del_timer_sync(&il->watchdog);
be663ab6 5357
83007196 5358 il_clear_ucode_stations(il);
d735f921
SG		 5359
5360 /* FIXME: race conditions ? */
5361 spin_lock_irq(&il->sta_lock);
5362 /*
5363 * Remove all key information that is not stored as part
5364 * of station information since mac80211 may not have had
5365 * a chance to remove all the keys. When device is
5366 * reconfigured by mac80211 after an error all keys will
5367 * be reconfigured.
5368 */
5369 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5370 il->_4965.key_mapping_keys = 0;
5371 spin_unlock_irq(&il->sta_lock);
5372
46bc8d4b
SG		 5373 il_dealloc_bcast_stations(il);
5374 il_clear_driver_stations(il);
be663ab6
WYG		 5375
5376 /* Unblock any waiting calls */
46bc8d4b 5377 wake_up_all(&il->wait_command_queue);
be663ab6
WYG		 5378
5379 /* Wipe out the EXIT_PENDING status bit if we are not actually
5380 * exiting the module */
5381 if (!exit_pending)
a6766ccd 5382 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5383
5384 /* stop and reset the on-board processor */
841b2cca 5385 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6
WYG		 5386
5387 /* tell the device to stop sending interrupts */
46bc8d4b
SG		 5388 spin_lock_irqsave(&il->lock, flags);
5389 il_disable_interrupts(il);
5390 spin_unlock_irqrestore(&il->lock, flags);
5391 il4965_synchronize_irq(il);
be663ab6 5392
46bc8d4b
SG		 5393 if (il->mac80211_registered)
5394 ieee80211_stop_queues(il->hw);
be663ab6 5395
e2ebc833 5396 /* If we have not previously called il_init() then
be663ab6 5397 * clear all bits but the RF Kill bit and return */
46bc8d4b 5398 if (!il_is_init(il)) {
e7392364 5399 il->status =
bc269a8e 5400 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0 5401 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
e7392364 5402 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6
WYG		 5403 goto exit;
5404 }
5405
5406 /* ...otherwise clear out all the status bits but the RF Kill
5407 * bit and continue taking the NIC down. */
e7392364 5408 il->status &=
bc269a8e 5409 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0
SG		 5410 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5411 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
e7392364 5412 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6 5413
775ed8ab
SG		 5414 /*
5415 * We disabled and synchronized interrupt, and priv->mutex is taken, so
5416 * here is the only thread which will program device registers, but
5417 * still have lockdep assertions, so we are taking reg_lock.
5418 */
5419 spin_lock_irq(&il->reg_lock);
5420 /* FIXME: il_grab_nic_access if rfkill is off ? */
5421
46bc8d4b
SG		 5422 il4965_txq_ctx_stop(il);
5423 il4965_rxq_stop(il);
be663ab6 5424 /* Power-down device's busmaster DMA clocks */
775ed8ab 5425 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6 5426 udelay(5);
be663ab6 5427 /* Make sure (redundant) we've released our request to stay awake */
775ed8ab 5428 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
be663ab6 5429 /* Stop the device, and put it in low power state */
775ed8ab
SG		 5430 _il_apm_stop(il);
5431
5432 spin_unlock_irq(&il->reg_lock);
be663ab6 5433
775ed8ab 5434 il4965_txq_ctx_unmap(il);
e7392364 5435exit:
46bc8d4b 5436 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
be663ab6 5437
46bc8d4b
SG		 5438 dev_kfree_skb(il->beacon_skb);
5439 il->beacon_skb = NULL;
be663ab6
WYG		 5440
5441 /* clear out any free frames */
46bc8d4b 5442 il4965_clear_free_frames(il);
be663ab6
WYG		 5443}
5444
e7392364
SG		 5445static void
5446il4965_down(struct il_priv *il)
be663ab6 5447{
46bc8d4b
SG		 5448 mutex_lock(&il->mutex);
5449 __il4965_down(il);
5450 mutex_unlock(&il->mutex);
be663ab6 5451
46bc8d4b 5452 il4965_cancel_deferred_work(il);
be663ab6
WYG		 5453}
5454
be663ab6 5455
71e0c6c2 5456static void
e7392364 5457il4965_set_hw_ready(struct il_priv *il)
be663ab6 5458{
71e0c6c2 5459 int ret;
be663ab6 5460
46bc8d4b 5461 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 5462 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
be663ab6
WYG		 5463
5464 /* See if we got it */
71e0c6c2
SG		 5465 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5466 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5467 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5468 100);
5469 if (ret >= 0)
46bc8d4b 5470 il->hw_ready = true;
be663ab6 5471
71e0c6c2 5472 D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not");
be663ab6
WYG		 5473}
5474
71e0c6c2 5475static void
e7392364 5476il4965_prepare_card_hw(struct il_priv *il)
be663ab6 5477{
71e0c6c2 5478 int ret;
be663ab6 5479
71e0c6c2 5480 il->hw_ready = false;
be663ab6 5481
71e0c6c2 5482 il4965_set_hw_ready(il);
46bc8d4b 5483 if (il->hw_ready)
71e0c6c2 5484 return;
be663ab6
WYG		 5485
5486 /* If HW is not ready, prepare the conditions to check again */
e7392364 5487 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
be663ab6 5488
e7392364
SG		 5489 ret =
5490 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5491 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5492 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
be663ab6
WYG		 5493
5494 /* HW should be ready by now, check again. */
5495 if (ret != -ETIMEDOUT)
46bc8d4b 5496 il4965_set_hw_ready(il);
be663ab6
WYG		 5497}
5498
5499#define MAX_HW_RESTARTS 5
5500
e7392364
SG		 5501static int
5502__il4965_up(struct il_priv *il)
be663ab6 5503{
be663ab6
WYG		 5504 int i;
5505 int ret;
5506
a6766ccd 5507 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 5508 IL_WARN("Exit pending; will not bring the NIC up\n");
be663ab6
WYG		 5509 return -EIO;
5510 }
5511
46bc8d4b 5512 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 5513 IL_ERR("ucode not available for device bringup\n");
be663ab6
WYG		 5514 return -EIO;
5515 }
5516
83007196 5517 ret = il4965_alloc_bcast_station(il);
17d6e557
SG		 5518 if (ret) {
5519 il_dealloc_bcast_stations(il);
5520 return ret;
be663ab6
WYG		 5521 }
5522
46bc8d4b 5523 il4965_prepare_card_hw(il);
46bc8d4b 5524 if (!il->hw_ready) {
71e0c6c2 5525 IL_ERR("HW not ready\n");
be663ab6
WYG		 5526 return -EIO;
5527 }
5528
5529 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 5530 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 5531 clear_bit(S_RFKILL, &il->status);
3976b451 5532 else {
bc269a8e 5533 set_bit(S_RFKILL, &il->status);
46bc8d4b 5534 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
be663ab6 5535
3976b451 5536 il_enable_rfkill_int(il);
9406f797 5537 IL_WARN("Radio disabled by HW RF Kill switch\n");
be663ab6
WYG		 5538 return 0;
5539 }
5540
841b2cca 5541 _il_wr(il, CSR_INT, 0xFFFFFFFF);
be663ab6 5542
e2ebc833 5543 /* must be initialised before il_hw_nic_init */
46bc8d4b 5544 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
be663ab6 5545
46bc8d4b 5546 ret = il4965_hw_nic_init(il);
be663ab6 5547 if (ret) {
9406f797 5548 IL_ERR("Unable to init nic\n");
be663ab6
WYG		 5549 return ret;
5550 }
5551
5552 /* make sure rfkill handshake bits are cleared */
841b2cca 5553 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 5554 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6
WYG		 5555
5556 /* clear (again), then enable host interrupts */
841b2cca 5557 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5558 il_enable_interrupts(il);
be663ab6
WYG		 5559
5560 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG		 5561 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5562 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
be663ab6
WYG		 5563
5564 /* Copy original ucode data image from disk into backup cache.
5565 * This will be used to initialize the on-board processor's
5566 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG		 5567 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5568 il->ucode_data.len);
be663ab6
WYG		 5569
5570 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5571
5572 /* load bootstrap state machine,
5573 * load bootstrap program into processor's memory,
5574 * prepare to load the "initialize" uCode */
1600b875 5575 ret = il->ops->load_ucode(il);
be663ab6
WYG		 5576
5577 if (ret) {
e7392364 5578 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
be663ab6
WYG		 5579 continue;
5580 }
5581
5582 /* start card; "initialize" will load runtime ucode */
46bc8d4b 5583 il4965_nic_start(il);
be663ab6 5584
58de00a4 5585 D_INFO(DRV_NAME " is coming up\n");
be663ab6
WYG		 5586
5587 return 0;
5588 }
5589
a6766ccd 5590 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 5591 __il4965_down(il);
a6766ccd 5592 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5593
5594 /* tried to restart and config the device for as long as our
5595 * patience could withstand */
9406f797 5596 IL_ERR("Unable to initialize device after %d attempts.\n", i);
be663ab6
WYG		 5597 return -EIO;
5598}
5599
be663ab6
WYG		 5600/*****************************************************************************
5601 *
5602 * Workqueue callbacks
5603 *
5604 *****************************************************************************/
5605
e7392364
SG		 5606static void
5607il4965_bg_init_alive_start(struct work_struct *data)
be663ab6 5608{
46bc8d4b 5609 struct il_priv *il =
e2ebc833 5610 container_of(data, struct il_priv, init_alive_start.work);
be663ab6 5611
46bc8d4b 5612 mutex_lock(&il->mutex);
a6766ccd 5613 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5614 goto out;
be663ab6 5615
1600b875 5616 il->ops->init_alive_start(il);
28a6e577 5617out:
46bc8d4b 5618 mutex_unlock(&il->mutex);
be663ab6
WYG		 5619}
5620
e7392364
SG		 5621static void
5622il4965_bg_alive_start(struct work_struct *data)
be663ab6 5623{
46bc8d4b 5624 struct il_priv *il =
e2ebc833 5625 container_of(data, struct il_priv, alive_start.work);
be663ab6 5626
46bc8d4b 5627 mutex_lock(&il->mutex);
a6766ccd 5628 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5629 goto out;
be663ab6 5630
46bc8d4b 5631 il4965_alive_start(il);
28a6e577 5632out:
46bc8d4b 5633 mutex_unlock(&il->mutex);
be663ab6
WYG		 5634}
5635
e7392364
SG		 5636static void
5637il4965_bg_run_time_calib_work(struct work_struct *work)
be663ab6 5638{
46bc8d4b 5639 struct il_priv *il = container_of(work, struct il_priv,
e7392364 5640 run_time_calib_work);
be663ab6 5641
46bc8d4b 5642 mutex_lock(&il->mutex);
be663ab6 5643
a6766ccd
SG		 5644 if (test_bit(S_EXIT_PENDING, &il->status) ||
5645 test_bit(S_SCANNING, &il->status)) {
46bc8d4b 5646 mutex_unlock(&il->mutex);
be663ab6
WYG		 5647 return;
5648 }
5649
46bc8d4b 5650 if (il->start_calib) {
e7392364
SG		 5651 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5652 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
be663ab6
WYG		 5653 }
5654
46bc8d4b 5655 mutex_unlock(&il->mutex);
be663ab6
WYG		 5656}
5657
e7392364
SG		 5658static void
5659il4965_bg_restart(struct work_struct *data)
be663ab6 5660{
46bc8d4b 5661 struct il_priv *il = container_of(data, struct il_priv, restart);
be663ab6 5662
a6766ccd 5663 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5664 return;
5665
a6766ccd 5666 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 5667 mutex_lock(&il->mutex);
46bc8d4b 5668 il->is_open = 0;
be663ab6 5669
46bc8d4b 5670 __il4965_down(il);
be663ab6 5671
46bc8d4b
SG		 5672 mutex_unlock(&il->mutex);
5673 il4965_cancel_deferred_work(il);
5674 ieee80211_restart_hw(il->hw);
be663ab6 5675 } else {
46bc8d4b 5676 il4965_down(il);
be663ab6 5677
46bc8d4b 5678 mutex_lock(&il->mutex);
a6766ccd 5679 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 5680 mutex_unlock(&il->mutex);
be663ab6 5681 return;
28a6e577 5682 }
be663ab6 5683
46bc8d4b
SG		 5684 __il4965_up(il);
5685 mutex_unlock(&il->mutex);
be663ab6
WYG		 5686 }
5687}
5688
e7392364
SG		 5689static void
5690il4965_bg_rx_replenish(struct work_struct *data)
be663ab6 5691{
e7392364 5692 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
be663ab6 5693
a6766ccd 5694 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5695 return;
5696
46bc8d4b
SG		 5697 mutex_lock(&il->mutex);
5698 il4965_rx_replenish(il);
5699 mutex_unlock(&il->mutex);
be663ab6
WYG		 5700}
5701
5702/*****************************************************************************
5703 *
5704 * mac80211 entry point functions
5705 *
5706 *****************************************************************************/
5707
5708#define UCODE_READY_TIMEOUT (4 * HZ)
5709
5710/*
5711 * Not a mac80211 entry point function, but it fits in with all the
5712 * other mac80211 functions grouped here.
5713 */
e7392364
SG		 5714static int
5715il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
be663ab6
WYG		 5716{
5717 int ret;
46bc8d4b 5718 struct ieee80211_hw *hw = il->hw;
be663ab6
WYG		 5719
5720 hw->rate_control_algorithm = "iwl-4965-rs";
5721
5722 /* Tell mac80211 our characteristics */
e7392364
SG		 5723 hw->flags =
5724 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
5725 IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT |
07db8f8f
SG		 5726 IEEE80211_HW_REPORTS_TX_ACK_STATUS | IEEE80211_HW_SUPPORTS_PS |
5727 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
46bc8d4b 5728 if (il->cfg->sku & IL_SKU_N)
e7392364
SG		 5729 hw->flags |=
5730 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5731 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
be663ab6 5732
e2ebc833
SG		 5733 hw->sta_data_size = sizeof(struct il_station_priv);
5734 hw->vif_data_size = sizeof(struct il_vif_priv);
be663ab6 5735
8c9c48d5
SG		 5736 hw->wiphy->interface_modes =
5737 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
be663ab6 5738
e7392364 5739 hw->wiphy->flags |=
d7fbcada
SG		 5740 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS |
5741 WIPHY_FLAG_IBSS_RSN;
be663ab6
WYG		 5742
5743 /*
5744 * For now, disable PS by default because it affects
5745 * RX performance significantly.
5746 */
5747 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5748
5749 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5750 /* we create the 802.11 header and a zero-length SSID element */
5751 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5752
5753 /* Default value; 4 EDCA QOS priorities */
5754 hw->queues = 4;
5755
e2ebc833 5756 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
be663ab6 5757
46bc8d4b
SG		 5758 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5759 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 5760 &il->bands[IEEE80211_BAND_2GHZ];
46bc8d4b
SG		 5761 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5762 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 5763 &il->bands[IEEE80211_BAND_5GHZ];
be663ab6 5764
46bc8d4b 5765 il_leds_init(il);
be663ab6 5766
46bc8d4b 5767 ret = ieee80211_register_hw(il->hw);
be663ab6 5768 if (ret) {
9406f797 5769 IL_ERR("Failed to register hw (error %d)\n", ret);
be663ab6
WYG		 5770 return ret;
5771 }
46bc8d4b 5772 il->mac80211_registered = 1;
be663ab6
WYG		 5773
5774 return 0;
5775}
5776
e7392364
SG		 5777int
5778il4965_mac_start(struct ieee80211_hw *hw)
be663ab6 5779{
46bc8d4b 5780 struct il_priv *il = hw->priv;
be663ab6
WYG		 5781 int ret;
5782
58de00a4 5783 D_MAC80211("enter\n");
be663ab6
WYG		 5784
5785 /* we should be verifying the device is ready to be opened */
46bc8d4b
SG		 5786 mutex_lock(&il->mutex);
5787 ret = __il4965_up(il);
5788 mutex_unlock(&il->mutex);
be663ab6
WYG		 5789
5790 if (ret)
5791 return ret;
5792
46bc8d4b 5793 if (il_is_rfkill(il))
be663ab6
WYG		 5794 goto out;
5795
58de00a4 5796 D_INFO("Start UP work done.\n");
be663ab6
WYG		 5797
5798 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5799 * mac80211 will not be run successfully. */
46bc8d4b 5800 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 5801 test_bit(S_READY, &il->status),
5802 UCODE_READY_TIMEOUT);
be663ab6 5803 if (!ret) {
a6766ccd 5804 if (!test_bit(S_READY, &il->status)) {
9406f797 5805 IL_ERR("START_ALIVE timeout after %dms.\n",
be663ab6
WYG		 5806 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5807 return -ETIMEDOUT;
5808 }
5809 }
5810
46bc8d4b 5811 il4965_led_enable(il);
be663ab6
WYG		 5812
5813out:
46bc8d4b 5814 il->is_open = 1;
58de00a4 5815 D_MAC80211("leave\n");
be663ab6
WYG		 5816 return 0;
5817}
5818
e7392364
SG		 5819void
5820il4965_mac_stop(struct ieee80211_hw *hw)
be663ab6 5821{
46bc8d4b 5822 struct il_priv *il = hw->priv;
be663ab6 5823
58de00a4 5824 D_MAC80211("enter\n");
be663ab6 5825
46bc8d4b 5826 if (!il->is_open)
be663ab6
WYG		 5827 return;
5828
46bc8d4b 5829 il->is_open = 0;
be663ab6 5830
46bc8d4b 5831 il4965_down(il);
be663ab6 5832
46bc8d4b 5833 flush_workqueue(il->workqueue);
be663ab6 5834
a078a1fd
SG		 5835 /* User space software may expect getting rfkill changes
5836 * even if interface is down */
841b2cca 5837 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5838 il_enable_rfkill_int(il);
be663ab6 5839
58de00a4 5840 D_MAC80211("leave\n");
be663ab6
WYG		 5841}
5842
e7392364 5843void
36323f81
TH		 5844il4965_mac_tx(struct ieee80211_hw *hw,
5845 struct ieee80211_tx_control *control,
5846 struct sk_buff *skb)
be663ab6 5847{
46bc8d4b 5848 struct il_priv *il = hw->priv;
be663ab6 5849
58de00a4 5850 D_MACDUMP("enter\n");
be663ab6 5851
58de00a4 5852 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 5853 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
be663ab6 5854
36323f81 5855 if (il4965_tx_skb(il, control->sta, skb))
be663ab6
WYG		 5856 dev_kfree_skb_any(skb);
5857
58de00a4 5858 D_MACDUMP("leave\n");
be663ab6
WYG		 5859}
5860
e7392364
SG		 5861void
5862il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5863 struct ieee80211_key_conf *keyconf,
5864 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
be663ab6 5865{
46bc8d4b 5866 struct il_priv *il = hw->priv;
be663ab6 5867
58de00a4 5868 D_MAC80211("enter\n");
be663ab6 5869
83007196 5870 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
be663ab6 5871
58de00a4 5872 D_MAC80211("leave\n");
be663ab6
WYG		 5873}
5874
e7392364
SG		 5875int
5876il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5877 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5878 struct ieee80211_key_conf *key)
be663ab6 5879{
46bc8d4b 5880 struct il_priv *il = hw->priv;
be663ab6
WYG		 5881 int ret;
5882 u8 sta_id;
5883 bool is_default_wep_key = false;
5884
58de00a4 5885 D_MAC80211("enter\n");
be663ab6 5886
46bc8d4b 5887 if (il->cfg->mod_params->sw_crypto) {
58de00a4 5888 D_MAC80211("leave - hwcrypto disabled\n");
be663ab6
WYG		 5889 return -EOPNOTSUPP;
5890 }
5891
d7fbcada
SG		 5892 /*
5893 * To support IBSS RSN, don't program group keys in IBSS, the
5894 * hardware will then not attempt to decrypt the frames.
5895 */
5896 if (vif->type == NL80211_IFTYPE_ADHOC &&
5897 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
5898 D_MAC80211("leave - ad-hoc group key\n");
5899 return -EOPNOTSUPP;
5900 }
5901
83007196 5902 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 5903 if (sta_id == IL_INVALID_STATION)
be663ab6
WYG		 5904 return -EINVAL;
5905
46bc8d4b
SG		 5906 mutex_lock(&il->mutex);
5907 il_scan_cancel_timeout(il, 100);
be663ab6
WYG		 5908
5909 /*
5910 * If we are getting WEP group key and we didn't receive any key mapping
5911 * so far, we are in legacy wep mode (group key only), otherwise we are
5912 * in 1X mode.
5913 * In legacy wep mode, we use another host command to the uCode.
5914 */
5915 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
e7392364 5916 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
be663ab6 5917 if (cmd == SET_KEY)
d735f921 5918 is_default_wep_key = !il->_4965.key_mapping_keys;
be663ab6
WYG		 5919 else
5920 is_default_wep_key =
e7392364 5921 (key->hw_key_idx == HW_KEY_DEFAULT);
be663ab6
WYG		 5922 }
5923
5924 switch (cmd) {
5925 case SET_KEY:
5926 if (is_default_wep_key)
83007196 5927 ret = il4965_set_default_wep_key(il, key);
be663ab6 5928 else
83007196 5929 ret = il4965_set_dynamic_key(il, key, sta_id);
be663ab6 5930
58de00a4 5931 D_MAC80211("enable hwcrypto key\n");
be663ab6
WYG		 5932 break;
5933 case DISABLE_KEY:
5934 if (is_default_wep_key)
83007196 5935 ret = il4965_remove_default_wep_key(il, key);
be663ab6 5936 else
83007196 5937 ret = il4965_remove_dynamic_key(il, key, sta_id);
be663ab6 5938
58de00a4 5939 D_MAC80211("disable hwcrypto key\n");
be663ab6
WYG		 5940 break;
5941 default:
5942 ret = -EINVAL;
5943 }
5944
46bc8d4b 5945 mutex_unlock(&il->mutex);
58de00a4 5946 D_MAC80211("leave\n");
be663ab6
WYG		 5947
5948 return ret;
5949}
5950
e7392364
SG		 5951int
5952il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5953 enum ieee80211_ampdu_mlme_action action,
5954 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5955 u8 buf_size)
be663ab6 5956{
46bc8d4b 5957 struct il_priv *il = hw->priv;
be663ab6
WYG		 5958 int ret = -EINVAL;
5959
e7392364 5960 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
be663ab6 5961
46bc8d4b 5962 if (!(il->cfg->sku & IL_SKU_N))
be663ab6
WYG		 5963 return -EACCES;
5964
46bc8d4b 5965 mutex_lock(&il->mutex);
be663ab6
WYG		 5966
5967 switch (action) {
5968 case IEEE80211_AMPDU_RX_START:
58de00a4 5969 D_HT("start Rx\n");
46bc8d4b 5970 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
be663ab6
WYG		 5971 break;
5972 case IEEE80211_AMPDU_RX_STOP:
58de00a4 5973 D_HT("stop Rx\n");
46bc8d4b 5974 ret = il4965_sta_rx_agg_stop(il, sta, tid);
a6766ccd 5975 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5976 ret = 0;
5977 break;
5978 case IEEE80211_AMPDU_TX_START:
58de00a4 5979 D_HT("start Tx\n");
46bc8d4b 5980 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
be663ab6 5981 break;
18b559d5
JB		 5982 case IEEE80211_AMPDU_TX_STOP_CONT:
5983 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5984 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
58de00a4 5985 D_HT("stop Tx\n");
46bc8d4b 5986 ret = il4965_tx_agg_stop(il, vif, sta, tid);
a6766ccd 5987 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5988 ret = 0;
5989 break;
5990 case IEEE80211_AMPDU_TX_OPERATIONAL:
5991 ret = 0;
5992 break;
5993 }
46bc8d4b 5994 mutex_unlock(&il->mutex);
be663ab6
WYG		 5995
5996 return ret;
5997}
5998
e7392364
SG		 5999int
6000il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6001 struct ieee80211_sta *sta)
be663ab6 6002{
46bc8d4b 6003 struct il_priv *il = hw->priv;
e2ebc833 6004 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
be663ab6
WYG		 6005 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
6006 int ret;
6007 u8 sta_id;
6008
e7392364 6009 D_INFO("received request to add station %pM\n", sta->addr);
46bc8d4b 6010 mutex_lock(&il->mutex);
e7392364 6011 D_INFO("proceeding to add station %pM\n", sta->addr);
e2ebc833 6012 sta_priv->common.sta_id = IL_INVALID_STATION;
be663ab6
WYG		 6013
6014 atomic_set(&sta_priv->pending_frames, 0);
6015
e7392364 6016 ret =
83007196 6017 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
be663ab6 6018 if (ret) {
e7392364 6019 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
be663ab6 6020 /* Should we return success if return code is EEXIST ? */
46bc8d4b 6021 mutex_unlock(&il->mutex);
be663ab6
WYG		 6022 return ret;
6023 }
6024
6025 sta_priv->common.sta_id = sta_id;
6026
6027 /* Initialize rate scaling */
e7392364 6028 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG		 6029 il4965_rs_rate_init(il, sta, sta_id);
6030 mutex_unlock(&il->mutex);
be663ab6
WYG		 6031
6032 return 0;
6033}
6034
e7392364
SG		 6035void
6036il4965_mac_channel_switch(struct ieee80211_hw *hw,
6037 struct ieee80211_channel_switch *ch_switch)
be663ab6 6038{
46bc8d4b 6039 struct il_priv *il = hw->priv;
e2ebc833 6040 const struct il_channel_info *ch_info;
be663ab6
WYG		 6041 struct ieee80211_conf *conf = &hw->conf;
6042 struct ieee80211_channel *channel = ch_switch->channel;
46bc8d4b 6043 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6 6044 u16 ch;
be663ab6 6045
58de00a4 6046 D_MAC80211("enter\n");
be663ab6 6047
46bc8d4b 6048 mutex_lock(&il->mutex);
28a6e577 6049
46bc8d4b 6050 if (il_is_rfkill(il))
28a6e577 6051 goto out;
be663ab6 6052
a6766ccd
SG		 6053 if (test_bit(S_EXIT_PENDING, &il->status) ||
6054 test_bit(S_SCANNING, &il->status) ||
6055 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
28a6e577 6056 goto out;
be663ab6 6057
c8b03958 6058 if (!il_is_associated(il))
28a6e577 6059 goto out;
be663ab6 6060
1600b875 6061 if (!il->ops->set_channel_switch)
7f1f9742 6062 goto out;
be663ab6 6063
7f1f9742 6064 ch = channel->hw_value;
c8b03958 6065 if (le16_to_cpu(il->active.channel) == ch)
7f1f9742
SG		 6066 goto out;
6067
46bc8d4b 6068 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 6069 if (!il_is_channel_valid(ch_info)) {
58de00a4 6070 D_MAC80211("invalid channel\n");
7f1f9742
SG		 6071 goto out;
6072 }
6073
46bc8d4b 6074 spin_lock_irq(&il->lock);
7f1f9742 6075
46bc8d4b 6076 il->current_ht_config.smps = conf->smps_mode;
7f1f9742
SG		 6077
6078 /* Configure HT40 channels */
1c03c462
SG		 6079 il->ht.enabled = conf_is_ht(conf);
6080 if (il->ht.enabled) {
7f1f9742 6081 if (conf_is_ht40_minus(conf)) {
1c03c462 6082 il->ht.extension_chan_offset =
e7392364 6083 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 6084 il->ht.is_40mhz = true;
7f1f9742 6085 } else if (conf_is_ht40_plus(conf)) {
1c03c462 6086 il->ht.extension_chan_offset =
e7392364 6087 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 6088 il->ht.is_40mhz = true;
7f1f9742 6089 } else {
1c03c462 6090 il->ht.extension_chan_offset =
e7392364 6091 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 6092 il->ht.is_40mhz = false;
be663ab6 6093 }
7f1f9742 6094 } else
1c03c462 6095 il->ht.is_40mhz = false;
7f1f9742 6096
c8b03958
SG		 6097 if ((le16_to_cpu(il->staging.channel) != ch))
6098 il->staging.flags = 0;
7f1f9742 6099
83007196 6100 il_set_rxon_channel(il, channel);
46bc8d4b 6101 il_set_rxon_ht(il, ht_conf);
83007196 6102 il_set_flags_for_band(il, channel->band, il->vif);
7f1f9742 6103
46bc8d4b 6104 spin_unlock_irq(&il->lock);
7f1f9742 6105
46bc8d4b 6106 il_set_rate(il);
7f1f9742
SG		 6107 /*
6108 * at this point, staging_rxon has the
6109 * configuration for channel switch
6110 */
a6766ccd 6111 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6112 il->switch_channel = cpu_to_le16(ch);
1600b875 6113 if (il->ops->set_channel_switch(il, ch_switch)) {
a6766ccd 6114 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6115 il->switch_channel = 0;
83007196 6116 ieee80211_chswitch_done(il->vif, false);
be663ab6 6117 }
7f1f9742 6118
be663ab6 6119out:
46bc8d4b 6120 mutex_unlock(&il->mutex);
58de00a4 6121 D_MAC80211("leave\n");
be663ab6
WYG		 6122}
6123
e7392364
SG		 6124void
6125il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6126 unsigned int *total_flags, u64 multicast)
be663ab6 6127{
46bc8d4b 6128 struct il_priv *il = hw->priv;
be663ab6 6129 __le32 filter_or = 0, filter_nand = 0;
be663ab6
WYG		 6130
6131#define CHK(test, flag) do { \
6132 if (*total_flags & (test)) \
6133 filter_or |= (flag); \
6134 else \
6135 filter_nand |= (flag); \
6136 } while (0)
6137
e7392364
SG		 6138 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6139 *total_flags);
be663ab6
WYG		 6140
6141 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
6142 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6143 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6144 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6145
6146#undef CHK
6147
46bc8d4b 6148 mutex_lock(&il->mutex);
be663ab6 6149
c8b03958
SG		 6150 il->staging.filter_flags &= ~filter_nand;
6151 il->staging.filter_flags |= filter_or;
be663ab6 6152
17d6e557
SG		 6153 /*
6154 * Not committing directly because hardware can perform a scan,
6155 * but we'll eventually commit the filter flags change anyway.
6156 */
be663ab6 6157
46bc8d4b 6158 mutex_unlock(&il->mutex);
be663ab6
WYG		 6159
6160 /*
6161 * Receiving all multicast frames is always enabled by the
e2ebc833 6162 * default flags setup in il_connection_init_rx_config()
be663ab6
WYG		 6163 * since we currently do not support programming multicast
6164 * filters into the device.
6165 */
e7392364
SG		 6166 *total_flags &=
6167 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
6168 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
be663ab6
WYG		 6169}
6170
6171/*****************************************************************************
6172 *
6173 * driver setup and teardown
6174 *
6175 *****************************************************************************/
6176
e7392364
SG		 6177static void
6178il4965_bg_txpower_work(struct work_struct *work)
be663ab6 6179{
46bc8d4b 6180 struct il_priv *il = container_of(work, struct il_priv,
e7392364 6181 txpower_work);
be663ab6 6182
46bc8d4b 6183 mutex_lock(&il->mutex);
f325757a 6184
be663ab6 6185 /* If a scan happened to start before we got here
ebf0d90d 6186 * then just return; the stats notification will
be663ab6
WYG		 6187 * kick off another scheduled work to compensate for
6188 * any temperature delta we missed here. */
a6766ccd
SG		 6189 if (test_bit(S_EXIT_PENDING, &il->status) ||
6190 test_bit(S_SCANNING, &il->status))
f325757a 6191 goto out;
be663ab6
WYG		 6192
6193 /* Regardless of if we are associated, we must reconfigure the
6194 * TX power since frames can be sent on non-radar channels while
6195 * not associated */
1600b875 6196 il->ops->send_tx_power(il);
be663ab6
WYG		 6197
6198 /* Update last_temperature to keep is_calib_needed from running
6199 * when it isn't needed... */
46bc8d4b 6200 il->last_temperature = il->temperature;
f325757a 6201out:
46bc8d4b 6202 mutex_unlock(&il->mutex);
be663ab6
WYG		 6203}
6204
e7392364
SG		 6205static void
6206il4965_setup_deferred_work(struct il_priv *il)
be663ab6 6207{
46bc8d4b 6208 il->workqueue = create_singlethread_workqueue(DRV_NAME);
be663ab6 6209
46bc8d4b 6210 init_waitqueue_head(&il->wait_command_queue);
be663ab6 6211
46bc8d4b
SG		 6212 INIT_WORK(&il->restart, il4965_bg_restart);
6213 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6214 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6215 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6216 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
be663ab6 6217
46bc8d4b 6218 il_setup_scan_deferred_work(il);
be663ab6 6219
46bc8d4b 6220 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
be663ab6 6221
ebf0d90d
SG		 6222 init_timer(&il->stats_periodic);
6223 il->stats_periodic.data = (unsigned long)il;
6224 il->stats_periodic.function = il4965_bg_stats_periodic;
be663ab6 6225
46bc8d4b
SG		 6226 init_timer(&il->watchdog);
6227 il->watchdog.data = (unsigned long)il;
6228 il->watchdog.function = il_bg_watchdog;
be663ab6 6229
e7392364
SG		 6230 tasklet_init(&il->irq_tasklet,
6231 (void (*)(unsigned long))il4965_irq_tasklet,
6232 (unsigned long)il);
be663ab6
WYG		 6233}
6234
e7392364
SG		 6235static void
6236il4965_cancel_deferred_work(struct il_priv *il)
be663ab6 6237{
46bc8d4b
SG		 6238 cancel_work_sync(&il->txpower_work);
6239 cancel_delayed_work_sync(&il->init_alive_start);
6240 cancel_delayed_work(&il->alive_start);
6241 cancel_work_sync(&il->run_time_calib_work);
be663ab6 6242
46bc8d4b 6243 il_cancel_scan_deferred_work(il);
be663ab6 6244
ebf0d90d 6245 del_timer_sync(&il->stats_periodic);
be663ab6
WYG		 6246}
6247
e7392364
SG		 6248static void
6249il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
be663ab6
WYG		 6250{
6251 int i;
6252
2eb05816 6253 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
d2ddf621 6254 rates[i].bitrate = il_rates[i].ieee * 5;
e7392364 6255 rates[i].hw_value = i; /* Rate scaling will work on idxes */
be663ab6
WYG		 6256 rates[i].hw_value_short = i;
6257 rates[i].flags = 0;
e2ebc833 6258 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
be663ab6
WYG		 6259 /*
6260 * If CCK != 1M then set short preamble rate flag.
6261 */
6262 rates[i].flags |=
e7392364
SG		 6263 (il_rates[i].plcp ==
6264 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
be663ab6
WYG		 6265 }
6266 }
6267}
e7392364 6268
be663ab6 6269/*
46bc8d4b 6270 * Acquire il->lock before calling this function !
be663ab6 6271 */
e7392364
SG		 6272void
6273il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
be663ab6 6274{
e7392364 6275 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
0c2c8852 6276 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
be663ab6
WYG		 6277}
6278
e7392364
SG		 6279void
6280il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6281 int tx_fifo_id, int scd_retry)
be663ab6
WYG		 6282{
6283 int txq_id = txq->q.id;
6284
6285 /* Find out whether to activate Tx queue */
46bc8d4b 6286 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
be663ab6
WYG		 6287
6288 /* Set up and activate */
d3175167 6289 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 6290 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6291 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6292 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6293 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6294 IL49_SCD_QUEUE_STTS_REG_MSK);
be663ab6
WYG		 6295
6296 txq->sched_retry = scd_retry;
6297
e7392364
SG		 6298 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6299 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
be663ab6
WYG		 6300}
6301
c39ae9fd
SG		 6302const struct ieee80211_ops il4965_mac_ops = {
6303 .tx = il4965_mac_tx,
6304 .start = il4965_mac_start,
6305 .stop = il4965_mac_stop,
6306 .add_interface = il_mac_add_interface,
6307 .remove_interface = il_mac_remove_interface,
6308 .change_interface = il_mac_change_interface,
6309 .config = il_mac_config,
6310 .configure_filter = il4965_configure_filter,
6311 .set_key = il4965_mac_set_key,
6312 .update_tkip_key = il4965_mac_update_tkip_key,
6313 .conf_tx = il_mac_conf_tx,
6314 .reset_tsf = il_mac_reset_tsf,
6315 .bss_info_changed = il_mac_bss_info_changed,
6316 .ampdu_action = il4965_mac_ampdu_action,
6317 .hw_scan = il_mac_hw_scan,
6318 .sta_add = il4965_mac_sta_add,
6319 .sta_remove = il_mac_sta_remove,
6320 .channel_switch = il4965_mac_channel_switch,
6321 .tx_last_beacon = il_mac_tx_last_beacon,
70277f47 6322 .flush = il_mac_flush,
c39ae9fd
SG		 6323};
6324
e7392364
SG		 6325static int
6326il4965_init_drv(struct il_priv *il)
be663ab6
WYG		 6327{
6328 int ret;
6329
46bc8d4b
SG		 6330 spin_lock_init(&il->sta_lock);
6331 spin_lock_init(&il->hcmd_lock);
be663ab6 6332
46bc8d4b 6333 INIT_LIST_HEAD(&il->free_frames);
be663ab6 6334
46bc8d4b 6335 mutex_init(&il->mutex);
be663ab6 6336
46bc8d4b
SG		 6337 il->ieee_channels = NULL;
6338 il->ieee_rates = NULL;
6339 il->band = IEEE80211_BAND_2GHZ;
be663ab6 6340
46bc8d4b
SG		 6341 il->iw_mode = NL80211_IFTYPE_STATION;
6342 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6343 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
be663ab6
WYG		 6344
6345 /* initialize force reset */
46bc8d4b 6346 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
be663ab6
WYG		 6347
6348 /* Choose which receivers/antennas to use */
c9363551
SG		 6349 if (il->ops->set_rxon_chain)
6350 il->ops->set_rxon_chain(il);
be663ab6 6351
46bc8d4b 6352 il_init_scan_params(il);
be663ab6 6353
46bc8d4b 6354 ret = il_init_channel_map(il);
be663ab6 6355 if (ret) {
9406f797 6356 IL_ERR("initializing regulatory failed: %d\n", ret);
be663ab6
WYG		 6357 goto err;
6358 }
6359
46bc8d4b 6360 ret = il_init_geos(il);
be663ab6 6361 if (ret) {
9406f797 6362 IL_ERR("initializing geos failed: %d\n", ret);
be663ab6
WYG		 6363 goto err_free_channel_map;
6364 }
46bc8d4b 6365 il4965_init_hw_rates(il, il->ieee_rates);
be663ab6
WYG		 6366
6367 return 0;
6368
6369err_free_channel_map:
46bc8d4b 6370 il_free_channel_map(il);
be663ab6
WYG		 6371err:
6372 return ret;
6373}
6374
e7392364
SG		 6375static void
6376il4965_uninit_drv(struct il_priv *il)
be663ab6 6377{
46bc8d4b
SG		 6378 il_free_geos(il);
6379 il_free_channel_map(il);
6380 kfree(il->scan_cmd);
be663ab6
WYG		 6381}
6382
e7392364
SG		 6383static void
6384il4965_hw_detect(struct il_priv *il)
be663ab6 6385{
841b2cca
SG		 6386 il->hw_rev = _il_rd(il, CSR_HW_REV);
6387 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
46bc8d4b 6388 il->rev_id = il->pci_dev->revision;
58de00a4 6389 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
be663ab6
WYG		 6390}
6391
1023f3bc
SG		 6392static struct il_sensitivity_ranges il4965_sensitivity = {
6393 .min_nrg_cck = 97,
6394 .max_nrg_cck = 0, /* not used, set to 0 */
6395
6396 .auto_corr_min_ofdm = 85,
6397 .auto_corr_min_ofdm_mrc = 170,
6398 .auto_corr_min_ofdm_x1 = 105,
6399 .auto_corr_min_ofdm_mrc_x1 = 220,
6400
6401 .auto_corr_max_ofdm = 120,
6402 .auto_corr_max_ofdm_mrc = 210,
6403 .auto_corr_max_ofdm_x1 = 140,
6404 .auto_corr_max_ofdm_mrc_x1 = 270,
6405
6406 .auto_corr_min_cck = 125,
6407 .auto_corr_max_cck = 200,
6408 .auto_corr_min_cck_mrc = 200,
6409 .auto_corr_max_cck_mrc = 400,
6410
6411 .nrg_th_cck = 100,
6412 .nrg_th_ofdm = 100,
6413
6414 .barker_corr_th_min = 190,
6415 .barker_corr_th_min_mrc = 390,
6416 .nrg_th_cca = 62,
6417};
6418
6419static void
e7392364 6420il4965_set_hw_params(struct il_priv *il)
be663ab6 6421{
b16db50a 6422 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
46bc8d4b
SG		 6423 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6424 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6425 if (il->cfg->mod_params->amsdu_size_8K)
6426 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
be663ab6 6427 else
46bc8d4b 6428 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
be663ab6 6429
46bc8d4b 6430 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
be663ab6 6431
46bc8d4b
SG		 6432 if (il->cfg->mod_params->disable_11n)
6433 il->cfg->sku &= ~IL_SKU_N;
be663ab6 6434
1023f3bc
SG		 6435 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6436 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6437 il->cfg->num_of_queues =
6438 il->cfg->mod_params->num_of_queues;
6439
6440 il->hw_params.max_txq_num = il->cfg->num_of_queues;
6441 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6442 il->hw_params.scd_bc_tbls_size =
6443 il->cfg->num_of_queues *
6444 sizeof(struct il4965_scd_bc_tbl);
6445
6446 il->hw_params.tfd_size = sizeof(struct il_tfd);
6447 il->hw_params.max_stations = IL4965_STATION_COUNT;
6448 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6449 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6450 il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6451 il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
6452
6453 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6454
6455 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6456 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6457 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6458 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6459
6460 il->hw_params.ct_kill_threshold =
6461 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6462
6463 il->hw_params.sens = &il4965_sensitivity;
6464 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
be663ab6
WYG		 6465}
6466
be663ab6 6467static int
e2ebc833 6468il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
be663ab6 6469{
7c2cde2e 6470 int err = 0;
46bc8d4b 6471 struct il_priv *il;
be663ab6 6472 struct ieee80211_hw *hw;
e2ebc833 6473 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
be663ab6
WYG		 6474 unsigned long flags;
6475 u16 pci_cmd;
6476
6477 /************************
6478 * 1. Allocating HW data
6479 ************************/
6480
c39ae9fd 6481 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
be663ab6
WYG		 6482 if (!hw) {
6483 err = -ENOMEM;
6484 goto out;
6485 }
46bc8d4b 6486 il = hw->priv;
c39ae9fd 6487 il->hw = hw;
be663ab6
WYG		 6488 SET_IEEE80211_DEV(hw, &pdev->dev);
6489
58de00a4 6490 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 6491 il->cfg = cfg;
c39ae9fd 6492 il->ops = &il4965_ops;
93b7654e
SG		 6493#ifdef CONFIG_IWLEGACY_DEBUGFS
6494 il->debugfs_ops = &il4965_debugfs_ops;
6495#endif
46bc8d4b
SG		 6496 il->pci_dev = pdev;
6497 il->inta_mask = CSR_INI_SET_MASK;
be663ab6 6498
be663ab6
WYG		 6499 /**************************
6500 * 2. Initializing PCI bus
6501 **************************/
e7392364
SG		 6502 pci_disable_link_state(pdev,
6503 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6504 PCIE_LINK_STATE_CLKPM);
be663ab6
WYG		 6505
6506 if (pci_enable_device(pdev)) {
6507 err = -ENODEV;
6508 goto out_ieee80211_free_hw;
6509 }
6510
6511 pci_set_master(pdev);
6512
6513 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6514 if (!err)
6515 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6516 if (err) {
6517 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6518 if (!err)
e7392364
SG		 6519 err =
6520 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
be663ab6
WYG		 6521 /* both attempts failed: */
6522 if (err) {
9406f797 6523 IL_WARN("No suitable DMA available.\n");
be663ab6
WYG		 6524 goto out_pci_disable_device;
6525 }
6526 }
6527
6528 err = pci_request_regions(pdev, DRV_NAME);
6529 if (err)
6530 goto out_pci_disable_device;
6531
46bc8d4b 6532 pci_set_drvdata(pdev, il);
be663ab6 6533
be663ab6
WYG		 6534 /***********************
6535 * 3. Read REV register
6536 ***********************/
a5f16137 6537 il->hw_base = pci_ioremap_bar(pdev, 0);
46bc8d4b 6538 if (!il->hw_base) {
be663ab6
WYG		 6539 err = -ENODEV;
6540 goto out_pci_release_regions;
6541 }
6542
58de00a4 6543 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 6544 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 6545 D_INFO("pci_resource_base = %p\n", il->hw_base);
be663ab6
WYG		 6546
6547 /* these spin locks will be used in apm_ops.init and EEPROM access
6548 * we should init now
6549 */
46bc8d4b
SG		 6550 spin_lock_init(&il->reg_lock);
6551 spin_lock_init(&il->lock);
be663ab6
WYG		 6552
6553 /*
6554 * stop and reset the on-board processor just in case it is in a
6555 * strange state ... like being left stranded by a primary kernel
6556 * and this is now the kdump kernel trying to start up
6557 */
841b2cca 6558 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6 6559
46bc8d4b 6560 il4965_hw_detect(il);
e7392364 6561 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
be663ab6
WYG		 6562
6563 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6564 * PCI Tx retries from interfering with C3 CPU state */
6565 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6566
46bc8d4b
SG		 6567 il4965_prepare_card_hw(il);
6568 if (!il->hw_ready) {
9406f797 6569 IL_WARN("Failed, HW not ready\n");
66284505 6570 err = -EIO;
be663ab6
WYG		 6571 goto out_iounmap;
6572 }
6573
6574 /*****************
6575 * 4. Read EEPROM
6576 *****************/
6577 /* Read the EEPROM */
46bc8d4b 6578 err = il_eeprom_init(il);
be663ab6 6579 if (err) {
9406f797 6580 IL_ERR("Unable to init EEPROM\n");
be663ab6
WYG		 6581 goto out_iounmap;
6582 }
46bc8d4b 6583 err = il4965_eeprom_check_version(il);
be663ab6
WYG		 6584 if (err)
6585 goto out_free_eeprom;
6586
be663ab6 6587 /* extract MAC Address */
46bc8d4b 6588 il4965_eeprom_get_mac(il, il->addresses[0].addr);
58de00a4 6589 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
46bc8d4b
SG		 6590 il->hw->wiphy->addresses = il->addresses;
6591 il->hw->wiphy->n_addresses = 1;
be663ab6
WYG		 6592
6593 /************************
6594 * 5. Setup HW constants
6595 ************************/
1023f3bc 6596 il4965_set_hw_params(il);
be663ab6
WYG		 6597
6598 /*******************
46bc8d4b 6599 * 6. Setup il
be663ab6
WYG		 6600 *******************/
6601
46bc8d4b 6602 err = il4965_init_drv(il);
be663ab6
WYG		 6603 if (err)
6604 goto out_free_eeprom;
46bc8d4b 6605 /* At this point both hw and il are initialized. */
be663ab6
WYG		 6606
6607 /********************
6608 * 7. Setup services
6609 ********************/
46bc8d4b
SG		 6610 spin_lock_irqsave(&il->lock, flags);
6611 il_disable_interrupts(il);
6612 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6613
46bc8d4b 6614 pci_enable_msi(il->pci_dev);
be663ab6 6615
e7392364 6616 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
be663ab6 6617 if (err) {
9406f797 6618 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
be663ab6
WYG		 6619 goto out_disable_msi;
6620 }
6621
46bc8d4b 6622 il4965_setup_deferred_work(il);
d0c72347 6623 il4965_setup_handlers(il);
be663ab6
WYG		 6624
6625 /*********************************************
6626 * 8. Enable interrupts and read RFKILL state
6627 *********************************************/
6628
a078a1fd 6629 /* enable rfkill interrupt: hw bug w/a */
46bc8d4b 6630 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
be663ab6
WYG		 6631 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6632 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
46bc8d4b 6633 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
be663ab6
WYG		 6634 }
6635
46bc8d4b 6636 il_enable_rfkill_int(il);
be663ab6
WYG		 6637
6638 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 6639 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 6640 clear_bit(S_RFKILL, &il->status);
be663ab6 6641 else
bc269a8e 6642 set_bit(S_RFKILL, &il->status);
be663ab6 6643
46bc8d4b 6644 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 6645 test_bit(S_RFKILL, &il->status));
be663ab6 6646
46bc8d4b 6647 il_power_initialize(il);
be663ab6 6648
46bc8d4b 6649 init_completion(&il->_4965.firmware_loading_complete);
be663ab6 6650
46bc8d4b 6651 err = il4965_request_firmware(il, true);
be663ab6
WYG		 6652 if (err)
6653 goto out_destroy_workqueue;
6654
6655 return 0;
6656
e7392364 6657out_destroy_workqueue:
46bc8d4b
SG		 6658 destroy_workqueue(il->workqueue);
6659 il->workqueue = NULL;
6660 free_irq(il->pci_dev->irq, il);
e7392364 6661out_disable_msi:
46bc8d4b
SG		 6662 pci_disable_msi(il->pci_dev);
6663 il4965_uninit_drv(il);
e7392364 6664out_free_eeprom:
46bc8d4b 6665 il_eeprom_free(il);
e7392364 6666out_iounmap:
a5f16137 6667 iounmap(il->hw_base);
e7392364 6668out_pci_release_regions:
be663ab6
WYG		 6669 pci_set_drvdata(pdev, NULL);
6670 pci_release_regions(pdev);
e7392364 6671out_pci_disable_device:
be663ab6 6672 pci_disable_device(pdev);
e7392364 6673out_ieee80211_free_hw:
46bc8d4b 6674 ieee80211_free_hw(il->hw);
e7392364 6675out:
be663ab6
WYG		 6676 return err;
6677}
6678
a027cb88 6679static void
e7392364 6680il4965_pci_remove(struct pci_dev *pdev)
be663ab6 6681{
46bc8d4b 6682 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 6683 unsigned long flags;
6684
46bc8d4b 6685 if (!il)
be663ab6
WYG		 6686 return;
6687
46bc8d4b 6688 wait_for_completion(&il->_4965.firmware_loading_complete);
be663ab6 6689
58de00a4 6690 D_INFO("*** UNLOAD DRIVER ***\n");
be663ab6 6691
46bc8d4b 6692 il_dbgfs_unregister(il);
e2ebc833 6693 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
be663ab6 6694
e2ebc833
SG		 6695 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6696 * to be called and il4965_down since we are removing the device
a6766ccd 6697 * we need to set S_EXIT_PENDING bit.
be663ab6 6698 */
a6766ccd 6699 set_bit(S_EXIT_PENDING, &il->status);
be663ab6 6700
46bc8d4b 6701 il_leds_exit(il);
be663ab6 6702
46bc8d4b
SG		 6703 if (il->mac80211_registered) {
6704 ieee80211_unregister_hw(il->hw);
6705 il->mac80211_registered = 0;
be663ab6 6706 } else {
46bc8d4b 6707 il4965_down(il);
be663ab6
WYG		 6708 }
6709
6710 /*
6711 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG		 6712 * This may be redundant with il4965_down(), but there are paths to
6713 * run il4965_down() without calling apm_ops.stop(), and there are
6714 * paths to avoid running il4965_down() at all before leaving driver.
be663ab6
WYG		 6715 * This (inexpensive) call *makes sure* device is reset.
6716 */
46bc8d4b 6717 il_apm_stop(il);
be663ab6
WYG		 6718
6719 /* make sure we flush any pending irq or
6720 * tasklet for the driver
6721 */
46bc8d4b
SG		 6722 spin_lock_irqsave(&il->lock, flags);
6723 il_disable_interrupts(il);
6724 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6725
46bc8d4b 6726 il4965_synchronize_irq(il);
be663ab6 6727
46bc8d4b 6728 il4965_dealloc_ucode_pci(il);
be663ab6 6729
46bc8d4b
SG		 6730 if (il->rxq.bd)
6731 il4965_rx_queue_free(il, &il->rxq);
6732 il4965_hw_txq_ctx_free(il);
be663ab6 6733
46bc8d4b 6734 il_eeprom_free(il);
be663ab6 6735
be663ab6 6736 /*netif_stop_queue(dev); */
46bc8d4b 6737 flush_workqueue(il->workqueue);
be663ab6 6738
e2ebc833 6739 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
46bc8d4b 6740 * il->workqueue... so we can't take down the workqueue
be663ab6 6741 * until now... */
46bc8d4b
SG		 6742 destroy_workqueue(il->workqueue);
6743 il->workqueue = NULL;
be663ab6 6744
46bc8d4b
SG		 6745 free_irq(il->pci_dev->irq, il);
6746 pci_disable_msi(il->pci_dev);
a5f16137 6747 iounmap(il->hw_base);
be663ab6
WYG		 6748 pci_release_regions(pdev);
6749 pci_disable_device(pdev);
6750 pci_set_drvdata(pdev, NULL);
6751
46bc8d4b 6752 il4965_uninit_drv(il);
be663ab6 6753
46bc8d4b 6754 dev_kfree_skb(il->beacon_skb);
be663ab6 6755
46bc8d4b 6756 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6757}
6758
6759/*
6760 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
46bc8d4b 6761 * must be called under il->lock and mac access
be663ab6 6762 */
e7392364
SG		 6763void
6764il4965_txq_set_sched(struct il_priv *il, u32 mask)
be663ab6 6765{
d3175167 6766 il_wr_prph(il, IL49_SCD_TXFACT, mask);
be663ab6
WYG		 6767}
6768
6769/*****************************************************************************
6770 *
6771 * driver and module entry point
6772 *
6773 *****************************************************************************/
6774
6775/* Hardware specific file defines the PCI IDs table for that hardware module */
e2ebc833 6776static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
e2ebc833
SG		 6777 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6778 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
be663ab6
WYG		 6779 {0}
6780};
e2ebc833 6781MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
be663ab6 6782
e2ebc833 6783static struct pci_driver il4965_driver = {
be663ab6 6784 .name = DRV_NAME,
e2ebc833
SG		 6785 .id_table = il4965_hw_card_ids,
6786 .probe = il4965_pci_probe,
a027cb88 6787 .remove = il4965_pci_remove,
e2ebc833 6788 .driver.pm = IL_LEGACY_PM_OPS,
be663ab6
WYG		 6789};
6790
e7392364
SG		 6791static int __init
6792il4965_init(void)
be663ab6
WYG		 6793{
6794
6795 int ret;
6796 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6797 pr_info(DRV_COPYRIGHT "\n");
6798
e2ebc833 6799 ret = il4965_rate_control_register();
be663ab6
WYG		 6800 if (ret) {
6801 pr_err("Unable to register rate control algorithm: %d\n", ret);
6802 return ret;
6803 }
6804
e2ebc833 6805 ret = pci_register_driver(&il4965_driver);
be663ab6
WYG		 6806 if (ret) {
6807 pr_err("Unable to initialize PCI module\n");
6808 goto error_register;
6809 }
6810
6811 return ret;
6812
6813error_register:
e2ebc833 6814 il4965_rate_control_unregister();
be663ab6
WYG		 6815 return ret;
6816}
6817
e7392364
SG		 6818static void __exit
6819il4965_exit(void)
be663ab6 6820{
e2ebc833
SG		 6821 pci_unregister_driver(&il4965_driver);
6822 il4965_rate_control_unregister();
be663ab6
WYG		 6823}
6824
e2ebc833
SG		 6825module_exit(il4965_exit);
6826module_init(il4965_init);
be663ab6 6827
d3175167 6828#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 6829module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
be663ab6
WYG		 6830MODULE_PARM_DESC(debug, "debug output mask");
6831#endif
6832
e2ebc833 6833module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
be663ab6 6834MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
e2ebc833 6835module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
be663ab6 6836MODULE_PARM_DESC(queues_num, "number of hw queues.");
e2ebc833 6837module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
be663ab6 6838MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
e7392364
SG		 6839module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6840 S_IRUGO);
be663ab6 6841MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
e2ebc833 6842module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
be663ab6 6843MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
Linux kernel - Deliverables
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