projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlegacy: merge il_base_params into il_cfg
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
be663ab6
WYG		 43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
98613be0 53#include "common.h"
af038f40 54#include "4965.h"
be663ab6 55
be663ab6
WYG		 56/******************************************************************************
57 *
58 * module boiler plate
59 *
60 ******************************************************************************/
61
62/*
63 * module name, copyright, version, etc.
64 */
65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
66
d3175167 67#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 68#define VD "d"
69#else
70#define VD
71#endif
72
73#define DRV_VERSION IWLWIFI_VERSION VD
74
be663ab6
WYG		 75MODULE_DESCRIPTION(DRV_DESCRIPTION);
76MODULE_VERSION(DRV_VERSION);
77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78MODULE_LICENSE("GPL");
79MODULE_ALIAS("iwl4965");
80
e7392364
SG		 81void
82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
fcb74588
SG		 83{
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
a6766ccd 86 if (!test_bit(S_EXIT_PENDING, &il->status))
fcb74588
SG		 87 queue_work(il->workqueue, &il->tx_flush);
88 }
89}
90
91/*
92 * EEPROM
93 */
94struct il_mod_params il4965_mod_params = {
95 .amsdu_size_8K = 1,
96 .restart_fw = 1,
97 /* the rest are 0 by default */
98};
99
e7392364
SG		 100void
101il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 102{
103 unsigned long flags;
104 int i;
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 114 PAGE_SIZE << il->hw_params.rx_page_order,
115 PCI_DMA_FROMDEVICE);
fcb74588
SG		 116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
118 }
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
120 }
121
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
124
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
129 rxq->free_count = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
131}
132
e7392364
SG		 133int
134il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 135{
136 u32 rb_size;
e7392364 137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
fcb74588
SG		 138 u32 rb_timeout = 0;
139
140 if (il->cfg->mod_params->amsdu_size_8K)
9a95b370 141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
fcb74588 142 else
9a95b370 143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
fcb74588
SG		 144
145 /* Stop Rx DMA */
9a95b370 146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
fcb74588
SG		 147
148 /* Reset driver's Rx queue write idx */
9a95b370 149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
fcb74588
SG		 150
151 /* Tell device where to find RBD circular buffer in DRAM */
e7392364 152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
fcb74588
SG		 153
154 /* Tell device where in DRAM to update its Rx status */
e7392364 155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
fcb74588
SG		 156
157 /* Enable Rx DMA
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
160 * RB timeout 0x10
161 * 256 RBDs
162 */
9a95b370 163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
e7392364
SG		 164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
1722f8e1
SG		 166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
167 rb_size |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
fcb74588
SG		 170
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
173
174 return 0;
175}
176
e7392364
SG		 177static void
178il4965_set_pwr_vmain(struct il_priv *il)
fcb74588
SG		 179{
180/*
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
183
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
188 */
189
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
e7392364
SG		 191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
fcb74588
SG		 193}
194
e7392364
SG		 195int
196il4965_hw_nic_init(struct il_priv *il)
fcb74588
SG		 197{
198 unsigned long flags;
199 struct il_rx_queue *rxq = &il->rxq;
200 int ret;
201
202 /* nic_init */
203 spin_lock_irqsave(&il->lock, flags);
c39ae9fd 204 il->ops->lib->apm_ops.init(il);
fcb74588
SG		 205
206 /* Set interrupt coalescing calibration timer to default (512 usecs) */
207 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
208
209 spin_unlock_irqrestore(&il->lock, flags);
210
211 il4965_set_pwr_vmain(il);
212
c39ae9fd 213 il->ops->lib->apm_ops.config(il);
fcb74588
SG		 214
215 /* Allocate the RX queue, or reset if it is already allocated */
216 if (!rxq->bd) {
217 ret = il_rx_queue_alloc(il);
218 if (ret) {
219 IL_ERR("Unable to initialize Rx queue\n");
220 return -ENOMEM;
221 }
222 } else
223 il4965_rx_queue_reset(il, rxq);
224
225 il4965_rx_replenish(il);
226
227 il4965_rx_init(il, rxq);
228
229 spin_lock_irqsave(&il->lock, flags);
230
231 rxq->need_update = 1;
232 il_rx_queue_update_write_ptr(il, rxq);
233
234 spin_unlock_irqrestore(&il->lock, flags);
235
236 /* Allocate or reset and init all Tx and Command queues */
237 if (!il->txq) {
238 ret = il4965_txq_ctx_alloc(il);
239 if (ret)
240 return ret;
241 } else
242 il4965_txq_ctx_reset(il);
243
a6766ccd 244 set_bit(S_INIT, &il->status);
fcb74588
SG		 245
246 return 0;
247}
248
249/**
250 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
251 */
e7392364
SG		 252static inline __le32
253il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
fcb74588 254{
e7392364 255 return cpu_to_le32((u32) (dma_addr >> 8));
fcb74588
SG		 256}
257
258/**
259 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
260 *
261 * If there are slots in the RX queue that need to be restocked,
262 * and we have free pre-allocated buffers, fill the ranks as much
263 * as we can, pulling from rx_free.
264 *
265 * This moves the 'write' idx forward to catch up with 'processed', and
266 * also updates the memory address in the firmware to reference the new
267 * target buffer.
268 */
e7392364
SG		 269void
270il4965_rx_queue_restock(struct il_priv *il)
fcb74588
SG		 271{
272 struct il_rx_queue *rxq = &il->rxq;
273 struct list_head *element;
274 struct il_rx_buf *rxb;
275 unsigned long flags;
276
277 spin_lock_irqsave(&rxq->lock, flags);
278 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
279 /* The overwritten rxb must be a used one */
280 rxb = rxq->queue[rxq->write];
281 BUG_ON(rxb && rxb->page);
282
283 /* Get next free Rx buffer, remove from free list */
284 element = rxq->rx_free.next;
285 rxb = list_entry(element, struct il_rx_buf, list);
286 list_del(element);
287
288 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG		 289 rxq->bd[rxq->write] =
290 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
fcb74588
SG		 291 rxq->queue[rxq->write] = rxb;
292 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
293 rxq->free_count--;
294 }
295 spin_unlock_irqrestore(&rxq->lock, flags);
296 /* If the pre-allocated buffer pool is dropping low, schedule to
297 * refill it */
298 if (rxq->free_count <= RX_LOW_WATERMARK)
299 queue_work(il->workqueue, &il->rx_replenish);
300
fcb74588
SG		 301 /* If we've added more space for the firmware to place data, tell it.
302 * Increment device's write pointer in multiples of 8. */
303 if (rxq->write_actual != (rxq->write & ~0x7)) {
304 spin_lock_irqsave(&rxq->lock, flags);
305 rxq->need_update = 1;
306 spin_unlock_irqrestore(&rxq->lock, flags);
307 il_rx_queue_update_write_ptr(il, rxq);
308 }
309}
310
311/**
312 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
313 *
314 * When moving to rx_free an SKB is allocated for the slot.
315 *
316 * Also restock the Rx queue via il_rx_queue_restock.
317 * This is called as a scheduled work item (except for during initialization)
318 */
e7392364
SG		 319static void
320il4965_rx_allocate(struct il_priv *il, gfp_t priority)
fcb74588
SG		 321{
322 struct il_rx_queue *rxq = &il->rxq;
323 struct list_head *element;
324 struct il_rx_buf *rxb;
325 struct page *page;
326 unsigned long flags;
327 gfp_t gfp_mask = priority;
328
329 while (1) {
330 spin_lock_irqsave(&rxq->lock, flags);
331 if (list_empty(&rxq->rx_used)) {
332 spin_unlock_irqrestore(&rxq->lock, flags);
333 return;
334 }
335 spin_unlock_irqrestore(&rxq->lock, flags);
336
337 if (rxq->free_count > RX_LOW_WATERMARK)
338 gfp_mask |= __GFP_NOWARN;
339
340 if (il->hw_params.rx_page_order > 0)
341 gfp_mask |= __GFP_COMP;
342
343 /* Alloc a new receive buffer */
344 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
345 if (!page) {
346 if (net_ratelimit())
e7392364
SG		 347 D_INFO("alloc_pages failed, " "order: %d\n",
348 il->hw_params.rx_page_order);
fcb74588
SG		 349
350 if (rxq->free_count <= RX_LOW_WATERMARK &&
351 net_ratelimit())
e7392364
SG		 352 IL_ERR("Failed to alloc_pages with %s. "
353 "Only %u free buffers remaining.\n",
354 priority ==
355 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
356 rxq->free_count);
fcb74588
SG		 357 /* We don't reschedule replenish work here -- we will
358 * call the restock method and if it still needs
359 * more buffers it will schedule replenish */
360 return;
361 }
362
363 spin_lock_irqsave(&rxq->lock, flags);
364
365 if (list_empty(&rxq->rx_used)) {
366 spin_unlock_irqrestore(&rxq->lock, flags);
367 __free_pages(page, il->hw_params.rx_page_order);
368 return;
369 }
370 element = rxq->rx_used.next;
371 rxb = list_entry(element, struct il_rx_buf, list);
372 list_del(element);
373
374 spin_unlock_irqrestore(&rxq->lock, flags);
375
376 BUG_ON(rxb->page);
377 rxb->page = page;
378 /* Get physical address of the RB */
e7392364
SG		 379 rxb->page_dma =
380 pci_map_page(il->pci_dev, page, 0,
381 PAGE_SIZE << il->hw_params.rx_page_order,
382 PCI_DMA_FROMDEVICE);
fcb74588
SG		 383 /* dma address must be no more than 36 bits */
384 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
385 /* and also 256 byte aligned! */
386 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
387
388 spin_lock_irqsave(&rxq->lock, flags);
389
390 list_add_tail(&rxb->list, &rxq->rx_free);
391 rxq->free_count++;
392 il->alloc_rxb_page++;
393
394 spin_unlock_irqrestore(&rxq->lock, flags);
395 }
396}
397
e7392364
SG		 398void
399il4965_rx_replenish(struct il_priv *il)
fcb74588
SG		 400{
401 unsigned long flags;
402
403 il4965_rx_allocate(il, GFP_KERNEL);
404
405 spin_lock_irqsave(&il->lock, flags);
406 il4965_rx_queue_restock(il);
407 spin_unlock_irqrestore(&il->lock, flags);
408}
409
e7392364
SG		 410void
411il4965_rx_replenish_now(struct il_priv *il)
fcb74588
SG		 412{
413 il4965_rx_allocate(il, GFP_ATOMIC);
414
415 il4965_rx_queue_restock(il);
416}
417
418/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
419 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
420 * This free routine walks the list of POOL entries and if SKB is set to
421 * non NULL it is unmapped and freed
422 */
e7392364
SG		 423void
424il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 425{
426 int i;
427 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
428 if (rxq->pool[i].page != NULL) {
429 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 430 PAGE_SIZE << il->hw_params.rx_page_order,
431 PCI_DMA_FROMDEVICE);
fcb74588
SG		 432 __il_free_pages(il, rxq->pool[i].page);
433 rxq->pool[i].page = NULL;
434 }
435 }
436
437 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
438 rxq->bd_dma);
439 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
440 rxq->rb_stts, rxq->rb_stts_dma);
441 rxq->bd = NULL;
e7392364 442 rxq->rb_stts = NULL;
fcb74588
SG		 443}
444
e7392364
SG		 445int
446il4965_rxq_stop(struct il_priv *il)
fcb74588
SG		 447{
448
449 /* stop Rx DMA */
9a95b370
SG		 450 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
451 il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
e7392364 452 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
fcb74588
SG		 453
454 return 0;
455}
456
e7392364
SG		 457int
458il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
fcb74588
SG		 459{
460 int idx = 0;
461 int band_offset = 0;
462
463 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
464 if (rate_n_flags & RATE_MCS_HT_MSK) {
465 idx = (rate_n_flags & 0xff);
466 return idx;
e7392364 467 /* Legacy rate format, search for match in table */
fcb74588
SG		 468 } else {
469 if (band == IEEE80211_BAND_5GHZ)
470 band_offset = IL_FIRST_OFDM_RATE;
471 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
472 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
473 return idx - band_offset;
474 }
475
476 return -1;
477}
478
e7392364
SG		 479static int
480il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
fcb74588
SG		 481{
482 /* data from PHY/DSP regarding signal strength, etc.,
483 * contents are always there, not configurable by host. */
484 struct il4965_rx_non_cfg_phy *ncphy =
485 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
e7392364
SG		 486 u32 agc =
487 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
488 IL49_AGC_DB_POS;
fcb74588
SG		 489
490 u32 valid_antennae =
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
e7392364 492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
fcb74588
SG		 493 u8 max_rssi = 0;
494 u32 i;
495
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
504
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
507 max_rssi, agc);
508
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
512}
513
e7392364
SG		 514static u32
515il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
fcb74588
SG		 516{
517 u32 decrypt_out = 0;
518
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
e7392364
SG		 520 RX_RES_STATUS_STATION_FOUND)
521 decrypt_out |=
522 (RX_RES_STATUS_STATION_FOUND |
523 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
fcb74588
SG		 524
525 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
526
527 /* packet was not encrypted */
528 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 529 RX_RES_STATUS_SEC_TYPE_NONE)
fcb74588
SG		 530 return decrypt_out;
531
532 /* packet was encrypted with unknown alg */
533 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 534 RX_RES_STATUS_SEC_TYPE_ERR)
fcb74588
SG		 535 return decrypt_out;
536
537 /* decryption was not done in HW */
538 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
e7392364 539 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
fcb74588
SG		 540 return decrypt_out;
541
542 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
543
544 case RX_RES_STATUS_SEC_TYPE_CCMP:
545 /* alg is CCM: check MIC only */
546 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
547 /* Bad MIC */
548 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
549 else
550 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
551
552 break;
553
554 case RX_RES_STATUS_SEC_TYPE_TKIP:
555 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
556 /* Bad TTAK */
557 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
558 break;
559 }
560 /* fall through if TTAK OK */
561 default:
562 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
563 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
564 else
565 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
566 break;
567 }
568
e7392364 569 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
fcb74588
SG		 570
571 return decrypt_out;
572}
573
e7392364
SG		 574static void
575il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
576 u16 len, u32 ampdu_status, struct il_rx_buf *rxb,
577 struct ieee80211_rx_status *stats)
fcb74588
SG		 578{
579 struct sk_buff *skb;
580 __le16 fc = hdr->frame_control;
581
582 /* We only process data packets if the interface is open */
583 if (unlikely(!il->is_open)) {
e7392364 584 D_DROP("Dropping packet while interface is not open.\n");
fcb74588
SG		 585 return;
586 }
587
588 /* In case of HW accelerated crypto and bad decryption, drop */
589 if (!il->cfg->mod_params->sw_crypto &&
590 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
591 return;
592
593 skb = dev_alloc_skb(128);
594 if (!skb) {
595 IL_ERR("dev_alloc_skb failed\n");
596 return;
597 }
598
599 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
600
601 il_update_stats(il, false, fc, len);
602 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
603
604 ieee80211_rx(il->hw, skb);
605 il->alloc_rxb_page--;
606 rxb->page = NULL;
607}
608
4d69c752
SG		 609/* Called for N_RX (legacy ABG frames), or
610 * N_RX_MPDU (HT high-throughput N frames). */
e7392364
SG		 611void
612il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 613{
614 struct ieee80211_hdr *header;
615 struct ieee80211_rx_status rx_status;
616 struct il_rx_pkt *pkt = rxb_addr(rxb);
617 struct il_rx_phy_res *phy_res;
618 __le32 rx_pkt_status;
619 struct il_rx_mpdu_res_start *amsdu;
620 u32 len;
621 u32 ampdu_status;
622 u32 rate_n_flags;
623
624 /**
4d69c752
SG		 625 * N_RX and N_RX_MPDU are handled differently.
626 * N_RX: physical layer info is in this buffer
627 * N_RX_MPDU: physical layer info was sent in separate
fcb74588
SG		 628 * command and cached in il->last_phy_res
629 *
630 * Here we set up local variables depending on which command is
631 * received.
632 */
4d69c752 633 if (pkt->hdr.cmd == N_RX) {
fcb74588 634 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
e7392364
SG		 635 header =
636 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
637 phy_res->cfg_phy_cnt);
fcb74588
SG		 638
639 len = le16_to_cpu(phy_res->byte_count);
e7392364
SG		 640 rx_pkt_status =
641 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
642 phy_res->cfg_phy_cnt + len);
fcb74588
SG		 643 ampdu_status = le32_to_cpu(rx_pkt_status);
644 } else {
645 if (!il->_4965.last_phy_res_valid) {
646 IL_ERR("MPDU frame without cached PHY data\n");
647 return;
648 }
649 phy_res = &il->_4965.last_phy_res;
650 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
651 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
652 len = le16_to_cpu(amsdu->byte_count);
e7392364
SG		 653 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
654 ampdu_status =
655 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
fcb74588
SG		 656 }
657
658 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
659 D_DROP("dsp size out of range [0,20]: %d/n",
e7392364 660 phy_res->cfg_phy_cnt);
fcb74588
SG		 661 return;
662 }
663
664 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
665 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e7392364 666 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
fcb74588
SG		 667 return;
668 }
669
670 /* This will be used in several places later */
671 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
672
673 /* rx_status carries information about the packet to mac80211 */
674 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
e7392364
SG		 675 rx_status.band =
676 (phy_res->
677 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
678 IEEE80211_BAND_5GHZ;
fcb74588 679 rx_status.freq =
e7392364
SG		 680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
681 rx_status.band);
fcb74588 682 rx_status.rate_idx =
e7392364 683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
fcb74588
SG		 684 rx_status.flag = 0;
685
686 /* TSF isn't reliable. In order to allow smooth user experience,
687 * this W/A doesn't propagate it to the mac80211 */
e7392364 688 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU; */
fcb74588
SG		 689
690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
691
692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
693 rx_status.signal = il4965_calc_rssi(il, phy_res);
694
695 il_dbg_log_rx_data_frame(il, len, header);
e7392364
SG		 696 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
697 (unsigned long long)rx_status.mactime);
fcb74588
SG		 698
699 /*
700 * "antenna number"
701 *
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
707 *
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
710 * as a bitmask.
711 */
712 rx_status.antenna =
e7392364
SG		 713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
714 RX_RES_PHY_FLAGS_ANTENNA_POS;
fcb74588
SG		 715
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
719
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
727
e7392364
SG		 728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
729 &rx_status);
fcb74588
SG		 730}
731
4d69c752 732/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
6e9848b4 733 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
e7392364
SG		 734void
735il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 736{
737 struct il_rx_pkt *pkt = rxb_addr(rxb);
738 il->_4965.last_phy_res_valid = true;
739 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
740 sizeof(struct il_rx_phy_res));
741}
742
e7392364
SG		 743static int
744il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
745 enum ieee80211_band band, u8 is_active,
746 u8 n_probes, struct il_scan_channel *scan_ch)
fcb74588
SG		 747{
748 struct ieee80211_channel *chan;
749 const struct ieee80211_supported_band *sband;
750 const struct il_channel_info *ch_info;
751 u16 passive_dwell = 0;
752 u16 active_dwell = 0;
753 int added, i;
754 u16 channel;
755
756 sband = il_get_hw_mode(il, band);
757 if (!sband)
758 return 0;
759
760 active_dwell = il_get_active_dwell_time(il, band, n_probes);
761 passive_dwell = il_get_passive_dwell_time(il, band, vif);
762
763 if (passive_dwell <= active_dwell)
764 passive_dwell = active_dwell + 1;
765
766 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
767 chan = il->scan_request->channels[i];
768
769 if (chan->band != band)
770 continue;
771
772 channel = chan->hw_value;
773 scan_ch->channel = cpu_to_le16(channel);
774
775 ch_info = il_get_channel_info(il, band, channel);
776 if (!il_is_channel_valid(ch_info)) {
e7392364
SG		 777 D_SCAN("Channel %d is INVALID for this band.\n",
778 channel);
fcb74588
SG		 779 continue;
780 }
781
782 if (!is_active || il_is_channel_passive(ch_info) ||
783 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
784 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
785 else
786 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
787
788 if (n_probes)
789 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
790
791 scan_ch->active_dwell = cpu_to_le16(active_dwell);
792 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
793
794 /* Set txpower levels to defaults */
795 scan_ch->dsp_atten = 110;
796
797 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
798 * power level:
799 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
800 */
801 if (band == IEEE80211_BAND_5GHZ)
802 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
803 else
804 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
805
e7392364
SG		 806 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
807 le32_to_cpu(scan_ch->type),
808 (scan_ch->
809 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
810 (scan_ch->
811 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
812 passive_dwell);
fcb74588
SG		 813
814 scan_ch++;
815 added++;
816 }
817
818 D_SCAN("total channels to scan %d\n", added);
819 return added;
820}
821
a0c1ef3b
SG		 822static void
823il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
824{
825 int i;
826 u8 ind = *ant;
827
828 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
829 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
830 if (valid & BIT(ind)) {
831 *ant = ind;
832 return;
833 }
834 }
835}
836
e7392364
SG		 837int
838il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
fcb74588
SG		 839{
840 struct il_host_cmd cmd = {
4d69c752 841 .id = C_SCAN,
fcb74588
SG		 842 .len = sizeof(struct il_scan_cmd),
843 .flags = CMD_SIZE_HUGE,
844 };
845 struct il_scan_cmd *scan;
fcb74588
SG		 846 u32 rate_flags = 0;
847 u16 cmd_len;
848 u16 rx_chain = 0;
849 enum ieee80211_band band;
850 u8 n_probes = 0;
851 u8 rx_ant = il->hw_params.valid_rx_ant;
852 u8 rate;
853 bool is_active = false;
e7392364 854 int chan_mod;
fcb74588
SG		 855 u8 active_chains;
856 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
857 int ret;
858
859 lockdep_assert_held(&il->mutex);
860
fcb74588 861 if (!il->scan_cmd) {
e7392364
SG		 862 il->scan_cmd =
863 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
864 GFP_KERNEL);
fcb74588 865 if (!il->scan_cmd) {
e7392364 866 D_SCAN("fail to allocate memory for scan\n");
fcb74588
SG		 867 return -ENOMEM;
868 }
869 }
870 scan = il->scan_cmd;
871 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
872
873 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
874 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
875
876 if (il_is_any_associated(il)) {
877 u16 interval;
878 u32 extra;
879 u32 suspend_time = 100;
880 u32 scan_suspend_time = 100;
881
882 D_INFO("Scanning while associated...\n");
883 interval = vif->bss_conf.beacon_int;
884
885 scan->suspend_time = 0;
886 scan->max_out_time = cpu_to_le32(200 * 1024);
887 if (!interval)
888 interval = suspend_time;
889
890 extra = (suspend_time / interval) << 22;
e7392364
SG		 891 scan_suspend_time =
892 (extra | ((suspend_time % interval) * 1024));
fcb74588
SG		 893 scan->suspend_time = cpu_to_le32(scan_suspend_time);
894 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 895 scan_suspend_time, interval);
fcb74588
SG		 896 }
897
898 if (il->scan_request->n_ssids) {
899 int i, p = 0;
900 D_SCAN("Kicking off active scan\n");
901 for (i = 0; i < il->scan_request->n_ssids; i++) {
902 /* always does wildcard anyway */
903 if (!il->scan_request->ssids[i].ssid_len)
904 continue;
905 scan->direct_scan[p].id = WLAN_EID_SSID;
906 scan->direct_scan[p].len =
e7392364 907 il->scan_request->ssids[i].ssid_len;
fcb74588
SG		 908 memcpy(scan->direct_scan[p].ssid,
909 il->scan_request->ssids[i].ssid,
910 il->scan_request->ssids[i].ssid_len);
911 n_probes++;
912 p++;
913 }
914 is_active = true;
915 } else
916 D_SCAN("Start passive scan.\n");
917
918 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 919 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
fcb74588
SG		 920 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
921
922 switch (il->scan_band) {
923 case IEEE80211_BAND_2GHZ:
924 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
e7392364 925 chan_mod =
c8b03958 926 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
e7392364 927 RXON_FLG_CHANNEL_MODE_POS;
fcb74588
SG		 928 if (chan_mod == CHANNEL_MODE_PURE_40) {
929 rate = RATE_6M_PLCP;
930 } else {
931 rate = RATE_1M_PLCP;
932 rate_flags = RATE_MCS_CCK_MSK;
933 }
934 break;
935 case IEEE80211_BAND_5GHZ:
936 rate = RATE_6M_PLCP;
937 break;
938 default:
939 IL_WARN("Invalid scan band\n");
940 return -EIO;
941 }
942
943 /*
944 * If active scanning is requested but a certain channel is
945 * marked passive, we can do active scanning if we detect
946 * transmissions.
947 *
948 * There is an issue with some firmware versions that triggers
949 * a sysassert on a "good CRC threshold" of zero (== disabled),
950 * on a radar channel even though this means that we should NOT
951 * send probes.
952 *
953 * The "good CRC threshold" is the number of frames that we
954 * need to receive during our dwell time on a channel before
955 * sending out probes -- setting this to a huge value will
956 * mean we never reach it, but at the same time work around
957 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
958 * here instead of IL_GOOD_CRC_TH_DISABLED.
959 */
e7392364
SG		 960 scan->good_CRC_th =
961 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
fcb74588
SG		 962
963 band = il->scan_band;
964
965 if (il->cfg->scan_rx_antennas[band])
966 rx_ant = il->cfg->scan_rx_antennas[band];
967
a0c1ef3b 968 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
616107ed
SG		 969 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
970 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
fcb74588
SG		 971
972 /* In power save mode use one chain, otherwise use all chains */
a6766ccd 973 if (test_bit(S_POWER_PMI, &il->status)) {
fcb74588 974 /* rx_ant has been set to all valid chains previously */
e7392364
SG		 975 active_chains =
976 rx_ant & ((u8) (il->chain_noise_data.active_chains));
fcb74588
SG		 977 if (!active_chains)
978 active_chains = rx_ant;
979
980 D_SCAN("chain_noise_data.active_chains: %u\n",
e7392364 981 il->chain_noise_data.active_chains);
fcb74588
SG		 982
983 rx_ant = il4965_first_antenna(active_chains);
984 }
985
986 /* MIMO is not used here, but value is required */
987 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
988 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
989 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
990 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
991 scan->rx_chain = cpu_to_le16(rx_chain);
992
e7392364
SG		 993 cmd_len =
994 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
995 vif->addr, il->scan_request->ie,
996 il->scan_request->ie_len,
997 IL_MAX_SCAN_SIZE - sizeof(*scan));
fcb74588
SG		 998 scan->tx_cmd.len = cpu_to_le16(cmd_len);
999
e7392364
SG		 1000 scan->filter_flags |=
1001 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
fcb74588 1002
e7392364
SG		 1003 scan->channel_count =
1004 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1005 (void *)&scan->data[cmd_len]);
fcb74588
SG		 1006 if (scan->channel_count == 0) {
1007 D_SCAN("channel count %d\n", scan->channel_count);
1008 return -EIO;
1009 }
1010
e7392364
SG		 1011 cmd.len +=
1012 le16_to_cpu(scan->tx_cmd.len) +
fcb74588
SG		 1013 scan->channel_count * sizeof(struct il_scan_channel);
1014 cmd.data = scan;
1015 scan->len = cpu_to_le16(cmd.len);
1016
a6766ccd 1017 set_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1018
1019 ret = il_send_cmd_sync(il, &cmd);
1020 if (ret)
a6766ccd 1021 clear_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1022
1023 return ret;
1024}
1025
e7392364
SG		 1026int
1027il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1028 bool add)
fcb74588
SG		 1029{
1030 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1031
1032 if (add)
83007196 1033 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
fcb74588
SG		 1034 &vif_priv->ibss_bssid_sta_id);
1035 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
e7392364 1036 vif->bss_conf.bssid);
fcb74588
SG		 1037}
1038
e7392364
SG		 1039void
1040il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
fcb74588
SG		 1041{
1042 lockdep_assert_held(&il->sta_lock);
1043
1044 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1045 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1046 else {
1047 D_TX("free more than tfds_in_queue (%u:%d)\n",
e7392364 1048 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
fcb74588
SG		 1049 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1050 }
1051}
1052
1053#define IL_TX_QUEUE_MSK 0xfffff
1054
e7392364
SG		 1055static bool
1056il4965_is_single_rx_stream(struct il_priv *il)
fcb74588
SG		 1057{
1058 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
e7392364 1059 il->current_ht_config.single_chain_sufficient;
fcb74588
SG		 1060}
1061
1062#define IL_NUM_RX_CHAINS_MULTIPLE 3
1063#define IL_NUM_RX_CHAINS_SINGLE 2
1064#define IL_NUM_IDLE_CHAINS_DUAL 2
1065#define IL_NUM_IDLE_CHAINS_SINGLE 1
1066
1067/*
1068 * Determine how many receiver/antenna chains to use.
1069 *
1070 * More provides better reception via diversity. Fewer saves power
1071 * at the expense of throughput, but only when not in powersave to
1072 * start with.
1073 *
1074 * MIMO (dual stream) requires at least 2, but works better with 3.
1075 * This does not determine *which* chains to use, just how many.
1076 */
e7392364
SG		 1077static int
1078il4965_get_active_rx_chain_count(struct il_priv *il)
fcb74588
SG		 1079{
1080 /* # of Rx chains to use when expecting MIMO. */
1081 if (il4965_is_single_rx_stream(il))
1082 return IL_NUM_RX_CHAINS_SINGLE;
1083 else
1084 return IL_NUM_RX_CHAINS_MULTIPLE;
1085}
1086
1087/*
1088 * When we are in power saving mode, unless device support spatial
1089 * multiplexing power save, use the active count for rx chain count.
1090 */
1091static int
1092il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1093{
1094 /* # Rx chains when idling, depending on SMPS mode */
1095 switch (il->current_ht_config.smps) {
1096 case IEEE80211_SMPS_STATIC:
1097 case IEEE80211_SMPS_DYNAMIC:
1098 return IL_NUM_IDLE_CHAINS_SINGLE;
1099 case IEEE80211_SMPS_OFF:
1100 return active_cnt;
1101 default:
e7392364 1102 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
fcb74588
SG		 1103 return active_cnt;
1104 }
1105}
1106
1107/* up to 4 chains */
e7392364
SG		 1108static u8
1109il4965_count_chain_bitmap(u32 chain_bitmap)
fcb74588
SG		 1110{
1111 u8 res;
1112 res = (chain_bitmap & BIT(0)) >> 0;
1113 res += (chain_bitmap & BIT(1)) >> 1;
1114 res += (chain_bitmap & BIT(2)) >> 2;
1115 res += (chain_bitmap & BIT(3)) >> 3;
1116 return res;
1117}
1118
1119/**
1120 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1121 *
1122 * Selects how many and which Rx receivers/antennas/chains to use.
1123 * This should not be used for scan command ... it puts data in wrong place.
1124 */
e7392364 1125void
83007196 1126il4965_set_rxon_chain(struct il_priv *il)
fcb74588
SG		 1127{
1128 bool is_single = il4965_is_single_rx_stream(il);
a6766ccd 1129 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
fcb74588
SG		 1130 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1131 u32 active_chains;
1132 u16 rx_chain;
1133
1134 /* Tell uCode which antennas are actually connected.
1135 * Before first association, we assume all antennas are connected.
1136 * Just after first association, il4965_chain_noise_calibration()
1137 * checks which antennas actually *are* connected. */
1138 if (il->chain_noise_data.active_chains)
1139 active_chains = il->chain_noise_data.active_chains;
1140 else
1141 active_chains = il->hw_params.valid_rx_ant;
1142
1143 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1144
1145 /* How many receivers should we use? */
1146 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1147 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1148
fcb74588
SG		 1149 /* correct rx chain count according hw settings
1150 * and chain noise calibration
1151 */
1152 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1153 if (valid_rx_cnt < active_rx_cnt)
1154 active_rx_cnt = valid_rx_cnt;
1155
1156 if (valid_rx_cnt < idle_rx_cnt)
1157 idle_rx_cnt = valid_rx_cnt;
1158
1159 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
e7392364 1160 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
fcb74588 1161
c8b03958 1162 il->staging.rx_chain = cpu_to_le16(rx_chain);
fcb74588
SG		 1163
1164 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
c8b03958 1165 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1166 else
c8b03958 1167 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1168
c8b03958 1169 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
e7392364 1170 active_rx_cnt, idle_rx_cnt);
fcb74588
SG		 1171
1172 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1173 active_rx_cnt < idle_rx_cnt);
1174}
1175
e7392364
SG		 1176static const char *
1177il4965_get_fh_string(int cmd)
fcb74588
SG		 1178{
1179 switch (cmd) {
e7392364
SG		 1180 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1181 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1182 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1183 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1184 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1185 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1186 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1187 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1188 IL_CMD(FH49_TSSR_TX_ERROR_REG);
fcb74588
SG		 1189 default:
1190 return "UNKNOWN";
1191 }
1192}
1193
e7392364
SG		 1194int
1195il4965_dump_fh(struct il_priv *il, char **buf, bool display)
fcb74588
SG		 1196{
1197 int i;
1198#ifdef CONFIG_IWLEGACY_DEBUG
1199 int pos = 0;
1200 size_t bufsz = 0;
1201#endif
1202 static const u32 fh_tbl[] = {
9a95b370
SG		 1203 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1204 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1205 FH49_RSCSR_CHNL0_WPTR,
1206 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1207 FH49_MEM_RSSR_SHARED_CTRL_REG,
1208 FH49_MEM_RSSR_RX_STATUS_REG,
1209 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1210 FH49_TSSR_TX_STATUS_REG,
1211 FH49_TSSR_TX_ERROR_REG
fcb74588
SG		 1212 };
1213#ifdef CONFIG_IWLEGACY_DEBUG
1214 if (display) {
1215 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1216 *buf = kmalloc(bufsz, GFP_KERNEL);
1217 if (!*buf)
1218 return -ENOMEM;
e7392364
SG		 1219 pos +=
1220 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
fcb74588 1221 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
e7392364
SG		 1222 pos +=
1223 scnprintf(*buf + pos, bufsz - pos,
1224 " %34s: 0X%08x\n",
1722f8e1
SG		 1225 il4965_get_fh_string(fh_tbl[i]),
1226 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1227 }
1228 return pos;
1229 }
1230#endif
1231 IL_ERR("FH register values:\n");
e7392364
SG		 1232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1233 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1234 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1235 }
1236 return 0;
1237}
a1751b22 1238
e7392364
SG		 1239void
1240il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1241{
1242 struct il_rx_pkt *pkt = rxb_addr(rxb);
1243 struct il_missed_beacon_notif *missed_beacon;
1244
1245 missed_beacon = &pkt->u.missed_beacon;
1246 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1247 il->missed_beacon_threshold) {
e7392364
SG		 1248 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1249 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1250 le32_to_cpu(missed_beacon->total_missed_becons),
1251 le32_to_cpu(missed_beacon->num_recvd_beacons),
1252 le32_to_cpu(missed_beacon->num_expected_beacons));
a6766ccd 1253 if (!test_bit(S_SCANNING, &il->status))
a1751b22
SG		 1254 il4965_init_sensitivity(il);
1255 }
1256}
1257
1258/* Calculate noise level, based on measurements during network silence just
1259 * before arriving beacon. This measurement can be done only if we know
1260 * exactly when to expect beacons, therefore only when we're associated. */
e7392364
SG		 1261static void
1262il4965_rx_calc_noise(struct il_priv *il)
a1751b22
SG		 1263{
1264 struct stats_rx_non_phy *rx_info;
1265 int num_active_rx = 0;
1266 int total_silence = 0;
1267 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1268 int last_rx_noise;
1269
1270 rx_info = &(il->_4965.stats.rx.general);
1271 bcn_silence_a =
e7392364 1272 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
a1751b22 1273 bcn_silence_b =
e7392364 1274 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
a1751b22 1275 bcn_silence_c =
e7392364 1276 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
a1751b22
SG		 1277
1278 if (bcn_silence_a) {
1279 total_silence += bcn_silence_a;
1280 num_active_rx++;
1281 }
1282 if (bcn_silence_b) {
1283 total_silence += bcn_silence_b;
1284 num_active_rx++;
1285 }
1286 if (bcn_silence_c) {
1287 total_silence += bcn_silence_c;
1288 num_active_rx++;
1289 }
1290
1291 /* Average among active antennas */
1292 if (num_active_rx)
1293 last_rx_noise = (total_silence / num_active_rx) - 107;
1294 else
1295 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1296
e7392364
SG		 1297 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1298 bcn_silence_b, bcn_silence_c, last_rx_noise);
a1751b22
SG		 1299}
1300
1301#ifdef CONFIG_IWLEGACY_DEBUGFS
1302/*
1303 * based on the assumption of all stats counter are in DWORD
1304 * FIXME: This function is for debugging, do not deal with
1305 * the case of counters roll-over.
1306 */
e7392364
SG		 1307static void
1308il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
a1751b22
SG		 1309{
1310 int i, size;
1311 __le32 *prev_stats;
1312 u32 *accum_stats;
1313 u32 *delta, *max_delta;
1314 struct stats_general_common *general, *accum_general;
1315 struct stats_tx *tx, *accum_tx;
1316
1722f8e1
SG		 1317 prev_stats = (__le32 *) &il->_4965.stats;
1318 accum_stats = (u32 *) &il->_4965.accum_stats;
a1751b22
SG		 1319 size = sizeof(struct il_notif_stats);
1320 general = &il->_4965.stats.general.common;
1321 accum_general = &il->_4965.accum_stats.general.common;
1322 tx = &il->_4965.stats.tx;
1323 accum_tx = &il->_4965.accum_stats.tx;
1722f8e1
SG		 1324 delta = (u32 *) &il->_4965.delta_stats;
1325 max_delta = (u32 *) &il->_4965.max_delta;
a1751b22
SG		 1326
1327 for (i = sizeof(__le32); i < size;
e7392364
SG		 1328 i +=
1329 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1330 accum_stats++) {
a1751b22 1331 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
e7392364
SG		 1332 *delta =
1333 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
a1751b22
SG		 1334 *accum_stats += *delta;
1335 if (*delta > *max_delta)
1336 *max_delta = *delta;
1337 }
1338 }
1339
1340 /* reset accumulative stats for "no-counter" type stats */
1341 accum_general->temperature = general->temperature;
1342 accum_general->ttl_timestamp = general->ttl_timestamp;
1343}
1344#endif
1345
1346#define REG_RECALIB_PERIOD (60)
1347
e7392364
SG		 1348void
1349il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1350{
1351 int change;
1352 struct il_rx_pkt *pkt = rxb_addr(rxb);
1353
e7392364
SG		 1354 D_RX("Statistics notification received (%d vs %d).\n",
1355 (int)sizeof(struct il_notif_stats),
1356 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1357
1358 change =
1359 ((il->_4965.stats.general.common.temperature !=
1360 pkt->u.stats.general.common.temperature) ||
1361 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1362 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
a1751b22 1363#ifdef CONFIG_IWLEGACY_DEBUGFS
1722f8e1 1364 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
a1751b22
SG		 1365#endif
1366
1367 /* TODO: reading some of stats is unneeded */
e7392364 1368 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
a1751b22 1369
db7746f7 1370 set_bit(S_STATS, &il->status);
a1751b22
SG		 1371
1372 /* Reschedule the stats timer to occur in
1373 * REG_RECALIB_PERIOD seconds to ensure we get a
1374 * thermal update even if the uCode doesn't give
1375 * us one */
e7392364
SG		 1376 mod_timer(&il->stats_periodic,
1377 jiffies + msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
a1751b22 1378
a6766ccd 1379 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
4d69c752 1380 (pkt->hdr.cmd == N_STATS)) {
a1751b22
SG		 1381 il4965_rx_calc_noise(il);
1382 queue_work(il->workqueue, &il->run_time_calib_work);
1383 }
c39ae9fd
SG		 1384 if (il->ops->lib->temp_ops.temperature && change)
1385 il->ops->lib->temp_ops.temperature(il);
a1751b22
SG		 1386}
1387
e7392364
SG		 1388void
1389il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1390{
1391 struct il_rx_pkt *pkt = rxb_addr(rxb);
1392
db7746f7 1393 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
a1751b22
SG		 1394#ifdef CONFIG_IWLEGACY_DEBUGFS
1395 memset(&il->_4965.accum_stats, 0,
e7392364 1396 sizeof(struct il_notif_stats));
a1751b22 1397 memset(&il->_4965.delta_stats, 0,
e7392364
SG		 1398 sizeof(struct il_notif_stats));
1399 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
a1751b22
SG		 1400#endif
1401 D_RX("Statistics have been cleared\n");
1402 }
d2dfb33e 1403 il4965_hdl_stats(il, rxb);
a1751b22
SG		 1404}
1405
8f29b456
SG		 1406
1407/*
1408 * mac80211 queues, ACs, hardware queues, FIFOs.
1409 *
1410 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1411 *
1412 * Mac80211 uses the following numbers, which we get as from it
1413 * by way of skb_get_queue_mapping(skb):
1414 *
1415 * VO 0
1416 * VI 1
1417 * BE 2
1418 * BK 3
1419 *
1420 *
1421 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1422 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1423 * own queue per aggregation session (RA/TID combination), such queues are
1424 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1425 * order to map frames to the right queue, we also need an AC->hw queue
1426 * mapping. This is implemented here.
1427 *
1428 * Due to the way hw queues are set up (by the hw specific modules like
af038f40 1429 * 4965.c), the AC->hw queue mapping is the identity
8f29b456
SG		 1430 * mapping.
1431 */
1432
a1751b22
SG		 1433static const u8 tid_to_ac[] = {
1434 IEEE80211_AC_BE,
1435 IEEE80211_AC_BK,
1436 IEEE80211_AC_BK,
1437 IEEE80211_AC_BE,
1438 IEEE80211_AC_VI,
1439 IEEE80211_AC_VI,
1440 IEEE80211_AC_VO,
1441 IEEE80211_AC_VO
1442};
1443
e7392364
SG		 1444static inline int
1445il4965_get_ac_from_tid(u16 tid)
a1751b22
SG		 1446{
1447 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1448 return tid_to_ac[tid];
1449
1450 /* no support for TIDs 8-15 yet */
1451 return -EINVAL;
1452}
1453
1454static inline int
83007196 1455il4965_get_fifo_from_tid(u16 tid)
a1751b22 1456{
b75b3a70
SG		 1457 const u8 ac_to_fifo[] = {
1458 IL_TX_FIFO_VO,
1459 IL_TX_FIFO_VI,
1460 IL_TX_FIFO_BE,
1461 IL_TX_FIFO_BK,
1462 };
1463
a1751b22 1464 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
b75b3a70 1465 return ac_to_fifo[tid_to_ac[tid]];
a1751b22
SG		 1466
1467 /* no support for TIDs 8-15 yet */
1468 return -EINVAL;
1469}
1470
1471/*
4d69c752 1472 * handle build C_TX command notification.
a1751b22 1473 */
e7392364
SG		 1474static void
1475il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1476 struct il_tx_cmd *tx_cmd,
1477 struct ieee80211_tx_info *info,
1478 struct ieee80211_hdr *hdr, u8 std_id)
a1751b22
SG		 1479{
1480 __le16 fc = hdr->frame_control;
1481 __le32 tx_flags = tx_cmd->tx_flags;
1482
1483 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1484 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1485 tx_flags |= TX_CMD_FLG_ACK_MSK;
1486 if (ieee80211_is_mgmt(fc))
1487 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1488 if (ieee80211_is_probe_resp(fc) &&
1489 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1490 tx_flags |= TX_CMD_FLG_TSF_MSK;
1491 } else {
1492 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1493 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1494 }
1495
1496 if (ieee80211_is_back_req(fc))
1497 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1498
1499 tx_cmd->sta_id = std_id;
1500 if (ieee80211_has_morefrags(fc))
1501 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1502
1503 if (ieee80211_is_data_qos(fc)) {
1504 u8 *qc = ieee80211_get_qos_ctl(hdr);
1505 tx_cmd->tid_tspec = qc[0] & 0xf;
1506 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1507 } else {
1508 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1509 }
1510
1511 il_tx_cmd_protection(il, info, fc, &tx_flags);
1512
1513 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1514 if (ieee80211_is_mgmt(fc)) {
1515 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1516 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1517 else
1518 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1519 } else {
1520 tx_cmd->timeout.pm_frame_timeout = 0;
1521 }
1522
1523 tx_cmd->driver_txop = 0;
1524 tx_cmd->tx_flags = tx_flags;
1525 tx_cmd->next_frame_len = 0;
1526}
1527
e7392364
SG		 1528static void
1529il4965_tx_cmd_build_rate(struct il_priv *il, struct il_tx_cmd *tx_cmd,
1530 struct ieee80211_tx_info *info, __le16 fc)
a1751b22 1531{
616107ed 1532 const u8 rts_retry_limit = 60;
a1751b22
SG		 1533 u32 rate_flags;
1534 int rate_idx;
a1751b22
SG		 1535 u8 data_retry_limit;
1536 u8 rate_plcp;
1537
e7392364 1538 /* Set retry limit on DATA packets and Probe Responses */
a1751b22
SG		 1539 if (ieee80211_is_probe_resp(fc))
1540 data_retry_limit = 3;
1541 else
1542 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1543 tx_cmd->data_retry_limit = data_retry_limit;
a1751b22 1544 /* Set retry limit on RTS packets */
616107ed 1545 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
a1751b22
SG		 1546
1547 /* DATA packets will use the uCode station table for rate/antenna
1548 * selection */
1549 if (ieee80211_is_data(fc)) {
1550 tx_cmd->initial_rate_idx = 0;
1551 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1552 return;
1553 }
1554
1555 /**
1556 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1557 * not really a TX rate. Thus, we use the lowest supported rate for
1558 * this band. Also use the lowest supported rate if the stored rate
1559 * idx is invalid.
1560 */
1561 rate_idx = info->control.rates[0].idx;
e7392364
SG		 1562 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1563 || rate_idx > RATE_COUNT_LEGACY)
1564 rate_idx =
1565 rate_lowest_index(&il->bands[info->band],
1566 info->control.sta);
a1751b22
SG		 1567 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1568 if (info->band == IEEE80211_BAND_5GHZ)
1569 rate_idx += IL_FIRST_OFDM_RATE;
1570 /* Get PLCP rate for tx_cmd->rate_n_flags */
1571 rate_plcp = il_rates[rate_idx].plcp;
1572 /* Zero out flags for this packet */
1573 rate_flags = 0;
1574
1575 /* Set CCK flag as needed */
1576 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1577 rate_flags |= RATE_MCS_CCK_MSK;
1578
1579 /* Set up antennas */
a0c1ef3b 1580 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 1581 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
a1751b22
SG		 1582
1583 /* Set the rate in the TX cmd */
616107ed 1584 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
a1751b22
SG		 1585}
1586
e7392364
SG		 1587static void
1588il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1589 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1590 int sta_id)
a1751b22
SG		 1591{
1592 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1593
1594 switch (keyconf->cipher) {
1595 case WLAN_CIPHER_SUITE_CCMP:
1596 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1597 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1598 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1599 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1600 D_TX("tx_cmd with AES hwcrypto\n");
1601 break;
1602
1603 case WLAN_CIPHER_SUITE_TKIP:
1604 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1605 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1606 D_TX("tx_cmd with tkip hwcrypto\n");
1607 break;
1608
1609 case WLAN_CIPHER_SUITE_WEP104:
1610 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1611 /* fall through */
1612 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG		 1613 tx_cmd->sec_ctl |=
1614 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1615 TX_CMD_SEC_SHIFT);
a1751b22
SG		 1616
1617 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1618
e7392364
SG		 1619 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1620 keyconf->keyidx);
a1751b22
SG		 1621 break;
1622
1623 default:
1624 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1625 break;
1626 }
1627}
1628
1629/*
4d69c752 1630 * start C_TX command process
a1751b22 1631 */
e7392364
SG		 1632int
1633il4965_tx_skb(struct il_priv *il, struct sk_buff *skb)
a1751b22
SG		 1634{
1635 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1636 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1637 struct ieee80211_sta *sta = info->control.sta;
1638 struct il_station_priv *sta_priv = NULL;
1639 struct il_tx_queue *txq;
1640 struct il_queue *q;
1641 struct il_device_cmd *out_cmd;
1642 struct il_cmd_meta *out_meta;
1643 struct il_tx_cmd *tx_cmd;
a1751b22
SG		 1644 int txq_id;
1645 dma_addr_t phys_addr;
1646 dma_addr_t txcmd_phys;
1647 dma_addr_t scratch_phys;
1648 u16 len, firstlen, secondlen;
1649 u16 seq_number = 0;
1650 __le16 fc;
1651 u8 hdr_len;
1652 u8 sta_id;
1653 u8 wait_write_ptr = 0;
1654 u8 tid = 0;
1655 u8 *qc = NULL;
1656 unsigned long flags;
1657 bool is_agg = false;
1658
a1751b22
SG		 1659 spin_lock_irqsave(&il->lock, flags);
1660 if (il_is_rfkill(il)) {
1661 D_DROP("Dropping - RF KILL\n");
1662 goto drop_unlock;
1663 }
1664
1665 fc = hdr->frame_control;
1666
1667#ifdef CONFIG_IWLEGACY_DEBUG
1668 if (ieee80211_is_auth(fc))
1669 D_TX("Sending AUTH frame\n");
1670 else if (ieee80211_is_assoc_req(fc))
1671 D_TX("Sending ASSOC frame\n");
1672 else if (ieee80211_is_reassoc_req(fc))
1673 D_TX("Sending REASSOC frame\n");
1674#endif
1675
1676 hdr_len = ieee80211_hdrlen(fc);
1677
1678 /* For management frames use broadcast id to do not break aggregation */
1679 if (!ieee80211_is_data(fc))
b16db50a 1680 sta_id = il->hw_params.bcast_id;
a1751b22
SG		 1681 else {
1682 /* Find idx into station table for destination station */
83007196 1683 sta_id = il_sta_id_or_broadcast(il, info->control.sta);
a1751b22
SG		 1684
1685 if (sta_id == IL_INVALID_STATION) {
e7392364 1686 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
a1751b22
SG		 1687 goto drop_unlock;
1688 }
1689 }
1690
1691 D_TX("station Id %d\n", sta_id);
1692
1693 if (sta)
1694 sta_priv = (void *)sta->drv_priv;
1695
1696 if (sta_priv && sta_priv->asleep &&
1697 (info->flags & IEEE80211_TX_CTL_POLL_RESPONSE)) {
1698 /*
1699 * This sends an asynchronous command to the device,
1700 * but we can rely on it being processed before the
1701 * next frame is processed -- and the next frame to
1702 * this station is the one that will consume this
1703 * counter.
1704 * For now set the counter to just 1 since we do not
1705 * support uAPSD yet.
1706 */
1707 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1708 }
1709
d1e14e94
SG		 1710 /* FIXME: remove me ? */
1711 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1712
eb123af3
SG		 1713 /* Access category (AC) is also the queue number */
1714 txq_id = skb_get_queue_mapping(skb);
a1751b22
SG		 1715
1716 /* irqs already disabled/saved above when locking il->lock */
1717 spin_lock(&il->sta_lock);
1718
1719 if (ieee80211_is_data_qos(fc)) {
1720 qc = ieee80211_get_qos_ctl(hdr);
1721 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1722 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1723 spin_unlock(&il->sta_lock);
1724 goto drop_unlock;
1725 }
1726 seq_number = il->stations[sta_id].tid[tid].seq_number;
1727 seq_number &= IEEE80211_SCTL_SEQ;
e7392364
SG		 1728 hdr->seq_ctrl =
1729 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
a1751b22
SG		 1730 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1731 seq_number += 0x10;
1732 /* aggregation is on for this <sta,tid> */
1733 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1734 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1735 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1736 is_agg = true;
1737 }
1738 }
1739
1740 txq = &il->txq[txq_id];
1741 q = &txq->q;
1742
1743 if (unlikely(il_queue_space(q) < q->high_mark)) {
1744 spin_unlock(&il->sta_lock);
1745 goto drop_unlock;
1746 }
1747
1748 if (ieee80211_is_data_qos(fc)) {
1749 il->stations[sta_id].tid[tid].tfds_in_queue++;
1750 if (!ieee80211_has_morefrags(fc))
1751 il->stations[sta_id].tid[tid].seq_number = seq_number;
1752 }
1753
1754 spin_unlock(&il->sta_lock);
1755
1756 /* Set up driver data for this TFD */
1757 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info));
1758 txq->txb[q->write_ptr].skb = skb;
a1751b22
SG		 1759
1760 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1761 out_cmd = txq->cmd[q->write_ptr];
1762 out_meta = &txq->meta[q->write_ptr];
1763 tx_cmd = &out_cmd->cmd.tx;
1764 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1765 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1766
1767 /*
1768 * Set up the Tx-command (not MAC!) header.
1769 * Store the chosen Tx queue and TFD idx within the sequence field;
1770 * after Tx, uCode's Tx response will return this value so driver can
1771 * locate the frame within the tx queue and do post-tx processing.
1772 */
4d69c752 1773 out_cmd->hdr.cmd = C_TX;
e7392364
SG		 1774 out_cmd->hdr.sequence =
1775 cpu_to_le16((u16)
1776 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
a1751b22
SG		 1777
1778 /* Copy MAC header from skb into command buffer */
1779 memcpy(tx_cmd->hdr, hdr, hdr_len);
1780
a1751b22 1781 /* Total # bytes to be transmitted */
e7392364 1782 len = (u16) skb->len;
a1751b22
SG		 1783 tx_cmd->len = cpu_to_le16(len);
1784
1785 if (info->control.hw_key)
1786 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1787
1788 /* TODO need this for burst mode later on */
1789 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1790 il_dbg_log_tx_data_frame(il, len, hdr);
1791
1792 il4965_tx_cmd_build_rate(il, tx_cmd, info, fc);
1793
1794 il_update_stats(il, true, fc, len);
1795 /*
1796 * Use the first empty entry in this queue's command buffer array
1797 * to contain the Tx command and MAC header concatenated together
1798 * (payload data will be in another buffer).
1799 * Size of this varies, due to varying MAC header length.
1800 * If end is not dword aligned, we'll have 2 extra bytes at the end
1801 * of the MAC header (device reads on dword boundaries).
1802 * We'll tell device about this padding later.
1803 */
e7392364 1804 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
a1751b22
SG		 1805 firstlen = (len + 3) & ~3;
1806
1807 /* Tell NIC about any 2-byte padding after MAC header */
1808 if (firstlen != len)
1809 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1810
1811 /* Physical address of this Tx command's header (not MAC header!),
1812 * within command buffer array. */
e7392364
SG		 1813 txcmd_phys =
1814 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1815 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1816 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1817 dma_unmap_len_set(out_meta, len, firstlen);
1818 /* Add buffer containing Tx command and MAC(!) header to TFD's
1819 * first entry */
c39ae9fd 1820 il->ops->lib->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
a1751b22
SG		 1821
1822 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1823 txq->need_update = 1;
1824 } else {
1825 wait_write_ptr = 1;
1826 txq->need_update = 0;
1827 }
1828
1829 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1830 * if any (802.11 null frames have no payload). */
1831 secondlen = skb->len - hdr_len;
1832 if (secondlen > 0) {
e7392364
SG		 1833 phys_addr =
1834 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1835 PCI_DMA_TODEVICE);
c39ae9fd
SG		 1836 il->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr,
1837 secondlen, 0, 0);
a1751b22
SG		 1838 }
1839
e7392364
SG		 1840 scratch_phys =
1841 txcmd_phys + sizeof(struct il_cmd_header) +
1842 offsetof(struct il_tx_cmd, scratch);
a1751b22
SG		 1843
1844 /* take back ownership of DMA buffer to enable update */
e7392364
SG		 1845 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1846 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1847 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1848 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1849
e7392364 1850 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
a1751b22 1851 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
e7392364
SG		 1852 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1853 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
a1751b22
SG		 1854
1855 /* Set up entry for this TFD in Tx byte-count array */
1856 if (info->flags & IEEE80211_TX_CTL_AMPDU)
c39ae9fd
SG		 1857 il->ops->lib->txq_update_byte_cnt_tbl(il, txq,
1858 le16_to_cpu(tx_cmd->len));
a1751b22 1859
e7392364
SG		 1860 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1861 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1862
1863 /* Tell device the write idx *just past* this latest filled TFD */
1864 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1865 il_txq_update_write_ptr(il, txq);
1866 spin_unlock_irqrestore(&il->lock, flags);
1867
1868 /*
1869 * At this point the frame is "transmitted" successfully
1870 * and we will get a TX status notification eventually,
1871 * regardless of the value of ret. "ret" only indicates
1872 * whether or not we should update the write pointer.
1873 */
1874
1875 /*
1876 * Avoid atomic ops if it isn't an associated client.
1877 * Also, if this is a packet for aggregation, don't
1878 * increase the counter because the ucode will stop
1879 * aggregation queues when their respective station
1880 * goes to sleep.
1881 */
1882 if (sta_priv && sta_priv->client && !is_agg)
1883 atomic_inc(&sta_priv->pending_frames);
1884
1885 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1886 if (wait_write_ptr) {
1887 spin_lock_irqsave(&il->lock, flags);
1888 txq->need_update = 1;
1889 il_txq_update_write_ptr(il, txq);
1890 spin_unlock_irqrestore(&il->lock, flags);
1891 } else {
1892 il_stop_queue(il, txq);
1893 }
1894 }
1895
1896 return 0;
1897
1898drop_unlock:
1899 spin_unlock_irqrestore(&il->lock, flags);
1900 return -1;
1901}
1902
e7392364
SG		 1903static inline int
1904il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
a1751b22 1905{
e7392364
SG		 1906 ptr->addr =
1907 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL);
a1751b22
SG		 1908 if (!ptr->addr)
1909 return -ENOMEM;
1910 ptr->size = size;
1911 return 0;
1912}
1913
e7392364
SG		 1914static inline void
1915il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
a1751b22
SG		 1916{
1917 if (unlikely(!ptr->addr))
1918 return;
1919
1920 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1921 memset(ptr, 0, sizeof(*ptr));
1922}
1923
1924/**
1925 * il4965_hw_txq_ctx_free - Free TXQ Context
1926 *
1927 * Destroy all TX DMA queues and structures
1928 */
e7392364
SG		 1929void
1930il4965_hw_txq_ctx_free(struct il_priv *il)
a1751b22
SG		 1931{
1932 int txq_id;
1933
1934 /* Tx queues */
1935 if (il->txq) {
1936 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1937 if (txq_id == il->cmd_queue)
1938 il_cmd_queue_free(il);
1939 else
1940 il_tx_queue_free(il, txq_id);
1941 }
1942 il4965_free_dma_ptr(il, &il->kw);
1943
1944 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1945
1946 /* free tx queue structure */
1947 il_txq_mem(il);
1948}
1949
1950/**
1951 * il4965_txq_ctx_alloc - allocate TX queue context
1952 * Allocate all Tx DMA structures and initialize them
1953 *
1954 * @param il
1955 * @return error code
1956 */
e7392364
SG		 1957int
1958il4965_txq_ctx_alloc(struct il_priv *il)
a1751b22
SG		 1959{
1960 int ret;
1961 int txq_id, slots_num;
1962 unsigned long flags;
1963
1964 /* Free all tx/cmd queues and keep-warm buffer */
1965 il4965_hw_txq_ctx_free(il);
1966
e7392364
SG		 1967 ret =
1968 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1969 il->hw_params.scd_bc_tbls_size);
a1751b22
SG		 1970 if (ret) {
1971 IL_ERR("Scheduler BC Table allocation failed\n");
1972 goto error_bc_tbls;
1973 }
1974 /* Alloc keep-warm buffer */
1975 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1976 if (ret) {
1977 IL_ERR("Keep Warm allocation failed\n");
1978 goto error_kw;
1979 }
1980
1981 /* allocate tx queue structure */
1982 ret = il_alloc_txq_mem(il);
1983 if (ret)
1984 goto error;
1985
1986 spin_lock_irqsave(&il->lock, flags);
1987
1988 /* Turn off all Tx DMA fifos */
1989 il4965_txq_set_sched(il, 0);
1990
1991 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 1992 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 1993
1994 spin_unlock_irqrestore(&il->lock, flags);
1995
1996 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1997 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
e7392364
SG		 1998 slots_num =
1999 (txq_id ==
2000 il->cmd_queue) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
2001 ret = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
a1751b22
SG		 2002 if (ret) {
2003 IL_ERR("Tx %d queue init failed\n", txq_id);
2004 goto error;
2005 }
2006 }
2007
2008 return ret;
2009
e7392364 2010error:
a1751b22
SG		 2011 il4965_hw_txq_ctx_free(il);
2012 il4965_free_dma_ptr(il, &il->kw);
e7392364 2013error_kw:
a1751b22 2014 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
e7392364 2015error_bc_tbls:
a1751b22
SG		 2016 return ret;
2017}
2018
e7392364
SG		 2019void
2020il4965_txq_ctx_reset(struct il_priv *il)
a1751b22
SG		 2021{
2022 int txq_id, slots_num;
2023 unsigned long flags;
2024
2025 spin_lock_irqsave(&il->lock, flags);
2026
2027 /* Turn off all Tx DMA fifos */
2028 il4965_txq_set_sched(il, 0);
2029
2030 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2031 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2032
2033 spin_unlock_irqrestore(&il->lock, flags);
2034
2035 /* Alloc and init all Tx queues, including the command queue (#4) */
2036 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
e7392364
SG		 2037 slots_num =
2038 txq_id == il->cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
2039 il_tx_queue_reset(il, &il->txq[txq_id], slots_num, txq_id);
a1751b22
SG		 2040 }
2041}
2042
2043/**
2044 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2045 */
e7392364
SG		 2046void
2047il4965_txq_ctx_stop(struct il_priv *il)
a1751b22
SG		 2048{
2049 int ch, txq_id;
2050 unsigned long flags;
2051
2052 /* Turn off all Tx DMA fifos */
2053 spin_lock_irqsave(&il->lock, flags);
2054
2055 il4965_txq_set_sched(il, 0);
2056
2057 /* Stop each Tx DMA channel, and wait for it to be idle */
2058 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
e7392364
SG		 2059 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2060 if (il_poll_bit
2061 (il, FH49_TSSR_TX_STATUS_REG,
2062 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000))
a1751b22 2063 IL_ERR("Failing on timeout while stopping"
1722f8e1
SG		 2064 " DMA channel %d [0x%08x]", ch,
2065 il_rd(il, FH49_TSSR_TX_STATUS_REG));
a1751b22
SG		 2066 }
2067 spin_unlock_irqrestore(&il->lock, flags);
2068
2069 if (!il->txq)
2070 return;
2071
2072 /* Unmap DMA from host system and free skb's */
2073 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2074 if (txq_id == il->cmd_queue)
2075 il_cmd_queue_unmap(il);
2076 else
2077 il_tx_queue_unmap(il, txq_id);
2078}
2079
2080/*
2081 * Find first available (lowest unused) Tx Queue, mark it "active".
2082 * Called only when finding queue for aggregation.
2083 * Should never return anything < 7, because they should already
2084 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2085 */
e7392364
SG		 2086static int
2087il4965_txq_ctx_activate_free(struct il_priv *il)
a1751b22
SG		 2088{
2089 int txq_id;
2090
2091 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2092 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2093 return txq_id;
2094 return -1;
2095}
2096
2097/**
2098 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2099 */
e7392364
SG		 2100static void
2101il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
a1751b22
SG		 2102{
2103 /* Simply stop the queue, but don't change any configuration;
2104 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
e7392364 2105 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 2106 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2107 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
a1751b22
SG		 2108}
2109
2110/**
2111 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2112 */
e7392364
SG		 2113static int
2114il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
a1751b22
SG		 2115{
2116 u32 tbl_dw_addr;
2117 u32 tbl_dw;
2118 u16 scd_q2ratid;
2119
2120 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2121
e7392364
SG		 2122 tbl_dw_addr =
2123 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
a1751b22
SG		 2124
2125 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2126
2127 if (txq_id & 0x1)
2128 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2129 else
2130 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2131
2132 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2133
2134 return 0;
2135}
2136
2137/**
2138 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2139 *
2140 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2141 * i.e. it must be one of the higher queues used for aggregation
2142 */
e7392364
SG		 2143static int
2144il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2145 int tid, u16 ssn_idx)
a1751b22
SG		 2146{
2147 unsigned long flags;
2148 u16 ra_tid;
2149 int ret;
2150
2151 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2152 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2153 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2154 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2155 txq_id, IL49_FIRST_AMPDU_QUEUE,
2156 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2157 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2158 return -EINVAL;
2159 }
2160
2161 ra_tid = BUILD_RAxTID(sta_id, tid);
2162
2163 /* Modify device's station table to Tx this TID */
2164 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2165 if (ret)
2166 return ret;
2167
2168 spin_lock_irqsave(&il->lock, flags);
2169
2170 /* Stop this Tx queue before configuring it */
2171 il4965_tx_queue_stop_scheduler(il, txq_id);
2172
2173 /* Map receiver-address / traffic-ID to this queue */
2174 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2175
2176 /* Set this queue as a chain-building queue */
2177 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2178
2179 /* Place first TFD at idx corresponding to start sequence number.
2180 * Assumes that ssn_idx is valid (!= 0xFFF) */
2181 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2182 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2183 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2184
2185 /* Set up Tx win size and frame limit for this queue */
2186 il_write_targ_mem(il,
e7392364
SG		 2187 il->scd_base_addr +
2188 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2189 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2190 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
a1751b22 2191
e7392364
SG		 2192 il_write_targ_mem(il,
2193 il->scd_base_addr +
2194 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2195 (SCD_FRAME_LIMIT <<
2196 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2197 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
a1751b22
SG		 2198
2199 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2200
2201 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2202 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2203
2204 spin_unlock_irqrestore(&il->lock, flags);
2205
2206 return 0;
2207}
2208
e7392364
SG		 2209int
2210il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2211 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
a1751b22
SG		 2212{
2213 int sta_id;
2214 int tx_fifo;
2215 int txq_id;
2216 int ret;
2217 unsigned long flags;
2218 struct il_tid_data *tid_data;
2219
83007196
SG		 2220 /* FIXME: warning if tx fifo not found ? */
2221 tx_fifo = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2222 if (unlikely(tx_fifo < 0))
2223 return tx_fifo;
2224
53611e05 2225 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
a1751b22
SG		 2226
2227 sta_id = il_sta_id(sta);
2228 if (sta_id == IL_INVALID_STATION) {
2229 IL_ERR("Start AGG on invalid station\n");
2230 return -ENXIO;
2231 }
2232 if (unlikely(tid >= MAX_TID_COUNT))
2233 return -EINVAL;
2234
2235 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2236 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2237 return -ENXIO;
2238 }
2239
2240 txq_id = il4965_txq_ctx_activate_free(il);
2241 if (txq_id == -1) {
2242 IL_ERR("No free aggregation queue available\n");
2243 return -ENXIO;
2244 }
2245
2246 spin_lock_irqsave(&il->sta_lock, flags);
2247 tid_data = &il->stations[sta_id].tid[tid];
2248 *ssn = SEQ_TO_SN(tid_data->seq_number);
2249 tid_data->agg.txq_id = txq_id;
e7392364 2250 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
a1751b22
SG		 2251 spin_unlock_irqrestore(&il->sta_lock, flags);
2252
e7392364 2253 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
a1751b22
SG		 2254 if (ret)
2255 return ret;
2256
2257 spin_lock_irqsave(&il->sta_lock, flags);
2258 tid_data = &il->stations[sta_id].tid[tid];
2259 if (tid_data->tfds_in_queue == 0) {
2260 D_HT("HW queue is empty\n");
2261 tid_data->agg.state = IL_AGG_ON;
2262 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2263 } else {
e7392364
SG		 2264 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2265 tid_data->tfds_in_queue);
a1751b22
SG		 2266 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2267 }
2268 spin_unlock_irqrestore(&il->sta_lock, flags);
2269 return ret;
2270}
2271
2272/**
2273 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2274 * il->lock must be held by the caller
2275 */
e7392364
SG		 2276static int
2277il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
a1751b22
SG		 2278{
2279 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2280 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2281 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2282 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2283 txq_id, IL49_FIRST_AMPDU_QUEUE,
2284 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2285 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2286 return -EINVAL;
2287 }
2288
2289 il4965_tx_queue_stop_scheduler(il, txq_id);
2290
e7392364 2291 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
a1751b22
SG		 2292
2293 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2294 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2295 /* supposes that ssn_idx is valid (!= 0xFFF) */
2296 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2297
e7392364 2298 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
a1751b22
SG		 2299 il_txq_ctx_deactivate(il, txq_id);
2300 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2301
2302 return 0;
2303}
2304
e7392364
SG		 2305int
2306il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2307 struct ieee80211_sta *sta, u16 tid)
a1751b22
SG		 2308{
2309 int tx_fifo_id, txq_id, sta_id, ssn;
2310 struct il_tid_data *tid_data;
2311 int write_ptr, read_ptr;
2312 unsigned long flags;
2313
83007196
SG		 2314 /* FIXME: warning if tx_fifo_id not found ? */
2315 tx_fifo_id = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2316 if (unlikely(tx_fifo_id < 0))
2317 return tx_fifo_id;
2318
2319 sta_id = il_sta_id(sta);
2320
2321 if (sta_id == IL_INVALID_STATION) {
2322 IL_ERR("Invalid station for AGG tid %d\n", tid);
2323 return -ENXIO;
2324 }
2325
2326 spin_lock_irqsave(&il->sta_lock, flags);
2327
2328 tid_data = &il->stations[sta_id].tid[tid];
2329 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2330 txq_id = tid_data->agg.txq_id;
2331
2332 switch (il->stations[sta_id].tid[tid].agg.state) {
2333 case IL_EMPTYING_HW_QUEUE_ADDBA:
2334 /*
2335 * This can happen if the peer stops aggregation
2336 * again before we've had a chance to drain the
2337 * queue we selected previously, i.e. before the
2338 * session was really started completely.
2339 */
2340 D_HT("AGG stop before setup done\n");
2341 goto turn_off;
2342 case IL_AGG_ON:
2343 break;
2344 default:
2345 IL_WARN("Stopping AGG while state not ON or starting\n");
2346 }
2347
2348 write_ptr = il->txq[txq_id].q.write_ptr;
2349 read_ptr = il->txq[txq_id].q.read_ptr;
2350
2351 /* The queue is not empty */
2352 if (write_ptr != read_ptr) {
2353 D_HT("Stopping a non empty AGG HW QUEUE\n");
2354 il->stations[sta_id].tid[tid].agg.state =
e7392364 2355 IL_EMPTYING_HW_QUEUE_DELBA;
a1751b22
SG		 2356 spin_unlock_irqrestore(&il->sta_lock, flags);
2357 return 0;
2358 }
2359
2360 D_HT("HW queue is empty\n");
e7392364 2361turn_off:
a1751b22
SG		 2362 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2363
2364 /* do not restore/save irqs */
2365 spin_unlock(&il->sta_lock);
2366 spin_lock(&il->lock);
2367
2368 /*
2369 * the only reason this call can fail is queue number out of range,
2370 * which can happen if uCode is reloaded and all the station
2371 * information are lost. if it is outside the range, there is no need
2372 * to deactivate the uCode queue, just return "success" to allow
2373 * mac80211 to clean up it own data.
2374 */
2375 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2376 spin_unlock_irqrestore(&il->lock, flags);
2377
2378 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2379
2380 return 0;
2381}
2382
e7392364
SG		 2383int
2384il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
a1751b22
SG		 2385{
2386 struct il_queue *q = &il->txq[txq_id].q;
2387 u8 *addr = il->stations[sta_id].sta.sta.addr;
2388 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
a1751b22
SG		 2389
2390 lockdep_assert_held(&il->sta_lock);
2391
2392 switch (il->stations[sta_id].tid[tid].agg.state) {
2393 case IL_EMPTYING_HW_QUEUE_DELBA:
2394 /* We are reclaiming the last packet of the */
2395 /* aggregated HW queue */
e7392364 2396 if (txq_id == tid_data->agg.txq_id &&
a1751b22
SG		 2397 q->read_ptr == q->write_ptr) {
2398 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
83007196 2399 int tx_fifo = il4965_get_fifo_from_tid(tid);
e7392364 2400 D_HT("HW queue empty: continue DELBA flow\n");
a1751b22
SG		 2401 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2402 tid_data->agg.state = IL_AGG_OFF;
83007196 2403 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2404 }
2405 break;
2406 case IL_EMPTYING_HW_QUEUE_ADDBA:
2407 /* We are reclaiming the last packet of the queue */
2408 if (tid_data->tfds_in_queue == 0) {
e7392364 2409 D_HT("HW queue empty: continue ADDBA flow\n");
a1751b22 2410 tid_data->agg.state = IL_AGG_ON;
83007196 2411 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2412 }
2413 break;
2414 }
2415
2416 return 0;
2417}
2418
e7392364 2419static void
83007196 2420il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
a1751b22
SG		 2421{
2422 struct ieee80211_sta *sta;
2423 struct il_station_priv *sta_priv;
2424
2425 rcu_read_lock();
83007196 2426 sta = ieee80211_find_sta(il->vif, addr1);
a1751b22
SG		 2427 if (sta) {
2428 sta_priv = (void *)sta->drv_priv;
2429 /* avoid atomic ops if this isn't a client */
2430 if (sta_priv->client &&
2431 atomic_dec_return(&sta_priv->pending_frames) == 0)
2432 ieee80211_sta_block_awake(il->hw, sta, false);
2433 }
2434 rcu_read_unlock();
2435}
2436
2437static void
e7392364 2438il4965_tx_status(struct il_priv *il, struct il_tx_info *tx_info, bool is_agg)
a1751b22 2439{
e7392364 2440 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
a1751b22
SG		 2441
2442 if (!is_agg)
83007196 2443 il4965_non_agg_tx_status(il, hdr->addr1);
a1751b22
SG		 2444
2445 ieee80211_tx_status_irqsafe(il->hw, tx_info->skb);
2446}
2447
e7392364
SG		 2448int
2449il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
a1751b22
SG		 2450{
2451 struct il_tx_queue *txq = &il->txq[txq_id];
2452 struct il_queue *q = &txq->q;
2453 struct il_tx_info *tx_info;
2454 int nfreed = 0;
2455 struct ieee80211_hdr *hdr;
2456
2457 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2458 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 2459 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2460 q->write_ptr, q->read_ptr);
a1751b22
SG		 2461 return 0;
2462 }
2463
e7392364 2464 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
a1751b22
SG		 2465 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2466
2467 tx_info = &txq->txb[txq->q.read_ptr];
2468
2469 if (WARN_ON_ONCE(tx_info->skb == NULL))
2470 continue;
2471
2472 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
2473 if (ieee80211_is_data_qos(hdr->frame_control))
2474 nfreed++;
2475
2476 il4965_tx_status(il, tx_info,
2477 txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2478 tx_info->skb = NULL;
2479
c39ae9fd 2480 il->ops->lib->txq_free_tfd(il, txq);
a1751b22
SG		 2481 }
2482 return nfreed;
2483}
2484
2485/**
2486 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2487 *
2488 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2489 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2490 */
e7392364
SG		 2491static int
2492il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2493 struct il_compressed_ba_resp *ba_resp)
a1751b22
SG		 2494{
2495 int i, sh, ack;
2496 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2497 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2498 int successes = 0;
2499 struct ieee80211_tx_info *info;
2500 u64 bitmap, sent_bitmap;
2501
e7392364 2502 if (unlikely(!agg->wait_for_ba)) {
a1751b22
SG		 2503 if (unlikely(ba_resp->bitmap))
2504 IL_ERR("Received BA when not expected\n");
2505 return -EINVAL;
2506 }
2507
2508 /* Mark that the expected block-ack response arrived */
2509 agg->wait_for_ba = 0;
e7392364 2510 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
a1751b22
SG		 2511
2512 /* Calculate shift to align block-ack bits with our Tx win bits */
2513 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
e7392364 2514 if (sh < 0) /* tbw something is wrong with indices */
a1751b22
SG		 2515 sh += 0x100;
2516
2517 if (agg->frame_count > (64 - sh)) {
2518 D_TX_REPLY("more frames than bitmap size");
2519 return -1;
2520 }
2521
2522 /* don't use 64-bit values for now */
2523 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2524
2525 /* check for success or failure according to the
2526 * transmitted bitmap and block-ack bitmap */
2527 sent_bitmap = bitmap & agg->bitmap;
2528
2529 /* For each frame attempted in aggregation,
2530 * update driver's record of tx frame's status. */
2531 i = 0;
2532 while (sent_bitmap) {
2533 ack = sent_bitmap & 1ULL;
2534 successes += ack;
e7392364
SG		 2535 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2536 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
a1751b22
SG		 2537 sent_bitmap >>= 1;
2538 ++i;
2539 }
2540
e7392364 2541 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
a1751b22
SG		 2542
2543 info = IEEE80211_SKB_CB(il->txq[scd_flow].txb[agg->start_idx].skb);
2544 memset(&info->status, 0, sizeof(info->status));
2545 info->flags |= IEEE80211_TX_STAT_ACK;
2546 info->flags |= IEEE80211_TX_STAT_AMPDU;
2547 info->status.ampdu_ack_len = successes;
2548 info->status.ampdu_len = agg->frame_count;
2549 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2550
2551 return 0;
2552}
2553
2554/**
2555 * translate ucode response to mac80211 tx status control values
2556 */
e7392364
SG		 2557void
2558il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2559 struct ieee80211_tx_info *info)
a1751b22
SG		 2560{
2561 struct ieee80211_tx_rate *r = &info->control.rates[0];
2562
2563 info->antenna_sel_tx =
e7392364 2564 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
a1751b22
SG		 2565 if (rate_n_flags & RATE_MCS_HT_MSK)
2566 r->flags |= IEEE80211_TX_RC_MCS;
2567 if (rate_n_flags & RATE_MCS_GF_MSK)
2568 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2569 if (rate_n_flags & RATE_MCS_HT40_MSK)
2570 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2571 if (rate_n_flags & RATE_MCS_DUP_MSK)
2572 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2573 if (rate_n_flags & RATE_MCS_SGI_MSK)
2574 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2575 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2576}
2577
2578/**
6e9848b4 2579 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
a1751b22
SG		 2580 *
2581 * Handles block-acknowledge notification from device, which reports success
2582 * of frames sent via aggregation.
2583 */
e7392364
SG		 2584void
2585il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 2586{
2587 struct il_rx_pkt *pkt = rxb_addr(rxb);
2588 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2589 struct il_tx_queue *txq = NULL;
2590 struct il_ht_agg *agg;
2591 int idx;
2592 int sta_id;
2593 int tid;
2594 unsigned long flags;
2595
2596 /* "flow" corresponds to Tx queue */
2597 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2598
2599 /* "ssn" is start of block-ack Tx win, corresponds to idx
2600 * (in Tx queue's circular buffer) of first TFD/frame in win */
2601 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2602
2603 if (scd_flow >= il->hw_params.max_txq_num) {
e7392364 2604 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
a1751b22
SG		 2605 return;
2606 }
2607
2608 txq = &il->txq[scd_flow];
2609 sta_id = ba_resp->sta_id;
2610 tid = ba_resp->tid;
2611 agg = &il->stations[sta_id].tid[tid].agg;
2612 if (unlikely(agg->txq_id != scd_flow)) {
2613 /*
2614 * FIXME: this is a uCode bug which need to be addressed,
2615 * log the information and return for now!
2616 * since it is possible happen very often and in order
2617 * not to fill the syslog, don't enable the logging by default
2618 */
e7392364
SG		 2619 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2620 scd_flow, agg->txq_id);
a1751b22
SG		 2621 return;
2622 }
2623
2624 /* Find idx just before block-ack win */
2625 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2626
2627 spin_lock_irqsave(&il->sta_lock, flags);
2628
e7392364 2629 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
1722f8e1 2630 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
e7392364
SG		 2631 ba_resp->sta_id);
2632 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2633 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2634 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2635 ba_resp->scd_flow, ba_resp->scd_ssn);
2636 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2637 (unsigned long long)agg->bitmap);
a1751b22
SG		 2638
2639 /* Update driver's record of ACK vs. not for each frame in win */
2640 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2641
2642 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2643 * block-ack win (we assume that they've been successfully
2644 * transmitted ... if not, it's too late anyway). */
2645 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2646 /* calculate mac80211 ampdu sw queue to wake */
2647 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2648 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2649
2650 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2651 il->mac80211_registered &&
2652 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2653 il_wake_queue(il, txq);
2654
2655 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2656 }
2657
2658 spin_unlock_irqrestore(&il->sta_lock, flags);
2659}
2660
2661#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2662const char *
2663il4965_get_tx_fail_reason(u32 status)
a1751b22
SG		 2664{
2665#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2666#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2667
2668 switch (status & TX_STATUS_MSK) {
2669 case TX_STATUS_SUCCESS:
2670 return "SUCCESS";
e7392364
SG		 2671 TX_STATUS_POSTPONE(DELAY);
2672 TX_STATUS_POSTPONE(FEW_BYTES);
2673 TX_STATUS_POSTPONE(QUIET_PERIOD);
2674 TX_STATUS_POSTPONE(CALC_TTAK);
2675 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2676 TX_STATUS_FAIL(SHORT_LIMIT);
2677 TX_STATUS_FAIL(LONG_LIMIT);
2678 TX_STATUS_FAIL(FIFO_UNDERRUN);
2679 TX_STATUS_FAIL(DRAIN_FLOW);
2680 TX_STATUS_FAIL(RFKILL_FLUSH);
2681 TX_STATUS_FAIL(LIFE_EXPIRE);
2682 TX_STATUS_FAIL(DEST_PS);
2683 TX_STATUS_FAIL(HOST_ABORTED);
2684 TX_STATUS_FAIL(BT_RETRY);
2685 TX_STATUS_FAIL(STA_INVALID);
2686 TX_STATUS_FAIL(FRAG_DROPPED);
2687 TX_STATUS_FAIL(TID_DISABLE);
2688 TX_STATUS_FAIL(FIFO_FLUSHED);
2689 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
2690 TX_STATUS_FAIL(PASSIVE_NO_RX);
2691 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
a1751b22
SG		 2692 }
2693
2694 return "UNKNOWN";
2695
2696#undef TX_STATUS_FAIL
2697#undef TX_STATUS_POSTPONE
2698}
2699#endif /* CONFIG_IWLEGACY_DEBUG */
2700
eb3cdfb7
SG		 2701static struct il_link_quality_cmd *
2702il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
2703{
2704 int i, r;
2705 struct il_link_quality_cmd *link_cmd;
2706 u32 rate_flags = 0;
2707 __le32 rate_n_flags;
2708
2709 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
2710 if (!link_cmd) {
2711 IL_ERR("Unable to allocate memory for LQ cmd.\n");
2712 return NULL;
2713 }
2714 /* Set up the rate scaling to start at selected rate, fall back
2715 * all the way down to 1M in IEEE order, and then spin on 1M */
2716 if (il->band == IEEE80211_BAND_5GHZ)
2717 r = RATE_6M_IDX;
2718 else
2719 r = RATE_1M_IDX;
2720
2721 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
2722 rate_flags |= RATE_MCS_CCK_MSK;
2723
e7392364
SG		 2724 rate_flags |=
2725 il4965_first_antenna(il->hw_params.
2726 valid_tx_ant) << RATE_MCS_ANT_POS;
616107ed 2727 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
eb3cdfb7
SG		 2728 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
2729 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
2730
2731 link_cmd->general_params.single_stream_ant_msk =
e7392364 2732 il4965_first_antenna(il->hw_params.valid_tx_ant);
eb3cdfb7
SG		 2733
2734 link_cmd->general_params.dual_stream_ant_msk =
e7392364
SG		 2735 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
2736 valid_tx_ant);
eb3cdfb7
SG		 2737 if (!link_cmd->general_params.dual_stream_ant_msk) {
2738 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
2739 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
2740 link_cmd->general_params.dual_stream_ant_msk =
e7392364 2741 il->hw_params.valid_tx_ant;
eb3cdfb7
SG		 2742 }
2743
2744 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
2745 link_cmd->agg_params.agg_time_limit =
e7392364 2746 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
eb3cdfb7
SG		 2747
2748 link_cmd->sta_id = sta_id;
2749
2750 return link_cmd;
2751}
2752
2753/*
2754 * il4965_add_bssid_station - Add the special IBSS BSSID station
2755 *
2756 * Function sleeps.
2757 */
2758int
83007196 2759il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
eb3cdfb7
SG		 2760{
2761 int ret;
2762 u8 sta_id;
2763 struct il_link_quality_cmd *link_cmd;
2764 unsigned long flags;
2765
2766 if (sta_id_r)
2767 *sta_id_r = IL_INVALID_STATION;
2768
83007196 2769 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
eb3cdfb7
SG		 2770 if (ret) {
2771 IL_ERR("Unable to add station %pM\n", addr);
2772 return ret;
2773 }
2774
2775 if (sta_id_r)
2776 *sta_id_r = sta_id;
2777
2778 spin_lock_irqsave(&il->sta_lock, flags);
2779 il->stations[sta_id].used |= IL_STA_LOCAL;
2780 spin_unlock_irqrestore(&il->sta_lock, flags);
2781
2782 /* Set up default rate scaling table in device's station table */
2783 link_cmd = il4965_sta_alloc_lq(il, sta_id);
2784 if (!link_cmd) {
e7392364
SG		 2785 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
2786 addr);
eb3cdfb7
SG		 2787 return -ENOMEM;
2788 }
2789
83007196 2790 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
eb3cdfb7
SG		 2791 if (ret)
2792 IL_ERR("Link quality command failed (%d)\n", ret);
2793
2794 spin_lock_irqsave(&il->sta_lock, flags);
2795 il->stations[sta_id].lq = link_cmd;
2796 spin_unlock_irqrestore(&il->sta_lock, flags);
2797
2798 return 0;
2799}
2800
e7392364 2801static int
83007196 2802il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
eb3cdfb7 2803{
d735f921 2804 int i;
eb3cdfb7
SG		 2805 u8 buff[sizeof(struct il_wep_cmd) +
2806 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
2807 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
e7392364 2808 size_t cmd_size = sizeof(struct il_wep_cmd);
eb3cdfb7 2809 struct il_host_cmd cmd = {
d98e2942 2810 .id = C_WEPKEY,
eb3cdfb7
SG		 2811 .data = wep_cmd,
2812 .flags = CMD_SYNC,
2813 };
d735f921 2814 bool not_empty = false;
eb3cdfb7
SG		 2815
2816 might_sleep();
2817
e7392364
SG		 2818 memset(wep_cmd, 0,
2819 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
eb3cdfb7 2820
e7392364 2821 for (i = 0; i < WEP_KEYS_MAX; i++) {
d735f921
SG		 2822 u8 key_size = il->_4965.wep_keys[i].key_size;
2823
eb3cdfb7 2824 wep_cmd->key[i].key_idx = i;
d735f921 2825 if (key_size) {
eb3cdfb7 2826 wep_cmd->key[i].key_offset = i;
d735f921
SG		 2827 not_empty = true;
2828 } else
eb3cdfb7 2829 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
eb3cdfb7 2830
d735f921
SG		 2831 wep_cmd->key[i].key_size = key_size;
2832 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
eb3cdfb7
SG		 2833 }
2834
2835 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
2836 wep_cmd->num_keys = WEP_KEYS_MAX;
2837
2838 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
eb3cdfb7
SG		 2839 cmd.len = cmd_size;
2840
2841 if (not_empty || send_if_empty)
2842 return il_send_cmd(il, &cmd);
2843 else
2844 return 0;
2845}
2846
e7392364 2847int
83007196 2848il4965_restore_default_wep_keys(struct il_priv *il)
eb3cdfb7
SG		 2849{
2850 lockdep_assert_held(&il->mutex);
2851
83007196 2852 return il4965_static_wepkey_cmd(il, false);
eb3cdfb7
SG		 2853}
2854
e7392364 2855int
83007196 2856il4965_remove_default_wep_key(struct il_priv *il,
e7392364 2857 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 2858{
2859 int ret;
d735f921 2860 int idx = keyconf->keyidx;
eb3cdfb7
SG		 2861
2862 lockdep_assert_held(&il->mutex);
2863
d735f921 2864 D_WEP("Removing default WEP key: idx=%d\n", idx);
eb3cdfb7 2865
d735f921 2866 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
eb3cdfb7 2867 if (il_is_rfkill(il)) {
e7392364 2868 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
eb3cdfb7
SG		 2869 /* but keys in device are clear anyway so return success */
2870 return 0;
2871 }
83007196 2872 ret = il4965_static_wepkey_cmd(il, 1);
d735f921 2873 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
eb3cdfb7
SG		 2874
2875 return ret;
2876}
2877
e7392364 2878int
83007196 2879il4965_set_default_wep_key(struct il_priv *il,
e7392364 2880 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 2881{
2882 int ret;
d735f921
SG		 2883 int len = keyconf->keylen;
2884 int idx = keyconf->keyidx;
eb3cdfb7
SG		 2885
2886 lockdep_assert_held(&il->mutex);
2887
d735f921 2888 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
eb3cdfb7
SG		 2889 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
2890 return -EINVAL;
2891 }
2892
2893 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2894 keyconf->hw_key_idx = HW_KEY_DEFAULT;
8f9e5645 2895 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
eb3cdfb7 2896
d735f921
SG		 2897 il->_4965.wep_keys[idx].key_size = len;
2898 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
eb3cdfb7 2899
83007196 2900 ret = il4965_static_wepkey_cmd(il, false);
eb3cdfb7 2901
d735f921 2902 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
eb3cdfb7
SG		 2903 return ret;
2904}
2905
e7392364 2906static int
83007196 2907il4965_set_wep_dynamic_key_info(struct il_priv *il,
e7392364 2908 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 2909{
2910 unsigned long flags;
2911 __le16 key_flags = 0;
2912 struct il_addsta_cmd sta_cmd;
2913
2914 lockdep_assert_held(&il->mutex);
2915
2916 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2917
2918 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
2919 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2920 key_flags &= ~STA_KEY_FLG_INVALID;
2921
2922 if (keyconf->keylen == WEP_KEY_LEN_128)
2923 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
2924
b16db50a 2925 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 2926 key_flags |= STA_KEY_MULTICAST_MSK;
2927
2928 spin_lock_irqsave(&il->sta_lock, flags);
2929
2930 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
2931 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
2932 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
2933
e7392364 2934 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 2935
e7392364
SG		 2936 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
2937 keyconf->keylen);
eb3cdfb7 2938
e7392364
SG		 2939 if ((il->stations[sta_id].sta.key.
2940 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 2941 il->stations[sta_id].sta.key.key_offset =
e7392364 2942 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 2943 /* else, we are overriding an existing key => no need to allocated room
2944 * in uCode. */
2945
2946 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 2947 "no space for a new key");
eb3cdfb7
SG		 2948
2949 il->stations[sta_id].sta.key.key_flags = key_flags;
2950 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
2951 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2952
2953 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 2954 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 2955 spin_unlock_irqrestore(&il->sta_lock, flags);
2956
2957 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2958}
2959
e7392364
SG		 2960static int
2961il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
e7392364 2962 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 2963{
2964 unsigned long flags;
2965 __le16 key_flags = 0;
2966 struct il_addsta_cmd sta_cmd;
2967
2968 lockdep_assert_held(&il->mutex);
2969
2970 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
2971 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2972 key_flags &= ~STA_KEY_FLG_INVALID;
2973
b16db50a 2974 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 2975 key_flags |= STA_KEY_MULTICAST_MSK;
2976
2977 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2978
2979 spin_lock_irqsave(&il->sta_lock, flags);
2980 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
2981 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
2982
e7392364 2983 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 2984
e7392364 2985 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
eb3cdfb7 2986
e7392364
SG		 2987 if ((il->stations[sta_id].sta.key.
2988 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 2989 il->stations[sta_id].sta.key.key_offset =
e7392364 2990 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 2991 /* else, we are overriding an existing key => no need to allocated room
2992 * in uCode. */
2993
2994 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 2995 "no space for a new key");
eb3cdfb7
SG		 2996
2997 il->stations[sta_id].sta.key.key_flags = key_flags;
2998 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
2999 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3000
3001 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3002 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3003 spin_unlock_irqrestore(&il->sta_lock, flags);
3004
3005 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3006}
3007
e7392364
SG		 3008static int
3009il4965_set_tkip_dynamic_key_info(struct il_priv *il,
e7392364 3010 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3011{
3012 unsigned long flags;
3013 int ret = 0;
3014 __le16 key_flags = 0;
3015
3016 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3017 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3018 key_flags &= ~STA_KEY_FLG_INVALID;
3019
b16db50a 3020 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3021 key_flags |= STA_KEY_MULTICAST_MSK;
3022
3023 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3024 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3025
3026 spin_lock_irqsave(&il->sta_lock, flags);
3027
3028 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3029 il->stations[sta_id].keyinfo.keylen = 16;
3030
e7392364
SG		 3031 if ((il->stations[sta_id].sta.key.
3032 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3033 il->stations[sta_id].sta.key.key_offset =
e7392364 3034 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3035 /* else, we are overriding an existing key => no need to allocated room
3036 * in uCode. */
3037
3038 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3039 "no space for a new key");
eb3cdfb7
SG		 3040
3041 il->stations[sta_id].sta.key.key_flags = key_flags;
3042
eb3cdfb7
SG		 3043 /* This copy is acutally not needed: we get the key with each TX */
3044 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3045
3046 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3047
3048 spin_unlock_irqrestore(&il->sta_lock, flags);
3049
3050 return ret;
3051}
3052
e7392364 3053void
83007196
SG		 3054il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3055 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
eb3cdfb7
SG		 3056{
3057 u8 sta_id;
3058 unsigned long flags;
3059 int i;
3060
3061 if (il_scan_cancel(il)) {
3062 /* cancel scan failed, just live w/ bad key and rely
3063 briefly on SW decryption */
3064 return;
3065 }
3066
83007196 3067 sta_id = il_sta_id_or_broadcast(il, sta);
eb3cdfb7
SG		 3068 if (sta_id == IL_INVALID_STATION)
3069 return;
3070
3071 spin_lock_irqsave(&il->sta_lock, flags);
3072
3073 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3074
3075 for (i = 0; i < 5; i++)
3076 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
e7392364 3077 cpu_to_le16(phase1key[i]);
eb3cdfb7
SG		 3078
3079 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3080 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3081
3082 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3083
3084 spin_unlock_irqrestore(&il->sta_lock, flags);
eb3cdfb7
SG		 3085}
3086
e7392364 3087int
83007196 3088il4965_remove_dynamic_key(struct il_priv *il,
e7392364 3089 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3090{
3091 unsigned long flags;
3092 u16 key_flags;
3093 u8 keyidx;
3094 struct il_addsta_cmd sta_cmd;
3095
3096 lockdep_assert_held(&il->mutex);
3097
d735f921 3098 il->_4965.key_mapping_keys--;
eb3cdfb7
SG		 3099
3100 spin_lock_irqsave(&il->sta_lock, flags);
3101 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3102 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3103
e7392364 3104 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
eb3cdfb7
SG		 3105
3106 if (keyconf->keyidx != keyidx) {
3107 /* We need to remove a key with idx different that the one
3108 * in the uCode. This means that the key we need to remove has
3109 * been replaced by another one with different idx.
3110 * Don't do anything and return ok
3111 */
3112 spin_unlock_irqrestore(&il->sta_lock, flags);
3113 return 0;
3114 }
3115
3116 if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) {
e7392364
SG		 3117 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3118 key_flags);
eb3cdfb7
SG		 3119 spin_unlock_irqrestore(&il->sta_lock, flags);
3120 return 0;
3121 }
3122
e7392364
SG		 3123 if (!test_and_clear_bit
3124 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
eb3cdfb7 3125 IL_ERR("idx %d not used in uCode key table.\n",
e7392364
SG		 3126 il->stations[sta_id].sta.key.key_offset);
3127 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3128 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
eb3cdfb7 3129 il->stations[sta_id].sta.key.key_flags =
e7392364 3130 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
eb3cdfb7
SG		 3131 il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
3132 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3133 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3134
3135 if (il_is_rfkill(il)) {
e7392364
SG		 3136 D_WEP
3137 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
eb3cdfb7
SG		 3138 spin_unlock_irqrestore(&il->sta_lock, flags);
3139 return 0;
3140 }
3141 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3142 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3143 spin_unlock_irqrestore(&il->sta_lock, flags);
3144
3145 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3146}
3147
e7392364 3148int
83007196
SG		 3149il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3150 u8 sta_id)
eb3cdfb7
SG		 3151{
3152 int ret;
3153
3154 lockdep_assert_held(&il->mutex);
3155
d735f921 3156 il->_4965.key_mapping_keys++;
eb3cdfb7
SG		 3157 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3158
3159 switch (keyconf->cipher) {
3160 case WLAN_CIPHER_SUITE_CCMP:
e7392364 3161 ret =
83007196 3162 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3163 break;
3164 case WLAN_CIPHER_SUITE_TKIP:
e7392364 3165 ret =
83007196 3166 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3167 break;
3168 case WLAN_CIPHER_SUITE_WEP40:
3169 case WLAN_CIPHER_SUITE_WEP104:
83007196 3170 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3171 break;
3172 default:
e7392364
SG		 3173 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3174 keyconf->cipher);
eb3cdfb7
SG		 3175 ret = -EINVAL;
3176 }
3177
e7392364
SG		 3178 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3179 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
eb3cdfb7
SG		 3180
3181 return ret;
3182}
3183
3184/**
3185 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3186 *
3187 * This adds the broadcast station into the driver's station table
3188 * and marks it driver active, so that it will be restored to the
3189 * device at the next best time.
3190 */
e7392364 3191int
83007196 3192il4965_alloc_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3193{
3194 struct il_link_quality_cmd *link_cmd;
3195 unsigned long flags;
3196 u8 sta_id;
3197
3198 spin_lock_irqsave(&il->sta_lock, flags);
83007196 3199 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
eb3cdfb7
SG		 3200 if (sta_id == IL_INVALID_STATION) {
3201 IL_ERR("Unable to prepare broadcast station\n");
3202 spin_unlock_irqrestore(&il->sta_lock, flags);
3203
3204 return -EINVAL;
3205 }
3206
3207 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3208 il->stations[sta_id].used |= IL_STA_BCAST;
3209 spin_unlock_irqrestore(&il->sta_lock, flags);
3210
3211 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3212 if (!link_cmd) {
e7392364
SG		 3213 IL_ERR
3214 ("Unable to initialize rate scaling for bcast station.\n");
eb3cdfb7
SG		 3215 return -ENOMEM;
3216 }
3217
3218 spin_lock_irqsave(&il->sta_lock, flags);
3219 il->stations[sta_id].lq = link_cmd;
3220 spin_unlock_irqrestore(&il->sta_lock, flags);
3221
3222 return 0;
3223}
3224
3225/**
3226 * il4965_update_bcast_station - update broadcast station's LQ command
3227 *
3228 * Only used by iwl4965. Placed here to have all bcast station management
3229 * code together.
3230 */
e7392364 3231static int
83007196 3232il4965_update_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3233{
3234 unsigned long flags;
3235 struct il_link_quality_cmd *link_cmd;
b16db50a 3236 u8 sta_id = il->hw_params.bcast_id;
eb3cdfb7
SG		 3237
3238 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3239 if (!link_cmd) {
1722f8e1 3240 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
eb3cdfb7
SG		 3241 return -ENOMEM;
3242 }
3243
3244 spin_lock_irqsave(&il->sta_lock, flags);
3245 if (il->stations[sta_id].lq)
3246 kfree(il->stations[sta_id].lq);
3247 else
1722f8e1 3248 D_INFO("Bcast sta rate scaling has not been initialized.\n");
eb3cdfb7
SG		 3249 il->stations[sta_id].lq = link_cmd;
3250 spin_unlock_irqrestore(&il->sta_lock, flags);
3251
3252 return 0;
3253}
3254
e7392364
SG		 3255int
3256il4965_update_bcast_stations(struct il_priv *il)
eb3cdfb7 3257{
83007196 3258 return il4965_update_bcast_station(il);
eb3cdfb7
SG		 3259}
3260
3261/**
3262 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3263 */
e7392364
SG		 3264int
3265il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
eb3cdfb7
SG		 3266{
3267 unsigned long flags;
3268 struct il_addsta_cmd sta_cmd;
3269
3270 lockdep_assert_held(&il->mutex);
3271
3272 /* Remove "disable" flag, to enable Tx for this TID */
3273 spin_lock_irqsave(&il->sta_lock, flags);
3274 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3275 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3276 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3277 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3278 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3279 spin_unlock_irqrestore(&il->sta_lock, flags);
3280
3281 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3282}
3283
e7392364
SG		 3284int
3285il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3286 u16 ssn)
eb3cdfb7
SG		 3287{
3288 unsigned long flags;
3289 int sta_id;
3290 struct il_addsta_cmd sta_cmd;
3291
3292 lockdep_assert_held(&il->mutex);
3293
3294 sta_id = il_sta_id(sta);
3295 if (sta_id == IL_INVALID_STATION)
3296 return -ENXIO;
3297
3298 spin_lock_irqsave(&il->sta_lock, flags);
3299 il->stations[sta_id].sta.station_flags_msk = 0;
3300 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
e7392364 3301 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3302 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3303 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3304 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3305 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3306 spin_unlock_irqrestore(&il->sta_lock, flags);
3307
3308 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3309}
3310
e7392364
SG		 3311int
3312il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
eb3cdfb7
SG		 3313{
3314 unsigned long flags;
3315 int sta_id;
3316 struct il_addsta_cmd sta_cmd;
3317
3318 lockdep_assert_held(&il->mutex);
3319
3320 sta_id = il_sta_id(sta);
3321 if (sta_id == IL_INVALID_STATION) {
3322 IL_ERR("Invalid station for AGG tid %d\n", tid);
3323 return -ENXIO;
3324 }
3325
3326 spin_lock_irqsave(&il->sta_lock, flags);
3327 il->stations[sta_id].sta.station_flags_msk = 0;
3328 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
e7392364 3329 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3330 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3331 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3332 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3333 spin_unlock_irqrestore(&il->sta_lock, flags);
3334
3335 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3336}
3337
3338void
3339il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3340{
3341 unsigned long flags;
3342
3343 spin_lock_irqsave(&il->sta_lock, flags);
3344 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3345 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3346 il->stations[sta_id].sta.sta.modify_mask =
e7392364 3347 STA_MODIFY_SLEEP_TX_COUNT_MSK;
eb3cdfb7
SG		 3348 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3349 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364 3350 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
eb3cdfb7
SG		 3351 spin_unlock_irqrestore(&il->sta_lock, flags);
3352
3353}
3354
e7392364
SG		 3355void
3356il4965_update_chain_flags(struct il_priv *il)
be663ab6 3357{
c39ae9fd
SG		 3358 if (il->ops->hcmd->set_rxon_chain) {
3359 il->ops->hcmd->set_rxon_chain(il);
c8b03958 3360 if (il->active.rx_chain != il->staging.rx_chain)
83007196 3361 il_commit_rxon(il);
be663ab6
WYG		 3362 }
3363}
3364
e7392364
SG		 3365static void
3366il4965_clear_free_frames(struct il_priv *il)
be663ab6
WYG		 3367{
3368 struct list_head *element;
3369
e7392364 3370 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
be663ab6 3371
46bc8d4b
SG		 3372 while (!list_empty(&il->free_frames)) {
3373 element = il->free_frames.next;
be663ab6 3374 list_del(element);
e2ebc833 3375 kfree(list_entry(element, struct il_frame, list));
46bc8d4b 3376 il->frames_count--;
be663ab6
WYG		 3377 }
3378
46bc8d4b 3379 if (il->frames_count) {
9406f797 3380 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 3381 il->frames_count);
46bc8d4b 3382 il->frames_count = 0;
be663ab6
WYG		 3383 }
3384}
3385
e7392364
SG		 3386static struct il_frame *
3387il4965_get_free_frame(struct il_priv *il)
be663ab6 3388{
e2ebc833 3389 struct il_frame *frame;
be663ab6 3390 struct list_head *element;
46bc8d4b 3391 if (list_empty(&il->free_frames)) {
be663ab6
WYG		 3392 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3393 if (!frame) {
9406f797 3394 IL_ERR("Could not allocate frame!\n");
be663ab6
WYG		 3395 return NULL;
3396 }
3397
46bc8d4b 3398 il->frames_count++;
be663ab6
WYG		 3399 return frame;
3400 }
3401
46bc8d4b 3402 element = il->free_frames.next;
be663ab6 3403 list_del(element);
e2ebc833 3404 return list_entry(element, struct il_frame, list);
be663ab6
WYG		 3405}
3406
e7392364
SG		 3407static void
3408il4965_free_frame(struct il_priv *il, struct il_frame *frame)
be663ab6
WYG		 3409{
3410 memset(frame, 0, sizeof(*frame));
46bc8d4b 3411 list_add(&frame->list, &il->free_frames);
be663ab6
WYG		 3412}
3413
e7392364
SG		 3414static u32
3415il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3416 int left)
be663ab6 3417{
46bc8d4b 3418 lockdep_assert_held(&il->mutex);
be663ab6 3419
46bc8d4b 3420 if (!il->beacon_skb)
be663ab6
WYG		 3421 return 0;
3422
46bc8d4b 3423 if (il->beacon_skb->len > left)
be663ab6
WYG		 3424 return 0;
3425
46bc8d4b 3426 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
be663ab6 3427
46bc8d4b 3428 return il->beacon_skb->len;
be663ab6
WYG		 3429}
3430
3431/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
e7392364
SG		 3432static void
3433il4965_set_beacon_tim(struct il_priv *il,
3434 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3435 u32 frame_size)
be663ab6
WYG		 3436{
3437 u16 tim_idx;
3438 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3439
3440 /*
0c2c8852 3441 * The idx is relative to frame start but we start looking at the
be663ab6
WYG		 3442 * variable-length part of the beacon.
3443 */
3444 tim_idx = mgmt->u.beacon.variable - beacon;
3445
3446 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3447 while ((tim_idx < (frame_size - 2)) &&
e7392364
SG		 3448 (beacon[tim_idx] != WLAN_EID_TIM))
3449 tim_idx += beacon[tim_idx + 1] + 2;
be663ab6
WYG		 3450
3451 /* If TIM field was found, set variables */
3452 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3453 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
e7392364 3454 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
be663ab6 3455 } else
9406f797 3456 IL_WARN("Unable to find TIM Element in beacon\n");
be663ab6
WYG		 3457}
3458
e7392364
SG		 3459static unsigned int
3460il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
be663ab6 3461{
e2ebc833 3462 struct il_tx_beacon_cmd *tx_beacon_cmd;
be663ab6
WYG		 3463 u32 frame_size;
3464 u32 rate_flags;
3465 u32 rate;
3466 /*
3467 * We have to set up the TX command, the TX Beacon command, and the
3468 * beacon contents.
3469 */
3470
46bc8d4b 3471 lockdep_assert_held(&il->mutex);
be663ab6 3472
83007196
SG		 3473 if (!il->beacon_enabled) {
3474 IL_ERR("Trying to build beacon without beaconing enabled\n");
be663ab6
WYG		 3475 return 0;
3476 }
3477
3478 /* Initialize memory */
3479 tx_beacon_cmd = &frame->u.beacon;
3480 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3481
3482 /* Set up TX beacon contents */
e7392364
SG		 3483 frame_size =
3484 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3485 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
be663ab6
WYG		 3486 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3487 return 0;
3488 if (!frame_size)
3489 return 0;
3490
3491 /* Set up TX command fields */
e7392364 3492 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
b16db50a 3493 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
be663ab6 3494 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e7392364
SG		 3495 tx_beacon_cmd->tx.tx_flags =
3496 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3497 TX_CMD_FLG_STA_RATE_MSK;
be663ab6
WYG		 3498
3499 /* Set up TX beacon command fields */
e7392364
SG		 3500 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3501 frame_size);
be663ab6
WYG		 3502
3503 /* Set up packet rate and flags */
83007196 3504 rate = il_get_lowest_plcp(il);
a0c1ef3b 3505 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 3506 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
e2ebc833 3507 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
be663ab6 3508 rate_flags |= RATE_MCS_CCK_MSK;
616107ed 3509 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
be663ab6
WYG		 3510
3511 return sizeof(*tx_beacon_cmd) + frame_size;
3512}
3513
e7392364
SG		 3514int
3515il4965_send_beacon_cmd(struct il_priv *il)
be663ab6 3516{
e2ebc833 3517 struct il_frame *frame;
be663ab6
WYG		 3518 unsigned int frame_size;
3519 int rc;
3520
46bc8d4b 3521 frame = il4965_get_free_frame(il);
be663ab6 3522 if (!frame) {
9406f797 3523 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 3524 "command.\n");
be663ab6
WYG		 3525 return -ENOMEM;
3526 }
3527
46bc8d4b 3528 frame_size = il4965_hw_get_beacon_cmd(il, frame);
be663ab6 3529 if (!frame_size) {
9406f797 3530 IL_ERR("Error configuring the beacon command\n");
46bc8d4b 3531 il4965_free_frame(il, frame);
be663ab6
WYG		 3532 return -EINVAL;
3533 }
3534
e7392364 3535 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
be663ab6 3536
46bc8d4b 3537 il4965_free_frame(il, frame);
be663ab6
WYG		 3538
3539 return rc;
3540}
3541
e7392364
SG		 3542static inline dma_addr_t
3543il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
be663ab6 3544{
e2ebc833 3545 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3546
3547 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3548 if (sizeof(dma_addr_t) > sizeof(u32))
3549 addr |=
e7392364
SG		 3550 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3551 16;
be663ab6
WYG		 3552
3553 return addr;
3554}
3555
e7392364
SG		 3556static inline u16
3557il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
be663ab6 3558{
e2ebc833 3559 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3560
3561 return le16_to_cpu(tb->hi_n_len) >> 4;
3562}
3563
e7392364
SG		 3564static inline void
3565il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
be663ab6 3566{
e2ebc833 3567 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3568 u16 hi_n_len = len << 4;
3569
3570 put_unaligned_le32(addr, &tb->lo);
3571 if (sizeof(dma_addr_t) > sizeof(u32))
3572 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3573
3574 tb->hi_n_len = cpu_to_le16(hi_n_len);
3575
3576 tfd->num_tbs = idx + 1;
3577}
3578
e7392364
SG		 3579static inline u8
3580il4965_tfd_get_num_tbs(struct il_tfd *tfd)
be663ab6
WYG		 3581{
3582 return tfd->num_tbs & 0x1f;
3583}
3584
3585/**
e2ebc833 3586 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
46bc8d4b 3587 * @il - driver ilate data
be663ab6
WYG		 3588 * @txq - tx queue
3589 *
0c2c8852 3590 * Does NOT advance any TFD circular buffer read/write idxes
be663ab6
WYG		 3591 * Does NOT free the TFD itself (which is within circular buffer)
3592 */
e7392364
SG		 3593void
3594il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
be663ab6 3595{
e2ebc833
SG		 3596 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3597 struct il_tfd *tfd;
46bc8d4b 3598 struct pci_dev *dev = il->pci_dev;
0c2c8852 3599 int idx = txq->q.read_ptr;
be663ab6
WYG		 3600 int i;
3601 int num_tbs;
3602
0c2c8852 3603 tfd = &tfd_tmp[idx];
be663ab6
WYG		 3604
3605 /* Sanity check on number of chunks */
e2ebc833 3606 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6 3607
e2ebc833 3608 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3609 IL_ERR("Too many chunks: %i\n", num_tbs);
be663ab6
WYG		 3610 /* @todo issue fatal error, it is quite serious situation */
3611 return;
3612 }
3613
3614 /* Unmap tx_cmd */
3615 if (num_tbs)
e7392364
SG		 3616 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3617 dma_unmap_len(&txq->meta[idx], len),
3618 PCI_DMA_BIDIRECTIONAL);
be663ab6
WYG		 3619
3620 /* Unmap chunks, if any. */
3621 for (i = 1; i < num_tbs; i++)
e2ebc833 3622 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
e7392364
SG		 3623 il4965_tfd_tb_get_len(tfd, i),
3624 PCI_DMA_TODEVICE);
be663ab6
WYG		 3625
3626 /* free SKB */
3627 if (txq->txb) {
3628 struct sk_buff *skb;
3629
3630 skb = txq->txb[txq->q.read_ptr].skb;
3631
3632 /* can be called from irqs-disabled context */
3633 if (skb) {
3634 dev_kfree_skb_any(skb);
3635 txq->txb[txq->q.read_ptr].skb = NULL;
3636 }
3637 }
3638}
3639
e7392364
SG		 3640int
3641il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3642 dma_addr_t addr, u16 len, u8 reset, u8 pad)
be663ab6 3643{
e2ebc833
SG		 3644 struct il_queue *q;
3645 struct il_tfd *tfd, *tfd_tmp;
be663ab6
WYG		 3646 u32 num_tbs;
3647
3648 q = &txq->q;
e2ebc833 3649 tfd_tmp = (struct il_tfd *)txq->tfds;
be663ab6
WYG		 3650 tfd = &tfd_tmp[q->write_ptr];
3651
3652 if (reset)
3653 memset(tfd, 0, sizeof(*tfd));
3654
e2ebc833 3655 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6
WYG		 3656
3657 /* Each TFD can point to a maximum 20 Tx buffers */
e2ebc833 3658 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3659 IL_ERR("Error can not send more than %d chunks\n",
e7392364 3660 IL_NUM_OF_TBS);
be663ab6
WYG		 3661 return -EINVAL;
3662 }
3663
3664 BUG_ON(addr & ~DMA_BIT_MASK(36));
e2ebc833 3665 if (unlikely(addr & ~IL_TX_DMA_MASK))
e7392364 3666 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
be663ab6 3667
e2ebc833 3668 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
be663ab6
WYG		 3669
3670 return 0;
3671}
3672
3673/*
3674 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3675 * given Tx queue, and enable the DMA channel used for that queue.
3676 *
3677 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3678 * channels supported in hardware.
3679 */
e7392364
SG		 3680int
3681il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
be663ab6
WYG		 3682{
3683 int txq_id = txq->q.id;
3684
3685 /* Circular buffer (TFD queue in DRAM) physical base address */
e7392364 3686 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
be663ab6
WYG		 3687
3688 return 0;
3689}
3690
3691/******************************************************************************
3692 *
3693 * Generic RX handler implementations
3694 *
3695 ******************************************************************************/
e7392364
SG		 3696static void
3697il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 3698{
dcae1c64 3699 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 3700 struct il_alive_resp *palive;
be663ab6
WYG		 3701 struct delayed_work *pwork;
3702
3703 palive = &pkt->u.alive_frame;
3704
e7392364
SG		 3705 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
3706 palive->is_valid, palive->ver_type, palive->ver_subtype);
be663ab6
WYG		 3707
3708 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 3709 D_INFO("Initialization Alive received.\n");
e7392364 3710 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 3711 sizeof(struct il_init_alive_resp));
46bc8d4b 3712 pwork = &il->init_alive_start;
be663ab6 3713 } else {
58de00a4 3714 D_INFO("Runtime Alive received.\n");
46bc8d4b 3715 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 3716 sizeof(struct il_alive_resp));
46bc8d4b 3717 pwork = &il->alive_start;
be663ab6
WYG		 3718 }
3719
3720 /* We delay the ALIVE response by 5ms to
3721 * give the HW RF Kill time to activate... */
3722 if (palive->is_valid == UCODE_VALID_OK)
e7392364 3723 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
be663ab6 3724 else
9406f797 3725 IL_WARN("uCode did not respond OK.\n");
be663ab6
WYG		 3726}
3727
3728/**
ebf0d90d 3729 * il4965_bg_stats_periodic - Timer callback to queue stats
be663ab6 3730 *
ebf0d90d 3731 * This callback is provided in order to send a stats request.
be663ab6
WYG		 3732 *
3733 * This timer function is continually reset to execute within
4d69c752 3734 * REG_RECALIB_PERIOD seconds since the last N_STATS
ebf0d90d 3735 * was received. We need to ensure we receive the stats in order
be663ab6
WYG		 3736 * to update the temperature used for calibrating the TXPOWER.
3737 */
e7392364
SG		 3738static void
3739il4965_bg_stats_periodic(unsigned long data)
be663ab6 3740{
46bc8d4b 3741 struct il_priv *il = (struct il_priv *)data;
be663ab6 3742
a6766ccd 3743 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 3744 return;
3745
3746 /* dont send host command if rf-kill is on */
46bc8d4b 3747 if (!il_is_ready_rf(il))
be663ab6
WYG		 3748 return;
3749
ebf0d90d 3750 il_send_stats_request(il, CMD_ASYNC, false);
be663ab6
WYG		 3751}
3752
e7392364
SG		 3753static void
3754il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 3755{
dcae1c64 3756 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 3757 struct il4965_beacon_notif *beacon =
e7392364 3758 (struct il4965_beacon_notif *)pkt->u.raw;
d3175167 3759#ifdef CONFIG_IWLEGACY_DEBUG
e2ebc833 3760 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
be663ab6 3761
5bf0dac4 3762 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
e7392364
SG		 3763 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
3764 beacon->beacon_notify_hdr.failure_frame,
3765 le32_to_cpu(beacon->ibss_mgr_status),
3766 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
be663ab6 3767#endif
46bc8d4b 3768 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
be663ab6
WYG		 3769}
3770
e7392364
SG		 3771static void
3772il4965_perform_ct_kill_task(struct il_priv *il)
be663ab6
WYG		 3773{
3774 unsigned long flags;
3775
58de00a4 3776 D_POWER("Stop all queues\n");
be663ab6 3777
46bc8d4b
SG		 3778 if (il->mac80211_registered)
3779 ieee80211_stop_queues(il->hw);
be663ab6 3780
841b2cca 3781 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 3782 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
841b2cca 3783 _il_rd(il, CSR_UCODE_DRV_GP1);
be663ab6 3784
46bc8d4b 3785 spin_lock_irqsave(&il->reg_lock, flags);
13882269
SG		 3786 if (!_il_grab_nic_access(il))
3787 _il_release_nic_access(il);
46bc8d4b 3788 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6
WYG		 3789}
3790
3791/* Handle notification from uCode that card's power state is changing
3792 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG		 3793static void
3794il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 3795{
dcae1c64 3796 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 3797 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 3798 unsigned long status = il->status;
be663ab6 3799
58de00a4 3800 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
e7392364
SG		 3801 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3802 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
3803 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
be663ab6 3804
e7392364 3805 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
be663ab6 3806
841b2cca 3807 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 3808 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6 3809
e7392364 3810 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 3811
3812 if (!(flags & RXON_CARD_DISABLED)) {
841b2cca 3813 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 3814 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0c1a94e2 3815 il_wr(il, HBUS_TARG_MBX_C,
e7392364 3816 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 3817 }
3818 }
3819
3820 if (flags & CT_CARD_DISABLED)
46bc8d4b 3821 il4965_perform_ct_kill_task(il);
be663ab6
WYG		 3822
3823 if (flags & HW_CARD_DISABLED)
a6766ccd 3824 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 3825 else
a6766ccd 3826 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 3827
3828 if (!(flags & RXON_CARD_DISABLED))
46bc8d4b 3829 il_scan_cancel(il);
be663ab6 3830
a6766ccd
SG		 3831 if ((test_bit(S_RF_KILL_HW, &status) !=
3832 test_bit(S_RF_KILL_HW, &il->status)))
46bc8d4b 3833 wiphy_rfkill_set_hw_state(il->hw->wiphy,
e7392364 3834 test_bit(S_RF_KILL_HW, &il->status));
be663ab6 3835 else
46bc8d4b 3836 wake_up(&il->wait_command_queue);
be663ab6
WYG		 3837}
3838
3839/**
d0c72347 3840 * il4965_setup_handlers - Initialize Rx handler callbacks
be663ab6
WYG		 3841 *
3842 * Setup the RX handlers for each of the reply types sent from the uCode
3843 * to the host.
3844 *
3845 * This function chains into the hardware specific files for them to setup
3846 * any hardware specific handlers as well.
3847 */
e7392364
SG		 3848static void
3849il4965_setup_handlers(struct il_priv *il)
be663ab6 3850{
6e9848b4
SG		 3851 il->handlers[N_ALIVE] = il4965_hdl_alive;
3852 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 3853 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 3854 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 3855 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 3856 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 3857 il->handlers[N_BEACON] = il4965_hdl_beacon;
be663ab6
WYG		 3858
3859 /*
3860 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG		 3861 * stats request from the host as well as for the periodic
3862 * stats notifications (after received beacons) from the uCode.
be663ab6 3863 */
d2dfb33e
SG		 3864 il->handlers[C_STATS] = il4965_hdl_c_stats;
3865 il->handlers[N_STATS] = il4965_hdl_stats;
be663ab6 3866
46bc8d4b 3867 il_setup_rx_scan_handlers(il);
be663ab6
WYG		 3868
3869 /* status change handler */
e7392364 3870 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
be663ab6 3871
e7392364 3872 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
be663ab6 3873 /* Rx handlers */
6e9848b4
SG		 3874 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
3875 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
be663ab6 3876 /* block ack */
6e9848b4 3877 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
be663ab6 3878 /* Set up hardware specific Rx handlers */
c39ae9fd 3879 il->ops->lib->handler_setup(il);
be663ab6
WYG		 3880}
3881
3882/**
e2ebc833 3883 * il4965_rx_handle - Main entry function for receiving responses from uCode
be663ab6 3884 *
d0c72347 3885 * Uses the il->handlers callback function array to invoke
be663ab6
WYG		 3886 * the appropriate handlers, including command responses,
3887 * frame-received notifications, and other notifications.
3888 */
e7392364
SG		 3889void
3890il4965_rx_handle(struct il_priv *il)
be663ab6 3891{
b73bb5f1 3892 struct il_rx_buf *rxb;
dcae1c64 3893 struct il_rx_pkt *pkt;
46bc8d4b 3894 struct il_rx_queue *rxq = &il->rxq;
be663ab6
WYG		 3895 u32 r, i;
3896 int reclaim;
3897 unsigned long flags;
3898 u8 fill_rx = 0;
3899 u32 count = 8;
3900 int total_empty;
3901
0c2c8852 3902 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
be663ab6 3903 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 3904 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
be663ab6
WYG		 3905 i = rxq->read;
3906
3907 /* Rx interrupt, but nothing sent from uCode */
3908 if (i == r)
58de00a4 3909 D_RX("r = %d, i = %d\n", r, i);
be663ab6
WYG		 3910
3911 /* calculate total frames need to be restock after handling RX */
3912 total_empty = r - rxq->write_actual;
3913 if (total_empty < 0)
3914 total_empty += RX_QUEUE_SIZE;
3915
3916 if (total_empty > (RX_QUEUE_SIZE / 2))
3917 fill_rx = 1;
3918
3919 while (i != r) {
3920 int len;
3921
3922 rxb = rxq->queue[i];
3923
3924 /* If an RXB doesn't have a Rx queue slot associated with it,
3925 * then a bug has been introduced in the queue refilling
3926 * routines -- catch it here */
3927 BUG_ON(rxb == NULL);
3928
3929 rxq->queue[i] = NULL;
3930
46bc8d4b
SG		 3931 pci_unmap_page(il->pci_dev, rxb->page_dma,
3932 PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 3933 PCI_DMA_FROMDEVICE);
3934 pkt = rxb_addr(rxb);
3935
e94a4099 3936 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 3937 len += sizeof(u32); /* account for status word */
be663ab6
WYG		 3938
3939 /* Reclaim a command buffer only if this packet is a response
3940 * to a (driver-originated) command.
3941 * If the packet (e.g. Rx frame) originated from uCode,
3942 * there is no command buffer to reclaim.
3943 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3944 * but apparently a few don't get set; catch them here. */
3945 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364
SG		 3946 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
3947 (pkt->hdr.cmd != N_RX_MPDU) &&
3948 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
3949 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
be663ab6
WYG		 3950
3951 /* Based on type of command response or notification,
3952 * handle those that need handling via function in
d0c72347
SG		 3953 * handlers table. See il4965_setup_handlers() */
3954 if (il->handlers[pkt->hdr.cmd]) {
e7392364
SG		 3955 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
3956 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG		 3957 il->isr_stats.handlers[pkt->hdr.cmd]++;
3958 il->handlers[pkt->hdr.cmd] (il, rxb);
be663ab6
WYG		 3959 } else {
3960 /* No handling needed */
e7392364
SG		 3961 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
3962 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
be663ab6
WYG		 3963 }
3964
3965 /*
3966 * XXX: After here, we should always check rxb->page
3967 * against NULL before touching it or its virtual
d0c72347 3968 * memory (pkt). Because some handler might have
be663ab6
WYG		 3969 * already taken or freed the pages.
3970 */
3971
3972 if (reclaim) {
3973 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 3974 * and fire off the (possibly) blocking il_send_cmd()
be663ab6
WYG		 3975 * as we reclaim the driver command queue */
3976 if (rxb->page)
46bc8d4b 3977 il_tx_cmd_complete(il, rxb);
be663ab6 3978 else
9406f797 3979 IL_WARN("Claim null rxb?\n");
be663ab6
WYG		 3980 }
3981
3982 /* Reuse the page if possible. For notification packets and
3983 * SKBs that fail to Rx correctly, add them back into the
3984 * rx_free list for reuse later. */
3985 spin_lock_irqsave(&rxq->lock, flags);
3986 if (rxb->page != NULL) {
e7392364
SG		 3987 rxb->page_dma =
3988 pci_map_page(il->pci_dev, rxb->page, 0,
3989 PAGE_SIZE << il->hw_params.
3990 rx_page_order, PCI_DMA_FROMDEVICE);
be663ab6
WYG		 3991 list_add_tail(&rxb->list, &rxq->rx_free);
3992 rxq->free_count++;
3993 } else
3994 list_add_tail(&rxb->list, &rxq->rx_used);
3995
3996 spin_unlock_irqrestore(&rxq->lock, flags);
3997
3998 i = (i + 1) & RX_QUEUE_MASK;
3999 /* If there are a lot of unused frames,
4000 * restock the Rx queue so ucode wont assert. */
4001 if (fill_rx) {
4002 count++;
4003 if (count >= 8) {
4004 rxq->read = i;
46bc8d4b 4005 il4965_rx_replenish_now(il);
be663ab6
WYG		 4006 count = 0;
4007 }
4008 }
4009 }
4010
4011 /* Backtrack one entry */
4012 rxq->read = i;
4013 if (fill_rx)
46bc8d4b 4014 il4965_rx_replenish_now(il);
be663ab6 4015 else
46bc8d4b 4016 il4965_rx_queue_restock(il);
be663ab6
WYG		 4017}
4018
4019/* call this function to flush any scheduled tasklet */
e7392364
SG		 4020static inline void
4021il4965_synchronize_irq(struct il_priv *il)
be663ab6 4022{
e7392364 4023 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG		 4024 synchronize_irq(il->pci_dev->irq);
4025 tasklet_kill(&il->irq_tasklet);
be663ab6
WYG		 4026}
4027
e7392364
SG		 4028static void
4029il4965_irq_tasklet(struct il_priv *il)
be663ab6
WYG		 4030{
4031 u32 inta, handled = 0;
4032 u32 inta_fh;
4033 unsigned long flags;
4034 u32 i;
d3175167 4035#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4036 u32 inta_mask;
4037#endif
4038
46bc8d4b 4039 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4040
4041 /* Ack/clear/reset pending uCode interrupts.
4042 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4043 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG		 4044 inta = _il_rd(il, CSR_INT);
4045 _il_wr(il, CSR_INT, inta);
be663ab6
WYG		 4046
4047 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4048 * Any new interrupts that happen after this, either while we're
4049 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG		 4050 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4051 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
be663ab6 4052
d3175167 4053#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4054 if (il_get_debug_level(il) & IL_DL_ISR) {
be663ab6 4055 /* just for debug */
841b2cca 4056 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG		 4057 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4058 inta_mask, inta_fh);
be663ab6
WYG		 4059 }
4060#endif
4061
46bc8d4b 4062 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4063
4064 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4065 * atomic, make sure that inta covers all the interrupts that
4066 * we've discovered, even if FH interrupt came in just after
4067 * reading CSR_INT. */
4068 if (inta_fh & CSR49_FH_INT_RX_MASK)
4069 inta |= CSR_INT_BIT_FH_RX;
4070 if (inta_fh & CSR49_FH_INT_TX_MASK)
4071 inta |= CSR_INT_BIT_FH_TX;
4072
4073 /* Now service all interrupt bits discovered above. */
4074 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 4075 IL_ERR("Hardware error detected. Restarting.\n");
be663ab6
WYG		 4076
4077 /* Tell the device to stop sending interrupts */
46bc8d4b 4078 il_disable_interrupts(il);
be663ab6 4079
46bc8d4b
SG		 4080 il->isr_stats.hw++;
4081 il_irq_handle_error(il);
be663ab6
WYG		 4082
4083 handled |= CSR_INT_BIT_HW_ERR;
4084
4085 return;
4086 }
d3175167 4087#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4088 if (il_get_debug_level(il) & (IL_DL_ISR)) {
be663ab6
WYG		 4089 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4090 if (inta & CSR_INT_BIT_SCD) {
58de00a4 4091 D_ISR("Scheduler finished to transmit "
e7392364 4092 "the frame/frames.\n");
46bc8d4b 4093 il->isr_stats.sch++;
be663ab6
WYG		 4094 }
4095
4096 /* Alive notification via Rx interrupt will do the real work */
4097 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 4098 D_ISR("Alive interrupt\n");
46bc8d4b 4099 il->isr_stats.alive++;
be663ab6
WYG		 4100 }
4101 }
4102#endif
4103 /* Safely ignore these bits for debug checks below */
4104 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4105
4106 /* HW RF KILL switch toggled */
4107 if (inta & CSR_INT_BIT_RF_KILL) {
4108 int hw_rf_kill = 0;
e7392364
SG		 4109 if (!
4110 (_il_rd(il, CSR_GP_CNTRL) &
4111 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4112 hw_rf_kill = 1;
4113
9406f797 4114 IL_WARN("RF_KILL bit toggled to %s.\n",
e7392364 4115 hw_rf_kill ? "disable radio" : "enable radio");
be663ab6 4116
46bc8d4b 4117 il->isr_stats.rfkill++;
be663ab6
WYG		 4118
4119 /* driver only loads ucode once setting the interface up.
4120 * the driver allows loading the ucode even if the radio
4121 * is killed. Hence update the killswitch state here. The
4122 * rfkill handler will care about restarting if needed.
4123 */
a6766ccd 4124 if (!test_bit(S_ALIVE, &il->status)) {
be663ab6 4125 if (hw_rf_kill)
a6766ccd 4126 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 4127 else
a6766ccd 4128 clear_bit(S_RF_KILL_HW, &il->status);
46bc8d4b 4129 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
be663ab6
WYG		 4130 }
4131
4132 handled |= CSR_INT_BIT_RF_KILL;
4133 }
4134
4135 /* Chip got too hot and stopped itself */
4136 if (inta & CSR_INT_BIT_CT_KILL) {
9406f797 4137 IL_ERR("Microcode CT kill error detected.\n");
46bc8d4b 4138 il->isr_stats.ctkill++;
be663ab6
WYG		 4139 handled |= CSR_INT_BIT_CT_KILL;
4140 }
4141
4142 /* Error detected by uCode */
4143 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG		 4144 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4145 inta);
46bc8d4b
SG		 4146 il->isr_stats.sw++;
4147 il_irq_handle_error(il);
be663ab6
WYG		 4148 handled |= CSR_INT_BIT_SW_ERR;
4149 }
4150
4151 /*
4152 * uCode wakes up after power-down sleep.
4153 * Tell device about any new tx or host commands enqueued,
4154 * and about any Rx buffers made available while asleep.
4155 */
4156 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 4157 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG		 4158 il_rx_queue_update_write_ptr(il, &il->rxq);
4159 for (i = 0; i < il->hw_params.max_txq_num; i++)
4160 il_txq_update_write_ptr(il, &il->txq[i]);
4161 il->isr_stats.wakeup++;
be663ab6
WYG		 4162 handled |= CSR_INT_BIT_WAKEUP;
4163 }
4164
4165 /* All uCode command responses, including Tx command responses,
4166 * Rx "responses" (frame-received notification), and other
4167 * notifications from uCode come through here*/
4168 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG		 4169 il4965_rx_handle(il);
4170 il->isr_stats.rx++;
be663ab6
WYG		 4171 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4172 }
4173
4174 /* This "Tx" DMA channel is used only for loading uCode */
4175 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 4176 D_ISR("uCode load interrupt\n");
46bc8d4b 4177 il->isr_stats.tx++;
be663ab6
WYG		 4178 handled |= CSR_INT_BIT_FH_TX;
4179 /* Wake up uCode load routine, now that load is complete */
46bc8d4b
SG		 4180 il->ucode_write_complete = 1;
4181 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4182 }
4183
4184 if (inta & ~handled) {
9406f797 4185 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 4186 il->isr_stats.unhandled++;
be663ab6
WYG		 4187 }
4188
46bc8d4b 4189 if (inta & ~(il->inta_mask)) {
9406f797 4190 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 4191 inta & ~il->inta_mask);
9a95b370 4192 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
be663ab6
WYG		 4193 }
4194
4195 /* Re-enable all interrupts */
93fd74e3 4196 /* only Re-enable if disabled by irq */
a6766ccd 4197 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 4198 il_enable_interrupts(il);
a078a1fd
SG		 4199 /* Re-enable RF_KILL if it occurred */
4200 else if (handled & CSR_INT_BIT_RF_KILL)
46bc8d4b 4201 il_enable_rfkill_int(il);
be663ab6 4202
d3175167 4203#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4204 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG		 4205 inta = _il_rd(il, CSR_INT);
4206 inta_mask = _il_rd(il, CSR_INT_MASK);
4207 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
e7392364
SG		 4208 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4209 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
be663ab6
WYG		 4210 }
4211#endif
4212}
4213
4214/*****************************************************************************
4215 *
4216 * sysfs attributes
4217 *
4218 *****************************************************************************/
4219
d3175167 4220#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4221
4222/*
4223 * The following adds a new attribute to the sysfs representation
4224 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4225 * used for controlling the debug level.
4226 *
4227 * See the level definitions in iwl for details.
4228 *
4229 * The debug_level being managed using sysfs below is a per device debug
4230 * level that is used instead of the global debug level if it (the per
4231 * device debug level) is set.
4232 */
e7392364
SG		 4233static ssize_t
4234il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4235 char *buf)
be663ab6 4236{
46bc8d4b
SG		 4237 struct il_priv *il = dev_get_drvdata(d);
4238 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
be663ab6 4239}
e7392364
SG		 4240
4241static ssize_t
4242il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4243 const char *buf, size_t count)
be663ab6 4244{
46bc8d4b 4245 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4246 unsigned long val;
4247 int ret;
4248
4249 ret = strict_strtoul(buf, 0, &val);
4250 if (ret)
9406f797 4251 IL_ERR("%s is not in hex or decimal form.\n", buf);
be663ab6 4252 else {
46bc8d4b
SG		 4253 il->debug_level = val;
4254 if (il_alloc_traffic_mem(il))
e7392364 4255 IL_ERR("Not enough memory to generate traffic log\n");
be663ab6
WYG		 4256 }
4257 return strnlen(buf, count);
4258}
4259
e7392364
SG		 4260static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4261 il4965_store_debug_level);
be663ab6 4262
d3175167 4263#endif /* CONFIG_IWLEGACY_DEBUG */
be663ab6 4264
e7392364
SG		 4265static ssize_t
4266il4965_show_temperature(struct device *d, struct device_attribute *attr,
4267 char *buf)
be663ab6 4268{
46bc8d4b 4269 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4270
46bc8d4b 4271 if (!il_is_alive(il))
be663ab6
WYG		 4272 return -EAGAIN;
4273
46bc8d4b 4274 return sprintf(buf, "%d\n", il->temperature);
be663ab6
WYG		 4275}
4276
e2ebc833 4277static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
be663ab6 4278
e7392364
SG		 4279static ssize_t
4280il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
be663ab6 4281{
46bc8d4b 4282 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4283
46bc8d4b 4284 if (!il_is_ready_rf(il))
be663ab6
WYG		 4285 return sprintf(buf, "off\n");
4286 else
46bc8d4b 4287 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
be663ab6
WYG		 4288}
4289
e7392364
SG		 4290static ssize_t
4291il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4292 const char *buf, size_t count)
be663ab6 4293{
46bc8d4b 4294 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4295 unsigned long val;
4296 int ret;
4297
4298 ret = strict_strtoul(buf, 10, &val);
4299 if (ret)
9406f797 4300 IL_INFO("%s is not in decimal form.\n", buf);
be663ab6 4301 else {
46bc8d4b 4302 ret = il_set_tx_power(il, val, false);
be663ab6 4303 if (ret)
e7392364 4304 IL_ERR("failed setting tx power (0x%d).\n", ret);
be663ab6
WYG		 4305 else
4306 ret = count;
4307 }
4308 return ret;
4309}
4310
e7392364
SG		 4311static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4312 il4965_store_tx_power);
be663ab6 4313
e2ebc833 4314static struct attribute *il_sysfs_entries[] = {
be663ab6
WYG		 4315 &dev_attr_temperature.attr,
4316 &dev_attr_tx_power.attr,
d3175167 4317#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4318 &dev_attr_debug_level.attr,
4319#endif
4320 NULL
4321};
4322
e2ebc833 4323static struct attribute_group il_attribute_group = {
be663ab6 4324 .name = NULL, /* put in device directory */
e2ebc833 4325 .attrs = il_sysfs_entries,
be663ab6
WYG		 4326};
4327
4328/******************************************************************************
4329 *
4330 * uCode download functions
4331 *
4332 ******************************************************************************/
4333
e7392364
SG		 4334static void
4335il4965_dealloc_ucode_pci(struct il_priv *il)
be663ab6 4336{
46bc8d4b
SG		 4337 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4338 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4339 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4340 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4341 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4342 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6
WYG		 4343}
4344
e7392364
SG		 4345static void
4346il4965_nic_start(struct il_priv *il)
be663ab6
WYG		 4347{
4348 /* Remove all resets to allow NIC to operate */
841b2cca 4349 _il_wr(il, CSR_RESET, 0);
be663ab6
WYG		 4350}
4351
e2ebc833 4352static void il4965_ucode_callback(const struct firmware *ucode_raw,
e7392364
SG		 4353 void *context);
4354static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
be663ab6 4355
e7392364
SG		 4356static int __must_check
4357il4965_request_firmware(struct il_priv *il, bool first)
be663ab6 4358{
46bc8d4b 4359 const char *name_pre = il->cfg->fw_name_pre;
be663ab6
WYG		 4360 char tag[8];
4361
4362 if (first) {
0c2c8852
SG		 4363 il->fw_idx = il->cfg->ucode_api_max;
4364 sprintf(tag, "%d", il->fw_idx);
be663ab6 4365 } else {
0c2c8852
SG		 4366 il->fw_idx--;
4367 sprintf(tag, "%d", il->fw_idx);
be663ab6
WYG		 4368 }
4369
0c2c8852 4370 if (il->fw_idx < il->cfg->ucode_api_min) {
9406f797 4371 IL_ERR("no suitable firmware found!\n");
be663ab6
WYG		 4372 return -ENOENT;
4373 }
4374
46bc8d4b 4375 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
be663ab6 4376
e7392364 4377 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
be663ab6 4378
46bc8d4b
SG		 4379 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4380 &il->pci_dev->dev, GFP_KERNEL, il,
e2ebc833 4381 il4965_ucode_callback);
be663ab6
WYG		 4382}
4383
e2ebc833 4384struct il4965_firmware_pieces {
be663ab6
WYG		 4385 const void *inst, *data, *init, *init_data, *boot;
4386 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4387};
4388
e7392364
SG		 4389static int
4390il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4391 struct il4965_firmware_pieces *pieces)
be663ab6 4392{
e2ebc833 4393 struct il_ucode_header *ucode = (void *)ucode_raw->data;
be663ab6
WYG		 4394 u32 api_ver, hdr_size;
4395 const u8 *src;
4396
46bc8d4b
SG		 4397 il->ucode_ver = le32_to_cpu(ucode->ver);
4398 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4399
4400 switch (api_ver) {
4401 default:
4402 case 0:
4403 case 1:
4404 case 2:
4405 hdr_size = 24;
4406 if (ucode_raw->size < hdr_size) {
9406f797 4407 IL_ERR("File size too small!\n");
be663ab6
WYG		 4408 return -EINVAL;
4409 }
4410 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4411 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4412 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
e7392364 4413 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
be663ab6
WYG		 4414 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4415 src = ucode->v1.data;
4416 break;
4417 }
4418
4419 /* Verify size of file vs. image size info in file's header */
e7392364
SG		 4420 if (ucode_raw->size !=
4421 hdr_size + pieces->inst_size + pieces->data_size +
4422 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
be663ab6 4423
e7392364
SG		 4424 IL_ERR("uCode file size %d does not match expected size\n",
4425 (int)ucode_raw->size);
be663ab6
WYG		 4426 return -EINVAL;
4427 }
4428
4429 pieces->inst = src;
4430 src += pieces->inst_size;
4431 pieces->data = src;
4432 src += pieces->data_size;
4433 pieces->init = src;
4434 src += pieces->init_size;
4435 pieces->init_data = src;
4436 src += pieces->init_data_size;
4437 pieces->boot = src;
4438 src += pieces->boot_size;
4439
4440 return 0;
4441}
4442
4443/**
e2ebc833 4444 * il4965_ucode_callback - callback when firmware was loaded
be663ab6
WYG		 4445 *
4446 * If loaded successfully, copies the firmware into buffers
4447 * for the card to fetch (via DMA).
4448 */
4449static void
e2ebc833 4450il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
be663ab6 4451{
46bc8d4b 4452 struct il_priv *il = context;
e2ebc833 4453 struct il_ucode_header *ucode;
be663ab6 4454 int err;
e2ebc833 4455 struct il4965_firmware_pieces pieces;
46bc8d4b
SG		 4456 const unsigned int api_max = il->cfg->ucode_api_max;
4457 const unsigned int api_min = il->cfg->ucode_api_min;
be663ab6
WYG		 4458 u32 api_ver;
4459
4460 u32 max_probe_length = 200;
4461 u32 standard_phy_calibration_size =
e7392364 4462 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
be663ab6
WYG		 4463
4464 memset(&pieces, 0, sizeof(pieces));
4465
4466 if (!ucode_raw) {
0c2c8852 4467 if (il->fw_idx <= il->cfg->ucode_api_max)
e7392364
SG		 4468 IL_ERR("request for firmware file '%s' failed.\n",
4469 il->firmware_name);
be663ab6
WYG		 4470 goto try_again;
4471 }
4472
e7392364
SG		 4473 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4474 ucode_raw->size);
be663ab6
WYG		 4475
4476 /* Make sure that we got at least the API version number */
4477 if (ucode_raw->size < 4) {
9406f797 4478 IL_ERR("File size way too small!\n");
be663ab6
WYG		 4479 goto try_again;
4480 }
4481
4482 /* Data from ucode file: header followed by uCode images */
e2ebc833 4483 ucode = (struct il_ucode_header *)ucode_raw->data;
be663ab6 4484
46bc8d4b 4485 err = il4965_load_firmware(il, ucode_raw, &pieces);
be663ab6
WYG		 4486
4487 if (err)
4488 goto try_again;
4489
46bc8d4b 4490 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4491
4492 /*
4493 * api_ver should match the api version forming part of the
4494 * firmware filename ... but we don't check for that and only rely
4495 * on the API version read from firmware header from here on forward
4496 */
4497 if (api_ver < api_min || api_ver > api_max) {
e7392364
SG		 4498 IL_ERR("Driver unable to support your firmware API. "
4499 "Driver supports v%u, firmware is v%u.\n", api_max,
4500 api_ver);
be663ab6
WYG		 4501 goto try_again;
4502 }
4503
4504 if (api_ver != api_max)
e7392364
SG		 4505 IL_ERR("Firmware has old API version. Expected v%u, "
4506 "got v%u. New firmware can be obtained "
4507 "from http://www.intellinuxwireless.org.\n", api_max,
4508 api_ver);
be663ab6 4509
9406f797 4510 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG		 4511 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4512 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
be663ab6 4513
e7392364
SG		 4514 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4515 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4516 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
46bc8d4b 4517 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6
WYG		 4518
4519 /*
4520 * For any of the failures below (before allocating pci memory)
4521 * we will try to load a version with a smaller API -- maybe the
4522 * user just got a corrupted version of the latest API.
4523 */
4524
e7392364
SG		 4525 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4526 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4527 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4528 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4529 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4530 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
be663ab6
WYG		 4531
4532 /* Verify that uCode images will fit in card's SRAM */
46bc8d4b 4533 if (pieces.inst_size > il->hw_params.max_inst_size) {
9406f797 4534 IL_ERR("uCode instr len %Zd too large to fit in\n",
e7392364 4535 pieces.inst_size);
be663ab6
WYG		 4536 goto try_again;
4537 }
4538
46bc8d4b 4539 if (pieces.data_size > il->hw_params.max_data_size) {
9406f797 4540 IL_ERR("uCode data len %Zd too large to fit in\n",
e7392364 4541 pieces.data_size);
be663ab6
WYG		 4542 goto try_again;
4543 }
4544
46bc8d4b 4545 if (pieces.init_size > il->hw_params.max_inst_size) {
9406f797 4546 IL_ERR("uCode init instr len %Zd too large to fit in\n",
e7392364 4547 pieces.init_size);
be663ab6
WYG		 4548 goto try_again;
4549 }
4550
46bc8d4b 4551 if (pieces.init_data_size > il->hw_params.max_data_size) {
9406f797 4552 IL_ERR("uCode init data len %Zd too large to fit in\n",
e7392364 4553 pieces.init_data_size);
be663ab6
WYG		 4554 goto try_again;
4555 }
4556
46bc8d4b 4557 if (pieces.boot_size > il->hw_params.max_bsm_size) {
9406f797 4558 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
e7392364 4559 pieces.boot_size);
be663ab6
WYG		 4560 goto try_again;
4561 }
4562
4563 /* Allocate ucode buffers for card's bus-master loading ... */
4564
4565 /* Runtime instructions and 2 copies of data:
4566 * 1) unmodified from disk
4567 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG		 4568 il->ucode_code.len = pieces.inst_size;
4569 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
be663ab6 4570
46bc8d4b
SG		 4571 il->ucode_data.len = pieces.data_size;
4572 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
be663ab6 4573
46bc8d4b
SG		 4574 il->ucode_data_backup.len = pieces.data_size;
4575 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
be663ab6 4576
46bc8d4b
SG		 4577 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4578 !il->ucode_data_backup.v_addr)
be663ab6
WYG		 4579 goto err_pci_alloc;
4580
4581 /* Initialization instructions and data */
4582 if (pieces.init_size && pieces.init_data_size) {
46bc8d4b
SG		 4583 il->ucode_init.len = pieces.init_size;
4584 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
be663ab6 4585
46bc8d4b
SG		 4586 il->ucode_init_data.len = pieces.init_data_size;
4587 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
be663ab6 4588
46bc8d4b 4589 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
be663ab6
WYG		 4590 goto err_pci_alloc;
4591 }
4592
4593 /* Bootstrap (instructions only, no data) */
4594 if (pieces.boot_size) {
46bc8d4b
SG		 4595 il->ucode_boot.len = pieces.boot_size;
4596 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6 4597
46bc8d4b 4598 if (!il->ucode_boot.v_addr)
be663ab6
WYG		 4599 goto err_pci_alloc;
4600 }
4601
4602 /* Now that we can no longer fail, copy information */
4603
46bc8d4b 4604 il->sta_key_max_num = STA_KEY_MAX_NUM;
be663ab6
WYG		 4605
4606 /* Copy images into buffers for card's bus-master reads ... */
4607
4608 /* Runtime instructions (first block of data in file) */
58de00a4 4609 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
e7392364 4610 pieces.inst_size);
46bc8d4b 4611 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
be663ab6 4612
58de00a4 4613 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 4614 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
be663ab6
WYG		 4615
4616 /*
4617 * Runtime data
e2ebc833 4618 * NOTE: Copy into backup buffer will be done in il_up()
be663ab6 4619 */
58de00a4 4620 D_INFO("Copying (but not loading) uCode data len %Zd\n",
e7392364 4621 pieces.data_size);
46bc8d4b
SG		 4622 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4623 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
be663ab6
WYG		 4624
4625 /* Initialization instructions */
4626 if (pieces.init_size) {
e7392364
SG		 4627 D_INFO("Copying (but not loading) init instr len %Zd\n",
4628 pieces.init_size);
46bc8d4b 4629 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
be663ab6
WYG		 4630 }
4631
4632 /* Initialization data */
4633 if (pieces.init_data_size) {
e7392364
SG		 4634 D_INFO("Copying (but not loading) init data len %Zd\n",
4635 pieces.init_data_size);
46bc8d4b 4636 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
be663ab6
WYG		 4637 pieces.init_data_size);
4638 }
4639
4640 /* Bootstrap instructions */
58de00a4 4641 D_INFO("Copying (but not loading) boot instr len %Zd\n",
e7392364 4642 pieces.boot_size);
46bc8d4b 4643 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
be663ab6
WYG		 4644
4645 /*
4646 * figure out the offset of chain noise reset and gain commands
4647 * base on the size of standard phy calibration commands table size
4648 */
46bc8d4b 4649 il->_4965.phy_calib_chain_noise_reset_cmd =
e7392364 4650 standard_phy_calibration_size;
46bc8d4b 4651 il->_4965.phy_calib_chain_noise_gain_cmd =
e7392364 4652 standard_phy_calibration_size + 1;
be663ab6
WYG		 4653
4654 /**************************************************
4655 * This is still part of probe() in a sense...
4656 *
4657 * 9. Setup and register with mac80211 and debugfs
4658 **************************************************/
46bc8d4b 4659 err = il4965_mac_setup_register(il, max_probe_length);
be663ab6
WYG		 4660 if (err)
4661 goto out_unbind;
4662
46bc8d4b 4663 err = il_dbgfs_register(il, DRV_NAME);
be663ab6 4664 if (err)
e7392364
SG		 4665 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4666 err);
be663ab6 4667
e7392364 4668 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
be663ab6 4669 if (err) {
9406f797 4670 IL_ERR("failed to create sysfs device attributes\n");
be663ab6
WYG		 4671 goto out_unbind;
4672 }
4673
4674 /* We have our copies now, allow OS release its copies */
4675 release_firmware(ucode_raw);
46bc8d4b 4676 complete(&il->_4965.firmware_loading_complete);
be663ab6
WYG		 4677 return;
4678
e7392364 4679try_again:
be663ab6 4680 /* try next, if any */
46bc8d4b 4681 if (il4965_request_firmware(il, false))
be663ab6
WYG		 4682 goto out_unbind;
4683 release_firmware(ucode_raw);
4684 return;
4685
e7392364 4686err_pci_alloc:
9406f797 4687 IL_ERR("failed to allocate pci memory\n");
46bc8d4b 4688 il4965_dealloc_ucode_pci(il);
e7392364 4689out_unbind:
46bc8d4b
SG		 4690 complete(&il->_4965.firmware_loading_complete);
4691 device_release_driver(&il->pci_dev->dev);
be663ab6
WYG		 4692 release_firmware(ucode_raw);
4693}
4694
e7392364 4695static const char *const desc_lookup_text[] = {
be663ab6
WYG		 4696 "OK",
4697 "FAIL",
4698 "BAD_PARAM",
4699 "BAD_CHECKSUM",
4700 "NMI_INTERRUPT_WDG",
4701 "SYSASSERT",
4702 "FATAL_ERROR",
4703 "BAD_COMMAND",
4704 "HW_ERROR_TUNE_LOCK",
4705 "HW_ERROR_TEMPERATURE",
4706 "ILLEGAL_CHAN_FREQ",
3b98c7f4 4707 "VCC_NOT_STBL",
9a95b370 4708 "FH49_ERROR",
be663ab6
WYG		 4709 "NMI_INTERRUPT_HOST",
4710 "NMI_INTERRUPT_ACTION_PT",
4711 "NMI_INTERRUPT_UNKNOWN",
4712 "UCODE_VERSION_MISMATCH",
4713 "HW_ERROR_ABS_LOCK",
4714 "HW_ERROR_CAL_LOCK_FAIL",
4715 "NMI_INTERRUPT_INST_ACTION_PT",
4716 "NMI_INTERRUPT_DATA_ACTION_PT",
4717 "NMI_TRM_HW_ER",
4718 "NMI_INTERRUPT_TRM",
861d9c3f 4719 "NMI_INTERRUPT_BREAK_POINT",
be663ab6
WYG		 4720 "DEBUG_0",
4721 "DEBUG_1",
4722 "DEBUG_2",
4723 "DEBUG_3",
4724};
4725
e7392364
SG		 4726static struct {
4727 char *name;
4728 u8 num;
4729} advanced_lookup[] = {
4730 {
4731 "NMI_INTERRUPT_WDG", 0x34}, {
4732 "SYSASSERT", 0x35}, {
4733 "UCODE_VERSION_MISMATCH", 0x37}, {
4734 "BAD_COMMAND", 0x38}, {
4735 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
4736 "FATAL_ERROR", 0x3D}, {
4737 "NMI_TRM_HW_ERR", 0x46}, {
4738 "NMI_INTERRUPT_TRM", 0x4C}, {
4739 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
4740 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
4741 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
4742 "NMI_INTERRUPT_HOST", 0x66}, {
4743 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
4744 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
4745 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
4746"ADVANCED_SYSASSERT", 0},};
4747
4748static const char *
4749il4965_desc_lookup(u32 num)
be663ab6
WYG		 4750{
4751 int i;
4752 int max = ARRAY_SIZE(desc_lookup_text);
4753
4754 if (num < max)
4755 return desc_lookup_text[num];
4756
4757 max = ARRAY_SIZE(advanced_lookup) - 1;
4758 for (i = 0; i < max; i++) {
4759 if (advanced_lookup[i].num == num)
4760 break;
4761 }
4762 return advanced_lookup[i].name;
4763}
4764
4765#define ERROR_START_OFFSET (1 * sizeof(u32))
4766#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4767
e7392364
SG		 4768void
4769il4965_dump_nic_error_log(struct il_priv *il)
be663ab6
WYG		 4770{
4771 u32 data2, line;
4772 u32 desc, time, count, base, data1;
4773 u32 blink1, blink2, ilink1, ilink2;
4774 u32 pc, hcmd;
4775
1722f8e1 4776 if (il->ucode_type == UCODE_INIT)
46bc8d4b 4777 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
1722f8e1 4778 else
46bc8d4b 4779 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
be663ab6 4780
c39ae9fd 4781 if (!il->ops->lib->is_valid_rtc_data_addr(base)) {
e7392364
SG		 4782 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
4783 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
be663ab6
WYG		 4784 return;
4785 }
4786
46bc8d4b 4787 count = il_read_targ_mem(il, base);
be663ab6
WYG		 4788
4789 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 4790 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 4791 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
46bc8d4b
SG		 4792 }
4793
4794 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
4795 il->isr_stats.err_code = desc;
4796 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
4797 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
4798 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
4799 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
4800 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
4801 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
4802 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
4803 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
4804 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
4805 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
4806
9406f797 4807 IL_ERR("Desc Time "
e7392364 4808 "data1 data2 line\n");
9406f797 4809 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
e7392364 4810 il4965_desc_lookup(desc), desc, time, data1, data2, line);
9406f797 4811 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
e7392364
SG		 4812 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
4813 blink2, ilink1, ilink2, hcmd);
be663ab6
WYG		 4814}
4815
e7392364
SG		 4816static void
4817il4965_rf_kill_ct_config(struct il_priv *il)
be663ab6 4818{
e2ebc833 4819 struct il_ct_kill_config cmd;
be663ab6
WYG		 4820 unsigned long flags;
4821 int ret = 0;
4822
46bc8d4b 4823 spin_lock_irqsave(&il->lock, flags);
841b2cca 4824 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 4825 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
46bc8d4b 4826 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4827
4828 cmd.critical_temperature_R =
e7392364 4829 cpu_to_le32(il->hw_params.ct_kill_threshold);
be663ab6 4830
e7392364 4831 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
be663ab6 4832 if (ret)
4d69c752 4833 IL_ERR("C_CT_KILL_CONFIG failed\n");
be663ab6 4834 else
e7392364
SG		 4835 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
4836 "critical temperature is %d\n",
4837 il->hw_params.ct_kill_threshold);
be663ab6
WYG		 4838}
4839
4840static const s8 default_queue_to_tx_fifo[] = {
e2ebc833
SG		 4841 IL_TX_FIFO_VO,
4842 IL_TX_FIFO_VI,
4843 IL_TX_FIFO_BE,
4844 IL_TX_FIFO_BK,
d3175167 4845 IL49_CMD_FIFO_NUM,
e2ebc833
SG		 4846 IL_TX_FIFO_UNUSED,
4847 IL_TX_FIFO_UNUSED,
be663ab6
WYG		 4848};
4849
e53aac42
SG		 4850#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
4851
e7392364
SG		 4852static int
4853il4965_alive_notify(struct il_priv *il)
be663ab6
WYG		 4854{
4855 u32 a;
4856 unsigned long flags;
4857 int i, chan;
4858 u32 reg_val;
4859
46bc8d4b 4860 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4861
4862 /* Clear 4965's internal Tx Scheduler data base */
e7392364 4863 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
d3175167
SG		 4864 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
4865 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
46bc8d4b 4866 il_write_targ_mem(il, a, 0);
d3175167 4867 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
46bc8d4b 4868 il_write_targ_mem(il, a, 0);
e7392364
SG		 4869 for (;
4870 a <
4871 il->scd_base_addr +
4872 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
4873 a += 4)
46bc8d4b 4874 il_write_targ_mem(il, a, 0);
be663ab6
WYG		 4875
4876 /* Tel 4965 where to find Tx byte count tables */
e7392364 4877 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
be663ab6
WYG		 4878
4879 /* Enable DMA channel */
e7392364
SG		 4880 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
4881 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
4882 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
4883 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
be663ab6
WYG		 4884
4885 /* Update FH chicken bits */
9a95b370
SG		 4886 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
4887 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
e7392364 4888 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
be663ab6
WYG		 4889
4890 /* Disable chain mode for all queues */
d3175167 4891 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
be663ab6
WYG		 4892
4893 /* Initialize each Tx queue (including the command queue) */
46bc8d4b 4894 for (i = 0; i < il->hw_params.max_txq_num; i++) {
be663ab6 4895
0c2c8852 4896 /* TFD circular buffer read/write idxes */
d3175167 4897 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
0c1a94e2 4898 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
be663ab6
WYG		 4899
4900 /* Max Tx Window size for Scheduler-ACK mode */
e7392364
SG		 4901 il_write_targ_mem(il,
4902 il->scd_base_addr +
4903 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
4904 (SCD_WIN_SIZE <<
4905 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4906 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
be663ab6
WYG		 4907
4908 /* Frame limit */
e7392364
SG		 4909 il_write_targ_mem(il,
4910 il->scd_base_addr +
4911 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
4912 sizeof(u32),
4913 (SCD_FRAME_LIMIT <<
4914 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
4915 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
be663ab6
WYG		 4916
4917 }
d3175167 4918 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
e7392364 4919 (1 << il->hw_params.max_txq_num) - 1);
be663ab6
WYG		 4920
4921 /* Activate all Tx DMA/FIFO channels */
46bc8d4b 4922 il4965_txq_set_sched(il, IL_MASK(0, 6));
be663ab6 4923
46bc8d4b 4924 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
be663ab6
WYG		 4925
4926 /* make sure all queue are not stopped */
46bc8d4b 4927 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
be663ab6 4928 for (i = 0; i < 4; i++)
46bc8d4b 4929 atomic_set(&il->queue_stop_count[i], 0);
be663ab6
WYG		 4930
4931 /* reset to 0 to enable all the queue first */
46bc8d4b 4932 il->txq_ctx_active_msk = 0;
be663ab6
WYG		 4933 /* Map each Tx/cmd queue to its corresponding fifo */
4934 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
4935
4936 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
4937 int ac = default_queue_to_tx_fifo[i];
4938
46bc8d4b 4939 il_txq_ctx_activate(il, i);
be663ab6 4940
e2ebc833 4941 if (ac == IL_TX_FIFO_UNUSED)
be663ab6
WYG		 4942 continue;
4943
46bc8d4b 4944 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
be663ab6
WYG		 4945 }
4946
46bc8d4b 4947 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4948
4949 return 0;
4950}
4951
4952/**
4d69c752 4953 * il4965_alive_start - called after N_ALIVE notification received
be663ab6 4954 * from protocol/runtime uCode (initialization uCode's
e2ebc833 4955 * Alive gets handled by il_init_alive_start()).
be663ab6 4956 */
e7392364
SG		 4957static void
4958il4965_alive_start(struct il_priv *il)
be663ab6
WYG		 4959{
4960 int ret = 0;
be663ab6 4961
58de00a4 4962 D_INFO("Runtime Alive received.\n");
be663ab6 4963
46bc8d4b 4964 if (il->card_alive.is_valid != UCODE_VALID_OK) {
be663ab6
WYG		 4965 /* We had an error bringing up the hardware, so take it
4966 * all the way back down so we can try again */
58de00a4 4967 D_INFO("Alive failed.\n");
be663ab6
WYG		 4968 goto restart;
4969 }
4970
4971 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
4972 * This is a paranoid check, because we would not have gotten the
4973 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 4974 if (il4965_verify_ucode(il)) {
be663ab6
WYG		 4975 /* Runtime instruction load was bad;
4976 * take it all the way back down so we can try again */
58de00a4 4977 D_INFO("Bad runtime uCode load.\n");
be663ab6
WYG		 4978 goto restart;
4979 }
4980
46bc8d4b 4981 ret = il4965_alive_notify(il);
be663ab6 4982 if (ret) {
e7392364 4983 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
be663ab6
WYG		 4984 goto restart;
4985 }
4986
be663ab6 4987 /* After the ALIVE response, we can send host commands to the uCode */
a6766ccd 4988 set_bit(S_ALIVE, &il->status);
be663ab6
WYG		 4989
4990 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 4991 il_setup_watchdog(il);
be663ab6 4992
46bc8d4b 4993 if (il_is_rfkill(il))
be663ab6
WYG		 4994 return;
4995
46bc8d4b 4996 ieee80211_wake_queues(il->hw);
be663ab6 4997
2eb05816 4998 il->active_rate = RATES_MASK;
be663ab6 4999
c8b03958 5000 if (il_is_associated(il)) {
e2ebc833 5001 struct il_rxon_cmd *active_rxon =
c8b03958 5002 (struct il_rxon_cmd *)&il->active;
be663ab6 5003 /* apply any changes in staging */
c8b03958 5004 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5005 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5006 } else {
be663ab6 5007 /* Initialize our rx_config data */
83007196 5008 il_connection_init_rx_config(il);
be663ab6 5009
c39ae9fd
SG		 5010 if (il->ops->hcmd->set_rxon_chain)
5011 il->ops->hcmd->set_rxon_chain(il);
be663ab6
WYG		 5012 }
5013
5014 /* Configure bluetooth coexistence if enabled */
46bc8d4b 5015 il_send_bt_config(il);
be663ab6 5016
46bc8d4b 5017 il4965_reset_run_time_calib(il);
be663ab6 5018
a6766ccd 5019 set_bit(S_READY, &il->status);
be663ab6
WYG		 5020
5021 /* Configure the adapter for unassociated operation */
83007196 5022 il_commit_rxon(il);
be663ab6
WYG		 5023
5024 /* At this point, the NIC is initialized and operational */
46bc8d4b 5025 il4965_rf_kill_ct_config(il);
be663ab6 5026
58de00a4 5027 D_INFO("ALIVE processing complete.\n");
46bc8d4b 5028 wake_up(&il->wait_command_queue);
be663ab6 5029
46bc8d4b 5030 il_power_update_mode(il, true);
58de00a4 5031 D_INFO("Updated power mode\n");
be663ab6
WYG		 5032
5033 return;
5034
e7392364 5035restart:
46bc8d4b 5036 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 5037}
5038
46bc8d4b 5039static void il4965_cancel_deferred_work(struct il_priv *il);
be663ab6 5040
e7392364
SG		 5041static void
5042__il4965_down(struct il_priv *il)
be663ab6
WYG		 5043{
5044 unsigned long flags;
ab42b404 5045 int exit_pending;
be663ab6 5046
58de00a4 5047 D_INFO(DRV_NAME " is going down\n");
be663ab6 5048
46bc8d4b 5049 il_scan_cancel_timeout(il, 200);
be663ab6 5050
a6766ccd 5051 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
be663ab6 5052
a6766ccd 5053 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
be663ab6 5054 * to prevent rearm timer */
46bc8d4b 5055 del_timer_sync(&il->watchdog);
be663ab6 5056
83007196 5057 il_clear_ucode_stations(il);
d735f921
SG		 5058
5059 /* FIXME: race conditions ? */
5060 spin_lock_irq(&il->sta_lock);
5061 /*
5062 * Remove all key information that is not stored as part
5063 * of station information since mac80211 may not have had
5064 * a chance to remove all the keys. When device is
5065 * reconfigured by mac80211 after an error all keys will
5066 * be reconfigured.
5067 */
5068 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5069 il->_4965.key_mapping_keys = 0;
5070 spin_unlock_irq(&il->sta_lock);
5071
46bc8d4b
SG		 5072 il_dealloc_bcast_stations(il);
5073 il_clear_driver_stations(il);
be663ab6
WYG		 5074
5075 /* Unblock any waiting calls */
46bc8d4b 5076 wake_up_all(&il->wait_command_queue);
be663ab6
WYG		 5077
5078 /* Wipe out the EXIT_PENDING status bit if we are not actually
5079 * exiting the module */
5080 if (!exit_pending)
a6766ccd 5081 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5082
5083 /* stop and reset the on-board processor */
841b2cca 5084 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6
WYG		 5085
5086 /* tell the device to stop sending interrupts */
46bc8d4b
SG		 5087 spin_lock_irqsave(&il->lock, flags);
5088 il_disable_interrupts(il);
5089 spin_unlock_irqrestore(&il->lock, flags);
5090 il4965_synchronize_irq(il);
be663ab6 5091
46bc8d4b
SG		 5092 if (il->mac80211_registered)
5093 ieee80211_stop_queues(il->hw);
be663ab6 5094
e2ebc833 5095 /* If we have not previously called il_init() then
be663ab6 5096 * clear all bits but the RF Kill bit and return */
46bc8d4b 5097 if (!il_is_init(il)) {
e7392364
SG		 5098 il->status =
5099 test_bit(S_RF_KILL_HW,
5100 &il->
5101 status) << S_RF_KILL_HW |
5102 test_bit(S_GEO_CONFIGURED,
5103 &il->
5104 status) << S_GEO_CONFIGURED |
5105 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6
WYG		 5106 goto exit;
5107 }
5108
5109 /* ...otherwise clear out all the status bits but the RF Kill
5110 * bit and continue taking the NIC down. */
e7392364
SG		 5111 il->status &=
5112 test_bit(S_RF_KILL_HW,
5113 &il->status) << S_RF_KILL_HW | test_bit(S_GEO_CONFIGURED,
5114 &il->
5115 status) <<
5116 S_GEO_CONFIGURED | test_bit(S_FW_ERROR,
5117 &il->
5118 status) << S_FW_ERROR |
5119 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6 5120
46bc8d4b
SG		 5121 il4965_txq_ctx_stop(il);
5122 il4965_rxq_stop(il);
be663ab6
WYG		 5123
5124 /* Power-down device's busmaster DMA clocks */
db54eb57 5125 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 5126 udelay(5);
5127
5128 /* Make sure (redundant) we've released our request to stay awake */
e7392364 5129 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
be663ab6
WYG		 5130
5131 /* Stop the device, and put it in low power state */
46bc8d4b 5132 il_apm_stop(il);
be663ab6 5133
e7392364 5134exit:
46bc8d4b 5135 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
be663ab6 5136
46bc8d4b
SG		 5137 dev_kfree_skb(il->beacon_skb);
5138 il->beacon_skb = NULL;
be663ab6
WYG		 5139
5140 /* clear out any free frames */
46bc8d4b 5141 il4965_clear_free_frames(il);
be663ab6
WYG		 5142}
5143
e7392364
SG		 5144static void
5145il4965_down(struct il_priv *il)
be663ab6 5146{
46bc8d4b
SG		 5147 mutex_lock(&il->mutex);
5148 __il4965_down(il);
5149 mutex_unlock(&il->mutex);
be663ab6 5150
46bc8d4b 5151 il4965_cancel_deferred_work(il);
be663ab6
WYG		 5152}
5153
5154#define HW_READY_TIMEOUT (50)
5155
e7392364
SG		 5156static int
5157il4965_set_hw_ready(struct il_priv *il)
be663ab6
WYG		 5158{
5159 int ret = 0;
5160
46bc8d4b 5161 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 5162 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
be663ab6
WYG		 5163
5164 /* See if we got it */
e7392364
SG		 5165 ret =
5166 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5167 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5168 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, HW_READY_TIMEOUT);
be663ab6 5169 if (ret != -ETIMEDOUT)
46bc8d4b 5170 il->hw_ready = true;
be663ab6 5171 else
46bc8d4b 5172 il->hw_ready = false;
be663ab6 5173
e7392364 5174 D_INFO("hardware %s\n", (il->hw_ready == 1) ? "ready" : "not ready");
be663ab6
WYG		 5175 return ret;
5176}
5177
e7392364
SG		 5178static int
5179il4965_prepare_card_hw(struct il_priv *il)
be663ab6
WYG		 5180{
5181 int ret = 0;
5182
58de00a4 5183 D_INFO("il4965_prepare_card_hw enter\n");
be663ab6 5184
46bc8d4b
SG		 5185 ret = il4965_set_hw_ready(il);
5186 if (il->hw_ready)
be663ab6
WYG		 5187 return ret;
5188
5189 /* If HW is not ready, prepare the conditions to check again */
e7392364 5190 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
be663ab6 5191
e7392364
SG		 5192 ret =
5193 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5194 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5195 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
be663ab6
WYG		 5196
5197 /* HW should be ready by now, check again. */
5198 if (ret != -ETIMEDOUT)
46bc8d4b 5199 il4965_set_hw_ready(il);
be663ab6
WYG		 5200
5201 return ret;
5202}
5203
5204#define MAX_HW_RESTARTS 5
5205
e7392364
SG		 5206static int
5207__il4965_up(struct il_priv *il)
be663ab6 5208{
be663ab6
WYG		 5209 int i;
5210 int ret;
5211
a6766ccd 5212 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 5213 IL_WARN("Exit pending; will not bring the NIC up\n");
be663ab6
WYG		 5214 return -EIO;
5215 }
5216
46bc8d4b 5217 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 5218 IL_ERR("ucode not available for device bringup\n");
be663ab6
WYG		 5219 return -EIO;
5220 }
5221
83007196 5222 ret = il4965_alloc_bcast_station(il);
17d6e557
SG		 5223 if (ret) {
5224 il_dealloc_bcast_stations(il);
5225 return ret;
be663ab6
WYG		 5226 }
5227
46bc8d4b 5228 il4965_prepare_card_hw(il);
be663ab6 5229
46bc8d4b 5230 if (!il->hw_ready) {
9406f797 5231 IL_WARN("Exit HW not ready\n");
be663ab6
WYG		 5232 return -EIO;
5233 }
5234
5235 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 5236 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
a6766ccd 5237 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 5238 else
a6766ccd 5239 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 5240
46bc8d4b
SG		 5241 if (il_is_rfkill(il)) {
5242 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
be663ab6 5243
46bc8d4b 5244 il_enable_interrupts(il);
9406f797 5245 IL_WARN("Radio disabled by HW RF Kill switch\n");
be663ab6
WYG		 5246 return 0;
5247 }
5248
841b2cca 5249 _il_wr(il, CSR_INT, 0xFFFFFFFF);
be663ab6 5250
e2ebc833 5251 /* must be initialised before il_hw_nic_init */
46bc8d4b 5252 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
be663ab6 5253
46bc8d4b 5254 ret = il4965_hw_nic_init(il);
be663ab6 5255 if (ret) {
9406f797 5256 IL_ERR("Unable to init nic\n");
be663ab6
WYG		 5257 return ret;
5258 }
5259
5260 /* make sure rfkill handshake bits are cleared */
841b2cca 5261 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 5262 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6
WYG		 5263
5264 /* clear (again), then enable host interrupts */
841b2cca 5265 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5266 il_enable_interrupts(il);
be663ab6
WYG		 5267
5268 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG		 5269 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5270 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
be663ab6
WYG		 5271
5272 /* Copy original ucode data image from disk into backup cache.
5273 * This will be used to initialize the on-board processor's
5274 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG		 5275 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5276 il->ucode_data.len);
be663ab6
WYG		 5277
5278 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5279
5280 /* load bootstrap state machine,
5281 * load bootstrap program into processor's memory,
5282 * prepare to load the "initialize" uCode */
c39ae9fd 5283 ret = il->ops->lib->load_ucode(il);
be663ab6
WYG		 5284
5285 if (ret) {
e7392364 5286 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
be663ab6
WYG		 5287 continue;
5288 }
5289
5290 /* start card; "initialize" will load runtime ucode */
46bc8d4b 5291 il4965_nic_start(il);
be663ab6 5292
58de00a4 5293 D_INFO(DRV_NAME " is coming up\n");
be663ab6
WYG		 5294
5295 return 0;
5296 }
5297
a6766ccd 5298 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 5299 __il4965_down(il);
a6766ccd 5300 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5301
5302 /* tried to restart and config the device for as long as our
5303 * patience could withstand */
9406f797 5304 IL_ERR("Unable to initialize device after %d attempts.\n", i);
be663ab6
WYG		 5305 return -EIO;
5306}
5307
be663ab6
WYG		 5308/*****************************************************************************
5309 *
5310 * Workqueue callbacks
5311 *
5312 *****************************************************************************/
5313
e7392364
SG		 5314static void
5315il4965_bg_init_alive_start(struct work_struct *data)
be663ab6 5316{
46bc8d4b 5317 struct il_priv *il =
e2ebc833 5318 container_of(data, struct il_priv, init_alive_start.work);
be663ab6 5319
46bc8d4b 5320 mutex_lock(&il->mutex);
a6766ccd 5321 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5322 goto out;
be663ab6 5323
c39ae9fd 5324 il->ops->lib->init_alive_start(il);
28a6e577 5325out:
46bc8d4b 5326 mutex_unlock(&il->mutex);
be663ab6
WYG		 5327}
5328
e7392364
SG		 5329static void
5330il4965_bg_alive_start(struct work_struct *data)
be663ab6 5331{
46bc8d4b 5332 struct il_priv *il =
e2ebc833 5333 container_of(data, struct il_priv, alive_start.work);
be663ab6 5334
46bc8d4b 5335 mutex_lock(&il->mutex);
a6766ccd 5336 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5337 goto out;
be663ab6 5338
46bc8d4b 5339 il4965_alive_start(il);
28a6e577 5340out:
46bc8d4b 5341 mutex_unlock(&il->mutex);
be663ab6
WYG		 5342}
5343
e7392364
SG		 5344static void
5345il4965_bg_run_time_calib_work(struct work_struct *work)
be663ab6 5346{
46bc8d4b 5347 struct il_priv *il = container_of(work, struct il_priv,
e7392364 5348 run_time_calib_work);
be663ab6 5349
46bc8d4b 5350 mutex_lock(&il->mutex);
be663ab6 5351
a6766ccd
SG		 5352 if (test_bit(S_EXIT_PENDING, &il->status) ||
5353 test_bit(S_SCANNING, &il->status)) {
46bc8d4b 5354 mutex_unlock(&il->mutex);
be663ab6
WYG		 5355 return;
5356 }
5357
46bc8d4b 5358 if (il->start_calib) {
e7392364
SG		 5359 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5360 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
be663ab6
WYG		 5361 }
5362
46bc8d4b 5363 mutex_unlock(&il->mutex);
be663ab6
WYG		 5364}
5365
e7392364
SG		 5366static void
5367il4965_bg_restart(struct work_struct *data)
be663ab6 5368{
46bc8d4b 5369 struct il_priv *il = container_of(data, struct il_priv, restart);
be663ab6 5370
a6766ccd 5371 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5372 return;
5373
a6766ccd 5374 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 5375 mutex_lock(&il->mutex);
83007196
SG		 5376 /* FIXME: do we dereference vif without mutex locked ? */
5377 il->vif = NULL;
46bc8d4b 5378 il->is_open = 0;
be663ab6 5379
46bc8d4b 5380 __il4965_down(il);
be663ab6 5381
46bc8d4b
SG		 5382 mutex_unlock(&il->mutex);
5383 il4965_cancel_deferred_work(il);
5384 ieee80211_restart_hw(il->hw);
be663ab6 5385 } else {
46bc8d4b 5386 il4965_down(il);
be663ab6 5387
46bc8d4b 5388 mutex_lock(&il->mutex);
a6766ccd 5389 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 5390 mutex_unlock(&il->mutex);
be663ab6 5391 return;
28a6e577 5392 }
be663ab6 5393
46bc8d4b
SG		 5394 __il4965_up(il);
5395 mutex_unlock(&il->mutex);
be663ab6
WYG		 5396 }
5397}
5398
e7392364
SG		 5399static void
5400il4965_bg_rx_replenish(struct work_struct *data)
be663ab6 5401{
e7392364 5402 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
be663ab6 5403
a6766ccd 5404 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5405 return;
5406
46bc8d4b
SG		 5407 mutex_lock(&il->mutex);
5408 il4965_rx_replenish(il);
5409 mutex_unlock(&il->mutex);
be663ab6
WYG		 5410}
5411
5412/*****************************************************************************
5413 *
5414 * mac80211 entry point functions
5415 *
5416 *****************************************************************************/
5417
5418#define UCODE_READY_TIMEOUT (4 * HZ)
5419
5420/*
5421 * Not a mac80211 entry point function, but it fits in with all the
5422 * other mac80211 functions grouped here.
5423 */
e7392364
SG		 5424static int
5425il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
be663ab6
WYG		 5426{
5427 int ret;
46bc8d4b 5428 struct ieee80211_hw *hw = il->hw;
be663ab6
WYG		 5429
5430 hw->rate_control_algorithm = "iwl-4965-rs";
5431
5432 /* Tell mac80211 our characteristics */
e7392364
SG		 5433 hw->flags =
5434 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
5435 IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT |
5436 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
be663ab6 5437
46bc8d4b 5438 if (il->cfg->sku & IL_SKU_N)
e7392364
SG		 5439 hw->flags |=
5440 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5441 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
be663ab6 5442
e2ebc833
SG		 5443 hw->sta_data_size = sizeof(struct il_station_priv);
5444 hw->vif_data_size = sizeof(struct il_vif_priv);
be663ab6 5445
8c9c48d5
SG		 5446 hw->wiphy->interface_modes =
5447 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
be663ab6 5448
e7392364
SG		 5449 hw->wiphy->flags |=
5450 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS;
be663ab6
WYG		 5451
5452 /*
5453 * For now, disable PS by default because it affects
5454 * RX performance significantly.
5455 */
5456 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5457
5458 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5459 /* we create the 802.11 header and a zero-length SSID element */
5460 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5461
5462 /* Default value; 4 EDCA QOS priorities */
5463 hw->queues = 4;
5464
e2ebc833 5465 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
be663ab6 5466
46bc8d4b
SG		 5467 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5468 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 5469 &il->bands[IEEE80211_BAND_2GHZ];
46bc8d4b
SG		 5470 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5471 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 5472 &il->bands[IEEE80211_BAND_5GHZ];
be663ab6 5473
46bc8d4b 5474 il_leds_init(il);
be663ab6 5475
46bc8d4b 5476 ret = ieee80211_register_hw(il->hw);
be663ab6 5477 if (ret) {
9406f797 5478 IL_ERR("Failed to register hw (error %d)\n", ret);
be663ab6
WYG		 5479 return ret;
5480 }
46bc8d4b 5481 il->mac80211_registered = 1;
be663ab6
WYG		 5482
5483 return 0;
5484}
5485
e7392364
SG		 5486int
5487il4965_mac_start(struct ieee80211_hw *hw)
be663ab6 5488{
46bc8d4b 5489 struct il_priv *il = hw->priv;
be663ab6
WYG		 5490 int ret;
5491
58de00a4 5492 D_MAC80211("enter\n");
be663ab6
WYG		 5493
5494 /* we should be verifying the device is ready to be opened */
46bc8d4b
SG		 5495 mutex_lock(&il->mutex);
5496 ret = __il4965_up(il);
5497 mutex_unlock(&il->mutex);
be663ab6
WYG		 5498
5499 if (ret)
5500 return ret;
5501
46bc8d4b 5502 if (il_is_rfkill(il))
be663ab6
WYG		 5503 goto out;
5504
58de00a4 5505 D_INFO("Start UP work done.\n");
be663ab6
WYG		 5506
5507 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5508 * mac80211 will not be run successfully. */
46bc8d4b 5509 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 5510 test_bit(S_READY, &il->status),
5511 UCODE_READY_TIMEOUT);
be663ab6 5512 if (!ret) {
a6766ccd 5513 if (!test_bit(S_READY, &il->status)) {
9406f797 5514 IL_ERR("START_ALIVE timeout after %dms.\n",
be663ab6
WYG		 5515 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5516 return -ETIMEDOUT;
5517 }
5518 }
5519
46bc8d4b 5520 il4965_led_enable(il);
be663ab6
WYG		 5521
5522out:
46bc8d4b 5523 il->is_open = 1;
58de00a4 5524 D_MAC80211("leave\n");
be663ab6
WYG		 5525 return 0;
5526}
5527
e7392364
SG		 5528void
5529il4965_mac_stop(struct ieee80211_hw *hw)
be663ab6 5530{
46bc8d4b 5531 struct il_priv *il = hw->priv;
be663ab6 5532
58de00a4 5533 D_MAC80211("enter\n");
be663ab6 5534
46bc8d4b 5535 if (!il->is_open)
be663ab6
WYG		 5536 return;
5537
46bc8d4b 5538 il->is_open = 0;
be663ab6 5539
46bc8d4b 5540 il4965_down(il);
be663ab6 5541
46bc8d4b 5542 flush_workqueue(il->workqueue);
be663ab6 5543
a078a1fd
SG		 5544 /* User space software may expect getting rfkill changes
5545 * even if interface is down */
841b2cca 5546 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5547 il_enable_rfkill_int(il);
be663ab6 5548
58de00a4 5549 D_MAC80211("leave\n");
be663ab6
WYG		 5550}
5551
e7392364
SG		 5552void
5553il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
be663ab6 5554{
46bc8d4b 5555 struct il_priv *il = hw->priv;
be663ab6 5556
58de00a4 5557 D_MACDUMP("enter\n");
be663ab6 5558
58de00a4 5559 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 5560 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
be663ab6 5561
46bc8d4b 5562 if (il4965_tx_skb(il, skb))
be663ab6
WYG		 5563 dev_kfree_skb_any(skb);
5564
58de00a4 5565 D_MACDUMP("leave\n");
be663ab6
WYG		 5566}
5567
e7392364
SG		 5568void
5569il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5570 struct ieee80211_key_conf *keyconf,
5571 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
be663ab6 5572{
46bc8d4b 5573 struct il_priv *il = hw->priv;
be663ab6 5574
58de00a4 5575 D_MAC80211("enter\n");
be663ab6 5576
83007196 5577 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
be663ab6 5578
58de00a4 5579 D_MAC80211("leave\n");
be663ab6
WYG		 5580}
5581
e7392364
SG		 5582int
5583il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5584 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5585 struct ieee80211_key_conf *key)
be663ab6 5586{
46bc8d4b 5587 struct il_priv *il = hw->priv;
be663ab6
WYG		 5588 int ret;
5589 u8 sta_id;
5590 bool is_default_wep_key = false;
5591
58de00a4 5592 D_MAC80211("enter\n");
be663ab6 5593
46bc8d4b 5594 if (il->cfg->mod_params->sw_crypto) {
58de00a4 5595 D_MAC80211("leave - hwcrypto disabled\n");
be663ab6
WYG		 5596 return -EOPNOTSUPP;
5597 }
5598
83007196 5599 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 5600 if (sta_id == IL_INVALID_STATION)
be663ab6
WYG		 5601 return -EINVAL;
5602
46bc8d4b
SG		 5603 mutex_lock(&il->mutex);
5604 il_scan_cancel_timeout(il, 100);
be663ab6
WYG		 5605
5606 /*
5607 * If we are getting WEP group key and we didn't receive any key mapping
5608 * so far, we are in legacy wep mode (group key only), otherwise we are
5609 * in 1X mode.
5610 * In legacy wep mode, we use another host command to the uCode.
5611 */
5612 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
e7392364 5613 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
be663ab6 5614 if (cmd == SET_KEY)
d735f921 5615 is_default_wep_key = !il->_4965.key_mapping_keys;
be663ab6
WYG		 5616 else
5617 is_default_wep_key =
e7392364 5618 (key->hw_key_idx == HW_KEY_DEFAULT);
be663ab6
WYG		 5619 }
5620
5621 switch (cmd) {
5622 case SET_KEY:
5623 if (is_default_wep_key)
83007196 5624 ret = il4965_set_default_wep_key(il, key);
be663ab6 5625 else
83007196 5626 ret = il4965_set_dynamic_key(il, key, sta_id);
be663ab6 5627
58de00a4 5628 D_MAC80211("enable hwcrypto key\n");
be663ab6
WYG		 5629 break;
5630 case DISABLE_KEY:
5631 if (is_default_wep_key)
83007196 5632 ret = il4965_remove_default_wep_key(il, key);
be663ab6 5633 else
83007196 5634 ret = il4965_remove_dynamic_key(il, key, sta_id);
be663ab6 5635
58de00a4 5636 D_MAC80211("disable hwcrypto key\n");
be663ab6
WYG		 5637 break;
5638 default:
5639 ret = -EINVAL;
5640 }
5641
46bc8d4b 5642 mutex_unlock(&il->mutex);
58de00a4 5643 D_MAC80211("leave\n");
be663ab6
WYG		 5644
5645 return ret;
5646}
5647
e7392364
SG		 5648int
5649il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5650 enum ieee80211_ampdu_mlme_action action,
5651 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5652 u8 buf_size)
be663ab6 5653{
46bc8d4b 5654 struct il_priv *il = hw->priv;
be663ab6
WYG		 5655 int ret = -EINVAL;
5656
e7392364 5657 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
be663ab6 5658
46bc8d4b 5659 if (!(il->cfg->sku & IL_SKU_N))
be663ab6
WYG		 5660 return -EACCES;
5661
46bc8d4b 5662 mutex_lock(&il->mutex);
be663ab6
WYG		 5663
5664 switch (action) {
5665 case IEEE80211_AMPDU_RX_START:
58de00a4 5666 D_HT("start Rx\n");
46bc8d4b 5667 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
be663ab6
WYG		 5668 break;
5669 case IEEE80211_AMPDU_RX_STOP:
58de00a4 5670 D_HT("stop Rx\n");
46bc8d4b 5671 ret = il4965_sta_rx_agg_stop(il, sta, tid);
a6766ccd 5672 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5673 ret = 0;
5674 break;
5675 case IEEE80211_AMPDU_TX_START:
58de00a4 5676 D_HT("start Tx\n");
46bc8d4b 5677 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
be663ab6
WYG		 5678 break;
5679 case IEEE80211_AMPDU_TX_STOP:
58de00a4 5680 D_HT("stop Tx\n");
46bc8d4b 5681 ret = il4965_tx_agg_stop(il, vif, sta, tid);
a6766ccd 5682 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5683 ret = 0;
5684 break;
5685 case IEEE80211_AMPDU_TX_OPERATIONAL:
5686 ret = 0;
5687 break;
5688 }
46bc8d4b 5689 mutex_unlock(&il->mutex);
be663ab6
WYG		 5690
5691 return ret;
5692}
5693
e7392364
SG		 5694int
5695il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5696 struct ieee80211_sta *sta)
be663ab6 5697{
46bc8d4b 5698 struct il_priv *il = hw->priv;
e2ebc833 5699 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
be663ab6
WYG		 5700 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
5701 int ret;
5702 u8 sta_id;
5703
e7392364 5704 D_INFO("received request to add station %pM\n", sta->addr);
46bc8d4b 5705 mutex_lock(&il->mutex);
e7392364 5706 D_INFO("proceeding to add station %pM\n", sta->addr);
e2ebc833 5707 sta_priv->common.sta_id = IL_INVALID_STATION;
be663ab6
WYG		 5708
5709 atomic_set(&sta_priv->pending_frames, 0);
5710
e7392364 5711 ret =
83007196 5712 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
be663ab6 5713 if (ret) {
e7392364 5714 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
be663ab6 5715 /* Should we return success if return code is EEXIST ? */
46bc8d4b 5716 mutex_unlock(&il->mutex);
be663ab6
WYG		 5717 return ret;
5718 }
5719
5720 sta_priv->common.sta_id = sta_id;
5721
5722 /* Initialize rate scaling */
e7392364 5723 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG		 5724 il4965_rs_rate_init(il, sta, sta_id);
5725 mutex_unlock(&il->mutex);
be663ab6
WYG		 5726
5727 return 0;
5728}
5729
e7392364
SG		 5730void
5731il4965_mac_channel_switch(struct ieee80211_hw *hw,
5732 struct ieee80211_channel_switch *ch_switch)
be663ab6 5733{
46bc8d4b 5734 struct il_priv *il = hw->priv;
e2ebc833 5735 const struct il_channel_info *ch_info;
be663ab6
WYG		 5736 struct ieee80211_conf *conf = &hw->conf;
5737 struct ieee80211_channel *channel = ch_switch->channel;
46bc8d4b 5738 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6 5739 u16 ch;
be663ab6 5740
58de00a4 5741 D_MAC80211("enter\n");
be663ab6 5742
46bc8d4b 5743 mutex_lock(&il->mutex);
28a6e577 5744
46bc8d4b 5745 if (il_is_rfkill(il))
28a6e577 5746 goto out;
be663ab6 5747
a6766ccd
SG		 5748 if (test_bit(S_EXIT_PENDING, &il->status) ||
5749 test_bit(S_SCANNING, &il->status) ||
5750 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
28a6e577 5751 goto out;
be663ab6 5752
c8b03958 5753 if (!il_is_associated(il))
28a6e577 5754 goto out;
be663ab6 5755
c39ae9fd 5756 if (!il->ops->lib->set_channel_switch)
7f1f9742 5757 goto out;
be663ab6 5758
7f1f9742 5759 ch = channel->hw_value;
c8b03958 5760 if (le16_to_cpu(il->active.channel) == ch)
7f1f9742
SG		 5761 goto out;
5762
46bc8d4b 5763 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5764 if (!il_is_channel_valid(ch_info)) {
58de00a4 5765 D_MAC80211("invalid channel\n");
7f1f9742
SG		 5766 goto out;
5767 }
5768
46bc8d4b 5769 spin_lock_irq(&il->lock);
7f1f9742 5770
46bc8d4b 5771 il->current_ht_config.smps = conf->smps_mode;
7f1f9742
SG		 5772
5773 /* Configure HT40 channels */
1c03c462
SG		 5774 il->ht.enabled = conf_is_ht(conf);
5775 if (il->ht.enabled) {
7f1f9742 5776 if (conf_is_ht40_minus(conf)) {
1c03c462 5777 il->ht.extension_chan_offset =
e7392364 5778 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 5779 il->ht.is_40mhz = true;
7f1f9742 5780 } else if (conf_is_ht40_plus(conf)) {
1c03c462 5781 il->ht.extension_chan_offset =
e7392364 5782 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 5783 il->ht.is_40mhz = true;
7f1f9742 5784 } else {
1c03c462 5785 il->ht.extension_chan_offset =
e7392364 5786 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 5787 il->ht.is_40mhz = false;
be663ab6 5788 }
7f1f9742 5789 } else
1c03c462 5790 il->ht.is_40mhz = false;
7f1f9742 5791
c8b03958
SG		 5792 if ((le16_to_cpu(il->staging.channel) != ch))
5793 il->staging.flags = 0;
7f1f9742 5794
83007196 5795 il_set_rxon_channel(il, channel);
46bc8d4b 5796 il_set_rxon_ht(il, ht_conf);
83007196 5797 il_set_flags_for_band(il, channel->band, il->vif);
7f1f9742 5798
46bc8d4b 5799 spin_unlock_irq(&il->lock);
7f1f9742 5800
46bc8d4b 5801 il_set_rate(il);
7f1f9742
SG		 5802 /*
5803 * at this point, staging_rxon has the
5804 * configuration for channel switch
5805 */
a6766ccd 5806 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 5807 il->switch_channel = cpu_to_le16(ch);
c39ae9fd 5808 if (il->ops->lib->set_channel_switch(il, ch_switch)) {
a6766ccd 5809 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 5810 il->switch_channel = 0;
83007196 5811 ieee80211_chswitch_done(il->vif, false);
be663ab6 5812 }
7f1f9742 5813
be663ab6 5814out:
46bc8d4b 5815 mutex_unlock(&il->mutex);
58de00a4 5816 D_MAC80211("leave\n");
be663ab6
WYG		 5817}
5818
e7392364
SG		 5819void
5820il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
5821 unsigned int *total_flags, u64 multicast)
be663ab6 5822{
46bc8d4b 5823 struct il_priv *il = hw->priv;
be663ab6 5824 __le32 filter_or = 0, filter_nand = 0;
be663ab6
WYG		 5825
5826#define CHK(test, flag) do { \
5827 if (*total_flags & (test)) \
5828 filter_or |= (flag); \
5829 else \
5830 filter_nand |= (flag); \
5831 } while (0)
5832
e7392364
SG		 5833 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
5834 *total_flags);
be663ab6
WYG		 5835
5836 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
5837 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
5838 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
5839 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
5840
5841#undef CHK
5842
46bc8d4b 5843 mutex_lock(&il->mutex);
be663ab6 5844
c8b03958
SG		 5845 il->staging.filter_flags &= ~filter_nand;
5846 il->staging.filter_flags |= filter_or;
be663ab6 5847
17d6e557
SG		 5848 /*
5849 * Not committing directly because hardware can perform a scan,
5850 * but we'll eventually commit the filter flags change anyway.
5851 */
be663ab6 5852
46bc8d4b 5853 mutex_unlock(&il->mutex);
be663ab6
WYG		 5854
5855 /*
5856 * Receiving all multicast frames is always enabled by the
e2ebc833 5857 * default flags setup in il_connection_init_rx_config()
be663ab6
WYG		 5858 * since we currently do not support programming multicast
5859 * filters into the device.
5860 */
e7392364
SG		 5861 *total_flags &=
5862 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
5863 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
be663ab6
WYG		 5864}
5865
5866/*****************************************************************************
5867 *
5868 * driver setup and teardown
5869 *
5870 *****************************************************************************/
5871
e7392364
SG		 5872static void
5873il4965_bg_txpower_work(struct work_struct *work)
be663ab6 5874{
46bc8d4b 5875 struct il_priv *il = container_of(work, struct il_priv,
e7392364 5876 txpower_work);
be663ab6 5877
46bc8d4b 5878 mutex_lock(&il->mutex);
f325757a 5879
be663ab6 5880 /* If a scan happened to start before we got here
ebf0d90d 5881 * then just return; the stats notification will
be663ab6
WYG		 5882 * kick off another scheduled work to compensate for
5883 * any temperature delta we missed here. */
a6766ccd
SG		 5884 if (test_bit(S_EXIT_PENDING, &il->status) ||
5885 test_bit(S_SCANNING, &il->status))
f325757a 5886 goto out;
be663ab6
WYG		 5887
5888 /* Regardless of if we are associated, we must reconfigure the
5889 * TX power since frames can be sent on non-radar channels while
5890 * not associated */
c39ae9fd 5891 il->ops->lib->send_tx_power(il);
be663ab6
WYG		 5892
5893 /* Update last_temperature to keep is_calib_needed from running
5894 * when it isn't needed... */
46bc8d4b 5895 il->last_temperature = il->temperature;
f325757a 5896out:
46bc8d4b 5897 mutex_unlock(&il->mutex);
be663ab6
WYG		 5898}
5899
e7392364
SG		 5900static void
5901il4965_setup_deferred_work(struct il_priv *il)
be663ab6 5902{
46bc8d4b 5903 il->workqueue = create_singlethread_workqueue(DRV_NAME);
be663ab6 5904
46bc8d4b 5905 init_waitqueue_head(&il->wait_command_queue);
be663ab6 5906
46bc8d4b
SG		 5907 INIT_WORK(&il->restart, il4965_bg_restart);
5908 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
5909 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
5910 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
5911 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
be663ab6 5912
46bc8d4b 5913 il_setup_scan_deferred_work(il);
be663ab6 5914
46bc8d4b 5915 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
be663ab6 5916
ebf0d90d
SG		 5917 init_timer(&il->stats_periodic);
5918 il->stats_periodic.data = (unsigned long)il;
5919 il->stats_periodic.function = il4965_bg_stats_periodic;
be663ab6 5920
46bc8d4b
SG		 5921 init_timer(&il->watchdog);
5922 il->watchdog.data = (unsigned long)il;
5923 il->watchdog.function = il_bg_watchdog;
be663ab6 5924
e7392364
SG		 5925 tasklet_init(&il->irq_tasklet,
5926 (void (*)(unsigned long))il4965_irq_tasklet,
5927 (unsigned long)il);
be663ab6
WYG		 5928}
5929
e7392364
SG		 5930static void
5931il4965_cancel_deferred_work(struct il_priv *il)
be663ab6 5932{
46bc8d4b
SG		 5933 cancel_work_sync(&il->txpower_work);
5934 cancel_delayed_work_sync(&il->init_alive_start);
5935 cancel_delayed_work(&il->alive_start);
5936 cancel_work_sync(&il->run_time_calib_work);
be663ab6 5937
46bc8d4b 5938 il_cancel_scan_deferred_work(il);
be663ab6 5939
ebf0d90d 5940 del_timer_sync(&il->stats_periodic);
be663ab6
WYG		 5941}
5942
e7392364
SG		 5943static void
5944il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
be663ab6
WYG		 5945{
5946 int i;
5947
2eb05816 5948 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
d2ddf621 5949 rates[i].bitrate = il_rates[i].ieee * 5;
e7392364 5950 rates[i].hw_value = i; /* Rate scaling will work on idxes */
be663ab6
WYG		 5951 rates[i].hw_value_short = i;
5952 rates[i].flags = 0;
e2ebc833 5953 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
be663ab6
WYG		 5954 /*
5955 * If CCK != 1M then set short preamble rate flag.
5956 */
5957 rates[i].flags |=
e7392364
SG		 5958 (il_rates[i].plcp ==
5959 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
be663ab6
WYG		 5960 }
5961 }
5962}
e7392364 5963
be663ab6 5964/*
46bc8d4b 5965 * Acquire il->lock before calling this function !
be663ab6 5966 */
e7392364
SG		 5967void
5968il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
be663ab6 5969{
e7392364 5970 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
0c2c8852 5971 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
be663ab6
WYG		 5972}
5973
e7392364
SG		 5974void
5975il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
5976 int tx_fifo_id, int scd_retry)
be663ab6
WYG		 5977{
5978 int txq_id = txq->q.id;
5979
5980 /* Find out whether to activate Tx queue */
46bc8d4b 5981 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
be663ab6
WYG		 5982
5983 /* Set up and activate */
d3175167 5984 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 5985 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5986 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
5987 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
5988 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
5989 IL49_SCD_QUEUE_STTS_REG_MSK);
be663ab6
WYG		 5990
5991 txq->sched_retry = scd_retry;
5992
e7392364
SG		 5993 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
5994 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
be663ab6
WYG		 5995}
5996
c39ae9fd
SG		 5997const struct ieee80211_ops il4965_mac_ops = {
5998 .tx = il4965_mac_tx,
5999 .start = il4965_mac_start,
6000 .stop = il4965_mac_stop,
6001 .add_interface = il_mac_add_interface,
6002 .remove_interface = il_mac_remove_interface,
6003 .change_interface = il_mac_change_interface,
6004 .config = il_mac_config,
6005 .configure_filter = il4965_configure_filter,
6006 .set_key = il4965_mac_set_key,
6007 .update_tkip_key = il4965_mac_update_tkip_key,
6008 .conf_tx = il_mac_conf_tx,
6009 .reset_tsf = il_mac_reset_tsf,
6010 .bss_info_changed = il_mac_bss_info_changed,
6011 .ampdu_action = il4965_mac_ampdu_action,
6012 .hw_scan = il_mac_hw_scan,
6013 .sta_add = il4965_mac_sta_add,
6014 .sta_remove = il_mac_sta_remove,
6015 .channel_switch = il4965_mac_channel_switch,
6016 .tx_last_beacon = il_mac_tx_last_beacon,
6017};
6018
e7392364
SG		 6019static int
6020il4965_init_drv(struct il_priv *il)
be663ab6
WYG		 6021{
6022 int ret;
6023
46bc8d4b
SG		 6024 spin_lock_init(&il->sta_lock);
6025 spin_lock_init(&il->hcmd_lock);
be663ab6 6026
46bc8d4b 6027 INIT_LIST_HEAD(&il->free_frames);
be663ab6 6028
46bc8d4b 6029 mutex_init(&il->mutex);
be663ab6 6030
46bc8d4b
SG		 6031 il->ieee_channels = NULL;
6032 il->ieee_rates = NULL;
6033 il->band = IEEE80211_BAND_2GHZ;
be663ab6 6034
46bc8d4b
SG		 6035 il->iw_mode = NL80211_IFTYPE_STATION;
6036 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6037 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
be663ab6
WYG		 6038
6039 /* initialize force reset */
46bc8d4b 6040 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
be663ab6
WYG		 6041
6042 /* Choose which receivers/antennas to use */
c39ae9fd
SG		 6043 if (il->ops->hcmd->set_rxon_chain)
6044 il->ops->hcmd->set_rxon_chain(il);
be663ab6 6045
46bc8d4b 6046 il_init_scan_params(il);
be663ab6 6047
46bc8d4b 6048 ret = il_init_channel_map(il);
be663ab6 6049 if (ret) {
9406f797 6050 IL_ERR("initializing regulatory failed: %d\n", ret);
be663ab6
WYG		 6051 goto err;
6052 }
6053
46bc8d4b 6054 ret = il_init_geos(il);
be663ab6 6055 if (ret) {
9406f797 6056 IL_ERR("initializing geos failed: %d\n", ret);
be663ab6
WYG		 6057 goto err_free_channel_map;
6058 }
46bc8d4b 6059 il4965_init_hw_rates(il, il->ieee_rates);
be663ab6
WYG		 6060
6061 return 0;
6062
6063err_free_channel_map:
46bc8d4b 6064 il_free_channel_map(il);
be663ab6
WYG		 6065err:
6066 return ret;
6067}
6068
e7392364
SG		 6069static void
6070il4965_uninit_drv(struct il_priv *il)
be663ab6 6071{
46bc8d4b
SG		 6072 il4965_calib_free_results(il);
6073 il_free_geos(il);
6074 il_free_channel_map(il);
6075 kfree(il->scan_cmd);
be663ab6
WYG		 6076}
6077
e7392364
SG		 6078static void
6079il4965_hw_detect(struct il_priv *il)
be663ab6 6080{
841b2cca
SG		 6081 il->hw_rev = _il_rd(il, CSR_HW_REV);
6082 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
46bc8d4b 6083 il->rev_id = il->pci_dev->revision;
58de00a4 6084 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
be663ab6
WYG		 6085}
6086
e7392364
SG		 6087static int
6088il4965_set_hw_params(struct il_priv *il)
be663ab6 6089{
b16db50a 6090 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
46bc8d4b
SG		 6091 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6092 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6093 if (il->cfg->mod_params->amsdu_size_8K)
6094 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
be663ab6 6095 else
46bc8d4b 6096 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
be663ab6 6097
46bc8d4b 6098 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
be663ab6 6099
46bc8d4b
SG		 6100 if (il->cfg->mod_params->disable_11n)
6101 il->cfg->sku &= ~IL_SKU_N;
be663ab6
WYG		 6102
6103 /* Device-specific setup */
c39ae9fd 6104 return il->ops->lib->set_hw_params(il);
be663ab6
WYG		 6105}
6106
be663ab6 6107static int
e2ebc833 6108il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
be663ab6 6109{
7c2cde2e 6110 int err = 0;
46bc8d4b 6111 struct il_priv *il;
be663ab6 6112 struct ieee80211_hw *hw;
e2ebc833 6113 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
be663ab6
WYG		 6114 unsigned long flags;
6115 u16 pci_cmd;
6116
6117 /************************
6118 * 1. Allocating HW data
6119 ************************/
6120
c39ae9fd 6121 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
be663ab6
WYG		 6122 if (!hw) {
6123 err = -ENOMEM;
6124 goto out;
6125 }
46bc8d4b 6126 il = hw->priv;
c39ae9fd 6127 il->hw = hw;
be663ab6
WYG		 6128 SET_IEEE80211_DEV(hw, &pdev->dev);
6129
58de00a4 6130 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 6131 il->cfg = cfg;
c39ae9fd 6132 il->ops = &il4965_ops;
46bc8d4b
SG		 6133 il->pci_dev = pdev;
6134 il->inta_mask = CSR_INI_SET_MASK;
be663ab6 6135
46bc8d4b 6136 if (il_alloc_traffic_mem(il))
9406f797 6137 IL_ERR("Not enough memory to generate traffic log\n");
be663ab6
WYG		 6138
6139 /**************************
6140 * 2. Initializing PCI bus
6141 **************************/
e7392364
SG		 6142 pci_disable_link_state(pdev,
6143 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6144 PCIE_LINK_STATE_CLKPM);
be663ab6
WYG		 6145
6146 if (pci_enable_device(pdev)) {
6147 err = -ENODEV;
6148 goto out_ieee80211_free_hw;
6149 }
6150
6151 pci_set_master(pdev);
6152
6153 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6154 if (!err)
6155 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6156 if (err) {
6157 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6158 if (!err)
e7392364
SG		 6159 err =
6160 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
be663ab6
WYG		 6161 /* both attempts failed: */
6162 if (err) {
9406f797 6163 IL_WARN("No suitable DMA available.\n");
be663ab6
WYG		 6164 goto out_pci_disable_device;
6165 }
6166 }
6167
6168 err = pci_request_regions(pdev, DRV_NAME);
6169 if (err)
6170 goto out_pci_disable_device;
6171
46bc8d4b 6172 pci_set_drvdata(pdev, il);
be663ab6 6173
be663ab6
WYG		 6174 /***********************
6175 * 3. Read REV register
6176 ***********************/
46bc8d4b
SG		 6177 il->hw_base = pci_iomap(pdev, 0, 0);
6178 if (!il->hw_base) {
be663ab6
WYG		 6179 err = -ENODEV;
6180 goto out_pci_release_regions;
6181 }
6182
58de00a4 6183 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 6184 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 6185 D_INFO("pci_resource_base = %p\n", il->hw_base);
be663ab6
WYG		 6186
6187 /* these spin locks will be used in apm_ops.init and EEPROM access
6188 * we should init now
6189 */
46bc8d4b
SG		 6190 spin_lock_init(&il->reg_lock);
6191 spin_lock_init(&il->lock);
be663ab6
WYG		 6192
6193 /*
6194 * stop and reset the on-board processor just in case it is in a
6195 * strange state ... like being left stranded by a primary kernel
6196 * and this is now the kdump kernel trying to start up
6197 */
841b2cca 6198 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6 6199
46bc8d4b 6200 il4965_hw_detect(il);
e7392364 6201 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
be663ab6
WYG		 6202
6203 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6204 * PCI Tx retries from interfering with C3 CPU state */
6205 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6206
46bc8d4b
SG		 6207 il4965_prepare_card_hw(il);
6208 if (!il->hw_ready) {
9406f797 6209 IL_WARN("Failed, HW not ready\n");
be663ab6
WYG		 6210 goto out_iounmap;
6211 }
6212
6213 /*****************
6214 * 4. Read EEPROM
6215 *****************/
6216 /* Read the EEPROM */
46bc8d4b 6217 err = il_eeprom_init(il);
be663ab6 6218 if (err) {
9406f797 6219 IL_ERR("Unable to init EEPROM\n");
be663ab6
WYG		 6220 goto out_iounmap;
6221 }
46bc8d4b 6222 err = il4965_eeprom_check_version(il);
be663ab6
WYG		 6223 if (err)
6224 goto out_free_eeprom;
6225
6226 if (err)
6227 goto out_free_eeprom;
6228
6229 /* extract MAC Address */
46bc8d4b 6230 il4965_eeprom_get_mac(il, il->addresses[0].addr);
58de00a4 6231 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
46bc8d4b
SG		 6232 il->hw->wiphy->addresses = il->addresses;
6233 il->hw->wiphy->n_addresses = 1;
be663ab6
WYG		 6234
6235 /************************
6236 * 5. Setup HW constants
6237 ************************/
46bc8d4b 6238 if (il4965_set_hw_params(il)) {
9406f797 6239 IL_ERR("failed to set hw parameters\n");
be663ab6
WYG		 6240 goto out_free_eeprom;
6241 }
6242
6243 /*******************
46bc8d4b 6244 * 6. Setup il
be663ab6
WYG		 6245 *******************/
6246
46bc8d4b 6247 err = il4965_init_drv(il);
be663ab6
WYG		 6248 if (err)
6249 goto out_free_eeprom;
46bc8d4b 6250 /* At this point both hw and il are initialized. */
be663ab6
WYG		 6251
6252 /********************
6253 * 7. Setup services
6254 ********************/
46bc8d4b
SG		 6255 spin_lock_irqsave(&il->lock, flags);
6256 il_disable_interrupts(il);
6257 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6258
46bc8d4b 6259 pci_enable_msi(il->pci_dev);
be663ab6 6260
e7392364 6261 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
be663ab6 6262 if (err) {
9406f797 6263 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
be663ab6
WYG		 6264 goto out_disable_msi;
6265 }
6266
46bc8d4b 6267 il4965_setup_deferred_work(il);
d0c72347 6268 il4965_setup_handlers(il);
be663ab6
WYG		 6269
6270 /*********************************************
6271 * 8. Enable interrupts and read RFKILL state
6272 *********************************************/
6273
a078a1fd 6274 /* enable rfkill interrupt: hw bug w/a */
46bc8d4b 6275 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
be663ab6
WYG		 6276 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6277 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
46bc8d4b 6278 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
be663ab6
WYG		 6279 }
6280
46bc8d4b 6281 il_enable_rfkill_int(il);
be663ab6
WYG		 6282
6283 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 6284 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
a6766ccd 6285 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 6286 else
a6766ccd 6287 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 6288
46bc8d4b 6289 wiphy_rfkill_set_hw_state(il->hw->wiphy,
e7392364 6290 test_bit(S_RF_KILL_HW, &il->status));
be663ab6 6291
46bc8d4b 6292 il_power_initialize(il);
be663ab6 6293
46bc8d4b 6294 init_completion(&il->_4965.firmware_loading_complete);
be663ab6 6295
46bc8d4b 6296 err = il4965_request_firmware(il, true);
be663ab6
WYG		 6297 if (err)
6298 goto out_destroy_workqueue;
6299
6300 return 0;
6301
e7392364 6302out_destroy_workqueue:
46bc8d4b
SG		 6303 destroy_workqueue(il->workqueue);
6304 il->workqueue = NULL;
6305 free_irq(il->pci_dev->irq, il);
e7392364 6306out_disable_msi:
46bc8d4b
SG		 6307 pci_disable_msi(il->pci_dev);
6308 il4965_uninit_drv(il);
e7392364 6309out_free_eeprom:
46bc8d4b 6310 il_eeprom_free(il);
e7392364 6311out_iounmap:
46bc8d4b 6312 pci_iounmap(pdev, il->hw_base);
e7392364 6313out_pci_release_regions:
be663ab6
WYG		 6314 pci_set_drvdata(pdev, NULL);
6315 pci_release_regions(pdev);
e7392364 6316out_pci_disable_device:
be663ab6 6317 pci_disable_device(pdev);
e7392364 6318out_ieee80211_free_hw:
46bc8d4b
SG		 6319 il_free_traffic_mem(il);
6320 ieee80211_free_hw(il->hw);
e7392364 6321out:
be663ab6
WYG		 6322 return err;
6323}
6324
e7392364
SG		 6325static void __devexit
6326il4965_pci_remove(struct pci_dev *pdev)
be663ab6 6327{
46bc8d4b 6328 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 6329 unsigned long flags;
6330
46bc8d4b 6331 if (!il)
be663ab6
WYG		 6332 return;
6333
46bc8d4b 6334 wait_for_completion(&il->_4965.firmware_loading_complete);
be663ab6 6335
58de00a4 6336 D_INFO("*** UNLOAD DRIVER ***\n");
be663ab6 6337
46bc8d4b 6338 il_dbgfs_unregister(il);
e2ebc833 6339 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
be663ab6 6340
e2ebc833
SG		 6341 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6342 * to be called and il4965_down since we are removing the device
a6766ccd 6343 * we need to set S_EXIT_PENDING bit.
be663ab6 6344 */
a6766ccd 6345 set_bit(S_EXIT_PENDING, &il->status);
be663ab6 6346
46bc8d4b 6347 il_leds_exit(il);
be663ab6 6348
46bc8d4b
SG		 6349 if (il->mac80211_registered) {
6350 ieee80211_unregister_hw(il->hw);
6351 il->mac80211_registered = 0;
be663ab6 6352 } else {
46bc8d4b 6353 il4965_down(il);
be663ab6
WYG		 6354 }
6355
6356 /*
6357 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG		 6358 * This may be redundant with il4965_down(), but there are paths to
6359 * run il4965_down() without calling apm_ops.stop(), and there are
6360 * paths to avoid running il4965_down() at all before leaving driver.
be663ab6
WYG		 6361 * This (inexpensive) call *makes sure* device is reset.
6362 */
46bc8d4b 6363 il_apm_stop(il);
be663ab6
WYG		 6364
6365 /* make sure we flush any pending irq or
6366 * tasklet for the driver
6367 */
46bc8d4b
SG		 6368 spin_lock_irqsave(&il->lock, flags);
6369 il_disable_interrupts(il);
6370 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6371
46bc8d4b 6372 il4965_synchronize_irq(il);
be663ab6 6373
46bc8d4b 6374 il4965_dealloc_ucode_pci(il);
be663ab6 6375
46bc8d4b
SG		 6376 if (il->rxq.bd)
6377 il4965_rx_queue_free(il, &il->rxq);
6378 il4965_hw_txq_ctx_free(il);
be663ab6 6379
46bc8d4b 6380 il_eeprom_free(il);
be663ab6 6381
be663ab6 6382 /*netif_stop_queue(dev); */
46bc8d4b 6383 flush_workqueue(il->workqueue);
be663ab6 6384
e2ebc833 6385 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
46bc8d4b 6386 * il->workqueue... so we can't take down the workqueue
be663ab6 6387 * until now... */
46bc8d4b
SG		 6388 destroy_workqueue(il->workqueue);
6389 il->workqueue = NULL;
6390 il_free_traffic_mem(il);
be663ab6 6391
46bc8d4b
SG		 6392 free_irq(il->pci_dev->irq, il);
6393 pci_disable_msi(il->pci_dev);
6394 pci_iounmap(pdev, il->hw_base);
be663ab6
WYG		 6395 pci_release_regions(pdev);
6396 pci_disable_device(pdev);
6397 pci_set_drvdata(pdev, NULL);
6398
46bc8d4b 6399 il4965_uninit_drv(il);
be663ab6 6400
46bc8d4b 6401 dev_kfree_skb(il->beacon_skb);
be663ab6 6402
46bc8d4b 6403 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6404}
6405
6406/*
6407 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
46bc8d4b 6408 * must be called under il->lock and mac access
be663ab6 6409 */
e7392364
SG		 6410void
6411il4965_txq_set_sched(struct il_priv *il, u32 mask)
be663ab6 6412{
d3175167 6413 il_wr_prph(il, IL49_SCD_TXFACT, mask);
be663ab6
WYG		 6414}
6415
6416/*****************************************************************************
6417 *
6418 * driver and module entry point
6419 *
6420 *****************************************************************************/
6421
6422/* Hardware specific file defines the PCI IDs table for that hardware module */
e2ebc833 6423static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
e2ebc833
SG		 6424 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6425 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
be663ab6
WYG		 6426 {0}
6427};
e2ebc833 6428MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
be663ab6 6429
e2ebc833 6430static struct pci_driver il4965_driver = {
be663ab6 6431 .name = DRV_NAME,
e2ebc833
SG		 6432 .id_table = il4965_hw_card_ids,
6433 .probe = il4965_pci_probe,
6434 .remove = __devexit_p(il4965_pci_remove),
6435 .driver.pm = IL_LEGACY_PM_OPS,
be663ab6
WYG		 6436};
6437
e7392364
SG		 6438static int __init
6439il4965_init(void)
be663ab6
WYG		 6440{
6441
6442 int ret;
6443 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6444 pr_info(DRV_COPYRIGHT "\n");
6445
e2ebc833 6446 ret = il4965_rate_control_register();
be663ab6
WYG		 6447 if (ret) {
6448 pr_err("Unable to register rate control algorithm: %d\n", ret);
6449 return ret;
6450 }
6451
e2ebc833 6452 ret = pci_register_driver(&il4965_driver);
be663ab6
WYG		 6453 if (ret) {
6454 pr_err("Unable to initialize PCI module\n");
6455 goto error_register;
6456 }
6457
6458 return ret;
6459
6460error_register:
e2ebc833 6461 il4965_rate_control_unregister();
be663ab6
WYG		 6462 return ret;
6463}
6464
e7392364
SG		 6465static void __exit
6466il4965_exit(void)
be663ab6 6467{
e2ebc833
SG		 6468 pci_unregister_driver(&il4965_driver);
6469 il4965_rate_control_unregister();
be663ab6
WYG		 6470}
6471
e2ebc833
SG		 6472module_exit(il4965_exit);
6473module_init(il4965_init);
be663ab6 6474
d3175167 6475#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 6476module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
be663ab6
WYG		 6477MODULE_PARM_DESC(debug, "debug output mask");
6478#endif
6479
e2ebc833 6480module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
be663ab6 6481MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
e2ebc833 6482module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
be663ab6 6483MODULE_PARM_DESC(queues_num, "number of hw queues.");
e2ebc833 6484module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
be663ab6 6485MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
e7392364
SG		 6486module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6487 S_IRUGO);
be663ab6 6488MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
e2ebc833 6489module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
be663ab6 6490MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
Linux kernel - Deliverables
This page took 0.496084 seconds and 5 git commands to generate.