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iwlegacy: move debugfs_ops to il_priv
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
be663ab6
WYG		 43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
98613be0 53#include "common.h"
af038f40 54#include "4965.h"
be663ab6 55
be663ab6
WYG		 56/******************************************************************************
57 *
58 * module boiler plate
59 *
60 ******************************************************************************/
61
62/*
63 * module name, copyright, version, etc.
64 */
65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
66
d3175167 67#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 68#define VD "d"
69#else
70#define VD
71#endif
72
73#define DRV_VERSION IWLWIFI_VERSION VD
74
be663ab6
WYG		 75MODULE_DESCRIPTION(DRV_DESCRIPTION);
76MODULE_VERSION(DRV_VERSION);
77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78MODULE_LICENSE("GPL");
79MODULE_ALIAS("iwl4965");
80
e7392364
SG		 81void
82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
fcb74588
SG		 83{
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
a6766ccd 86 if (!test_bit(S_EXIT_PENDING, &il->status))
fcb74588
SG		 87 queue_work(il->workqueue, &il->tx_flush);
88 }
89}
90
91/*
92 * EEPROM
93 */
94struct il_mod_params il4965_mod_params = {
95 .amsdu_size_8K = 1,
96 .restart_fw = 1,
97 /* the rest are 0 by default */
98};
99
e7392364
SG		 100void
101il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 102{
103 unsigned long flags;
104 int i;
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 114 PAGE_SIZE << il->hw_params.rx_page_order,
115 PCI_DMA_FROMDEVICE);
fcb74588
SG		 116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
118 }
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
120 }
121
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
124
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
129 rxq->free_count = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
131}
132
e7392364
SG		 133int
134il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 135{
136 u32 rb_size;
e7392364 137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
fcb74588
SG		 138 u32 rb_timeout = 0;
139
140 if (il->cfg->mod_params->amsdu_size_8K)
9a95b370 141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
fcb74588 142 else
9a95b370 143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
fcb74588
SG		 144
145 /* Stop Rx DMA */
9a95b370 146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
fcb74588
SG		 147
148 /* Reset driver's Rx queue write idx */
9a95b370 149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
fcb74588
SG		 150
151 /* Tell device where to find RBD circular buffer in DRAM */
e7392364 152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
fcb74588
SG		 153
154 /* Tell device where in DRAM to update its Rx status */
e7392364 155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
fcb74588
SG		 156
157 /* Enable Rx DMA
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
160 * RB timeout 0x10
161 * 256 RBDs
162 */
9a95b370 163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
e7392364
SG		 164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
1722f8e1
SG		 166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
167 rb_size |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
fcb74588
SG		 170
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
173
174 return 0;
175}
176
e7392364
SG		 177static void
178il4965_set_pwr_vmain(struct il_priv *il)
fcb74588
SG		 179{
180/*
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
183
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
188 */
189
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
e7392364
SG		 191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
fcb74588
SG		 193}
194
e7392364
SG		 195int
196il4965_hw_nic_init(struct il_priv *il)
fcb74588
SG		 197{
198 unsigned long flags;
199 struct il_rx_queue *rxq = &il->rxq;
200 int ret;
201
202 /* nic_init */
203 spin_lock_irqsave(&il->lock, flags);
c39ae9fd 204 il->ops->lib->apm_ops.init(il);
fcb74588
SG		 205
206 /* Set interrupt coalescing calibration timer to default (512 usecs) */
207 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
208
209 spin_unlock_irqrestore(&il->lock, flags);
210
211 il4965_set_pwr_vmain(il);
212
c39ae9fd 213 il->ops->lib->apm_ops.config(il);
fcb74588
SG		 214
215 /* Allocate the RX queue, or reset if it is already allocated */
216 if (!rxq->bd) {
217 ret = il_rx_queue_alloc(il);
218 if (ret) {
219 IL_ERR("Unable to initialize Rx queue\n");
220 return -ENOMEM;
221 }
222 } else
223 il4965_rx_queue_reset(il, rxq);
224
225 il4965_rx_replenish(il);
226
227 il4965_rx_init(il, rxq);
228
229 spin_lock_irqsave(&il->lock, flags);
230
231 rxq->need_update = 1;
232 il_rx_queue_update_write_ptr(il, rxq);
233
234 spin_unlock_irqrestore(&il->lock, flags);
235
236 /* Allocate or reset and init all Tx and Command queues */
237 if (!il->txq) {
238 ret = il4965_txq_ctx_alloc(il);
239 if (ret)
240 return ret;
241 } else
242 il4965_txq_ctx_reset(il);
243
a6766ccd 244 set_bit(S_INIT, &il->status);
fcb74588
SG		 245
246 return 0;
247}
248
249/**
250 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
251 */
e7392364
SG		 252static inline __le32
253il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
fcb74588 254{
e7392364 255 return cpu_to_le32((u32) (dma_addr >> 8));
fcb74588
SG		 256}
257
258/**
259 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
260 *
261 * If there are slots in the RX queue that need to be restocked,
262 * and we have free pre-allocated buffers, fill the ranks as much
263 * as we can, pulling from rx_free.
264 *
265 * This moves the 'write' idx forward to catch up with 'processed', and
266 * also updates the memory address in the firmware to reference the new
267 * target buffer.
268 */
e7392364
SG		 269void
270il4965_rx_queue_restock(struct il_priv *il)
fcb74588
SG		 271{
272 struct il_rx_queue *rxq = &il->rxq;
273 struct list_head *element;
274 struct il_rx_buf *rxb;
275 unsigned long flags;
276
277 spin_lock_irqsave(&rxq->lock, flags);
278 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
279 /* The overwritten rxb must be a used one */
280 rxb = rxq->queue[rxq->write];
281 BUG_ON(rxb && rxb->page);
282
283 /* Get next free Rx buffer, remove from free list */
284 element = rxq->rx_free.next;
285 rxb = list_entry(element, struct il_rx_buf, list);
286 list_del(element);
287
288 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG		 289 rxq->bd[rxq->write] =
290 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
fcb74588
SG		 291 rxq->queue[rxq->write] = rxb;
292 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
293 rxq->free_count--;
294 }
295 spin_unlock_irqrestore(&rxq->lock, flags);
296 /* If the pre-allocated buffer pool is dropping low, schedule to
297 * refill it */
298 if (rxq->free_count <= RX_LOW_WATERMARK)
299 queue_work(il->workqueue, &il->rx_replenish);
300
fcb74588
SG		 301 /* If we've added more space for the firmware to place data, tell it.
302 * Increment device's write pointer in multiples of 8. */
303 if (rxq->write_actual != (rxq->write & ~0x7)) {
304 spin_lock_irqsave(&rxq->lock, flags);
305 rxq->need_update = 1;
306 spin_unlock_irqrestore(&rxq->lock, flags);
307 il_rx_queue_update_write_ptr(il, rxq);
308 }
309}
310
311/**
312 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
313 *
314 * When moving to rx_free an SKB is allocated for the slot.
315 *
316 * Also restock the Rx queue via il_rx_queue_restock.
317 * This is called as a scheduled work item (except for during initialization)
318 */
e7392364
SG		 319static void
320il4965_rx_allocate(struct il_priv *il, gfp_t priority)
fcb74588
SG		 321{
322 struct il_rx_queue *rxq = &il->rxq;
323 struct list_head *element;
324 struct il_rx_buf *rxb;
325 struct page *page;
326 unsigned long flags;
327 gfp_t gfp_mask = priority;
328
329 while (1) {
330 spin_lock_irqsave(&rxq->lock, flags);
331 if (list_empty(&rxq->rx_used)) {
332 spin_unlock_irqrestore(&rxq->lock, flags);
333 return;
334 }
335 spin_unlock_irqrestore(&rxq->lock, flags);
336
337 if (rxq->free_count > RX_LOW_WATERMARK)
338 gfp_mask |= __GFP_NOWARN;
339
340 if (il->hw_params.rx_page_order > 0)
341 gfp_mask |= __GFP_COMP;
342
343 /* Alloc a new receive buffer */
344 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
345 if (!page) {
346 if (net_ratelimit())
e7392364
SG		 347 D_INFO("alloc_pages failed, " "order: %d\n",
348 il->hw_params.rx_page_order);
fcb74588
SG		 349
350 if (rxq->free_count <= RX_LOW_WATERMARK &&
351 net_ratelimit())
e7392364
SG		 352 IL_ERR("Failed to alloc_pages with %s. "
353 "Only %u free buffers remaining.\n",
354 priority ==
355 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
356 rxq->free_count);
fcb74588
SG		 357 /* We don't reschedule replenish work here -- we will
358 * call the restock method and if it still needs
359 * more buffers it will schedule replenish */
360 return;
361 }
362
363 spin_lock_irqsave(&rxq->lock, flags);
364
365 if (list_empty(&rxq->rx_used)) {
366 spin_unlock_irqrestore(&rxq->lock, flags);
367 __free_pages(page, il->hw_params.rx_page_order);
368 return;
369 }
370 element = rxq->rx_used.next;
371 rxb = list_entry(element, struct il_rx_buf, list);
372 list_del(element);
373
374 spin_unlock_irqrestore(&rxq->lock, flags);
375
376 BUG_ON(rxb->page);
377 rxb->page = page;
378 /* Get physical address of the RB */
e7392364
SG		 379 rxb->page_dma =
380 pci_map_page(il->pci_dev, page, 0,
381 PAGE_SIZE << il->hw_params.rx_page_order,
382 PCI_DMA_FROMDEVICE);
fcb74588
SG		 383 /* dma address must be no more than 36 bits */
384 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
385 /* and also 256 byte aligned! */
386 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
387
388 spin_lock_irqsave(&rxq->lock, flags);
389
390 list_add_tail(&rxb->list, &rxq->rx_free);
391 rxq->free_count++;
392 il->alloc_rxb_page++;
393
394 spin_unlock_irqrestore(&rxq->lock, flags);
395 }
396}
397
e7392364
SG		 398void
399il4965_rx_replenish(struct il_priv *il)
fcb74588
SG		 400{
401 unsigned long flags;
402
403 il4965_rx_allocate(il, GFP_KERNEL);
404
405 spin_lock_irqsave(&il->lock, flags);
406 il4965_rx_queue_restock(il);
407 spin_unlock_irqrestore(&il->lock, flags);
408}
409
e7392364
SG		 410void
411il4965_rx_replenish_now(struct il_priv *il)
fcb74588
SG		 412{
413 il4965_rx_allocate(il, GFP_ATOMIC);
414
415 il4965_rx_queue_restock(il);
416}
417
418/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
419 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
420 * This free routine walks the list of POOL entries and if SKB is set to
421 * non NULL it is unmapped and freed
422 */
e7392364
SG		 423void
424il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 425{
426 int i;
427 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
428 if (rxq->pool[i].page != NULL) {
429 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 430 PAGE_SIZE << il->hw_params.rx_page_order,
431 PCI_DMA_FROMDEVICE);
fcb74588
SG		 432 __il_free_pages(il, rxq->pool[i].page);
433 rxq->pool[i].page = NULL;
434 }
435 }
436
437 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
438 rxq->bd_dma);
439 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
440 rxq->rb_stts, rxq->rb_stts_dma);
441 rxq->bd = NULL;
e7392364 442 rxq->rb_stts = NULL;
fcb74588
SG		 443}
444
e7392364
SG		 445int
446il4965_rxq_stop(struct il_priv *il)
fcb74588
SG		 447{
448
449 /* stop Rx DMA */
9a95b370
SG		 450 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
451 il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
e7392364 452 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
fcb74588
SG		 453
454 return 0;
455}
456
e7392364
SG		 457int
458il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
fcb74588
SG		 459{
460 int idx = 0;
461 int band_offset = 0;
462
463 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
464 if (rate_n_flags & RATE_MCS_HT_MSK) {
465 idx = (rate_n_flags & 0xff);
466 return idx;
e7392364 467 /* Legacy rate format, search for match in table */
fcb74588
SG		 468 } else {
469 if (band == IEEE80211_BAND_5GHZ)
470 band_offset = IL_FIRST_OFDM_RATE;
471 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
472 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
473 return idx - band_offset;
474 }
475
476 return -1;
477}
478
e7392364
SG		 479static int
480il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
fcb74588
SG		 481{
482 /* data from PHY/DSP regarding signal strength, etc.,
483 * contents are always there, not configurable by host. */
484 struct il4965_rx_non_cfg_phy *ncphy =
485 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
e7392364
SG		 486 u32 agc =
487 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
488 IL49_AGC_DB_POS;
fcb74588
SG		 489
490 u32 valid_antennae =
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
e7392364 492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
fcb74588
SG		 493 u8 max_rssi = 0;
494 u32 i;
495
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
504
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
507 max_rssi, agc);
508
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
512}
513
e7392364
SG		 514static u32
515il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
fcb74588
SG		 516{
517 u32 decrypt_out = 0;
518
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
e7392364
SG		 520 RX_RES_STATUS_STATION_FOUND)
521 decrypt_out |=
522 (RX_RES_STATUS_STATION_FOUND |
523 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
fcb74588
SG		 524
525 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
526
527 /* packet was not encrypted */
528 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 529 RX_RES_STATUS_SEC_TYPE_NONE)
fcb74588
SG		 530 return decrypt_out;
531
532 /* packet was encrypted with unknown alg */
533 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 534 RX_RES_STATUS_SEC_TYPE_ERR)
fcb74588
SG		 535 return decrypt_out;
536
537 /* decryption was not done in HW */
538 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
e7392364 539 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
fcb74588
SG		 540 return decrypt_out;
541
542 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
543
544 case RX_RES_STATUS_SEC_TYPE_CCMP:
545 /* alg is CCM: check MIC only */
546 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
547 /* Bad MIC */
548 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
549 else
550 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
551
552 break;
553
554 case RX_RES_STATUS_SEC_TYPE_TKIP:
555 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
556 /* Bad TTAK */
557 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
558 break;
559 }
560 /* fall through if TTAK OK */
561 default:
562 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
563 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
564 else
565 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
566 break;
567 }
568
e7392364 569 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
fcb74588
SG		 570
571 return decrypt_out;
572}
573
e7392364
SG		 574static void
575il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
576 u16 len, u32 ampdu_status, struct il_rx_buf *rxb,
577 struct ieee80211_rx_status *stats)
fcb74588
SG		 578{
579 struct sk_buff *skb;
580 __le16 fc = hdr->frame_control;
581
582 /* We only process data packets if the interface is open */
583 if (unlikely(!il->is_open)) {
e7392364 584 D_DROP("Dropping packet while interface is not open.\n");
fcb74588
SG		 585 return;
586 }
587
588 /* In case of HW accelerated crypto and bad decryption, drop */
589 if (!il->cfg->mod_params->sw_crypto &&
590 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
591 return;
592
593 skb = dev_alloc_skb(128);
594 if (!skb) {
595 IL_ERR("dev_alloc_skb failed\n");
596 return;
597 }
598
599 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
600
601 il_update_stats(il, false, fc, len);
602 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
603
604 ieee80211_rx(il->hw, skb);
605 il->alloc_rxb_page--;
606 rxb->page = NULL;
607}
608
4d69c752
SG		 609/* Called for N_RX (legacy ABG frames), or
610 * N_RX_MPDU (HT high-throughput N frames). */
e7392364
SG		 611void
612il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 613{
614 struct ieee80211_hdr *header;
615 struct ieee80211_rx_status rx_status;
616 struct il_rx_pkt *pkt = rxb_addr(rxb);
617 struct il_rx_phy_res *phy_res;
618 __le32 rx_pkt_status;
619 struct il_rx_mpdu_res_start *amsdu;
620 u32 len;
621 u32 ampdu_status;
622 u32 rate_n_flags;
623
624 /**
4d69c752
SG		 625 * N_RX and N_RX_MPDU are handled differently.
626 * N_RX: physical layer info is in this buffer
627 * N_RX_MPDU: physical layer info was sent in separate
fcb74588
SG		 628 * command and cached in il->last_phy_res
629 *
630 * Here we set up local variables depending on which command is
631 * received.
632 */
4d69c752 633 if (pkt->hdr.cmd == N_RX) {
fcb74588 634 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
e7392364
SG		 635 header =
636 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
637 phy_res->cfg_phy_cnt);
fcb74588
SG		 638
639 len = le16_to_cpu(phy_res->byte_count);
e7392364
SG		 640 rx_pkt_status =
641 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
642 phy_res->cfg_phy_cnt + len);
fcb74588
SG		 643 ampdu_status = le32_to_cpu(rx_pkt_status);
644 } else {
645 if (!il->_4965.last_phy_res_valid) {
646 IL_ERR("MPDU frame without cached PHY data\n");
647 return;
648 }
649 phy_res = &il->_4965.last_phy_res;
650 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
651 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
652 len = le16_to_cpu(amsdu->byte_count);
e7392364
SG		 653 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
654 ampdu_status =
655 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
fcb74588
SG		 656 }
657
658 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
659 D_DROP("dsp size out of range [0,20]: %d/n",
e7392364 660 phy_res->cfg_phy_cnt);
fcb74588
SG		 661 return;
662 }
663
664 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
665 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e7392364 666 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
fcb74588
SG		 667 return;
668 }
669
670 /* This will be used in several places later */
671 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
672
673 /* rx_status carries information about the packet to mac80211 */
674 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
e7392364
SG		 675 rx_status.band =
676 (phy_res->
677 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
678 IEEE80211_BAND_5GHZ;
fcb74588 679 rx_status.freq =
e7392364
SG		 680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
681 rx_status.band);
fcb74588 682 rx_status.rate_idx =
e7392364 683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
fcb74588
SG		 684 rx_status.flag = 0;
685
686 /* TSF isn't reliable. In order to allow smooth user experience,
687 * this W/A doesn't propagate it to the mac80211 */
e7392364 688 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU; */
fcb74588
SG		 689
690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
691
692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
693 rx_status.signal = il4965_calc_rssi(il, phy_res);
694
695 il_dbg_log_rx_data_frame(il, len, header);
e7392364
SG		 696 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
697 (unsigned long long)rx_status.mactime);
fcb74588
SG		 698
699 /*
700 * "antenna number"
701 *
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
707 *
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
710 * as a bitmask.
711 */
712 rx_status.antenna =
e7392364
SG		 713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
714 RX_RES_PHY_FLAGS_ANTENNA_POS;
fcb74588
SG		 715
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
719
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
727
e7392364
SG		 728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
729 &rx_status);
fcb74588
SG		 730}
731
4d69c752 732/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
6e9848b4 733 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
e7392364
SG		 734void
735il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 736{
737 struct il_rx_pkt *pkt = rxb_addr(rxb);
738 il->_4965.last_phy_res_valid = true;
739 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
740 sizeof(struct il_rx_phy_res));
741}
742
e7392364
SG		 743static int
744il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
745 enum ieee80211_band band, u8 is_active,
746 u8 n_probes, struct il_scan_channel *scan_ch)
fcb74588
SG		 747{
748 struct ieee80211_channel *chan;
749 const struct ieee80211_supported_band *sband;
750 const struct il_channel_info *ch_info;
751 u16 passive_dwell = 0;
752 u16 active_dwell = 0;
753 int added, i;
754 u16 channel;
755
756 sband = il_get_hw_mode(il, band);
757 if (!sband)
758 return 0;
759
760 active_dwell = il_get_active_dwell_time(il, band, n_probes);
761 passive_dwell = il_get_passive_dwell_time(il, band, vif);
762
763 if (passive_dwell <= active_dwell)
764 passive_dwell = active_dwell + 1;
765
766 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
767 chan = il->scan_request->channels[i];
768
769 if (chan->band != band)
770 continue;
771
772 channel = chan->hw_value;
773 scan_ch->channel = cpu_to_le16(channel);
774
775 ch_info = il_get_channel_info(il, band, channel);
776 if (!il_is_channel_valid(ch_info)) {
e7392364
SG		 777 D_SCAN("Channel %d is INVALID for this band.\n",
778 channel);
fcb74588
SG		 779 continue;
780 }
781
782 if (!is_active || il_is_channel_passive(ch_info) ||
783 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
784 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
785 else
786 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
787
788 if (n_probes)
789 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
790
791 scan_ch->active_dwell = cpu_to_le16(active_dwell);
792 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
793
794 /* Set txpower levels to defaults */
795 scan_ch->dsp_atten = 110;
796
797 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
798 * power level:
799 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
800 */
801 if (band == IEEE80211_BAND_5GHZ)
802 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
803 else
804 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
805
e7392364
SG		 806 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
807 le32_to_cpu(scan_ch->type),
808 (scan_ch->
809 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
810 (scan_ch->
811 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
812 passive_dwell);
fcb74588
SG		 813
814 scan_ch++;
815 added++;
816 }
817
818 D_SCAN("total channels to scan %d\n", added);
819 return added;
820}
821
a0c1ef3b
SG		 822static void
823il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
824{
825 int i;
826 u8 ind = *ant;
827
828 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
829 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
830 if (valid & BIT(ind)) {
831 *ant = ind;
832 return;
833 }
834 }
835}
836
e7392364
SG		 837int
838il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
fcb74588
SG		 839{
840 struct il_host_cmd cmd = {
4d69c752 841 .id = C_SCAN,
fcb74588
SG		 842 .len = sizeof(struct il_scan_cmd),
843 .flags = CMD_SIZE_HUGE,
844 };
845 struct il_scan_cmd *scan;
fcb74588
SG		 846 u32 rate_flags = 0;
847 u16 cmd_len;
848 u16 rx_chain = 0;
849 enum ieee80211_band band;
850 u8 n_probes = 0;
851 u8 rx_ant = il->hw_params.valid_rx_ant;
852 u8 rate;
853 bool is_active = false;
e7392364 854 int chan_mod;
fcb74588
SG		 855 u8 active_chains;
856 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
857 int ret;
858
859 lockdep_assert_held(&il->mutex);
860
fcb74588 861 if (!il->scan_cmd) {
e7392364
SG		 862 il->scan_cmd =
863 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
864 GFP_KERNEL);
fcb74588 865 if (!il->scan_cmd) {
e7392364 866 D_SCAN("fail to allocate memory for scan\n");
fcb74588
SG		 867 return -ENOMEM;
868 }
869 }
870 scan = il->scan_cmd;
871 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
872
873 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
874 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
875
876 if (il_is_any_associated(il)) {
877 u16 interval;
878 u32 extra;
879 u32 suspend_time = 100;
880 u32 scan_suspend_time = 100;
881
882 D_INFO("Scanning while associated...\n");
883 interval = vif->bss_conf.beacon_int;
884
885 scan->suspend_time = 0;
886 scan->max_out_time = cpu_to_le32(200 * 1024);
887 if (!interval)
888 interval = suspend_time;
889
890 extra = (suspend_time / interval) << 22;
e7392364
SG		 891 scan_suspend_time =
892 (extra | ((suspend_time % interval) * 1024));
fcb74588
SG		 893 scan->suspend_time = cpu_to_le32(scan_suspend_time);
894 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 895 scan_suspend_time, interval);
fcb74588
SG		 896 }
897
898 if (il->scan_request->n_ssids) {
899 int i, p = 0;
900 D_SCAN("Kicking off active scan\n");
901 for (i = 0; i < il->scan_request->n_ssids; i++) {
902 /* always does wildcard anyway */
903 if (!il->scan_request->ssids[i].ssid_len)
904 continue;
905 scan->direct_scan[p].id = WLAN_EID_SSID;
906 scan->direct_scan[p].len =
e7392364 907 il->scan_request->ssids[i].ssid_len;
fcb74588
SG		 908 memcpy(scan->direct_scan[p].ssid,
909 il->scan_request->ssids[i].ssid,
910 il->scan_request->ssids[i].ssid_len);
911 n_probes++;
912 p++;
913 }
914 is_active = true;
915 } else
916 D_SCAN("Start passive scan.\n");
917
918 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 919 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
fcb74588
SG		 920 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
921
922 switch (il->scan_band) {
923 case IEEE80211_BAND_2GHZ:
924 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
e7392364 925 chan_mod =
c8b03958 926 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
e7392364 927 RXON_FLG_CHANNEL_MODE_POS;
fcb74588
SG		 928 if (chan_mod == CHANNEL_MODE_PURE_40) {
929 rate = RATE_6M_PLCP;
930 } else {
931 rate = RATE_1M_PLCP;
932 rate_flags = RATE_MCS_CCK_MSK;
933 }
934 break;
935 case IEEE80211_BAND_5GHZ:
936 rate = RATE_6M_PLCP;
937 break;
938 default:
939 IL_WARN("Invalid scan band\n");
940 return -EIO;
941 }
942
943 /*
944 * If active scanning is requested but a certain channel is
945 * marked passive, we can do active scanning if we detect
946 * transmissions.
947 *
948 * There is an issue with some firmware versions that triggers
949 * a sysassert on a "good CRC threshold" of zero (== disabled),
950 * on a radar channel even though this means that we should NOT
951 * send probes.
952 *
953 * The "good CRC threshold" is the number of frames that we
954 * need to receive during our dwell time on a channel before
955 * sending out probes -- setting this to a huge value will
956 * mean we never reach it, but at the same time work around
957 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
958 * here instead of IL_GOOD_CRC_TH_DISABLED.
959 */
e7392364
SG		 960 scan->good_CRC_th =
961 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
fcb74588
SG		 962
963 band = il->scan_band;
964
965 if (il->cfg->scan_rx_antennas[band])
966 rx_ant = il->cfg->scan_rx_antennas[band];
967
a0c1ef3b 968 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
616107ed
SG		 969 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
970 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
fcb74588
SG		 971
972 /* In power save mode use one chain, otherwise use all chains */
a6766ccd 973 if (test_bit(S_POWER_PMI, &il->status)) {
fcb74588 974 /* rx_ant has been set to all valid chains previously */
e7392364
SG		 975 active_chains =
976 rx_ant & ((u8) (il->chain_noise_data.active_chains));
fcb74588
SG		 977 if (!active_chains)
978 active_chains = rx_ant;
979
980 D_SCAN("chain_noise_data.active_chains: %u\n",
e7392364 981 il->chain_noise_data.active_chains);
fcb74588
SG		 982
983 rx_ant = il4965_first_antenna(active_chains);
984 }
985
986 /* MIMO is not used here, but value is required */
987 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
988 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
989 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
990 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
991 scan->rx_chain = cpu_to_le16(rx_chain);
992
e7392364
SG		 993 cmd_len =
994 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
995 vif->addr, il->scan_request->ie,
996 il->scan_request->ie_len,
997 IL_MAX_SCAN_SIZE - sizeof(*scan));
fcb74588
SG		 998 scan->tx_cmd.len = cpu_to_le16(cmd_len);
999
e7392364
SG		 1000 scan->filter_flags |=
1001 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
fcb74588 1002
e7392364
SG		 1003 scan->channel_count =
1004 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1005 (void *)&scan->data[cmd_len]);
fcb74588
SG		 1006 if (scan->channel_count == 0) {
1007 D_SCAN("channel count %d\n", scan->channel_count);
1008 return -EIO;
1009 }
1010
e7392364
SG		 1011 cmd.len +=
1012 le16_to_cpu(scan->tx_cmd.len) +
fcb74588
SG		 1013 scan->channel_count * sizeof(struct il_scan_channel);
1014 cmd.data = scan;
1015 scan->len = cpu_to_le16(cmd.len);
1016
a6766ccd 1017 set_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1018
1019 ret = il_send_cmd_sync(il, &cmd);
1020 if (ret)
a6766ccd 1021 clear_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1022
1023 return ret;
1024}
1025
e7392364
SG		 1026int
1027il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1028 bool add)
fcb74588
SG		 1029{
1030 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1031
1032 if (add)
83007196 1033 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
fcb74588
SG		 1034 &vif_priv->ibss_bssid_sta_id);
1035 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
e7392364 1036 vif->bss_conf.bssid);
fcb74588
SG		 1037}
1038
e7392364
SG		 1039void
1040il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
fcb74588
SG		 1041{
1042 lockdep_assert_held(&il->sta_lock);
1043
1044 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1045 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1046 else {
1047 D_TX("free more than tfds_in_queue (%u:%d)\n",
e7392364 1048 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
fcb74588
SG		 1049 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1050 }
1051}
1052
1053#define IL_TX_QUEUE_MSK 0xfffff
1054
e7392364
SG		 1055static bool
1056il4965_is_single_rx_stream(struct il_priv *il)
fcb74588
SG		 1057{
1058 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
e7392364 1059 il->current_ht_config.single_chain_sufficient;
fcb74588
SG		 1060}
1061
1062#define IL_NUM_RX_CHAINS_MULTIPLE 3
1063#define IL_NUM_RX_CHAINS_SINGLE 2
1064#define IL_NUM_IDLE_CHAINS_DUAL 2
1065#define IL_NUM_IDLE_CHAINS_SINGLE 1
1066
1067/*
1068 * Determine how many receiver/antenna chains to use.
1069 *
1070 * More provides better reception via diversity. Fewer saves power
1071 * at the expense of throughput, but only when not in powersave to
1072 * start with.
1073 *
1074 * MIMO (dual stream) requires at least 2, but works better with 3.
1075 * This does not determine *which* chains to use, just how many.
1076 */
e7392364
SG		 1077static int
1078il4965_get_active_rx_chain_count(struct il_priv *il)
fcb74588
SG		 1079{
1080 /* # of Rx chains to use when expecting MIMO. */
1081 if (il4965_is_single_rx_stream(il))
1082 return IL_NUM_RX_CHAINS_SINGLE;
1083 else
1084 return IL_NUM_RX_CHAINS_MULTIPLE;
1085}
1086
1087/*
1088 * When we are in power saving mode, unless device support spatial
1089 * multiplexing power save, use the active count for rx chain count.
1090 */
1091static int
1092il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1093{
1094 /* # Rx chains when idling, depending on SMPS mode */
1095 switch (il->current_ht_config.smps) {
1096 case IEEE80211_SMPS_STATIC:
1097 case IEEE80211_SMPS_DYNAMIC:
1098 return IL_NUM_IDLE_CHAINS_SINGLE;
1099 case IEEE80211_SMPS_OFF:
1100 return active_cnt;
1101 default:
e7392364 1102 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
fcb74588
SG		 1103 return active_cnt;
1104 }
1105}
1106
1107/* up to 4 chains */
e7392364
SG		 1108static u8
1109il4965_count_chain_bitmap(u32 chain_bitmap)
fcb74588
SG		 1110{
1111 u8 res;
1112 res = (chain_bitmap & BIT(0)) >> 0;
1113 res += (chain_bitmap & BIT(1)) >> 1;
1114 res += (chain_bitmap & BIT(2)) >> 2;
1115 res += (chain_bitmap & BIT(3)) >> 3;
1116 return res;
1117}
1118
1119/**
1120 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1121 *
1122 * Selects how many and which Rx receivers/antennas/chains to use.
1123 * This should not be used for scan command ... it puts data in wrong place.
1124 */
e7392364 1125void
83007196 1126il4965_set_rxon_chain(struct il_priv *il)
fcb74588
SG		 1127{
1128 bool is_single = il4965_is_single_rx_stream(il);
a6766ccd 1129 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
fcb74588
SG		 1130 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1131 u32 active_chains;
1132 u16 rx_chain;
1133
1134 /* Tell uCode which antennas are actually connected.
1135 * Before first association, we assume all antennas are connected.
1136 * Just after first association, il4965_chain_noise_calibration()
1137 * checks which antennas actually *are* connected. */
1138 if (il->chain_noise_data.active_chains)
1139 active_chains = il->chain_noise_data.active_chains;
1140 else
1141 active_chains = il->hw_params.valid_rx_ant;
1142
1143 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1144
1145 /* How many receivers should we use? */
1146 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1147 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1148
fcb74588
SG		 1149 /* correct rx chain count according hw settings
1150 * and chain noise calibration
1151 */
1152 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1153 if (valid_rx_cnt < active_rx_cnt)
1154 active_rx_cnt = valid_rx_cnt;
1155
1156 if (valid_rx_cnt < idle_rx_cnt)
1157 idle_rx_cnt = valid_rx_cnt;
1158
1159 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
e7392364 1160 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
fcb74588 1161
c8b03958 1162 il->staging.rx_chain = cpu_to_le16(rx_chain);
fcb74588
SG		 1163
1164 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
c8b03958 1165 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1166 else
c8b03958 1167 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1168
c8b03958 1169 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
e7392364 1170 active_rx_cnt, idle_rx_cnt);
fcb74588
SG		 1171
1172 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1173 active_rx_cnt < idle_rx_cnt);
1174}
1175
e7392364
SG		 1176static const char *
1177il4965_get_fh_string(int cmd)
fcb74588
SG		 1178{
1179 switch (cmd) {
e7392364
SG		 1180 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1181 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1182 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1183 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1184 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1185 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1186 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1187 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1188 IL_CMD(FH49_TSSR_TX_ERROR_REG);
fcb74588
SG		 1189 default:
1190 return "UNKNOWN";
1191 }
1192}
1193
e7392364
SG		 1194int
1195il4965_dump_fh(struct il_priv *il, char **buf, bool display)
fcb74588
SG		 1196{
1197 int i;
1198#ifdef CONFIG_IWLEGACY_DEBUG
1199 int pos = 0;
1200 size_t bufsz = 0;
1201#endif
1202 static const u32 fh_tbl[] = {
9a95b370
SG		 1203 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1204 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1205 FH49_RSCSR_CHNL0_WPTR,
1206 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1207 FH49_MEM_RSSR_SHARED_CTRL_REG,
1208 FH49_MEM_RSSR_RX_STATUS_REG,
1209 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1210 FH49_TSSR_TX_STATUS_REG,
1211 FH49_TSSR_TX_ERROR_REG
fcb74588
SG		 1212 };
1213#ifdef CONFIG_IWLEGACY_DEBUG
1214 if (display) {
1215 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1216 *buf = kmalloc(bufsz, GFP_KERNEL);
1217 if (!*buf)
1218 return -ENOMEM;
e7392364
SG		 1219 pos +=
1220 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
fcb74588 1221 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
e7392364
SG		 1222 pos +=
1223 scnprintf(*buf + pos, bufsz - pos,
1224 " %34s: 0X%08x\n",
1722f8e1
SG		 1225 il4965_get_fh_string(fh_tbl[i]),
1226 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1227 }
1228 return pos;
1229 }
1230#endif
1231 IL_ERR("FH register values:\n");
e7392364
SG		 1232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1233 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1234 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1235 }
1236 return 0;
1237}
a1751b22 1238
e7392364
SG		 1239void
1240il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1241{
1242 struct il_rx_pkt *pkt = rxb_addr(rxb);
1243 struct il_missed_beacon_notif *missed_beacon;
1244
1245 missed_beacon = &pkt->u.missed_beacon;
1246 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1247 il->missed_beacon_threshold) {
e7392364
SG		 1248 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1249 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1250 le32_to_cpu(missed_beacon->total_missed_becons),
1251 le32_to_cpu(missed_beacon->num_recvd_beacons),
1252 le32_to_cpu(missed_beacon->num_expected_beacons));
a6766ccd 1253 if (!test_bit(S_SCANNING, &il->status))
a1751b22
SG		 1254 il4965_init_sensitivity(il);
1255 }
1256}
1257
1258/* Calculate noise level, based on measurements during network silence just
1259 * before arriving beacon. This measurement can be done only if we know
1260 * exactly when to expect beacons, therefore only when we're associated. */
e7392364
SG		 1261static void
1262il4965_rx_calc_noise(struct il_priv *il)
a1751b22
SG		 1263{
1264 struct stats_rx_non_phy *rx_info;
1265 int num_active_rx = 0;
1266 int total_silence = 0;
1267 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1268 int last_rx_noise;
1269
1270 rx_info = &(il->_4965.stats.rx.general);
1271 bcn_silence_a =
e7392364 1272 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
a1751b22 1273 bcn_silence_b =
e7392364 1274 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
a1751b22 1275 bcn_silence_c =
e7392364 1276 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
a1751b22
SG		 1277
1278 if (bcn_silence_a) {
1279 total_silence += bcn_silence_a;
1280 num_active_rx++;
1281 }
1282 if (bcn_silence_b) {
1283 total_silence += bcn_silence_b;
1284 num_active_rx++;
1285 }
1286 if (bcn_silence_c) {
1287 total_silence += bcn_silence_c;
1288 num_active_rx++;
1289 }
1290
1291 /* Average among active antennas */
1292 if (num_active_rx)
1293 last_rx_noise = (total_silence / num_active_rx) - 107;
1294 else
1295 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1296
e7392364
SG		 1297 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1298 bcn_silence_b, bcn_silence_c, last_rx_noise);
a1751b22
SG		 1299}
1300
1301#ifdef CONFIG_IWLEGACY_DEBUGFS
1302/*
1303 * based on the assumption of all stats counter are in DWORD
1304 * FIXME: This function is for debugging, do not deal with
1305 * the case of counters roll-over.
1306 */
e7392364
SG		 1307static void
1308il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
a1751b22
SG		 1309{
1310 int i, size;
1311 __le32 *prev_stats;
1312 u32 *accum_stats;
1313 u32 *delta, *max_delta;
1314 struct stats_general_common *general, *accum_general;
1315 struct stats_tx *tx, *accum_tx;
1316
1722f8e1
SG		 1317 prev_stats = (__le32 *) &il->_4965.stats;
1318 accum_stats = (u32 *) &il->_4965.accum_stats;
a1751b22
SG		 1319 size = sizeof(struct il_notif_stats);
1320 general = &il->_4965.stats.general.common;
1321 accum_general = &il->_4965.accum_stats.general.common;
1322 tx = &il->_4965.stats.tx;
1323 accum_tx = &il->_4965.accum_stats.tx;
1722f8e1
SG		 1324 delta = (u32 *) &il->_4965.delta_stats;
1325 max_delta = (u32 *) &il->_4965.max_delta;
a1751b22
SG		 1326
1327 for (i = sizeof(__le32); i < size;
e7392364
SG		 1328 i +=
1329 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1330 accum_stats++) {
a1751b22 1331 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
e7392364
SG		 1332 *delta =
1333 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
a1751b22
SG		 1334 *accum_stats += *delta;
1335 if (*delta > *max_delta)
1336 *max_delta = *delta;
1337 }
1338 }
1339
1340 /* reset accumulative stats for "no-counter" type stats */
1341 accum_general->temperature = general->temperature;
1342 accum_general->ttl_timestamp = general->ttl_timestamp;
1343}
1344#endif
1345
1346#define REG_RECALIB_PERIOD (60)
1347
e7392364
SG		 1348void
1349il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1350{
1351 int change;
1352 struct il_rx_pkt *pkt = rxb_addr(rxb);
1353
e7392364
SG		 1354 D_RX("Statistics notification received (%d vs %d).\n",
1355 (int)sizeof(struct il_notif_stats),
1356 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1357
1358 change =
1359 ((il->_4965.stats.general.common.temperature !=
1360 pkt->u.stats.general.common.temperature) ||
1361 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1362 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
a1751b22 1363#ifdef CONFIG_IWLEGACY_DEBUGFS
1722f8e1 1364 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
a1751b22
SG		 1365#endif
1366
1367 /* TODO: reading some of stats is unneeded */
e7392364 1368 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
a1751b22 1369
db7746f7 1370 set_bit(S_STATS, &il->status);
a1751b22
SG		 1371
1372 /* Reschedule the stats timer to occur in
1373 * REG_RECALIB_PERIOD seconds to ensure we get a
1374 * thermal update even if the uCode doesn't give
1375 * us one */
e7392364
SG		 1376 mod_timer(&il->stats_periodic,
1377 jiffies + msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
a1751b22 1378
a6766ccd 1379 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
4d69c752 1380 (pkt->hdr.cmd == N_STATS)) {
a1751b22
SG		 1381 il4965_rx_calc_noise(il);
1382 queue_work(il->workqueue, &il->run_time_calib_work);
1383 }
c39ae9fd
SG		 1384 if (il->ops->lib->temp_ops.temperature && change)
1385 il->ops->lib->temp_ops.temperature(il);
a1751b22
SG		 1386}
1387
e7392364
SG		 1388void
1389il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1390{
1391 struct il_rx_pkt *pkt = rxb_addr(rxb);
1392
db7746f7 1393 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
a1751b22
SG		 1394#ifdef CONFIG_IWLEGACY_DEBUGFS
1395 memset(&il->_4965.accum_stats, 0,
e7392364 1396 sizeof(struct il_notif_stats));
a1751b22 1397 memset(&il->_4965.delta_stats, 0,
e7392364
SG		 1398 sizeof(struct il_notif_stats));
1399 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
a1751b22
SG		 1400#endif
1401 D_RX("Statistics have been cleared\n");
1402 }
d2dfb33e 1403 il4965_hdl_stats(il, rxb);
a1751b22
SG		 1404}
1405
8f29b456
SG		 1406
1407/*
1408 * mac80211 queues, ACs, hardware queues, FIFOs.
1409 *
1410 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1411 *
1412 * Mac80211 uses the following numbers, which we get as from it
1413 * by way of skb_get_queue_mapping(skb):
1414 *
1415 * VO 0
1416 * VI 1
1417 * BE 2
1418 * BK 3
1419 *
1420 *
1421 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1422 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1423 * own queue per aggregation session (RA/TID combination), such queues are
1424 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1425 * order to map frames to the right queue, we also need an AC->hw queue
1426 * mapping. This is implemented here.
1427 *
1428 * Due to the way hw queues are set up (by the hw specific modules like
af038f40 1429 * 4965.c), the AC->hw queue mapping is the identity
8f29b456
SG		 1430 * mapping.
1431 */
1432
a1751b22
SG		 1433static const u8 tid_to_ac[] = {
1434 IEEE80211_AC_BE,
1435 IEEE80211_AC_BK,
1436 IEEE80211_AC_BK,
1437 IEEE80211_AC_BE,
1438 IEEE80211_AC_VI,
1439 IEEE80211_AC_VI,
1440 IEEE80211_AC_VO,
1441 IEEE80211_AC_VO
1442};
1443
e7392364
SG		 1444static inline int
1445il4965_get_ac_from_tid(u16 tid)
a1751b22
SG		 1446{
1447 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1448 return tid_to_ac[tid];
1449
1450 /* no support for TIDs 8-15 yet */
1451 return -EINVAL;
1452}
1453
1454static inline int
83007196 1455il4965_get_fifo_from_tid(u16 tid)
a1751b22 1456{
b75b3a70
SG		 1457 const u8 ac_to_fifo[] = {
1458 IL_TX_FIFO_VO,
1459 IL_TX_FIFO_VI,
1460 IL_TX_FIFO_BE,
1461 IL_TX_FIFO_BK,
1462 };
1463
a1751b22 1464 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
b75b3a70 1465 return ac_to_fifo[tid_to_ac[tid]];
a1751b22
SG		 1466
1467 /* no support for TIDs 8-15 yet */
1468 return -EINVAL;
1469}
1470
1471/*
4d69c752 1472 * handle build C_TX command notification.
a1751b22 1473 */
e7392364
SG		 1474static void
1475il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1476 struct il_tx_cmd *tx_cmd,
1477 struct ieee80211_tx_info *info,
1478 struct ieee80211_hdr *hdr, u8 std_id)
a1751b22
SG		 1479{
1480 __le16 fc = hdr->frame_control;
1481 __le32 tx_flags = tx_cmd->tx_flags;
1482
1483 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1484 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1485 tx_flags |= TX_CMD_FLG_ACK_MSK;
1486 if (ieee80211_is_mgmt(fc))
1487 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1488 if (ieee80211_is_probe_resp(fc) &&
1489 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1490 tx_flags |= TX_CMD_FLG_TSF_MSK;
1491 } else {
1492 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1493 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1494 }
1495
1496 if (ieee80211_is_back_req(fc))
1497 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1498
1499 tx_cmd->sta_id = std_id;
1500 if (ieee80211_has_morefrags(fc))
1501 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1502
1503 if (ieee80211_is_data_qos(fc)) {
1504 u8 *qc = ieee80211_get_qos_ctl(hdr);
1505 tx_cmd->tid_tspec = qc[0] & 0xf;
1506 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1507 } else {
1508 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1509 }
1510
1511 il_tx_cmd_protection(il, info, fc, &tx_flags);
1512
1513 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1514 if (ieee80211_is_mgmt(fc)) {
1515 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1516 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1517 else
1518 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1519 } else {
1520 tx_cmd->timeout.pm_frame_timeout = 0;
1521 }
1522
1523 tx_cmd->driver_txop = 0;
1524 tx_cmd->tx_flags = tx_flags;
1525 tx_cmd->next_frame_len = 0;
1526}
1527
e7392364
SG		 1528static void
1529il4965_tx_cmd_build_rate(struct il_priv *il, struct il_tx_cmd *tx_cmd,
1530 struct ieee80211_tx_info *info, __le16 fc)
a1751b22 1531{
616107ed 1532 const u8 rts_retry_limit = 60;
a1751b22
SG		 1533 u32 rate_flags;
1534 int rate_idx;
a1751b22
SG		 1535 u8 data_retry_limit;
1536 u8 rate_plcp;
1537
e7392364 1538 /* Set retry limit on DATA packets and Probe Responses */
a1751b22
SG		 1539 if (ieee80211_is_probe_resp(fc))
1540 data_retry_limit = 3;
1541 else
1542 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1543 tx_cmd->data_retry_limit = data_retry_limit;
a1751b22 1544 /* Set retry limit on RTS packets */
616107ed 1545 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
a1751b22
SG		 1546
1547 /* DATA packets will use the uCode station table for rate/antenna
1548 * selection */
1549 if (ieee80211_is_data(fc)) {
1550 tx_cmd->initial_rate_idx = 0;
1551 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1552 return;
1553 }
1554
1555 /**
1556 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1557 * not really a TX rate. Thus, we use the lowest supported rate for
1558 * this band. Also use the lowest supported rate if the stored rate
1559 * idx is invalid.
1560 */
1561 rate_idx = info->control.rates[0].idx;
e7392364
SG		 1562 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1563 || rate_idx > RATE_COUNT_LEGACY)
1564 rate_idx =
1565 rate_lowest_index(&il->bands[info->band],
1566 info->control.sta);
a1751b22
SG		 1567 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1568 if (info->band == IEEE80211_BAND_5GHZ)
1569 rate_idx += IL_FIRST_OFDM_RATE;
1570 /* Get PLCP rate for tx_cmd->rate_n_flags */
1571 rate_plcp = il_rates[rate_idx].plcp;
1572 /* Zero out flags for this packet */
1573 rate_flags = 0;
1574
1575 /* Set CCK flag as needed */
1576 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1577 rate_flags |= RATE_MCS_CCK_MSK;
1578
1579 /* Set up antennas */
a0c1ef3b 1580 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 1581 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
a1751b22
SG		 1582
1583 /* Set the rate in the TX cmd */
616107ed 1584 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
a1751b22
SG		 1585}
1586
e7392364
SG		 1587static void
1588il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1589 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1590 int sta_id)
a1751b22
SG		 1591{
1592 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1593
1594 switch (keyconf->cipher) {
1595 case WLAN_CIPHER_SUITE_CCMP:
1596 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1597 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1598 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1599 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1600 D_TX("tx_cmd with AES hwcrypto\n");
1601 break;
1602
1603 case WLAN_CIPHER_SUITE_TKIP:
1604 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1605 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1606 D_TX("tx_cmd with tkip hwcrypto\n");
1607 break;
1608
1609 case WLAN_CIPHER_SUITE_WEP104:
1610 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1611 /* fall through */
1612 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG		 1613 tx_cmd->sec_ctl |=
1614 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1615 TX_CMD_SEC_SHIFT);
a1751b22
SG		 1616
1617 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1618
e7392364
SG		 1619 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1620 keyconf->keyidx);
a1751b22
SG		 1621 break;
1622
1623 default:
1624 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1625 break;
1626 }
1627}
1628
1629/*
4d69c752 1630 * start C_TX command process
a1751b22 1631 */
e7392364
SG		 1632int
1633il4965_tx_skb(struct il_priv *il, struct sk_buff *skb)
a1751b22
SG		 1634{
1635 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1636 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1637 struct ieee80211_sta *sta = info->control.sta;
1638 struct il_station_priv *sta_priv = NULL;
1639 struct il_tx_queue *txq;
1640 struct il_queue *q;
1641 struct il_device_cmd *out_cmd;
1642 struct il_cmd_meta *out_meta;
1643 struct il_tx_cmd *tx_cmd;
a1751b22
SG		 1644 int txq_id;
1645 dma_addr_t phys_addr;
1646 dma_addr_t txcmd_phys;
1647 dma_addr_t scratch_phys;
1648 u16 len, firstlen, secondlen;
1649 u16 seq_number = 0;
1650 __le16 fc;
1651 u8 hdr_len;
1652 u8 sta_id;
1653 u8 wait_write_ptr = 0;
1654 u8 tid = 0;
1655 u8 *qc = NULL;
1656 unsigned long flags;
1657 bool is_agg = false;
1658
a1751b22
SG		 1659 spin_lock_irqsave(&il->lock, flags);
1660 if (il_is_rfkill(il)) {
1661 D_DROP("Dropping - RF KILL\n");
1662 goto drop_unlock;
1663 }
1664
1665 fc = hdr->frame_control;
1666
1667#ifdef CONFIG_IWLEGACY_DEBUG
1668 if (ieee80211_is_auth(fc))
1669 D_TX("Sending AUTH frame\n");
1670 else if (ieee80211_is_assoc_req(fc))
1671 D_TX("Sending ASSOC frame\n");
1672 else if (ieee80211_is_reassoc_req(fc))
1673 D_TX("Sending REASSOC frame\n");
1674#endif
1675
1676 hdr_len = ieee80211_hdrlen(fc);
1677
1678 /* For management frames use broadcast id to do not break aggregation */
1679 if (!ieee80211_is_data(fc))
b16db50a 1680 sta_id = il->hw_params.bcast_id;
a1751b22
SG		 1681 else {
1682 /* Find idx into station table for destination station */
83007196 1683 sta_id = il_sta_id_or_broadcast(il, info->control.sta);
a1751b22
SG		 1684
1685 if (sta_id == IL_INVALID_STATION) {
e7392364 1686 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
a1751b22
SG		 1687 goto drop_unlock;
1688 }
1689 }
1690
1691 D_TX("station Id %d\n", sta_id);
1692
1693 if (sta)
1694 sta_priv = (void *)sta->drv_priv;
1695
1696 if (sta_priv && sta_priv->asleep &&
1697 (info->flags & IEEE80211_TX_CTL_POLL_RESPONSE)) {
1698 /*
1699 * This sends an asynchronous command to the device,
1700 * but we can rely on it being processed before the
1701 * next frame is processed -- and the next frame to
1702 * this station is the one that will consume this
1703 * counter.
1704 * For now set the counter to just 1 since we do not
1705 * support uAPSD yet.
1706 */
1707 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1708 }
1709
d1e14e94
SG		 1710 /* FIXME: remove me ? */
1711 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1712
eb123af3
SG		 1713 /* Access category (AC) is also the queue number */
1714 txq_id = skb_get_queue_mapping(skb);
a1751b22
SG		 1715
1716 /* irqs already disabled/saved above when locking il->lock */
1717 spin_lock(&il->sta_lock);
1718
1719 if (ieee80211_is_data_qos(fc)) {
1720 qc = ieee80211_get_qos_ctl(hdr);
1721 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1722 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1723 spin_unlock(&il->sta_lock);
1724 goto drop_unlock;
1725 }
1726 seq_number = il->stations[sta_id].tid[tid].seq_number;
1727 seq_number &= IEEE80211_SCTL_SEQ;
e7392364
SG		 1728 hdr->seq_ctrl =
1729 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
a1751b22
SG		 1730 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1731 seq_number += 0x10;
1732 /* aggregation is on for this <sta,tid> */
1733 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1734 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1735 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1736 is_agg = true;
1737 }
1738 }
1739
1740 txq = &il->txq[txq_id];
1741 q = &txq->q;
1742
1743 if (unlikely(il_queue_space(q) < q->high_mark)) {
1744 spin_unlock(&il->sta_lock);
1745 goto drop_unlock;
1746 }
1747
1748 if (ieee80211_is_data_qos(fc)) {
1749 il->stations[sta_id].tid[tid].tfds_in_queue++;
1750 if (!ieee80211_has_morefrags(fc))
1751 il->stations[sta_id].tid[tid].seq_number = seq_number;
1752 }
1753
1754 spin_unlock(&il->sta_lock);
1755
00ea99e1 1756 txq->skbs[q->write_ptr] = skb;
a1751b22
SG		 1757
1758 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1759 out_cmd = txq->cmd[q->write_ptr];
1760 out_meta = &txq->meta[q->write_ptr];
1761 tx_cmd = &out_cmd->cmd.tx;
1762 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1763 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1764
1765 /*
1766 * Set up the Tx-command (not MAC!) header.
1767 * Store the chosen Tx queue and TFD idx within the sequence field;
1768 * after Tx, uCode's Tx response will return this value so driver can
1769 * locate the frame within the tx queue and do post-tx processing.
1770 */
4d69c752 1771 out_cmd->hdr.cmd = C_TX;
e7392364
SG		 1772 out_cmd->hdr.sequence =
1773 cpu_to_le16((u16)
1774 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
a1751b22
SG		 1775
1776 /* Copy MAC header from skb into command buffer */
1777 memcpy(tx_cmd->hdr, hdr, hdr_len);
1778
a1751b22 1779 /* Total # bytes to be transmitted */
e7392364 1780 len = (u16) skb->len;
a1751b22
SG		 1781 tx_cmd->len = cpu_to_le16(len);
1782
1783 if (info->control.hw_key)
1784 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1785
1786 /* TODO need this for burst mode later on */
1787 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1788 il_dbg_log_tx_data_frame(il, len, hdr);
1789
1790 il4965_tx_cmd_build_rate(il, tx_cmd, info, fc);
1791
1792 il_update_stats(il, true, fc, len);
1793 /*
1794 * Use the first empty entry in this queue's command buffer array
1795 * to contain the Tx command and MAC header concatenated together
1796 * (payload data will be in another buffer).
1797 * Size of this varies, due to varying MAC header length.
1798 * If end is not dword aligned, we'll have 2 extra bytes at the end
1799 * of the MAC header (device reads on dword boundaries).
1800 * We'll tell device about this padding later.
1801 */
e7392364 1802 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
a1751b22
SG		 1803 firstlen = (len + 3) & ~3;
1804
1805 /* Tell NIC about any 2-byte padding after MAC header */
1806 if (firstlen != len)
1807 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1808
1809 /* Physical address of this Tx command's header (not MAC header!),
1810 * within command buffer array. */
e7392364
SG		 1811 txcmd_phys =
1812 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1813 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1814 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1815 dma_unmap_len_set(out_meta, len, firstlen);
1816 /* Add buffer containing Tx command and MAC(!) header to TFD's
1817 * first entry */
c39ae9fd 1818 il->ops->lib->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
a1751b22
SG		 1819
1820 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1821 txq->need_update = 1;
1822 } else {
1823 wait_write_ptr = 1;
1824 txq->need_update = 0;
1825 }
1826
1827 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1828 * if any (802.11 null frames have no payload). */
1829 secondlen = skb->len - hdr_len;
1830 if (secondlen > 0) {
e7392364
SG		 1831 phys_addr =
1832 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1833 PCI_DMA_TODEVICE);
c39ae9fd
SG		 1834 il->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr,
1835 secondlen, 0, 0);
a1751b22
SG		 1836 }
1837
e7392364
SG		 1838 scratch_phys =
1839 txcmd_phys + sizeof(struct il_cmd_header) +
1840 offsetof(struct il_tx_cmd, scratch);
a1751b22
SG		 1841
1842 /* take back ownership of DMA buffer to enable update */
e7392364
SG		 1843 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1844 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1845 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1846 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1847
e7392364 1848 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
a1751b22 1849 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
e7392364
SG		 1850 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1851 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
a1751b22
SG		 1852
1853 /* Set up entry for this TFD in Tx byte-count array */
1854 if (info->flags & IEEE80211_TX_CTL_AMPDU)
c39ae9fd
SG		 1855 il->ops->lib->txq_update_byte_cnt_tbl(il, txq,
1856 le16_to_cpu(tx_cmd->len));
a1751b22 1857
e7392364
SG		 1858 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1859 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1860
1861 /* Tell device the write idx *just past* this latest filled TFD */
1862 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1863 il_txq_update_write_ptr(il, txq);
1864 spin_unlock_irqrestore(&il->lock, flags);
1865
1866 /*
1867 * At this point the frame is "transmitted" successfully
1868 * and we will get a TX status notification eventually,
1869 * regardless of the value of ret. "ret" only indicates
1870 * whether or not we should update the write pointer.
1871 */
1872
1873 /*
1874 * Avoid atomic ops if it isn't an associated client.
1875 * Also, if this is a packet for aggregation, don't
1876 * increase the counter because the ucode will stop
1877 * aggregation queues when their respective station
1878 * goes to sleep.
1879 */
1880 if (sta_priv && sta_priv->client && !is_agg)
1881 atomic_inc(&sta_priv->pending_frames);
1882
1883 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1884 if (wait_write_ptr) {
1885 spin_lock_irqsave(&il->lock, flags);
1886 txq->need_update = 1;
1887 il_txq_update_write_ptr(il, txq);
1888 spin_unlock_irqrestore(&il->lock, flags);
1889 } else {
1890 il_stop_queue(il, txq);
1891 }
1892 }
1893
1894 return 0;
1895
1896drop_unlock:
1897 spin_unlock_irqrestore(&il->lock, flags);
1898 return -1;
1899}
1900
e7392364
SG		 1901static inline int
1902il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
a1751b22 1903{
e7392364
SG		 1904 ptr->addr =
1905 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL);
a1751b22
SG		 1906 if (!ptr->addr)
1907 return -ENOMEM;
1908 ptr->size = size;
1909 return 0;
1910}
1911
e7392364
SG		 1912static inline void
1913il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
a1751b22
SG		 1914{
1915 if (unlikely(!ptr->addr))
1916 return;
1917
1918 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1919 memset(ptr, 0, sizeof(*ptr));
1920}
1921
1922/**
1923 * il4965_hw_txq_ctx_free - Free TXQ Context
1924 *
1925 * Destroy all TX DMA queues and structures
1926 */
e7392364
SG		 1927void
1928il4965_hw_txq_ctx_free(struct il_priv *il)
a1751b22
SG		 1929{
1930 int txq_id;
1931
1932 /* Tx queues */
1933 if (il->txq) {
1934 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1935 if (txq_id == il->cmd_queue)
1936 il_cmd_queue_free(il);
1937 else
1938 il_tx_queue_free(il, txq_id);
1939 }
1940 il4965_free_dma_ptr(il, &il->kw);
1941
1942 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1943
1944 /* free tx queue structure */
1945 il_txq_mem(il);
1946}
1947
1948/**
1949 * il4965_txq_ctx_alloc - allocate TX queue context
1950 * Allocate all Tx DMA structures and initialize them
1951 *
1952 * @param il
1953 * @return error code
1954 */
e7392364
SG		 1955int
1956il4965_txq_ctx_alloc(struct il_priv *il)
a1751b22
SG		 1957{
1958 int ret;
1959 int txq_id, slots_num;
1960 unsigned long flags;
1961
1962 /* Free all tx/cmd queues and keep-warm buffer */
1963 il4965_hw_txq_ctx_free(il);
1964
e7392364
SG		 1965 ret =
1966 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1967 il->hw_params.scd_bc_tbls_size);
a1751b22
SG		 1968 if (ret) {
1969 IL_ERR("Scheduler BC Table allocation failed\n");
1970 goto error_bc_tbls;
1971 }
1972 /* Alloc keep-warm buffer */
1973 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1974 if (ret) {
1975 IL_ERR("Keep Warm allocation failed\n");
1976 goto error_kw;
1977 }
1978
1979 /* allocate tx queue structure */
1980 ret = il_alloc_txq_mem(il);
1981 if (ret)
1982 goto error;
1983
1984 spin_lock_irqsave(&il->lock, flags);
1985
1986 /* Turn off all Tx DMA fifos */
1987 il4965_txq_set_sched(il, 0);
1988
1989 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 1990 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 1991
1992 spin_unlock_irqrestore(&il->lock, flags);
1993
1994 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1995 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
e7392364
SG		 1996 slots_num =
1997 (txq_id ==
1998 il->cmd_queue) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1999 ret = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
a1751b22
SG		 2000 if (ret) {
2001 IL_ERR("Tx %d queue init failed\n", txq_id);
2002 goto error;
2003 }
2004 }
2005
2006 return ret;
2007
e7392364 2008error:
a1751b22
SG		 2009 il4965_hw_txq_ctx_free(il);
2010 il4965_free_dma_ptr(il, &il->kw);
e7392364 2011error_kw:
a1751b22 2012 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
e7392364 2013error_bc_tbls:
a1751b22
SG		 2014 return ret;
2015}
2016
e7392364
SG		 2017void
2018il4965_txq_ctx_reset(struct il_priv *il)
a1751b22
SG		 2019{
2020 int txq_id, slots_num;
2021 unsigned long flags;
2022
2023 spin_lock_irqsave(&il->lock, flags);
2024
2025 /* Turn off all Tx DMA fifos */
2026 il4965_txq_set_sched(il, 0);
2027
2028 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2029 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2030
2031 spin_unlock_irqrestore(&il->lock, flags);
2032
2033 /* Alloc and init all Tx queues, including the command queue (#4) */
2034 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
e7392364
SG		 2035 slots_num =
2036 txq_id == il->cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
2037 il_tx_queue_reset(il, &il->txq[txq_id], slots_num, txq_id);
a1751b22
SG		 2038 }
2039}
2040
2041/**
2042 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2043 */
e7392364
SG		 2044void
2045il4965_txq_ctx_stop(struct il_priv *il)
a1751b22
SG		 2046{
2047 int ch, txq_id;
2048 unsigned long flags;
2049
2050 /* Turn off all Tx DMA fifos */
2051 spin_lock_irqsave(&il->lock, flags);
2052
2053 il4965_txq_set_sched(il, 0);
2054
2055 /* Stop each Tx DMA channel, and wait for it to be idle */
2056 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
e7392364
SG		 2057 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2058 if (il_poll_bit
2059 (il, FH49_TSSR_TX_STATUS_REG,
2060 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000))
a1751b22 2061 IL_ERR("Failing on timeout while stopping"
1722f8e1
SG		 2062 " DMA channel %d [0x%08x]", ch,
2063 il_rd(il, FH49_TSSR_TX_STATUS_REG));
a1751b22
SG		 2064 }
2065 spin_unlock_irqrestore(&il->lock, flags);
2066
2067 if (!il->txq)
2068 return;
2069
2070 /* Unmap DMA from host system and free skb's */
2071 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2072 if (txq_id == il->cmd_queue)
2073 il_cmd_queue_unmap(il);
2074 else
2075 il_tx_queue_unmap(il, txq_id);
2076}
2077
2078/*
2079 * Find first available (lowest unused) Tx Queue, mark it "active".
2080 * Called only when finding queue for aggregation.
2081 * Should never return anything < 7, because they should already
2082 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2083 */
e7392364
SG		 2084static int
2085il4965_txq_ctx_activate_free(struct il_priv *il)
a1751b22
SG		 2086{
2087 int txq_id;
2088
2089 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2090 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2091 return txq_id;
2092 return -1;
2093}
2094
2095/**
2096 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2097 */
e7392364
SG		 2098static void
2099il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
a1751b22
SG		 2100{
2101 /* Simply stop the queue, but don't change any configuration;
2102 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
e7392364 2103 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 2104 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2105 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
a1751b22
SG		 2106}
2107
2108/**
2109 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2110 */
e7392364
SG		 2111static int
2112il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
a1751b22
SG		 2113{
2114 u32 tbl_dw_addr;
2115 u32 tbl_dw;
2116 u16 scd_q2ratid;
2117
2118 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2119
e7392364
SG		 2120 tbl_dw_addr =
2121 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
a1751b22
SG		 2122
2123 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2124
2125 if (txq_id & 0x1)
2126 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2127 else
2128 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2129
2130 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2131
2132 return 0;
2133}
2134
2135/**
2136 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2137 *
2138 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2139 * i.e. it must be one of the higher queues used for aggregation
2140 */
e7392364
SG		 2141static int
2142il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2143 int tid, u16 ssn_idx)
a1751b22
SG		 2144{
2145 unsigned long flags;
2146 u16 ra_tid;
2147 int ret;
2148
2149 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2150 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2151 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2152 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2153 txq_id, IL49_FIRST_AMPDU_QUEUE,
2154 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2155 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2156 return -EINVAL;
2157 }
2158
2159 ra_tid = BUILD_RAxTID(sta_id, tid);
2160
2161 /* Modify device's station table to Tx this TID */
2162 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2163 if (ret)
2164 return ret;
2165
2166 spin_lock_irqsave(&il->lock, flags);
2167
2168 /* Stop this Tx queue before configuring it */
2169 il4965_tx_queue_stop_scheduler(il, txq_id);
2170
2171 /* Map receiver-address / traffic-ID to this queue */
2172 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2173
2174 /* Set this queue as a chain-building queue */
2175 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2176
2177 /* Place first TFD at idx corresponding to start sequence number.
2178 * Assumes that ssn_idx is valid (!= 0xFFF) */
2179 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2180 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2181 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2182
2183 /* Set up Tx win size and frame limit for this queue */
2184 il_write_targ_mem(il,
e7392364
SG		 2185 il->scd_base_addr +
2186 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2187 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2188 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
a1751b22 2189
e7392364
SG		 2190 il_write_targ_mem(il,
2191 il->scd_base_addr +
2192 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2193 (SCD_FRAME_LIMIT <<
2194 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2195 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
a1751b22
SG		 2196
2197 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2198
2199 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2200 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2201
2202 spin_unlock_irqrestore(&il->lock, flags);
2203
2204 return 0;
2205}
2206
e7392364
SG		 2207int
2208il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2209 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
a1751b22
SG		 2210{
2211 int sta_id;
2212 int tx_fifo;
2213 int txq_id;
2214 int ret;
2215 unsigned long flags;
2216 struct il_tid_data *tid_data;
2217
83007196
SG		 2218 /* FIXME: warning if tx fifo not found ? */
2219 tx_fifo = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2220 if (unlikely(tx_fifo < 0))
2221 return tx_fifo;
2222
53611e05 2223 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
a1751b22
SG		 2224
2225 sta_id = il_sta_id(sta);
2226 if (sta_id == IL_INVALID_STATION) {
2227 IL_ERR("Start AGG on invalid station\n");
2228 return -ENXIO;
2229 }
2230 if (unlikely(tid >= MAX_TID_COUNT))
2231 return -EINVAL;
2232
2233 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2234 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2235 return -ENXIO;
2236 }
2237
2238 txq_id = il4965_txq_ctx_activate_free(il);
2239 if (txq_id == -1) {
2240 IL_ERR("No free aggregation queue available\n");
2241 return -ENXIO;
2242 }
2243
2244 spin_lock_irqsave(&il->sta_lock, flags);
2245 tid_data = &il->stations[sta_id].tid[tid];
2246 *ssn = SEQ_TO_SN(tid_data->seq_number);
2247 tid_data->agg.txq_id = txq_id;
e7392364 2248 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
a1751b22
SG		 2249 spin_unlock_irqrestore(&il->sta_lock, flags);
2250
e7392364 2251 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
a1751b22
SG		 2252 if (ret)
2253 return ret;
2254
2255 spin_lock_irqsave(&il->sta_lock, flags);
2256 tid_data = &il->stations[sta_id].tid[tid];
2257 if (tid_data->tfds_in_queue == 0) {
2258 D_HT("HW queue is empty\n");
2259 tid_data->agg.state = IL_AGG_ON;
2260 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2261 } else {
e7392364
SG		 2262 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2263 tid_data->tfds_in_queue);
a1751b22
SG		 2264 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2265 }
2266 spin_unlock_irqrestore(&il->sta_lock, flags);
2267 return ret;
2268}
2269
2270/**
2271 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2272 * il->lock must be held by the caller
2273 */
e7392364
SG		 2274static int
2275il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
a1751b22
SG		 2276{
2277 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2278 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2279 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2280 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2281 txq_id, IL49_FIRST_AMPDU_QUEUE,
2282 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2283 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2284 return -EINVAL;
2285 }
2286
2287 il4965_tx_queue_stop_scheduler(il, txq_id);
2288
e7392364 2289 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
a1751b22
SG		 2290
2291 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2292 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2293 /* supposes that ssn_idx is valid (!= 0xFFF) */
2294 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2295
e7392364 2296 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
a1751b22
SG		 2297 il_txq_ctx_deactivate(il, txq_id);
2298 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2299
2300 return 0;
2301}
2302
e7392364
SG		 2303int
2304il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2305 struct ieee80211_sta *sta, u16 tid)
a1751b22
SG		 2306{
2307 int tx_fifo_id, txq_id, sta_id, ssn;
2308 struct il_tid_data *tid_data;
2309 int write_ptr, read_ptr;
2310 unsigned long flags;
2311
83007196
SG		 2312 /* FIXME: warning if tx_fifo_id not found ? */
2313 tx_fifo_id = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2314 if (unlikely(tx_fifo_id < 0))
2315 return tx_fifo_id;
2316
2317 sta_id = il_sta_id(sta);
2318
2319 if (sta_id == IL_INVALID_STATION) {
2320 IL_ERR("Invalid station for AGG tid %d\n", tid);
2321 return -ENXIO;
2322 }
2323
2324 spin_lock_irqsave(&il->sta_lock, flags);
2325
2326 tid_data = &il->stations[sta_id].tid[tid];
2327 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2328 txq_id = tid_data->agg.txq_id;
2329
2330 switch (il->stations[sta_id].tid[tid].agg.state) {
2331 case IL_EMPTYING_HW_QUEUE_ADDBA:
2332 /*
2333 * This can happen if the peer stops aggregation
2334 * again before we've had a chance to drain the
2335 * queue we selected previously, i.e. before the
2336 * session was really started completely.
2337 */
2338 D_HT("AGG stop before setup done\n");
2339 goto turn_off;
2340 case IL_AGG_ON:
2341 break;
2342 default:
2343 IL_WARN("Stopping AGG while state not ON or starting\n");
2344 }
2345
2346 write_ptr = il->txq[txq_id].q.write_ptr;
2347 read_ptr = il->txq[txq_id].q.read_ptr;
2348
2349 /* The queue is not empty */
2350 if (write_ptr != read_ptr) {
2351 D_HT("Stopping a non empty AGG HW QUEUE\n");
2352 il->stations[sta_id].tid[tid].agg.state =
e7392364 2353 IL_EMPTYING_HW_QUEUE_DELBA;
a1751b22
SG		 2354 spin_unlock_irqrestore(&il->sta_lock, flags);
2355 return 0;
2356 }
2357
2358 D_HT("HW queue is empty\n");
e7392364 2359turn_off:
a1751b22
SG		 2360 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2361
2362 /* do not restore/save irqs */
2363 spin_unlock(&il->sta_lock);
2364 spin_lock(&il->lock);
2365
2366 /*
2367 * the only reason this call can fail is queue number out of range,
2368 * which can happen if uCode is reloaded and all the station
2369 * information are lost. if it is outside the range, there is no need
2370 * to deactivate the uCode queue, just return "success" to allow
2371 * mac80211 to clean up it own data.
2372 */
2373 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2374 spin_unlock_irqrestore(&il->lock, flags);
2375
2376 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2377
2378 return 0;
2379}
2380
e7392364
SG		 2381int
2382il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
a1751b22
SG		 2383{
2384 struct il_queue *q = &il->txq[txq_id].q;
2385 u8 *addr = il->stations[sta_id].sta.sta.addr;
2386 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
a1751b22
SG		 2387
2388 lockdep_assert_held(&il->sta_lock);
2389
2390 switch (il->stations[sta_id].tid[tid].agg.state) {
2391 case IL_EMPTYING_HW_QUEUE_DELBA:
2392 /* We are reclaiming the last packet of the */
2393 /* aggregated HW queue */
e7392364 2394 if (txq_id == tid_data->agg.txq_id &&
a1751b22
SG		 2395 q->read_ptr == q->write_ptr) {
2396 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
83007196 2397 int tx_fifo = il4965_get_fifo_from_tid(tid);
e7392364 2398 D_HT("HW queue empty: continue DELBA flow\n");
a1751b22
SG		 2399 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2400 tid_data->agg.state = IL_AGG_OFF;
83007196 2401 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2402 }
2403 break;
2404 case IL_EMPTYING_HW_QUEUE_ADDBA:
2405 /* We are reclaiming the last packet of the queue */
2406 if (tid_data->tfds_in_queue == 0) {
e7392364 2407 D_HT("HW queue empty: continue ADDBA flow\n");
a1751b22 2408 tid_data->agg.state = IL_AGG_ON;
83007196 2409 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2410 }
2411 break;
2412 }
2413
2414 return 0;
2415}
2416
e7392364 2417static void
83007196 2418il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
a1751b22
SG		 2419{
2420 struct ieee80211_sta *sta;
2421 struct il_station_priv *sta_priv;
2422
2423 rcu_read_lock();
83007196 2424 sta = ieee80211_find_sta(il->vif, addr1);
a1751b22
SG		 2425 if (sta) {
2426 sta_priv = (void *)sta->drv_priv;
2427 /* avoid atomic ops if this isn't a client */
2428 if (sta_priv->client &&
2429 atomic_dec_return(&sta_priv->pending_frames) == 0)
2430 ieee80211_sta_block_awake(il->hw, sta, false);
2431 }
2432 rcu_read_unlock();
2433}
2434
2435static void
00ea99e1 2436il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
a1751b22 2437{
00ea99e1 2438 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
a1751b22
SG		 2439
2440 if (!is_agg)
83007196 2441 il4965_non_agg_tx_status(il, hdr->addr1);
a1751b22 2442
00ea99e1 2443 ieee80211_tx_status_irqsafe(il->hw, skb);
a1751b22
SG		 2444}
2445
e7392364
SG		 2446int
2447il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
a1751b22
SG		 2448{
2449 struct il_tx_queue *txq = &il->txq[txq_id];
2450 struct il_queue *q = &txq->q;
a1751b22
SG		 2451 int nfreed = 0;
2452 struct ieee80211_hdr *hdr;
00ea99e1 2453 struct sk_buff *skb;
a1751b22
SG		 2454
2455 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2456 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 2457 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2458 q->write_ptr, q->read_ptr);
a1751b22
SG		 2459 return 0;
2460 }
2461
e7392364 2462 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
a1751b22
SG		 2463 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2464
00ea99e1 2465 skb = txq->skbs[txq->q.read_ptr];
a1751b22 2466
00ea99e1 2467 if (WARN_ON_ONCE(skb == NULL))
a1751b22
SG		 2468 continue;
2469
00ea99e1 2470 hdr = (struct ieee80211_hdr *) skb->data;
a1751b22
SG		 2471 if (ieee80211_is_data_qos(hdr->frame_control))
2472 nfreed++;
2473
00ea99e1 2474 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
a1751b22 2475
00ea99e1 2476 txq->skbs[txq->q.read_ptr] = NULL;
c39ae9fd 2477 il->ops->lib->txq_free_tfd(il, txq);
a1751b22
SG		 2478 }
2479 return nfreed;
2480}
2481
2482/**
2483 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2484 *
2485 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2486 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2487 */
e7392364
SG		 2488static int
2489il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2490 struct il_compressed_ba_resp *ba_resp)
a1751b22
SG		 2491{
2492 int i, sh, ack;
2493 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2494 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2495 int successes = 0;
2496 struct ieee80211_tx_info *info;
2497 u64 bitmap, sent_bitmap;
2498
e7392364 2499 if (unlikely(!agg->wait_for_ba)) {
a1751b22
SG		 2500 if (unlikely(ba_resp->bitmap))
2501 IL_ERR("Received BA when not expected\n");
2502 return -EINVAL;
2503 }
2504
2505 /* Mark that the expected block-ack response arrived */
2506 agg->wait_for_ba = 0;
e7392364 2507 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
a1751b22
SG		 2508
2509 /* Calculate shift to align block-ack bits with our Tx win bits */
2510 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
e7392364 2511 if (sh < 0) /* tbw something is wrong with indices */
a1751b22
SG		 2512 sh += 0x100;
2513
2514 if (agg->frame_count > (64 - sh)) {
2515 D_TX_REPLY("more frames than bitmap size");
2516 return -1;
2517 }
2518
2519 /* don't use 64-bit values for now */
2520 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2521
2522 /* check for success or failure according to the
2523 * transmitted bitmap and block-ack bitmap */
2524 sent_bitmap = bitmap & agg->bitmap;
2525
2526 /* For each frame attempted in aggregation,
2527 * update driver's record of tx frame's status. */
2528 i = 0;
2529 while (sent_bitmap) {
2530 ack = sent_bitmap & 1ULL;
2531 successes += ack;
e7392364
SG		 2532 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2533 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
a1751b22
SG		 2534 sent_bitmap >>= 1;
2535 ++i;
2536 }
2537
e7392364 2538 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
a1751b22 2539
00ea99e1 2540 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
a1751b22
SG		 2541 memset(&info->status, 0, sizeof(info->status));
2542 info->flags |= IEEE80211_TX_STAT_ACK;
2543 info->flags |= IEEE80211_TX_STAT_AMPDU;
2544 info->status.ampdu_ack_len = successes;
2545 info->status.ampdu_len = agg->frame_count;
2546 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2547
2548 return 0;
2549}
2550
3dfea27d
SG		 2551static inline bool
2552il4965_is_tx_success(u32 status)
2553{
2554 status &= TX_STATUS_MSK;
2555 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2556}
2557
2558static u8
2559il4965_find_station(struct il_priv *il, const u8 *addr)
2560{
2561 int i;
2562 int start = 0;
2563 int ret = IL_INVALID_STATION;
2564 unsigned long flags;
2565
2566 if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2567 start = IL_STA_ID;
2568
2569 if (is_broadcast_ether_addr(addr))
2570 return il->hw_params.bcast_id;
2571
2572 spin_lock_irqsave(&il->sta_lock, flags);
2573 for (i = start; i < il->hw_params.max_stations; i++)
2574 if (il->stations[i].used &&
2575 (!compare_ether_addr(il->stations[i].sta.sta.addr, addr))) {
2576 ret = i;
2577 goto out;
2578 }
2579
2580 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2581
2582out:
2583 /*
2584 * It may be possible that more commands interacting with stations
2585 * arrive before we completed processing the adding of
2586 * station
2587 */
2588 if (ret != IL_INVALID_STATION &&
2589 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2590 ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2591 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2592 IL_ERR("Requested station info for sta %d before ready.\n",
2593 ret);
2594 ret = IL_INVALID_STATION;
2595 }
2596 spin_unlock_irqrestore(&il->sta_lock, flags);
2597 return ret;
2598}
2599
2600static int
2601il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2602{
2603 if (il->iw_mode == NL80211_IFTYPE_STATION)
2604 return IL_AP_ID;
2605 else {
2606 u8 *da = ieee80211_get_DA(hdr);
2607
2608 return il4965_find_station(il, da);
2609 }
2610}
2611
2612static inline u32
2613il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2614{
2615 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
2616}
2617
2618static inline u32
2619il4965_tx_status_to_mac80211(u32 status)
2620{
2621 status &= TX_STATUS_MSK;
2622
2623 switch (status) {
2624 case TX_STATUS_SUCCESS:
2625 case TX_STATUS_DIRECT_DONE:
2626 return IEEE80211_TX_STAT_ACK;
2627 case TX_STATUS_FAIL_DEST_PS:
2628 return IEEE80211_TX_STAT_TX_FILTERED;
2629 default:
2630 return 0;
2631 }
2632}
2633
2634/**
2635 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2636 */
2637static int
2638il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2639 struct il4965_tx_resp *tx_resp, int txq_id,
2640 u16 start_idx)
2641{
2642 u16 status;
2643 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2644 struct ieee80211_tx_info *info = NULL;
2645 struct ieee80211_hdr *hdr = NULL;
2646 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2647 int i, sh, idx;
2648 u16 seq;
2649 if (agg->wait_for_ba)
2650 D_TX_REPLY("got tx response w/o block-ack\n");
2651
2652 agg->frame_count = tx_resp->frame_count;
2653 agg->start_idx = start_idx;
2654 agg->rate_n_flags = rate_n_flags;
2655 agg->bitmap = 0;
2656
2657 /* num frames attempted by Tx command */
2658 if (agg->frame_count == 1) {
2659 /* Only one frame was attempted; no block-ack will arrive */
2660 status = le16_to_cpu(frame_status[0].status);
2661 idx = start_idx;
2662
2663 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2664 agg->frame_count, agg->start_idx, idx);
2665
2666 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2667 info->status.rates[0].count = tx_resp->failure_frame + 1;
2668 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2669 info->flags |= il4965_tx_status_to_mac80211(status);
2670 il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2671
2672 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2673 tx_resp->failure_frame);
2674 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2675
2676 agg->wait_for_ba = 0;
2677 } else {
2678 /* Two or more frames were attempted; expect block-ack */
2679 u64 bitmap = 0;
2680 int start = agg->start_idx;
2681 struct sk_buff *skb;
2682
2683 /* Construct bit-map of pending frames within Tx win */
2684 for (i = 0; i < agg->frame_count; i++) {
2685 u16 sc;
2686 status = le16_to_cpu(frame_status[i].status);
2687 seq = le16_to_cpu(frame_status[i].sequence);
2688 idx = SEQ_TO_IDX(seq);
2689 txq_id = SEQ_TO_QUEUE(seq);
2690
2691 if (status &
2692 (AGG_TX_STATE_FEW_BYTES_MSK |
2693 AGG_TX_STATE_ABORT_MSK))
2694 continue;
2695
2696 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2697 agg->frame_count, txq_id, idx);
2698
2699 skb = il->txq[txq_id].skbs[idx];
2700 if (WARN_ON_ONCE(skb == NULL))
2701 return -1;
2702 hdr = (struct ieee80211_hdr *) skb->data;
2703
2704 sc = le16_to_cpu(hdr->seq_ctrl);
2705 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2706 IL_ERR("BUG_ON idx doesn't match seq control"
2707 " idx=%d, seq_idx=%d, seq=%d\n", idx,
2708 SEQ_TO_SN(sc), hdr->seq_ctrl);
2709 return -1;
2710 }
2711
2712 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
2713 SEQ_TO_SN(sc));
2714
2715 sh = idx - start;
2716 if (sh > 64) {
2717 sh = (start - idx) + 0xff;
2718 bitmap = bitmap << sh;
2719 sh = 0;
2720 start = idx;
2721 } else if (sh < -64)
2722 sh = 0xff - (start - idx);
2723 else if (sh < 0) {
2724 sh = start - idx;
2725 start = idx;
2726 bitmap = bitmap << sh;
2727 sh = 0;
2728 }
2729 bitmap |= 1ULL << sh;
2730 D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2731 (unsigned long long)bitmap);
2732 }
2733
2734 agg->bitmap = bitmap;
2735 agg->start_idx = start;
2736 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2737 agg->frame_count, agg->start_idx,
2738 (unsigned long long)agg->bitmap);
2739
2740 if (bitmap)
2741 agg->wait_for_ba = 1;
2742 }
2743 return 0;
2744}
2745
2746/**
2747 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2748 */
2749static void
2750il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2751{
2752 struct il_rx_pkt *pkt = rxb_addr(rxb);
2753 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2754 int txq_id = SEQ_TO_QUEUE(sequence);
2755 int idx = SEQ_TO_IDX(sequence);
2756 struct il_tx_queue *txq = &il->txq[txq_id];
2757 struct sk_buff *skb;
2758 struct ieee80211_hdr *hdr;
2759 struct ieee80211_tx_info *info;
2760 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2761 u32 status = le32_to_cpu(tx_resp->u.status);
2762 int uninitialized_var(tid);
2763 int sta_id;
2764 int freed;
2765 u8 *qc = NULL;
2766 unsigned long flags;
2767
2768 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2769 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2770 "is out of range [0-%d] %d %d\n", txq_id, idx,
2771 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2772 return;
2773 }
2774
2775 txq->time_stamp = jiffies;
2776
2777 skb = txq->skbs[txq->q.read_ptr];
2778 info = IEEE80211_SKB_CB(skb);
2779 memset(&info->status, 0, sizeof(info->status));
2780
2781 hdr = (struct ieee80211_hdr *) skb->data;
2782 if (ieee80211_is_data_qos(hdr->frame_control)) {
2783 qc = ieee80211_get_qos_ctl(hdr);
2784 tid = qc[0] & 0xf;
2785 }
2786
2787 sta_id = il4965_get_ra_sta_id(il, hdr);
2788 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2789 IL_ERR("Station not known\n");
2790 return;
2791 }
2792
2793 spin_lock_irqsave(&il->sta_lock, flags);
2794 if (txq->sched_retry) {
2795 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2796 struct il_ht_agg *agg = NULL;
2797 WARN_ON(!qc);
2798
2799 agg = &il->stations[sta_id].tid[tid].agg;
2800
2801 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2802
2803 /* check if BAR is needed */
2804 if (tx_resp->frame_count == 1 &&
2805 !il4965_is_tx_success(status))
2806 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2807
2808 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2809 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2810 D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2811 "%d idx %d\n", scd_ssn, idx);
2812 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2813 if (qc)
2814 il4965_free_tfds_in_queue(il, sta_id, tid,
2815 freed);
2816
2817 if (il->mac80211_registered &&
2818 il_queue_space(&txq->q) > txq->q.low_mark &&
2819 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2820 il_wake_queue(il, txq);
2821 }
2822 } else {
2823 info->status.rates[0].count = tx_resp->failure_frame + 1;
2824 info->flags |= il4965_tx_status_to_mac80211(status);
2825 il4965_hwrate_to_tx_control(il,
2826 le32_to_cpu(tx_resp->rate_n_flags),
2827 info);
2828
2829 D_TX_REPLY("TXQ %d status %s (0x%08x) "
2830 "rate_n_flags 0x%x retries %d\n", txq_id,
2831 il4965_get_tx_fail_reason(status), status,
2832 le32_to_cpu(tx_resp->rate_n_flags),
2833 tx_resp->failure_frame);
2834
2835 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2836 if (qc && likely(sta_id != IL_INVALID_STATION))
2837 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2838 else if (sta_id == IL_INVALID_STATION)
2839 D_TX_REPLY("Station not known\n");
2840
2841 if (il->mac80211_registered &&
2842 il_queue_space(&txq->q) > txq->q.low_mark)
2843 il_wake_queue(il, txq);
2844 }
2845 if (qc && likely(sta_id != IL_INVALID_STATION))
2846 il4965_txq_check_empty(il, sta_id, tid, txq_id);
2847
2848 il4965_check_abort_status(il, tx_resp->frame_count, status);
2849
2850 spin_unlock_irqrestore(&il->sta_lock, flags);
2851}
2852
a1751b22
SG		 2853/**
2854 * translate ucode response to mac80211 tx status control values
2855 */
e7392364
SG		 2856void
2857il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2858 struct ieee80211_tx_info *info)
a1751b22
SG		 2859{
2860 struct ieee80211_tx_rate *r = &info->control.rates[0];
2861
2862 info->antenna_sel_tx =
e7392364 2863 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
a1751b22
SG		 2864 if (rate_n_flags & RATE_MCS_HT_MSK)
2865 r->flags |= IEEE80211_TX_RC_MCS;
2866 if (rate_n_flags & RATE_MCS_GF_MSK)
2867 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2868 if (rate_n_flags & RATE_MCS_HT40_MSK)
2869 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2870 if (rate_n_flags & RATE_MCS_DUP_MSK)
2871 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2872 if (rate_n_flags & RATE_MCS_SGI_MSK)
2873 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2874 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2875}
2876
2877/**
6e9848b4 2878 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
a1751b22
SG		 2879 *
2880 * Handles block-acknowledge notification from device, which reports success
2881 * of frames sent via aggregation.
2882 */
e7392364
SG		 2883void
2884il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 2885{
2886 struct il_rx_pkt *pkt = rxb_addr(rxb);
2887 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2888 struct il_tx_queue *txq = NULL;
2889 struct il_ht_agg *agg;
2890 int idx;
2891 int sta_id;
2892 int tid;
2893 unsigned long flags;
2894
2895 /* "flow" corresponds to Tx queue */
2896 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2897
2898 /* "ssn" is start of block-ack Tx win, corresponds to idx
2899 * (in Tx queue's circular buffer) of first TFD/frame in win */
2900 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2901
2902 if (scd_flow >= il->hw_params.max_txq_num) {
e7392364 2903 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
a1751b22
SG		 2904 return;
2905 }
2906
2907 txq = &il->txq[scd_flow];
2908 sta_id = ba_resp->sta_id;
2909 tid = ba_resp->tid;
2910 agg = &il->stations[sta_id].tid[tid].agg;
2911 if (unlikely(agg->txq_id != scd_flow)) {
2912 /*
2913 * FIXME: this is a uCode bug which need to be addressed,
2914 * log the information and return for now!
2915 * since it is possible happen very often and in order
2916 * not to fill the syslog, don't enable the logging by default
2917 */
e7392364
SG		 2918 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2919 scd_flow, agg->txq_id);
a1751b22
SG		 2920 return;
2921 }
2922
2923 /* Find idx just before block-ack win */
2924 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2925
2926 spin_lock_irqsave(&il->sta_lock, flags);
2927
e7392364 2928 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
1722f8e1 2929 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
e7392364
SG		 2930 ba_resp->sta_id);
2931 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2932 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2933 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2934 ba_resp->scd_flow, ba_resp->scd_ssn);
2935 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2936 (unsigned long long)agg->bitmap);
a1751b22
SG		 2937
2938 /* Update driver's record of ACK vs. not for each frame in win */
2939 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2940
2941 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2942 * block-ack win (we assume that they've been successfully
2943 * transmitted ... if not, it's too late anyway). */
2944 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2945 /* calculate mac80211 ampdu sw queue to wake */
2946 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2947 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2948
2949 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2950 il->mac80211_registered &&
2951 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2952 il_wake_queue(il, txq);
2953
2954 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2955 }
2956
2957 spin_unlock_irqrestore(&il->sta_lock, flags);
2958}
2959
2960#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2961const char *
2962il4965_get_tx_fail_reason(u32 status)
a1751b22
SG		 2963{
2964#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2965#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2966
2967 switch (status & TX_STATUS_MSK) {
2968 case TX_STATUS_SUCCESS:
2969 return "SUCCESS";
e7392364
SG		 2970 TX_STATUS_POSTPONE(DELAY);
2971 TX_STATUS_POSTPONE(FEW_BYTES);
2972 TX_STATUS_POSTPONE(QUIET_PERIOD);
2973 TX_STATUS_POSTPONE(CALC_TTAK);
2974 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2975 TX_STATUS_FAIL(SHORT_LIMIT);
2976 TX_STATUS_FAIL(LONG_LIMIT);
2977 TX_STATUS_FAIL(FIFO_UNDERRUN);
2978 TX_STATUS_FAIL(DRAIN_FLOW);
2979 TX_STATUS_FAIL(RFKILL_FLUSH);
2980 TX_STATUS_FAIL(LIFE_EXPIRE);
2981 TX_STATUS_FAIL(DEST_PS);
2982 TX_STATUS_FAIL(HOST_ABORTED);
2983 TX_STATUS_FAIL(BT_RETRY);
2984 TX_STATUS_FAIL(STA_INVALID);
2985 TX_STATUS_FAIL(FRAG_DROPPED);
2986 TX_STATUS_FAIL(TID_DISABLE);
2987 TX_STATUS_FAIL(FIFO_FLUSHED);
2988 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
2989 TX_STATUS_FAIL(PASSIVE_NO_RX);
2990 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
a1751b22
SG		 2991 }
2992
2993 return "UNKNOWN";
2994
2995#undef TX_STATUS_FAIL
2996#undef TX_STATUS_POSTPONE
2997}
2998#endif /* CONFIG_IWLEGACY_DEBUG */
2999
eb3cdfb7
SG		 3000static struct il_link_quality_cmd *
3001il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
3002{
3003 int i, r;
3004 struct il_link_quality_cmd *link_cmd;
3005 u32 rate_flags = 0;
3006 __le32 rate_n_flags;
3007
3008 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3009 if (!link_cmd) {
3010 IL_ERR("Unable to allocate memory for LQ cmd.\n");
3011 return NULL;
3012 }
3013 /* Set up the rate scaling to start at selected rate, fall back
3014 * all the way down to 1M in IEEE order, and then spin on 1M */
3015 if (il->band == IEEE80211_BAND_5GHZ)
3016 r = RATE_6M_IDX;
3017 else
3018 r = RATE_1M_IDX;
3019
3020 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3021 rate_flags |= RATE_MCS_CCK_MSK;
3022
e7392364
SG		 3023 rate_flags |=
3024 il4965_first_antenna(il->hw_params.
3025 valid_tx_ant) << RATE_MCS_ANT_POS;
616107ed 3026 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
eb3cdfb7
SG		 3027 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3028 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3029
3030 link_cmd->general_params.single_stream_ant_msk =
e7392364 3031 il4965_first_antenna(il->hw_params.valid_tx_ant);
eb3cdfb7
SG		 3032
3033 link_cmd->general_params.dual_stream_ant_msk =
e7392364
SG		 3034 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3035 valid_tx_ant);
eb3cdfb7
SG		 3036 if (!link_cmd->general_params.dual_stream_ant_msk) {
3037 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3038 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3039 link_cmd->general_params.dual_stream_ant_msk =
e7392364 3040 il->hw_params.valid_tx_ant;
eb3cdfb7
SG		 3041 }
3042
3043 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3044 link_cmd->agg_params.agg_time_limit =
e7392364 3045 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
eb3cdfb7
SG		 3046
3047 link_cmd->sta_id = sta_id;
3048
3049 return link_cmd;
3050}
3051
3052/*
3053 * il4965_add_bssid_station - Add the special IBSS BSSID station
3054 *
3055 * Function sleeps.
3056 */
3057int
83007196 3058il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
eb3cdfb7
SG		 3059{
3060 int ret;
3061 u8 sta_id;
3062 struct il_link_quality_cmd *link_cmd;
3063 unsigned long flags;
3064
3065 if (sta_id_r)
3066 *sta_id_r = IL_INVALID_STATION;
3067
83007196 3068 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
eb3cdfb7
SG		 3069 if (ret) {
3070 IL_ERR("Unable to add station %pM\n", addr);
3071 return ret;
3072 }
3073
3074 if (sta_id_r)
3075 *sta_id_r = sta_id;
3076
3077 spin_lock_irqsave(&il->sta_lock, flags);
3078 il->stations[sta_id].used |= IL_STA_LOCAL;
3079 spin_unlock_irqrestore(&il->sta_lock, flags);
3080
3081 /* Set up default rate scaling table in device's station table */
3082 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3083 if (!link_cmd) {
e7392364
SG		 3084 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3085 addr);
eb3cdfb7
SG		 3086 return -ENOMEM;
3087 }
3088
83007196 3089 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
eb3cdfb7
SG		 3090 if (ret)
3091 IL_ERR("Link quality command failed (%d)\n", ret);
3092
3093 spin_lock_irqsave(&il->sta_lock, flags);
3094 il->stations[sta_id].lq = link_cmd;
3095 spin_unlock_irqrestore(&il->sta_lock, flags);
3096
3097 return 0;
3098}
3099
e7392364 3100static int
83007196 3101il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
eb3cdfb7 3102{
d735f921 3103 int i;
eb3cdfb7
SG		 3104 u8 buff[sizeof(struct il_wep_cmd) +
3105 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3106 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
e7392364 3107 size_t cmd_size = sizeof(struct il_wep_cmd);
eb3cdfb7 3108 struct il_host_cmd cmd = {
d98e2942 3109 .id = C_WEPKEY,
eb3cdfb7
SG		 3110 .data = wep_cmd,
3111 .flags = CMD_SYNC,
3112 };
d735f921 3113 bool not_empty = false;
eb3cdfb7
SG		 3114
3115 might_sleep();
3116
e7392364
SG		 3117 memset(wep_cmd, 0,
3118 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
eb3cdfb7 3119
e7392364 3120 for (i = 0; i < WEP_KEYS_MAX; i++) {
d735f921
SG		 3121 u8 key_size = il->_4965.wep_keys[i].key_size;
3122
eb3cdfb7 3123 wep_cmd->key[i].key_idx = i;
d735f921 3124 if (key_size) {
eb3cdfb7 3125 wep_cmd->key[i].key_offset = i;
d735f921
SG		 3126 not_empty = true;
3127 } else
eb3cdfb7 3128 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
eb3cdfb7 3129
d735f921
SG		 3130 wep_cmd->key[i].key_size = key_size;
3131 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
eb3cdfb7
SG		 3132 }
3133
3134 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3135 wep_cmd->num_keys = WEP_KEYS_MAX;
3136
3137 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
eb3cdfb7
SG		 3138 cmd.len = cmd_size;
3139
3140 if (not_empty || send_if_empty)
3141 return il_send_cmd(il, &cmd);
3142 else
3143 return 0;
3144}
3145
e7392364 3146int
83007196 3147il4965_restore_default_wep_keys(struct il_priv *il)
eb3cdfb7
SG		 3148{
3149 lockdep_assert_held(&il->mutex);
3150
83007196 3151 return il4965_static_wepkey_cmd(il, false);
eb3cdfb7
SG		 3152}
3153
e7392364 3154int
83007196 3155il4965_remove_default_wep_key(struct il_priv *il,
e7392364 3156 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3157{
3158 int ret;
d735f921 3159 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3160
3161 lockdep_assert_held(&il->mutex);
3162
d735f921 3163 D_WEP("Removing default WEP key: idx=%d\n", idx);
eb3cdfb7 3164
d735f921 3165 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
eb3cdfb7 3166 if (il_is_rfkill(il)) {
e7392364 3167 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
eb3cdfb7
SG		 3168 /* but keys in device are clear anyway so return success */
3169 return 0;
3170 }
83007196 3171 ret = il4965_static_wepkey_cmd(il, 1);
d735f921 3172 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
eb3cdfb7
SG		 3173
3174 return ret;
3175}
3176
e7392364 3177int
83007196 3178il4965_set_default_wep_key(struct il_priv *il,
e7392364 3179 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3180{
3181 int ret;
d735f921
SG		 3182 int len = keyconf->keylen;
3183 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3184
3185 lockdep_assert_held(&il->mutex);
3186
d735f921 3187 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
eb3cdfb7
SG		 3188 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3189 return -EINVAL;
3190 }
3191
3192 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3193 keyconf->hw_key_idx = HW_KEY_DEFAULT;
8f9e5645 3194 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
eb3cdfb7 3195
d735f921
SG		 3196 il->_4965.wep_keys[idx].key_size = len;
3197 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
eb3cdfb7 3198
83007196 3199 ret = il4965_static_wepkey_cmd(il, false);
eb3cdfb7 3200
d735f921 3201 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
eb3cdfb7
SG		 3202 return ret;
3203}
3204
e7392364 3205static int
83007196 3206il4965_set_wep_dynamic_key_info(struct il_priv *il,
e7392364 3207 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3208{
3209 unsigned long flags;
3210 __le16 key_flags = 0;
3211 struct il_addsta_cmd sta_cmd;
3212
3213 lockdep_assert_held(&il->mutex);
3214
3215 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3216
3217 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3218 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3219 key_flags &= ~STA_KEY_FLG_INVALID;
3220
3221 if (keyconf->keylen == WEP_KEY_LEN_128)
3222 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3223
b16db50a 3224 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3225 key_flags |= STA_KEY_MULTICAST_MSK;
3226
3227 spin_lock_irqsave(&il->sta_lock, flags);
3228
3229 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3230 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3231 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3232
e7392364 3233 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3234
e7392364
SG		 3235 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3236 keyconf->keylen);
eb3cdfb7 3237
e7392364
SG		 3238 if ((il->stations[sta_id].sta.key.
3239 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3240 il->stations[sta_id].sta.key.key_offset =
e7392364 3241 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3242 /* else, we are overriding an existing key => no need to allocated room
3243 * in uCode. */
3244
3245 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3246 "no space for a new key");
eb3cdfb7
SG		 3247
3248 il->stations[sta_id].sta.key.key_flags = key_flags;
3249 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3250 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3251
3252 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3253 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3254 spin_unlock_irqrestore(&il->sta_lock, flags);
3255
3256 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3257}
3258
e7392364
SG		 3259static int
3260il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
e7392364 3261 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3262{
3263 unsigned long flags;
3264 __le16 key_flags = 0;
3265 struct il_addsta_cmd sta_cmd;
3266
3267 lockdep_assert_held(&il->mutex);
3268
3269 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3270 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3271 key_flags &= ~STA_KEY_FLG_INVALID;
3272
b16db50a 3273 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3274 key_flags |= STA_KEY_MULTICAST_MSK;
3275
3276 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3277
3278 spin_lock_irqsave(&il->sta_lock, flags);
3279 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3280 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3281
e7392364 3282 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3283
e7392364 3284 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3285
e7392364
SG		 3286 if ((il->stations[sta_id].sta.key.
3287 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3288 il->stations[sta_id].sta.key.key_offset =
e7392364 3289 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3290 /* else, we are overriding an existing key => no need to allocated room
3291 * in uCode. */
3292
3293 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3294 "no space for a new key");
eb3cdfb7
SG		 3295
3296 il->stations[sta_id].sta.key.key_flags = key_flags;
3297 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3298 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3299
3300 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3301 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3302 spin_unlock_irqrestore(&il->sta_lock, flags);
3303
3304 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3305}
3306
e7392364
SG		 3307static int
3308il4965_set_tkip_dynamic_key_info(struct il_priv *il,
e7392364 3309 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3310{
3311 unsigned long flags;
3312 int ret = 0;
3313 __le16 key_flags = 0;
3314
3315 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3316 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3317 key_flags &= ~STA_KEY_FLG_INVALID;
3318
b16db50a 3319 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3320 key_flags |= STA_KEY_MULTICAST_MSK;
3321
3322 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3323 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3324
3325 spin_lock_irqsave(&il->sta_lock, flags);
3326
3327 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3328 il->stations[sta_id].keyinfo.keylen = 16;
3329
e7392364
SG		 3330 if ((il->stations[sta_id].sta.key.
3331 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3332 il->stations[sta_id].sta.key.key_offset =
e7392364 3333 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3334 /* else, we are overriding an existing key => no need to allocated room
3335 * in uCode. */
3336
3337 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3338 "no space for a new key");
eb3cdfb7
SG		 3339
3340 il->stations[sta_id].sta.key.key_flags = key_flags;
3341
eb3cdfb7
SG		 3342 /* This copy is acutally not needed: we get the key with each TX */
3343 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3344
3345 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3346
3347 spin_unlock_irqrestore(&il->sta_lock, flags);
3348
3349 return ret;
3350}
3351
e7392364 3352void
83007196
SG		 3353il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3354 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
eb3cdfb7
SG		 3355{
3356 u8 sta_id;
3357 unsigned long flags;
3358 int i;
3359
3360 if (il_scan_cancel(il)) {
3361 /* cancel scan failed, just live w/ bad key and rely
3362 briefly on SW decryption */
3363 return;
3364 }
3365
83007196 3366 sta_id = il_sta_id_or_broadcast(il, sta);
eb3cdfb7
SG		 3367 if (sta_id == IL_INVALID_STATION)
3368 return;
3369
3370 spin_lock_irqsave(&il->sta_lock, flags);
3371
3372 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3373
3374 for (i = 0; i < 5; i++)
3375 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
e7392364 3376 cpu_to_le16(phase1key[i]);
eb3cdfb7
SG		 3377
3378 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3379 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3380
3381 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3382
3383 spin_unlock_irqrestore(&il->sta_lock, flags);
eb3cdfb7
SG		 3384}
3385
e7392364 3386int
83007196 3387il4965_remove_dynamic_key(struct il_priv *il,
e7392364 3388 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3389{
3390 unsigned long flags;
3391 u16 key_flags;
3392 u8 keyidx;
3393 struct il_addsta_cmd sta_cmd;
3394
3395 lockdep_assert_held(&il->mutex);
3396
d735f921 3397 il->_4965.key_mapping_keys--;
eb3cdfb7
SG		 3398
3399 spin_lock_irqsave(&il->sta_lock, flags);
3400 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3401 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3402
e7392364 3403 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
eb3cdfb7
SG		 3404
3405 if (keyconf->keyidx != keyidx) {
3406 /* We need to remove a key with idx different that the one
3407 * in the uCode. This means that the key we need to remove has
3408 * been replaced by another one with different idx.
3409 * Don't do anything and return ok
3410 */
3411 spin_unlock_irqrestore(&il->sta_lock, flags);
3412 return 0;
3413 }
3414
3415 if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) {
e7392364
SG		 3416 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3417 key_flags);
eb3cdfb7
SG		 3418 spin_unlock_irqrestore(&il->sta_lock, flags);
3419 return 0;
3420 }
3421
e7392364
SG		 3422 if (!test_and_clear_bit
3423 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
eb3cdfb7 3424 IL_ERR("idx %d not used in uCode key table.\n",
e7392364
SG		 3425 il->stations[sta_id].sta.key.key_offset);
3426 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3427 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
eb3cdfb7 3428 il->stations[sta_id].sta.key.key_flags =
e7392364 3429 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
eb3cdfb7
SG		 3430 il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
3431 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3432 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3433
3434 if (il_is_rfkill(il)) {
e7392364
SG		 3435 D_WEP
3436 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
eb3cdfb7
SG		 3437 spin_unlock_irqrestore(&il->sta_lock, flags);
3438 return 0;
3439 }
3440 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3441 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3442 spin_unlock_irqrestore(&il->sta_lock, flags);
3443
3444 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3445}
3446
e7392364 3447int
83007196
SG		 3448il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3449 u8 sta_id)
eb3cdfb7
SG		 3450{
3451 int ret;
3452
3453 lockdep_assert_held(&il->mutex);
3454
d735f921 3455 il->_4965.key_mapping_keys++;
eb3cdfb7
SG		 3456 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3457
3458 switch (keyconf->cipher) {
3459 case WLAN_CIPHER_SUITE_CCMP:
e7392364 3460 ret =
83007196 3461 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3462 break;
3463 case WLAN_CIPHER_SUITE_TKIP:
e7392364 3464 ret =
83007196 3465 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3466 break;
3467 case WLAN_CIPHER_SUITE_WEP40:
3468 case WLAN_CIPHER_SUITE_WEP104:
83007196 3469 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3470 break;
3471 default:
e7392364
SG		 3472 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3473 keyconf->cipher);
eb3cdfb7
SG		 3474 ret = -EINVAL;
3475 }
3476
e7392364
SG		 3477 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3478 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
eb3cdfb7
SG		 3479
3480 return ret;
3481}
3482
3483/**
3484 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3485 *
3486 * This adds the broadcast station into the driver's station table
3487 * and marks it driver active, so that it will be restored to the
3488 * device at the next best time.
3489 */
e7392364 3490int
83007196 3491il4965_alloc_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3492{
3493 struct il_link_quality_cmd *link_cmd;
3494 unsigned long flags;
3495 u8 sta_id;
3496
3497 spin_lock_irqsave(&il->sta_lock, flags);
83007196 3498 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
eb3cdfb7
SG		 3499 if (sta_id == IL_INVALID_STATION) {
3500 IL_ERR("Unable to prepare broadcast station\n");
3501 spin_unlock_irqrestore(&il->sta_lock, flags);
3502
3503 return -EINVAL;
3504 }
3505
3506 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3507 il->stations[sta_id].used |= IL_STA_BCAST;
3508 spin_unlock_irqrestore(&il->sta_lock, flags);
3509
3510 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3511 if (!link_cmd) {
e7392364
SG		 3512 IL_ERR
3513 ("Unable to initialize rate scaling for bcast station.\n");
eb3cdfb7
SG		 3514 return -ENOMEM;
3515 }
3516
3517 spin_lock_irqsave(&il->sta_lock, flags);
3518 il->stations[sta_id].lq = link_cmd;
3519 spin_unlock_irqrestore(&il->sta_lock, flags);
3520
3521 return 0;
3522}
3523
3524/**
3525 * il4965_update_bcast_station - update broadcast station's LQ command
3526 *
3527 * Only used by iwl4965. Placed here to have all bcast station management
3528 * code together.
3529 */
e7392364 3530static int
83007196 3531il4965_update_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3532{
3533 unsigned long flags;
3534 struct il_link_quality_cmd *link_cmd;
b16db50a 3535 u8 sta_id = il->hw_params.bcast_id;
eb3cdfb7
SG		 3536
3537 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3538 if (!link_cmd) {
1722f8e1 3539 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
eb3cdfb7
SG		 3540 return -ENOMEM;
3541 }
3542
3543 spin_lock_irqsave(&il->sta_lock, flags);
3544 if (il->stations[sta_id].lq)
3545 kfree(il->stations[sta_id].lq);
3546 else
1722f8e1 3547 D_INFO("Bcast sta rate scaling has not been initialized.\n");
eb3cdfb7
SG		 3548 il->stations[sta_id].lq = link_cmd;
3549 spin_unlock_irqrestore(&il->sta_lock, flags);
3550
3551 return 0;
3552}
3553
e7392364
SG		 3554int
3555il4965_update_bcast_stations(struct il_priv *il)
eb3cdfb7 3556{
83007196 3557 return il4965_update_bcast_station(il);
eb3cdfb7
SG		 3558}
3559
3560/**
3561 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3562 */
e7392364
SG		 3563int
3564il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
eb3cdfb7
SG		 3565{
3566 unsigned long flags;
3567 struct il_addsta_cmd sta_cmd;
3568
3569 lockdep_assert_held(&il->mutex);
3570
3571 /* Remove "disable" flag, to enable Tx for this TID */
3572 spin_lock_irqsave(&il->sta_lock, flags);
3573 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3574 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3575 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3576 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3577 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3578 spin_unlock_irqrestore(&il->sta_lock, flags);
3579
3580 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3581}
3582
e7392364
SG		 3583int
3584il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3585 u16 ssn)
eb3cdfb7
SG		 3586{
3587 unsigned long flags;
3588 int sta_id;
3589 struct il_addsta_cmd sta_cmd;
3590
3591 lockdep_assert_held(&il->mutex);
3592
3593 sta_id = il_sta_id(sta);
3594 if (sta_id == IL_INVALID_STATION)
3595 return -ENXIO;
3596
3597 spin_lock_irqsave(&il->sta_lock, flags);
3598 il->stations[sta_id].sta.station_flags_msk = 0;
3599 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
e7392364 3600 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3601 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3602 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3603 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3604 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3605 spin_unlock_irqrestore(&il->sta_lock, flags);
3606
3607 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3608}
3609
e7392364
SG		 3610int
3611il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
eb3cdfb7
SG		 3612{
3613 unsigned long flags;
3614 int sta_id;
3615 struct il_addsta_cmd sta_cmd;
3616
3617 lockdep_assert_held(&il->mutex);
3618
3619 sta_id = il_sta_id(sta);
3620 if (sta_id == IL_INVALID_STATION) {
3621 IL_ERR("Invalid station for AGG tid %d\n", tid);
3622 return -ENXIO;
3623 }
3624
3625 spin_lock_irqsave(&il->sta_lock, flags);
3626 il->stations[sta_id].sta.station_flags_msk = 0;
3627 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
e7392364 3628 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3629 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3630 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3631 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3632 spin_unlock_irqrestore(&il->sta_lock, flags);
3633
3634 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3635}
3636
3637void
3638il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3639{
3640 unsigned long flags;
3641
3642 spin_lock_irqsave(&il->sta_lock, flags);
3643 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3644 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3645 il->stations[sta_id].sta.sta.modify_mask =
e7392364 3646 STA_MODIFY_SLEEP_TX_COUNT_MSK;
eb3cdfb7
SG		 3647 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3648 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364 3649 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
eb3cdfb7
SG		 3650 spin_unlock_irqrestore(&il->sta_lock, flags);
3651
3652}
3653
e7392364
SG		 3654void
3655il4965_update_chain_flags(struct il_priv *il)
be663ab6 3656{
c39ae9fd
SG		 3657 if (il->ops->hcmd->set_rxon_chain) {
3658 il->ops->hcmd->set_rxon_chain(il);
c8b03958 3659 if (il->active.rx_chain != il->staging.rx_chain)
83007196 3660 il_commit_rxon(il);
be663ab6
WYG		 3661 }
3662}
3663
e7392364
SG		 3664static void
3665il4965_clear_free_frames(struct il_priv *il)
be663ab6
WYG		 3666{
3667 struct list_head *element;
3668
e7392364 3669 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
be663ab6 3670
46bc8d4b
SG		 3671 while (!list_empty(&il->free_frames)) {
3672 element = il->free_frames.next;
be663ab6 3673 list_del(element);
e2ebc833 3674 kfree(list_entry(element, struct il_frame, list));
46bc8d4b 3675 il->frames_count--;
be663ab6
WYG		 3676 }
3677
46bc8d4b 3678 if (il->frames_count) {
9406f797 3679 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 3680 il->frames_count);
46bc8d4b 3681 il->frames_count = 0;
be663ab6
WYG		 3682 }
3683}
3684
e7392364
SG		 3685static struct il_frame *
3686il4965_get_free_frame(struct il_priv *il)
be663ab6 3687{
e2ebc833 3688 struct il_frame *frame;
be663ab6 3689 struct list_head *element;
46bc8d4b 3690 if (list_empty(&il->free_frames)) {
be663ab6
WYG		 3691 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3692 if (!frame) {
9406f797 3693 IL_ERR("Could not allocate frame!\n");
be663ab6
WYG		 3694 return NULL;
3695 }
3696
46bc8d4b 3697 il->frames_count++;
be663ab6
WYG		 3698 return frame;
3699 }
3700
46bc8d4b 3701 element = il->free_frames.next;
be663ab6 3702 list_del(element);
e2ebc833 3703 return list_entry(element, struct il_frame, list);
be663ab6
WYG		 3704}
3705
e7392364
SG		 3706static void
3707il4965_free_frame(struct il_priv *il, struct il_frame *frame)
be663ab6
WYG		 3708{
3709 memset(frame, 0, sizeof(*frame));
46bc8d4b 3710 list_add(&frame->list, &il->free_frames);
be663ab6
WYG		 3711}
3712
e7392364
SG		 3713static u32
3714il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3715 int left)
be663ab6 3716{
46bc8d4b 3717 lockdep_assert_held(&il->mutex);
be663ab6 3718
46bc8d4b 3719 if (!il->beacon_skb)
be663ab6
WYG		 3720 return 0;
3721
46bc8d4b 3722 if (il->beacon_skb->len > left)
be663ab6
WYG		 3723 return 0;
3724
46bc8d4b 3725 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
be663ab6 3726
46bc8d4b 3727 return il->beacon_skb->len;
be663ab6
WYG		 3728}
3729
3730/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
e7392364
SG		 3731static void
3732il4965_set_beacon_tim(struct il_priv *il,
3733 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3734 u32 frame_size)
be663ab6
WYG		 3735{
3736 u16 tim_idx;
3737 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3738
3739 /*
0c2c8852 3740 * The idx is relative to frame start but we start looking at the
be663ab6
WYG		 3741 * variable-length part of the beacon.
3742 */
3743 tim_idx = mgmt->u.beacon.variable - beacon;
3744
3745 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3746 while ((tim_idx < (frame_size - 2)) &&
e7392364
SG		 3747 (beacon[tim_idx] != WLAN_EID_TIM))
3748 tim_idx += beacon[tim_idx + 1] + 2;
be663ab6
WYG		 3749
3750 /* If TIM field was found, set variables */
3751 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3752 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
e7392364 3753 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
be663ab6 3754 } else
9406f797 3755 IL_WARN("Unable to find TIM Element in beacon\n");
be663ab6
WYG		 3756}
3757
e7392364
SG		 3758static unsigned int
3759il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
be663ab6 3760{
e2ebc833 3761 struct il_tx_beacon_cmd *tx_beacon_cmd;
be663ab6
WYG		 3762 u32 frame_size;
3763 u32 rate_flags;
3764 u32 rate;
3765 /*
3766 * We have to set up the TX command, the TX Beacon command, and the
3767 * beacon contents.
3768 */
3769
46bc8d4b 3770 lockdep_assert_held(&il->mutex);
be663ab6 3771
83007196
SG		 3772 if (!il->beacon_enabled) {
3773 IL_ERR("Trying to build beacon without beaconing enabled\n");
be663ab6
WYG		 3774 return 0;
3775 }
3776
3777 /* Initialize memory */
3778 tx_beacon_cmd = &frame->u.beacon;
3779 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3780
3781 /* Set up TX beacon contents */
e7392364
SG		 3782 frame_size =
3783 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3784 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
be663ab6
WYG		 3785 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3786 return 0;
3787 if (!frame_size)
3788 return 0;
3789
3790 /* Set up TX command fields */
e7392364 3791 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
b16db50a 3792 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
be663ab6 3793 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e7392364
SG		 3794 tx_beacon_cmd->tx.tx_flags =
3795 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3796 TX_CMD_FLG_STA_RATE_MSK;
be663ab6
WYG		 3797
3798 /* Set up TX beacon command fields */
e7392364
SG		 3799 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3800 frame_size);
be663ab6
WYG		 3801
3802 /* Set up packet rate and flags */
83007196 3803 rate = il_get_lowest_plcp(il);
a0c1ef3b 3804 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 3805 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
e2ebc833 3806 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
be663ab6 3807 rate_flags |= RATE_MCS_CCK_MSK;
616107ed 3808 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
be663ab6
WYG		 3809
3810 return sizeof(*tx_beacon_cmd) + frame_size;
3811}
3812
e7392364
SG		 3813int
3814il4965_send_beacon_cmd(struct il_priv *il)
be663ab6 3815{
e2ebc833 3816 struct il_frame *frame;
be663ab6
WYG		 3817 unsigned int frame_size;
3818 int rc;
3819
46bc8d4b 3820 frame = il4965_get_free_frame(il);
be663ab6 3821 if (!frame) {
9406f797 3822 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 3823 "command.\n");
be663ab6
WYG		 3824 return -ENOMEM;
3825 }
3826
46bc8d4b 3827 frame_size = il4965_hw_get_beacon_cmd(il, frame);
be663ab6 3828 if (!frame_size) {
9406f797 3829 IL_ERR("Error configuring the beacon command\n");
46bc8d4b 3830 il4965_free_frame(il, frame);
be663ab6
WYG		 3831 return -EINVAL;
3832 }
3833
e7392364 3834 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
be663ab6 3835
46bc8d4b 3836 il4965_free_frame(il, frame);
be663ab6
WYG		 3837
3838 return rc;
3839}
3840
e7392364
SG		 3841static inline dma_addr_t
3842il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
be663ab6 3843{
e2ebc833 3844 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3845
3846 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3847 if (sizeof(dma_addr_t) > sizeof(u32))
3848 addr |=
e7392364
SG		 3849 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3850 16;
be663ab6
WYG		 3851
3852 return addr;
3853}
3854
e7392364
SG		 3855static inline u16
3856il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
be663ab6 3857{
e2ebc833 3858 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3859
3860 return le16_to_cpu(tb->hi_n_len) >> 4;
3861}
3862
e7392364
SG		 3863static inline void
3864il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
be663ab6 3865{
e2ebc833 3866 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3867 u16 hi_n_len = len << 4;
3868
3869 put_unaligned_le32(addr, &tb->lo);
3870 if (sizeof(dma_addr_t) > sizeof(u32))
3871 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3872
3873 tb->hi_n_len = cpu_to_le16(hi_n_len);
3874
3875 tfd->num_tbs = idx + 1;
3876}
3877
e7392364
SG		 3878static inline u8
3879il4965_tfd_get_num_tbs(struct il_tfd *tfd)
be663ab6
WYG		 3880{
3881 return tfd->num_tbs & 0x1f;
3882}
3883
3884/**
e2ebc833 3885 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
46bc8d4b 3886 * @il - driver ilate data
be663ab6
WYG		 3887 * @txq - tx queue
3888 *
0c2c8852 3889 * Does NOT advance any TFD circular buffer read/write idxes
be663ab6
WYG		 3890 * Does NOT free the TFD itself (which is within circular buffer)
3891 */
e7392364
SG		 3892void
3893il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
be663ab6 3894{
e2ebc833
SG		 3895 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3896 struct il_tfd *tfd;
46bc8d4b 3897 struct pci_dev *dev = il->pci_dev;
0c2c8852 3898 int idx = txq->q.read_ptr;
be663ab6
WYG		 3899 int i;
3900 int num_tbs;
3901
0c2c8852 3902 tfd = &tfd_tmp[idx];
be663ab6
WYG		 3903
3904 /* Sanity check on number of chunks */
e2ebc833 3905 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6 3906
e2ebc833 3907 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3908 IL_ERR("Too many chunks: %i\n", num_tbs);
be663ab6
WYG		 3909 /* @todo issue fatal error, it is quite serious situation */
3910 return;
3911 }
3912
3913 /* Unmap tx_cmd */
3914 if (num_tbs)
e7392364
SG		 3915 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3916 dma_unmap_len(&txq->meta[idx], len),
3917 PCI_DMA_BIDIRECTIONAL);
be663ab6
WYG		 3918
3919 /* Unmap chunks, if any. */
3920 for (i = 1; i < num_tbs; i++)
e2ebc833 3921 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
e7392364
SG		 3922 il4965_tfd_tb_get_len(tfd, i),
3923 PCI_DMA_TODEVICE);
be663ab6
WYG		 3924
3925 /* free SKB */
00ea99e1
SG		 3926 if (txq->skbs) {
3927 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
be663ab6
WYG		 3928
3929 /* can be called from irqs-disabled context */
3930 if (skb) {
3931 dev_kfree_skb_any(skb);
00ea99e1 3932 txq->skbs[txq->q.read_ptr] = NULL;
be663ab6
WYG		 3933 }
3934 }
3935}
3936
e7392364
SG		 3937int
3938il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3939 dma_addr_t addr, u16 len, u8 reset, u8 pad)
be663ab6 3940{
e2ebc833
SG		 3941 struct il_queue *q;
3942 struct il_tfd *tfd, *tfd_tmp;
be663ab6
WYG		 3943 u32 num_tbs;
3944
3945 q = &txq->q;
e2ebc833 3946 tfd_tmp = (struct il_tfd *)txq->tfds;
be663ab6
WYG		 3947 tfd = &tfd_tmp[q->write_ptr];
3948
3949 if (reset)
3950 memset(tfd, 0, sizeof(*tfd));
3951
e2ebc833 3952 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6
WYG		 3953
3954 /* Each TFD can point to a maximum 20 Tx buffers */
e2ebc833 3955 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3956 IL_ERR("Error can not send more than %d chunks\n",
e7392364 3957 IL_NUM_OF_TBS);
be663ab6
WYG		 3958 return -EINVAL;
3959 }
3960
3961 BUG_ON(addr & ~DMA_BIT_MASK(36));
e2ebc833 3962 if (unlikely(addr & ~IL_TX_DMA_MASK))
e7392364 3963 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
be663ab6 3964
e2ebc833 3965 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
be663ab6
WYG		 3966
3967 return 0;
3968}
3969
3970/*
3971 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3972 * given Tx queue, and enable the DMA channel used for that queue.
3973 *
3974 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3975 * channels supported in hardware.
3976 */
e7392364
SG		 3977int
3978il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
be663ab6
WYG		 3979{
3980 int txq_id = txq->q.id;
3981
3982 /* Circular buffer (TFD queue in DRAM) physical base address */
e7392364 3983 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
be663ab6
WYG		 3984
3985 return 0;
3986}
3987
3988/******************************************************************************
3989 *
3990 * Generic RX handler implementations
3991 *
3992 ******************************************************************************/
e7392364
SG		 3993static void
3994il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 3995{
dcae1c64 3996 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 3997 struct il_alive_resp *palive;
be663ab6
WYG		 3998 struct delayed_work *pwork;
3999
4000 palive = &pkt->u.alive_frame;
4001
e7392364
SG		 4002 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
4003 palive->is_valid, palive->ver_type, palive->ver_subtype);
be663ab6
WYG		 4004
4005 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 4006 D_INFO("Initialization Alive received.\n");
e7392364 4007 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 4008 sizeof(struct il_init_alive_resp));
46bc8d4b 4009 pwork = &il->init_alive_start;
be663ab6 4010 } else {
58de00a4 4011 D_INFO("Runtime Alive received.\n");
46bc8d4b 4012 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 4013 sizeof(struct il_alive_resp));
46bc8d4b 4014 pwork = &il->alive_start;
be663ab6
WYG		 4015 }
4016
4017 /* We delay the ALIVE response by 5ms to
4018 * give the HW RF Kill time to activate... */
4019 if (palive->is_valid == UCODE_VALID_OK)
e7392364 4020 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
be663ab6 4021 else
9406f797 4022 IL_WARN("uCode did not respond OK.\n");
be663ab6
WYG		 4023}
4024
4025/**
ebf0d90d 4026 * il4965_bg_stats_periodic - Timer callback to queue stats
be663ab6 4027 *
ebf0d90d 4028 * This callback is provided in order to send a stats request.
be663ab6
WYG		 4029 *
4030 * This timer function is continually reset to execute within
4d69c752 4031 * REG_RECALIB_PERIOD seconds since the last N_STATS
ebf0d90d 4032 * was received. We need to ensure we receive the stats in order
be663ab6
WYG		 4033 * to update the temperature used for calibrating the TXPOWER.
4034 */
e7392364
SG		 4035static void
4036il4965_bg_stats_periodic(unsigned long data)
be663ab6 4037{
46bc8d4b 4038 struct il_priv *il = (struct il_priv *)data;
be663ab6 4039
a6766ccd 4040 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4041 return;
4042
4043 /* dont send host command if rf-kill is on */
46bc8d4b 4044 if (!il_is_ready_rf(il))
be663ab6
WYG		 4045 return;
4046
ebf0d90d 4047 il_send_stats_request(il, CMD_ASYNC, false);
be663ab6
WYG		 4048}
4049
e7392364
SG		 4050static void
4051il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4052{
dcae1c64 4053 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4054 struct il4965_beacon_notif *beacon =
e7392364 4055 (struct il4965_beacon_notif *)pkt->u.raw;
d3175167 4056#ifdef CONFIG_IWLEGACY_DEBUG
e2ebc833 4057 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
be663ab6 4058
5bf0dac4 4059 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
e7392364
SG		 4060 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4061 beacon->beacon_notify_hdr.failure_frame,
4062 le32_to_cpu(beacon->ibss_mgr_status),
4063 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
be663ab6 4064#endif
46bc8d4b 4065 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
be663ab6
WYG		 4066}
4067
e7392364
SG		 4068static void
4069il4965_perform_ct_kill_task(struct il_priv *il)
be663ab6
WYG		 4070{
4071 unsigned long flags;
4072
58de00a4 4073 D_POWER("Stop all queues\n");
be663ab6 4074
46bc8d4b
SG		 4075 if (il->mac80211_registered)
4076 ieee80211_stop_queues(il->hw);
be663ab6 4077
841b2cca 4078 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4079 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
841b2cca 4080 _il_rd(il, CSR_UCODE_DRV_GP1);
be663ab6 4081
46bc8d4b 4082 spin_lock_irqsave(&il->reg_lock, flags);
1e0f32a4 4083 if (likely(_il_grab_nic_access(il)))
13882269 4084 _il_release_nic_access(il);
46bc8d4b 4085 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6
WYG		 4086}
4087
4088/* Handle notification from uCode that card's power state is changing
4089 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG		 4090static void
4091il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4092{
dcae1c64 4093 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4094 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 4095 unsigned long status = il->status;
be663ab6 4096
58de00a4 4097 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
e7392364
SG		 4098 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4099 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4100 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
be663ab6 4101
e7392364 4102 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
be663ab6 4103
841b2cca 4104 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4105 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6 4106
e7392364 4107 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4108
4109 if (!(flags & RXON_CARD_DISABLED)) {
841b2cca 4110 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 4111 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0c1a94e2 4112 il_wr(il, HBUS_TARG_MBX_C,
e7392364 4113 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4114 }
4115 }
4116
4117 if (flags & CT_CARD_DISABLED)
46bc8d4b 4118 il4965_perform_ct_kill_task(il);
be663ab6
WYG		 4119
4120 if (flags & HW_CARD_DISABLED)
a6766ccd 4121 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 4122 else
a6766ccd 4123 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 4124
4125 if (!(flags & RXON_CARD_DISABLED))
46bc8d4b 4126 il_scan_cancel(il);
be663ab6 4127
a6766ccd
SG		 4128 if ((test_bit(S_RF_KILL_HW, &status) !=
4129 test_bit(S_RF_KILL_HW, &il->status)))
46bc8d4b 4130 wiphy_rfkill_set_hw_state(il->hw->wiphy,
e7392364 4131 test_bit(S_RF_KILL_HW, &il->status));
be663ab6 4132 else
46bc8d4b 4133 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4134}
4135
4136/**
d0c72347 4137 * il4965_setup_handlers - Initialize Rx handler callbacks
be663ab6
WYG		 4138 *
4139 * Setup the RX handlers for each of the reply types sent from the uCode
4140 * to the host.
4141 *
4142 * This function chains into the hardware specific files for them to setup
4143 * any hardware specific handlers as well.
4144 */
e7392364
SG		 4145static void
4146il4965_setup_handlers(struct il_priv *il)
be663ab6 4147{
6e9848b4
SG		 4148 il->handlers[N_ALIVE] = il4965_hdl_alive;
4149 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 4150 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 4151 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 4152 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 4153 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 4154 il->handlers[N_BEACON] = il4965_hdl_beacon;
be663ab6
WYG		 4155
4156 /*
4157 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG		 4158 * stats request from the host as well as for the periodic
4159 * stats notifications (after received beacons) from the uCode.
be663ab6 4160 */
d2dfb33e
SG		 4161 il->handlers[C_STATS] = il4965_hdl_c_stats;
4162 il->handlers[N_STATS] = il4965_hdl_stats;
be663ab6 4163
46bc8d4b 4164 il_setup_rx_scan_handlers(il);
be663ab6
WYG		 4165
4166 /* status change handler */
e7392364 4167 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
be663ab6 4168
e7392364 4169 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
be663ab6 4170 /* Rx handlers */
6e9848b4
SG		 4171 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4172 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
3dfea27d 4173 il->handlers[N_RX] = il4965_hdl_rx;
be663ab6 4174 /* block ack */
6e9848b4 4175 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
3dfea27d
SG		 4176 /* Tx response */
4177 il->handlers[C_TX] = il4965_hdl_tx;
be663ab6
WYG		 4178}
4179
4180/**
e2ebc833 4181 * il4965_rx_handle - Main entry function for receiving responses from uCode
be663ab6 4182 *
d0c72347 4183 * Uses the il->handlers callback function array to invoke
be663ab6
WYG		 4184 * the appropriate handlers, including command responses,
4185 * frame-received notifications, and other notifications.
4186 */
e7392364
SG		 4187void
4188il4965_rx_handle(struct il_priv *il)
be663ab6 4189{
b73bb5f1 4190 struct il_rx_buf *rxb;
dcae1c64 4191 struct il_rx_pkt *pkt;
46bc8d4b 4192 struct il_rx_queue *rxq = &il->rxq;
be663ab6
WYG		 4193 u32 r, i;
4194 int reclaim;
4195 unsigned long flags;
4196 u8 fill_rx = 0;
4197 u32 count = 8;
4198 int total_empty;
4199
0c2c8852 4200 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
be663ab6 4201 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 4202 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
be663ab6
WYG		 4203 i = rxq->read;
4204
4205 /* Rx interrupt, but nothing sent from uCode */
4206 if (i == r)
58de00a4 4207 D_RX("r = %d, i = %d\n", r, i);
be663ab6
WYG		 4208
4209 /* calculate total frames need to be restock after handling RX */
4210 total_empty = r - rxq->write_actual;
4211 if (total_empty < 0)
4212 total_empty += RX_QUEUE_SIZE;
4213
4214 if (total_empty > (RX_QUEUE_SIZE / 2))
4215 fill_rx = 1;
4216
4217 while (i != r) {
4218 int len;
4219
4220 rxb = rxq->queue[i];
4221
4222 /* If an RXB doesn't have a Rx queue slot associated with it,
4223 * then a bug has been introduced in the queue refilling
4224 * routines -- catch it here */
4225 BUG_ON(rxb == NULL);
4226
4227 rxq->queue[i] = NULL;
4228
46bc8d4b
SG		 4229 pci_unmap_page(il->pci_dev, rxb->page_dma,
4230 PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 4231 PCI_DMA_FROMDEVICE);
4232 pkt = rxb_addr(rxb);
4233
e94a4099 4234 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 4235 len += sizeof(u32); /* account for status word */
be663ab6
WYG		 4236
4237 /* Reclaim a command buffer only if this packet is a response
4238 * to a (driver-originated) command.
4239 * If the packet (e.g. Rx frame) originated from uCode,
4240 * there is no command buffer to reclaim.
4241 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4242 * but apparently a few don't get set; catch them here. */
4243 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364
SG		 4244 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
4245 (pkt->hdr.cmd != N_RX_MPDU) &&
4246 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
4247 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
be663ab6
WYG		 4248
4249 /* Based on type of command response or notification,
4250 * handle those that need handling via function in
d0c72347
SG		 4251 * handlers table. See il4965_setup_handlers() */
4252 if (il->handlers[pkt->hdr.cmd]) {
e7392364
SG		 4253 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4254 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG		 4255 il->isr_stats.handlers[pkt->hdr.cmd]++;
4256 il->handlers[pkt->hdr.cmd] (il, rxb);
be663ab6
WYG		 4257 } else {
4258 /* No handling needed */
e7392364
SG		 4259 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4260 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
be663ab6
WYG		 4261 }
4262
4263 /*
4264 * XXX: After here, we should always check rxb->page
4265 * against NULL before touching it or its virtual
d0c72347 4266 * memory (pkt). Because some handler might have
be663ab6
WYG		 4267 * already taken or freed the pages.
4268 */
4269
4270 if (reclaim) {
4271 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 4272 * and fire off the (possibly) blocking il_send_cmd()
be663ab6
WYG		 4273 * as we reclaim the driver command queue */
4274 if (rxb->page)
46bc8d4b 4275 il_tx_cmd_complete(il, rxb);
be663ab6 4276 else
9406f797 4277 IL_WARN("Claim null rxb?\n");
be663ab6
WYG		 4278 }
4279
4280 /* Reuse the page if possible. For notification packets and
4281 * SKBs that fail to Rx correctly, add them back into the
4282 * rx_free list for reuse later. */
4283 spin_lock_irqsave(&rxq->lock, flags);
4284 if (rxb->page != NULL) {
e7392364
SG		 4285 rxb->page_dma =
4286 pci_map_page(il->pci_dev, rxb->page, 0,
4287 PAGE_SIZE << il->hw_params.
4288 rx_page_order, PCI_DMA_FROMDEVICE);
be663ab6
WYG		 4289 list_add_tail(&rxb->list, &rxq->rx_free);
4290 rxq->free_count++;
4291 } else
4292 list_add_tail(&rxb->list, &rxq->rx_used);
4293
4294 spin_unlock_irqrestore(&rxq->lock, flags);
4295
4296 i = (i + 1) & RX_QUEUE_MASK;
4297 /* If there are a lot of unused frames,
4298 * restock the Rx queue so ucode wont assert. */
4299 if (fill_rx) {
4300 count++;
4301 if (count >= 8) {
4302 rxq->read = i;
46bc8d4b 4303 il4965_rx_replenish_now(il);
be663ab6
WYG		 4304 count = 0;
4305 }
4306 }
4307 }
4308
4309 /* Backtrack one entry */
4310 rxq->read = i;
4311 if (fill_rx)
46bc8d4b 4312 il4965_rx_replenish_now(il);
be663ab6 4313 else
46bc8d4b 4314 il4965_rx_queue_restock(il);
be663ab6
WYG		 4315}
4316
4317/* call this function to flush any scheduled tasklet */
e7392364
SG		 4318static inline void
4319il4965_synchronize_irq(struct il_priv *il)
be663ab6 4320{
e7392364 4321 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG		 4322 synchronize_irq(il->pci_dev->irq);
4323 tasklet_kill(&il->irq_tasklet);
be663ab6
WYG		 4324}
4325
e7392364
SG		 4326static void
4327il4965_irq_tasklet(struct il_priv *il)
be663ab6
WYG		 4328{
4329 u32 inta, handled = 0;
4330 u32 inta_fh;
4331 unsigned long flags;
4332 u32 i;
d3175167 4333#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4334 u32 inta_mask;
4335#endif
4336
46bc8d4b 4337 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4338
4339 /* Ack/clear/reset pending uCode interrupts.
4340 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4341 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG		 4342 inta = _il_rd(il, CSR_INT);
4343 _il_wr(il, CSR_INT, inta);
be663ab6
WYG		 4344
4345 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4346 * Any new interrupts that happen after this, either while we're
4347 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG		 4348 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4349 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
be663ab6 4350
d3175167 4351#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4352 if (il_get_debug_level(il) & IL_DL_ISR) {
be663ab6 4353 /* just for debug */
841b2cca 4354 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG		 4355 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4356 inta_mask, inta_fh);
be663ab6
WYG		 4357 }
4358#endif
4359
46bc8d4b 4360 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4361
4362 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4363 * atomic, make sure that inta covers all the interrupts that
4364 * we've discovered, even if FH interrupt came in just after
4365 * reading CSR_INT. */
4366 if (inta_fh & CSR49_FH_INT_RX_MASK)
4367 inta |= CSR_INT_BIT_FH_RX;
4368 if (inta_fh & CSR49_FH_INT_TX_MASK)
4369 inta |= CSR_INT_BIT_FH_TX;
4370
4371 /* Now service all interrupt bits discovered above. */
4372 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 4373 IL_ERR("Hardware error detected. Restarting.\n");
be663ab6
WYG		 4374
4375 /* Tell the device to stop sending interrupts */
46bc8d4b 4376 il_disable_interrupts(il);
be663ab6 4377
46bc8d4b
SG		 4378 il->isr_stats.hw++;
4379 il_irq_handle_error(il);
be663ab6
WYG		 4380
4381 handled |= CSR_INT_BIT_HW_ERR;
4382
4383 return;
4384 }
d3175167 4385#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4386 if (il_get_debug_level(il) & (IL_DL_ISR)) {
be663ab6
WYG		 4387 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4388 if (inta & CSR_INT_BIT_SCD) {
58de00a4 4389 D_ISR("Scheduler finished to transmit "
e7392364 4390 "the frame/frames.\n");
46bc8d4b 4391 il->isr_stats.sch++;
be663ab6
WYG		 4392 }
4393
4394 /* Alive notification via Rx interrupt will do the real work */
4395 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 4396 D_ISR("Alive interrupt\n");
46bc8d4b 4397 il->isr_stats.alive++;
be663ab6
WYG		 4398 }
4399 }
4400#endif
4401 /* Safely ignore these bits for debug checks below */
4402 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4403
4404 /* HW RF KILL switch toggled */
4405 if (inta & CSR_INT_BIT_RF_KILL) {
4406 int hw_rf_kill = 0;
e7392364
SG		 4407 if (!
4408 (_il_rd(il, CSR_GP_CNTRL) &
4409 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4410 hw_rf_kill = 1;
4411
9406f797 4412 IL_WARN("RF_KILL bit toggled to %s.\n",
e7392364 4413 hw_rf_kill ? "disable radio" : "enable radio");
be663ab6 4414
46bc8d4b 4415 il->isr_stats.rfkill++;
be663ab6
WYG		 4416
4417 /* driver only loads ucode once setting the interface up.
4418 * the driver allows loading the ucode even if the radio
4419 * is killed. Hence update the killswitch state here. The
4420 * rfkill handler will care about restarting if needed.
4421 */
a6766ccd 4422 if (!test_bit(S_ALIVE, &il->status)) {
be663ab6 4423 if (hw_rf_kill)
a6766ccd 4424 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 4425 else
a6766ccd 4426 clear_bit(S_RF_KILL_HW, &il->status);
46bc8d4b 4427 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
be663ab6
WYG		 4428 }
4429
4430 handled |= CSR_INT_BIT_RF_KILL;
4431 }
4432
4433 /* Chip got too hot and stopped itself */
4434 if (inta & CSR_INT_BIT_CT_KILL) {
9406f797 4435 IL_ERR("Microcode CT kill error detected.\n");
46bc8d4b 4436 il->isr_stats.ctkill++;
be663ab6
WYG		 4437 handled |= CSR_INT_BIT_CT_KILL;
4438 }
4439
4440 /* Error detected by uCode */
4441 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG		 4442 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4443 inta);
46bc8d4b
SG		 4444 il->isr_stats.sw++;
4445 il_irq_handle_error(il);
be663ab6
WYG		 4446 handled |= CSR_INT_BIT_SW_ERR;
4447 }
4448
4449 /*
4450 * uCode wakes up after power-down sleep.
4451 * Tell device about any new tx or host commands enqueued,
4452 * and about any Rx buffers made available while asleep.
4453 */
4454 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 4455 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG		 4456 il_rx_queue_update_write_ptr(il, &il->rxq);
4457 for (i = 0; i < il->hw_params.max_txq_num; i++)
4458 il_txq_update_write_ptr(il, &il->txq[i]);
4459 il->isr_stats.wakeup++;
be663ab6
WYG		 4460 handled |= CSR_INT_BIT_WAKEUP;
4461 }
4462
4463 /* All uCode command responses, including Tx command responses,
4464 * Rx "responses" (frame-received notification), and other
4465 * notifications from uCode come through here*/
4466 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG		 4467 il4965_rx_handle(il);
4468 il->isr_stats.rx++;
be663ab6
WYG		 4469 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4470 }
4471
4472 /* This "Tx" DMA channel is used only for loading uCode */
4473 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 4474 D_ISR("uCode load interrupt\n");
46bc8d4b 4475 il->isr_stats.tx++;
be663ab6
WYG		 4476 handled |= CSR_INT_BIT_FH_TX;
4477 /* Wake up uCode load routine, now that load is complete */
46bc8d4b
SG		 4478 il->ucode_write_complete = 1;
4479 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4480 }
4481
4482 if (inta & ~handled) {
9406f797 4483 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 4484 il->isr_stats.unhandled++;
be663ab6
WYG		 4485 }
4486
46bc8d4b 4487 if (inta & ~(il->inta_mask)) {
9406f797 4488 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 4489 inta & ~il->inta_mask);
9a95b370 4490 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
be663ab6
WYG		 4491 }
4492
4493 /* Re-enable all interrupts */
93fd74e3 4494 /* only Re-enable if disabled by irq */
a6766ccd 4495 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 4496 il_enable_interrupts(il);
a078a1fd
SG		 4497 /* Re-enable RF_KILL if it occurred */
4498 else if (handled & CSR_INT_BIT_RF_KILL)
46bc8d4b 4499 il_enable_rfkill_int(il);
be663ab6 4500
d3175167 4501#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4502 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG		 4503 inta = _il_rd(il, CSR_INT);
4504 inta_mask = _il_rd(il, CSR_INT_MASK);
4505 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
e7392364
SG		 4506 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4507 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
be663ab6
WYG		 4508 }
4509#endif
4510}
4511
4512/*****************************************************************************
4513 *
4514 * sysfs attributes
4515 *
4516 *****************************************************************************/
4517
d3175167 4518#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4519
4520/*
4521 * The following adds a new attribute to the sysfs representation
4522 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4523 * used for controlling the debug level.
4524 *
4525 * See the level definitions in iwl for details.
4526 *
4527 * The debug_level being managed using sysfs below is a per device debug
4528 * level that is used instead of the global debug level if it (the per
4529 * device debug level) is set.
4530 */
e7392364
SG		 4531static ssize_t
4532il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4533 char *buf)
be663ab6 4534{
46bc8d4b
SG		 4535 struct il_priv *il = dev_get_drvdata(d);
4536 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
be663ab6 4537}
e7392364
SG		 4538
4539static ssize_t
4540il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4541 const char *buf, size_t count)
be663ab6 4542{
46bc8d4b 4543 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4544 unsigned long val;
4545 int ret;
4546
4547 ret = strict_strtoul(buf, 0, &val);
4548 if (ret)
9406f797 4549 IL_ERR("%s is not in hex or decimal form.\n", buf);
be663ab6 4550 else {
46bc8d4b
SG		 4551 il->debug_level = val;
4552 if (il_alloc_traffic_mem(il))
e7392364 4553 IL_ERR("Not enough memory to generate traffic log\n");
be663ab6
WYG		 4554 }
4555 return strnlen(buf, count);
4556}
4557
e7392364
SG		 4558static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4559 il4965_store_debug_level);
be663ab6 4560
d3175167 4561#endif /* CONFIG_IWLEGACY_DEBUG */
be663ab6 4562
e7392364
SG		 4563static ssize_t
4564il4965_show_temperature(struct device *d, struct device_attribute *attr,
4565 char *buf)
be663ab6 4566{
46bc8d4b 4567 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4568
46bc8d4b 4569 if (!il_is_alive(il))
be663ab6
WYG		 4570 return -EAGAIN;
4571
46bc8d4b 4572 return sprintf(buf, "%d\n", il->temperature);
be663ab6
WYG		 4573}
4574
e2ebc833 4575static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
be663ab6 4576
e7392364
SG		 4577static ssize_t
4578il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
be663ab6 4579{
46bc8d4b 4580 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4581
46bc8d4b 4582 if (!il_is_ready_rf(il))
be663ab6
WYG		 4583 return sprintf(buf, "off\n");
4584 else
46bc8d4b 4585 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
be663ab6
WYG		 4586}
4587
e7392364
SG		 4588static ssize_t
4589il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4590 const char *buf, size_t count)
be663ab6 4591{
46bc8d4b 4592 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4593 unsigned long val;
4594 int ret;
4595
4596 ret = strict_strtoul(buf, 10, &val);
4597 if (ret)
9406f797 4598 IL_INFO("%s is not in decimal form.\n", buf);
be663ab6 4599 else {
46bc8d4b 4600 ret = il_set_tx_power(il, val, false);
be663ab6 4601 if (ret)
e7392364 4602 IL_ERR("failed setting tx power (0x%d).\n", ret);
be663ab6
WYG		 4603 else
4604 ret = count;
4605 }
4606 return ret;
4607}
4608
e7392364
SG		 4609static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4610 il4965_store_tx_power);
be663ab6 4611
e2ebc833 4612static struct attribute *il_sysfs_entries[] = {
be663ab6
WYG		 4613 &dev_attr_temperature.attr,
4614 &dev_attr_tx_power.attr,
d3175167 4615#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4616 &dev_attr_debug_level.attr,
4617#endif
4618 NULL
4619};
4620
e2ebc833 4621static struct attribute_group il_attribute_group = {
be663ab6 4622 .name = NULL, /* put in device directory */
e2ebc833 4623 .attrs = il_sysfs_entries,
be663ab6
WYG		 4624};
4625
4626/******************************************************************************
4627 *
4628 * uCode download functions
4629 *
4630 ******************************************************************************/
4631
e7392364
SG		 4632static void
4633il4965_dealloc_ucode_pci(struct il_priv *il)
be663ab6 4634{
46bc8d4b
SG		 4635 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4636 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4637 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4638 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4639 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4640 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6
WYG		 4641}
4642
e7392364
SG		 4643static void
4644il4965_nic_start(struct il_priv *il)
be663ab6
WYG		 4645{
4646 /* Remove all resets to allow NIC to operate */
841b2cca 4647 _il_wr(il, CSR_RESET, 0);
be663ab6
WYG		 4648}
4649
e2ebc833 4650static void il4965_ucode_callback(const struct firmware *ucode_raw,
e7392364
SG		 4651 void *context);
4652static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
be663ab6 4653
e7392364
SG		 4654static int __must_check
4655il4965_request_firmware(struct il_priv *il, bool first)
be663ab6 4656{
46bc8d4b 4657 const char *name_pre = il->cfg->fw_name_pre;
be663ab6
WYG		 4658 char tag[8];
4659
4660 if (first) {
0c2c8852
SG		 4661 il->fw_idx = il->cfg->ucode_api_max;
4662 sprintf(tag, "%d", il->fw_idx);
be663ab6 4663 } else {
0c2c8852
SG		 4664 il->fw_idx--;
4665 sprintf(tag, "%d", il->fw_idx);
be663ab6
WYG		 4666 }
4667
0c2c8852 4668 if (il->fw_idx < il->cfg->ucode_api_min) {
9406f797 4669 IL_ERR("no suitable firmware found!\n");
be663ab6
WYG		 4670 return -ENOENT;
4671 }
4672
46bc8d4b 4673 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
be663ab6 4674
e7392364 4675 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
be663ab6 4676
46bc8d4b
SG		 4677 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4678 &il->pci_dev->dev, GFP_KERNEL, il,
e2ebc833 4679 il4965_ucode_callback);
be663ab6
WYG		 4680}
4681
e2ebc833 4682struct il4965_firmware_pieces {
be663ab6
WYG		 4683 const void *inst, *data, *init, *init_data, *boot;
4684 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4685};
4686
e7392364
SG		 4687static int
4688il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4689 struct il4965_firmware_pieces *pieces)
be663ab6 4690{
e2ebc833 4691 struct il_ucode_header *ucode = (void *)ucode_raw->data;
be663ab6
WYG		 4692 u32 api_ver, hdr_size;
4693 const u8 *src;
4694
46bc8d4b
SG		 4695 il->ucode_ver = le32_to_cpu(ucode->ver);
4696 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4697
4698 switch (api_ver) {
4699 default:
4700 case 0:
4701 case 1:
4702 case 2:
4703 hdr_size = 24;
4704 if (ucode_raw->size < hdr_size) {
9406f797 4705 IL_ERR("File size too small!\n");
be663ab6
WYG		 4706 return -EINVAL;
4707 }
4708 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4709 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4710 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
e7392364 4711 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
be663ab6
WYG		 4712 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4713 src = ucode->v1.data;
4714 break;
4715 }
4716
4717 /* Verify size of file vs. image size info in file's header */
e7392364
SG		 4718 if (ucode_raw->size !=
4719 hdr_size + pieces->inst_size + pieces->data_size +
4720 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
be663ab6 4721
e7392364
SG		 4722 IL_ERR("uCode file size %d does not match expected size\n",
4723 (int)ucode_raw->size);
be663ab6
WYG		 4724 return -EINVAL;
4725 }
4726
4727 pieces->inst = src;
4728 src += pieces->inst_size;
4729 pieces->data = src;
4730 src += pieces->data_size;
4731 pieces->init = src;
4732 src += pieces->init_size;
4733 pieces->init_data = src;
4734 src += pieces->init_data_size;
4735 pieces->boot = src;
4736 src += pieces->boot_size;
4737
4738 return 0;
4739}
4740
4741/**
e2ebc833 4742 * il4965_ucode_callback - callback when firmware was loaded
be663ab6
WYG		 4743 *
4744 * If loaded successfully, copies the firmware into buffers
4745 * for the card to fetch (via DMA).
4746 */
4747static void
e2ebc833 4748il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
be663ab6 4749{
46bc8d4b 4750 struct il_priv *il = context;
e2ebc833 4751 struct il_ucode_header *ucode;
be663ab6 4752 int err;
e2ebc833 4753 struct il4965_firmware_pieces pieces;
46bc8d4b
SG		 4754 const unsigned int api_max = il->cfg->ucode_api_max;
4755 const unsigned int api_min = il->cfg->ucode_api_min;
be663ab6
WYG		 4756 u32 api_ver;
4757
4758 u32 max_probe_length = 200;
4759 u32 standard_phy_calibration_size =
e7392364 4760 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
be663ab6
WYG		 4761
4762 memset(&pieces, 0, sizeof(pieces));
4763
4764 if (!ucode_raw) {
0c2c8852 4765 if (il->fw_idx <= il->cfg->ucode_api_max)
e7392364
SG		 4766 IL_ERR("request for firmware file '%s' failed.\n",
4767 il->firmware_name);
be663ab6
WYG		 4768 goto try_again;
4769 }
4770
e7392364
SG		 4771 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4772 ucode_raw->size);
be663ab6
WYG		 4773
4774 /* Make sure that we got at least the API version number */
4775 if (ucode_raw->size < 4) {
9406f797 4776 IL_ERR("File size way too small!\n");
be663ab6
WYG		 4777 goto try_again;
4778 }
4779
4780 /* Data from ucode file: header followed by uCode images */
e2ebc833 4781 ucode = (struct il_ucode_header *)ucode_raw->data;
be663ab6 4782
46bc8d4b 4783 err = il4965_load_firmware(il, ucode_raw, &pieces);
be663ab6
WYG		 4784
4785 if (err)
4786 goto try_again;
4787
46bc8d4b 4788 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4789
4790 /*
4791 * api_ver should match the api version forming part of the
4792 * firmware filename ... but we don't check for that and only rely
4793 * on the API version read from firmware header from here on forward
4794 */
4795 if (api_ver < api_min || api_ver > api_max) {
e7392364
SG		 4796 IL_ERR("Driver unable to support your firmware API. "
4797 "Driver supports v%u, firmware is v%u.\n", api_max,
4798 api_ver);
be663ab6
WYG		 4799 goto try_again;
4800 }
4801
4802 if (api_ver != api_max)
e7392364
SG		 4803 IL_ERR("Firmware has old API version. Expected v%u, "
4804 "got v%u. New firmware can be obtained "
4805 "from http://www.intellinuxwireless.org.\n", api_max,
4806 api_ver);
be663ab6 4807
9406f797 4808 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG		 4809 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4810 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
be663ab6 4811
e7392364
SG		 4812 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4813 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4814 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
46bc8d4b 4815 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6
WYG		 4816
4817 /*
4818 * For any of the failures below (before allocating pci memory)
4819 * we will try to load a version with a smaller API -- maybe the
4820 * user just got a corrupted version of the latest API.
4821 */
4822
e7392364
SG		 4823 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4824 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4825 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4826 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4827 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4828 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
be663ab6
WYG		 4829
4830 /* Verify that uCode images will fit in card's SRAM */
46bc8d4b 4831 if (pieces.inst_size > il->hw_params.max_inst_size) {
9406f797 4832 IL_ERR("uCode instr len %Zd too large to fit in\n",
e7392364 4833 pieces.inst_size);
be663ab6
WYG		 4834 goto try_again;
4835 }
4836
46bc8d4b 4837 if (pieces.data_size > il->hw_params.max_data_size) {
9406f797 4838 IL_ERR("uCode data len %Zd too large to fit in\n",
e7392364 4839 pieces.data_size);
be663ab6
WYG		 4840 goto try_again;
4841 }
4842
46bc8d4b 4843 if (pieces.init_size > il->hw_params.max_inst_size) {
9406f797 4844 IL_ERR("uCode init instr len %Zd too large to fit in\n",
e7392364 4845 pieces.init_size);
be663ab6
WYG		 4846 goto try_again;
4847 }
4848
46bc8d4b 4849 if (pieces.init_data_size > il->hw_params.max_data_size) {
9406f797 4850 IL_ERR("uCode init data len %Zd too large to fit in\n",
e7392364 4851 pieces.init_data_size);
be663ab6
WYG		 4852 goto try_again;
4853 }
4854
46bc8d4b 4855 if (pieces.boot_size > il->hw_params.max_bsm_size) {
9406f797 4856 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
e7392364 4857 pieces.boot_size);
be663ab6
WYG		 4858 goto try_again;
4859 }
4860
4861 /* Allocate ucode buffers for card's bus-master loading ... */
4862
4863 /* Runtime instructions and 2 copies of data:
4864 * 1) unmodified from disk
4865 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG		 4866 il->ucode_code.len = pieces.inst_size;
4867 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
be663ab6 4868
46bc8d4b
SG		 4869 il->ucode_data.len = pieces.data_size;
4870 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
be663ab6 4871
46bc8d4b
SG		 4872 il->ucode_data_backup.len = pieces.data_size;
4873 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
be663ab6 4874
46bc8d4b
SG		 4875 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4876 !il->ucode_data_backup.v_addr)
be663ab6
WYG		 4877 goto err_pci_alloc;
4878
4879 /* Initialization instructions and data */
4880 if (pieces.init_size && pieces.init_data_size) {
46bc8d4b
SG		 4881 il->ucode_init.len = pieces.init_size;
4882 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
be663ab6 4883
46bc8d4b
SG		 4884 il->ucode_init_data.len = pieces.init_data_size;
4885 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
be663ab6 4886
46bc8d4b 4887 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
be663ab6
WYG		 4888 goto err_pci_alloc;
4889 }
4890
4891 /* Bootstrap (instructions only, no data) */
4892 if (pieces.boot_size) {
46bc8d4b
SG		 4893 il->ucode_boot.len = pieces.boot_size;
4894 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6 4895
46bc8d4b 4896 if (!il->ucode_boot.v_addr)
be663ab6
WYG		 4897 goto err_pci_alloc;
4898 }
4899
4900 /* Now that we can no longer fail, copy information */
4901
46bc8d4b 4902 il->sta_key_max_num = STA_KEY_MAX_NUM;
be663ab6
WYG		 4903
4904 /* Copy images into buffers for card's bus-master reads ... */
4905
4906 /* Runtime instructions (first block of data in file) */
58de00a4 4907 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
e7392364 4908 pieces.inst_size);
46bc8d4b 4909 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
be663ab6 4910
58de00a4 4911 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 4912 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
be663ab6
WYG		 4913
4914 /*
4915 * Runtime data
e2ebc833 4916 * NOTE: Copy into backup buffer will be done in il_up()
be663ab6 4917 */
58de00a4 4918 D_INFO("Copying (but not loading) uCode data len %Zd\n",
e7392364 4919 pieces.data_size);
46bc8d4b
SG		 4920 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4921 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
be663ab6
WYG		 4922
4923 /* Initialization instructions */
4924 if (pieces.init_size) {
e7392364
SG		 4925 D_INFO("Copying (but not loading) init instr len %Zd\n",
4926 pieces.init_size);
46bc8d4b 4927 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
be663ab6
WYG		 4928 }
4929
4930 /* Initialization data */
4931 if (pieces.init_data_size) {
e7392364
SG		 4932 D_INFO("Copying (but not loading) init data len %Zd\n",
4933 pieces.init_data_size);
46bc8d4b 4934 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
be663ab6
WYG		 4935 pieces.init_data_size);
4936 }
4937
4938 /* Bootstrap instructions */
58de00a4 4939 D_INFO("Copying (but not loading) boot instr len %Zd\n",
e7392364 4940 pieces.boot_size);
46bc8d4b 4941 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
be663ab6
WYG		 4942
4943 /*
4944 * figure out the offset of chain noise reset and gain commands
4945 * base on the size of standard phy calibration commands table size
4946 */
46bc8d4b 4947 il->_4965.phy_calib_chain_noise_reset_cmd =
e7392364 4948 standard_phy_calibration_size;
46bc8d4b 4949 il->_4965.phy_calib_chain_noise_gain_cmd =
e7392364 4950 standard_phy_calibration_size + 1;
be663ab6
WYG		 4951
4952 /**************************************************
4953 * This is still part of probe() in a sense...
4954 *
4955 * 9. Setup and register with mac80211 and debugfs
4956 **************************************************/
46bc8d4b 4957 err = il4965_mac_setup_register(il, max_probe_length);
be663ab6
WYG		 4958 if (err)
4959 goto out_unbind;
4960
46bc8d4b 4961 err = il_dbgfs_register(il, DRV_NAME);
be663ab6 4962 if (err)
e7392364
SG		 4963 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4964 err);
be663ab6 4965
e7392364 4966 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
be663ab6 4967 if (err) {
9406f797 4968 IL_ERR("failed to create sysfs device attributes\n");
be663ab6
WYG		 4969 goto out_unbind;
4970 }
4971
4972 /* We have our copies now, allow OS release its copies */
4973 release_firmware(ucode_raw);
46bc8d4b 4974 complete(&il->_4965.firmware_loading_complete);
be663ab6
WYG		 4975 return;
4976
e7392364 4977try_again:
be663ab6 4978 /* try next, if any */
46bc8d4b 4979 if (il4965_request_firmware(il, false))
be663ab6
WYG		 4980 goto out_unbind;
4981 release_firmware(ucode_raw);
4982 return;
4983
e7392364 4984err_pci_alloc:
9406f797 4985 IL_ERR("failed to allocate pci memory\n");
46bc8d4b 4986 il4965_dealloc_ucode_pci(il);
e7392364 4987out_unbind:
46bc8d4b
SG		 4988 complete(&il->_4965.firmware_loading_complete);
4989 device_release_driver(&il->pci_dev->dev);
be663ab6
WYG		 4990 release_firmware(ucode_raw);
4991}
4992
e7392364 4993static const char *const desc_lookup_text[] = {
be663ab6
WYG		 4994 "OK",
4995 "FAIL",
4996 "BAD_PARAM",
4997 "BAD_CHECKSUM",
4998 "NMI_INTERRUPT_WDG",
4999 "SYSASSERT",
5000 "FATAL_ERROR",
5001 "BAD_COMMAND",
5002 "HW_ERROR_TUNE_LOCK",
5003 "HW_ERROR_TEMPERATURE",
5004 "ILLEGAL_CHAN_FREQ",
3b98c7f4 5005 "VCC_NOT_STBL",
9a95b370 5006 "FH49_ERROR",
be663ab6
WYG		 5007 "NMI_INTERRUPT_HOST",
5008 "NMI_INTERRUPT_ACTION_PT",
5009 "NMI_INTERRUPT_UNKNOWN",
5010 "UCODE_VERSION_MISMATCH",
5011 "HW_ERROR_ABS_LOCK",
5012 "HW_ERROR_CAL_LOCK_FAIL",
5013 "NMI_INTERRUPT_INST_ACTION_PT",
5014 "NMI_INTERRUPT_DATA_ACTION_PT",
5015 "NMI_TRM_HW_ER",
5016 "NMI_INTERRUPT_TRM",
861d9c3f 5017 "NMI_INTERRUPT_BREAK_POINT",
be663ab6
WYG		 5018 "DEBUG_0",
5019 "DEBUG_1",
5020 "DEBUG_2",
5021 "DEBUG_3",
5022};
5023
e7392364
SG		 5024static struct {
5025 char *name;
5026 u8 num;
5027} advanced_lookup[] = {
5028 {
5029 "NMI_INTERRUPT_WDG", 0x34}, {
5030 "SYSASSERT", 0x35}, {
5031 "UCODE_VERSION_MISMATCH", 0x37}, {
5032 "BAD_COMMAND", 0x38}, {
5033 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5034 "FATAL_ERROR", 0x3D}, {
5035 "NMI_TRM_HW_ERR", 0x46}, {
5036 "NMI_INTERRUPT_TRM", 0x4C}, {
5037 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5038 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5039 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5040 "NMI_INTERRUPT_HOST", 0x66}, {
5041 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5042 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5043 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5044"ADVANCED_SYSASSERT", 0},};
5045
5046static const char *
5047il4965_desc_lookup(u32 num)
be663ab6
WYG		 5048{
5049 int i;
5050 int max = ARRAY_SIZE(desc_lookup_text);
5051
5052 if (num < max)
5053 return desc_lookup_text[num];
5054
5055 max = ARRAY_SIZE(advanced_lookup) - 1;
5056 for (i = 0; i < max; i++) {
5057 if (advanced_lookup[i].num == num)
5058 break;
5059 }
5060 return advanced_lookup[i].name;
5061}
5062
5063#define ERROR_START_OFFSET (1 * sizeof(u32))
5064#define ERROR_ELEM_SIZE (7 * sizeof(u32))
5065
e7392364
SG		 5066void
5067il4965_dump_nic_error_log(struct il_priv *il)
be663ab6
WYG		 5068{
5069 u32 data2, line;
5070 u32 desc, time, count, base, data1;
5071 u32 blink1, blink2, ilink1, ilink2;
5072 u32 pc, hcmd;
5073
1722f8e1 5074 if (il->ucode_type == UCODE_INIT)
46bc8d4b 5075 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
1722f8e1 5076 else
46bc8d4b 5077 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
be663ab6 5078
c39ae9fd 5079 if (!il->ops->lib->is_valid_rtc_data_addr(base)) {
e7392364
SG		 5080 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5081 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
be663ab6
WYG		 5082 return;
5083 }
5084
46bc8d4b 5085 count = il_read_targ_mem(il, base);
be663ab6
WYG		 5086
5087 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 5088 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 5089 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
46bc8d4b
SG		 5090 }
5091
5092 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5093 il->isr_stats.err_code = desc;
5094 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5095 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5096 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5097 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5098 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5099 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5100 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5101 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5102 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5103 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5104
9406f797 5105 IL_ERR("Desc Time "
e7392364 5106 "data1 data2 line\n");
9406f797 5107 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
e7392364 5108 il4965_desc_lookup(desc), desc, time, data1, data2, line);
9406f797 5109 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
e7392364
SG		 5110 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5111 blink2, ilink1, ilink2, hcmd);
be663ab6
WYG		 5112}
5113
e7392364
SG		 5114static void
5115il4965_rf_kill_ct_config(struct il_priv *il)
be663ab6 5116{
e2ebc833 5117 struct il_ct_kill_config cmd;
be663ab6
WYG		 5118 unsigned long flags;
5119 int ret = 0;
5120
46bc8d4b 5121 spin_lock_irqsave(&il->lock, flags);
841b2cca 5122 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 5123 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
46bc8d4b 5124 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5125
5126 cmd.critical_temperature_R =
e7392364 5127 cpu_to_le32(il->hw_params.ct_kill_threshold);
be663ab6 5128
e7392364 5129 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
be663ab6 5130 if (ret)
4d69c752 5131 IL_ERR("C_CT_KILL_CONFIG failed\n");
be663ab6 5132 else
e7392364
SG		 5133 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5134 "critical temperature is %d\n",
5135 il->hw_params.ct_kill_threshold);
be663ab6
WYG		 5136}
5137
5138static const s8 default_queue_to_tx_fifo[] = {
e2ebc833
SG		 5139 IL_TX_FIFO_VO,
5140 IL_TX_FIFO_VI,
5141 IL_TX_FIFO_BE,
5142 IL_TX_FIFO_BK,
d3175167 5143 IL49_CMD_FIFO_NUM,
e2ebc833
SG		 5144 IL_TX_FIFO_UNUSED,
5145 IL_TX_FIFO_UNUSED,
be663ab6
WYG		 5146};
5147
e53aac42
SG		 5148#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5149
e7392364
SG		 5150static int
5151il4965_alive_notify(struct il_priv *il)
be663ab6
WYG		 5152{
5153 u32 a;
5154 unsigned long flags;
5155 int i, chan;
5156 u32 reg_val;
5157
46bc8d4b 5158 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5159
5160 /* Clear 4965's internal Tx Scheduler data base */
e7392364 5161 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
d3175167
SG		 5162 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5163 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
46bc8d4b 5164 il_write_targ_mem(il, a, 0);
d3175167 5165 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
46bc8d4b 5166 il_write_targ_mem(il, a, 0);
e7392364
SG		 5167 for (;
5168 a <
5169 il->scd_base_addr +
5170 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5171 a += 4)
46bc8d4b 5172 il_write_targ_mem(il, a, 0);
be663ab6
WYG		 5173
5174 /* Tel 4965 where to find Tx byte count tables */
e7392364 5175 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
be663ab6
WYG		 5176
5177 /* Enable DMA channel */
e7392364
SG		 5178 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5179 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5180 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5181 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
be663ab6
WYG		 5182
5183 /* Update FH chicken bits */
9a95b370
SG		 5184 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5185 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
e7392364 5186 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
be663ab6
WYG		 5187
5188 /* Disable chain mode for all queues */
d3175167 5189 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
be663ab6
WYG		 5190
5191 /* Initialize each Tx queue (including the command queue) */
46bc8d4b 5192 for (i = 0; i < il->hw_params.max_txq_num; i++) {
be663ab6 5193
0c2c8852 5194 /* TFD circular buffer read/write idxes */
d3175167 5195 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
0c1a94e2 5196 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
be663ab6
WYG		 5197
5198 /* Max Tx Window size for Scheduler-ACK mode */
e7392364
SG		 5199 il_write_targ_mem(il,
5200 il->scd_base_addr +
5201 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5202 (SCD_WIN_SIZE <<
5203 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5204 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
be663ab6
WYG		 5205
5206 /* Frame limit */
e7392364
SG		 5207 il_write_targ_mem(il,
5208 il->scd_base_addr +
5209 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5210 sizeof(u32),
5211 (SCD_FRAME_LIMIT <<
5212 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5213 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
be663ab6
WYG		 5214
5215 }
d3175167 5216 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
e7392364 5217 (1 << il->hw_params.max_txq_num) - 1);
be663ab6
WYG		 5218
5219 /* Activate all Tx DMA/FIFO channels */
46bc8d4b 5220 il4965_txq_set_sched(il, IL_MASK(0, 6));
be663ab6 5221
46bc8d4b 5222 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
be663ab6
WYG		 5223
5224 /* make sure all queue are not stopped */
46bc8d4b 5225 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
be663ab6 5226 for (i = 0; i < 4; i++)
46bc8d4b 5227 atomic_set(&il->queue_stop_count[i], 0);
be663ab6
WYG		 5228
5229 /* reset to 0 to enable all the queue first */
46bc8d4b 5230 il->txq_ctx_active_msk = 0;
be663ab6
WYG		 5231 /* Map each Tx/cmd queue to its corresponding fifo */
5232 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5233
5234 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5235 int ac = default_queue_to_tx_fifo[i];
5236
46bc8d4b 5237 il_txq_ctx_activate(il, i);
be663ab6 5238
e2ebc833 5239 if (ac == IL_TX_FIFO_UNUSED)
be663ab6
WYG		 5240 continue;
5241
46bc8d4b 5242 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
be663ab6
WYG		 5243 }
5244
46bc8d4b 5245 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5246
5247 return 0;
5248}
5249
5250/**
4d69c752 5251 * il4965_alive_start - called after N_ALIVE notification received
be663ab6 5252 * from protocol/runtime uCode (initialization uCode's
e2ebc833 5253 * Alive gets handled by il_init_alive_start()).
be663ab6 5254 */
e7392364
SG		 5255static void
5256il4965_alive_start(struct il_priv *il)
be663ab6
WYG		 5257{
5258 int ret = 0;
be663ab6 5259
58de00a4 5260 D_INFO("Runtime Alive received.\n");
be663ab6 5261
46bc8d4b 5262 if (il->card_alive.is_valid != UCODE_VALID_OK) {
be663ab6
WYG		 5263 /* We had an error bringing up the hardware, so take it
5264 * all the way back down so we can try again */
58de00a4 5265 D_INFO("Alive failed.\n");
be663ab6
WYG		 5266 goto restart;
5267 }
5268
5269 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5270 * This is a paranoid check, because we would not have gotten the
5271 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 5272 if (il4965_verify_ucode(il)) {
be663ab6
WYG		 5273 /* Runtime instruction load was bad;
5274 * take it all the way back down so we can try again */
58de00a4 5275 D_INFO("Bad runtime uCode load.\n");
be663ab6
WYG		 5276 goto restart;
5277 }
5278
46bc8d4b 5279 ret = il4965_alive_notify(il);
be663ab6 5280 if (ret) {
e7392364 5281 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
be663ab6
WYG		 5282 goto restart;
5283 }
5284
be663ab6 5285 /* After the ALIVE response, we can send host commands to the uCode */
a6766ccd 5286 set_bit(S_ALIVE, &il->status);
be663ab6
WYG		 5287
5288 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 5289 il_setup_watchdog(il);
be663ab6 5290
46bc8d4b 5291 if (il_is_rfkill(il))
be663ab6
WYG		 5292 return;
5293
46bc8d4b 5294 ieee80211_wake_queues(il->hw);
be663ab6 5295
2eb05816 5296 il->active_rate = RATES_MASK;
be663ab6 5297
c8b03958 5298 if (il_is_associated(il)) {
e2ebc833 5299 struct il_rxon_cmd *active_rxon =
c8b03958 5300 (struct il_rxon_cmd *)&il->active;
be663ab6 5301 /* apply any changes in staging */
c8b03958 5302 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5303 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5304 } else {
be663ab6 5305 /* Initialize our rx_config data */
83007196 5306 il_connection_init_rx_config(il);
be663ab6 5307
c39ae9fd
SG		 5308 if (il->ops->hcmd->set_rxon_chain)
5309 il->ops->hcmd->set_rxon_chain(il);
be663ab6
WYG		 5310 }
5311
5312 /* Configure bluetooth coexistence if enabled */
46bc8d4b 5313 il_send_bt_config(il);
be663ab6 5314
46bc8d4b 5315 il4965_reset_run_time_calib(il);
be663ab6 5316
a6766ccd 5317 set_bit(S_READY, &il->status);
be663ab6
WYG		 5318
5319 /* Configure the adapter for unassociated operation */
83007196 5320 il_commit_rxon(il);
be663ab6
WYG		 5321
5322 /* At this point, the NIC is initialized and operational */
46bc8d4b 5323 il4965_rf_kill_ct_config(il);
be663ab6 5324
58de00a4 5325 D_INFO("ALIVE processing complete.\n");
46bc8d4b 5326 wake_up(&il->wait_command_queue);
be663ab6 5327
46bc8d4b 5328 il_power_update_mode(il, true);
58de00a4 5329 D_INFO("Updated power mode\n");
be663ab6
WYG		 5330
5331 return;
5332
e7392364 5333restart:
46bc8d4b 5334 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 5335}
5336
46bc8d4b 5337static void il4965_cancel_deferred_work(struct il_priv *il);
be663ab6 5338
e7392364
SG		 5339static void
5340__il4965_down(struct il_priv *il)
be663ab6
WYG		 5341{
5342 unsigned long flags;
ab42b404 5343 int exit_pending;
be663ab6 5344
58de00a4 5345 D_INFO(DRV_NAME " is going down\n");
be663ab6 5346
46bc8d4b 5347 il_scan_cancel_timeout(il, 200);
be663ab6 5348
a6766ccd 5349 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
be663ab6 5350
a6766ccd 5351 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
be663ab6 5352 * to prevent rearm timer */
46bc8d4b 5353 del_timer_sync(&il->watchdog);
be663ab6 5354
83007196 5355 il_clear_ucode_stations(il);
d735f921
SG		 5356
5357 /* FIXME: race conditions ? */
5358 spin_lock_irq(&il->sta_lock);
5359 /*
5360 * Remove all key information that is not stored as part
5361 * of station information since mac80211 may not have had
5362 * a chance to remove all the keys. When device is
5363 * reconfigured by mac80211 after an error all keys will
5364 * be reconfigured.
5365 */
5366 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5367 il->_4965.key_mapping_keys = 0;
5368 spin_unlock_irq(&il->sta_lock);
5369
46bc8d4b
SG		 5370 il_dealloc_bcast_stations(il);
5371 il_clear_driver_stations(il);
be663ab6
WYG		 5372
5373 /* Unblock any waiting calls */
46bc8d4b 5374 wake_up_all(&il->wait_command_queue);
be663ab6
WYG		 5375
5376 /* Wipe out the EXIT_PENDING status bit if we are not actually
5377 * exiting the module */
5378 if (!exit_pending)
a6766ccd 5379 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5380
5381 /* stop and reset the on-board processor */
841b2cca 5382 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6
WYG		 5383
5384 /* tell the device to stop sending interrupts */
46bc8d4b
SG		 5385 spin_lock_irqsave(&il->lock, flags);
5386 il_disable_interrupts(il);
5387 spin_unlock_irqrestore(&il->lock, flags);
5388 il4965_synchronize_irq(il);
be663ab6 5389
46bc8d4b
SG		 5390 if (il->mac80211_registered)
5391 ieee80211_stop_queues(il->hw);
be663ab6 5392
e2ebc833 5393 /* If we have not previously called il_init() then
be663ab6 5394 * clear all bits but the RF Kill bit and return */
46bc8d4b 5395 if (!il_is_init(il)) {
e7392364
SG		 5396 il->status =
5397 test_bit(S_RF_KILL_HW,
5398 &il->
5399 status) << S_RF_KILL_HW |
5400 test_bit(S_GEO_CONFIGURED,
5401 &il->
5402 status) << S_GEO_CONFIGURED |
5403 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6
WYG		 5404 goto exit;
5405 }
5406
5407 /* ...otherwise clear out all the status bits but the RF Kill
5408 * bit and continue taking the NIC down. */
e7392364
SG		 5409 il->status &=
5410 test_bit(S_RF_KILL_HW,
5411 &il->status) << S_RF_KILL_HW | test_bit(S_GEO_CONFIGURED,
5412 &il->
5413 status) <<
5414 S_GEO_CONFIGURED | test_bit(S_FW_ERROR,
5415 &il->
5416 status) << S_FW_ERROR |
5417 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6 5418
46bc8d4b
SG		 5419 il4965_txq_ctx_stop(il);
5420 il4965_rxq_stop(il);
be663ab6
WYG		 5421
5422 /* Power-down device's busmaster DMA clocks */
db54eb57 5423 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 5424 udelay(5);
5425
5426 /* Make sure (redundant) we've released our request to stay awake */
e7392364 5427 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
be663ab6
WYG		 5428
5429 /* Stop the device, and put it in low power state */
46bc8d4b 5430 il_apm_stop(il);
be663ab6 5431
e7392364 5432exit:
46bc8d4b 5433 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
be663ab6 5434
46bc8d4b
SG		 5435 dev_kfree_skb(il->beacon_skb);
5436 il->beacon_skb = NULL;
be663ab6
WYG		 5437
5438 /* clear out any free frames */
46bc8d4b 5439 il4965_clear_free_frames(il);
be663ab6
WYG		 5440}
5441
e7392364
SG		 5442static void
5443il4965_down(struct il_priv *il)
be663ab6 5444{
46bc8d4b
SG		 5445 mutex_lock(&il->mutex);
5446 __il4965_down(il);
5447 mutex_unlock(&il->mutex);
be663ab6 5448
46bc8d4b 5449 il4965_cancel_deferred_work(il);
be663ab6
WYG		 5450}
5451
5452#define HW_READY_TIMEOUT (50)
5453
e7392364
SG		 5454static int
5455il4965_set_hw_ready(struct il_priv *il)
be663ab6
WYG		 5456{
5457 int ret = 0;
5458
46bc8d4b 5459 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 5460 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
be663ab6
WYG		 5461
5462 /* See if we got it */
e7392364
SG		 5463 ret =
5464 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5465 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5466 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, HW_READY_TIMEOUT);
be663ab6 5467 if (ret != -ETIMEDOUT)
46bc8d4b 5468 il->hw_ready = true;
be663ab6 5469 else
46bc8d4b 5470 il->hw_ready = false;
be663ab6 5471
e7392364 5472 D_INFO("hardware %s\n", (il->hw_ready == 1) ? "ready" : "not ready");
be663ab6
WYG		 5473 return ret;
5474}
5475
e7392364
SG		 5476static int
5477il4965_prepare_card_hw(struct il_priv *il)
be663ab6
WYG		 5478{
5479 int ret = 0;
5480
58de00a4 5481 D_INFO("il4965_prepare_card_hw enter\n");
be663ab6 5482
46bc8d4b
SG		 5483 ret = il4965_set_hw_ready(il);
5484 if (il->hw_ready)
be663ab6
WYG		 5485 return ret;
5486
5487 /* If HW is not ready, prepare the conditions to check again */
e7392364 5488 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
be663ab6 5489
e7392364
SG		 5490 ret =
5491 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5492 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5493 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
be663ab6
WYG		 5494
5495 /* HW should be ready by now, check again. */
5496 if (ret != -ETIMEDOUT)
46bc8d4b 5497 il4965_set_hw_ready(il);
be663ab6
WYG		 5498
5499 return ret;
5500}
5501
5502#define MAX_HW_RESTARTS 5
5503
e7392364
SG		 5504static int
5505__il4965_up(struct il_priv *il)
be663ab6 5506{
be663ab6
WYG		 5507 int i;
5508 int ret;
5509
a6766ccd 5510 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 5511 IL_WARN("Exit pending; will not bring the NIC up\n");
be663ab6
WYG		 5512 return -EIO;
5513 }
5514
46bc8d4b 5515 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 5516 IL_ERR("ucode not available for device bringup\n");
be663ab6
WYG		 5517 return -EIO;
5518 }
5519
83007196 5520 ret = il4965_alloc_bcast_station(il);
17d6e557
SG		 5521 if (ret) {
5522 il_dealloc_bcast_stations(il);
5523 return ret;
be663ab6
WYG		 5524 }
5525
46bc8d4b 5526 il4965_prepare_card_hw(il);
be663ab6 5527
46bc8d4b 5528 if (!il->hw_ready) {
9406f797 5529 IL_WARN("Exit HW not ready\n");
be663ab6
WYG		 5530 return -EIO;
5531 }
5532
5533 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 5534 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
a6766ccd 5535 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 5536 else
a6766ccd 5537 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 5538
46bc8d4b
SG		 5539 if (il_is_rfkill(il)) {
5540 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
be663ab6 5541
46bc8d4b 5542 il_enable_interrupts(il);
9406f797 5543 IL_WARN("Radio disabled by HW RF Kill switch\n");
be663ab6
WYG		 5544 return 0;
5545 }
5546
841b2cca 5547 _il_wr(il, CSR_INT, 0xFFFFFFFF);
be663ab6 5548
e2ebc833 5549 /* must be initialised before il_hw_nic_init */
46bc8d4b 5550 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
be663ab6 5551
46bc8d4b 5552 ret = il4965_hw_nic_init(il);
be663ab6 5553 if (ret) {
9406f797 5554 IL_ERR("Unable to init nic\n");
be663ab6
WYG		 5555 return ret;
5556 }
5557
5558 /* make sure rfkill handshake bits are cleared */
841b2cca 5559 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 5560 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6
WYG		 5561
5562 /* clear (again), then enable host interrupts */
841b2cca 5563 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5564 il_enable_interrupts(il);
be663ab6
WYG		 5565
5566 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG		 5567 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5568 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
be663ab6
WYG		 5569
5570 /* Copy original ucode data image from disk into backup cache.
5571 * This will be used to initialize the on-board processor's
5572 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG		 5573 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5574 il->ucode_data.len);
be663ab6
WYG		 5575
5576 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5577
5578 /* load bootstrap state machine,
5579 * load bootstrap program into processor's memory,
5580 * prepare to load the "initialize" uCode */
c39ae9fd 5581 ret = il->ops->lib->load_ucode(il);
be663ab6
WYG		 5582
5583 if (ret) {
e7392364 5584 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
be663ab6
WYG		 5585 continue;
5586 }
5587
5588 /* start card; "initialize" will load runtime ucode */
46bc8d4b 5589 il4965_nic_start(il);
be663ab6 5590
58de00a4 5591 D_INFO(DRV_NAME " is coming up\n");
be663ab6
WYG		 5592
5593 return 0;
5594 }
5595
a6766ccd 5596 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 5597 __il4965_down(il);
a6766ccd 5598 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5599
5600 /* tried to restart and config the device for as long as our
5601 * patience could withstand */
9406f797 5602 IL_ERR("Unable to initialize device after %d attempts.\n", i);
be663ab6
WYG		 5603 return -EIO;
5604}
5605
be663ab6
WYG		 5606/*****************************************************************************
5607 *
5608 * Workqueue callbacks
5609 *
5610 *****************************************************************************/
5611
e7392364
SG		 5612static void
5613il4965_bg_init_alive_start(struct work_struct *data)
be663ab6 5614{
46bc8d4b 5615 struct il_priv *il =
e2ebc833 5616 container_of(data, struct il_priv, init_alive_start.work);
be663ab6 5617
46bc8d4b 5618 mutex_lock(&il->mutex);
a6766ccd 5619 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5620 goto out;
be663ab6 5621
c39ae9fd 5622 il->ops->lib->init_alive_start(il);
28a6e577 5623out:
46bc8d4b 5624 mutex_unlock(&il->mutex);
be663ab6
WYG		 5625}
5626
e7392364
SG		 5627static void
5628il4965_bg_alive_start(struct work_struct *data)
be663ab6 5629{
46bc8d4b 5630 struct il_priv *il =
e2ebc833 5631 container_of(data, struct il_priv, alive_start.work);
be663ab6 5632
46bc8d4b 5633 mutex_lock(&il->mutex);
a6766ccd 5634 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5635 goto out;
be663ab6 5636
46bc8d4b 5637 il4965_alive_start(il);
28a6e577 5638out:
46bc8d4b 5639 mutex_unlock(&il->mutex);
be663ab6
WYG		 5640}
5641
e7392364
SG		 5642static void
5643il4965_bg_run_time_calib_work(struct work_struct *work)
be663ab6 5644{
46bc8d4b 5645 struct il_priv *il = container_of(work, struct il_priv,
e7392364 5646 run_time_calib_work);
be663ab6 5647
46bc8d4b 5648 mutex_lock(&il->mutex);
be663ab6 5649
a6766ccd
SG		 5650 if (test_bit(S_EXIT_PENDING, &il->status) ||
5651 test_bit(S_SCANNING, &il->status)) {
46bc8d4b 5652 mutex_unlock(&il->mutex);
be663ab6
WYG		 5653 return;
5654 }
5655
46bc8d4b 5656 if (il->start_calib) {
e7392364
SG		 5657 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5658 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
be663ab6
WYG		 5659 }
5660
46bc8d4b 5661 mutex_unlock(&il->mutex);
be663ab6
WYG		 5662}
5663
e7392364
SG		 5664static void
5665il4965_bg_restart(struct work_struct *data)
be663ab6 5666{
46bc8d4b 5667 struct il_priv *il = container_of(data, struct il_priv, restart);
be663ab6 5668
a6766ccd 5669 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5670 return;
5671
a6766ccd 5672 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 5673 mutex_lock(&il->mutex);
83007196
SG		 5674 /* FIXME: do we dereference vif without mutex locked ? */
5675 il->vif = NULL;
46bc8d4b 5676 il->is_open = 0;
be663ab6 5677
46bc8d4b 5678 __il4965_down(il);
be663ab6 5679
46bc8d4b
SG		 5680 mutex_unlock(&il->mutex);
5681 il4965_cancel_deferred_work(il);
5682 ieee80211_restart_hw(il->hw);
be663ab6 5683 } else {
46bc8d4b 5684 il4965_down(il);
be663ab6 5685
46bc8d4b 5686 mutex_lock(&il->mutex);
a6766ccd 5687 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 5688 mutex_unlock(&il->mutex);
be663ab6 5689 return;
28a6e577 5690 }
be663ab6 5691
46bc8d4b
SG		 5692 __il4965_up(il);
5693 mutex_unlock(&il->mutex);
be663ab6
WYG		 5694 }
5695}
5696
e7392364
SG		 5697static void
5698il4965_bg_rx_replenish(struct work_struct *data)
be663ab6 5699{
e7392364 5700 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
be663ab6 5701
a6766ccd 5702 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5703 return;
5704
46bc8d4b
SG		 5705 mutex_lock(&il->mutex);
5706 il4965_rx_replenish(il);
5707 mutex_unlock(&il->mutex);
be663ab6
WYG		 5708}
5709
5710/*****************************************************************************
5711 *
5712 * mac80211 entry point functions
5713 *
5714 *****************************************************************************/
5715
5716#define UCODE_READY_TIMEOUT (4 * HZ)
5717
5718/*
5719 * Not a mac80211 entry point function, but it fits in with all the
5720 * other mac80211 functions grouped here.
5721 */
e7392364
SG		 5722static int
5723il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
be663ab6
WYG		 5724{
5725 int ret;
46bc8d4b 5726 struct ieee80211_hw *hw = il->hw;
be663ab6
WYG		 5727
5728 hw->rate_control_algorithm = "iwl-4965-rs";
5729
5730 /* Tell mac80211 our characteristics */
e7392364
SG		 5731 hw->flags =
5732 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
5733 IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT |
5734 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
be663ab6 5735
46bc8d4b 5736 if (il->cfg->sku & IL_SKU_N)
e7392364
SG		 5737 hw->flags |=
5738 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5739 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
be663ab6 5740
e2ebc833
SG		 5741 hw->sta_data_size = sizeof(struct il_station_priv);
5742 hw->vif_data_size = sizeof(struct il_vif_priv);
be663ab6 5743
8c9c48d5
SG		 5744 hw->wiphy->interface_modes =
5745 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
be663ab6 5746
e7392364
SG		 5747 hw->wiphy->flags |=
5748 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS;
be663ab6
WYG		 5749
5750 /*
5751 * For now, disable PS by default because it affects
5752 * RX performance significantly.
5753 */
5754 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5755
5756 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5757 /* we create the 802.11 header and a zero-length SSID element */
5758 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5759
5760 /* Default value; 4 EDCA QOS priorities */
5761 hw->queues = 4;
5762
e2ebc833 5763 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
be663ab6 5764
46bc8d4b
SG		 5765 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5766 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 5767 &il->bands[IEEE80211_BAND_2GHZ];
46bc8d4b
SG		 5768 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5769 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 5770 &il->bands[IEEE80211_BAND_5GHZ];
be663ab6 5771
46bc8d4b 5772 il_leds_init(il);
be663ab6 5773
46bc8d4b 5774 ret = ieee80211_register_hw(il->hw);
be663ab6 5775 if (ret) {
9406f797 5776 IL_ERR("Failed to register hw (error %d)\n", ret);
be663ab6
WYG		 5777 return ret;
5778 }
46bc8d4b 5779 il->mac80211_registered = 1;
be663ab6
WYG		 5780
5781 return 0;
5782}
5783
e7392364
SG		 5784int
5785il4965_mac_start(struct ieee80211_hw *hw)
be663ab6 5786{
46bc8d4b 5787 struct il_priv *il = hw->priv;
be663ab6
WYG		 5788 int ret;
5789
58de00a4 5790 D_MAC80211("enter\n");
be663ab6
WYG		 5791
5792 /* we should be verifying the device is ready to be opened */
46bc8d4b
SG		 5793 mutex_lock(&il->mutex);
5794 ret = __il4965_up(il);
5795 mutex_unlock(&il->mutex);
be663ab6
WYG		 5796
5797 if (ret)
5798 return ret;
5799
46bc8d4b 5800 if (il_is_rfkill(il))
be663ab6
WYG		 5801 goto out;
5802
58de00a4 5803 D_INFO("Start UP work done.\n");
be663ab6
WYG		 5804
5805 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5806 * mac80211 will not be run successfully. */
46bc8d4b 5807 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 5808 test_bit(S_READY, &il->status),
5809 UCODE_READY_TIMEOUT);
be663ab6 5810 if (!ret) {
a6766ccd 5811 if (!test_bit(S_READY, &il->status)) {
9406f797 5812 IL_ERR("START_ALIVE timeout after %dms.\n",
be663ab6
WYG		 5813 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5814 return -ETIMEDOUT;
5815 }
5816 }
5817
46bc8d4b 5818 il4965_led_enable(il);
be663ab6
WYG		 5819
5820out:
46bc8d4b 5821 il->is_open = 1;
58de00a4 5822 D_MAC80211("leave\n");
be663ab6
WYG		 5823 return 0;
5824}
5825
e7392364
SG		 5826void
5827il4965_mac_stop(struct ieee80211_hw *hw)
be663ab6 5828{
46bc8d4b 5829 struct il_priv *il = hw->priv;
be663ab6 5830
58de00a4 5831 D_MAC80211("enter\n");
be663ab6 5832
46bc8d4b 5833 if (!il->is_open)
be663ab6
WYG		 5834 return;
5835
46bc8d4b 5836 il->is_open = 0;
be663ab6 5837
46bc8d4b 5838 il4965_down(il);
be663ab6 5839
46bc8d4b 5840 flush_workqueue(il->workqueue);
be663ab6 5841
a078a1fd
SG		 5842 /* User space software may expect getting rfkill changes
5843 * even if interface is down */
841b2cca 5844 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5845 il_enable_rfkill_int(il);
be663ab6 5846
58de00a4 5847 D_MAC80211("leave\n");
be663ab6
WYG		 5848}
5849
e7392364
SG		 5850void
5851il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
be663ab6 5852{
46bc8d4b 5853 struct il_priv *il = hw->priv;
be663ab6 5854
58de00a4 5855 D_MACDUMP("enter\n");
be663ab6 5856
58de00a4 5857 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 5858 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
be663ab6 5859
46bc8d4b 5860 if (il4965_tx_skb(il, skb))
be663ab6
WYG		 5861 dev_kfree_skb_any(skb);
5862
58de00a4 5863 D_MACDUMP("leave\n");
be663ab6
WYG		 5864}
5865
e7392364
SG		 5866void
5867il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5868 struct ieee80211_key_conf *keyconf,
5869 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
be663ab6 5870{
46bc8d4b 5871 struct il_priv *il = hw->priv;
be663ab6 5872
58de00a4 5873 D_MAC80211("enter\n");
be663ab6 5874
83007196 5875 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
be663ab6 5876
58de00a4 5877 D_MAC80211("leave\n");
be663ab6
WYG		 5878}
5879
e7392364
SG		 5880int
5881il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5882 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5883 struct ieee80211_key_conf *key)
be663ab6 5884{
46bc8d4b 5885 struct il_priv *il = hw->priv;
be663ab6
WYG		 5886 int ret;
5887 u8 sta_id;
5888 bool is_default_wep_key = false;
5889
58de00a4 5890 D_MAC80211("enter\n");
be663ab6 5891
46bc8d4b 5892 if (il->cfg->mod_params->sw_crypto) {
58de00a4 5893 D_MAC80211("leave - hwcrypto disabled\n");
be663ab6
WYG		 5894 return -EOPNOTSUPP;
5895 }
5896
83007196 5897 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 5898 if (sta_id == IL_INVALID_STATION)
be663ab6
WYG		 5899 return -EINVAL;
5900
46bc8d4b
SG		 5901 mutex_lock(&il->mutex);
5902 il_scan_cancel_timeout(il, 100);
be663ab6
WYG		 5903
5904 /*
5905 * If we are getting WEP group key and we didn't receive any key mapping
5906 * so far, we are in legacy wep mode (group key only), otherwise we are
5907 * in 1X mode.
5908 * In legacy wep mode, we use another host command to the uCode.
5909 */
5910 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
e7392364 5911 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
be663ab6 5912 if (cmd == SET_KEY)
d735f921 5913 is_default_wep_key = !il->_4965.key_mapping_keys;
be663ab6
WYG		 5914 else
5915 is_default_wep_key =
e7392364 5916 (key->hw_key_idx == HW_KEY_DEFAULT);
be663ab6
WYG		 5917 }
5918
5919 switch (cmd) {
5920 case SET_KEY:
5921 if (is_default_wep_key)
83007196 5922 ret = il4965_set_default_wep_key(il, key);
be663ab6 5923 else
83007196 5924 ret = il4965_set_dynamic_key(il, key, sta_id);
be663ab6 5925
58de00a4 5926 D_MAC80211("enable hwcrypto key\n");
be663ab6
WYG		 5927 break;
5928 case DISABLE_KEY:
5929 if (is_default_wep_key)
83007196 5930 ret = il4965_remove_default_wep_key(il, key);
be663ab6 5931 else
83007196 5932 ret = il4965_remove_dynamic_key(il, key, sta_id);
be663ab6 5933
58de00a4 5934 D_MAC80211("disable hwcrypto key\n");
be663ab6
WYG		 5935 break;
5936 default:
5937 ret = -EINVAL;
5938 }
5939
46bc8d4b 5940 mutex_unlock(&il->mutex);
58de00a4 5941 D_MAC80211("leave\n");
be663ab6
WYG		 5942
5943 return ret;
5944}
5945
e7392364
SG		 5946int
5947il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5948 enum ieee80211_ampdu_mlme_action action,
5949 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5950 u8 buf_size)
be663ab6 5951{
46bc8d4b 5952 struct il_priv *il = hw->priv;
be663ab6
WYG		 5953 int ret = -EINVAL;
5954
e7392364 5955 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
be663ab6 5956
46bc8d4b 5957 if (!(il->cfg->sku & IL_SKU_N))
be663ab6
WYG		 5958 return -EACCES;
5959
46bc8d4b 5960 mutex_lock(&il->mutex);
be663ab6
WYG		 5961
5962 switch (action) {
5963 case IEEE80211_AMPDU_RX_START:
58de00a4 5964 D_HT("start Rx\n");
46bc8d4b 5965 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
be663ab6
WYG		 5966 break;
5967 case IEEE80211_AMPDU_RX_STOP:
58de00a4 5968 D_HT("stop Rx\n");
46bc8d4b 5969 ret = il4965_sta_rx_agg_stop(il, sta, tid);
a6766ccd 5970 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5971 ret = 0;
5972 break;
5973 case IEEE80211_AMPDU_TX_START:
58de00a4 5974 D_HT("start Tx\n");
46bc8d4b 5975 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
be663ab6
WYG		 5976 break;
5977 case IEEE80211_AMPDU_TX_STOP:
58de00a4 5978 D_HT("stop Tx\n");
46bc8d4b 5979 ret = il4965_tx_agg_stop(il, vif, sta, tid);
a6766ccd 5980 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5981 ret = 0;
5982 break;
5983 case IEEE80211_AMPDU_TX_OPERATIONAL:
5984 ret = 0;
5985 break;
5986 }
46bc8d4b 5987 mutex_unlock(&il->mutex);
be663ab6
WYG		 5988
5989 return ret;
5990}
5991
e7392364
SG		 5992int
5993il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5994 struct ieee80211_sta *sta)
be663ab6 5995{
46bc8d4b 5996 struct il_priv *il = hw->priv;
e2ebc833 5997 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
be663ab6
WYG		 5998 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
5999 int ret;
6000 u8 sta_id;
6001
e7392364 6002 D_INFO("received request to add station %pM\n", sta->addr);
46bc8d4b 6003 mutex_lock(&il->mutex);
e7392364 6004 D_INFO("proceeding to add station %pM\n", sta->addr);
e2ebc833 6005 sta_priv->common.sta_id = IL_INVALID_STATION;
be663ab6
WYG		 6006
6007 atomic_set(&sta_priv->pending_frames, 0);
6008
e7392364 6009 ret =
83007196 6010 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
be663ab6 6011 if (ret) {
e7392364 6012 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
be663ab6 6013 /* Should we return success if return code is EEXIST ? */
46bc8d4b 6014 mutex_unlock(&il->mutex);
be663ab6
WYG		 6015 return ret;
6016 }
6017
6018 sta_priv->common.sta_id = sta_id;
6019
6020 /* Initialize rate scaling */
e7392364 6021 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG		 6022 il4965_rs_rate_init(il, sta, sta_id);
6023 mutex_unlock(&il->mutex);
be663ab6
WYG		 6024
6025 return 0;
6026}
6027
e7392364
SG		 6028void
6029il4965_mac_channel_switch(struct ieee80211_hw *hw,
6030 struct ieee80211_channel_switch *ch_switch)
be663ab6 6031{
46bc8d4b 6032 struct il_priv *il = hw->priv;
e2ebc833 6033 const struct il_channel_info *ch_info;
be663ab6
WYG		 6034 struct ieee80211_conf *conf = &hw->conf;
6035 struct ieee80211_channel *channel = ch_switch->channel;
46bc8d4b 6036 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6 6037 u16 ch;
be663ab6 6038
58de00a4 6039 D_MAC80211("enter\n");
be663ab6 6040
46bc8d4b 6041 mutex_lock(&il->mutex);
28a6e577 6042
46bc8d4b 6043 if (il_is_rfkill(il))
28a6e577 6044 goto out;
be663ab6 6045
a6766ccd
SG		 6046 if (test_bit(S_EXIT_PENDING, &il->status) ||
6047 test_bit(S_SCANNING, &il->status) ||
6048 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
28a6e577 6049 goto out;
be663ab6 6050
c8b03958 6051 if (!il_is_associated(il))
28a6e577 6052 goto out;
be663ab6 6053
c39ae9fd 6054 if (!il->ops->lib->set_channel_switch)
7f1f9742 6055 goto out;
be663ab6 6056
7f1f9742 6057 ch = channel->hw_value;
c8b03958 6058 if (le16_to_cpu(il->active.channel) == ch)
7f1f9742
SG		 6059 goto out;
6060
46bc8d4b 6061 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 6062 if (!il_is_channel_valid(ch_info)) {
58de00a4 6063 D_MAC80211("invalid channel\n");
7f1f9742
SG		 6064 goto out;
6065 }
6066
46bc8d4b 6067 spin_lock_irq(&il->lock);
7f1f9742 6068
46bc8d4b 6069 il->current_ht_config.smps = conf->smps_mode;
7f1f9742
SG		 6070
6071 /* Configure HT40 channels */
1c03c462
SG		 6072 il->ht.enabled = conf_is_ht(conf);
6073 if (il->ht.enabled) {
7f1f9742 6074 if (conf_is_ht40_minus(conf)) {
1c03c462 6075 il->ht.extension_chan_offset =
e7392364 6076 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 6077 il->ht.is_40mhz = true;
7f1f9742 6078 } else if (conf_is_ht40_plus(conf)) {
1c03c462 6079 il->ht.extension_chan_offset =
e7392364 6080 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 6081 il->ht.is_40mhz = true;
7f1f9742 6082 } else {
1c03c462 6083 il->ht.extension_chan_offset =
e7392364 6084 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 6085 il->ht.is_40mhz = false;
be663ab6 6086 }
7f1f9742 6087 } else
1c03c462 6088 il->ht.is_40mhz = false;
7f1f9742 6089
c8b03958
SG		 6090 if ((le16_to_cpu(il->staging.channel) != ch))
6091 il->staging.flags = 0;
7f1f9742 6092
83007196 6093 il_set_rxon_channel(il, channel);
46bc8d4b 6094 il_set_rxon_ht(il, ht_conf);
83007196 6095 il_set_flags_for_band(il, channel->band, il->vif);
7f1f9742 6096
46bc8d4b 6097 spin_unlock_irq(&il->lock);
7f1f9742 6098
46bc8d4b 6099 il_set_rate(il);
7f1f9742
SG		 6100 /*
6101 * at this point, staging_rxon has the
6102 * configuration for channel switch
6103 */
a6766ccd 6104 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6105 il->switch_channel = cpu_to_le16(ch);
c39ae9fd 6106 if (il->ops->lib->set_channel_switch(il, ch_switch)) {
a6766ccd 6107 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6108 il->switch_channel = 0;
83007196 6109 ieee80211_chswitch_done(il->vif, false);
be663ab6 6110 }
7f1f9742 6111
be663ab6 6112out:
46bc8d4b 6113 mutex_unlock(&il->mutex);
58de00a4 6114 D_MAC80211("leave\n");
be663ab6
WYG		 6115}
6116
e7392364
SG		 6117void
6118il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6119 unsigned int *total_flags, u64 multicast)
be663ab6 6120{
46bc8d4b 6121 struct il_priv *il = hw->priv;
be663ab6 6122 __le32 filter_or = 0, filter_nand = 0;
be663ab6
WYG		 6123
6124#define CHK(test, flag) do { \
6125 if (*total_flags & (test)) \
6126 filter_or |= (flag); \
6127 else \
6128 filter_nand |= (flag); \
6129 } while (0)
6130
e7392364
SG		 6131 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6132 *total_flags);
be663ab6
WYG		 6133
6134 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
6135 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6136 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6137 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6138
6139#undef CHK
6140
46bc8d4b 6141 mutex_lock(&il->mutex);
be663ab6 6142
c8b03958
SG		 6143 il->staging.filter_flags &= ~filter_nand;
6144 il->staging.filter_flags |= filter_or;
be663ab6 6145
17d6e557
SG		 6146 /*
6147 * Not committing directly because hardware can perform a scan,
6148 * but we'll eventually commit the filter flags change anyway.
6149 */
be663ab6 6150
46bc8d4b 6151 mutex_unlock(&il->mutex);
be663ab6
WYG		 6152
6153 /*
6154 * Receiving all multicast frames is always enabled by the
e2ebc833 6155 * default flags setup in il_connection_init_rx_config()
be663ab6
WYG		 6156 * since we currently do not support programming multicast
6157 * filters into the device.
6158 */
e7392364
SG		 6159 *total_flags &=
6160 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
6161 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
be663ab6
WYG		 6162}
6163
6164/*****************************************************************************
6165 *
6166 * driver setup and teardown
6167 *
6168 *****************************************************************************/
6169
e7392364
SG		 6170static void
6171il4965_bg_txpower_work(struct work_struct *work)
be663ab6 6172{
46bc8d4b 6173 struct il_priv *il = container_of(work, struct il_priv,
e7392364 6174 txpower_work);
be663ab6 6175
46bc8d4b 6176 mutex_lock(&il->mutex);
f325757a 6177
be663ab6 6178 /* If a scan happened to start before we got here
ebf0d90d 6179 * then just return; the stats notification will
be663ab6
WYG		 6180 * kick off another scheduled work to compensate for
6181 * any temperature delta we missed here. */
a6766ccd
SG		 6182 if (test_bit(S_EXIT_PENDING, &il->status) ||
6183 test_bit(S_SCANNING, &il->status))
f325757a 6184 goto out;
be663ab6
WYG		 6185
6186 /* Regardless of if we are associated, we must reconfigure the
6187 * TX power since frames can be sent on non-radar channels while
6188 * not associated */
c39ae9fd 6189 il->ops->lib->send_tx_power(il);
be663ab6
WYG		 6190
6191 /* Update last_temperature to keep is_calib_needed from running
6192 * when it isn't needed... */
46bc8d4b 6193 il->last_temperature = il->temperature;
f325757a 6194out:
46bc8d4b 6195 mutex_unlock(&il->mutex);
be663ab6
WYG		 6196}
6197
e7392364
SG		 6198static void
6199il4965_setup_deferred_work(struct il_priv *il)
be663ab6 6200{
46bc8d4b 6201 il->workqueue = create_singlethread_workqueue(DRV_NAME);
be663ab6 6202
46bc8d4b 6203 init_waitqueue_head(&il->wait_command_queue);
be663ab6 6204
46bc8d4b
SG		 6205 INIT_WORK(&il->restart, il4965_bg_restart);
6206 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6207 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6208 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6209 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
be663ab6 6210
46bc8d4b 6211 il_setup_scan_deferred_work(il);
be663ab6 6212
46bc8d4b 6213 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
be663ab6 6214
ebf0d90d
SG		 6215 init_timer(&il->stats_periodic);
6216 il->stats_periodic.data = (unsigned long)il;
6217 il->stats_periodic.function = il4965_bg_stats_periodic;
be663ab6 6218
46bc8d4b
SG		 6219 init_timer(&il->watchdog);
6220 il->watchdog.data = (unsigned long)il;
6221 il->watchdog.function = il_bg_watchdog;
be663ab6 6222
e7392364
SG		 6223 tasklet_init(&il->irq_tasklet,
6224 (void (*)(unsigned long))il4965_irq_tasklet,
6225 (unsigned long)il);
be663ab6
WYG		 6226}
6227
e7392364
SG		 6228static void
6229il4965_cancel_deferred_work(struct il_priv *il)
be663ab6 6230{
46bc8d4b
SG		 6231 cancel_work_sync(&il->txpower_work);
6232 cancel_delayed_work_sync(&il->init_alive_start);
6233 cancel_delayed_work(&il->alive_start);
6234 cancel_work_sync(&il->run_time_calib_work);
be663ab6 6235
46bc8d4b 6236 il_cancel_scan_deferred_work(il);
be663ab6 6237
ebf0d90d 6238 del_timer_sync(&il->stats_periodic);
be663ab6
WYG		 6239}
6240
e7392364
SG		 6241static void
6242il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
be663ab6
WYG		 6243{
6244 int i;
6245
2eb05816 6246 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
d2ddf621 6247 rates[i].bitrate = il_rates[i].ieee * 5;
e7392364 6248 rates[i].hw_value = i; /* Rate scaling will work on idxes */
be663ab6
WYG		 6249 rates[i].hw_value_short = i;
6250 rates[i].flags = 0;
e2ebc833 6251 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
be663ab6
WYG		 6252 /*
6253 * If CCK != 1M then set short preamble rate flag.
6254 */
6255 rates[i].flags |=
e7392364
SG		 6256 (il_rates[i].plcp ==
6257 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
be663ab6
WYG		 6258 }
6259 }
6260}
e7392364 6261
be663ab6 6262/*
46bc8d4b 6263 * Acquire il->lock before calling this function !
be663ab6 6264 */
e7392364
SG		 6265void
6266il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
be663ab6 6267{
e7392364 6268 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
0c2c8852 6269 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
be663ab6
WYG		 6270}
6271
e7392364
SG		 6272void
6273il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6274 int tx_fifo_id, int scd_retry)
be663ab6
WYG		 6275{
6276 int txq_id = txq->q.id;
6277
6278 /* Find out whether to activate Tx queue */
46bc8d4b 6279 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
be663ab6
WYG		 6280
6281 /* Set up and activate */
d3175167 6282 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 6283 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6284 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6285 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6286 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6287 IL49_SCD_QUEUE_STTS_REG_MSK);
be663ab6
WYG		 6288
6289 txq->sched_retry = scd_retry;
6290
e7392364
SG		 6291 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6292 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
be663ab6
WYG		 6293}
6294
c39ae9fd
SG		 6295const struct ieee80211_ops il4965_mac_ops = {
6296 .tx = il4965_mac_tx,
6297 .start = il4965_mac_start,
6298 .stop = il4965_mac_stop,
6299 .add_interface = il_mac_add_interface,
6300 .remove_interface = il_mac_remove_interface,
6301 .change_interface = il_mac_change_interface,
6302 .config = il_mac_config,
6303 .configure_filter = il4965_configure_filter,
6304 .set_key = il4965_mac_set_key,
6305 .update_tkip_key = il4965_mac_update_tkip_key,
6306 .conf_tx = il_mac_conf_tx,
6307 .reset_tsf = il_mac_reset_tsf,
6308 .bss_info_changed = il_mac_bss_info_changed,
6309 .ampdu_action = il4965_mac_ampdu_action,
6310 .hw_scan = il_mac_hw_scan,
6311 .sta_add = il4965_mac_sta_add,
6312 .sta_remove = il_mac_sta_remove,
6313 .channel_switch = il4965_mac_channel_switch,
6314 .tx_last_beacon = il_mac_tx_last_beacon,
6315};
6316
e7392364
SG		 6317static int
6318il4965_init_drv(struct il_priv *il)
be663ab6
WYG		 6319{
6320 int ret;
6321
46bc8d4b
SG		 6322 spin_lock_init(&il->sta_lock);
6323 spin_lock_init(&il->hcmd_lock);
be663ab6 6324
46bc8d4b 6325 INIT_LIST_HEAD(&il->free_frames);
be663ab6 6326
46bc8d4b 6327 mutex_init(&il->mutex);
be663ab6 6328
46bc8d4b
SG		 6329 il->ieee_channels = NULL;
6330 il->ieee_rates = NULL;
6331 il->band = IEEE80211_BAND_2GHZ;
be663ab6 6332
46bc8d4b
SG		 6333 il->iw_mode = NL80211_IFTYPE_STATION;
6334 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6335 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
be663ab6
WYG		 6336
6337 /* initialize force reset */
46bc8d4b 6338 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
be663ab6
WYG		 6339
6340 /* Choose which receivers/antennas to use */
c39ae9fd
SG		 6341 if (il->ops->hcmd->set_rxon_chain)
6342 il->ops->hcmd->set_rxon_chain(il);
be663ab6 6343
46bc8d4b 6344 il_init_scan_params(il);
be663ab6 6345
46bc8d4b 6346 ret = il_init_channel_map(il);
be663ab6 6347 if (ret) {
9406f797 6348 IL_ERR("initializing regulatory failed: %d\n", ret);
be663ab6
WYG		 6349 goto err;
6350 }
6351
46bc8d4b 6352 ret = il_init_geos(il);
be663ab6 6353 if (ret) {
9406f797 6354 IL_ERR("initializing geos failed: %d\n", ret);
be663ab6
WYG		 6355 goto err_free_channel_map;
6356 }
46bc8d4b 6357 il4965_init_hw_rates(il, il->ieee_rates);
be663ab6
WYG		 6358
6359 return 0;
6360
6361err_free_channel_map:
46bc8d4b 6362 il_free_channel_map(il);
be663ab6
WYG		 6363err:
6364 return ret;
6365}
6366
e7392364
SG		 6367static void
6368il4965_uninit_drv(struct il_priv *il)
be663ab6 6369{
46bc8d4b
SG		 6370 il4965_calib_free_results(il);
6371 il_free_geos(il);
6372 il_free_channel_map(il);
6373 kfree(il->scan_cmd);
be663ab6
WYG		 6374}
6375
e7392364
SG		 6376static void
6377il4965_hw_detect(struct il_priv *il)
be663ab6 6378{
841b2cca
SG		 6379 il->hw_rev = _il_rd(il, CSR_HW_REV);
6380 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
46bc8d4b 6381 il->rev_id = il->pci_dev->revision;
58de00a4 6382 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
be663ab6
WYG		 6383}
6384
1023f3bc
SG		 6385static struct il_sensitivity_ranges il4965_sensitivity = {
6386 .min_nrg_cck = 97,
6387 .max_nrg_cck = 0, /* not used, set to 0 */
6388
6389 .auto_corr_min_ofdm = 85,
6390 .auto_corr_min_ofdm_mrc = 170,
6391 .auto_corr_min_ofdm_x1 = 105,
6392 .auto_corr_min_ofdm_mrc_x1 = 220,
6393
6394 .auto_corr_max_ofdm = 120,
6395 .auto_corr_max_ofdm_mrc = 210,
6396 .auto_corr_max_ofdm_x1 = 140,
6397 .auto_corr_max_ofdm_mrc_x1 = 270,
6398
6399 .auto_corr_min_cck = 125,
6400 .auto_corr_max_cck = 200,
6401 .auto_corr_min_cck_mrc = 200,
6402 .auto_corr_max_cck_mrc = 400,
6403
6404 .nrg_th_cck = 100,
6405 .nrg_th_ofdm = 100,
6406
6407 .barker_corr_th_min = 190,
6408 .barker_corr_th_min_mrc = 390,
6409 .nrg_th_cca = 62,
6410};
6411
6412static void
e7392364 6413il4965_set_hw_params(struct il_priv *il)
be663ab6 6414{
b16db50a 6415 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
46bc8d4b
SG		 6416 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6417 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6418 if (il->cfg->mod_params->amsdu_size_8K)
6419 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
be663ab6 6420 else
46bc8d4b 6421 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
be663ab6 6422
46bc8d4b 6423 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
be663ab6 6424
46bc8d4b
SG		 6425 if (il->cfg->mod_params->disable_11n)
6426 il->cfg->sku &= ~IL_SKU_N;
be663ab6 6427
1023f3bc
SG		 6428 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6429 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6430 il->cfg->num_of_queues =
6431 il->cfg->mod_params->num_of_queues;
6432
6433 il->hw_params.max_txq_num = il->cfg->num_of_queues;
6434 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6435 il->hw_params.scd_bc_tbls_size =
6436 il->cfg->num_of_queues *
6437 sizeof(struct il4965_scd_bc_tbl);
6438
6439 il->hw_params.tfd_size = sizeof(struct il_tfd);
6440 il->hw_params.max_stations = IL4965_STATION_COUNT;
6441 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6442 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6443 il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6444 il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
6445
6446 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6447
6448 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6449 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6450 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6451 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6452
6453 il->hw_params.ct_kill_threshold =
6454 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6455
6456 il->hw_params.sens = &il4965_sensitivity;
6457 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
be663ab6
WYG		 6458}
6459
be663ab6 6460static int
e2ebc833 6461il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
be663ab6 6462{
7c2cde2e 6463 int err = 0;
46bc8d4b 6464 struct il_priv *il;
be663ab6 6465 struct ieee80211_hw *hw;
e2ebc833 6466 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
be663ab6
WYG		 6467 unsigned long flags;
6468 u16 pci_cmd;
6469
6470 /************************
6471 * 1. Allocating HW data
6472 ************************/
6473
c39ae9fd 6474 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
be663ab6
WYG		 6475 if (!hw) {
6476 err = -ENOMEM;
6477 goto out;
6478 }
46bc8d4b 6479 il = hw->priv;
c39ae9fd 6480 il->hw = hw;
be663ab6
WYG		 6481 SET_IEEE80211_DEV(hw, &pdev->dev);
6482
58de00a4 6483 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 6484 il->cfg = cfg;
c39ae9fd 6485 il->ops = &il4965_ops;
93b7654e
SG		 6486#ifdef CONFIG_IWLEGACY_DEBUGFS
6487 il->debugfs_ops = &il4965_debugfs_ops;
6488#endif
46bc8d4b
SG		 6489 il->pci_dev = pdev;
6490 il->inta_mask = CSR_INI_SET_MASK;
be663ab6 6491
46bc8d4b 6492 if (il_alloc_traffic_mem(il))
9406f797 6493 IL_ERR("Not enough memory to generate traffic log\n");
be663ab6
WYG		 6494
6495 /**************************
6496 * 2. Initializing PCI bus
6497 **************************/
e7392364
SG		 6498 pci_disable_link_state(pdev,
6499 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6500 PCIE_LINK_STATE_CLKPM);
be663ab6
WYG		 6501
6502 if (pci_enable_device(pdev)) {
6503 err = -ENODEV;
6504 goto out_ieee80211_free_hw;
6505 }
6506
6507 pci_set_master(pdev);
6508
6509 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6510 if (!err)
6511 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6512 if (err) {
6513 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6514 if (!err)
e7392364
SG		 6515 err =
6516 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
be663ab6
WYG		 6517 /* both attempts failed: */
6518 if (err) {
9406f797 6519 IL_WARN("No suitable DMA available.\n");
be663ab6
WYG		 6520 goto out_pci_disable_device;
6521 }
6522 }
6523
6524 err = pci_request_regions(pdev, DRV_NAME);
6525 if (err)
6526 goto out_pci_disable_device;
6527
46bc8d4b 6528 pci_set_drvdata(pdev, il);
be663ab6 6529
be663ab6
WYG		 6530 /***********************
6531 * 3. Read REV register
6532 ***********************/
a5f16137 6533 il->hw_base = pci_ioremap_bar(pdev, 0);
46bc8d4b 6534 if (!il->hw_base) {
be663ab6
WYG		 6535 err = -ENODEV;
6536 goto out_pci_release_regions;
6537 }
6538
58de00a4 6539 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 6540 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 6541 D_INFO("pci_resource_base = %p\n", il->hw_base);
be663ab6
WYG		 6542
6543 /* these spin locks will be used in apm_ops.init and EEPROM access
6544 * we should init now
6545 */
46bc8d4b
SG		 6546 spin_lock_init(&il->reg_lock);
6547 spin_lock_init(&il->lock);
be663ab6
WYG		 6548
6549 /*
6550 * stop and reset the on-board processor just in case it is in a
6551 * strange state ... like being left stranded by a primary kernel
6552 * and this is now the kdump kernel trying to start up
6553 */
841b2cca 6554 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6 6555
46bc8d4b 6556 il4965_hw_detect(il);
e7392364 6557 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
be663ab6
WYG		 6558
6559 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6560 * PCI Tx retries from interfering with C3 CPU state */
6561 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6562
46bc8d4b
SG		 6563 il4965_prepare_card_hw(il);
6564 if (!il->hw_ready) {
9406f797 6565 IL_WARN("Failed, HW not ready\n");
be663ab6
WYG		 6566 goto out_iounmap;
6567 }
6568
6569 /*****************
6570 * 4. Read EEPROM
6571 *****************/
6572 /* Read the EEPROM */
46bc8d4b 6573 err = il_eeprom_init(il);
be663ab6 6574 if (err) {
9406f797 6575 IL_ERR("Unable to init EEPROM\n");
be663ab6
WYG		 6576 goto out_iounmap;
6577 }
46bc8d4b 6578 err = il4965_eeprom_check_version(il);
be663ab6
WYG		 6579 if (err)
6580 goto out_free_eeprom;
6581
6582 if (err)
6583 goto out_free_eeprom;
6584
6585 /* extract MAC Address */
46bc8d4b 6586 il4965_eeprom_get_mac(il, il->addresses[0].addr);
58de00a4 6587 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
46bc8d4b
SG		 6588 il->hw->wiphy->addresses = il->addresses;
6589 il->hw->wiphy->n_addresses = 1;
be663ab6
WYG		 6590
6591 /************************
6592 * 5. Setup HW constants
6593 ************************/
1023f3bc 6594 il4965_set_hw_params(il);
be663ab6
WYG		 6595
6596 /*******************
46bc8d4b 6597 * 6. Setup il
be663ab6
WYG		 6598 *******************/
6599
46bc8d4b 6600 err = il4965_init_drv(il);
be663ab6
WYG		 6601 if (err)
6602 goto out_free_eeprom;
46bc8d4b 6603 /* At this point both hw and il are initialized. */
be663ab6
WYG		 6604
6605 /********************
6606 * 7. Setup services
6607 ********************/
46bc8d4b
SG		 6608 spin_lock_irqsave(&il->lock, flags);
6609 il_disable_interrupts(il);
6610 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6611
46bc8d4b 6612 pci_enable_msi(il->pci_dev);
be663ab6 6613
e7392364 6614 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
be663ab6 6615 if (err) {
9406f797 6616 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
be663ab6
WYG		 6617 goto out_disable_msi;
6618 }
6619
46bc8d4b 6620 il4965_setup_deferred_work(il);
d0c72347 6621 il4965_setup_handlers(il);
be663ab6
WYG		 6622
6623 /*********************************************
6624 * 8. Enable interrupts and read RFKILL state
6625 *********************************************/
6626
a078a1fd 6627 /* enable rfkill interrupt: hw bug w/a */
46bc8d4b 6628 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
be663ab6
WYG		 6629 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6630 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
46bc8d4b 6631 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
be663ab6
WYG		 6632 }
6633
46bc8d4b 6634 il_enable_rfkill_int(il);
be663ab6
WYG		 6635
6636 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 6637 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
a6766ccd 6638 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 6639 else
a6766ccd 6640 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 6641
46bc8d4b 6642 wiphy_rfkill_set_hw_state(il->hw->wiphy,
e7392364 6643 test_bit(S_RF_KILL_HW, &il->status));
be663ab6 6644
46bc8d4b 6645 il_power_initialize(il);
be663ab6 6646
46bc8d4b 6647 init_completion(&il->_4965.firmware_loading_complete);
be663ab6 6648
46bc8d4b 6649 err = il4965_request_firmware(il, true);
be663ab6
WYG		 6650 if (err)
6651 goto out_destroy_workqueue;
6652
6653 return 0;
6654
e7392364 6655out_destroy_workqueue:
46bc8d4b
SG		 6656 destroy_workqueue(il->workqueue);
6657 il->workqueue = NULL;
6658 free_irq(il->pci_dev->irq, il);
e7392364 6659out_disable_msi:
46bc8d4b
SG		 6660 pci_disable_msi(il->pci_dev);
6661 il4965_uninit_drv(il);
e7392364 6662out_free_eeprom:
46bc8d4b 6663 il_eeprom_free(il);
e7392364 6664out_iounmap:
a5f16137 6665 iounmap(il->hw_base);
e7392364 6666out_pci_release_regions:
be663ab6
WYG		 6667 pci_set_drvdata(pdev, NULL);
6668 pci_release_regions(pdev);
e7392364 6669out_pci_disable_device:
be663ab6 6670 pci_disable_device(pdev);
e7392364 6671out_ieee80211_free_hw:
46bc8d4b
SG		 6672 il_free_traffic_mem(il);
6673 ieee80211_free_hw(il->hw);
e7392364 6674out:
be663ab6
WYG		 6675 return err;
6676}
6677
e7392364
SG		 6678static void __devexit
6679il4965_pci_remove(struct pci_dev *pdev)
be663ab6 6680{
46bc8d4b 6681 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 6682 unsigned long flags;
6683
46bc8d4b 6684 if (!il)
be663ab6
WYG		 6685 return;
6686
46bc8d4b 6687 wait_for_completion(&il->_4965.firmware_loading_complete);
be663ab6 6688
58de00a4 6689 D_INFO("*** UNLOAD DRIVER ***\n");
be663ab6 6690
46bc8d4b 6691 il_dbgfs_unregister(il);
e2ebc833 6692 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
be663ab6 6693
e2ebc833
SG		 6694 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6695 * to be called and il4965_down since we are removing the device
a6766ccd 6696 * we need to set S_EXIT_PENDING bit.
be663ab6 6697 */
a6766ccd 6698 set_bit(S_EXIT_PENDING, &il->status);
be663ab6 6699
46bc8d4b 6700 il_leds_exit(il);
be663ab6 6701
46bc8d4b
SG		 6702 if (il->mac80211_registered) {
6703 ieee80211_unregister_hw(il->hw);
6704 il->mac80211_registered = 0;
be663ab6 6705 } else {
46bc8d4b 6706 il4965_down(il);
be663ab6
WYG		 6707 }
6708
6709 /*
6710 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG		 6711 * This may be redundant with il4965_down(), but there are paths to
6712 * run il4965_down() without calling apm_ops.stop(), and there are
6713 * paths to avoid running il4965_down() at all before leaving driver.
be663ab6
WYG		 6714 * This (inexpensive) call *makes sure* device is reset.
6715 */
46bc8d4b 6716 il_apm_stop(il);
be663ab6
WYG		 6717
6718 /* make sure we flush any pending irq or
6719 * tasklet for the driver
6720 */
46bc8d4b
SG		 6721 spin_lock_irqsave(&il->lock, flags);
6722 il_disable_interrupts(il);
6723 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6724
46bc8d4b 6725 il4965_synchronize_irq(il);
be663ab6 6726
46bc8d4b 6727 il4965_dealloc_ucode_pci(il);
be663ab6 6728
46bc8d4b
SG		 6729 if (il->rxq.bd)
6730 il4965_rx_queue_free(il, &il->rxq);
6731 il4965_hw_txq_ctx_free(il);
be663ab6 6732
46bc8d4b 6733 il_eeprom_free(il);
be663ab6 6734
be663ab6 6735 /*netif_stop_queue(dev); */
46bc8d4b 6736 flush_workqueue(il->workqueue);
be663ab6 6737
e2ebc833 6738 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
46bc8d4b 6739 * il->workqueue... so we can't take down the workqueue
be663ab6 6740 * until now... */
46bc8d4b
SG		 6741 destroy_workqueue(il->workqueue);
6742 il->workqueue = NULL;
6743 il_free_traffic_mem(il);
be663ab6 6744
46bc8d4b
SG		 6745 free_irq(il->pci_dev->irq, il);
6746 pci_disable_msi(il->pci_dev);
a5f16137 6747 iounmap(il->hw_base);
be663ab6
WYG		 6748 pci_release_regions(pdev);
6749 pci_disable_device(pdev);
6750 pci_set_drvdata(pdev, NULL);
6751
46bc8d4b 6752 il4965_uninit_drv(il);
be663ab6 6753
46bc8d4b 6754 dev_kfree_skb(il->beacon_skb);
be663ab6 6755
46bc8d4b 6756 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6757}
6758
6759/*
6760 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
46bc8d4b 6761 * must be called under il->lock and mac access
be663ab6 6762 */
e7392364
SG		 6763void
6764il4965_txq_set_sched(struct il_priv *il, u32 mask)
be663ab6 6765{
d3175167 6766 il_wr_prph(il, IL49_SCD_TXFACT, mask);
be663ab6
WYG		 6767}
6768
6769/*****************************************************************************
6770 *
6771 * driver and module entry point
6772 *
6773 *****************************************************************************/
6774
6775/* Hardware specific file defines the PCI IDs table for that hardware module */
e2ebc833 6776static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
e2ebc833
SG		 6777 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6778 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
be663ab6
WYG		 6779 {0}
6780};
e2ebc833 6781MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
be663ab6 6782
e2ebc833 6783static struct pci_driver il4965_driver = {
be663ab6 6784 .name = DRV_NAME,
e2ebc833
SG		 6785 .id_table = il4965_hw_card_ids,
6786 .probe = il4965_pci_probe,
6787 .remove = __devexit_p(il4965_pci_remove),
6788 .driver.pm = IL_LEGACY_PM_OPS,
be663ab6
WYG		 6789};
6790
e7392364
SG		 6791static int __init
6792il4965_init(void)
be663ab6
WYG		 6793{
6794
6795 int ret;
6796 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6797 pr_info(DRV_COPYRIGHT "\n");
6798
e2ebc833 6799 ret = il4965_rate_control_register();
be663ab6
WYG		 6800 if (ret) {
6801 pr_err("Unable to register rate control algorithm: %d\n", ret);
6802 return ret;
6803 }
6804
e2ebc833 6805 ret = pci_register_driver(&il4965_driver);
be663ab6
WYG		 6806 if (ret) {
6807 pr_err("Unable to initialize PCI module\n");
6808 goto error_register;
6809 }
6810
6811 return ret;
6812
6813error_register:
e2ebc833 6814 il4965_rate_control_unregister();
be663ab6
WYG		 6815 return ret;
6816}
6817
e7392364
SG		 6818static void __exit
6819il4965_exit(void)
be663ab6 6820{
e2ebc833
SG		 6821 pci_unregister_driver(&il4965_driver);
6822 il4965_rate_control_unregister();
be663ab6
WYG		 6823}
6824
e2ebc833
SG		 6825module_exit(il4965_exit);
6826module_init(il4965_init);
be663ab6 6827
d3175167 6828#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 6829module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
be663ab6
WYG		 6830MODULE_PARM_DESC(debug, "debug output mask");
6831#endif
6832
e2ebc833 6833module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
be663ab6 6834MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
e2ebc833 6835module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
be663ab6 6836MODULE_PARM_DESC(queues_num, "number of hw queues.");
e2ebc833 6837module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
be663ab6 6838MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
e7392364
SG		 6839module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6840 S_IRUGO);
be663ab6 6841MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
e2ebc833 6842module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
be663ab6 6843MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
Linux kernel - Deliverables
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