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iwlegacy: more checks for dma mapping errors
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
be663ab6
WYG		 43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
98613be0 53#include "common.h"
af038f40 54#include "4965.h"
be663ab6 55
be663ab6
WYG		 56/******************************************************************************
57 *
58 * module boiler plate
59 *
60 ******************************************************************************/
61
62/*
63 * module name, copyright, version, etc.
64 */
65#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
66
d3175167 67#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 68#define VD "d"
69#else
70#define VD
71#endif
72
73#define DRV_VERSION IWLWIFI_VERSION VD
74
be663ab6
WYG		 75MODULE_DESCRIPTION(DRV_DESCRIPTION);
76MODULE_VERSION(DRV_VERSION);
77MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78MODULE_LICENSE("GPL");
79MODULE_ALIAS("iwl4965");
80
e7392364
SG		 81void
82il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
fcb74588
SG		 83{
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
a6766ccd 86 if (!test_bit(S_EXIT_PENDING, &il->status))
fcb74588
SG		 87 queue_work(il->workqueue, &il->tx_flush);
88 }
89}
90
91/*
92 * EEPROM
93 */
94struct il_mod_params il4965_mod_params = {
95 .amsdu_size_8K = 1,
96 .restart_fw = 1,
97 /* the rest are 0 by default */
98};
99
e7392364
SG		 100void
101il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 102{
103 unsigned long flags;
104 int i;
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 114 PAGE_SIZE << il->hw_params.rx_page_order,
115 PCI_DMA_FROMDEVICE);
fcb74588
SG		 116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
118 }
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
120 }
121
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
124
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
129 rxq->free_count = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
131}
132
e7392364
SG		 133int
134il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 135{
136 u32 rb_size;
e7392364 137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
fcb74588
SG		 138 u32 rb_timeout = 0;
139
140 if (il->cfg->mod_params->amsdu_size_8K)
9a95b370 141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
fcb74588 142 else
9a95b370 143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
fcb74588
SG		 144
145 /* Stop Rx DMA */
9a95b370 146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
fcb74588
SG		 147
148 /* Reset driver's Rx queue write idx */
9a95b370 149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
fcb74588
SG		 150
151 /* Tell device where to find RBD circular buffer in DRAM */
e7392364 152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
fcb74588
SG		 153
154 /* Tell device where in DRAM to update its Rx status */
e7392364 155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
fcb74588
SG		 156
157 /* Enable Rx DMA
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
160 * RB timeout 0x10
161 * 256 RBDs
162 */
9a95b370 163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
e7392364
SG		 164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
1722f8e1
SG		 166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
167 rb_size |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
fcb74588
SG		 170
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
173
174 return 0;
175}
176
e7392364
SG		 177static void
178il4965_set_pwr_vmain(struct il_priv *il)
fcb74588
SG		 179{
180/*
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
183
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
188 */
189
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
e7392364
SG		 191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
fcb74588
SG		 193}
194
e7392364
SG		 195int
196il4965_hw_nic_init(struct il_priv *il)
fcb74588
SG		 197{
198 unsigned long flags;
199 struct il_rx_queue *rxq = &il->rxq;
200 int ret;
201
fcb74588 202 spin_lock_irqsave(&il->lock, flags);
f03ee2a8 203 il_apm_init(il);
fcb74588
SG		 204 /* Set interrupt coalescing calibration timer to default (512 usecs) */
205 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
fcb74588
SG		 206 spin_unlock_irqrestore(&il->lock, flags);
207
208 il4965_set_pwr_vmain(il);
f03ee2a8 209 il4965_nic_config(il);
fcb74588
SG		 210
211 /* Allocate the RX queue, or reset if it is already allocated */
212 if (!rxq->bd) {
213 ret = il_rx_queue_alloc(il);
214 if (ret) {
215 IL_ERR("Unable to initialize Rx queue\n");
216 return -ENOMEM;
217 }
218 } else
219 il4965_rx_queue_reset(il, rxq);
220
221 il4965_rx_replenish(il);
222
223 il4965_rx_init(il, rxq);
224
225 spin_lock_irqsave(&il->lock, flags);
226
227 rxq->need_update = 1;
228 il_rx_queue_update_write_ptr(il, rxq);
229
230 spin_unlock_irqrestore(&il->lock, flags);
231
232 /* Allocate or reset and init all Tx and Command queues */
233 if (!il->txq) {
234 ret = il4965_txq_ctx_alloc(il);
235 if (ret)
236 return ret;
237 } else
238 il4965_txq_ctx_reset(il);
239
a6766ccd 240 set_bit(S_INIT, &il->status);
fcb74588
SG		 241
242 return 0;
243}
244
245/**
246 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
247 */
e7392364
SG		 248static inline __le32
249il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
fcb74588 250{
e7392364 251 return cpu_to_le32((u32) (dma_addr >> 8));
fcb74588
SG		 252}
253
254/**
255 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
256 *
257 * If there are slots in the RX queue that need to be restocked,
258 * and we have free pre-allocated buffers, fill the ranks as much
259 * as we can, pulling from rx_free.
260 *
261 * This moves the 'write' idx forward to catch up with 'processed', and
262 * also updates the memory address in the firmware to reference the new
263 * target buffer.
264 */
e7392364
SG		 265void
266il4965_rx_queue_restock(struct il_priv *il)
fcb74588
SG		 267{
268 struct il_rx_queue *rxq = &il->rxq;
269 struct list_head *element;
270 struct il_rx_buf *rxb;
271 unsigned long flags;
272
273 spin_lock_irqsave(&rxq->lock, flags);
274 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
275 /* The overwritten rxb must be a used one */
276 rxb = rxq->queue[rxq->write];
277 BUG_ON(rxb && rxb->page);
278
279 /* Get next free Rx buffer, remove from free list */
280 element = rxq->rx_free.next;
281 rxb = list_entry(element, struct il_rx_buf, list);
282 list_del(element);
283
284 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG		 285 rxq->bd[rxq->write] =
286 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
fcb74588
SG		 287 rxq->queue[rxq->write] = rxb;
288 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
289 rxq->free_count--;
290 }
291 spin_unlock_irqrestore(&rxq->lock, flags);
292 /* If the pre-allocated buffer pool is dropping low, schedule to
293 * refill it */
294 if (rxq->free_count <= RX_LOW_WATERMARK)
295 queue_work(il->workqueue, &il->rx_replenish);
296
fcb74588
SG		 297 /* If we've added more space for the firmware to place data, tell it.
298 * Increment device's write pointer in multiples of 8. */
299 if (rxq->write_actual != (rxq->write & ~0x7)) {
300 spin_lock_irqsave(&rxq->lock, flags);
301 rxq->need_update = 1;
302 spin_unlock_irqrestore(&rxq->lock, flags);
303 il_rx_queue_update_write_ptr(il, rxq);
304 }
305}
306
307/**
308 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
309 *
310 * When moving to rx_free an SKB is allocated for the slot.
311 *
312 * Also restock the Rx queue via il_rx_queue_restock.
313 * This is called as a scheduled work item (except for during initialization)
314 */
e7392364
SG		 315static void
316il4965_rx_allocate(struct il_priv *il, gfp_t priority)
fcb74588
SG		 317{
318 struct il_rx_queue *rxq = &il->rxq;
319 struct list_head *element;
320 struct il_rx_buf *rxb;
321 struct page *page;
96ebbe8d 322 dma_addr_t page_dma;
fcb74588
SG		 323 unsigned long flags;
324 gfp_t gfp_mask = priority;
325
326 while (1) {
327 spin_lock_irqsave(&rxq->lock, flags);
328 if (list_empty(&rxq->rx_used)) {
329 spin_unlock_irqrestore(&rxq->lock, flags);
330 return;
331 }
332 spin_unlock_irqrestore(&rxq->lock, flags);
333
334 if (rxq->free_count > RX_LOW_WATERMARK)
335 gfp_mask |= __GFP_NOWARN;
336
337 if (il->hw_params.rx_page_order > 0)
338 gfp_mask |= __GFP_COMP;
339
340 /* Alloc a new receive buffer */
341 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
342 if (!page) {
343 if (net_ratelimit())
e7392364
SG		 344 D_INFO("alloc_pages failed, " "order: %d\n",
345 il->hw_params.rx_page_order);
fcb74588
SG		 346
347 if (rxq->free_count <= RX_LOW_WATERMARK &&
348 net_ratelimit())
e7392364
SG		 349 IL_ERR("Failed to alloc_pages with %s. "
350 "Only %u free buffers remaining.\n",
351 priority ==
352 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
353 rxq->free_count);
fcb74588
SG		 354 /* We don't reschedule replenish work here -- we will
355 * call the restock method and if it still needs
356 * more buffers it will schedule replenish */
357 return;
358 }
359
96ebbe8d
SG		 360 /* Get physical address of the RB */
361 page_dma =
362 pci_map_page(il->pci_dev, page, 0,
363 PAGE_SIZE << il->hw_params.rx_page_order,
364 PCI_DMA_FROMDEVICE);
365 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
366 __free_pages(page, il->hw_params.rx_page_order);
367 break;
368 }
369
fcb74588
SG		 370 spin_lock_irqsave(&rxq->lock, flags);
371
372 if (list_empty(&rxq->rx_used)) {
373 spin_unlock_irqrestore(&rxq->lock, flags);
96ebbe8d
SG		 374 pci_unmap_page(il->pci_dev, page_dma,
375 PAGE_SIZE << il->hw_params.rx_page_order,
376 PCI_DMA_FROMDEVICE);
fcb74588
SG		 377 __free_pages(page, il->hw_params.rx_page_order);
378 return;
379 }
96ebbe8d 380
fcb74588
SG		 381 element = rxq->rx_used.next;
382 rxb = list_entry(element, struct il_rx_buf, list);
383 list_del(element);
384
fcb74588 385 BUG_ON(rxb->page);
fcb74588 386
96ebbe8d
SG		 387 rxb->page = page;
388 rxb->page_dma = page_dma;
fcb74588
SG		 389 list_add_tail(&rxb->list, &rxq->rx_free);
390 rxq->free_count++;
391 il->alloc_rxb_page++;
392
393 spin_unlock_irqrestore(&rxq->lock, flags);
394 }
395}
396
e7392364
SG		 397void
398il4965_rx_replenish(struct il_priv *il)
fcb74588
SG		 399{
400 unsigned long flags;
401
402 il4965_rx_allocate(il, GFP_KERNEL);
403
404 spin_lock_irqsave(&il->lock, flags);
405 il4965_rx_queue_restock(il);
406 spin_unlock_irqrestore(&il->lock, flags);
407}
408
e7392364
SG		 409void
410il4965_rx_replenish_now(struct il_priv *il)
fcb74588
SG		 411{
412 il4965_rx_allocate(il, GFP_ATOMIC);
413
414 il4965_rx_queue_restock(il);
415}
416
417/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
418 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
419 * This free routine walks the list of POOL entries and if SKB is set to
420 * non NULL it is unmapped and freed
421 */
e7392364
SG		 422void
423il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
fcb74588
SG		 424{
425 int i;
426 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
427 if (rxq->pool[i].page != NULL) {
428 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG		 429 PAGE_SIZE << il->hw_params.rx_page_order,
430 PCI_DMA_FROMDEVICE);
fcb74588
SG		 431 __il_free_pages(il, rxq->pool[i].page);
432 rxq->pool[i].page = NULL;
433 }
434 }
435
436 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
437 rxq->bd_dma);
438 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
439 rxq->rb_stts, rxq->rb_stts_dma);
440 rxq->bd = NULL;
e7392364 441 rxq->rb_stts = NULL;
fcb74588
SG		 442}
443
e7392364
SG		 444int
445il4965_rxq_stop(struct il_priv *il)
fcb74588 446{
775ed8ab 447 int ret;
fcb74588 448
775ed8ab
SG		 449 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
450 ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
451 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
452 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
453 1000);
454 if (ret < 0)
455 IL_ERR("Can't stop Rx DMA.\n");
fcb74588
SG		 456
457 return 0;
458}
459
e7392364
SG		 460int
461il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
fcb74588
SG		 462{
463 int idx = 0;
464 int band_offset = 0;
465
466 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
467 if (rate_n_flags & RATE_MCS_HT_MSK) {
468 idx = (rate_n_flags & 0xff);
469 return idx;
e7392364 470 /* Legacy rate format, search for match in table */
fcb74588
SG		 471 } else {
472 if (band == IEEE80211_BAND_5GHZ)
473 band_offset = IL_FIRST_OFDM_RATE;
474 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
475 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
476 return idx - band_offset;
477 }
478
479 return -1;
480}
481
e7392364
SG		 482static int
483il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
fcb74588
SG		 484{
485 /* data from PHY/DSP regarding signal strength, etc.,
486 * contents are always there, not configurable by host. */
487 struct il4965_rx_non_cfg_phy *ncphy =
488 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
e7392364
SG		 489 u32 agc =
490 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
491 IL49_AGC_DB_POS;
fcb74588
SG		 492
493 u32 valid_antennae =
494 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
e7392364 495 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
fcb74588
SG		 496 u8 max_rssi = 0;
497 u32 i;
498
499 /* Find max rssi among 3 possible receivers.
500 * These values are measured by the digital signal processor (DSP).
501 * They should stay fairly constant even as the signal strength varies,
502 * if the radio's automatic gain control (AGC) is working right.
503 * AGC value (see below) will provide the "interesting" info. */
504 for (i = 0; i < 3; i++)
505 if (valid_antennae & (1 << i))
506 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
507
508 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
509 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
510 max_rssi, agc);
511
512 /* dBm = max_rssi dB - agc dB - constant.
513 * Higher AGC (higher radio gain) means lower signal. */
514 return max_rssi - agc - IL4965_RSSI_OFFSET;
515}
516
e7392364
SG		 517static u32
518il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
fcb74588
SG		 519{
520 u32 decrypt_out = 0;
521
522 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
e7392364
SG		 523 RX_RES_STATUS_STATION_FOUND)
524 decrypt_out |=
525 (RX_RES_STATUS_STATION_FOUND |
526 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
fcb74588
SG		 527
528 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
529
530 /* packet was not encrypted */
531 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 532 RX_RES_STATUS_SEC_TYPE_NONE)
fcb74588
SG		 533 return decrypt_out;
534
535 /* packet was encrypted with unknown alg */
536 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
e7392364 537 RX_RES_STATUS_SEC_TYPE_ERR)
fcb74588
SG		 538 return decrypt_out;
539
540 /* decryption was not done in HW */
541 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
e7392364 542 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
fcb74588
SG		 543 return decrypt_out;
544
545 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
546
547 case RX_RES_STATUS_SEC_TYPE_CCMP:
548 /* alg is CCM: check MIC only */
549 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
550 /* Bad MIC */
551 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
552 else
553 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
554
555 break;
556
557 case RX_RES_STATUS_SEC_TYPE_TKIP:
558 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
559 /* Bad TTAK */
560 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
561 break;
562 }
563 /* fall through if TTAK OK */
564 default:
565 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
566 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
567 else
568 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
569 break;
570 }
571
e7392364 572 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
fcb74588
SG		 573
574 return decrypt_out;
575}
576
e7392364
SG		 577static void
578il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
579 u16 len, u32 ampdu_status, struct il_rx_buf *rxb,
580 struct ieee80211_rx_status *stats)
fcb74588
SG		 581{
582 struct sk_buff *skb;
583 __le16 fc = hdr->frame_control;
584
585 /* We only process data packets if the interface is open */
586 if (unlikely(!il->is_open)) {
e7392364 587 D_DROP("Dropping packet while interface is not open.\n");
fcb74588
SG		 588 return;
589 }
590
591 /* In case of HW accelerated crypto and bad decryption, drop */
592 if (!il->cfg->mod_params->sw_crypto &&
593 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
594 return;
595
596 skb = dev_alloc_skb(128);
597 if (!skb) {
598 IL_ERR("dev_alloc_skb failed\n");
599 return;
600 }
601
50269e19
ED		 602 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len,
603 len);
fcb74588
SG		 604
605 il_update_stats(il, false, fc, len);
606 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
607
608 ieee80211_rx(il->hw, skb);
609 il->alloc_rxb_page--;
610 rxb->page = NULL;
611}
612
4d69c752
SG		 613/* Called for N_RX (legacy ABG frames), or
614 * N_RX_MPDU (HT high-throughput N frames). */
e7392364
SG		 615void
616il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 617{
618 struct ieee80211_hdr *header;
d369167f 619 struct ieee80211_rx_status rx_status = {};
fcb74588
SG		 620 struct il_rx_pkt *pkt = rxb_addr(rxb);
621 struct il_rx_phy_res *phy_res;
622 __le32 rx_pkt_status;
623 struct il_rx_mpdu_res_start *amsdu;
624 u32 len;
625 u32 ampdu_status;
626 u32 rate_n_flags;
627
628 /**
4d69c752
SG		 629 * N_RX and N_RX_MPDU are handled differently.
630 * N_RX: physical layer info is in this buffer
631 * N_RX_MPDU: physical layer info was sent in separate
fcb74588
SG		 632 * command and cached in il->last_phy_res
633 *
634 * Here we set up local variables depending on which command is
635 * received.
636 */
4d69c752 637 if (pkt->hdr.cmd == N_RX) {
fcb74588 638 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
e7392364
SG		 639 header =
640 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
641 phy_res->cfg_phy_cnt);
fcb74588
SG		 642
643 len = le16_to_cpu(phy_res->byte_count);
e7392364
SG		 644 rx_pkt_status =
645 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
646 phy_res->cfg_phy_cnt + len);
fcb74588
SG		 647 ampdu_status = le32_to_cpu(rx_pkt_status);
648 } else {
649 if (!il->_4965.last_phy_res_valid) {
650 IL_ERR("MPDU frame without cached PHY data\n");
651 return;
652 }
653 phy_res = &il->_4965.last_phy_res;
654 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
655 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
656 len = le16_to_cpu(amsdu->byte_count);
e7392364
SG		 657 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
658 ampdu_status =
659 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
fcb74588
SG		 660 }
661
662 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
663 D_DROP("dsp size out of range [0,20]: %d/n",
e7392364 664 phy_res->cfg_phy_cnt);
fcb74588
SG		 665 return;
666 }
667
668 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
669 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e7392364 670 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
fcb74588
SG		 671 return;
672 }
673
674 /* This will be used in several places later */
675 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
676
677 /* rx_status carries information about the packet to mac80211 */
678 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
e7392364
SG		 679 rx_status.band =
680 (phy_res->
681 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
682 IEEE80211_BAND_5GHZ;
fcb74588 683 rx_status.freq =
e7392364
SG		 684 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
685 rx_status.band);
fcb74588 686 rx_status.rate_idx =
e7392364 687 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
fcb74588
SG		 688 rx_status.flag = 0;
689
690 /* TSF isn't reliable. In order to allow smooth user experience,
691 * this W/A doesn't propagate it to the mac80211 */
f4bda337 692 /*rx_status.flag |= RX_FLAG_MACTIME_START; */
fcb74588
SG		 693
694 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
695
696 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
697 rx_status.signal = il4965_calc_rssi(il, phy_res);
698
e7392364
SG		 699 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
700 (unsigned long long)rx_status.mactime);
fcb74588
SG		 701
702 /*
703 * "antenna number"
704 *
705 * It seems that the antenna field in the phy flags value
706 * is actually a bit field. This is undefined by radiotap,
707 * it wants an actual antenna number but I always get "7"
708 * for most legacy frames I receive indicating that the
709 * same frame was received on all three RX chains.
710 *
711 * I think this field should be removed in favor of a
712 * new 802.11n radiotap field "RX chains" that is defined
713 * as a bitmask.
714 */
715 rx_status.antenna =
e7392364
SG		 716 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
717 RX_RES_PHY_FLAGS_ANTENNA_POS;
fcb74588
SG		 718
719 /* set the preamble flag if appropriate */
720 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
721 rx_status.flag |= RX_FLAG_SHORTPRE;
722
723 /* Set up the HT phy flags */
724 if (rate_n_flags & RATE_MCS_HT_MSK)
725 rx_status.flag |= RX_FLAG_HT;
726 if (rate_n_flags & RATE_MCS_HT40_MSK)
727 rx_status.flag |= RX_FLAG_40MHZ;
728 if (rate_n_flags & RATE_MCS_SGI_MSK)
729 rx_status.flag |= RX_FLAG_SHORT_GI;
730
0255beda
CL		 731 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) {
732 /* We know which subframes of an A-MPDU belong
733 * together since we get a single PHY response
734 * from the firmware for all of them.
735 */
736
737 rx_status.flag |= RX_FLAG_AMPDU_DETAILS;
738 rx_status.ampdu_reference = il->_4965.ampdu_ref;
739 }
740
e7392364
SG		 741 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
742 &rx_status);
fcb74588
SG		 743}
744
4d69c752 745/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
6e9848b4 746 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
e7392364
SG		 747void
748il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
fcb74588
SG		 749{
750 struct il_rx_pkt *pkt = rxb_addr(rxb);
751 il->_4965.last_phy_res_valid = true;
0255beda 752 il->_4965.ampdu_ref++;
fcb74588
SG		 753 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
754 sizeof(struct il_rx_phy_res));
755}
756
e7392364
SG		 757static int
758il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
759 enum ieee80211_band band, u8 is_active,
760 u8 n_probes, struct il_scan_channel *scan_ch)
fcb74588
SG		 761{
762 struct ieee80211_channel *chan;
763 const struct ieee80211_supported_band *sband;
764 const struct il_channel_info *ch_info;
765 u16 passive_dwell = 0;
766 u16 active_dwell = 0;
767 int added, i;
768 u16 channel;
769
770 sband = il_get_hw_mode(il, band);
771 if (!sband)
772 return 0;
773
774 active_dwell = il_get_active_dwell_time(il, band, n_probes);
775 passive_dwell = il_get_passive_dwell_time(il, band, vif);
776
777 if (passive_dwell <= active_dwell)
778 passive_dwell = active_dwell + 1;
779
780 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
781 chan = il->scan_request->channels[i];
782
783 if (chan->band != band)
784 continue;
785
786 channel = chan->hw_value;
787 scan_ch->channel = cpu_to_le16(channel);
788
789 ch_info = il_get_channel_info(il, band, channel);
790 if (!il_is_channel_valid(ch_info)) {
e7392364
SG		 791 D_SCAN("Channel %d is INVALID for this band.\n",
792 channel);
fcb74588
SG		 793 continue;
794 }
795
796 if (!is_active || il_is_channel_passive(ch_info) ||
797 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
798 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
799 else
800 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
801
802 if (n_probes)
803 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
804
805 scan_ch->active_dwell = cpu_to_le16(active_dwell);
806 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
807
808 /* Set txpower levels to defaults */
809 scan_ch->dsp_atten = 110;
810
811 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
812 * power level:
813 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
814 */
815 if (band == IEEE80211_BAND_5GHZ)
816 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
817 else
818 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
819
e7392364
SG		 820 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
821 le32_to_cpu(scan_ch->type),
822 (scan_ch->
823 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
824 (scan_ch->
825 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
826 passive_dwell);
fcb74588
SG		 827
828 scan_ch++;
829 added++;
830 }
831
832 D_SCAN("total channels to scan %d\n", added);
833 return added;
834}
835
a0c1ef3b
SG		 836static void
837il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
838{
839 int i;
840 u8 ind = *ant;
841
842 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
843 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
844 if (valid & BIT(ind)) {
845 *ant = ind;
846 return;
847 }
848 }
849}
850
e7392364
SG		 851int
852il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
fcb74588
SG		 853{
854 struct il_host_cmd cmd = {
4d69c752 855 .id = C_SCAN,
fcb74588
SG		 856 .len = sizeof(struct il_scan_cmd),
857 .flags = CMD_SIZE_HUGE,
858 };
859 struct il_scan_cmd *scan;
fcb74588
SG		 860 u32 rate_flags = 0;
861 u16 cmd_len;
862 u16 rx_chain = 0;
863 enum ieee80211_band band;
864 u8 n_probes = 0;
865 u8 rx_ant = il->hw_params.valid_rx_ant;
866 u8 rate;
867 bool is_active = false;
e7392364 868 int chan_mod;
fcb74588
SG		 869 u8 active_chains;
870 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
871 int ret;
872
873 lockdep_assert_held(&il->mutex);
874
fcb74588 875 if (!il->scan_cmd) {
e7392364
SG		 876 il->scan_cmd =
877 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
878 GFP_KERNEL);
fcb74588 879 if (!il->scan_cmd) {
e7392364 880 D_SCAN("fail to allocate memory for scan\n");
fcb74588
SG		 881 return -ENOMEM;
882 }
883 }
884 scan = il->scan_cmd;
885 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
886
887 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
888 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
889
890 if (il_is_any_associated(il)) {
891 u16 interval;
892 u32 extra;
893 u32 suspend_time = 100;
894 u32 scan_suspend_time = 100;
895
896 D_INFO("Scanning while associated...\n");
897 interval = vif->bss_conf.beacon_int;
898
899 scan->suspend_time = 0;
900 scan->max_out_time = cpu_to_le32(200 * 1024);
901 if (!interval)
902 interval = suspend_time;
903
904 extra = (suspend_time / interval) << 22;
e7392364
SG		 905 scan_suspend_time =
906 (extra | ((suspend_time % interval) * 1024));
fcb74588
SG		 907 scan->suspend_time = cpu_to_le32(scan_suspend_time);
908 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 909 scan_suspend_time, interval);
fcb74588
SG		 910 }
911
912 if (il->scan_request->n_ssids) {
913 int i, p = 0;
914 D_SCAN("Kicking off active scan\n");
915 for (i = 0; i < il->scan_request->n_ssids; i++) {
916 /* always does wildcard anyway */
917 if (!il->scan_request->ssids[i].ssid_len)
918 continue;
919 scan->direct_scan[p].id = WLAN_EID_SSID;
920 scan->direct_scan[p].len =
e7392364 921 il->scan_request->ssids[i].ssid_len;
fcb74588
SG		 922 memcpy(scan->direct_scan[p].ssid,
923 il->scan_request->ssids[i].ssid,
924 il->scan_request->ssids[i].ssid_len);
925 n_probes++;
926 p++;
927 }
928 is_active = true;
929 } else
930 D_SCAN("Start passive scan.\n");
931
932 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 933 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
fcb74588
SG		 934 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
935
936 switch (il->scan_band) {
937 case IEEE80211_BAND_2GHZ:
938 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
e7392364 939 chan_mod =
c8b03958 940 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
e7392364 941 RXON_FLG_CHANNEL_MODE_POS;
fcb74588
SG		 942 if (chan_mod == CHANNEL_MODE_PURE_40) {
943 rate = RATE_6M_PLCP;
944 } else {
945 rate = RATE_1M_PLCP;
946 rate_flags = RATE_MCS_CCK_MSK;
947 }
948 break;
949 case IEEE80211_BAND_5GHZ:
950 rate = RATE_6M_PLCP;
951 break;
952 default:
953 IL_WARN("Invalid scan band\n");
954 return -EIO;
955 }
956
957 /*
958 * If active scanning is requested but a certain channel is
959 * marked passive, we can do active scanning if we detect
960 * transmissions.
961 *
962 * There is an issue with some firmware versions that triggers
963 * a sysassert on a "good CRC threshold" of zero (== disabled),
964 * on a radar channel even though this means that we should NOT
965 * send probes.
966 *
967 * The "good CRC threshold" is the number of frames that we
968 * need to receive during our dwell time on a channel before
969 * sending out probes -- setting this to a huge value will
970 * mean we never reach it, but at the same time work around
971 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
972 * here instead of IL_GOOD_CRC_TH_DISABLED.
973 */
e7392364
SG		 974 scan->good_CRC_th =
975 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
fcb74588
SG		 976
977 band = il->scan_band;
978
979 if (il->cfg->scan_rx_antennas[band])
980 rx_ant = il->cfg->scan_rx_antennas[band];
981
a0c1ef3b 982 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
616107ed
SG		 983 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
984 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
fcb74588
SG		 985
986 /* In power save mode use one chain, otherwise use all chains */
a6766ccd 987 if (test_bit(S_POWER_PMI, &il->status)) {
fcb74588 988 /* rx_ant has been set to all valid chains previously */
e7392364
SG		 989 active_chains =
990 rx_ant & ((u8) (il->chain_noise_data.active_chains));
fcb74588
SG		 991 if (!active_chains)
992 active_chains = rx_ant;
993
994 D_SCAN("chain_noise_data.active_chains: %u\n",
e7392364 995 il->chain_noise_data.active_chains);
fcb74588
SG		 996
997 rx_ant = il4965_first_antenna(active_chains);
998 }
999
1000 /* MIMO is not used here, but value is required */
1001 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1002 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1003 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1004 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1005 scan->rx_chain = cpu_to_le16(rx_chain);
1006
e7392364
SG		 1007 cmd_len =
1008 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
1009 vif->addr, il->scan_request->ie,
1010 il->scan_request->ie_len,
1011 IL_MAX_SCAN_SIZE - sizeof(*scan));
fcb74588
SG		 1012 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1013
e7392364
SG		 1014 scan->filter_flags |=
1015 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
fcb74588 1016
e7392364
SG		 1017 scan->channel_count =
1018 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1019 (void *)&scan->data[cmd_len]);
fcb74588
SG		 1020 if (scan->channel_count == 0) {
1021 D_SCAN("channel count %d\n", scan->channel_count);
1022 return -EIO;
1023 }
1024
e7392364
SG		 1025 cmd.len +=
1026 le16_to_cpu(scan->tx_cmd.len) +
fcb74588
SG		 1027 scan->channel_count * sizeof(struct il_scan_channel);
1028 cmd.data = scan;
1029 scan->len = cpu_to_le16(cmd.len);
1030
a6766ccd 1031 set_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1032
1033 ret = il_send_cmd_sync(il, &cmd);
1034 if (ret)
a6766ccd 1035 clear_bit(S_SCAN_HW, &il->status);
fcb74588
SG		 1036
1037 return ret;
1038}
1039
e7392364
SG		 1040int
1041il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1042 bool add)
fcb74588
SG		 1043{
1044 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1045
1046 if (add)
83007196 1047 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
fcb74588
SG		 1048 &vif_priv->ibss_bssid_sta_id);
1049 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
e7392364 1050 vif->bss_conf.bssid);
fcb74588
SG		 1051}
1052
e7392364
SG		 1053void
1054il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
fcb74588
SG		 1055{
1056 lockdep_assert_held(&il->sta_lock);
1057
1058 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1059 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1060 else {
1061 D_TX("free more than tfds_in_queue (%u:%d)\n",
e7392364 1062 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
fcb74588
SG		 1063 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1064 }
1065}
1066
1067#define IL_TX_QUEUE_MSK 0xfffff
1068
e7392364
SG		 1069static bool
1070il4965_is_single_rx_stream(struct il_priv *il)
fcb74588
SG		 1071{
1072 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
e7392364 1073 il->current_ht_config.single_chain_sufficient;
fcb74588
SG		 1074}
1075
1076#define IL_NUM_RX_CHAINS_MULTIPLE 3
1077#define IL_NUM_RX_CHAINS_SINGLE 2
1078#define IL_NUM_IDLE_CHAINS_DUAL 2
1079#define IL_NUM_IDLE_CHAINS_SINGLE 1
1080
1081/*
1082 * Determine how many receiver/antenna chains to use.
1083 *
1084 * More provides better reception via diversity. Fewer saves power
1085 * at the expense of throughput, but only when not in powersave to
1086 * start with.
1087 *
1088 * MIMO (dual stream) requires at least 2, but works better with 3.
1089 * This does not determine *which* chains to use, just how many.
1090 */
e7392364
SG		 1091static int
1092il4965_get_active_rx_chain_count(struct il_priv *il)
fcb74588
SG		 1093{
1094 /* # of Rx chains to use when expecting MIMO. */
1095 if (il4965_is_single_rx_stream(il))
1096 return IL_NUM_RX_CHAINS_SINGLE;
1097 else
1098 return IL_NUM_RX_CHAINS_MULTIPLE;
1099}
1100
1101/*
1102 * When we are in power saving mode, unless device support spatial
1103 * multiplexing power save, use the active count for rx chain count.
1104 */
1105static int
1106il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1107{
1108 /* # Rx chains when idling, depending on SMPS mode */
1109 switch (il->current_ht_config.smps) {
1110 case IEEE80211_SMPS_STATIC:
1111 case IEEE80211_SMPS_DYNAMIC:
1112 return IL_NUM_IDLE_CHAINS_SINGLE;
1113 case IEEE80211_SMPS_OFF:
1114 return active_cnt;
1115 default:
e7392364 1116 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
fcb74588
SG		 1117 return active_cnt;
1118 }
1119}
1120
1121/* up to 4 chains */
e7392364
SG		 1122static u8
1123il4965_count_chain_bitmap(u32 chain_bitmap)
fcb74588
SG		 1124{
1125 u8 res;
1126 res = (chain_bitmap & BIT(0)) >> 0;
1127 res += (chain_bitmap & BIT(1)) >> 1;
1128 res += (chain_bitmap & BIT(2)) >> 2;
1129 res += (chain_bitmap & BIT(3)) >> 3;
1130 return res;
1131}
1132
1133/**
1134 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1135 *
1136 * Selects how many and which Rx receivers/antennas/chains to use.
1137 * This should not be used for scan command ... it puts data in wrong place.
1138 */
e7392364 1139void
83007196 1140il4965_set_rxon_chain(struct il_priv *il)
fcb74588
SG		 1141{
1142 bool is_single = il4965_is_single_rx_stream(il);
a6766ccd 1143 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
fcb74588
SG		 1144 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1145 u32 active_chains;
1146 u16 rx_chain;
1147
1148 /* Tell uCode which antennas are actually connected.
1149 * Before first association, we assume all antennas are connected.
1150 * Just after first association, il4965_chain_noise_calibration()
1151 * checks which antennas actually *are* connected. */
1152 if (il->chain_noise_data.active_chains)
1153 active_chains = il->chain_noise_data.active_chains;
1154 else
1155 active_chains = il->hw_params.valid_rx_ant;
1156
1157 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1158
1159 /* How many receivers should we use? */
1160 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1161 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1162
fcb74588
SG		 1163 /* correct rx chain count according hw settings
1164 * and chain noise calibration
1165 */
1166 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1167 if (valid_rx_cnt < active_rx_cnt)
1168 active_rx_cnt = valid_rx_cnt;
1169
1170 if (valid_rx_cnt < idle_rx_cnt)
1171 idle_rx_cnt = valid_rx_cnt;
1172
1173 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
e7392364 1174 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
fcb74588 1175
c8b03958 1176 il->staging.rx_chain = cpu_to_le16(rx_chain);
fcb74588
SG		 1177
1178 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
c8b03958 1179 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1180 else
c8b03958 1181 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
fcb74588 1182
c8b03958 1183 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
e7392364 1184 active_rx_cnt, idle_rx_cnt);
fcb74588
SG		 1185
1186 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1187 active_rx_cnt < idle_rx_cnt);
1188}
1189
e7392364
SG		 1190static const char *
1191il4965_get_fh_string(int cmd)
fcb74588
SG		 1192{
1193 switch (cmd) {
e7392364
SG		 1194 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1195 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1196 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1197 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1198 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1199 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1200 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1201 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1202 IL_CMD(FH49_TSSR_TX_ERROR_REG);
fcb74588
SG		 1203 default:
1204 return "UNKNOWN";
1205 }
1206}
1207
e7392364
SG		 1208int
1209il4965_dump_fh(struct il_priv *il, char **buf, bool display)
fcb74588
SG		 1210{
1211 int i;
1212#ifdef CONFIG_IWLEGACY_DEBUG
1213 int pos = 0;
1214 size_t bufsz = 0;
1215#endif
1216 static const u32 fh_tbl[] = {
9a95b370
SG		 1217 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1218 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1219 FH49_RSCSR_CHNL0_WPTR,
1220 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1221 FH49_MEM_RSSR_SHARED_CTRL_REG,
1222 FH49_MEM_RSSR_RX_STATUS_REG,
1223 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1224 FH49_TSSR_TX_STATUS_REG,
1225 FH49_TSSR_TX_ERROR_REG
fcb74588
SG		 1226 };
1227#ifdef CONFIG_IWLEGACY_DEBUG
1228 if (display) {
1229 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1230 *buf = kmalloc(bufsz, GFP_KERNEL);
1231 if (!*buf)
1232 return -ENOMEM;
e7392364
SG		 1233 pos +=
1234 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
fcb74588 1235 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
e7392364
SG		 1236 pos +=
1237 scnprintf(*buf + pos, bufsz - pos,
1238 " %34s: 0X%08x\n",
1722f8e1
SG		 1239 il4965_get_fh_string(fh_tbl[i]),
1240 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1241 }
1242 return pos;
1243 }
1244#endif
1245 IL_ERR("FH register values:\n");
e7392364
SG		 1246 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1247 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1248 il_rd(il, fh_tbl[i]));
fcb74588
SG		 1249 }
1250 return 0;
1251}
a1751b22 1252
e7392364
SG		 1253void
1254il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1255{
1256 struct il_rx_pkt *pkt = rxb_addr(rxb);
1257 struct il_missed_beacon_notif *missed_beacon;
1258
1259 missed_beacon = &pkt->u.missed_beacon;
1260 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1261 il->missed_beacon_threshold) {
e7392364
SG		 1262 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1263 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1264 le32_to_cpu(missed_beacon->total_missed_becons),
1265 le32_to_cpu(missed_beacon->num_recvd_beacons),
1266 le32_to_cpu(missed_beacon->num_expected_beacons));
a6766ccd 1267 if (!test_bit(S_SCANNING, &il->status))
a1751b22
SG		 1268 il4965_init_sensitivity(il);
1269 }
1270}
1271
1272/* Calculate noise level, based on measurements during network silence just
1273 * before arriving beacon. This measurement can be done only if we know
1274 * exactly when to expect beacons, therefore only when we're associated. */
e7392364
SG		 1275static void
1276il4965_rx_calc_noise(struct il_priv *il)
a1751b22
SG		 1277{
1278 struct stats_rx_non_phy *rx_info;
1279 int num_active_rx = 0;
1280 int total_silence = 0;
1281 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1282 int last_rx_noise;
1283
1284 rx_info = &(il->_4965.stats.rx.general);
1285 bcn_silence_a =
e7392364 1286 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
a1751b22 1287 bcn_silence_b =
e7392364 1288 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
a1751b22 1289 bcn_silence_c =
e7392364 1290 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
a1751b22
SG		 1291
1292 if (bcn_silence_a) {
1293 total_silence += bcn_silence_a;
1294 num_active_rx++;
1295 }
1296 if (bcn_silence_b) {
1297 total_silence += bcn_silence_b;
1298 num_active_rx++;
1299 }
1300 if (bcn_silence_c) {
1301 total_silence += bcn_silence_c;
1302 num_active_rx++;
1303 }
1304
1305 /* Average among active antennas */
1306 if (num_active_rx)
1307 last_rx_noise = (total_silence / num_active_rx) - 107;
1308 else
1309 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1310
e7392364
SG		 1311 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1312 bcn_silence_b, bcn_silence_c, last_rx_noise);
a1751b22
SG		 1313}
1314
1315#ifdef CONFIG_IWLEGACY_DEBUGFS
1316/*
1317 * based on the assumption of all stats counter are in DWORD
1318 * FIXME: This function is for debugging, do not deal with
1319 * the case of counters roll-over.
1320 */
e7392364
SG		 1321static void
1322il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
a1751b22
SG		 1323{
1324 int i, size;
1325 __le32 *prev_stats;
1326 u32 *accum_stats;
1327 u32 *delta, *max_delta;
1328 struct stats_general_common *general, *accum_general;
1329 struct stats_tx *tx, *accum_tx;
1330
1722f8e1
SG		 1331 prev_stats = (__le32 *) &il->_4965.stats;
1332 accum_stats = (u32 *) &il->_4965.accum_stats;
a1751b22
SG		 1333 size = sizeof(struct il_notif_stats);
1334 general = &il->_4965.stats.general.common;
1335 accum_general = &il->_4965.accum_stats.general.common;
1336 tx = &il->_4965.stats.tx;
1337 accum_tx = &il->_4965.accum_stats.tx;
1722f8e1
SG		 1338 delta = (u32 *) &il->_4965.delta_stats;
1339 max_delta = (u32 *) &il->_4965.max_delta;
a1751b22
SG		 1340
1341 for (i = sizeof(__le32); i < size;
e7392364
SG		 1342 i +=
1343 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1344 accum_stats++) {
a1751b22 1345 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
e7392364
SG		 1346 *delta =
1347 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
a1751b22
SG		 1348 *accum_stats += *delta;
1349 if (*delta > *max_delta)
1350 *max_delta = *delta;
1351 }
1352 }
1353
1354 /* reset accumulative stats for "no-counter" type stats */
1355 accum_general->temperature = general->temperature;
1356 accum_general->ttl_timestamp = general->ttl_timestamp;
1357}
1358#endif
1359
e7392364
SG		 1360void
1361il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22 1362{
527901d0
SG		 1363 const int recalib_seconds = 60;
1364 bool change;
a1751b22
SG		 1365 struct il_rx_pkt *pkt = rxb_addr(rxb);
1366
e7392364
SG		 1367 D_RX("Statistics notification received (%d vs %d).\n",
1368 (int)sizeof(struct il_notif_stats),
1369 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1370
1371 change =
1372 ((il->_4965.stats.general.common.temperature !=
1373 pkt->u.stats.general.common.temperature) ||
1374 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1375 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
a1751b22 1376#ifdef CONFIG_IWLEGACY_DEBUGFS
1722f8e1 1377 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
a1751b22
SG		 1378#endif
1379
1380 /* TODO: reading some of stats is unneeded */
e7392364 1381 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
a1751b22 1382
db7746f7 1383 set_bit(S_STATS, &il->status);
a1751b22 1384
527901d0
SG		 1385 /*
1386 * Reschedule the stats timer to occur in recalib_seconds to ensure
1387 * we get a thermal update even if the uCode doesn't give us one
1388 */
e7392364 1389 mod_timer(&il->stats_periodic,
527901d0 1390 jiffies + msecs_to_jiffies(recalib_seconds * 1000));
a1751b22 1391
a6766ccd 1392 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
4d69c752 1393 (pkt->hdr.cmd == N_STATS)) {
a1751b22
SG		 1394 il4965_rx_calc_noise(il);
1395 queue_work(il->workqueue, &il->run_time_calib_work);
1396 }
527901d0
SG		 1397
1398 if (change)
1399 il4965_temperature_calib(il);
a1751b22
SG		 1400}
1401
e7392364
SG		 1402void
1403il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 1404{
1405 struct il_rx_pkt *pkt = rxb_addr(rxb);
1406
db7746f7 1407 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
a1751b22
SG		 1408#ifdef CONFIG_IWLEGACY_DEBUGFS
1409 memset(&il->_4965.accum_stats, 0,
e7392364 1410 sizeof(struct il_notif_stats));
a1751b22 1411 memset(&il->_4965.delta_stats, 0,
e7392364
SG		 1412 sizeof(struct il_notif_stats));
1413 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
a1751b22
SG		 1414#endif
1415 D_RX("Statistics have been cleared\n");
1416 }
d2dfb33e 1417 il4965_hdl_stats(il, rxb);
a1751b22
SG		 1418}
1419
8f29b456
SG		 1420
1421/*
1422 * mac80211 queues, ACs, hardware queues, FIFOs.
1423 *
1424 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1425 *
1426 * Mac80211 uses the following numbers, which we get as from it
1427 * by way of skb_get_queue_mapping(skb):
1428 *
1429 * VO 0
1430 * VI 1
1431 * BE 2
1432 * BK 3
1433 *
1434 *
1435 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1436 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1437 * own queue per aggregation session (RA/TID combination), such queues are
1438 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1439 * order to map frames to the right queue, we also need an AC->hw queue
1440 * mapping. This is implemented here.
1441 *
1442 * Due to the way hw queues are set up (by the hw specific modules like
af038f40 1443 * 4965.c), the AC->hw queue mapping is the identity
8f29b456
SG		 1444 * mapping.
1445 */
1446
a1751b22
SG		 1447static const u8 tid_to_ac[] = {
1448 IEEE80211_AC_BE,
1449 IEEE80211_AC_BK,
1450 IEEE80211_AC_BK,
1451 IEEE80211_AC_BE,
1452 IEEE80211_AC_VI,
1453 IEEE80211_AC_VI,
1454 IEEE80211_AC_VO,
1455 IEEE80211_AC_VO
1456};
1457
e7392364
SG		 1458static inline int
1459il4965_get_ac_from_tid(u16 tid)
a1751b22
SG		 1460{
1461 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1462 return tid_to_ac[tid];
1463
1464 /* no support for TIDs 8-15 yet */
1465 return -EINVAL;
1466}
1467
1468static inline int
83007196 1469il4965_get_fifo_from_tid(u16 tid)
a1751b22 1470{
b75b3a70
SG		 1471 const u8 ac_to_fifo[] = {
1472 IL_TX_FIFO_VO,
1473 IL_TX_FIFO_VI,
1474 IL_TX_FIFO_BE,
1475 IL_TX_FIFO_BK,
1476 };
1477
a1751b22 1478 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
b75b3a70 1479 return ac_to_fifo[tid_to_ac[tid]];
a1751b22
SG		 1480
1481 /* no support for TIDs 8-15 yet */
1482 return -EINVAL;
1483}
1484
1485/*
4d69c752 1486 * handle build C_TX command notification.
a1751b22 1487 */
e7392364
SG		 1488static void
1489il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1490 struct il_tx_cmd *tx_cmd,
1491 struct ieee80211_tx_info *info,
1492 struct ieee80211_hdr *hdr, u8 std_id)
a1751b22
SG		 1493{
1494 __le16 fc = hdr->frame_control;
1495 __le32 tx_flags = tx_cmd->tx_flags;
1496
1497 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1498 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1499 tx_flags |= TX_CMD_FLG_ACK_MSK;
1500 if (ieee80211_is_mgmt(fc))
1501 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1502 if (ieee80211_is_probe_resp(fc) &&
1503 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1504 tx_flags |= TX_CMD_FLG_TSF_MSK;
1505 } else {
1506 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1507 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1508 }
1509
1510 if (ieee80211_is_back_req(fc))
1511 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1512
1513 tx_cmd->sta_id = std_id;
1514 if (ieee80211_has_morefrags(fc))
1515 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1516
1517 if (ieee80211_is_data_qos(fc)) {
1518 u8 *qc = ieee80211_get_qos_ctl(hdr);
1519 tx_cmd->tid_tspec = qc[0] & 0xf;
1520 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1521 } else {
1522 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1523 }
1524
1525 il_tx_cmd_protection(il, info, fc, &tx_flags);
1526
1527 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1528 if (ieee80211_is_mgmt(fc)) {
1529 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1530 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1531 else
1532 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1533 } else {
1534 tx_cmd->timeout.pm_frame_timeout = 0;
1535 }
1536
1537 tx_cmd->driver_txop = 0;
1538 tx_cmd->tx_flags = tx_flags;
1539 tx_cmd->next_frame_len = 0;
1540}
1541
e7392364 1542static void
36323f81
TH		 1543il4965_tx_cmd_build_rate(struct il_priv *il,
1544 struct il_tx_cmd *tx_cmd,
1545 struct ieee80211_tx_info *info,
1546 struct ieee80211_sta *sta,
1547 __le16 fc)
a1751b22 1548{
616107ed 1549 const u8 rts_retry_limit = 60;
a1751b22
SG		 1550 u32 rate_flags;
1551 int rate_idx;
a1751b22
SG		 1552 u8 data_retry_limit;
1553 u8 rate_plcp;
1554
e7392364 1555 /* Set retry limit on DATA packets and Probe Responses */
a1751b22
SG		 1556 if (ieee80211_is_probe_resp(fc))
1557 data_retry_limit = 3;
1558 else
1559 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1560 tx_cmd->data_retry_limit = data_retry_limit;
a1751b22 1561 /* Set retry limit on RTS packets */
616107ed 1562 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
a1751b22
SG		 1563
1564 /* DATA packets will use the uCode station table for rate/antenna
1565 * selection */
1566 if (ieee80211_is_data(fc)) {
1567 tx_cmd->initial_rate_idx = 0;
1568 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1569 return;
1570 }
1571
1572 /**
1573 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1574 * not really a TX rate. Thus, we use the lowest supported rate for
1575 * this band. Also use the lowest supported rate if the stored rate
1576 * idx is invalid.
1577 */
1578 rate_idx = info->control.rates[0].idx;
e7392364
SG		 1579 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1580 || rate_idx > RATE_COUNT_LEGACY)
36323f81 1581 rate_idx = rate_lowest_index(&il->bands[info->band], sta);
a1751b22
SG		 1582 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1583 if (info->band == IEEE80211_BAND_5GHZ)
1584 rate_idx += IL_FIRST_OFDM_RATE;
1585 /* Get PLCP rate for tx_cmd->rate_n_flags */
1586 rate_plcp = il_rates[rate_idx].plcp;
1587 /* Zero out flags for this packet */
1588 rate_flags = 0;
1589
1590 /* Set CCK flag as needed */
1591 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1592 rate_flags |= RATE_MCS_CCK_MSK;
1593
1594 /* Set up antennas */
a0c1ef3b 1595 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 1596 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
a1751b22
SG		 1597
1598 /* Set the rate in the TX cmd */
616107ed 1599 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
a1751b22
SG		 1600}
1601
e7392364
SG		 1602static void
1603il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1604 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1605 int sta_id)
a1751b22
SG		 1606{
1607 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1608
1609 switch (keyconf->cipher) {
1610 case WLAN_CIPHER_SUITE_CCMP:
1611 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1612 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1613 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1614 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1615 D_TX("tx_cmd with AES hwcrypto\n");
1616 break;
1617
1618 case WLAN_CIPHER_SUITE_TKIP:
1619 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1620 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1621 D_TX("tx_cmd with tkip hwcrypto\n");
1622 break;
1623
1624 case WLAN_CIPHER_SUITE_WEP104:
1625 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1626 /* fall through */
1627 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG		 1628 tx_cmd->sec_ctl |=
1629 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1630 TX_CMD_SEC_SHIFT);
a1751b22
SG		 1631
1632 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1633
e7392364
SG		 1634 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1635 keyconf->keyidx);
a1751b22
SG		 1636 break;
1637
1638 default:
1639 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1640 break;
1641 }
1642}
1643
1644/*
4d69c752 1645 * start C_TX command process
a1751b22 1646 */
e7392364 1647int
36323f81
TH		 1648il4965_tx_skb(struct il_priv *il,
1649 struct ieee80211_sta *sta,
1650 struct sk_buff *skb)
a1751b22
SG		 1651{
1652 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1653 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
a1751b22
SG		 1654 struct il_station_priv *sta_priv = NULL;
1655 struct il_tx_queue *txq;
1656 struct il_queue *q;
1657 struct il_device_cmd *out_cmd;
1658 struct il_cmd_meta *out_meta;
1659 struct il_tx_cmd *tx_cmd;
a1751b22
SG		 1660 int txq_id;
1661 dma_addr_t phys_addr;
1662 dma_addr_t txcmd_phys;
1663 dma_addr_t scratch_phys;
1664 u16 len, firstlen, secondlen;
1665 u16 seq_number = 0;
1666 __le16 fc;
1667 u8 hdr_len;
1668 u8 sta_id;
1669 u8 wait_write_ptr = 0;
1670 u8 tid = 0;
1671 u8 *qc = NULL;
1672 unsigned long flags;
1673 bool is_agg = false;
1674
a1751b22
SG		 1675 spin_lock_irqsave(&il->lock, flags);
1676 if (il_is_rfkill(il)) {
1677 D_DROP("Dropping - RF KILL\n");
1678 goto drop_unlock;
1679 }
1680
1681 fc = hdr->frame_control;
1682
1683#ifdef CONFIG_IWLEGACY_DEBUG
1684 if (ieee80211_is_auth(fc))
1685 D_TX("Sending AUTH frame\n");
1686 else if (ieee80211_is_assoc_req(fc))
1687 D_TX("Sending ASSOC frame\n");
1688 else if (ieee80211_is_reassoc_req(fc))
1689 D_TX("Sending REASSOC frame\n");
1690#endif
1691
1692 hdr_len = ieee80211_hdrlen(fc);
1693
1694 /* For management frames use broadcast id to do not break aggregation */
1695 if (!ieee80211_is_data(fc))
b16db50a 1696 sta_id = il->hw_params.bcast_id;
a1751b22
SG		 1697 else {
1698 /* Find idx into station table for destination station */
36323f81 1699 sta_id = il_sta_id_or_broadcast(il, sta);
a1751b22
SG		 1700
1701 if (sta_id == IL_INVALID_STATION) {
e7392364 1702 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
a1751b22
SG		 1703 goto drop_unlock;
1704 }
1705 }
1706
1707 D_TX("station Id %d\n", sta_id);
1708
1709 if (sta)
1710 sta_priv = (void *)sta->drv_priv;
1711
1712 if (sta_priv && sta_priv->asleep &&
02f2f1a9 1713 (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) {
a1751b22
SG		 1714 /*
1715 * This sends an asynchronous command to the device,
1716 * but we can rely on it being processed before the
1717 * next frame is processed -- and the next frame to
1718 * this station is the one that will consume this
1719 * counter.
1720 * For now set the counter to just 1 since we do not
1721 * support uAPSD yet.
1722 */
1723 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1724 }
1725
d1e14e94
SG		 1726 /* FIXME: remove me ? */
1727 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1728
eb123af3
SG		 1729 /* Access category (AC) is also the queue number */
1730 txq_id = skb_get_queue_mapping(skb);
a1751b22
SG		 1731
1732 /* irqs already disabled/saved above when locking il->lock */
1733 spin_lock(&il->sta_lock);
1734
1735 if (ieee80211_is_data_qos(fc)) {
1736 qc = ieee80211_get_qos_ctl(hdr);
1737 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1738 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1739 spin_unlock(&il->sta_lock);
1740 goto drop_unlock;
1741 }
1742 seq_number = il->stations[sta_id].tid[tid].seq_number;
1743 seq_number &= IEEE80211_SCTL_SEQ;
e7392364
SG		 1744 hdr->seq_ctrl =
1745 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
a1751b22
SG		 1746 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1747 seq_number += 0x10;
1748 /* aggregation is on for this <sta,tid> */
1749 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1750 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1751 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1752 is_agg = true;
1753 }
1754 }
1755
1756 txq = &il->txq[txq_id];
1757 q = &txq->q;
1758
1759 if (unlikely(il_queue_space(q) < q->high_mark)) {
1760 spin_unlock(&il->sta_lock);
1761 goto drop_unlock;
1762 }
1763
1764 if (ieee80211_is_data_qos(fc)) {
1765 il->stations[sta_id].tid[tid].tfds_in_queue++;
1766 if (!ieee80211_has_morefrags(fc))
1767 il->stations[sta_id].tid[tid].seq_number = seq_number;
1768 }
1769
1770 spin_unlock(&il->sta_lock);
1771
00ea99e1 1772 txq->skbs[q->write_ptr] = skb;
a1751b22
SG		 1773
1774 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1775 out_cmd = txq->cmd[q->write_ptr];
1776 out_meta = &txq->meta[q->write_ptr];
1777 tx_cmd = &out_cmd->cmd.tx;
1778 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1779 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1780
1781 /*
1782 * Set up the Tx-command (not MAC!) header.
1783 * Store the chosen Tx queue and TFD idx within the sequence field;
1784 * after Tx, uCode's Tx response will return this value so driver can
1785 * locate the frame within the tx queue and do post-tx processing.
1786 */
4d69c752 1787 out_cmd->hdr.cmd = C_TX;
e7392364
SG		 1788 out_cmd->hdr.sequence =
1789 cpu_to_le16((u16)
1790 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
a1751b22
SG		 1791
1792 /* Copy MAC header from skb into command buffer */
1793 memcpy(tx_cmd->hdr, hdr, hdr_len);
1794
a1751b22 1795 /* Total # bytes to be transmitted */
bdb084b2 1796 tx_cmd->len = cpu_to_le16((u16) skb->len);
a1751b22
SG		 1797
1798 if (info->control.hw_key)
1799 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1800
1801 /* TODO need this for burst mode later on */
1802 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
a1751b22 1803
36323f81 1804 il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc);
a1751b22 1805
a1751b22
SG		 1806 /*
1807 * Use the first empty entry in this queue's command buffer array
1808 * to contain the Tx command and MAC header concatenated together
1809 * (payload data will be in another buffer).
1810 * Size of this varies, due to varying MAC header length.
1811 * If end is not dword aligned, we'll have 2 extra bytes at the end
1812 * of the MAC header (device reads on dword boundaries).
1813 * We'll tell device about this padding later.
1814 */
e7392364 1815 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
a1751b22
SG		 1816 firstlen = (len + 3) & ~3;
1817
1818 /* Tell NIC about any 2-byte padding after MAC header */
1819 if (firstlen != len)
1820 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1821
1822 /* Physical address of this Tx command's header (not MAC header!),
1823 * within command buffer array. */
e7392364
SG		 1824 txcmd_phys =
1825 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1826 PCI_DMA_BIDIRECTIONAL);
bdb084b2
SG		 1827 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
1828 goto drop_unlock;
a1751b22
SG		 1829
1830 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1831 * if any (802.11 null frames have no payload). */
1832 secondlen = skb->len - hdr_len;
1833 if (secondlen > 0) {
e7392364
SG		 1834 phys_addr =
1835 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1836 PCI_DMA_TODEVICE);
bdb084b2
SG		 1837 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
1838 goto drop_unlock;
1839 }
1840
1841 /* Add buffer containing Tx command and MAC(!) header to TFD's
1842 * first entry */
1843 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
1844 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1845 dma_unmap_len_set(out_meta, len, firstlen);
1846 if (secondlen)
1600b875
SG		 1847 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen,
1848 0, 0);
bdb084b2
SG		 1849
1850 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1851 txq->need_update = 1;
1852 } else {
1853 wait_write_ptr = 1;
1854 txq->need_update = 0;
a1751b22
SG		 1855 }
1856
e7392364
SG		 1857 scratch_phys =
1858 txcmd_phys + sizeof(struct il_cmd_header) +
1859 offsetof(struct il_tx_cmd, scratch);
a1751b22
SG		 1860
1861 /* take back ownership of DMA buffer to enable update */
e7392364
SG		 1862 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1863 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1864 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1865 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1866
bdb084b2
SG		 1867 il_update_stats(il, true, fc, skb->len);
1868
e7392364 1869 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
a1751b22 1870 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
e7392364
SG		 1871 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1872 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
a1751b22
SG		 1873
1874 /* Set up entry for this TFD in Tx byte-count array */
1875 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1600b875 1876 il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len));
a1751b22 1877
e7392364
SG		 1878 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1879 PCI_DMA_BIDIRECTIONAL);
a1751b22
SG		 1880
1881 /* Tell device the write idx *just past* this latest filled TFD */
1882 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1883 il_txq_update_write_ptr(il, txq);
1884 spin_unlock_irqrestore(&il->lock, flags);
1885
1886 /*
1887 * At this point the frame is "transmitted" successfully
1888 * and we will get a TX status notification eventually,
1889 * regardless of the value of ret. "ret" only indicates
1890 * whether or not we should update the write pointer.
1891 */
1892
1893 /*
1894 * Avoid atomic ops if it isn't an associated client.
1895 * Also, if this is a packet for aggregation, don't
1896 * increase the counter because the ucode will stop
1897 * aggregation queues when their respective station
1898 * goes to sleep.
1899 */
1900 if (sta_priv && sta_priv->client && !is_agg)
1901 atomic_inc(&sta_priv->pending_frames);
1902
1903 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1904 if (wait_write_ptr) {
1905 spin_lock_irqsave(&il->lock, flags);
1906 txq->need_update = 1;
1907 il_txq_update_write_ptr(il, txq);
1908 spin_unlock_irqrestore(&il->lock, flags);
1909 } else {
1910 il_stop_queue(il, txq);
1911 }
1912 }
1913
1914 return 0;
1915
1916drop_unlock:
1917 spin_unlock_irqrestore(&il->lock, flags);
1918 return -1;
1919}
1920
e7392364
SG		 1921static inline int
1922il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
a1751b22 1923{
e7392364
SG		 1924 ptr->addr =
1925 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL);
a1751b22
SG		 1926 if (!ptr->addr)
1927 return -ENOMEM;
1928 ptr->size = size;
1929 return 0;
1930}
1931
e7392364
SG		 1932static inline void
1933il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
a1751b22
SG		 1934{
1935 if (unlikely(!ptr->addr))
1936 return;
1937
1938 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1939 memset(ptr, 0, sizeof(*ptr));
1940}
1941
1942/**
1943 * il4965_hw_txq_ctx_free - Free TXQ Context
1944 *
1945 * Destroy all TX DMA queues and structures
1946 */
e7392364
SG		 1947void
1948il4965_hw_txq_ctx_free(struct il_priv *il)
a1751b22
SG		 1949{
1950 int txq_id;
1951
1952 /* Tx queues */
1953 if (il->txq) {
1954 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1955 if (txq_id == il->cmd_queue)
1956 il_cmd_queue_free(il);
1957 else
1958 il_tx_queue_free(il, txq_id);
1959 }
1960 il4965_free_dma_ptr(il, &il->kw);
1961
1962 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1963
1964 /* free tx queue structure */
6668e4eb 1965 il_free_txq_mem(il);
a1751b22
SG		 1966}
1967
1968/**
1969 * il4965_txq_ctx_alloc - allocate TX queue context
1970 * Allocate all Tx DMA structures and initialize them
1971 *
1972 * @param il
1973 * @return error code
1974 */
e7392364
SG		 1975int
1976il4965_txq_ctx_alloc(struct il_priv *il)
a1751b22 1977{
d87c771f 1978 int ret, txq_id;
a1751b22
SG		 1979 unsigned long flags;
1980
1981 /* Free all tx/cmd queues and keep-warm buffer */
1982 il4965_hw_txq_ctx_free(il);
1983
e7392364
SG		 1984 ret =
1985 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1986 il->hw_params.scd_bc_tbls_size);
a1751b22
SG		 1987 if (ret) {
1988 IL_ERR("Scheduler BC Table allocation failed\n");
1989 goto error_bc_tbls;
1990 }
1991 /* Alloc keep-warm buffer */
1992 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1993 if (ret) {
1994 IL_ERR("Keep Warm allocation failed\n");
1995 goto error_kw;
1996 }
1997
1998 /* allocate tx queue structure */
1999 ret = il_alloc_txq_mem(il);
2000 if (ret)
2001 goto error;
2002
2003 spin_lock_irqsave(&il->lock, flags);
2004
2005 /* Turn off all Tx DMA fifos */
2006 il4965_txq_set_sched(il, 0);
2007
2008 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2009 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2010
2011 spin_unlock_irqrestore(&il->lock, flags);
2012
2013 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
2014 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
d87c771f 2015 ret = il_tx_queue_init(il, txq_id);
a1751b22
SG		 2016 if (ret) {
2017 IL_ERR("Tx %d queue init failed\n", txq_id);
2018 goto error;
2019 }
2020 }
2021
2022 return ret;
2023
e7392364 2024error:
a1751b22
SG		 2025 il4965_hw_txq_ctx_free(il);
2026 il4965_free_dma_ptr(il, &il->kw);
e7392364 2027error_kw:
a1751b22 2028 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
e7392364 2029error_bc_tbls:
a1751b22
SG		 2030 return ret;
2031}
2032
e7392364
SG		 2033void
2034il4965_txq_ctx_reset(struct il_priv *il)
a1751b22 2035{
d87c771f 2036 int txq_id;
a1751b22
SG		 2037 unsigned long flags;
2038
2039 spin_lock_irqsave(&il->lock, flags);
2040
2041 /* Turn off all Tx DMA fifos */
2042 il4965_txq_set_sched(il, 0);
a1751b22 2043 /* Tell NIC where to find the "keep warm" buffer */
9a95b370 2044 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
a1751b22
SG		 2045
2046 spin_unlock_irqrestore(&il->lock, flags);
2047
2048 /* Alloc and init all Tx queues, including the command queue (#4) */
d87c771f
SG		 2049 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2050 il_tx_queue_reset(il, txq_id);
a1751b22
SG		 2051}
2052
e7392364 2053void
775ed8ab 2054il4965_txq_ctx_unmap(struct il_priv *il)
a1751b22 2055{
775ed8ab 2056 int txq_id;
a1751b22
SG		 2057
2058 if (!il->txq)
2059 return;
2060
2061 /* Unmap DMA from host system and free skb's */
2062 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2063 if (txq_id == il->cmd_queue)
2064 il_cmd_queue_unmap(il);
2065 else
2066 il_tx_queue_unmap(il, txq_id);
2067}
2068
775ed8ab
SG		 2069/**
2070 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2071 */
2072void
2073il4965_txq_ctx_stop(struct il_priv *il)
2074{
2075 int ch, ret;
2076
2077 _il_wr_prph(il, IL49_SCD_TXFACT, 0);
2078
2079 /* Stop each Tx DMA channel, and wait for it to be idle */
2080 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2081 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2082 ret =
2083 _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
2084 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2085 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2086 1000);
2087 if (ret < 0)
2088 IL_ERR("Timeout stopping DMA channel %d [0x%08x]",
2089 ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
2090 }
2091}
2092
a1751b22
SG		 2093/*
2094 * Find first available (lowest unused) Tx Queue, mark it "active".
2095 * Called only when finding queue for aggregation.
2096 * Should never return anything < 7, because they should already
2097 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2098 */
e7392364
SG		 2099static int
2100il4965_txq_ctx_activate_free(struct il_priv *il)
a1751b22
SG		 2101{
2102 int txq_id;
2103
2104 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2105 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2106 return txq_id;
2107 return -1;
2108}
2109
2110/**
2111 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2112 */
e7392364
SG		 2113static void
2114il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
a1751b22
SG		 2115{
2116 /* Simply stop the queue, but don't change any configuration;
2117 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
e7392364 2118 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 2119 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2120 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
a1751b22
SG		 2121}
2122
2123/**
2124 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2125 */
e7392364
SG		 2126static int
2127il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
a1751b22
SG		 2128{
2129 u32 tbl_dw_addr;
2130 u32 tbl_dw;
2131 u16 scd_q2ratid;
2132
2133 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2134
e7392364
SG		 2135 tbl_dw_addr =
2136 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
a1751b22
SG		 2137
2138 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2139
2140 if (txq_id & 0x1)
2141 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2142 else
2143 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2144
2145 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2146
2147 return 0;
2148}
2149
2150/**
2151 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2152 *
2153 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2154 * i.e. it must be one of the higher queues used for aggregation
2155 */
e7392364
SG		 2156static int
2157il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2158 int tid, u16 ssn_idx)
a1751b22
SG		 2159{
2160 unsigned long flags;
2161 u16 ra_tid;
2162 int ret;
2163
2164 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2165 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2166 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2167 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2168 txq_id, IL49_FIRST_AMPDU_QUEUE,
2169 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2170 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2171 return -EINVAL;
2172 }
2173
2174 ra_tid = BUILD_RAxTID(sta_id, tid);
2175
2176 /* Modify device's station table to Tx this TID */
2177 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2178 if (ret)
2179 return ret;
2180
2181 spin_lock_irqsave(&il->lock, flags);
2182
2183 /* Stop this Tx queue before configuring it */
2184 il4965_tx_queue_stop_scheduler(il, txq_id);
2185
2186 /* Map receiver-address / traffic-ID to this queue */
2187 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2188
2189 /* Set this queue as a chain-building queue */
2190 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2191
2192 /* Place first TFD at idx corresponding to start sequence number.
2193 * Assumes that ssn_idx is valid (!= 0xFFF) */
2194 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2195 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2196 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2197
2198 /* Set up Tx win size and frame limit for this queue */
2199 il_write_targ_mem(il,
e7392364
SG		 2200 il->scd_base_addr +
2201 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2202 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2203 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
a1751b22 2204
e7392364
SG		 2205 il_write_targ_mem(il,
2206 il->scd_base_addr +
2207 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2208 (SCD_FRAME_LIMIT <<
2209 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2210 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
a1751b22
SG		 2211
2212 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2213
2214 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2215 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2216
2217 spin_unlock_irqrestore(&il->lock, flags);
2218
2219 return 0;
2220}
2221
e7392364
SG		 2222int
2223il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2224 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
a1751b22
SG		 2225{
2226 int sta_id;
2227 int tx_fifo;
2228 int txq_id;
2229 int ret;
2230 unsigned long flags;
2231 struct il_tid_data *tid_data;
2232
83007196
SG		 2233 /* FIXME: warning if tx fifo not found ? */
2234 tx_fifo = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2235 if (unlikely(tx_fifo < 0))
2236 return tx_fifo;
2237
53611e05 2238 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
a1751b22
SG		 2239
2240 sta_id = il_sta_id(sta);
2241 if (sta_id == IL_INVALID_STATION) {
2242 IL_ERR("Start AGG on invalid station\n");
2243 return -ENXIO;
2244 }
2245 if (unlikely(tid >= MAX_TID_COUNT))
2246 return -EINVAL;
2247
2248 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2249 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2250 return -ENXIO;
2251 }
2252
2253 txq_id = il4965_txq_ctx_activate_free(il);
2254 if (txq_id == -1) {
2255 IL_ERR("No free aggregation queue available\n");
2256 return -ENXIO;
2257 }
2258
2259 spin_lock_irqsave(&il->sta_lock, flags);
2260 tid_data = &il->stations[sta_id].tid[tid];
2261 *ssn = SEQ_TO_SN(tid_data->seq_number);
2262 tid_data->agg.txq_id = txq_id;
e7392364 2263 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
a1751b22
SG		 2264 spin_unlock_irqrestore(&il->sta_lock, flags);
2265
e7392364 2266 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
a1751b22
SG		 2267 if (ret)
2268 return ret;
2269
2270 spin_lock_irqsave(&il->sta_lock, flags);
2271 tid_data = &il->stations[sta_id].tid[tid];
2272 if (tid_data->tfds_in_queue == 0) {
2273 D_HT("HW queue is empty\n");
2274 tid_data->agg.state = IL_AGG_ON;
2275 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2276 } else {
e7392364
SG		 2277 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2278 tid_data->tfds_in_queue);
a1751b22
SG		 2279 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2280 }
2281 spin_unlock_irqrestore(&il->sta_lock, flags);
2282 return ret;
2283}
2284
2285/**
2286 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2287 * il->lock must be held by the caller
2288 */
e7392364
SG		 2289static int
2290il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
a1751b22
SG		 2291{
2292 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2293 (IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2294 il->cfg->num_of_ampdu_queues <= txq_id)) {
e7392364 2295 IL_WARN("queue number out of range: %d, must be %d to %d\n",
a1751b22
SG		 2296 txq_id, IL49_FIRST_AMPDU_QUEUE,
2297 IL49_FIRST_AMPDU_QUEUE +
89ef1ed2 2298 il->cfg->num_of_ampdu_queues - 1);
a1751b22
SG		 2299 return -EINVAL;
2300 }
2301
2302 il4965_tx_queue_stop_scheduler(il, txq_id);
2303
e7392364 2304 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
a1751b22
SG		 2305
2306 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2307 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2308 /* supposes that ssn_idx is valid (!= 0xFFF) */
2309 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2310
e7392364 2311 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
a1751b22
SG		 2312 il_txq_ctx_deactivate(il, txq_id);
2313 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2314
2315 return 0;
2316}
2317
e7392364
SG		 2318int
2319il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2320 struct ieee80211_sta *sta, u16 tid)
a1751b22
SG		 2321{
2322 int tx_fifo_id, txq_id, sta_id, ssn;
2323 struct il_tid_data *tid_data;
2324 int write_ptr, read_ptr;
2325 unsigned long flags;
2326
83007196
SG		 2327 /* FIXME: warning if tx_fifo_id not found ? */
2328 tx_fifo_id = il4965_get_fifo_from_tid(tid);
a1751b22
SG		 2329 if (unlikely(tx_fifo_id < 0))
2330 return tx_fifo_id;
2331
2332 sta_id = il_sta_id(sta);
2333
2334 if (sta_id == IL_INVALID_STATION) {
2335 IL_ERR("Invalid station for AGG tid %d\n", tid);
2336 return -ENXIO;
2337 }
2338
2339 spin_lock_irqsave(&il->sta_lock, flags);
2340
2341 tid_data = &il->stations[sta_id].tid[tid];
2342 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2343 txq_id = tid_data->agg.txq_id;
2344
2345 switch (il->stations[sta_id].tid[tid].agg.state) {
2346 case IL_EMPTYING_HW_QUEUE_ADDBA:
2347 /*
2348 * This can happen if the peer stops aggregation
2349 * again before we've had a chance to drain the
2350 * queue we selected previously, i.e. before the
2351 * session was really started completely.
2352 */
2353 D_HT("AGG stop before setup done\n");
2354 goto turn_off;
2355 case IL_AGG_ON:
2356 break;
2357 default:
2358 IL_WARN("Stopping AGG while state not ON or starting\n");
2359 }
2360
2361 write_ptr = il->txq[txq_id].q.write_ptr;
2362 read_ptr = il->txq[txq_id].q.read_ptr;
2363
2364 /* The queue is not empty */
2365 if (write_ptr != read_ptr) {
2366 D_HT("Stopping a non empty AGG HW QUEUE\n");
2367 il->stations[sta_id].tid[tid].agg.state =
e7392364 2368 IL_EMPTYING_HW_QUEUE_DELBA;
a1751b22
SG		 2369 spin_unlock_irqrestore(&il->sta_lock, flags);
2370 return 0;
2371 }
2372
2373 D_HT("HW queue is empty\n");
e7392364 2374turn_off:
a1751b22
SG		 2375 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2376
2377 /* do not restore/save irqs */
2378 spin_unlock(&il->sta_lock);
2379 spin_lock(&il->lock);
2380
2381 /*
2382 * the only reason this call can fail is queue number out of range,
2383 * which can happen if uCode is reloaded and all the station
2384 * information are lost. if it is outside the range, there is no need
2385 * to deactivate the uCode queue, just return "success" to allow
2386 * mac80211 to clean up it own data.
2387 */
2388 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2389 spin_unlock_irqrestore(&il->lock, flags);
2390
2391 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2392
2393 return 0;
2394}
2395
e7392364
SG		 2396int
2397il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
a1751b22
SG		 2398{
2399 struct il_queue *q = &il->txq[txq_id].q;
2400 u8 *addr = il->stations[sta_id].sta.sta.addr;
2401 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
a1751b22
SG		 2402
2403 lockdep_assert_held(&il->sta_lock);
2404
2405 switch (il->stations[sta_id].tid[tid].agg.state) {
2406 case IL_EMPTYING_HW_QUEUE_DELBA:
2407 /* We are reclaiming the last packet of the */
2408 /* aggregated HW queue */
e7392364 2409 if (txq_id == tid_data->agg.txq_id &&
a1751b22
SG		 2410 q->read_ptr == q->write_ptr) {
2411 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
83007196 2412 int tx_fifo = il4965_get_fifo_from_tid(tid);
e7392364 2413 D_HT("HW queue empty: continue DELBA flow\n");
a1751b22
SG		 2414 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2415 tid_data->agg.state = IL_AGG_OFF;
83007196 2416 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2417 }
2418 break;
2419 case IL_EMPTYING_HW_QUEUE_ADDBA:
2420 /* We are reclaiming the last packet of the queue */
2421 if (tid_data->tfds_in_queue == 0) {
e7392364 2422 D_HT("HW queue empty: continue ADDBA flow\n");
a1751b22 2423 tid_data->agg.state = IL_AGG_ON;
83007196 2424 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
a1751b22
SG		 2425 }
2426 break;
2427 }
2428
2429 return 0;
2430}
2431
e7392364 2432static void
83007196 2433il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
a1751b22
SG		 2434{
2435 struct ieee80211_sta *sta;
2436 struct il_station_priv *sta_priv;
2437
2438 rcu_read_lock();
83007196 2439 sta = ieee80211_find_sta(il->vif, addr1);
a1751b22
SG		 2440 if (sta) {
2441 sta_priv = (void *)sta->drv_priv;
2442 /* avoid atomic ops if this isn't a client */
2443 if (sta_priv->client &&
2444 atomic_dec_return(&sta_priv->pending_frames) == 0)
2445 ieee80211_sta_block_awake(il->hw, sta, false);
2446 }
2447 rcu_read_unlock();
2448}
2449
2450static void
00ea99e1 2451il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
a1751b22 2452{
00ea99e1 2453 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
a1751b22
SG		 2454
2455 if (!is_agg)
83007196 2456 il4965_non_agg_tx_status(il, hdr->addr1);
a1751b22 2457
00ea99e1 2458 ieee80211_tx_status_irqsafe(il->hw, skb);
a1751b22
SG		 2459}
2460
e7392364
SG		 2461int
2462il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
a1751b22
SG		 2463{
2464 struct il_tx_queue *txq = &il->txq[txq_id];
2465 struct il_queue *q = &txq->q;
a1751b22
SG		 2466 int nfreed = 0;
2467 struct ieee80211_hdr *hdr;
00ea99e1 2468 struct sk_buff *skb;
a1751b22
SG		 2469
2470 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2471 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 2472 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2473 q->write_ptr, q->read_ptr);
a1751b22
SG		 2474 return 0;
2475 }
2476
e7392364 2477 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
a1751b22
SG		 2478 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2479
00ea99e1 2480 skb = txq->skbs[txq->q.read_ptr];
a1751b22 2481
00ea99e1 2482 if (WARN_ON_ONCE(skb == NULL))
a1751b22
SG		 2483 continue;
2484
00ea99e1 2485 hdr = (struct ieee80211_hdr *) skb->data;
a1751b22
SG		 2486 if (ieee80211_is_data_qos(hdr->frame_control))
2487 nfreed++;
2488
00ea99e1 2489 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
a1751b22 2490
00ea99e1 2491 txq->skbs[txq->q.read_ptr] = NULL;
1600b875 2492 il->ops->txq_free_tfd(il, txq);
a1751b22
SG		 2493 }
2494 return nfreed;
2495}
2496
2497/**
2498 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2499 *
2500 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2501 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2502 */
e7392364
SG		 2503static int
2504il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2505 struct il_compressed_ba_resp *ba_resp)
a1751b22
SG		 2506{
2507 int i, sh, ack;
2508 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2509 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2510 int successes = 0;
2511 struct ieee80211_tx_info *info;
2512 u64 bitmap, sent_bitmap;
2513
e7392364 2514 if (unlikely(!agg->wait_for_ba)) {
a1751b22
SG		 2515 if (unlikely(ba_resp->bitmap))
2516 IL_ERR("Received BA when not expected\n");
2517 return -EINVAL;
2518 }
2519
2520 /* Mark that the expected block-ack response arrived */
2521 agg->wait_for_ba = 0;
e7392364 2522 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
a1751b22
SG		 2523
2524 /* Calculate shift to align block-ack bits with our Tx win bits */
2525 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
e7392364 2526 if (sh < 0) /* tbw something is wrong with indices */
a1751b22
SG		 2527 sh += 0x100;
2528
2529 if (agg->frame_count > (64 - sh)) {
2530 D_TX_REPLY("more frames than bitmap size");
2531 return -1;
2532 }
2533
2534 /* don't use 64-bit values for now */
2535 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2536
2537 /* check for success or failure according to the
2538 * transmitted bitmap and block-ack bitmap */
2539 sent_bitmap = bitmap & agg->bitmap;
2540
2541 /* For each frame attempted in aggregation,
2542 * update driver's record of tx frame's status. */
2543 i = 0;
2544 while (sent_bitmap) {
2545 ack = sent_bitmap & 1ULL;
2546 successes += ack;
e7392364
SG		 2547 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2548 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
a1751b22
SG		 2549 sent_bitmap >>= 1;
2550 ++i;
2551 }
2552
e7392364 2553 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
a1751b22 2554
00ea99e1 2555 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
a1751b22
SG		 2556 memset(&info->status, 0, sizeof(info->status));
2557 info->flags |= IEEE80211_TX_STAT_ACK;
2558 info->flags |= IEEE80211_TX_STAT_AMPDU;
2559 info->status.ampdu_ack_len = successes;
2560 info->status.ampdu_len = agg->frame_count;
2561 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2562
2563 return 0;
2564}
2565
3dfea27d
SG		 2566static inline bool
2567il4965_is_tx_success(u32 status)
2568{
2569 status &= TX_STATUS_MSK;
2570 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2571}
2572
2573static u8
2574il4965_find_station(struct il_priv *il, const u8 *addr)
2575{
2576 int i;
2577 int start = 0;
2578 int ret = IL_INVALID_STATION;
2579 unsigned long flags;
2580
2581 if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2582 start = IL_STA_ID;
2583
2584 if (is_broadcast_ether_addr(addr))
2585 return il->hw_params.bcast_id;
2586
2587 spin_lock_irqsave(&il->sta_lock, flags);
2588 for (i = start; i < il->hw_params.max_stations; i++)
2589 if (il->stations[i].used &&
2e42e474 2590 ether_addr_equal(il->stations[i].sta.sta.addr, addr)) {
3dfea27d
SG		 2591 ret = i;
2592 goto out;
2593 }
2594
2595 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2596
2597out:
2598 /*
2599 * It may be possible that more commands interacting with stations
2600 * arrive before we completed processing the adding of
2601 * station
2602 */
2603 if (ret != IL_INVALID_STATION &&
2604 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2605 ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2606 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2607 IL_ERR("Requested station info for sta %d before ready.\n",
2608 ret);
2609 ret = IL_INVALID_STATION;
2610 }
2611 spin_unlock_irqrestore(&il->sta_lock, flags);
2612 return ret;
2613}
2614
2615static int
2616il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2617{
2618 if (il->iw_mode == NL80211_IFTYPE_STATION)
2619 return IL_AP_ID;
2620 else {
2621 u8 *da = ieee80211_get_DA(hdr);
2622
2623 return il4965_find_station(il, da);
2624 }
2625}
2626
2627static inline u32
2628il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2629{
2630 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
2631}
2632
2633static inline u32
2634il4965_tx_status_to_mac80211(u32 status)
2635{
2636 status &= TX_STATUS_MSK;
2637
2638 switch (status) {
2639 case TX_STATUS_SUCCESS:
2640 case TX_STATUS_DIRECT_DONE:
2641 return IEEE80211_TX_STAT_ACK;
2642 case TX_STATUS_FAIL_DEST_PS:
2643 return IEEE80211_TX_STAT_TX_FILTERED;
2644 default:
2645 return 0;
2646 }
2647}
2648
2649/**
2650 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2651 */
2652static int
2653il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2654 struct il4965_tx_resp *tx_resp, int txq_id,
2655 u16 start_idx)
2656{
2657 u16 status;
2658 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2659 struct ieee80211_tx_info *info = NULL;
2660 struct ieee80211_hdr *hdr = NULL;
2661 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2662 int i, sh, idx;
2663 u16 seq;
2664 if (agg->wait_for_ba)
2665 D_TX_REPLY("got tx response w/o block-ack\n");
2666
2667 agg->frame_count = tx_resp->frame_count;
2668 agg->start_idx = start_idx;
2669 agg->rate_n_flags = rate_n_flags;
2670 agg->bitmap = 0;
2671
2672 /* num frames attempted by Tx command */
2673 if (agg->frame_count == 1) {
2674 /* Only one frame was attempted; no block-ack will arrive */
2675 status = le16_to_cpu(frame_status[0].status);
2676 idx = start_idx;
2677
2678 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2679 agg->frame_count, agg->start_idx, idx);
2680
2681 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2682 info->status.rates[0].count = tx_resp->failure_frame + 1;
2683 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2684 info->flags |= il4965_tx_status_to_mac80211(status);
2685 il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2686
2687 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2688 tx_resp->failure_frame);
2689 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2690
2691 agg->wait_for_ba = 0;
2692 } else {
2693 /* Two or more frames were attempted; expect block-ack */
2694 u64 bitmap = 0;
2695 int start = agg->start_idx;
2696 struct sk_buff *skb;
2697
2698 /* Construct bit-map of pending frames within Tx win */
2699 for (i = 0; i < agg->frame_count; i++) {
2700 u16 sc;
2701 status = le16_to_cpu(frame_status[i].status);
2702 seq = le16_to_cpu(frame_status[i].sequence);
2703 idx = SEQ_TO_IDX(seq);
2704 txq_id = SEQ_TO_QUEUE(seq);
2705
2706 if (status &
2707 (AGG_TX_STATE_FEW_BYTES_MSK |
2708 AGG_TX_STATE_ABORT_MSK))
2709 continue;
2710
2711 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2712 agg->frame_count, txq_id, idx);
2713
2714 skb = il->txq[txq_id].skbs[idx];
2715 if (WARN_ON_ONCE(skb == NULL))
2716 return -1;
2717 hdr = (struct ieee80211_hdr *) skb->data;
2718
2719 sc = le16_to_cpu(hdr->seq_ctrl);
2720 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2721 IL_ERR("BUG_ON idx doesn't match seq control"
2722 " idx=%d, seq_idx=%d, seq=%d\n", idx,
2723 SEQ_TO_SN(sc), hdr->seq_ctrl);
2724 return -1;
2725 }
2726
2727 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
2728 SEQ_TO_SN(sc));
2729
2730 sh = idx - start;
2731 if (sh > 64) {
2732 sh = (start - idx) + 0xff;
2733 bitmap = bitmap << sh;
2734 sh = 0;
2735 start = idx;
2736 } else if (sh < -64)
2737 sh = 0xff - (start - idx);
2738 else if (sh < 0) {
2739 sh = start - idx;
2740 start = idx;
2741 bitmap = bitmap << sh;
2742 sh = 0;
2743 }
2744 bitmap |= 1ULL << sh;
2745 D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2746 (unsigned long long)bitmap);
2747 }
2748
2749 agg->bitmap = bitmap;
2750 agg->start_idx = start;
2751 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2752 agg->frame_count, agg->start_idx,
2753 (unsigned long long)agg->bitmap);
2754
2755 if (bitmap)
2756 agg->wait_for_ba = 1;
2757 }
2758 return 0;
2759}
2760
2761/**
2762 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2763 */
2764static void
2765il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2766{
2767 struct il_rx_pkt *pkt = rxb_addr(rxb);
2768 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2769 int txq_id = SEQ_TO_QUEUE(sequence);
2770 int idx = SEQ_TO_IDX(sequence);
2771 struct il_tx_queue *txq = &il->txq[txq_id];
2772 struct sk_buff *skb;
2773 struct ieee80211_hdr *hdr;
2774 struct ieee80211_tx_info *info;
2775 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2776 u32 status = le32_to_cpu(tx_resp->u.status);
2777 int uninitialized_var(tid);
2778 int sta_id;
2779 int freed;
2780 u8 *qc = NULL;
2781 unsigned long flags;
2782
2783 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2784 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2785 "is out of range [0-%d] %d %d\n", txq_id, idx,
2786 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2787 return;
2788 }
2789
2790 txq->time_stamp = jiffies;
2791
2792 skb = txq->skbs[txq->q.read_ptr];
2793 info = IEEE80211_SKB_CB(skb);
2794 memset(&info->status, 0, sizeof(info->status));
2795
2796 hdr = (struct ieee80211_hdr *) skb->data;
2797 if (ieee80211_is_data_qos(hdr->frame_control)) {
2798 qc = ieee80211_get_qos_ctl(hdr);
2799 tid = qc[0] & 0xf;
2800 }
2801
2802 sta_id = il4965_get_ra_sta_id(il, hdr);
2803 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2804 IL_ERR("Station not known\n");
2805 return;
2806 }
2807
2808 spin_lock_irqsave(&il->sta_lock, flags);
2809 if (txq->sched_retry) {
2810 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2811 struct il_ht_agg *agg = NULL;
2812 WARN_ON(!qc);
2813
2814 agg = &il->stations[sta_id].tid[tid].agg;
2815
2816 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2817
2818 /* check if BAR is needed */
2819 if (tx_resp->frame_count == 1 &&
2820 !il4965_is_tx_success(status))
2821 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2822
2823 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2824 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2825 D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2826 "%d idx %d\n", scd_ssn, idx);
2827 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2828 if (qc)
2829 il4965_free_tfds_in_queue(il, sta_id, tid,
2830 freed);
2831
2832 if (il->mac80211_registered &&
2833 il_queue_space(&txq->q) > txq->q.low_mark &&
2834 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2835 il_wake_queue(il, txq);
2836 }
2837 } else {
2838 info->status.rates[0].count = tx_resp->failure_frame + 1;
2839 info->flags |= il4965_tx_status_to_mac80211(status);
2840 il4965_hwrate_to_tx_control(il,
2841 le32_to_cpu(tx_resp->rate_n_flags),
2842 info);
2843
2844 D_TX_REPLY("TXQ %d status %s (0x%08x) "
2845 "rate_n_flags 0x%x retries %d\n", txq_id,
2846 il4965_get_tx_fail_reason(status), status,
2847 le32_to_cpu(tx_resp->rate_n_flags),
2848 tx_resp->failure_frame);
2849
2850 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2851 if (qc && likely(sta_id != IL_INVALID_STATION))
2852 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2853 else if (sta_id == IL_INVALID_STATION)
2854 D_TX_REPLY("Station not known\n");
2855
2856 if (il->mac80211_registered &&
2857 il_queue_space(&txq->q) > txq->q.low_mark)
2858 il_wake_queue(il, txq);
2859 }
2860 if (qc && likely(sta_id != IL_INVALID_STATION))
2861 il4965_txq_check_empty(il, sta_id, tid, txq_id);
2862
2863 il4965_check_abort_status(il, tx_resp->frame_count, status);
2864
2865 spin_unlock_irqrestore(&il->sta_lock, flags);
2866}
2867
a1751b22
SG		 2868/**
2869 * translate ucode response to mac80211 tx status control values
2870 */
e7392364
SG		 2871void
2872il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2873 struct ieee80211_tx_info *info)
a1751b22 2874{
d748b464 2875 struct ieee80211_tx_rate *r = &info->status.rates[0];
a1751b22 2876
d748b464 2877 info->status.antenna =
e7392364 2878 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
a1751b22
SG		 2879 if (rate_n_flags & RATE_MCS_HT_MSK)
2880 r->flags |= IEEE80211_TX_RC_MCS;
2881 if (rate_n_flags & RATE_MCS_GF_MSK)
2882 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2883 if (rate_n_flags & RATE_MCS_HT40_MSK)
2884 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2885 if (rate_n_flags & RATE_MCS_DUP_MSK)
2886 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2887 if (rate_n_flags & RATE_MCS_SGI_MSK)
2888 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2889 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2890}
2891
2892/**
6e9848b4 2893 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
a1751b22
SG		 2894 *
2895 * Handles block-acknowledge notification from device, which reports success
2896 * of frames sent via aggregation.
2897 */
e7392364
SG		 2898void
2899il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
a1751b22
SG		 2900{
2901 struct il_rx_pkt *pkt = rxb_addr(rxb);
2902 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2903 struct il_tx_queue *txq = NULL;
2904 struct il_ht_agg *agg;
2905 int idx;
2906 int sta_id;
2907 int tid;
2908 unsigned long flags;
2909
2910 /* "flow" corresponds to Tx queue */
2911 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2912
2913 /* "ssn" is start of block-ack Tx win, corresponds to idx
2914 * (in Tx queue's circular buffer) of first TFD/frame in win */
2915 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2916
2917 if (scd_flow >= il->hw_params.max_txq_num) {
e7392364 2918 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
a1751b22
SG		 2919 return;
2920 }
2921
2922 txq = &il->txq[scd_flow];
2923 sta_id = ba_resp->sta_id;
2924 tid = ba_resp->tid;
2925 agg = &il->stations[sta_id].tid[tid].agg;
2926 if (unlikely(agg->txq_id != scd_flow)) {
2927 /*
2928 * FIXME: this is a uCode bug which need to be addressed,
2929 * log the information and return for now!
2930 * since it is possible happen very often and in order
2931 * not to fill the syslog, don't enable the logging by default
2932 */
e7392364
SG		 2933 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2934 scd_flow, agg->txq_id);
a1751b22
SG		 2935 return;
2936 }
2937
2938 /* Find idx just before block-ack win */
2939 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2940
2941 spin_lock_irqsave(&il->sta_lock, flags);
2942
e7392364 2943 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
1722f8e1 2944 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
e7392364
SG		 2945 ba_resp->sta_id);
2946 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2947 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2948 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2949 ba_resp->scd_flow, ba_resp->scd_ssn);
2950 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2951 (unsigned long long)agg->bitmap);
a1751b22
SG		 2952
2953 /* Update driver's record of ACK vs. not for each frame in win */
2954 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2955
2956 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2957 * block-ack win (we assume that they've been successfully
2958 * transmitted ... if not, it's too late anyway). */
2959 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2960 /* calculate mac80211 ampdu sw queue to wake */
2961 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2962 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2963
2964 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2965 il->mac80211_registered &&
2966 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2967 il_wake_queue(il, txq);
2968
2969 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2970 }
2971
2972 spin_unlock_irqrestore(&il->sta_lock, flags);
2973}
2974
2975#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2976const char *
2977il4965_get_tx_fail_reason(u32 status)
a1751b22
SG		 2978{
2979#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2980#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2981
2982 switch (status & TX_STATUS_MSK) {
2983 case TX_STATUS_SUCCESS:
2984 return "SUCCESS";
e7392364
SG		 2985 TX_STATUS_POSTPONE(DELAY);
2986 TX_STATUS_POSTPONE(FEW_BYTES);
2987 TX_STATUS_POSTPONE(QUIET_PERIOD);
2988 TX_STATUS_POSTPONE(CALC_TTAK);
2989 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2990 TX_STATUS_FAIL(SHORT_LIMIT);
2991 TX_STATUS_FAIL(LONG_LIMIT);
2992 TX_STATUS_FAIL(FIFO_UNDERRUN);
2993 TX_STATUS_FAIL(DRAIN_FLOW);
2994 TX_STATUS_FAIL(RFKILL_FLUSH);
2995 TX_STATUS_FAIL(LIFE_EXPIRE);
2996 TX_STATUS_FAIL(DEST_PS);
2997 TX_STATUS_FAIL(HOST_ABORTED);
2998 TX_STATUS_FAIL(BT_RETRY);
2999 TX_STATUS_FAIL(STA_INVALID);
3000 TX_STATUS_FAIL(FRAG_DROPPED);
3001 TX_STATUS_FAIL(TID_DISABLE);
3002 TX_STATUS_FAIL(FIFO_FLUSHED);
3003 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
3004 TX_STATUS_FAIL(PASSIVE_NO_RX);
3005 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
a1751b22
SG		 3006 }
3007
3008 return "UNKNOWN";
3009
3010#undef TX_STATUS_FAIL
3011#undef TX_STATUS_POSTPONE
3012}
3013#endif /* CONFIG_IWLEGACY_DEBUG */
3014
eb3cdfb7
SG		 3015static struct il_link_quality_cmd *
3016il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
3017{
3018 int i, r;
3019 struct il_link_quality_cmd *link_cmd;
3020 u32 rate_flags = 0;
3021 __le32 rate_n_flags;
3022
3023 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3024 if (!link_cmd) {
3025 IL_ERR("Unable to allocate memory for LQ cmd.\n");
3026 return NULL;
3027 }
3028 /* Set up the rate scaling to start at selected rate, fall back
3029 * all the way down to 1M in IEEE order, and then spin on 1M */
3030 if (il->band == IEEE80211_BAND_5GHZ)
3031 r = RATE_6M_IDX;
3032 else
3033 r = RATE_1M_IDX;
3034
3035 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3036 rate_flags |= RATE_MCS_CCK_MSK;
3037
e7392364
SG		 3038 rate_flags |=
3039 il4965_first_antenna(il->hw_params.
3040 valid_tx_ant) << RATE_MCS_ANT_POS;
616107ed 3041 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
eb3cdfb7
SG		 3042 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3043 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3044
3045 link_cmd->general_params.single_stream_ant_msk =
e7392364 3046 il4965_first_antenna(il->hw_params.valid_tx_ant);
eb3cdfb7
SG		 3047
3048 link_cmd->general_params.dual_stream_ant_msk =
e7392364
SG		 3049 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3050 valid_tx_ant);
eb3cdfb7
SG		 3051 if (!link_cmd->general_params.dual_stream_ant_msk) {
3052 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3053 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3054 link_cmd->general_params.dual_stream_ant_msk =
e7392364 3055 il->hw_params.valid_tx_ant;
eb3cdfb7
SG		 3056 }
3057
3058 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3059 link_cmd->agg_params.agg_time_limit =
e7392364 3060 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
eb3cdfb7
SG		 3061
3062 link_cmd->sta_id = sta_id;
3063
3064 return link_cmd;
3065}
3066
3067/*
3068 * il4965_add_bssid_station - Add the special IBSS BSSID station
3069 *
3070 * Function sleeps.
3071 */
3072int
83007196 3073il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
eb3cdfb7
SG		 3074{
3075 int ret;
3076 u8 sta_id;
3077 struct il_link_quality_cmd *link_cmd;
3078 unsigned long flags;
3079
3080 if (sta_id_r)
3081 *sta_id_r = IL_INVALID_STATION;
3082
83007196 3083 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
eb3cdfb7
SG		 3084 if (ret) {
3085 IL_ERR("Unable to add station %pM\n", addr);
3086 return ret;
3087 }
3088
3089 if (sta_id_r)
3090 *sta_id_r = sta_id;
3091
3092 spin_lock_irqsave(&il->sta_lock, flags);
3093 il->stations[sta_id].used |= IL_STA_LOCAL;
3094 spin_unlock_irqrestore(&il->sta_lock, flags);
3095
3096 /* Set up default rate scaling table in device's station table */
3097 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3098 if (!link_cmd) {
e7392364
SG		 3099 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3100 addr);
eb3cdfb7
SG		 3101 return -ENOMEM;
3102 }
3103
83007196 3104 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
eb3cdfb7
SG		 3105 if (ret)
3106 IL_ERR("Link quality command failed (%d)\n", ret);
3107
3108 spin_lock_irqsave(&il->sta_lock, flags);
3109 il->stations[sta_id].lq = link_cmd;
3110 spin_unlock_irqrestore(&il->sta_lock, flags);
3111
3112 return 0;
3113}
3114
e7392364 3115static int
83007196 3116il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
eb3cdfb7 3117{
d735f921 3118 int i;
eb3cdfb7
SG		 3119 u8 buff[sizeof(struct il_wep_cmd) +
3120 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3121 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
e7392364 3122 size_t cmd_size = sizeof(struct il_wep_cmd);
eb3cdfb7 3123 struct il_host_cmd cmd = {
d98e2942 3124 .id = C_WEPKEY,
eb3cdfb7
SG		 3125 .data = wep_cmd,
3126 .flags = CMD_SYNC,
3127 };
d735f921 3128 bool not_empty = false;
eb3cdfb7
SG		 3129
3130 might_sleep();
3131
e7392364
SG		 3132 memset(wep_cmd, 0,
3133 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
eb3cdfb7 3134
e7392364 3135 for (i = 0; i < WEP_KEYS_MAX; i++) {
d735f921
SG		 3136 u8 key_size = il->_4965.wep_keys[i].key_size;
3137
eb3cdfb7 3138 wep_cmd->key[i].key_idx = i;
d735f921 3139 if (key_size) {
eb3cdfb7 3140 wep_cmd->key[i].key_offset = i;
d735f921
SG		 3141 not_empty = true;
3142 } else
eb3cdfb7 3143 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
eb3cdfb7 3144
d735f921
SG		 3145 wep_cmd->key[i].key_size = key_size;
3146 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
eb3cdfb7
SG		 3147 }
3148
3149 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3150 wep_cmd->num_keys = WEP_KEYS_MAX;
3151
3152 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
eb3cdfb7
SG		 3153 cmd.len = cmd_size;
3154
3155 if (not_empty || send_if_empty)
3156 return il_send_cmd(il, &cmd);
3157 else
3158 return 0;
3159}
3160
e7392364 3161int
83007196 3162il4965_restore_default_wep_keys(struct il_priv *il)
eb3cdfb7
SG		 3163{
3164 lockdep_assert_held(&il->mutex);
3165
83007196 3166 return il4965_static_wepkey_cmd(il, false);
eb3cdfb7
SG		 3167}
3168
e7392364 3169int
83007196 3170il4965_remove_default_wep_key(struct il_priv *il,
e7392364 3171 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3172{
3173 int ret;
d735f921 3174 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3175
3176 lockdep_assert_held(&il->mutex);
3177
d735f921 3178 D_WEP("Removing default WEP key: idx=%d\n", idx);
eb3cdfb7 3179
d735f921 3180 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
eb3cdfb7 3181 if (il_is_rfkill(il)) {
e7392364 3182 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
eb3cdfb7
SG		 3183 /* but keys in device are clear anyway so return success */
3184 return 0;
3185 }
83007196 3186 ret = il4965_static_wepkey_cmd(il, 1);
d735f921 3187 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
eb3cdfb7
SG		 3188
3189 return ret;
3190}
3191
e7392364 3192int
83007196 3193il4965_set_default_wep_key(struct il_priv *il,
e7392364 3194 struct ieee80211_key_conf *keyconf)
eb3cdfb7
SG		 3195{
3196 int ret;
d735f921
SG		 3197 int len = keyconf->keylen;
3198 int idx = keyconf->keyidx;
eb3cdfb7
SG		 3199
3200 lockdep_assert_held(&il->mutex);
3201
d735f921 3202 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
eb3cdfb7
SG		 3203 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3204 return -EINVAL;
3205 }
3206
3207 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3208 keyconf->hw_key_idx = HW_KEY_DEFAULT;
8f9e5645 3209 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
eb3cdfb7 3210
d735f921
SG		 3211 il->_4965.wep_keys[idx].key_size = len;
3212 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
eb3cdfb7 3213
83007196 3214 ret = il4965_static_wepkey_cmd(il, false);
eb3cdfb7 3215
d735f921 3216 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
eb3cdfb7
SG		 3217 return ret;
3218}
3219
e7392364 3220static int
83007196 3221il4965_set_wep_dynamic_key_info(struct il_priv *il,
e7392364 3222 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3223{
3224 unsigned long flags;
3225 __le16 key_flags = 0;
3226 struct il_addsta_cmd sta_cmd;
3227
3228 lockdep_assert_held(&il->mutex);
3229
3230 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3231
3232 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3233 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3234 key_flags &= ~STA_KEY_FLG_INVALID;
3235
3236 if (keyconf->keylen == WEP_KEY_LEN_128)
3237 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3238
b16db50a 3239 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3240 key_flags |= STA_KEY_MULTICAST_MSK;
3241
3242 spin_lock_irqsave(&il->sta_lock, flags);
3243
3244 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3245 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3246 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3247
e7392364 3248 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3249
e7392364
SG		 3250 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3251 keyconf->keylen);
eb3cdfb7 3252
e7392364
SG		 3253 if ((il->stations[sta_id].sta.key.
3254 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3255 il->stations[sta_id].sta.key.key_offset =
e7392364 3256 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3257 /* else, we are overriding an existing key => no need to allocated room
3258 * in uCode. */
3259
3260 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3261 "no space for a new key");
eb3cdfb7
SG		 3262
3263 il->stations[sta_id].sta.key.key_flags = key_flags;
3264 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3265 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3266
3267 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3268 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3269 spin_unlock_irqrestore(&il->sta_lock, flags);
3270
3271 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3272}
3273
e7392364
SG		 3274static int
3275il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
e7392364 3276 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3277{
3278 unsigned long flags;
3279 __le16 key_flags = 0;
3280 struct il_addsta_cmd sta_cmd;
3281
3282 lockdep_assert_held(&il->mutex);
3283
3284 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3285 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3286 key_flags &= ~STA_KEY_FLG_INVALID;
3287
b16db50a 3288 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3289 key_flags |= STA_KEY_MULTICAST_MSK;
3290
3291 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3292
3293 spin_lock_irqsave(&il->sta_lock, flags);
3294 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3295 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3296
e7392364 3297 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3298
e7392364 3299 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
eb3cdfb7 3300
e7392364
SG		 3301 if ((il->stations[sta_id].sta.key.
3302 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3303 il->stations[sta_id].sta.key.key_offset =
e7392364 3304 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3305 /* else, we are overriding an existing key => no need to allocated room
3306 * in uCode. */
3307
3308 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3309 "no space for a new key");
eb3cdfb7
SG		 3310
3311 il->stations[sta_id].sta.key.key_flags = key_flags;
3312 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3313 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3314
3315 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3316 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3317 spin_unlock_irqrestore(&il->sta_lock, flags);
3318
3319 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3320}
3321
e7392364
SG		 3322static int
3323il4965_set_tkip_dynamic_key_info(struct il_priv *il,
e7392364 3324 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3325{
3326 unsigned long flags;
3327 int ret = 0;
3328 __le16 key_flags = 0;
3329
3330 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3331 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3332 key_flags &= ~STA_KEY_FLG_INVALID;
3333
b16db50a 3334 if (sta_id == il->hw_params.bcast_id)
eb3cdfb7
SG		 3335 key_flags |= STA_KEY_MULTICAST_MSK;
3336
3337 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3338 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3339
3340 spin_lock_irqsave(&il->sta_lock, flags);
3341
3342 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3343 il->stations[sta_id].keyinfo.keylen = 16;
3344
e7392364
SG		 3345 if ((il->stations[sta_id].sta.key.
3346 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
eb3cdfb7 3347 il->stations[sta_id].sta.key.key_offset =
e7392364 3348 il_get_free_ucode_key_idx(il);
eb3cdfb7
SG		 3349 /* else, we are overriding an existing key => no need to allocated room
3350 * in uCode. */
3351
3352 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 3353 "no space for a new key");
eb3cdfb7
SG		 3354
3355 il->stations[sta_id].sta.key.key_flags = key_flags;
3356
eb3cdfb7
SG		 3357 /* This copy is acutally not needed: we get the key with each TX */
3358 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3359
3360 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3361
3362 spin_unlock_irqrestore(&il->sta_lock, flags);
3363
3364 return ret;
3365}
3366
e7392364 3367void
83007196
SG		 3368il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3369 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
eb3cdfb7
SG		 3370{
3371 u8 sta_id;
3372 unsigned long flags;
3373 int i;
3374
3375 if (il_scan_cancel(il)) {
3376 /* cancel scan failed, just live w/ bad key and rely
3377 briefly on SW decryption */
3378 return;
3379 }
3380
83007196 3381 sta_id = il_sta_id_or_broadcast(il, sta);
eb3cdfb7
SG		 3382 if (sta_id == IL_INVALID_STATION)
3383 return;
3384
3385 spin_lock_irqsave(&il->sta_lock, flags);
3386
3387 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3388
3389 for (i = 0; i < 5; i++)
3390 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
e7392364 3391 cpu_to_le16(phase1key[i]);
eb3cdfb7
SG		 3392
3393 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3394 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3395
3396 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3397
3398 spin_unlock_irqrestore(&il->sta_lock, flags);
eb3cdfb7
SG		 3399}
3400
e7392364 3401int
83007196 3402il4965_remove_dynamic_key(struct il_priv *il,
e7392364 3403 struct ieee80211_key_conf *keyconf, u8 sta_id)
eb3cdfb7
SG		 3404{
3405 unsigned long flags;
3406 u16 key_flags;
3407 u8 keyidx;
3408 struct il_addsta_cmd sta_cmd;
3409
3410 lockdep_assert_held(&il->mutex);
3411
d735f921 3412 il->_4965.key_mapping_keys--;
eb3cdfb7
SG		 3413
3414 spin_lock_irqsave(&il->sta_lock, flags);
3415 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3416 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3417
e7392364 3418 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
eb3cdfb7
SG		 3419
3420 if (keyconf->keyidx != keyidx) {
3421 /* We need to remove a key with idx different that the one
3422 * in the uCode. This means that the key we need to remove has
3423 * been replaced by another one with different idx.
3424 * Don't do anything and return ok
3425 */
3426 spin_unlock_irqrestore(&il->sta_lock, flags);
3427 return 0;
3428 }
3429
b48d9665 3430 if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) {
e7392364
SG		 3431 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3432 key_flags);
eb3cdfb7
SG		 3433 spin_unlock_irqrestore(&il->sta_lock, flags);
3434 return 0;
3435 }
3436
e7392364
SG		 3437 if (!test_and_clear_bit
3438 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
eb3cdfb7 3439 IL_ERR("idx %d not used in uCode key table.\n",
e7392364
SG		 3440 il->stations[sta_id].sta.key.key_offset);
3441 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3442 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
eb3cdfb7 3443 il->stations[sta_id].sta.key.key_flags =
e7392364 3444 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
b48d9665 3445 il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx;
eb3cdfb7
SG		 3446 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3447 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3448
3449 if (il_is_rfkill(il)) {
e7392364
SG		 3450 D_WEP
3451 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
eb3cdfb7
SG		 3452 spin_unlock_irqrestore(&il->sta_lock, flags);
3453 return 0;
3454 }
3455 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3456 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3457 spin_unlock_irqrestore(&il->sta_lock, flags);
3458
3459 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3460}
3461
e7392364 3462int
83007196
SG		 3463il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3464 u8 sta_id)
eb3cdfb7
SG		 3465{
3466 int ret;
3467
3468 lockdep_assert_held(&il->mutex);
3469
d735f921 3470 il->_4965.key_mapping_keys++;
eb3cdfb7
SG		 3471 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3472
3473 switch (keyconf->cipher) {
3474 case WLAN_CIPHER_SUITE_CCMP:
e7392364 3475 ret =
83007196 3476 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3477 break;
3478 case WLAN_CIPHER_SUITE_TKIP:
e7392364 3479 ret =
83007196 3480 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3481 break;
3482 case WLAN_CIPHER_SUITE_WEP40:
3483 case WLAN_CIPHER_SUITE_WEP104:
83007196 3484 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
eb3cdfb7
SG		 3485 break;
3486 default:
e7392364
SG		 3487 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3488 keyconf->cipher);
eb3cdfb7
SG		 3489 ret = -EINVAL;
3490 }
3491
e7392364
SG		 3492 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3493 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
eb3cdfb7
SG		 3494
3495 return ret;
3496}
3497
3498/**
3499 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3500 *
3501 * This adds the broadcast station into the driver's station table
3502 * and marks it driver active, so that it will be restored to the
3503 * device at the next best time.
3504 */
e7392364 3505int
83007196 3506il4965_alloc_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3507{
3508 struct il_link_quality_cmd *link_cmd;
3509 unsigned long flags;
3510 u8 sta_id;
3511
3512 spin_lock_irqsave(&il->sta_lock, flags);
83007196 3513 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
eb3cdfb7
SG		 3514 if (sta_id == IL_INVALID_STATION) {
3515 IL_ERR("Unable to prepare broadcast station\n");
3516 spin_unlock_irqrestore(&il->sta_lock, flags);
3517
3518 return -EINVAL;
3519 }
3520
3521 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3522 il->stations[sta_id].used |= IL_STA_BCAST;
3523 spin_unlock_irqrestore(&il->sta_lock, flags);
3524
3525 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3526 if (!link_cmd) {
e7392364
SG		 3527 IL_ERR
3528 ("Unable to initialize rate scaling for bcast station.\n");
eb3cdfb7
SG		 3529 return -ENOMEM;
3530 }
3531
3532 spin_lock_irqsave(&il->sta_lock, flags);
3533 il->stations[sta_id].lq = link_cmd;
3534 spin_unlock_irqrestore(&il->sta_lock, flags);
3535
3536 return 0;
3537}
3538
3539/**
3540 * il4965_update_bcast_station - update broadcast station's LQ command
3541 *
3542 * Only used by iwl4965. Placed here to have all bcast station management
3543 * code together.
3544 */
e7392364 3545static int
83007196 3546il4965_update_bcast_station(struct il_priv *il)
eb3cdfb7
SG		 3547{
3548 unsigned long flags;
3549 struct il_link_quality_cmd *link_cmd;
b16db50a 3550 u8 sta_id = il->hw_params.bcast_id;
eb3cdfb7
SG		 3551
3552 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3553 if (!link_cmd) {
1722f8e1 3554 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
eb3cdfb7
SG		 3555 return -ENOMEM;
3556 }
3557
3558 spin_lock_irqsave(&il->sta_lock, flags);
3559 if (il->stations[sta_id].lq)
3560 kfree(il->stations[sta_id].lq);
3561 else
1722f8e1 3562 D_INFO("Bcast sta rate scaling has not been initialized.\n");
eb3cdfb7
SG		 3563 il->stations[sta_id].lq = link_cmd;
3564 spin_unlock_irqrestore(&il->sta_lock, flags);
3565
3566 return 0;
3567}
3568
e7392364
SG		 3569int
3570il4965_update_bcast_stations(struct il_priv *il)
eb3cdfb7 3571{
83007196 3572 return il4965_update_bcast_station(il);
eb3cdfb7
SG		 3573}
3574
3575/**
3576 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3577 */
e7392364
SG		 3578int
3579il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
eb3cdfb7
SG		 3580{
3581 unsigned long flags;
3582 struct il_addsta_cmd sta_cmd;
3583
3584 lockdep_assert_held(&il->mutex);
3585
3586 /* Remove "disable" flag, to enable Tx for this TID */
3587 spin_lock_irqsave(&il->sta_lock, flags);
3588 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3589 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3590 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3591 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3592 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3593 spin_unlock_irqrestore(&il->sta_lock, flags);
3594
3595 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3596}
3597
e7392364
SG		 3598int
3599il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3600 u16 ssn)
eb3cdfb7
SG		 3601{
3602 unsigned long flags;
3603 int sta_id;
3604 struct il_addsta_cmd sta_cmd;
3605
3606 lockdep_assert_held(&il->mutex);
3607
3608 sta_id = il_sta_id(sta);
3609 if (sta_id == IL_INVALID_STATION)
3610 return -ENXIO;
3611
3612 spin_lock_irqsave(&il->sta_lock, flags);
3613 il->stations[sta_id].sta.station_flags_msk = 0;
3614 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
e7392364 3615 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3616 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3617 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3618 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3619 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3620 spin_unlock_irqrestore(&il->sta_lock, flags);
3621
3622 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3623}
3624
e7392364
SG		 3625int
3626il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
eb3cdfb7
SG		 3627{
3628 unsigned long flags;
3629 int sta_id;
3630 struct il_addsta_cmd sta_cmd;
3631
3632 lockdep_assert_held(&il->mutex);
3633
3634 sta_id = il_sta_id(sta);
3635 if (sta_id == IL_INVALID_STATION) {
3636 IL_ERR("Invalid station for AGG tid %d\n", tid);
3637 return -ENXIO;
3638 }
3639
3640 spin_lock_irqsave(&il->sta_lock, flags);
3641 il->stations[sta_id].sta.station_flags_msk = 0;
3642 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
e7392364 3643 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
eb3cdfb7
SG		 3644 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3645 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 3646 sizeof(struct il_addsta_cmd));
eb3cdfb7
SG		 3647 spin_unlock_irqrestore(&il->sta_lock, flags);
3648
3649 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3650}
3651
3652void
3653il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3654{
3655 unsigned long flags;
3656
3657 spin_lock_irqsave(&il->sta_lock, flags);
3658 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3659 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3660 il->stations[sta_id].sta.sta.modify_mask =
e7392364 3661 STA_MODIFY_SLEEP_TX_COUNT_MSK;
eb3cdfb7
SG		 3662 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3663 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364 3664 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
eb3cdfb7
SG		 3665 spin_unlock_irqrestore(&il->sta_lock, flags);
3666
3667}
3668
e7392364
SG		 3669void
3670il4965_update_chain_flags(struct il_priv *il)
be663ab6 3671{
c9363551
SG		 3672 if (il->ops->set_rxon_chain) {
3673 il->ops->set_rxon_chain(il);
c8b03958 3674 if (il->active.rx_chain != il->staging.rx_chain)
83007196 3675 il_commit_rxon(il);
be663ab6
WYG		 3676 }
3677}
3678
e7392364
SG		 3679static void
3680il4965_clear_free_frames(struct il_priv *il)
be663ab6
WYG		 3681{
3682 struct list_head *element;
3683
e7392364 3684 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
be663ab6 3685
46bc8d4b
SG		 3686 while (!list_empty(&il->free_frames)) {
3687 element = il->free_frames.next;
be663ab6 3688 list_del(element);
e2ebc833 3689 kfree(list_entry(element, struct il_frame, list));
46bc8d4b 3690 il->frames_count--;
be663ab6
WYG		 3691 }
3692
46bc8d4b 3693 if (il->frames_count) {
9406f797 3694 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 3695 il->frames_count);
46bc8d4b 3696 il->frames_count = 0;
be663ab6
WYG		 3697 }
3698}
3699
e7392364
SG		 3700static struct il_frame *
3701il4965_get_free_frame(struct il_priv *il)
be663ab6 3702{
e2ebc833 3703 struct il_frame *frame;
be663ab6 3704 struct list_head *element;
46bc8d4b 3705 if (list_empty(&il->free_frames)) {
be663ab6
WYG		 3706 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3707 if (!frame) {
9406f797 3708 IL_ERR("Could not allocate frame!\n");
be663ab6
WYG		 3709 return NULL;
3710 }
3711
46bc8d4b 3712 il->frames_count++;
be663ab6
WYG		 3713 return frame;
3714 }
3715
46bc8d4b 3716 element = il->free_frames.next;
be663ab6 3717 list_del(element);
e2ebc833 3718 return list_entry(element, struct il_frame, list);
be663ab6
WYG		 3719}
3720
e7392364
SG		 3721static void
3722il4965_free_frame(struct il_priv *il, struct il_frame *frame)
be663ab6
WYG		 3723{
3724 memset(frame, 0, sizeof(*frame));
46bc8d4b 3725 list_add(&frame->list, &il->free_frames);
be663ab6
WYG		 3726}
3727
e7392364
SG		 3728static u32
3729il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3730 int left)
be663ab6 3731{
46bc8d4b 3732 lockdep_assert_held(&il->mutex);
be663ab6 3733
46bc8d4b 3734 if (!il->beacon_skb)
be663ab6
WYG		 3735 return 0;
3736
46bc8d4b 3737 if (il->beacon_skb->len > left)
be663ab6
WYG		 3738 return 0;
3739
46bc8d4b 3740 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
be663ab6 3741
46bc8d4b 3742 return il->beacon_skb->len;
be663ab6
WYG		 3743}
3744
3745/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
e7392364
SG		 3746static void
3747il4965_set_beacon_tim(struct il_priv *il,
3748 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3749 u32 frame_size)
be663ab6
WYG		 3750{
3751 u16 tim_idx;
3752 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3753
3754 /*
0c2c8852 3755 * The idx is relative to frame start but we start looking at the
be663ab6
WYG		 3756 * variable-length part of the beacon.
3757 */
3758 tim_idx = mgmt->u.beacon.variable - beacon;
3759
3760 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3761 while ((tim_idx < (frame_size - 2)) &&
e7392364
SG		 3762 (beacon[tim_idx] != WLAN_EID_TIM))
3763 tim_idx += beacon[tim_idx + 1] + 2;
be663ab6
WYG		 3764
3765 /* If TIM field was found, set variables */
3766 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3767 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
e7392364 3768 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
be663ab6 3769 } else
9406f797 3770 IL_WARN("Unable to find TIM Element in beacon\n");
be663ab6
WYG		 3771}
3772
e7392364
SG		 3773static unsigned int
3774il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
be663ab6 3775{
e2ebc833 3776 struct il_tx_beacon_cmd *tx_beacon_cmd;
be663ab6
WYG		 3777 u32 frame_size;
3778 u32 rate_flags;
3779 u32 rate;
3780 /*
3781 * We have to set up the TX command, the TX Beacon command, and the
3782 * beacon contents.
3783 */
3784
46bc8d4b 3785 lockdep_assert_held(&il->mutex);
be663ab6 3786
83007196
SG		 3787 if (!il->beacon_enabled) {
3788 IL_ERR("Trying to build beacon without beaconing enabled\n");
be663ab6
WYG		 3789 return 0;
3790 }
3791
3792 /* Initialize memory */
3793 tx_beacon_cmd = &frame->u.beacon;
3794 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3795
3796 /* Set up TX beacon contents */
e7392364
SG		 3797 frame_size =
3798 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3799 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
be663ab6
WYG		 3800 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3801 return 0;
3802 if (!frame_size)
3803 return 0;
3804
3805 /* Set up TX command fields */
e7392364 3806 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
b16db50a 3807 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
be663ab6 3808 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e7392364
SG		 3809 tx_beacon_cmd->tx.tx_flags =
3810 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3811 TX_CMD_FLG_STA_RATE_MSK;
be663ab6
WYG		 3812
3813 /* Set up TX beacon command fields */
e7392364
SG		 3814 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3815 frame_size);
be663ab6
WYG		 3816
3817 /* Set up packet rate and flags */
83007196 3818 rate = il_get_lowest_plcp(il);
a0c1ef3b 3819 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
616107ed 3820 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
e2ebc833 3821 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
be663ab6 3822 rate_flags |= RATE_MCS_CCK_MSK;
616107ed 3823 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
be663ab6
WYG		 3824
3825 return sizeof(*tx_beacon_cmd) + frame_size;
3826}
3827
e7392364
SG		 3828int
3829il4965_send_beacon_cmd(struct il_priv *il)
be663ab6 3830{
e2ebc833 3831 struct il_frame *frame;
be663ab6
WYG		 3832 unsigned int frame_size;
3833 int rc;
3834
46bc8d4b 3835 frame = il4965_get_free_frame(il);
be663ab6 3836 if (!frame) {
9406f797 3837 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 3838 "command.\n");
be663ab6
WYG		 3839 return -ENOMEM;
3840 }
3841
46bc8d4b 3842 frame_size = il4965_hw_get_beacon_cmd(il, frame);
be663ab6 3843 if (!frame_size) {
9406f797 3844 IL_ERR("Error configuring the beacon command\n");
46bc8d4b 3845 il4965_free_frame(il, frame);
be663ab6
WYG		 3846 return -EINVAL;
3847 }
3848
e7392364 3849 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
be663ab6 3850
46bc8d4b 3851 il4965_free_frame(il, frame);
be663ab6
WYG		 3852
3853 return rc;
3854}
3855
e7392364
SG		 3856static inline dma_addr_t
3857il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
be663ab6 3858{
e2ebc833 3859 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3860
3861 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3862 if (sizeof(dma_addr_t) > sizeof(u32))
3863 addr |=
e7392364
SG		 3864 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3865 16;
be663ab6
WYG		 3866
3867 return addr;
3868}
3869
e7392364
SG		 3870static inline u16
3871il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
be663ab6 3872{
e2ebc833 3873 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3874
3875 return le16_to_cpu(tb->hi_n_len) >> 4;
3876}
3877
e7392364
SG		 3878static inline void
3879il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
be663ab6 3880{
e2ebc833 3881 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3882 u16 hi_n_len = len << 4;
3883
3884 put_unaligned_le32(addr, &tb->lo);
3885 if (sizeof(dma_addr_t) > sizeof(u32))
3886 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3887
3888 tb->hi_n_len = cpu_to_le16(hi_n_len);
3889
3890 tfd->num_tbs = idx + 1;
3891}
3892
e7392364
SG		 3893static inline u8
3894il4965_tfd_get_num_tbs(struct il_tfd *tfd)
be663ab6
WYG		 3895{
3896 return tfd->num_tbs & 0x1f;
3897}
3898
3899/**
e2ebc833 3900 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
46bc8d4b 3901 * @il - driver ilate data
be663ab6
WYG		 3902 * @txq - tx queue
3903 *
0c2c8852 3904 * Does NOT advance any TFD circular buffer read/write idxes
be663ab6
WYG		 3905 * Does NOT free the TFD itself (which is within circular buffer)
3906 */
e7392364
SG		 3907void
3908il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
be663ab6 3909{
e2ebc833
SG		 3910 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3911 struct il_tfd *tfd;
46bc8d4b 3912 struct pci_dev *dev = il->pci_dev;
0c2c8852 3913 int idx = txq->q.read_ptr;
be663ab6
WYG		 3914 int i;
3915 int num_tbs;
3916
0c2c8852 3917 tfd = &tfd_tmp[idx];
be663ab6
WYG		 3918
3919 /* Sanity check on number of chunks */
e2ebc833 3920 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6 3921
e2ebc833 3922 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3923 IL_ERR("Too many chunks: %i\n", num_tbs);
be663ab6
WYG		 3924 /* @todo issue fatal error, it is quite serious situation */
3925 return;
3926 }
3927
3928 /* Unmap tx_cmd */
3929 if (num_tbs)
e7392364
SG		 3930 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3931 dma_unmap_len(&txq->meta[idx], len),
3932 PCI_DMA_BIDIRECTIONAL);
be663ab6
WYG		 3933
3934 /* Unmap chunks, if any. */
3935 for (i = 1; i < num_tbs; i++)
e2ebc833 3936 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
e7392364
SG		 3937 il4965_tfd_tb_get_len(tfd, i),
3938 PCI_DMA_TODEVICE);
be663ab6
WYG		 3939
3940 /* free SKB */
00ea99e1
SG		 3941 if (txq->skbs) {
3942 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
be663ab6
WYG		 3943
3944 /* can be called from irqs-disabled context */
3945 if (skb) {
3946 dev_kfree_skb_any(skb);
00ea99e1 3947 txq->skbs[txq->q.read_ptr] = NULL;
be663ab6
WYG		 3948 }
3949 }
3950}
3951
e7392364
SG		 3952int
3953il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3954 dma_addr_t addr, u16 len, u8 reset, u8 pad)
be663ab6 3955{
e2ebc833
SG		 3956 struct il_queue *q;
3957 struct il_tfd *tfd, *tfd_tmp;
be663ab6
WYG		 3958 u32 num_tbs;
3959
3960 q = &txq->q;
e2ebc833 3961 tfd_tmp = (struct il_tfd *)txq->tfds;
be663ab6
WYG		 3962 tfd = &tfd_tmp[q->write_ptr];
3963
3964 if (reset)
3965 memset(tfd, 0, sizeof(*tfd));
3966
e2ebc833 3967 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6
WYG		 3968
3969 /* Each TFD can point to a maximum 20 Tx buffers */
e2ebc833 3970 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3971 IL_ERR("Error can not send more than %d chunks\n",
e7392364 3972 IL_NUM_OF_TBS);
be663ab6
WYG		 3973 return -EINVAL;
3974 }
3975
3976 BUG_ON(addr & ~DMA_BIT_MASK(36));
e2ebc833 3977 if (unlikely(addr & ~IL_TX_DMA_MASK))
e7392364 3978 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
be663ab6 3979
e2ebc833 3980 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
be663ab6
WYG		 3981
3982 return 0;
3983}
3984
3985/*
3986 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3987 * given Tx queue, and enable the DMA channel used for that queue.
3988 *
3989 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3990 * channels supported in hardware.
3991 */
e7392364
SG		 3992int
3993il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
be663ab6
WYG		 3994{
3995 int txq_id = txq->q.id;
3996
3997 /* Circular buffer (TFD queue in DRAM) physical base address */
e7392364 3998 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
be663ab6
WYG		 3999
4000 return 0;
4001}
4002
4003/******************************************************************************
4004 *
4005 * Generic RX handler implementations
4006 *
4007 ******************************************************************************/
e7392364
SG		 4008static void
4009il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4010{
dcae1c64 4011 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4012 struct il_alive_resp *palive;
be663ab6
WYG		 4013 struct delayed_work *pwork;
4014
4015 palive = &pkt->u.alive_frame;
4016
e7392364
SG		 4017 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
4018 palive->is_valid, palive->ver_type, palive->ver_subtype);
be663ab6
WYG		 4019
4020 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 4021 D_INFO("Initialization Alive received.\n");
e7392364 4022 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 4023 sizeof(struct il_init_alive_resp));
46bc8d4b 4024 pwork = &il->init_alive_start;
be663ab6 4025 } else {
58de00a4 4026 D_INFO("Runtime Alive received.\n");
46bc8d4b 4027 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 4028 sizeof(struct il_alive_resp));
46bc8d4b 4029 pwork = &il->alive_start;
be663ab6
WYG		 4030 }
4031
4032 /* We delay the ALIVE response by 5ms to
4033 * give the HW RF Kill time to activate... */
4034 if (palive->is_valid == UCODE_VALID_OK)
e7392364 4035 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
be663ab6 4036 else
9406f797 4037 IL_WARN("uCode did not respond OK.\n");
be663ab6
WYG		 4038}
4039
4040/**
ebf0d90d 4041 * il4965_bg_stats_periodic - Timer callback to queue stats
be663ab6 4042 *
ebf0d90d 4043 * This callback is provided in order to send a stats request.
be663ab6
WYG		 4044 *
4045 * This timer function is continually reset to execute within
527901d0
SG		 4046 * 60 seconds since the last N_STATS was received. We need to
4047 * ensure we receive the stats in order to update the temperature
4048 * used for calibrating the TXPOWER.
be663ab6 4049 */
e7392364
SG		 4050static void
4051il4965_bg_stats_periodic(unsigned long data)
be663ab6 4052{
46bc8d4b 4053 struct il_priv *il = (struct il_priv *)data;
be663ab6 4054
a6766ccd 4055 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4056 return;
4057
4058 /* dont send host command if rf-kill is on */
46bc8d4b 4059 if (!il_is_ready_rf(il))
be663ab6
WYG		 4060 return;
4061
ebf0d90d 4062 il_send_stats_request(il, CMD_ASYNC, false);
be663ab6
WYG		 4063}
4064
e7392364
SG		 4065static void
4066il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4067{
dcae1c64 4068 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4069 struct il4965_beacon_notif *beacon =
e7392364 4070 (struct il4965_beacon_notif *)pkt->u.raw;
d3175167 4071#ifdef CONFIG_IWLEGACY_DEBUG
e2ebc833 4072 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
be663ab6 4073
5bf0dac4 4074 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
e7392364
SG		 4075 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4076 beacon->beacon_notify_hdr.failure_frame,
4077 le32_to_cpu(beacon->ibss_mgr_status),
4078 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
be663ab6 4079#endif
46bc8d4b 4080 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
be663ab6
WYG		 4081}
4082
e7392364
SG		 4083static void
4084il4965_perform_ct_kill_task(struct il_priv *il)
be663ab6
WYG		 4085{
4086 unsigned long flags;
4087
58de00a4 4088 D_POWER("Stop all queues\n");
be663ab6 4089
46bc8d4b
SG		 4090 if (il->mac80211_registered)
4091 ieee80211_stop_queues(il->hw);
be663ab6 4092
841b2cca 4093 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4094 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
841b2cca 4095 _il_rd(il, CSR_UCODE_DRV_GP1);
be663ab6 4096
46bc8d4b 4097 spin_lock_irqsave(&il->reg_lock, flags);
1e0f32a4 4098 if (likely(_il_grab_nic_access(il)))
13882269 4099 _il_release_nic_access(il);
46bc8d4b 4100 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6
WYG		 4101}
4102
4103/* Handle notification from uCode that card's power state is changing
4104 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG		 4105static void
4106il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4107{
dcae1c64 4108 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4109 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 4110 unsigned long status = il->status;
be663ab6 4111
58de00a4 4112 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
e7392364
SG		 4113 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4114 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4115 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
be663ab6 4116
e7392364 4117 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
be663ab6 4118
841b2cca 4119 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
e7392364 4120 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6 4121
e7392364 4122 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4123
4124 if (!(flags & RXON_CARD_DISABLED)) {
841b2cca 4125 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 4126 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0c1a94e2 4127 il_wr(il, HBUS_TARG_MBX_C,
e7392364 4128 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
be663ab6
WYG		 4129 }
4130 }
4131
4132 if (flags & CT_CARD_DISABLED)
46bc8d4b 4133 il4965_perform_ct_kill_task(il);
be663ab6
WYG		 4134
4135 if (flags & HW_CARD_DISABLED)
bc269a8e 4136 set_bit(S_RFKILL, &il->status);
be663ab6 4137 else
bc269a8e 4138 clear_bit(S_RFKILL, &il->status);
be663ab6
WYG		 4139
4140 if (!(flags & RXON_CARD_DISABLED))
46bc8d4b 4141 il_scan_cancel(il);
be663ab6 4142
bc269a8e
SG		 4143 if ((test_bit(S_RFKILL, &status) !=
4144 test_bit(S_RFKILL, &il->status)))
46bc8d4b 4145 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 4146 test_bit(S_RFKILL, &il->status));
be663ab6 4147 else
46bc8d4b 4148 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4149}
4150
4151/**
d0c72347 4152 * il4965_setup_handlers - Initialize Rx handler callbacks
be663ab6
WYG		 4153 *
4154 * Setup the RX handlers for each of the reply types sent from the uCode
4155 * to the host.
4156 *
4157 * This function chains into the hardware specific files for them to setup
4158 * any hardware specific handlers as well.
4159 */
e7392364
SG		 4160static void
4161il4965_setup_handlers(struct il_priv *il)
be663ab6 4162{
6e9848b4
SG		 4163 il->handlers[N_ALIVE] = il4965_hdl_alive;
4164 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 4165 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 4166 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 4167 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 4168 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 4169 il->handlers[N_BEACON] = il4965_hdl_beacon;
be663ab6
WYG		 4170
4171 /*
4172 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG		 4173 * stats request from the host as well as for the periodic
4174 * stats notifications (after received beacons) from the uCode.
be663ab6 4175 */
d2dfb33e
SG		 4176 il->handlers[C_STATS] = il4965_hdl_c_stats;
4177 il->handlers[N_STATS] = il4965_hdl_stats;
be663ab6 4178
46bc8d4b 4179 il_setup_rx_scan_handlers(il);
be663ab6
WYG		 4180
4181 /* status change handler */
e7392364 4182 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
be663ab6 4183
e7392364 4184 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
be663ab6 4185 /* Rx handlers */
6e9848b4
SG		 4186 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4187 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
3dfea27d 4188 il->handlers[N_RX] = il4965_hdl_rx;
be663ab6 4189 /* block ack */
6e9848b4 4190 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
3dfea27d
SG		 4191 /* Tx response */
4192 il->handlers[C_TX] = il4965_hdl_tx;
be663ab6
WYG		 4193}
4194
4195/**
e2ebc833 4196 * il4965_rx_handle - Main entry function for receiving responses from uCode
be663ab6 4197 *
d0c72347 4198 * Uses the il->handlers callback function array to invoke
be663ab6
WYG		 4199 * the appropriate handlers, including command responses,
4200 * frame-received notifications, and other notifications.
4201 */
e7392364
SG		 4202void
4203il4965_rx_handle(struct il_priv *il)
be663ab6 4204{
b73bb5f1 4205 struct il_rx_buf *rxb;
dcae1c64 4206 struct il_rx_pkt *pkt;
46bc8d4b 4207 struct il_rx_queue *rxq = &il->rxq;
be663ab6
WYG		 4208 u32 r, i;
4209 int reclaim;
4210 unsigned long flags;
4211 u8 fill_rx = 0;
4212 u32 count = 8;
4213 int total_empty;
4214
0c2c8852 4215 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
be663ab6 4216 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 4217 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
be663ab6
WYG		 4218 i = rxq->read;
4219
4220 /* Rx interrupt, but nothing sent from uCode */
4221 if (i == r)
58de00a4 4222 D_RX("r = %d, i = %d\n", r, i);
be663ab6
WYG		 4223
4224 /* calculate total frames need to be restock after handling RX */
4225 total_empty = r - rxq->write_actual;
4226 if (total_empty < 0)
4227 total_empty += RX_QUEUE_SIZE;
4228
4229 if (total_empty > (RX_QUEUE_SIZE / 2))
4230 fill_rx = 1;
4231
4232 while (i != r) {
4233 int len;
4234
4235 rxb = rxq->queue[i];
4236
4237 /* If an RXB doesn't have a Rx queue slot associated with it,
4238 * then a bug has been introduced in the queue refilling
4239 * routines -- catch it here */
4240 BUG_ON(rxb == NULL);
4241
4242 rxq->queue[i] = NULL;
4243
46bc8d4b
SG		 4244 pci_unmap_page(il->pci_dev, rxb->page_dma,
4245 PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 4246 PCI_DMA_FROMDEVICE);
4247 pkt = rxb_addr(rxb);
4248
e94a4099 4249 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 4250 len += sizeof(u32); /* account for status word */
be663ab6
WYG		 4251
4252 /* Reclaim a command buffer only if this packet is a response
4253 * to a (driver-originated) command.
4254 * If the packet (e.g. Rx frame) originated from uCode,
4255 * there is no command buffer to reclaim.
4256 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4257 * but apparently a few don't get set; catch them here. */
4258 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364
SG		 4259 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
4260 (pkt->hdr.cmd != N_RX_MPDU) &&
4261 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
4262 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
be663ab6
WYG		 4263
4264 /* Based on type of command response or notification,
4265 * handle those that need handling via function in
d0c72347
SG		 4266 * handlers table. See il4965_setup_handlers() */
4267 if (il->handlers[pkt->hdr.cmd]) {
e7392364
SG		 4268 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4269 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG		 4270 il->isr_stats.handlers[pkt->hdr.cmd]++;
4271 il->handlers[pkt->hdr.cmd] (il, rxb);
be663ab6
WYG		 4272 } else {
4273 /* No handling needed */
e7392364
SG		 4274 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4275 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
be663ab6
WYG		 4276 }
4277
4278 /*
4279 * XXX: After here, we should always check rxb->page
4280 * against NULL before touching it or its virtual
d0c72347 4281 * memory (pkt). Because some handler might have
be663ab6
WYG		 4282 * already taken or freed the pages.
4283 */
4284
4285 if (reclaim) {
4286 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 4287 * and fire off the (possibly) blocking il_send_cmd()
be663ab6
WYG		 4288 * as we reclaim the driver command queue */
4289 if (rxb->page)
46bc8d4b 4290 il_tx_cmd_complete(il, rxb);
be663ab6 4291 else
9406f797 4292 IL_WARN("Claim null rxb?\n");
be663ab6
WYG		 4293 }
4294
4295 /* Reuse the page if possible. For notification packets and
4296 * SKBs that fail to Rx correctly, add them back into the
4297 * rx_free list for reuse later. */
4298 spin_lock_irqsave(&rxq->lock, flags);
4299 if (rxb->page != NULL) {
e7392364
SG		 4300 rxb->page_dma =
4301 pci_map_page(il->pci_dev, rxb->page, 0,
4302 PAGE_SIZE << il->hw_params.
4303 rx_page_order, PCI_DMA_FROMDEVICE);
96ebbe8d
SG		 4304
4305 if (unlikely(pci_dma_mapping_error(il->pci_dev,
4306 rxb->page_dma))) {
4307 __il_free_pages(il, rxb->page);
4308 rxb->page = NULL;
4309 list_add_tail(&rxb->list, &rxq->rx_used);
4310 } else {
4311 list_add_tail(&rxb->list, &rxq->rx_free);
4312 rxq->free_count++;
4313 }
be663ab6
WYG		 4314 } else
4315 list_add_tail(&rxb->list, &rxq->rx_used);
4316
4317 spin_unlock_irqrestore(&rxq->lock, flags);
4318
4319 i = (i + 1) & RX_QUEUE_MASK;
4320 /* If there are a lot of unused frames,
4321 * restock the Rx queue so ucode wont assert. */
4322 if (fill_rx) {
4323 count++;
4324 if (count >= 8) {
4325 rxq->read = i;
46bc8d4b 4326 il4965_rx_replenish_now(il);
be663ab6
WYG		 4327 count = 0;
4328 }
4329 }
4330 }
4331
4332 /* Backtrack one entry */
4333 rxq->read = i;
4334 if (fill_rx)
46bc8d4b 4335 il4965_rx_replenish_now(il);
be663ab6 4336 else
46bc8d4b 4337 il4965_rx_queue_restock(il);
be663ab6
WYG		 4338}
4339
4340/* call this function to flush any scheduled tasklet */
e7392364
SG		 4341static inline void
4342il4965_synchronize_irq(struct il_priv *il)
be663ab6 4343{
e7392364 4344 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG		 4345 synchronize_irq(il->pci_dev->irq);
4346 tasklet_kill(&il->irq_tasklet);
be663ab6
WYG		 4347}
4348
e7392364
SG		 4349static void
4350il4965_irq_tasklet(struct il_priv *il)
be663ab6
WYG		 4351{
4352 u32 inta, handled = 0;
4353 u32 inta_fh;
4354 unsigned long flags;
4355 u32 i;
d3175167 4356#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4357 u32 inta_mask;
4358#endif
4359
46bc8d4b 4360 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4361
4362 /* Ack/clear/reset pending uCode interrupts.
4363 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4364 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG		 4365 inta = _il_rd(il, CSR_INT);
4366 _il_wr(il, CSR_INT, inta);
be663ab6
WYG		 4367
4368 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4369 * Any new interrupts that happen after this, either while we're
4370 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG		 4371 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4372 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
be663ab6 4373
d3175167 4374#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4375 if (il_get_debug_level(il) & IL_DL_ISR) {
be663ab6 4376 /* just for debug */
841b2cca 4377 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG		 4378 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4379 inta_mask, inta_fh);
be663ab6
WYG		 4380 }
4381#endif
4382
46bc8d4b 4383 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4384
4385 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4386 * atomic, make sure that inta covers all the interrupts that
4387 * we've discovered, even if FH interrupt came in just after
4388 * reading CSR_INT. */
4389 if (inta_fh & CSR49_FH_INT_RX_MASK)
4390 inta |= CSR_INT_BIT_FH_RX;
4391 if (inta_fh & CSR49_FH_INT_TX_MASK)
4392 inta |= CSR_INT_BIT_FH_TX;
4393
4394 /* Now service all interrupt bits discovered above. */
4395 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 4396 IL_ERR("Hardware error detected. Restarting.\n");
be663ab6
WYG		 4397
4398 /* Tell the device to stop sending interrupts */
46bc8d4b 4399 il_disable_interrupts(il);
be663ab6 4400
46bc8d4b
SG		 4401 il->isr_stats.hw++;
4402 il_irq_handle_error(il);
be663ab6
WYG		 4403
4404 handled |= CSR_INT_BIT_HW_ERR;
4405
4406 return;
4407 }
d3175167 4408#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4409 if (il_get_debug_level(il) & (IL_DL_ISR)) {
be663ab6
WYG		 4410 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4411 if (inta & CSR_INT_BIT_SCD) {
58de00a4 4412 D_ISR("Scheduler finished to transmit "
e7392364 4413 "the frame/frames.\n");
46bc8d4b 4414 il->isr_stats.sch++;
be663ab6
WYG		 4415 }
4416
4417 /* Alive notification via Rx interrupt will do the real work */
4418 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 4419 D_ISR("Alive interrupt\n");
46bc8d4b 4420 il->isr_stats.alive++;
be663ab6
WYG		 4421 }
4422 }
4423#endif
4424 /* Safely ignore these bits for debug checks below */
4425 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4426
4427 /* HW RF KILL switch toggled */
4428 if (inta & CSR_INT_BIT_RF_KILL) {
4429 int hw_rf_kill = 0;
c9363551
SG		 4430
4431 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4432 hw_rf_kill = 1;
4433
9406f797 4434 IL_WARN("RF_KILL bit toggled to %s.\n",
e7392364 4435 hw_rf_kill ? "disable radio" : "enable radio");
be663ab6 4436
46bc8d4b 4437 il->isr_stats.rfkill++;
be663ab6
WYG		 4438
4439 /* driver only loads ucode once setting the interface up.
4440 * the driver allows loading the ucode even if the radio
4441 * is killed. Hence update the killswitch state here. The
4442 * rfkill handler will care about restarting if needed.
4443 */
a6766ccd 4444 if (!test_bit(S_ALIVE, &il->status)) {
be663ab6 4445 if (hw_rf_kill)
bc269a8e 4446 set_bit(S_RFKILL, &il->status);
be663ab6 4447 else
bc269a8e 4448 clear_bit(S_RFKILL, &il->status);
46bc8d4b 4449 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
be663ab6
WYG		 4450 }
4451
4452 handled |= CSR_INT_BIT_RF_KILL;
4453 }
4454
4455 /* Chip got too hot and stopped itself */
4456 if (inta & CSR_INT_BIT_CT_KILL) {
9406f797 4457 IL_ERR("Microcode CT kill error detected.\n");
46bc8d4b 4458 il->isr_stats.ctkill++;
be663ab6
WYG		 4459 handled |= CSR_INT_BIT_CT_KILL;
4460 }
4461
4462 /* Error detected by uCode */
4463 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG		 4464 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4465 inta);
46bc8d4b
SG		 4466 il->isr_stats.sw++;
4467 il_irq_handle_error(il);
be663ab6
WYG		 4468 handled |= CSR_INT_BIT_SW_ERR;
4469 }
4470
4471 /*
4472 * uCode wakes up after power-down sleep.
4473 * Tell device about any new tx or host commands enqueued,
4474 * and about any Rx buffers made available while asleep.
4475 */
4476 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 4477 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG		 4478 il_rx_queue_update_write_ptr(il, &il->rxq);
4479 for (i = 0; i < il->hw_params.max_txq_num; i++)
4480 il_txq_update_write_ptr(il, &il->txq[i]);
4481 il->isr_stats.wakeup++;
be663ab6
WYG		 4482 handled |= CSR_INT_BIT_WAKEUP;
4483 }
4484
4485 /* All uCode command responses, including Tx command responses,
4486 * Rx "responses" (frame-received notification), and other
4487 * notifications from uCode come through here*/
4488 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG		 4489 il4965_rx_handle(il);
4490 il->isr_stats.rx++;
be663ab6
WYG		 4491 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4492 }
4493
4494 /* This "Tx" DMA channel is used only for loading uCode */
4495 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 4496 D_ISR("uCode load interrupt\n");
46bc8d4b 4497 il->isr_stats.tx++;
be663ab6
WYG		 4498 handled |= CSR_INT_BIT_FH_TX;
4499 /* Wake up uCode load routine, now that load is complete */
46bc8d4b
SG		 4500 il->ucode_write_complete = 1;
4501 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4502 }
4503
4504 if (inta & ~handled) {
9406f797 4505 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 4506 il->isr_stats.unhandled++;
be663ab6
WYG		 4507 }
4508
46bc8d4b 4509 if (inta & ~(il->inta_mask)) {
9406f797 4510 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 4511 inta & ~il->inta_mask);
9a95b370 4512 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
be663ab6
WYG		 4513 }
4514
4515 /* Re-enable all interrupts */
93fd74e3 4516 /* only Re-enable if disabled by irq */
a6766ccd 4517 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 4518 il_enable_interrupts(il);
a078a1fd
SG		 4519 /* Re-enable RF_KILL if it occurred */
4520 else if (handled & CSR_INT_BIT_RF_KILL)
46bc8d4b 4521 il_enable_rfkill_int(il);
be663ab6 4522
d3175167 4523#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4524 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG		 4525 inta = _il_rd(il, CSR_INT);
4526 inta_mask = _il_rd(il, CSR_INT_MASK);
4527 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
e7392364
SG		 4528 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4529 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
be663ab6
WYG		 4530 }
4531#endif
4532}
4533
4534/*****************************************************************************
4535 *
4536 * sysfs attributes
4537 *
4538 *****************************************************************************/
4539
d3175167 4540#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4541
4542/*
4543 * The following adds a new attribute to the sysfs representation
4544 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4545 * used for controlling the debug level.
4546 *
4547 * See the level definitions in iwl for details.
4548 *
4549 * The debug_level being managed using sysfs below is a per device debug
4550 * level that is used instead of the global debug level if it (the per
4551 * device debug level) is set.
4552 */
e7392364
SG		 4553static ssize_t
4554il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4555 char *buf)
be663ab6 4556{
46bc8d4b
SG		 4557 struct il_priv *il = dev_get_drvdata(d);
4558 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
be663ab6 4559}
e7392364
SG		 4560
4561static ssize_t
4562il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4563 const char *buf, size_t count)
be663ab6 4564{
46bc8d4b 4565 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4566 unsigned long val;
4567 int ret;
4568
4569 ret = strict_strtoul(buf, 0, &val);
4570 if (ret)
9406f797 4571 IL_ERR("%s is not in hex or decimal form.\n", buf);
288f9954 4572 else
46bc8d4b 4573 il->debug_level = val;
288f9954 4574
be663ab6
WYG		 4575 return strnlen(buf, count);
4576}
4577
e7392364
SG		 4578static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4579 il4965_store_debug_level);
be663ab6 4580
d3175167 4581#endif /* CONFIG_IWLEGACY_DEBUG */
be663ab6 4582
e7392364
SG		 4583static ssize_t
4584il4965_show_temperature(struct device *d, struct device_attribute *attr,
4585 char *buf)
be663ab6 4586{
46bc8d4b 4587 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4588
46bc8d4b 4589 if (!il_is_alive(il))
be663ab6
WYG		 4590 return -EAGAIN;
4591
46bc8d4b 4592 return sprintf(buf, "%d\n", il->temperature);
be663ab6
WYG		 4593}
4594
e2ebc833 4595static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
be663ab6 4596
e7392364
SG		 4597static ssize_t
4598il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
be663ab6 4599{
46bc8d4b 4600 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4601
46bc8d4b 4602 if (!il_is_ready_rf(il))
be663ab6
WYG		 4603 return sprintf(buf, "off\n");
4604 else
46bc8d4b 4605 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
be663ab6
WYG		 4606}
4607
e7392364
SG		 4608static ssize_t
4609il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4610 const char *buf, size_t count)
be663ab6 4611{
46bc8d4b 4612 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4613 unsigned long val;
4614 int ret;
4615
4616 ret = strict_strtoul(buf, 10, &val);
4617 if (ret)
9406f797 4618 IL_INFO("%s is not in decimal form.\n", buf);
be663ab6 4619 else {
46bc8d4b 4620 ret = il_set_tx_power(il, val, false);
be663ab6 4621 if (ret)
e7392364 4622 IL_ERR("failed setting tx power (0x%d).\n", ret);
be663ab6
WYG		 4623 else
4624 ret = count;
4625 }
4626 return ret;
4627}
4628
e7392364
SG		 4629static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4630 il4965_store_tx_power);
be663ab6 4631
e2ebc833 4632static struct attribute *il_sysfs_entries[] = {
be663ab6
WYG		 4633 &dev_attr_temperature.attr,
4634 &dev_attr_tx_power.attr,
d3175167 4635#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4636 &dev_attr_debug_level.attr,
4637#endif
4638 NULL
4639};
4640
e2ebc833 4641static struct attribute_group il_attribute_group = {
be663ab6 4642 .name = NULL, /* put in device directory */
e2ebc833 4643 .attrs = il_sysfs_entries,
be663ab6
WYG		 4644};
4645
4646/******************************************************************************
4647 *
4648 * uCode download functions
4649 *
4650 ******************************************************************************/
4651
e7392364
SG		 4652static void
4653il4965_dealloc_ucode_pci(struct il_priv *il)
be663ab6 4654{
46bc8d4b
SG		 4655 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4656 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4657 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4658 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4659 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4660 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6
WYG		 4661}
4662
e7392364
SG		 4663static void
4664il4965_nic_start(struct il_priv *il)
be663ab6
WYG		 4665{
4666 /* Remove all resets to allow NIC to operate */
841b2cca 4667 _il_wr(il, CSR_RESET, 0);
be663ab6
WYG		 4668}
4669
e2ebc833 4670static void il4965_ucode_callback(const struct firmware *ucode_raw,
e7392364
SG		 4671 void *context);
4672static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
be663ab6 4673
e7392364
SG		 4674static int __must_check
4675il4965_request_firmware(struct il_priv *il, bool first)
be663ab6 4676{
46bc8d4b 4677 const char *name_pre = il->cfg->fw_name_pre;
be663ab6
WYG		 4678 char tag[8];
4679
4680 if (first) {
0c2c8852
SG		 4681 il->fw_idx = il->cfg->ucode_api_max;
4682 sprintf(tag, "%d", il->fw_idx);
be663ab6 4683 } else {
0c2c8852
SG		 4684 il->fw_idx--;
4685 sprintf(tag, "%d", il->fw_idx);
be663ab6
WYG		 4686 }
4687
0c2c8852 4688 if (il->fw_idx < il->cfg->ucode_api_min) {
9406f797 4689 IL_ERR("no suitable firmware found!\n");
be663ab6
WYG		 4690 return -ENOENT;
4691 }
4692
46bc8d4b 4693 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
be663ab6 4694
e7392364 4695 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
be663ab6 4696
46bc8d4b
SG		 4697 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4698 &il->pci_dev->dev, GFP_KERNEL, il,
e2ebc833 4699 il4965_ucode_callback);
be663ab6
WYG		 4700}
4701
e2ebc833 4702struct il4965_firmware_pieces {
be663ab6
WYG		 4703 const void *inst, *data, *init, *init_data, *boot;
4704 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4705};
4706
e7392364
SG		 4707static int
4708il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4709 struct il4965_firmware_pieces *pieces)
be663ab6 4710{
e2ebc833 4711 struct il_ucode_header *ucode = (void *)ucode_raw->data;
be663ab6
WYG		 4712 u32 api_ver, hdr_size;
4713 const u8 *src;
4714
46bc8d4b
SG		 4715 il->ucode_ver = le32_to_cpu(ucode->ver);
4716 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4717
4718 switch (api_ver) {
4719 default:
4720 case 0:
4721 case 1:
4722 case 2:
4723 hdr_size = 24;
4724 if (ucode_raw->size < hdr_size) {
9406f797 4725 IL_ERR("File size too small!\n");
be663ab6
WYG		 4726 return -EINVAL;
4727 }
4728 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4729 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4730 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
e7392364 4731 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
be663ab6
WYG		 4732 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4733 src = ucode->v1.data;
4734 break;
4735 }
4736
4737 /* Verify size of file vs. image size info in file's header */
e7392364
SG		 4738 if (ucode_raw->size !=
4739 hdr_size + pieces->inst_size + pieces->data_size +
4740 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
be663ab6 4741
e7392364
SG		 4742 IL_ERR("uCode file size %d does not match expected size\n",
4743 (int)ucode_raw->size);
be663ab6
WYG		 4744 return -EINVAL;
4745 }
4746
4747 pieces->inst = src;
4748 src += pieces->inst_size;
4749 pieces->data = src;
4750 src += pieces->data_size;
4751 pieces->init = src;
4752 src += pieces->init_size;
4753 pieces->init_data = src;
4754 src += pieces->init_data_size;
4755 pieces->boot = src;
4756 src += pieces->boot_size;
4757
4758 return 0;
4759}
4760
4761/**
e2ebc833 4762 * il4965_ucode_callback - callback when firmware was loaded
be663ab6
WYG		 4763 *
4764 * If loaded successfully, copies the firmware into buffers
4765 * for the card to fetch (via DMA).
4766 */
4767static void
e2ebc833 4768il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
be663ab6 4769{
46bc8d4b 4770 struct il_priv *il = context;
e2ebc833 4771 struct il_ucode_header *ucode;
be663ab6 4772 int err;
e2ebc833 4773 struct il4965_firmware_pieces pieces;
46bc8d4b
SG		 4774 const unsigned int api_max = il->cfg->ucode_api_max;
4775 const unsigned int api_min = il->cfg->ucode_api_min;
be663ab6
WYG		 4776 u32 api_ver;
4777
4778 u32 max_probe_length = 200;
4779 u32 standard_phy_calibration_size =
e7392364 4780 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
be663ab6
WYG		 4781
4782 memset(&pieces, 0, sizeof(pieces));
4783
4784 if (!ucode_raw) {
0c2c8852 4785 if (il->fw_idx <= il->cfg->ucode_api_max)
e7392364
SG		 4786 IL_ERR("request for firmware file '%s' failed.\n",
4787 il->firmware_name);
be663ab6
WYG		 4788 goto try_again;
4789 }
4790
e7392364
SG		 4791 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4792 ucode_raw->size);
be663ab6
WYG		 4793
4794 /* Make sure that we got at least the API version number */
4795 if (ucode_raw->size < 4) {
9406f797 4796 IL_ERR("File size way too small!\n");
be663ab6
WYG		 4797 goto try_again;
4798 }
4799
4800 /* Data from ucode file: header followed by uCode images */
e2ebc833 4801 ucode = (struct il_ucode_header *)ucode_raw->data;
be663ab6 4802
46bc8d4b 4803 err = il4965_load_firmware(il, ucode_raw, &pieces);
be663ab6
WYG		 4804
4805 if (err)
4806 goto try_again;
4807
46bc8d4b 4808 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4809
4810 /*
4811 * api_ver should match the api version forming part of the
4812 * firmware filename ... but we don't check for that and only rely
4813 * on the API version read from firmware header from here on forward
4814 */
4815 if (api_ver < api_min || api_ver > api_max) {
e7392364
SG		 4816 IL_ERR("Driver unable to support your firmware API. "
4817 "Driver supports v%u, firmware is v%u.\n", api_max,
4818 api_ver);
be663ab6
WYG		 4819 goto try_again;
4820 }
4821
4822 if (api_ver != api_max)
e7392364
SG		 4823 IL_ERR("Firmware has old API version. Expected v%u, "
4824 "got v%u. New firmware can be obtained "
4825 "from http://www.intellinuxwireless.org.\n", api_max,
4826 api_ver);
be663ab6 4827
9406f797 4828 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG		 4829 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4830 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
be663ab6 4831
e7392364
SG		 4832 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4833 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4834 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
46bc8d4b 4835 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6
WYG		 4836
4837 /*
4838 * For any of the failures below (before allocating pci memory)
4839 * we will try to load a version with a smaller API -- maybe the
4840 * user just got a corrupted version of the latest API.
4841 */
4842
e7392364
SG		 4843 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4844 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4845 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4846 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4847 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4848 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
be663ab6
WYG		 4849
4850 /* Verify that uCode images will fit in card's SRAM */
46bc8d4b 4851 if (pieces.inst_size > il->hw_params.max_inst_size) {
9406f797 4852 IL_ERR("uCode instr len %Zd too large to fit in\n",
e7392364 4853 pieces.inst_size);
be663ab6
WYG		 4854 goto try_again;
4855 }
4856
46bc8d4b 4857 if (pieces.data_size > il->hw_params.max_data_size) {
9406f797 4858 IL_ERR("uCode data len %Zd too large to fit in\n",
e7392364 4859 pieces.data_size);
be663ab6
WYG		 4860 goto try_again;
4861 }
4862
46bc8d4b 4863 if (pieces.init_size > il->hw_params.max_inst_size) {
9406f797 4864 IL_ERR("uCode init instr len %Zd too large to fit in\n",
e7392364 4865 pieces.init_size);
be663ab6
WYG		 4866 goto try_again;
4867 }
4868
46bc8d4b 4869 if (pieces.init_data_size > il->hw_params.max_data_size) {
9406f797 4870 IL_ERR("uCode init data len %Zd too large to fit in\n",
e7392364 4871 pieces.init_data_size);
be663ab6
WYG		 4872 goto try_again;
4873 }
4874
46bc8d4b 4875 if (pieces.boot_size > il->hw_params.max_bsm_size) {
9406f797 4876 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
e7392364 4877 pieces.boot_size);
be663ab6
WYG		 4878 goto try_again;
4879 }
4880
4881 /* Allocate ucode buffers for card's bus-master loading ... */
4882
4883 /* Runtime instructions and 2 copies of data:
4884 * 1) unmodified from disk
4885 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG		 4886 il->ucode_code.len = pieces.inst_size;
4887 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
be663ab6 4888
46bc8d4b
SG		 4889 il->ucode_data.len = pieces.data_size;
4890 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
be663ab6 4891
46bc8d4b
SG		 4892 il->ucode_data_backup.len = pieces.data_size;
4893 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
be663ab6 4894
46bc8d4b
SG		 4895 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4896 !il->ucode_data_backup.v_addr)
be663ab6
WYG		 4897 goto err_pci_alloc;
4898
4899 /* Initialization instructions and data */
4900 if (pieces.init_size && pieces.init_data_size) {
46bc8d4b
SG		 4901 il->ucode_init.len = pieces.init_size;
4902 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
be663ab6 4903
46bc8d4b
SG		 4904 il->ucode_init_data.len = pieces.init_data_size;
4905 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
be663ab6 4906
46bc8d4b 4907 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
be663ab6
WYG		 4908 goto err_pci_alloc;
4909 }
4910
4911 /* Bootstrap (instructions only, no data) */
4912 if (pieces.boot_size) {
46bc8d4b
SG		 4913 il->ucode_boot.len = pieces.boot_size;
4914 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6 4915
46bc8d4b 4916 if (!il->ucode_boot.v_addr)
be663ab6
WYG		 4917 goto err_pci_alloc;
4918 }
4919
4920 /* Now that we can no longer fail, copy information */
4921
46bc8d4b 4922 il->sta_key_max_num = STA_KEY_MAX_NUM;
be663ab6
WYG		 4923
4924 /* Copy images into buffers for card's bus-master reads ... */
4925
4926 /* Runtime instructions (first block of data in file) */
58de00a4 4927 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
e7392364 4928 pieces.inst_size);
46bc8d4b 4929 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
be663ab6 4930
58de00a4 4931 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 4932 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
be663ab6
WYG		 4933
4934 /*
4935 * Runtime data
e2ebc833 4936 * NOTE: Copy into backup buffer will be done in il_up()
be663ab6 4937 */
58de00a4 4938 D_INFO("Copying (but not loading) uCode data len %Zd\n",
e7392364 4939 pieces.data_size);
46bc8d4b
SG		 4940 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4941 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
be663ab6
WYG		 4942
4943 /* Initialization instructions */
4944 if (pieces.init_size) {
e7392364
SG		 4945 D_INFO("Copying (but not loading) init instr len %Zd\n",
4946 pieces.init_size);
46bc8d4b 4947 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
be663ab6
WYG		 4948 }
4949
4950 /* Initialization data */
4951 if (pieces.init_data_size) {
e7392364
SG		 4952 D_INFO("Copying (but not loading) init data len %Zd\n",
4953 pieces.init_data_size);
46bc8d4b 4954 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
be663ab6
WYG		 4955 pieces.init_data_size);
4956 }
4957
4958 /* Bootstrap instructions */
58de00a4 4959 D_INFO("Copying (but not loading) boot instr len %Zd\n",
e7392364 4960 pieces.boot_size);
46bc8d4b 4961 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
be663ab6
WYG		 4962
4963 /*
4964 * figure out the offset of chain noise reset and gain commands
4965 * base on the size of standard phy calibration commands table size
4966 */
46bc8d4b 4967 il->_4965.phy_calib_chain_noise_reset_cmd =
e7392364 4968 standard_phy_calibration_size;
46bc8d4b 4969 il->_4965.phy_calib_chain_noise_gain_cmd =
e7392364 4970 standard_phy_calibration_size + 1;
be663ab6
WYG		 4971
4972 /**************************************************
4973 * This is still part of probe() in a sense...
4974 *
4975 * 9. Setup and register with mac80211 and debugfs
4976 **************************************************/
46bc8d4b 4977 err = il4965_mac_setup_register(il, max_probe_length);
be663ab6
WYG		 4978 if (err)
4979 goto out_unbind;
4980
46bc8d4b 4981 err = il_dbgfs_register(il, DRV_NAME);
be663ab6 4982 if (err)
e7392364
SG		 4983 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4984 err);
be663ab6 4985
e7392364 4986 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
be663ab6 4987 if (err) {
9406f797 4988 IL_ERR("failed to create sysfs device attributes\n");
be663ab6
WYG		 4989 goto out_unbind;
4990 }
4991
4992 /* We have our copies now, allow OS release its copies */
4993 release_firmware(ucode_raw);
46bc8d4b 4994 complete(&il->_4965.firmware_loading_complete);
be663ab6
WYG		 4995 return;
4996
e7392364 4997try_again:
be663ab6 4998 /* try next, if any */
46bc8d4b 4999 if (il4965_request_firmware(il, false))
be663ab6
WYG		 5000 goto out_unbind;
5001 release_firmware(ucode_raw);
5002 return;
5003
e7392364 5004err_pci_alloc:
9406f797 5005 IL_ERR("failed to allocate pci memory\n");
46bc8d4b 5006 il4965_dealloc_ucode_pci(il);
e7392364 5007out_unbind:
46bc8d4b
SG		 5008 complete(&il->_4965.firmware_loading_complete);
5009 device_release_driver(&il->pci_dev->dev);
be663ab6
WYG		 5010 release_firmware(ucode_raw);
5011}
5012
e7392364 5013static const char *const desc_lookup_text[] = {
be663ab6
WYG		 5014 "OK",
5015 "FAIL",
5016 "BAD_PARAM",
5017 "BAD_CHECKSUM",
5018 "NMI_INTERRUPT_WDG",
5019 "SYSASSERT",
5020 "FATAL_ERROR",
5021 "BAD_COMMAND",
5022 "HW_ERROR_TUNE_LOCK",
5023 "HW_ERROR_TEMPERATURE",
5024 "ILLEGAL_CHAN_FREQ",
3b98c7f4 5025 "VCC_NOT_STBL",
9a95b370 5026 "FH49_ERROR",
be663ab6
WYG		 5027 "NMI_INTERRUPT_HOST",
5028 "NMI_INTERRUPT_ACTION_PT",
5029 "NMI_INTERRUPT_UNKNOWN",
5030 "UCODE_VERSION_MISMATCH",
5031 "HW_ERROR_ABS_LOCK",
5032 "HW_ERROR_CAL_LOCK_FAIL",
5033 "NMI_INTERRUPT_INST_ACTION_PT",
5034 "NMI_INTERRUPT_DATA_ACTION_PT",
5035 "NMI_TRM_HW_ER",
5036 "NMI_INTERRUPT_TRM",
861d9c3f 5037 "NMI_INTERRUPT_BREAK_POINT",
be663ab6
WYG		 5038 "DEBUG_0",
5039 "DEBUG_1",
5040 "DEBUG_2",
5041 "DEBUG_3",
5042};
5043
e7392364
SG		 5044static struct {
5045 char *name;
5046 u8 num;
5047} advanced_lookup[] = {
5048 {
5049 "NMI_INTERRUPT_WDG", 0x34}, {
5050 "SYSASSERT", 0x35}, {
5051 "UCODE_VERSION_MISMATCH", 0x37}, {
5052 "BAD_COMMAND", 0x38}, {
5053 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5054 "FATAL_ERROR", 0x3D}, {
5055 "NMI_TRM_HW_ERR", 0x46}, {
5056 "NMI_INTERRUPT_TRM", 0x4C}, {
5057 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5058 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5059 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5060 "NMI_INTERRUPT_HOST", 0x66}, {
5061 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5062 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5063 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5064"ADVANCED_SYSASSERT", 0},};
5065
5066static const char *
5067il4965_desc_lookup(u32 num)
be663ab6
WYG		 5068{
5069 int i;
5070 int max = ARRAY_SIZE(desc_lookup_text);
5071
5072 if (num < max)
5073 return desc_lookup_text[num];
5074
5075 max = ARRAY_SIZE(advanced_lookup) - 1;
5076 for (i = 0; i < max; i++) {
5077 if (advanced_lookup[i].num == num)
5078 break;
5079 }
5080 return advanced_lookup[i].name;
5081}
5082
5083#define ERROR_START_OFFSET (1 * sizeof(u32))
5084#define ERROR_ELEM_SIZE (7 * sizeof(u32))
5085
e7392364
SG		 5086void
5087il4965_dump_nic_error_log(struct il_priv *il)
be663ab6
WYG		 5088{
5089 u32 data2, line;
5090 u32 desc, time, count, base, data1;
5091 u32 blink1, blink2, ilink1, ilink2;
5092 u32 pc, hcmd;
5093
1722f8e1 5094 if (il->ucode_type == UCODE_INIT)
46bc8d4b 5095 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
1722f8e1 5096 else
46bc8d4b 5097 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
be663ab6 5098
1600b875 5099 if (!il->ops->is_valid_rtc_data_addr(base)) {
e7392364
SG		 5100 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5101 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
be663ab6
WYG		 5102 return;
5103 }
5104
46bc8d4b 5105 count = il_read_targ_mem(il, base);
be663ab6
WYG		 5106
5107 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 5108 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 5109 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
46bc8d4b
SG		 5110 }
5111
5112 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5113 il->isr_stats.err_code = desc;
5114 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5115 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5116 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5117 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5118 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5119 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5120 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5121 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5122 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5123 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5124
9406f797 5125 IL_ERR("Desc Time "
e7392364 5126 "data1 data2 line\n");
9406f797 5127 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
e7392364 5128 il4965_desc_lookup(desc), desc, time, data1, data2, line);
9406f797 5129 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
e7392364
SG		 5130 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5131 blink2, ilink1, ilink2, hcmd);
be663ab6
WYG		 5132}
5133
e7392364
SG		 5134static void
5135il4965_rf_kill_ct_config(struct il_priv *il)
be663ab6 5136{
e2ebc833 5137 struct il_ct_kill_config cmd;
be663ab6
WYG		 5138 unsigned long flags;
5139 int ret = 0;
5140
46bc8d4b 5141 spin_lock_irqsave(&il->lock, flags);
841b2cca 5142 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
e7392364 5143 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
46bc8d4b 5144 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5145
5146 cmd.critical_temperature_R =
e7392364 5147 cpu_to_le32(il->hw_params.ct_kill_threshold);
be663ab6 5148
e7392364 5149 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
be663ab6 5150 if (ret)
4d69c752 5151 IL_ERR("C_CT_KILL_CONFIG failed\n");
be663ab6 5152 else
e7392364
SG		 5153 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5154 "critical temperature is %d\n",
5155 il->hw_params.ct_kill_threshold);
be663ab6
WYG		 5156}
5157
5158static const s8 default_queue_to_tx_fifo[] = {
e2ebc833
SG		 5159 IL_TX_FIFO_VO,
5160 IL_TX_FIFO_VI,
5161 IL_TX_FIFO_BE,
5162 IL_TX_FIFO_BK,
d3175167 5163 IL49_CMD_FIFO_NUM,
e2ebc833
SG		 5164 IL_TX_FIFO_UNUSED,
5165 IL_TX_FIFO_UNUSED,
be663ab6
WYG		 5166};
5167
e53aac42
SG		 5168#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5169
e7392364
SG		 5170static int
5171il4965_alive_notify(struct il_priv *il)
be663ab6
WYG		 5172{
5173 u32 a;
5174 unsigned long flags;
5175 int i, chan;
5176 u32 reg_val;
5177
46bc8d4b 5178 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5179
5180 /* Clear 4965's internal Tx Scheduler data base */
e7392364 5181 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
d3175167
SG		 5182 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5183 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
46bc8d4b 5184 il_write_targ_mem(il, a, 0);
d3175167 5185 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
46bc8d4b 5186 il_write_targ_mem(il, a, 0);
e7392364
SG		 5187 for (;
5188 a <
5189 il->scd_base_addr +
5190 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5191 a += 4)
46bc8d4b 5192 il_write_targ_mem(il, a, 0);
be663ab6
WYG		 5193
5194 /* Tel 4965 where to find Tx byte count tables */
e7392364 5195 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
be663ab6
WYG		 5196
5197 /* Enable DMA channel */
e7392364
SG		 5198 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5199 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5200 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5201 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
be663ab6
WYG		 5202
5203 /* Update FH chicken bits */
9a95b370
SG		 5204 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5205 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
e7392364 5206 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
be663ab6
WYG		 5207
5208 /* Disable chain mode for all queues */
d3175167 5209 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
be663ab6
WYG		 5210
5211 /* Initialize each Tx queue (including the command queue) */
46bc8d4b 5212 for (i = 0; i < il->hw_params.max_txq_num; i++) {
be663ab6 5213
0c2c8852 5214 /* TFD circular buffer read/write idxes */
d3175167 5215 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
0c1a94e2 5216 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
be663ab6
WYG		 5217
5218 /* Max Tx Window size for Scheduler-ACK mode */
e7392364
SG		 5219 il_write_targ_mem(il,
5220 il->scd_base_addr +
5221 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5222 (SCD_WIN_SIZE <<
5223 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5224 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
be663ab6
WYG		 5225
5226 /* Frame limit */
e7392364
SG		 5227 il_write_targ_mem(il,
5228 il->scd_base_addr +
5229 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5230 sizeof(u32),
5231 (SCD_FRAME_LIMIT <<
5232 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5233 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
be663ab6
WYG		 5234
5235 }
d3175167 5236 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
e7392364 5237 (1 << il->hw_params.max_txq_num) - 1);
be663ab6
WYG		 5238
5239 /* Activate all Tx DMA/FIFO channels */
46bc8d4b 5240 il4965_txq_set_sched(il, IL_MASK(0, 6));
be663ab6 5241
46bc8d4b 5242 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
be663ab6
WYG		 5243
5244 /* make sure all queue are not stopped */
46bc8d4b 5245 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
be663ab6 5246 for (i = 0; i < 4; i++)
46bc8d4b 5247 atomic_set(&il->queue_stop_count[i], 0);
be663ab6
WYG		 5248
5249 /* reset to 0 to enable all the queue first */
46bc8d4b 5250 il->txq_ctx_active_msk = 0;
be663ab6
WYG		 5251 /* Map each Tx/cmd queue to its corresponding fifo */
5252 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5253
5254 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5255 int ac = default_queue_to_tx_fifo[i];
5256
46bc8d4b 5257 il_txq_ctx_activate(il, i);
be663ab6 5258
e2ebc833 5259 if (ac == IL_TX_FIFO_UNUSED)
be663ab6
WYG		 5260 continue;
5261
46bc8d4b 5262 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
be663ab6
WYG		 5263 }
5264
46bc8d4b 5265 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5266
5267 return 0;
5268}
5269
5270/**
4d69c752 5271 * il4965_alive_start - called after N_ALIVE notification received
be663ab6 5272 * from protocol/runtime uCode (initialization uCode's
e2ebc833 5273 * Alive gets handled by il_init_alive_start()).
be663ab6 5274 */
e7392364
SG		 5275static void
5276il4965_alive_start(struct il_priv *il)
be663ab6
WYG		 5277{
5278 int ret = 0;
be663ab6 5279
58de00a4 5280 D_INFO("Runtime Alive received.\n");
be663ab6 5281
46bc8d4b 5282 if (il->card_alive.is_valid != UCODE_VALID_OK) {
be663ab6
WYG		 5283 /* We had an error bringing up the hardware, so take it
5284 * all the way back down so we can try again */
58de00a4 5285 D_INFO("Alive failed.\n");
be663ab6
WYG		 5286 goto restart;
5287 }
5288
5289 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5290 * This is a paranoid check, because we would not have gotten the
5291 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 5292 if (il4965_verify_ucode(il)) {
be663ab6
WYG		 5293 /* Runtime instruction load was bad;
5294 * take it all the way back down so we can try again */
58de00a4 5295 D_INFO("Bad runtime uCode load.\n");
be663ab6
WYG		 5296 goto restart;
5297 }
5298
46bc8d4b 5299 ret = il4965_alive_notify(il);
be663ab6 5300 if (ret) {
e7392364 5301 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
be663ab6
WYG		 5302 goto restart;
5303 }
5304
be663ab6 5305 /* After the ALIVE response, we can send host commands to the uCode */
a6766ccd 5306 set_bit(S_ALIVE, &il->status);
be663ab6
WYG		 5307
5308 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 5309 il_setup_watchdog(il);
be663ab6 5310
46bc8d4b 5311 if (il_is_rfkill(il))
be663ab6
WYG		 5312 return;
5313
46bc8d4b 5314 ieee80211_wake_queues(il->hw);
be663ab6 5315
2eb05816 5316 il->active_rate = RATES_MASK;
be663ab6 5317
c8b03958 5318 if (il_is_associated(il)) {
e2ebc833 5319 struct il_rxon_cmd *active_rxon =
c8b03958 5320 (struct il_rxon_cmd *)&il->active;
be663ab6 5321 /* apply any changes in staging */
c8b03958 5322 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5323 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5324 } else {
be663ab6 5325 /* Initialize our rx_config data */
83007196 5326 il_connection_init_rx_config(il);
be663ab6 5327
c9363551
SG		 5328 if (il->ops->set_rxon_chain)
5329 il->ops->set_rxon_chain(il);
be663ab6
WYG		 5330 }
5331
5332 /* Configure bluetooth coexistence if enabled */
46bc8d4b 5333 il_send_bt_config(il);
be663ab6 5334
46bc8d4b 5335 il4965_reset_run_time_calib(il);
be663ab6 5336
a6766ccd 5337 set_bit(S_READY, &il->status);
be663ab6
WYG		 5338
5339 /* Configure the adapter for unassociated operation */
83007196 5340 il_commit_rxon(il);
be663ab6
WYG		 5341
5342 /* At this point, the NIC is initialized and operational */
46bc8d4b 5343 il4965_rf_kill_ct_config(il);
be663ab6 5344
58de00a4 5345 D_INFO("ALIVE processing complete.\n");
46bc8d4b 5346 wake_up(&il->wait_command_queue);
be663ab6 5347
46bc8d4b 5348 il_power_update_mode(il, true);
58de00a4 5349 D_INFO("Updated power mode\n");
be663ab6
WYG		 5350
5351 return;
5352
e7392364 5353restart:
46bc8d4b 5354 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 5355}
5356
46bc8d4b 5357static void il4965_cancel_deferred_work(struct il_priv *il);
be663ab6 5358
e7392364
SG		 5359static void
5360__il4965_down(struct il_priv *il)
be663ab6
WYG		 5361{
5362 unsigned long flags;
ab42b404 5363 int exit_pending;
be663ab6 5364
58de00a4 5365 D_INFO(DRV_NAME " is going down\n");
be663ab6 5366
46bc8d4b 5367 il_scan_cancel_timeout(il, 200);
be663ab6 5368
a6766ccd 5369 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
be663ab6 5370
a6766ccd 5371 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
be663ab6 5372 * to prevent rearm timer */
46bc8d4b 5373 del_timer_sync(&il->watchdog);
be663ab6 5374
83007196 5375 il_clear_ucode_stations(il);
d735f921
SG		 5376
5377 /* FIXME: race conditions ? */
5378 spin_lock_irq(&il->sta_lock);
5379 /*
5380 * Remove all key information that is not stored as part
5381 * of station information since mac80211 may not have had
5382 * a chance to remove all the keys. When device is
5383 * reconfigured by mac80211 after an error all keys will
5384 * be reconfigured.
5385 */
5386 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5387 il->_4965.key_mapping_keys = 0;
5388 spin_unlock_irq(&il->sta_lock);
5389
46bc8d4b
SG		 5390 il_dealloc_bcast_stations(il);
5391 il_clear_driver_stations(il);
be663ab6
WYG		 5392
5393 /* Unblock any waiting calls */
46bc8d4b 5394 wake_up_all(&il->wait_command_queue);
be663ab6
WYG		 5395
5396 /* Wipe out the EXIT_PENDING status bit if we are not actually
5397 * exiting the module */
5398 if (!exit_pending)
a6766ccd 5399 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5400
5401 /* stop and reset the on-board processor */
841b2cca 5402 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6
WYG		 5403
5404 /* tell the device to stop sending interrupts */
46bc8d4b
SG		 5405 spin_lock_irqsave(&il->lock, flags);
5406 il_disable_interrupts(il);
5407 spin_unlock_irqrestore(&il->lock, flags);
5408 il4965_synchronize_irq(il);
be663ab6 5409
46bc8d4b
SG		 5410 if (il->mac80211_registered)
5411 ieee80211_stop_queues(il->hw);
be663ab6 5412
e2ebc833 5413 /* If we have not previously called il_init() then
be663ab6 5414 * clear all bits but the RF Kill bit and return */
46bc8d4b 5415 if (!il_is_init(il)) {
e7392364 5416 il->status =
bc269a8e 5417 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0 5418 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
e7392364 5419 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6
WYG		 5420 goto exit;
5421 }
5422
5423 /* ...otherwise clear out all the status bits but the RF Kill
5424 * bit and continue taking the NIC down. */
e7392364 5425 il->status &=
bc269a8e 5426 test_bit(S_RFKILL, &il->status) << S_RFKILL |
c37281a0
SG		 5427 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5428 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
e7392364 5429 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
be663ab6 5430
775ed8ab
SG		 5431 /*
5432 * We disabled and synchronized interrupt, and priv->mutex is taken, so
5433 * here is the only thread which will program device registers, but
5434 * still have lockdep assertions, so we are taking reg_lock.
5435 */
5436 spin_lock_irq(&il->reg_lock);
5437 /* FIXME: il_grab_nic_access if rfkill is off ? */
5438
46bc8d4b
SG		 5439 il4965_txq_ctx_stop(il);
5440 il4965_rxq_stop(il);
be663ab6 5441 /* Power-down device's busmaster DMA clocks */
775ed8ab 5442 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6 5443 udelay(5);
be663ab6 5444 /* Make sure (redundant) we've released our request to stay awake */
775ed8ab 5445 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
be663ab6 5446 /* Stop the device, and put it in low power state */
775ed8ab
SG		 5447 _il_apm_stop(il);
5448
5449 spin_unlock_irq(&il->reg_lock);
be663ab6 5450
775ed8ab 5451 il4965_txq_ctx_unmap(il);
e7392364 5452exit:
46bc8d4b 5453 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
be663ab6 5454
46bc8d4b
SG		 5455 dev_kfree_skb(il->beacon_skb);
5456 il->beacon_skb = NULL;
be663ab6
WYG		 5457
5458 /* clear out any free frames */
46bc8d4b 5459 il4965_clear_free_frames(il);
be663ab6
WYG		 5460}
5461
e7392364
SG		 5462static void
5463il4965_down(struct il_priv *il)
be663ab6 5464{
46bc8d4b
SG		 5465 mutex_lock(&il->mutex);
5466 __il4965_down(il);
5467 mutex_unlock(&il->mutex);
be663ab6 5468
46bc8d4b 5469 il4965_cancel_deferred_work(il);
be663ab6
WYG		 5470}
5471
be663ab6 5472
71e0c6c2 5473static void
e7392364 5474il4965_set_hw_ready(struct il_priv *il)
be663ab6 5475{
71e0c6c2 5476 int ret;
be663ab6 5477
46bc8d4b 5478 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 5479 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
be663ab6
WYG		 5480
5481 /* See if we got it */
71e0c6c2
SG		 5482 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5483 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5484 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5485 100);
5486 if (ret >= 0)
46bc8d4b 5487 il->hw_ready = true;
be663ab6 5488
71e0c6c2 5489 D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not");
be663ab6
WYG		 5490}
5491
71e0c6c2 5492static void
e7392364 5493il4965_prepare_card_hw(struct il_priv *il)
be663ab6 5494{
71e0c6c2 5495 int ret;
be663ab6 5496
71e0c6c2 5497 il->hw_ready = false;
be663ab6 5498
71e0c6c2 5499 il4965_set_hw_ready(il);
46bc8d4b 5500 if (il->hw_ready)
71e0c6c2 5501 return;
be663ab6
WYG		 5502
5503 /* If HW is not ready, prepare the conditions to check again */
e7392364 5504 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
be663ab6 5505
e7392364
SG		 5506 ret =
5507 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5508 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5509 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
be663ab6
WYG		 5510
5511 /* HW should be ready by now, check again. */
5512 if (ret != -ETIMEDOUT)
46bc8d4b 5513 il4965_set_hw_ready(il);
be663ab6
WYG		 5514}
5515
5516#define MAX_HW_RESTARTS 5
5517
e7392364
SG		 5518static int
5519__il4965_up(struct il_priv *il)
be663ab6 5520{
be663ab6
WYG		 5521 int i;
5522 int ret;
5523
a6766ccd 5524 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 5525 IL_WARN("Exit pending; will not bring the NIC up\n");
be663ab6
WYG		 5526 return -EIO;
5527 }
5528
46bc8d4b 5529 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 5530 IL_ERR("ucode not available for device bringup\n");
be663ab6
WYG		 5531 return -EIO;
5532 }
5533
83007196 5534 ret = il4965_alloc_bcast_station(il);
17d6e557
SG		 5535 if (ret) {
5536 il_dealloc_bcast_stations(il);
5537 return ret;
be663ab6
WYG		 5538 }
5539
46bc8d4b 5540 il4965_prepare_card_hw(il);
46bc8d4b 5541 if (!il->hw_ready) {
71e0c6c2 5542 IL_ERR("HW not ready\n");
be663ab6
WYG		 5543 return -EIO;
5544 }
5545
5546 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 5547 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 5548 clear_bit(S_RFKILL, &il->status);
3976b451 5549 else {
bc269a8e 5550 set_bit(S_RFKILL, &il->status);
46bc8d4b 5551 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
be663ab6 5552
3976b451 5553 il_enable_rfkill_int(il);
9406f797 5554 IL_WARN("Radio disabled by HW RF Kill switch\n");
be663ab6
WYG		 5555 return 0;
5556 }
5557
841b2cca 5558 _il_wr(il, CSR_INT, 0xFFFFFFFF);
be663ab6 5559
e2ebc833 5560 /* must be initialised before il_hw_nic_init */
46bc8d4b 5561 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
be663ab6 5562
46bc8d4b 5563 ret = il4965_hw_nic_init(il);
be663ab6 5564 if (ret) {
9406f797 5565 IL_ERR("Unable to init nic\n");
be663ab6
WYG		 5566 return ret;
5567 }
5568
5569 /* make sure rfkill handshake bits are cleared */
841b2cca 5570 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 5571 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
be663ab6
WYG		 5572
5573 /* clear (again), then enable host interrupts */
841b2cca 5574 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5575 il_enable_interrupts(il);
be663ab6
WYG		 5576
5577 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG		 5578 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5579 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
be663ab6
WYG		 5580
5581 /* Copy original ucode data image from disk into backup cache.
5582 * This will be used to initialize the on-board processor's
5583 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG		 5584 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5585 il->ucode_data.len);
be663ab6
WYG		 5586
5587 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5588
5589 /* load bootstrap state machine,
5590 * load bootstrap program into processor's memory,
5591 * prepare to load the "initialize" uCode */
1600b875 5592 ret = il->ops->load_ucode(il);
be663ab6
WYG		 5593
5594 if (ret) {
e7392364 5595 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
be663ab6
WYG		 5596 continue;
5597 }
5598
5599 /* start card; "initialize" will load runtime ucode */
46bc8d4b 5600 il4965_nic_start(il);
be663ab6 5601
58de00a4 5602 D_INFO(DRV_NAME " is coming up\n");
be663ab6
WYG		 5603
5604 return 0;
5605 }
5606
a6766ccd 5607 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 5608 __il4965_down(il);
a6766ccd 5609 clear_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 5610
5611 /* tried to restart and config the device for as long as our
5612 * patience could withstand */
9406f797 5613 IL_ERR("Unable to initialize device after %d attempts.\n", i);
be663ab6
WYG		 5614 return -EIO;
5615}
5616
be663ab6
WYG		 5617/*****************************************************************************
5618 *
5619 * Workqueue callbacks
5620 *
5621 *****************************************************************************/
5622
e7392364
SG		 5623static void
5624il4965_bg_init_alive_start(struct work_struct *data)
be663ab6 5625{
46bc8d4b 5626 struct il_priv *il =
e2ebc833 5627 container_of(data, struct il_priv, init_alive_start.work);
be663ab6 5628
46bc8d4b 5629 mutex_lock(&il->mutex);
a6766ccd 5630 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5631 goto out;
be663ab6 5632
1600b875 5633 il->ops->init_alive_start(il);
28a6e577 5634out:
46bc8d4b 5635 mutex_unlock(&il->mutex);
be663ab6
WYG		 5636}
5637
e7392364
SG		 5638static void
5639il4965_bg_alive_start(struct work_struct *data)
be663ab6 5640{
46bc8d4b 5641 struct il_priv *il =
e2ebc833 5642 container_of(data, struct il_priv, alive_start.work);
be663ab6 5643
46bc8d4b 5644 mutex_lock(&il->mutex);
a6766ccd 5645 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 5646 goto out;
be663ab6 5647
46bc8d4b 5648 il4965_alive_start(il);
28a6e577 5649out:
46bc8d4b 5650 mutex_unlock(&il->mutex);
be663ab6
WYG		 5651}
5652
e7392364
SG		 5653static void
5654il4965_bg_run_time_calib_work(struct work_struct *work)
be663ab6 5655{
46bc8d4b 5656 struct il_priv *il = container_of(work, struct il_priv,
e7392364 5657 run_time_calib_work);
be663ab6 5658
46bc8d4b 5659 mutex_lock(&il->mutex);
be663ab6 5660
a6766ccd
SG		 5661 if (test_bit(S_EXIT_PENDING, &il->status) ||
5662 test_bit(S_SCANNING, &il->status)) {
46bc8d4b 5663 mutex_unlock(&il->mutex);
be663ab6
WYG		 5664 return;
5665 }
5666
46bc8d4b 5667 if (il->start_calib) {
e7392364
SG		 5668 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5669 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
be663ab6
WYG		 5670 }
5671
46bc8d4b 5672 mutex_unlock(&il->mutex);
be663ab6
WYG		 5673}
5674
e7392364
SG		 5675static void
5676il4965_bg_restart(struct work_struct *data)
be663ab6 5677{
46bc8d4b 5678 struct il_priv *il = container_of(data, struct il_priv, restart);
be663ab6 5679
a6766ccd 5680 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5681 return;
5682
a6766ccd 5683 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 5684 mutex_lock(&il->mutex);
46bc8d4b 5685 il->is_open = 0;
be663ab6 5686
46bc8d4b 5687 __il4965_down(il);
be663ab6 5688
46bc8d4b
SG		 5689 mutex_unlock(&il->mutex);
5690 il4965_cancel_deferred_work(il);
5691 ieee80211_restart_hw(il->hw);
be663ab6 5692 } else {
46bc8d4b 5693 il4965_down(il);
be663ab6 5694
46bc8d4b 5695 mutex_lock(&il->mutex);
a6766ccd 5696 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 5697 mutex_unlock(&il->mutex);
be663ab6 5698 return;
28a6e577 5699 }
be663ab6 5700
46bc8d4b
SG		 5701 __il4965_up(il);
5702 mutex_unlock(&il->mutex);
be663ab6
WYG		 5703 }
5704}
5705
e7392364
SG		 5706static void
5707il4965_bg_rx_replenish(struct work_struct *data)
be663ab6 5708{
e7392364 5709 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
be663ab6 5710
a6766ccd 5711 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5712 return;
5713
46bc8d4b
SG		 5714 mutex_lock(&il->mutex);
5715 il4965_rx_replenish(il);
5716 mutex_unlock(&il->mutex);
be663ab6
WYG		 5717}
5718
5719/*****************************************************************************
5720 *
5721 * mac80211 entry point functions
5722 *
5723 *****************************************************************************/
5724
5725#define UCODE_READY_TIMEOUT (4 * HZ)
5726
5727/*
5728 * Not a mac80211 entry point function, but it fits in with all the
5729 * other mac80211 functions grouped here.
5730 */
e7392364
SG		 5731static int
5732il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
be663ab6
WYG		 5733{
5734 int ret;
46bc8d4b 5735 struct ieee80211_hw *hw = il->hw;
be663ab6
WYG		 5736
5737 hw->rate_control_algorithm = "iwl-4965-rs";
5738
5739 /* Tell mac80211 our characteristics */
e7392364
SG		 5740 hw->flags =
5741 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
c65dd147 5742 IEEE80211_HW_NEED_DTIM_BEFORE_ASSOC | IEEE80211_HW_SPECTRUM_MGMT |
07db8f8f
SG		 5743 IEEE80211_HW_REPORTS_TX_ACK_STATUS | IEEE80211_HW_SUPPORTS_PS |
5744 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
46bc8d4b 5745 if (il->cfg->sku & IL_SKU_N)
e7392364
SG		 5746 hw->flags |=
5747 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5748 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
be663ab6 5749
e2ebc833
SG		 5750 hw->sta_data_size = sizeof(struct il_station_priv);
5751 hw->vif_data_size = sizeof(struct il_vif_priv);
be663ab6 5752
8c9c48d5
SG		 5753 hw->wiphy->interface_modes =
5754 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
be663ab6 5755
e7392364 5756 hw->wiphy->flags |=
d7fbcada
SG		 5757 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS |
5758 WIPHY_FLAG_IBSS_RSN;
be663ab6
WYG		 5759
5760 /*
5761 * For now, disable PS by default because it affects
5762 * RX performance significantly.
5763 */
5764 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5765
5766 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5767 /* we create the 802.11 header and a zero-length SSID element */
5768 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5769
5770 /* Default value; 4 EDCA QOS priorities */
5771 hw->queues = 4;
5772
e2ebc833 5773 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
be663ab6 5774
46bc8d4b
SG		 5775 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5776 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 5777 &il->bands[IEEE80211_BAND_2GHZ];
46bc8d4b
SG		 5778 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5779 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 5780 &il->bands[IEEE80211_BAND_5GHZ];
be663ab6 5781
46bc8d4b 5782 il_leds_init(il);
be663ab6 5783
46bc8d4b 5784 ret = ieee80211_register_hw(il->hw);
be663ab6 5785 if (ret) {
9406f797 5786 IL_ERR("Failed to register hw (error %d)\n", ret);
be663ab6
WYG		 5787 return ret;
5788 }
46bc8d4b 5789 il->mac80211_registered = 1;
be663ab6
WYG		 5790
5791 return 0;
5792}
5793
e7392364
SG		 5794int
5795il4965_mac_start(struct ieee80211_hw *hw)
be663ab6 5796{
46bc8d4b 5797 struct il_priv *il = hw->priv;
be663ab6
WYG		 5798 int ret;
5799
58de00a4 5800 D_MAC80211("enter\n");
be663ab6
WYG		 5801
5802 /* we should be verifying the device is ready to be opened */
46bc8d4b
SG		 5803 mutex_lock(&il->mutex);
5804 ret = __il4965_up(il);
5805 mutex_unlock(&il->mutex);
be663ab6
WYG		 5806
5807 if (ret)
5808 return ret;
5809
46bc8d4b 5810 if (il_is_rfkill(il))
be663ab6
WYG		 5811 goto out;
5812
58de00a4 5813 D_INFO("Start UP work done.\n");
be663ab6
WYG		 5814
5815 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5816 * mac80211 will not be run successfully. */
46bc8d4b 5817 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 5818 test_bit(S_READY, &il->status),
5819 UCODE_READY_TIMEOUT);
be663ab6 5820 if (!ret) {
a6766ccd 5821 if (!test_bit(S_READY, &il->status)) {
9406f797 5822 IL_ERR("START_ALIVE timeout after %dms.\n",
be663ab6
WYG		 5823 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5824 return -ETIMEDOUT;
5825 }
5826 }
5827
46bc8d4b 5828 il4965_led_enable(il);
be663ab6
WYG		 5829
5830out:
46bc8d4b 5831 il->is_open = 1;
58de00a4 5832 D_MAC80211("leave\n");
be663ab6
WYG		 5833 return 0;
5834}
5835
e7392364
SG		 5836void
5837il4965_mac_stop(struct ieee80211_hw *hw)
be663ab6 5838{
46bc8d4b 5839 struct il_priv *il = hw->priv;
be663ab6 5840
58de00a4 5841 D_MAC80211("enter\n");
be663ab6 5842
46bc8d4b 5843 if (!il->is_open)
be663ab6
WYG		 5844 return;
5845
46bc8d4b 5846 il->is_open = 0;
be663ab6 5847
46bc8d4b 5848 il4965_down(il);
be663ab6 5849
46bc8d4b 5850 flush_workqueue(il->workqueue);
be663ab6 5851
a078a1fd
SG		 5852 /* User space software may expect getting rfkill changes
5853 * even if interface is down */
841b2cca 5854 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5855 il_enable_rfkill_int(il);
be663ab6 5856
58de00a4 5857 D_MAC80211("leave\n");
be663ab6
WYG		 5858}
5859
e7392364 5860void
36323f81
TH		 5861il4965_mac_tx(struct ieee80211_hw *hw,
5862 struct ieee80211_tx_control *control,
5863 struct sk_buff *skb)
be663ab6 5864{
46bc8d4b 5865 struct il_priv *il = hw->priv;
be663ab6 5866
58de00a4 5867 D_MACDUMP("enter\n");
be663ab6 5868
58de00a4 5869 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 5870 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
be663ab6 5871
36323f81 5872 if (il4965_tx_skb(il, control->sta, skb))
be663ab6
WYG		 5873 dev_kfree_skb_any(skb);
5874
58de00a4 5875 D_MACDUMP("leave\n");
be663ab6
WYG		 5876}
5877
e7392364
SG		 5878void
5879il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5880 struct ieee80211_key_conf *keyconf,
5881 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
be663ab6 5882{
46bc8d4b 5883 struct il_priv *il = hw->priv;
be663ab6 5884
58de00a4 5885 D_MAC80211("enter\n");
be663ab6 5886
83007196 5887 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
be663ab6 5888
58de00a4 5889 D_MAC80211("leave\n");
be663ab6
WYG		 5890}
5891
e7392364
SG		 5892int
5893il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5894 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5895 struct ieee80211_key_conf *key)
be663ab6 5896{
46bc8d4b 5897 struct il_priv *il = hw->priv;
be663ab6
WYG		 5898 int ret;
5899 u8 sta_id;
5900 bool is_default_wep_key = false;
5901
58de00a4 5902 D_MAC80211("enter\n");
be663ab6 5903
46bc8d4b 5904 if (il->cfg->mod_params->sw_crypto) {
58de00a4 5905 D_MAC80211("leave - hwcrypto disabled\n");
be663ab6
WYG		 5906 return -EOPNOTSUPP;
5907 }
5908
d7fbcada
SG		 5909 /*
5910 * To support IBSS RSN, don't program group keys in IBSS, the
5911 * hardware will then not attempt to decrypt the frames.
5912 */
5913 if (vif->type == NL80211_IFTYPE_ADHOC &&
5914 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
5915 D_MAC80211("leave - ad-hoc group key\n");
5916 return -EOPNOTSUPP;
5917 }
5918
83007196 5919 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 5920 if (sta_id == IL_INVALID_STATION)
be663ab6
WYG		 5921 return -EINVAL;
5922
46bc8d4b
SG		 5923 mutex_lock(&il->mutex);
5924 il_scan_cancel_timeout(il, 100);
be663ab6
WYG		 5925
5926 /*
5927 * If we are getting WEP group key and we didn't receive any key mapping
5928 * so far, we are in legacy wep mode (group key only), otherwise we are
5929 * in 1X mode.
5930 * In legacy wep mode, we use another host command to the uCode.
5931 */
5932 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
e7392364 5933 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
be663ab6 5934 if (cmd == SET_KEY)
d735f921 5935 is_default_wep_key = !il->_4965.key_mapping_keys;
be663ab6
WYG		 5936 else
5937 is_default_wep_key =
e7392364 5938 (key->hw_key_idx == HW_KEY_DEFAULT);
be663ab6
WYG		 5939 }
5940
5941 switch (cmd) {
5942 case SET_KEY:
5943 if (is_default_wep_key)
83007196 5944 ret = il4965_set_default_wep_key(il, key);
be663ab6 5945 else
83007196 5946 ret = il4965_set_dynamic_key(il, key, sta_id);
be663ab6 5947
58de00a4 5948 D_MAC80211("enable hwcrypto key\n");
be663ab6
WYG		 5949 break;
5950 case DISABLE_KEY:
5951 if (is_default_wep_key)
83007196 5952 ret = il4965_remove_default_wep_key(il, key);
be663ab6 5953 else
83007196 5954 ret = il4965_remove_dynamic_key(il, key, sta_id);
be663ab6 5955
58de00a4 5956 D_MAC80211("disable hwcrypto key\n");
be663ab6
WYG		 5957 break;
5958 default:
5959 ret = -EINVAL;
5960 }
5961
46bc8d4b 5962 mutex_unlock(&il->mutex);
58de00a4 5963 D_MAC80211("leave\n");
be663ab6
WYG		 5964
5965 return ret;
5966}
5967
e7392364
SG		 5968int
5969il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5970 enum ieee80211_ampdu_mlme_action action,
5971 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5972 u8 buf_size)
be663ab6 5973{
46bc8d4b 5974 struct il_priv *il = hw->priv;
be663ab6
WYG		 5975 int ret = -EINVAL;
5976
e7392364 5977 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
be663ab6 5978
46bc8d4b 5979 if (!(il->cfg->sku & IL_SKU_N))
be663ab6
WYG		 5980 return -EACCES;
5981
46bc8d4b 5982 mutex_lock(&il->mutex);
be663ab6
WYG		 5983
5984 switch (action) {
5985 case IEEE80211_AMPDU_RX_START:
58de00a4 5986 D_HT("start Rx\n");
46bc8d4b 5987 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
be663ab6
WYG		 5988 break;
5989 case IEEE80211_AMPDU_RX_STOP:
58de00a4 5990 D_HT("stop Rx\n");
46bc8d4b 5991 ret = il4965_sta_rx_agg_stop(il, sta, tid);
a6766ccd 5992 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5993 ret = 0;
5994 break;
5995 case IEEE80211_AMPDU_TX_START:
58de00a4 5996 D_HT("start Tx\n");
46bc8d4b 5997 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
be663ab6 5998 break;
18b559d5
JB		 5999 case IEEE80211_AMPDU_TX_STOP_CONT:
6000 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6001 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
58de00a4 6002 D_HT("stop Tx\n");
46bc8d4b 6003 ret = il4965_tx_agg_stop(il, vif, sta, tid);
a6766ccd 6004 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 6005 ret = 0;
6006 break;
6007 case IEEE80211_AMPDU_TX_OPERATIONAL:
6008 ret = 0;
6009 break;
6010 }
46bc8d4b 6011 mutex_unlock(&il->mutex);
be663ab6
WYG		 6012
6013 return ret;
6014}
6015
e7392364
SG		 6016int
6017il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6018 struct ieee80211_sta *sta)
be663ab6 6019{
46bc8d4b 6020 struct il_priv *il = hw->priv;
e2ebc833 6021 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
be663ab6
WYG		 6022 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
6023 int ret;
6024 u8 sta_id;
6025
e7392364 6026 D_INFO("received request to add station %pM\n", sta->addr);
46bc8d4b 6027 mutex_lock(&il->mutex);
e7392364 6028 D_INFO("proceeding to add station %pM\n", sta->addr);
e2ebc833 6029 sta_priv->common.sta_id = IL_INVALID_STATION;
be663ab6
WYG		 6030
6031 atomic_set(&sta_priv->pending_frames, 0);
6032
e7392364 6033 ret =
83007196 6034 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
be663ab6 6035 if (ret) {
e7392364 6036 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
be663ab6 6037 /* Should we return success if return code is EEXIST ? */
46bc8d4b 6038 mutex_unlock(&il->mutex);
be663ab6
WYG		 6039 return ret;
6040 }
6041
6042 sta_priv->common.sta_id = sta_id;
6043
6044 /* Initialize rate scaling */
e7392364 6045 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG		 6046 il4965_rs_rate_init(il, sta, sta_id);
6047 mutex_unlock(&il->mutex);
be663ab6
WYG		 6048
6049 return 0;
6050}
6051
e7392364
SG		 6052void
6053il4965_mac_channel_switch(struct ieee80211_hw *hw,
6054 struct ieee80211_channel_switch *ch_switch)
be663ab6 6055{
46bc8d4b 6056 struct il_priv *il = hw->priv;
e2ebc833 6057 const struct il_channel_info *ch_info;
be663ab6
WYG		 6058 struct ieee80211_conf *conf = &hw->conf;
6059 struct ieee80211_channel *channel = ch_switch->channel;
46bc8d4b 6060 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6 6061 u16 ch;
be663ab6 6062
58de00a4 6063 D_MAC80211("enter\n");
be663ab6 6064
46bc8d4b 6065 mutex_lock(&il->mutex);
28a6e577 6066
46bc8d4b 6067 if (il_is_rfkill(il))
28a6e577 6068 goto out;
be663ab6 6069
a6766ccd
SG		 6070 if (test_bit(S_EXIT_PENDING, &il->status) ||
6071 test_bit(S_SCANNING, &il->status) ||
6072 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
28a6e577 6073 goto out;
be663ab6 6074
c8b03958 6075 if (!il_is_associated(il))
28a6e577 6076 goto out;
be663ab6 6077
1600b875 6078 if (!il->ops->set_channel_switch)
7f1f9742 6079 goto out;
be663ab6 6080
7f1f9742 6081 ch = channel->hw_value;
c8b03958 6082 if (le16_to_cpu(il->active.channel) == ch)
7f1f9742
SG		 6083 goto out;
6084
46bc8d4b 6085 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 6086 if (!il_is_channel_valid(ch_info)) {
58de00a4 6087 D_MAC80211("invalid channel\n");
7f1f9742
SG		 6088 goto out;
6089 }
6090
46bc8d4b 6091 spin_lock_irq(&il->lock);
7f1f9742 6092
46bc8d4b 6093 il->current_ht_config.smps = conf->smps_mode;
7f1f9742
SG		 6094
6095 /* Configure HT40 channels */
1c03c462
SG		 6096 il->ht.enabled = conf_is_ht(conf);
6097 if (il->ht.enabled) {
7f1f9742 6098 if (conf_is_ht40_minus(conf)) {
1c03c462 6099 il->ht.extension_chan_offset =
e7392364 6100 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 6101 il->ht.is_40mhz = true;
7f1f9742 6102 } else if (conf_is_ht40_plus(conf)) {
1c03c462 6103 il->ht.extension_chan_offset =
e7392364 6104 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 6105 il->ht.is_40mhz = true;
7f1f9742 6106 } else {
1c03c462 6107 il->ht.extension_chan_offset =
e7392364 6108 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 6109 il->ht.is_40mhz = false;
be663ab6 6110 }
7f1f9742 6111 } else
1c03c462 6112 il->ht.is_40mhz = false;
7f1f9742 6113
c8b03958
SG		 6114 if ((le16_to_cpu(il->staging.channel) != ch))
6115 il->staging.flags = 0;
7f1f9742 6116
83007196 6117 il_set_rxon_channel(il, channel);
46bc8d4b 6118 il_set_rxon_ht(il, ht_conf);
83007196 6119 il_set_flags_for_band(il, channel->band, il->vif);
7f1f9742 6120
46bc8d4b 6121 spin_unlock_irq(&il->lock);
7f1f9742 6122
46bc8d4b 6123 il_set_rate(il);
7f1f9742
SG		 6124 /*
6125 * at this point, staging_rxon has the
6126 * configuration for channel switch
6127 */
a6766ccd 6128 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6129 il->switch_channel = cpu_to_le16(ch);
1600b875 6130 if (il->ops->set_channel_switch(il, ch_switch)) {
a6766ccd 6131 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
46bc8d4b 6132 il->switch_channel = 0;
83007196 6133 ieee80211_chswitch_done(il->vif, false);
be663ab6 6134 }
7f1f9742 6135
be663ab6 6136out:
46bc8d4b 6137 mutex_unlock(&il->mutex);
58de00a4 6138 D_MAC80211("leave\n");
be663ab6
WYG		 6139}
6140
e7392364
SG		 6141void
6142il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6143 unsigned int *total_flags, u64 multicast)
be663ab6 6144{
46bc8d4b 6145 struct il_priv *il = hw->priv;
be663ab6 6146 __le32 filter_or = 0, filter_nand = 0;
be663ab6
WYG		 6147
6148#define CHK(test, flag) do { \
6149 if (*total_flags & (test)) \
6150 filter_or |= (flag); \
6151 else \
6152 filter_nand |= (flag); \
6153 } while (0)
6154
e7392364
SG		 6155 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6156 *total_flags);
be663ab6
WYG		 6157
6158 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
6159 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6160 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6161 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6162
6163#undef CHK
6164
46bc8d4b 6165 mutex_lock(&il->mutex);
be663ab6 6166
c8b03958
SG		 6167 il->staging.filter_flags &= ~filter_nand;
6168 il->staging.filter_flags |= filter_or;
be663ab6 6169
17d6e557
SG		 6170 /*
6171 * Not committing directly because hardware can perform a scan,
6172 * but we'll eventually commit the filter flags change anyway.
6173 */
be663ab6 6174
46bc8d4b 6175 mutex_unlock(&il->mutex);
be663ab6
WYG		 6176
6177 /*
6178 * Receiving all multicast frames is always enabled by the
e2ebc833 6179 * default flags setup in il_connection_init_rx_config()
be663ab6
WYG		 6180 * since we currently do not support programming multicast
6181 * filters into the device.
6182 */
e7392364
SG		 6183 *total_flags &=
6184 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
6185 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
be663ab6
WYG		 6186}
6187
6188/*****************************************************************************
6189 *
6190 * driver setup and teardown
6191 *
6192 *****************************************************************************/
6193
e7392364
SG		 6194static void
6195il4965_bg_txpower_work(struct work_struct *work)
be663ab6 6196{
46bc8d4b 6197 struct il_priv *il = container_of(work, struct il_priv,
e7392364 6198 txpower_work);
be663ab6 6199
46bc8d4b 6200 mutex_lock(&il->mutex);
f325757a 6201
be663ab6 6202 /* If a scan happened to start before we got here
ebf0d90d 6203 * then just return; the stats notification will
be663ab6
WYG		 6204 * kick off another scheduled work to compensate for
6205 * any temperature delta we missed here. */
a6766ccd
SG		 6206 if (test_bit(S_EXIT_PENDING, &il->status) ||
6207 test_bit(S_SCANNING, &il->status))
f325757a 6208 goto out;
be663ab6
WYG		 6209
6210 /* Regardless of if we are associated, we must reconfigure the
6211 * TX power since frames can be sent on non-radar channels while
6212 * not associated */
1600b875 6213 il->ops->send_tx_power(il);
be663ab6
WYG		 6214
6215 /* Update last_temperature to keep is_calib_needed from running
6216 * when it isn't needed... */
46bc8d4b 6217 il->last_temperature = il->temperature;
f325757a 6218out:
46bc8d4b 6219 mutex_unlock(&il->mutex);
be663ab6
WYG		 6220}
6221
e7392364
SG		 6222static void
6223il4965_setup_deferred_work(struct il_priv *il)
be663ab6 6224{
46bc8d4b 6225 il->workqueue = create_singlethread_workqueue(DRV_NAME);
be663ab6 6226
46bc8d4b 6227 init_waitqueue_head(&il->wait_command_queue);
be663ab6 6228
46bc8d4b
SG		 6229 INIT_WORK(&il->restart, il4965_bg_restart);
6230 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6231 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6232 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6233 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
be663ab6 6234
46bc8d4b 6235 il_setup_scan_deferred_work(il);
be663ab6 6236
46bc8d4b 6237 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
be663ab6 6238
ebf0d90d
SG		 6239 init_timer(&il->stats_periodic);
6240 il->stats_periodic.data = (unsigned long)il;
6241 il->stats_periodic.function = il4965_bg_stats_periodic;
be663ab6 6242
46bc8d4b
SG		 6243 init_timer(&il->watchdog);
6244 il->watchdog.data = (unsigned long)il;
6245 il->watchdog.function = il_bg_watchdog;
be663ab6 6246
e7392364
SG		 6247 tasklet_init(&il->irq_tasklet,
6248 (void (*)(unsigned long))il4965_irq_tasklet,
6249 (unsigned long)il);
be663ab6
WYG		 6250}
6251
e7392364
SG		 6252static void
6253il4965_cancel_deferred_work(struct il_priv *il)
be663ab6 6254{
46bc8d4b
SG		 6255 cancel_work_sync(&il->txpower_work);
6256 cancel_delayed_work_sync(&il->init_alive_start);
6257 cancel_delayed_work(&il->alive_start);
6258 cancel_work_sync(&il->run_time_calib_work);
be663ab6 6259
46bc8d4b 6260 il_cancel_scan_deferred_work(il);
be663ab6 6261
ebf0d90d 6262 del_timer_sync(&il->stats_periodic);
be663ab6
WYG		 6263}
6264
e7392364
SG		 6265static void
6266il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
be663ab6
WYG		 6267{
6268 int i;
6269
2eb05816 6270 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
d2ddf621 6271 rates[i].bitrate = il_rates[i].ieee * 5;
e7392364 6272 rates[i].hw_value = i; /* Rate scaling will work on idxes */
be663ab6
WYG		 6273 rates[i].hw_value_short = i;
6274 rates[i].flags = 0;
e2ebc833 6275 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
be663ab6
WYG		 6276 /*
6277 * If CCK != 1M then set short preamble rate flag.
6278 */
6279 rates[i].flags |=
e7392364
SG		 6280 (il_rates[i].plcp ==
6281 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
be663ab6
WYG		 6282 }
6283 }
6284}
e7392364 6285
be663ab6 6286/*
46bc8d4b 6287 * Acquire il->lock before calling this function !
be663ab6 6288 */
e7392364
SG		 6289void
6290il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
be663ab6 6291{
e7392364 6292 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
0c2c8852 6293 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
be663ab6
WYG		 6294}
6295
e7392364
SG		 6296void
6297il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6298 int tx_fifo_id, int scd_retry)
be663ab6
WYG		 6299{
6300 int txq_id = txq->q.id;
6301
6302 /* Find out whether to activate Tx queue */
46bc8d4b 6303 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
be663ab6
WYG		 6304
6305 /* Set up and activate */
d3175167 6306 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
1722f8e1
SG		 6307 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6308 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6309 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6310 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6311 IL49_SCD_QUEUE_STTS_REG_MSK);
be663ab6
WYG		 6312
6313 txq->sched_retry = scd_retry;
6314
e7392364
SG		 6315 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6316 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
be663ab6
WYG		 6317}
6318
c39ae9fd
SG		 6319const struct ieee80211_ops il4965_mac_ops = {
6320 .tx = il4965_mac_tx,
6321 .start = il4965_mac_start,
6322 .stop = il4965_mac_stop,
6323 .add_interface = il_mac_add_interface,
6324 .remove_interface = il_mac_remove_interface,
6325 .change_interface = il_mac_change_interface,
6326 .config = il_mac_config,
6327 .configure_filter = il4965_configure_filter,
6328 .set_key = il4965_mac_set_key,
6329 .update_tkip_key = il4965_mac_update_tkip_key,
6330 .conf_tx = il_mac_conf_tx,
6331 .reset_tsf = il_mac_reset_tsf,
6332 .bss_info_changed = il_mac_bss_info_changed,
6333 .ampdu_action = il4965_mac_ampdu_action,
6334 .hw_scan = il_mac_hw_scan,
6335 .sta_add = il4965_mac_sta_add,
6336 .sta_remove = il_mac_sta_remove,
6337 .channel_switch = il4965_mac_channel_switch,
6338 .tx_last_beacon = il_mac_tx_last_beacon,
70277f47 6339 .flush = il_mac_flush,
c39ae9fd
SG		 6340};
6341
e7392364
SG		 6342static int
6343il4965_init_drv(struct il_priv *il)
be663ab6
WYG		 6344{
6345 int ret;
6346
46bc8d4b
SG		 6347 spin_lock_init(&il->sta_lock);
6348 spin_lock_init(&il->hcmd_lock);
be663ab6 6349
46bc8d4b 6350 INIT_LIST_HEAD(&il->free_frames);
be663ab6 6351
46bc8d4b 6352 mutex_init(&il->mutex);
be663ab6 6353
46bc8d4b
SG		 6354 il->ieee_channels = NULL;
6355 il->ieee_rates = NULL;
6356 il->band = IEEE80211_BAND_2GHZ;
be663ab6 6357
46bc8d4b
SG		 6358 il->iw_mode = NL80211_IFTYPE_STATION;
6359 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6360 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
be663ab6
WYG		 6361
6362 /* initialize force reset */
46bc8d4b 6363 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
be663ab6
WYG		 6364
6365 /* Choose which receivers/antennas to use */
c9363551
SG		 6366 if (il->ops->set_rxon_chain)
6367 il->ops->set_rxon_chain(il);
be663ab6 6368
46bc8d4b 6369 il_init_scan_params(il);
be663ab6 6370
46bc8d4b 6371 ret = il_init_channel_map(il);
be663ab6 6372 if (ret) {
9406f797 6373 IL_ERR("initializing regulatory failed: %d\n", ret);
be663ab6
WYG		 6374 goto err;
6375 }
6376
46bc8d4b 6377 ret = il_init_geos(il);
be663ab6 6378 if (ret) {
9406f797 6379 IL_ERR("initializing geos failed: %d\n", ret);
be663ab6
WYG		 6380 goto err_free_channel_map;
6381 }
46bc8d4b 6382 il4965_init_hw_rates(il, il->ieee_rates);
be663ab6
WYG		 6383
6384 return 0;
6385
6386err_free_channel_map:
46bc8d4b 6387 il_free_channel_map(il);
be663ab6
WYG		 6388err:
6389 return ret;
6390}
6391
e7392364
SG		 6392static void
6393il4965_uninit_drv(struct il_priv *il)
be663ab6 6394{
46bc8d4b
SG		 6395 il_free_geos(il);
6396 il_free_channel_map(il);
6397 kfree(il->scan_cmd);
be663ab6
WYG		 6398}
6399
e7392364
SG		 6400static void
6401il4965_hw_detect(struct il_priv *il)
be663ab6 6402{
841b2cca
SG		 6403 il->hw_rev = _il_rd(il, CSR_HW_REV);
6404 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
46bc8d4b 6405 il->rev_id = il->pci_dev->revision;
58de00a4 6406 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
be663ab6
WYG		 6407}
6408
1023f3bc
SG		 6409static struct il_sensitivity_ranges il4965_sensitivity = {
6410 .min_nrg_cck = 97,
6411 .max_nrg_cck = 0, /* not used, set to 0 */
6412
6413 .auto_corr_min_ofdm = 85,
6414 .auto_corr_min_ofdm_mrc = 170,
6415 .auto_corr_min_ofdm_x1 = 105,
6416 .auto_corr_min_ofdm_mrc_x1 = 220,
6417
6418 .auto_corr_max_ofdm = 120,
6419 .auto_corr_max_ofdm_mrc = 210,
6420 .auto_corr_max_ofdm_x1 = 140,
6421 .auto_corr_max_ofdm_mrc_x1 = 270,
6422
6423 .auto_corr_min_cck = 125,
6424 .auto_corr_max_cck = 200,
6425 .auto_corr_min_cck_mrc = 200,
6426 .auto_corr_max_cck_mrc = 400,
6427
6428 .nrg_th_cck = 100,
6429 .nrg_th_ofdm = 100,
6430
6431 .barker_corr_th_min = 190,
6432 .barker_corr_th_min_mrc = 390,
6433 .nrg_th_cca = 62,
6434};
6435
6436static void
e7392364 6437il4965_set_hw_params(struct il_priv *il)
be663ab6 6438{
b16db50a 6439 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
46bc8d4b
SG		 6440 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6441 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6442 if (il->cfg->mod_params->amsdu_size_8K)
6443 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
be663ab6 6444 else
46bc8d4b 6445 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
be663ab6 6446
46bc8d4b 6447 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
be663ab6 6448
46bc8d4b
SG		 6449 if (il->cfg->mod_params->disable_11n)
6450 il->cfg->sku &= ~IL_SKU_N;
be663ab6 6451
1023f3bc
SG		 6452 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6453 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6454 il->cfg->num_of_queues =
6455 il->cfg->mod_params->num_of_queues;
6456
6457 il->hw_params.max_txq_num = il->cfg->num_of_queues;
6458 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6459 il->hw_params.scd_bc_tbls_size =
6460 il->cfg->num_of_queues *
6461 sizeof(struct il4965_scd_bc_tbl);
6462
6463 il->hw_params.tfd_size = sizeof(struct il_tfd);
6464 il->hw_params.max_stations = IL4965_STATION_COUNT;
6465 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6466 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6467 il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6468 il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
6469
6470 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6471
6472 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6473 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6474 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6475 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6476
6477 il->hw_params.ct_kill_threshold =
6478 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6479
6480 il->hw_params.sens = &il4965_sensitivity;
6481 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
be663ab6
WYG		 6482}
6483
be663ab6 6484static int
e2ebc833 6485il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
be663ab6 6486{
7c2cde2e 6487 int err = 0;
46bc8d4b 6488 struct il_priv *il;
be663ab6 6489 struct ieee80211_hw *hw;
e2ebc833 6490 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
be663ab6
WYG		 6491 unsigned long flags;
6492 u16 pci_cmd;
6493
6494 /************************
6495 * 1. Allocating HW data
6496 ************************/
6497
c39ae9fd 6498 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
be663ab6
WYG		 6499 if (!hw) {
6500 err = -ENOMEM;
6501 goto out;
6502 }
46bc8d4b 6503 il = hw->priv;
c39ae9fd 6504 il->hw = hw;
be663ab6
WYG		 6505 SET_IEEE80211_DEV(hw, &pdev->dev);
6506
58de00a4 6507 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 6508 il->cfg = cfg;
c39ae9fd 6509 il->ops = &il4965_ops;
93b7654e
SG		 6510#ifdef CONFIG_IWLEGACY_DEBUGFS
6511 il->debugfs_ops = &il4965_debugfs_ops;
6512#endif
46bc8d4b
SG		 6513 il->pci_dev = pdev;
6514 il->inta_mask = CSR_INI_SET_MASK;
be663ab6 6515
be663ab6
WYG		 6516 /**************************
6517 * 2. Initializing PCI bus
6518 **************************/
e7392364
SG		 6519 pci_disable_link_state(pdev,
6520 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6521 PCIE_LINK_STATE_CLKPM);
be663ab6
WYG		 6522
6523 if (pci_enable_device(pdev)) {
6524 err = -ENODEV;
6525 goto out_ieee80211_free_hw;
6526 }
6527
6528 pci_set_master(pdev);
6529
6530 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6531 if (!err)
6532 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6533 if (err) {
6534 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6535 if (!err)
e7392364
SG		 6536 err =
6537 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
be663ab6
WYG		 6538 /* both attempts failed: */
6539 if (err) {
9406f797 6540 IL_WARN("No suitable DMA available.\n");
be663ab6
WYG		 6541 goto out_pci_disable_device;
6542 }
6543 }
6544
6545 err = pci_request_regions(pdev, DRV_NAME);
6546 if (err)
6547 goto out_pci_disable_device;
6548
46bc8d4b 6549 pci_set_drvdata(pdev, il);
be663ab6 6550
be663ab6
WYG		 6551 /***********************
6552 * 3. Read REV register
6553 ***********************/
a5f16137 6554 il->hw_base = pci_ioremap_bar(pdev, 0);
46bc8d4b 6555 if (!il->hw_base) {
be663ab6
WYG		 6556 err = -ENODEV;
6557 goto out_pci_release_regions;
6558 }
6559
58de00a4 6560 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 6561 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 6562 D_INFO("pci_resource_base = %p\n", il->hw_base);
be663ab6
WYG		 6563
6564 /* these spin locks will be used in apm_ops.init and EEPROM access
6565 * we should init now
6566 */
46bc8d4b
SG		 6567 spin_lock_init(&il->reg_lock);
6568 spin_lock_init(&il->lock);
be663ab6
WYG		 6569
6570 /*
6571 * stop and reset the on-board processor just in case it is in a
6572 * strange state ... like being left stranded by a primary kernel
6573 * and this is now the kdump kernel trying to start up
6574 */
841b2cca 6575 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6 6576
46bc8d4b 6577 il4965_hw_detect(il);
e7392364 6578 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
be663ab6
WYG		 6579
6580 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6581 * PCI Tx retries from interfering with C3 CPU state */
6582 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6583
46bc8d4b
SG		 6584 il4965_prepare_card_hw(il);
6585 if (!il->hw_ready) {
9406f797 6586 IL_WARN("Failed, HW not ready\n");
66284505 6587 err = -EIO;
be663ab6
WYG		 6588 goto out_iounmap;
6589 }
6590
6591 /*****************
6592 * 4. Read EEPROM
6593 *****************/
6594 /* Read the EEPROM */
46bc8d4b 6595 err = il_eeprom_init(il);
be663ab6 6596 if (err) {
9406f797 6597 IL_ERR("Unable to init EEPROM\n");
be663ab6
WYG		 6598 goto out_iounmap;
6599 }
46bc8d4b 6600 err = il4965_eeprom_check_version(il);
be663ab6
WYG		 6601 if (err)
6602 goto out_free_eeprom;
6603
be663ab6 6604 /* extract MAC Address */
46bc8d4b 6605 il4965_eeprom_get_mac(il, il->addresses[0].addr);
58de00a4 6606 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
46bc8d4b
SG		 6607 il->hw->wiphy->addresses = il->addresses;
6608 il->hw->wiphy->n_addresses = 1;
be663ab6
WYG		 6609
6610 /************************
6611 * 5. Setup HW constants
6612 ************************/
1023f3bc 6613 il4965_set_hw_params(il);
be663ab6
WYG		 6614
6615 /*******************
46bc8d4b 6616 * 6. Setup il
be663ab6
WYG		 6617 *******************/
6618
46bc8d4b 6619 err = il4965_init_drv(il);
be663ab6
WYG		 6620 if (err)
6621 goto out_free_eeprom;
46bc8d4b 6622 /* At this point both hw and il are initialized. */
be663ab6
WYG		 6623
6624 /********************
6625 * 7. Setup services
6626 ********************/
46bc8d4b
SG		 6627 spin_lock_irqsave(&il->lock, flags);
6628 il_disable_interrupts(il);
6629 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6630
46bc8d4b 6631 pci_enable_msi(il->pci_dev);
be663ab6 6632
e7392364 6633 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
be663ab6 6634 if (err) {
9406f797 6635 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
be663ab6
WYG		 6636 goto out_disable_msi;
6637 }
6638
46bc8d4b 6639 il4965_setup_deferred_work(il);
d0c72347 6640 il4965_setup_handlers(il);
be663ab6
WYG		 6641
6642 /*********************************************
6643 * 8. Enable interrupts and read RFKILL state
6644 *********************************************/
6645
a078a1fd 6646 /* enable rfkill interrupt: hw bug w/a */
46bc8d4b 6647 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
be663ab6
WYG		 6648 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6649 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
46bc8d4b 6650 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
be663ab6
WYG		 6651 }
6652
46bc8d4b 6653 il_enable_rfkill_int(il);
be663ab6
WYG		 6654
6655 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 6656 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
bc269a8e 6657 clear_bit(S_RFKILL, &il->status);
be663ab6 6658 else
bc269a8e 6659 set_bit(S_RFKILL, &il->status);
be663ab6 6660
46bc8d4b 6661 wiphy_rfkill_set_hw_state(il->hw->wiphy,
bc269a8e 6662 test_bit(S_RFKILL, &il->status));
be663ab6 6663
46bc8d4b 6664 il_power_initialize(il);
be663ab6 6665
46bc8d4b 6666 init_completion(&il->_4965.firmware_loading_complete);
be663ab6 6667
46bc8d4b 6668 err = il4965_request_firmware(il, true);
be663ab6
WYG		 6669 if (err)
6670 goto out_destroy_workqueue;
6671
6672 return 0;
6673
e7392364 6674out_destroy_workqueue:
46bc8d4b
SG		 6675 destroy_workqueue(il->workqueue);
6676 il->workqueue = NULL;
6677 free_irq(il->pci_dev->irq, il);
e7392364 6678out_disable_msi:
46bc8d4b
SG		 6679 pci_disable_msi(il->pci_dev);
6680 il4965_uninit_drv(il);
e7392364 6681out_free_eeprom:
46bc8d4b 6682 il_eeprom_free(il);
e7392364 6683out_iounmap:
a5f16137 6684 iounmap(il->hw_base);
e7392364 6685out_pci_release_regions:
be663ab6
WYG		 6686 pci_set_drvdata(pdev, NULL);
6687 pci_release_regions(pdev);
e7392364 6688out_pci_disable_device:
be663ab6 6689 pci_disable_device(pdev);
e7392364 6690out_ieee80211_free_hw:
46bc8d4b 6691 ieee80211_free_hw(il->hw);
e7392364 6692out:
be663ab6
WYG		 6693 return err;
6694}
6695
a027cb88 6696static void
e7392364 6697il4965_pci_remove(struct pci_dev *pdev)
be663ab6 6698{
46bc8d4b 6699 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 6700 unsigned long flags;
6701
46bc8d4b 6702 if (!il)
be663ab6
WYG		 6703 return;
6704
46bc8d4b 6705 wait_for_completion(&il->_4965.firmware_loading_complete);
be663ab6 6706
58de00a4 6707 D_INFO("*** UNLOAD DRIVER ***\n");
be663ab6 6708
46bc8d4b 6709 il_dbgfs_unregister(il);
e2ebc833 6710 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
be663ab6 6711
e2ebc833
SG		 6712 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6713 * to be called and il4965_down since we are removing the device
a6766ccd 6714 * we need to set S_EXIT_PENDING bit.
be663ab6 6715 */
a6766ccd 6716 set_bit(S_EXIT_PENDING, &il->status);
be663ab6 6717
46bc8d4b 6718 il_leds_exit(il);
be663ab6 6719
46bc8d4b
SG		 6720 if (il->mac80211_registered) {
6721 ieee80211_unregister_hw(il->hw);
6722 il->mac80211_registered = 0;
be663ab6 6723 } else {
46bc8d4b 6724 il4965_down(il);
be663ab6
WYG		 6725 }
6726
6727 /*
6728 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG		 6729 * This may be redundant with il4965_down(), but there are paths to
6730 * run il4965_down() without calling apm_ops.stop(), and there are
6731 * paths to avoid running il4965_down() at all before leaving driver.
be663ab6
WYG		 6732 * This (inexpensive) call *makes sure* device is reset.
6733 */
46bc8d4b 6734 il_apm_stop(il);
be663ab6
WYG		 6735
6736 /* make sure we flush any pending irq or
6737 * tasklet for the driver
6738 */
46bc8d4b
SG		 6739 spin_lock_irqsave(&il->lock, flags);
6740 il_disable_interrupts(il);
6741 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6742
46bc8d4b 6743 il4965_synchronize_irq(il);
be663ab6 6744
46bc8d4b 6745 il4965_dealloc_ucode_pci(il);
be663ab6 6746
46bc8d4b
SG		 6747 if (il->rxq.bd)
6748 il4965_rx_queue_free(il, &il->rxq);
6749 il4965_hw_txq_ctx_free(il);
be663ab6 6750
46bc8d4b 6751 il_eeprom_free(il);
be663ab6 6752
be663ab6 6753 /*netif_stop_queue(dev); */
46bc8d4b 6754 flush_workqueue(il->workqueue);
be663ab6 6755
e2ebc833 6756 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
46bc8d4b 6757 * il->workqueue... so we can't take down the workqueue
be663ab6 6758 * until now... */
46bc8d4b
SG		 6759 destroy_workqueue(il->workqueue);
6760 il->workqueue = NULL;
be663ab6 6761
46bc8d4b
SG		 6762 free_irq(il->pci_dev->irq, il);
6763 pci_disable_msi(il->pci_dev);
a5f16137 6764 iounmap(il->hw_base);
be663ab6
WYG		 6765 pci_release_regions(pdev);
6766 pci_disable_device(pdev);
6767 pci_set_drvdata(pdev, NULL);
6768
46bc8d4b 6769 il4965_uninit_drv(il);
be663ab6 6770
46bc8d4b 6771 dev_kfree_skb(il->beacon_skb);
be663ab6 6772
46bc8d4b 6773 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6774}
6775
6776/*
6777 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
46bc8d4b 6778 * must be called under il->lock and mac access
be663ab6 6779 */
e7392364
SG		 6780void
6781il4965_txq_set_sched(struct il_priv *il, u32 mask)
be663ab6 6782{
d3175167 6783 il_wr_prph(il, IL49_SCD_TXFACT, mask);
be663ab6
WYG		 6784}
6785
6786/*****************************************************************************
6787 *
6788 * driver and module entry point
6789 *
6790 *****************************************************************************/
6791
6792/* Hardware specific file defines the PCI IDs table for that hardware module */
e2ebc833 6793static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
e2ebc833
SG		 6794 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6795 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
be663ab6
WYG		 6796 {0}
6797};
e2ebc833 6798MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
be663ab6 6799
e2ebc833 6800static struct pci_driver il4965_driver = {
be663ab6 6801 .name = DRV_NAME,
e2ebc833
SG		 6802 .id_table = il4965_hw_card_ids,
6803 .probe = il4965_pci_probe,
a027cb88 6804 .remove = il4965_pci_remove,
e2ebc833 6805 .driver.pm = IL_LEGACY_PM_OPS,
be663ab6
WYG		 6806};
6807
e7392364
SG		 6808static int __init
6809il4965_init(void)
be663ab6
WYG		 6810{
6811
6812 int ret;
6813 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6814 pr_info(DRV_COPYRIGHT "\n");
6815
e2ebc833 6816 ret = il4965_rate_control_register();
be663ab6
WYG		 6817 if (ret) {
6818 pr_err("Unable to register rate control algorithm: %d\n", ret);
6819 return ret;
6820 }
6821
e2ebc833 6822 ret = pci_register_driver(&il4965_driver);
be663ab6
WYG		 6823 if (ret) {
6824 pr_err("Unable to initialize PCI module\n");
6825 goto error_register;
6826 }
6827
6828 return ret;
6829
6830error_register:
e2ebc833 6831 il4965_rate_control_unregister();
be663ab6
WYG		 6832 return ret;
6833}
6834
e7392364
SG		 6835static void __exit
6836il4965_exit(void)
be663ab6 6837{
e2ebc833
SG		 6838 pci_unregister_driver(&il4965_driver);
6839 il4965_rate_control_unregister();
be663ab6
WYG		 6840}
6841
e2ebc833
SG		 6842module_exit(il4965_exit);
6843module_init(il4965_init);
be663ab6 6844
d3175167 6845#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 6846module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
be663ab6
WYG		 6847MODULE_PARM_DESC(debug, "debug output mask");
6848#endif
6849
e2ebc833 6850module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
be663ab6 6851MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
e2ebc833 6852module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
be663ab6 6853MODULE_PARM_DESC(queues_num, "number of hw queues.");
e2ebc833 6854module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
be663ab6 6855MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
e7392364
SG		 6856module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6857 S_IRUGO);
be663ab6 6858MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
e2ebc833 6859module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
be663ab6 6860MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
Linux kernel - Deliverables
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