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iwlegacy: rename iwl-3945-{rs,debugfs}.c to 3945-{rs,debug}.c
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
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be663ab6
WYG		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
be663ab6
WYG		 43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
53#include "iwl-eeprom.h"
54#include "iwl-dev.h"
55#include "iwl-core.h"
56#include "iwl-io.h"
57#include "iwl-helpers.h"
58#include "iwl-sta.h"
59#include "iwl-4965-calib.h"
60#include "iwl-4965.h"
be663ab6
WYG		 61
62
63/******************************************************************************
64 *
65 * module boiler plate
66 *
67 ******************************************************************************/
68
69/*
70 * module name, copyright, version, etc.
71 */
72#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
73
d3175167 74#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 75#define VD "d"
76#else
77#define VD
78#endif
79
80#define DRV_VERSION IWLWIFI_VERSION VD
81
82
83MODULE_DESCRIPTION(DRV_DESCRIPTION);
84MODULE_VERSION(DRV_VERSION);
85MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
86MODULE_LICENSE("GPL");
87MODULE_ALIAS("iwl4965");
88
fcb74588
SG		 89void il4965_check_abort_status(struct il_priv *il,
90 u8 frame_count, u32 status)
91{
92 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
93 IL_ERR("Tx flush command to flush out all frames\n");
94 if (!test_bit(STATUS_EXIT_PENDING, &il->status))
95 queue_work(il->workqueue, &il->tx_flush);
96 }
97}
98
99/*
100 * EEPROM
101 */
102struct il_mod_params il4965_mod_params = {
103 .amsdu_size_8K = 1,
104 .restart_fw = 1,
105 /* the rest are 0 by default */
106};
107
108void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
109{
110 unsigned long flags;
111 int i;
112 spin_lock_irqsave(&rxq->lock, flags);
113 INIT_LIST_HEAD(&rxq->rx_free);
114 INIT_LIST_HEAD(&rxq->rx_used);
115 /* Fill the rx_used queue with _all_ of the Rx buffers */
116 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
117 /* In the reset function, these buffers may have been allocated
118 * to an SKB, so we need to unmap and free potential storage */
119 if (rxq->pool[i].page != NULL) {
120 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
121 PAGE_SIZE << il->hw_params.rx_page_order,
122 PCI_DMA_FROMDEVICE);
123 __il_free_pages(il, rxq->pool[i].page);
124 rxq->pool[i].page = NULL;
125 }
126 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
127 }
128
129 for (i = 0; i < RX_QUEUE_SIZE; i++)
130 rxq->queue[i] = NULL;
131
132 /* Set us so that we have processed and used all buffers, but have
133 * not restocked the Rx queue with fresh buffers */
134 rxq->read = rxq->write = 0;
135 rxq->write_actual = 0;
136 rxq->free_count = 0;
137 spin_unlock_irqrestore(&rxq->lock, flags);
138}
139
140int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
141{
142 u32 rb_size;
143 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
144 u32 rb_timeout = 0;
145
146 if (il->cfg->mod_params->amsdu_size_8K)
147 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
148 else
149 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
150
151 /* Stop Rx DMA */
152 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
153
154 /* Reset driver's Rx queue write idx */
155 il_wr(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
156
157 /* Tell device where to find RBD circular buffer in DRAM */
158 il_wr(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
159 (u32)(rxq->bd_dma >> 8));
160
161 /* Tell device where in DRAM to update its Rx status */
162 il_wr(il, FH_RSCSR_CHNL0_STTS_WPTR_REG,
163 rxq->rb_stts_dma >> 4);
164
165 /* Enable Rx DMA
166 * Direct rx interrupts to hosts
167 * Rx buffer size 4 or 8k
168 * RB timeout 0x10
169 * 256 RBDs
170 */
171 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG,
172 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
173 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
174 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
175 rb_size|
176 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
177 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
178
179 /* Set interrupt coalescing timer to default (2048 usecs) */
180 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
181
182 return 0;
183}
184
185static void il4965_set_pwr_vmain(struct il_priv *il)
186{
187/*
188 * (for documentation purposes)
189 * to set power to V_AUX, do:
190
191 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
192 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 */
196
197 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
198 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
199 ~APMG_PS_CTRL_MSK_PWR_SRC);
200}
201
202int il4965_hw_nic_init(struct il_priv *il)
203{
204 unsigned long flags;
205 struct il_rx_queue *rxq = &il->rxq;
206 int ret;
207
208 /* nic_init */
209 spin_lock_irqsave(&il->lock, flags);
210 il->cfg->ops->lib->apm_ops.init(il);
211
212 /* Set interrupt coalescing calibration timer to default (512 usecs) */
213 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
214
215 spin_unlock_irqrestore(&il->lock, flags);
216
217 il4965_set_pwr_vmain(il);
218
219 il->cfg->ops->lib->apm_ops.config(il);
220
221 /* Allocate the RX queue, or reset if it is already allocated */
222 if (!rxq->bd) {
223 ret = il_rx_queue_alloc(il);
224 if (ret) {
225 IL_ERR("Unable to initialize Rx queue\n");
226 return -ENOMEM;
227 }
228 } else
229 il4965_rx_queue_reset(il, rxq);
230
231 il4965_rx_replenish(il);
232
233 il4965_rx_init(il, rxq);
234
235 spin_lock_irqsave(&il->lock, flags);
236
237 rxq->need_update = 1;
238 il_rx_queue_update_write_ptr(il, rxq);
239
240 spin_unlock_irqrestore(&il->lock, flags);
241
242 /* Allocate or reset and init all Tx and Command queues */
243 if (!il->txq) {
244 ret = il4965_txq_ctx_alloc(il);
245 if (ret)
246 return ret;
247 } else
248 il4965_txq_ctx_reset(il);
249
250 set_bit(STATUS_INIT, &il->status);
251
252 return 0;
253}
254
255/**
256 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
257 */
258static inline __le32 il4965_dma_addr2rbd_ptr(struct il_priv *il,
259 dma_addr_t dma_addr)
260{
261 return cpu_to_le32((u32)(dma_addr >> 8));
262}
263
264/**
265 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
266 *
267 * If there are slots in the RX queue that need to be restocked,
268 * and we have free pre-allocated buffers, fill the ranks as much
269 * as we can, pulling from rx_free.
270 *
271 * This moves the 'write' idx forward to catch up with 'processed', and
272 * also updates the memory address in the firmware to reference the new
273 * target buffer.
274 */
275void il4965_rx_queue_restock(struct il_priv *il)
276{
277 struct il_rx_queue *rxq = &il->rxq;
278 struct list_head *element;
279 struct il_rx_buf *rxb;
280 unsigned long flags;
281
282 spin_lock_irqsave(&rxq->lock, flags);
283 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
284 /* The overwritten rxb must be a used one */
285 rxb = rxq->queue[rxq->write];
286 BUG_ON(rxb && rxb->page);
287
288 /* Get next free Rx buffer, remove from free list */
289 element = rxq->rx_free.next;
290 rxb = list_entry(element, struct il_rx_buf, list);
291 list_del(element);
292
293 /* Point to Rx buffer via next RBD in circular buffer */
294 rxq->bd[rxq->write] = il4965_dma_addr2rbd_ptr(il,
295 rxb->page_dma);
296 rxq->queue[rxq->write] = rxb;
297 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
298 rxq->free_count--;
299 }
300 spin_unlock_irqrestore(&rxq->lock, flags);
301 /* If the pre-allocated buffer pool is dropping low, schedule to
302 * refill it */
303 if (rxq->free_count <= RX_LOW_WATERMARK)
304 queue_work(il->workqueue, &il->rx_replenish);
305
306
307 /* If we've added more space for the firmware to place data, tell it.
308 * Increment device's write pointer in multiples of 8. */
309 if (rxq->write_actual != (rxq->write & ~0x7)) {
310 spin_lock_irqsave(&rxq->lock, flags);
311 rxq->need_update = 1;
312 spin_unlock_irqrestore(&rxq->lock, flags);
313 il_rx_queue_update_write_ptr(il, rxq);
314 }
315}
316
317/**
318 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
319 *
320 * When moving to rx_free an SKB is allocated for the slot.
321 *
322 * Also restock the Rx queue via il_rx_queue_restock.
323 * This is called as a scheduled work item (except for during initialization)
324 */
325static void il4965_rx_allocate(struct il_priv *il, gfp_t priority)
326{
327 struct il_rx_queue *rxq = &il->rxq;
328 struct list_head *element;
329 struct il_rx_buf *rxb;
330 struct page *page;
331 unsigned long flags;
332 gfp_t gfp_mask = priority;
333
334 while (1) {
335 spin_lock_irqsave(&rxq->lock, flags);
336 if (list_empty(&rxq->rx_used)) {
337 spin_unlock_irqrestore(&rxq->lock, flags);
338 return;
339 }
340 spin_unlock_irqrestore(&rxq->lock, flags);
341
342 if (rxq->free_count > RX_LOW_WATERMARK)
343 gfp_mask |= __GFP_NOWARN;
344
345 if (il->hw_params.rx_page_order > 0)
346 gfp_mask |= __GFP_COMP;
347
348 /* Alloc a new receive buffer */
349 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
350 if (!page) {
351 if (net_ratelimit())
352 D_INFO("alloc_pages failed, "
353 "order: %d\n",
354 il->hw_params.rx_page_order);
355
356 if (rxq->free_count <= RX_LOW_WATERMARK &&
357 net_ratelimit())
358 IL_ERR(
359 "Failed to alloc_pages with %s. "
360 "Only %u free buffers remaining.\n",
361 priority == GFP_ATOMIC ?
362 "GFP_ATOMIC" : "GFP_KERNEL",
363 rxq->free_count);
364 /* We don't reschedule replenish work here -- we will
365 * call the restock method and if it still needs
366 * more buffers it will schedule replenish */
367 return;
368 }
369
370 spin_lock_irqsave(&rxq->lock, flags);
371
372 if (list_empty(&rxq->rx_used)) {
373 spin_unlock_irqrestore(&rxq->lock, flags);
374 __free_pages(page, il->hw_params.rx_page_order);
375 return;
376 }
377 element = rxq->rx_used.next;
378 rxb = list_entry(element, struct il_rx_buf, list);
379 list_del(element);
380
381 spin_unlock_irqrestore(&rxq->lock, flags);
382
383 BUG_ON(rxb->page);
384 rxb->page = page;
385 /* Get physical address of the RB */
386 rxb->page_dma = pci_map_page(il->pci_dev, page, 0,
387 PAGE_SIZE << il->hw_params.rx_page_order,
388 PCI_DMA_FROMDEVICE);
389 /* dma address must be no more than 36 bits */
390 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
391 /* and also 256 byte aligned! */
392 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
393
394 spin_lock_irqsave(&rxq->lock, flags);
395
396 list_add_tail(&rxb->list, &rxq->rx_free);
397 rxq->free_count++;
398 il->alloc_rxb_page++;
399
400 spin_unlock_irqrestore(&rxq->lock, flags);
401 }
402}
403
404void il4965_rx_replenish(struct il_priv *il)
405{
406 unsigned long flags;
407
408 il4965_rx_allocate(il, GFP_KERNEL);
409
410 spin_lock_irqsave(&il->lock, flags);
411 il4965_rx_queue_restock(il);
412 spin_unlock_irqrestore(&il->lock, flags);
413}
414
415void il4965_rx_replenish_now(struct il_priv *il)
416{
417 il4965_rx_allocate(il, GFP_ATOMIC);
418
419 il4965_rx_queue_restock(il);
420}
421
422/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
423 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
424 * This free routine walks the list of POOL entries and if SKB is set to
425 * non NULL it is unmapped and freed
426 */
427void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
428{
429 int i;
430 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
431 if (rxq->pool[i].page != NULL) {
432 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
433 PAGE_SIZE << il->hw_params.rx_page_order,
434 PCI_DMA_FROMDEVICE);
435 __il_free_pages(il, rxq->pool[i].page);
436 rxq->pool[i].page = NULL;
437 }
438 }
439
440 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
441 rxq->bd_dma);
442 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
443 rxq->rb_stts, rxq->rb_stts_dma);
444 rxq->bd = NULL;
445 rxq->rb_stts = NULL;
446}
447
448int il4965_rxq_stop(struct il_priv *il)
449{
450
451 /* stop Rx DMA */
452 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
453 il_poll_bit(il, FH_MEM_RSSR_RX_STATUS_REG,
454 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
455
456 return 0;
457}
458
459int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
460{
461 int idx = 0;
462 int band_offset = 0;
463
464 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
465 if (rate_n_flags & RATE_MCS_HT_MSK) {
466 idx = (rate_n_flags & 0xff);
467 return idx;
468 /* Legacy rate format, search for match in table */
469 } else {
470 if (band == IEEE80211_BAND_5GHZ)
471 band_offset = IL_FIRST_OFDM_RATE;
472 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
473 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
474 return idx - band_offset;
475 }
476
477 return -1;
478}
479
480static int il4965_calc_rssi(struct il_priv *il,
481 struct il_rx_phy_res *rx_resp)
482{
483 /* data from PHY/DSP regarding signal strength, etc.,
484 * contents are always there, not configurable by host. */
485 struct il4965_rx_non_cfg_phy *ncphy =
486 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
487 u32 agc = (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK)
488 >> IL49_AGC_DB_POS;
489
490 u32 valid_antennae =
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
493 u8 max_rssi = 0;
494 u32 i;
495
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
504
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
507 max_rssi, agc);
508
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
512}
513
514
515static u32 il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
516{
517 u32 decrypt_out = 0;
518
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
520 RX_RES_STATUS_STATION_FOUND)
521 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
522 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
523
524 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
525
526 /* packet was not encrypted */
527 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
528 RX_RES_STATUS_SEC_TYPE_NONE)
529 return decrypt_out;
530
531 /* packet was encrypted with unknown alg */
532 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
533 RX_RES_STATUS_SEC_TYPE_ERR)
534 return decrypt_out;
535
536 /* decryption was not done in HW */
537 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
538 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
539 return decrypt_out;
540
541 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
542
543 case RX_RES_STATUS_SEC_TYPE_CCMP:
544 /* alg is CCM: check MIC only */
545 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
546 /* Bad MIC */
547 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
548 else
549 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
550
551 break;
552
553 case RX_RES_STATUS_SEC_TYPE_TKIP:
554 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
555 /* Bad TTAK */
556 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
557 break;
558 }
559 /* fall through if TTAK OK */
560 default:
561 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
562 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
563 else
564 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
565 break;
566 }
567
568 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
569 decrypt_in, decrypt_out);
570
571 return decrypt_out;
572}
573
574static void il4965_pass_packet_to_mac80211(struct il_priv *il,
575 struct ieee80211_hdr *hdr,
576 u16 len,
577 u32 ampdu_status,
578 struct il_rx_buf *rxb,
579 struct ieee80211_rx_status *stats)
580{
581 struct sk_buff *skb;
582 __le16 fc = hdr->frame_control;
583
584 /* We only process data packets if the interface is open */
585 if (unlikely(!il->is_open)) {
586 D_DROP(
587 "Dropping packet while interface is not open.\n");
588 return;
589 }
590
591 /* In case of HW accelerated crypto and bad decryption, drop */
592 if (!il->cfg->mod_params->sw_crypto &&
593 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
594 return;
595
596 skb = dev_alloc_skb(128);
597 if (!skb) {
598 IL_ERR("dev_alloc_skb failed\n");
599 return;
600 }
601
602 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
603
604 il_update_stats(il, false, fc, len);
605 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
606
607 ieee80211_rx(il->hw, skb);
608 il->alloc_rxb_page--;
609 rxb->page = NULL;
610}
611
612/* Called for REPLY_RX (legacy ABG frames), or
613 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
614void il4965_rx_reply_rx(struct il_priv *il,
615 struct il_rx_buf *rxb)
616{
617 struct ieee80211_hdr *header;
618 struct ieee80211_rx_status rx_status;
619 struct il_rx_pkt *pkt = rxb_addr(rxb);
620 struct il_rx_phy_res *phy_res;
621 __le32 rx_pkt_status;
622 struct il_rx_mpdu_res_start *amsdu;
623 u32 len;
624 u32 ampdu_status;
625 u32 rate_n_flags;
626
627 /**
628 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
629 * REPLY_RX: physical layer info is in this buffer
630 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
631 * command and cached in il->last_phy_res
632 *
633 * Here we set up local variables depending on which command is
634 * received.
635 */
636 if (pkt->hdr.cmd == REPLY_RX) {
637 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
638 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
639 + phy_res->cfg_phy_cnt);
640
641 len = le16_to_cpu(phy_res->byte_count);
642 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
643 phy_res->cfg_phy_cnt + len);
644 ampdu_status = le32_to_cpu(rx_pkt_status);
645 } else {
646 if (!il->_4965.last_phy_res_valid) {
647 IL_ERR("MPDU frame without cached PHY data\n");
648 return;
649 }
650 phy_res = &il->_4965.last_phy_res;
651 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
652 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
653 len = le16_to_cpu(amsdu->byte_count);
654 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
655 ampdu_status = il4965_translate_rx_status(il,
656 le32_to_cpu(rx_pkt_status));
657 }
658
659 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
660 D_DROP("dsp size out of range [0,20]: %d/n",
661 phy_res->cfg_phy_cnt);
662 return;
663 }
664
665 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
666 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
667 D_RX("Bad CRC or FIFO: 0x%08X.\n",
668 le32_to_cpu(rx_pkt_status));
669 return;
670 }
671
672 /* This will be used in several places later */
673 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
674
675 /* rx_status carries information about the packet to mac80211 */
676 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
677 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
678 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
679 rx_status.freq =
680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
681 rx_status.band);
682 rx_status.rate_idx =
683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
684 rx_status.flag = 0;
685
686 /* TSF isn't reliable. In order to allow smooth user experience,
687 * this W/A doesn't propagate it to the mac80211 */
688 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU;*/
689
690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
691
692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
693 rx_status.signal = il4965_calc_rssi(il, phy_res);
694
695 il_dbg_log_rx_data_frame(il, len, header);
696 D_STATS("Rssi %d, TSF %llu\n",
697 rx_status.signal, (unsigned long long)rx_status.mactime);
698
699 /*
700 * "antenna number"
701 *
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
707 *
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
710 * as a bitmask.
711 */
712 rx_status.antenna =
713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
714 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
715
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
719
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
727
728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status,
729 rxb, &rx_status);
730}
731
732/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
733 * This will be used later in il_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
734void il4965_rx_reply_rx_phy(struct il_priv *il,
735 struct il_rx_buf *rxb)
736{
737 struct il_rx_pkt *pkt = rxb_addr(rxb);
738 il->_4965.last_phy_res_valid = true;
739 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
740 sizeof(struct il_rx_phy_res));
741}
742
743static int il4965_get_channels_for_scan(struct il_priv *il,
744 struct ieee80211_vif *vif,
745 enum ieee80211_band band,
746 u8 is_active, u8 n_probes,
747 struct il_scan_channel *scan_ch)
748{
749 struct ieee80211_channel *chan;
750 const struct ieee80211_supported_band *sband;
751 const struct il_channel_info *ch_info;
752 u16 passive_dwell = 0;
753 u16 active_dwell = 0;
754 int added, i;
755 u16 channel;
756
757 sband = il_get_hw_mode(il, band);
758 if (!sband)
759 return 0;
760
761 active_dwell = il_get_active_dwell_time(il, band, n_probes);
762 passive_dwell = il_get_passive_dwell_time(il, band, vif);
763
764 if (passive_dwell <= active_dwell)
765 passive_dwell = active_dwell + 1;
766
767 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
768 chan = il->scan_request->channels[i];
769
770 if (chan->band != band)
771 continue;
772
773 channel = chan->hw_value;
774 scan_ch->channel = cpu_to_le16(channel);
775
776 ch_info = il_get_channel_info(il, band, channel);
777 if (!il_is_channel_valid(ch_info)) {
778 D_SCAN(
779 "Channel %d is INVALID for this band.\n",
780 channel);
781 continue;
782 }
783
784 if (!is_active || il_is_channel_passive(ch_info) ||
785 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
786 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
787 else
788 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
789
790 if (n_probes)
791 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
792
793 scan_ch->active_dwell = cpu_to_le16(active_dwell);
794 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
795
796 /* Set txpower levels to defaults */
797 scan_ch->dsp_atten = 110;
798
799 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
800 * power level:
801 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
802 */
803 if (band == IEEE80211_BAND_5GHZ)
804 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
805 else
806 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
807
808 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n",
809 channel, le32_to_cpu(scan_ch->type),
810 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
811 "ACTIVE" : "PASSIVE",
812 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
813 active_dwell : passive_dwell);
814
815 scan_ch++;
816 added++;
817 }
818
819 D_SCAN("total channels to scan %d\n", added);
820 return added;
821}
822
823int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
824{
825 struct il_host_cmd cmd = {
826 .id = REPLY_SCAN_CMD,
827 .len = sizeof(struct il_scan_cmd),
828 .flags = CMD_SIZE_HUGE,
829 };
830 struct il_scan_cmd *scan;
831 struct il_rxon_context *ctx = &il->ctx;
832 u32 rate_flags = 0;
833 u16 cmd_len;
834 u16 rx_chain = 0;
835 enum ieee80211_band band;
836 u8 n_probes = 0;
837 u8 rx_ant = il->hw_params.valid_rx_ant;
838 u8 rate;
839 bool is_active = false;
840 int chan_mod;
841 u8 active_chains;
842 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
843 int ret;
844
845 lockdep_assert_held(&il->mutex);
846
847 if (vif)
848 ctx = il_rxon_ctx_from_vif(vif);
849
850 if (!il->scan_cmd) {
851 il->scan_cmd = kmalloc(sizeof(struct il_scan_cmd) +
852 IL_MAX_SCAN_SIZE, GFP_KERNEL);
853 if (!il->scan_cmd) {
854 D_SCAN(
855 "fail to allocate memory for scan\n");
856 return -ENOMEM;
857 }
858 }
859 scan = il->scan_cmd;
860 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
861
862 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
863 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
864
865 if (il_is_any_associated(il)) {
866 u16 interval;
867 u32 extra;
868 u32 suspend_time = 100;
869 u32 scan_suspend_time = 100;
870
871 D_INFO("Scanning while associated...\n");
872 interval = vif->bss_conf.beacon_int;
873
874 scan->suspend_time = 0;
875 scan->max_out_time = cpu_to_le32(200 * 1024);
876 if (!interval)
877 interval = suspend_time;
878
879 extra = (suspend_time / interval) << 22;
880 scan_suspend_time = (extra |
881 ((suspend_time % interval) * 1024));
882 scan->suspend_time = cpu_to_le32(scan_suspend_time);
883 D_SCAN("suspend_time 0x%X beacon interval %d\n",
884 scan_suspend_time, interval);
885 }
886
887 if (il->scan_request->n_ssids) {
888 int i, p = 0;
889 D_SCAN("Kicking off active scan\n");
890 for (i = 0; i < il->scan_request->n_ssids; i++) {
891 /* always does wildcard anyway */
892 if (!il->scan_request->ssids[i].ssid_len)
893 continue;
894 scan->direct_scan[p].id = WLAN_EID_SSID;
895 scan->direct_scan[p].len =
896 il->scan_request->ssids[i].ssid_len;
897 memcpy(scan->direct_scan[p].ssid,
898 il->scan_request->ssids[i].ssid,
899 il->scan_request->ssids[i].ssid_len);
900 n_probes++;
901 p++;
902 }
903 is_active = true;
904 } else
905 D_SCAN("Start passive scan.\n");
906
907 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
908 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
909 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
910
911 switch (il->scan_band) {
912 case IEEE80211_BAND_2GHZ:
913 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
914 chan_mod = le32_to_cpu(
915 il->ctx.active.flags &
916 RXON_FLG_CHANNEL_MODE_MSK)
917 >> RXON_FLG_CHANNEL_MODE_POS;
918 if (chan_mod == CHANNEL_MODE_PURE_40) {
919 rate = RATE_6M_PLCP;
920 } else {
921 rate = RATE_1M_PLCP;
922 rate_flags = RATE_MCS_CCK_MSK;
923 }
924 break;
925 case IEEE80211_BAND_5GHZ:
926 rate = RATE_6M_PLCP;
927 break;
928 default:
929 IL_WARN("Invalid scan band\n");
930 return -EIO;
931 }
932
933 /*
934 * If active scanning is requested but a certain channel is
935 * marked passive, we can do active scanning if we detect
936 * transmissions.
937 *
938 * There is an issue with some firmware versions that triggers
939 * a sysassert on a "good CRC threshold" of zero (== disabled),
940 * on a radar channel even though this means that we should NOT
941 * send probes.
942 *
943 * The "good CRC threshold" is the number of frames that we
944 * need to receive during our dwell time on a channel before
945 * sending out probes -- setting this to a huge value will
946 * mean we never reach it, but at the same time work around
947 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
948 * here instead of IL_GOOD_CRC_TH_DISABLED.
949 */
950 scan->good_CRC_th = is_active ? IL_GOOD_CRC_TH_DEFAULT :
951 IL_GOOD_CRC_TH_NEVER;
952
953 band = il->scan_band;
954
955 if (il->cfg->scan_rx_antennas[band])
956 rx_ant = il->cfg->scan_rx_antennas[band];
957
958 il->scan_tx_ant[band] = il4965_toggle_tx_ant(il,
959 il->scan_tx_ant[band],
960 scan_tx_antennas);
961 rate_flags |= il4965_ant_idx_to_flags(il->scan_tx_ant[band]);
962 scan->tx_cmd.rate_n_flags = il4965_hw_set_rate_n_flags(rate, rate_flags);
963
964 /* In power save mode use one chain, otherwise use all chains */
965 if (test_bit(STATUS_POWER_PMI, &il->status)) {
966 /* rx_ant has been set to all valid chains previously */
967 active_chains = rx_ant &
968 ((u8)(il->chain_noise_data.active_chains));
969 if (!active_chains)
970 active_chains = rx_ant;
971
972 D_SCAN("chain_noise_data.active_chains: %u\n",
973 il->chain_noise_data.active_chains);
974
975 rx_ant = il4965_first_antenna(active_chains);
976 }
977
978 /* MIMO is not used here, but value is required */
979 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
980 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
981 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
982 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
983 scan->rx_chain = cpu_to_le16(rx_chain);
984
985 cmd_len = il_fill_probe_req(il,
986 (struct ieee80211_mgmt *)scan->data,
987 vif->addr,
988 il->scan_request->ie,
989 il->scan_request->ie_len,
990 IL_MAX_SCAN_SIZE - sizeof(*scan));
991 scan->tx_cmd.len = cpu_to_le16(cmd_len);
992
993 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
994 RXON_FILTER_BCON_AWARE_MSK);
995
996 scan->channel_count = il4965_get_channels_for_scan(il, vif, band,
997 is_active, n_probes,
998 (void *)&scan->data[cmd_len]);
999 if (scan->channel_count == 0) {
1000 D_SCAN("channel count %d\n", scan->channel_count);
1001 return -EIO;
1002 }
1003
1004 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1005 scan->channel_count * sizeof(struct il_scan_channel);
1006 cmd.data = scan;
1007 scan->len = cpu_to_le16(cmd.len);
1008
1009 set_bit(STATUS_SCAN_HW, &il->status);
1010
1011 ret = il_send_cmd_sync(il, &cmd);
1012 if (ret)
1013 clear_bit(STATUS_SCAN_HW, &il->status);
1014
1015 return ret;
1016}
1017
1018int il4965_manage_ibss_station(struct il_priv *il,
1019 struct ieee80211_vif *vif, bool add)
1020{
1021 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1022
1023 if (add)
1024 return il4965_add_bssid_station(il, vif_priv->ctx,
1025 vif->bss_conf.bssid,
1026 &vif_priv->ibss_bssid_sta_id);
1027 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
1028 vif->bss_conf.bssid);
1029}
1030
1031void il4965_free_tfds_in_queue(struct il_priv *il,
1032 int sta_id, int tid, int freed)
1033{
1034 lockdep_assert_held(&il->sta_lock);
1035
1036 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1037 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1038 else {
1039 D_TX("free more than tfds_in_queue (%u:%d)\n",
1040 il->stations[sta_id].tid[tid].tfds_in_queue,
1041 freed);
1042 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1043 }
1044}
1045
1046#define IL_TX_QUEUE_MSK 0xfffff
1047
1048static bool il4965_is_single_rx_stream(struct il_priv *il)
1049{
1050 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1051 il->current_ht_config.single_chain_sufficient;
1052}
1053
1054#define IL_NUM_RX_CHAINS_MULTIPLE 3
1055#define IL_NUM_RX_CHAINS_SINGLE 2
1056#define IL_NUM_IDLE_CHAINS_DUAL 2
1057#define IL_NUM_IDLE_CHAINS_SINGLE 1
1058
1059/*
1060 * Determine how many receiver/antenna chains to use.
1061 *
1062 * More provides better reception via diversity. Fewer saves power
1063 * at the expense of throughput, but only when not in powersave to
1064 * start with.
1065 *
1066 * MIMO (dual stream) requires at least 2, but works better with 3.
1067 * This does not determine *which* chains to use, just how many.
1068 */
1069static int il4965_get_active_rx_chain_count(struct il_priv *il)
1070{
1071 /* # of Rx chains to use when expecting MIMO. */
1072 if (il4965_is_single_rx_stream(il))
1073 return IL_NUM_RX_CHAINS_SINGLE;
1074 else
1075 return IL_NUM_RX_CHAINS_MULTIPLE;
1076}
1077
1078/*
1079 * When we are in power saving mode, unless device support spatial
1080 * multiplexing power save, use the active count for rx chain count.
1081 */
1082static int
1083il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1084{
1085 /* # Rx chains when idling, depending on SMPS mode */
1086 switch (il->current_ht_config.smps) {
1087 case IEEE80211_SMPS_STATIC:
1088 case IEEE80211_SMPS_DYNAMIC:
1089 return IL_NUM_IDLE_CHAINS_SINGLE;
1090 case IEEE80211_SMPS_OFF:
1091 return active_cnt;
1092 default:
1093 WARN(1, "invalid SMPS mode %d",
1094 il->current_ht_config.smps);
1095 return active_cnt;
1096 }
1097}
1098
1099/* up to 4 chains */
1100static u8 il4965_count_chain_bitmap(u32 chain_bitmap)
1101{
1102 u8 res;
1103 res = (chain_bitmap & BIT(0)) >> 0;
1104 res += (chain_bitmap & BIT(1)) >> 1;
1105 res += (chain_bitmap & BIT(2)) >> 2;
1106 res += (chain_bitmap & BIT(3)) >> 3;
1107 return res;
1108}
1109
1110/**
1111 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1112 *
1113 * Selects how many and which Rx receivers/antennas/chains to use.
1114 * This should not be used for scan command ... it puts data in wrong place.
1115 */
1116void il4965_set_rxon_chain(struct il_priv *il, struct il_rxon_context *ctx)
1117{
1118 bool is_single = il4965_is_single_rx_stream(il);
1119 bool is_cam = !test_bit(STATUS_POWER_PMI, &il->status);
1120 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1121 u32 active_chains;
1122 u16 rx_chain;
1123
1124 /* Tell uCode which antennas are actually connected.
1125 * Before first association, we assume all antennas are connected.
1126 * Just after first association, il4965_chain_noise_calibration()
1127 * checks which antennas actually *are* connected. */
1128 if (il->chain_noise_data.active_chains)
1129 active_chains = il->chain_noise_data.active_chains;
1130 else
1131 active_chains = il->hw_params.valid_rx_ant;
1132
1133 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1134
1135 /* How many receivers should we use? */
1136 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1137 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1138
1139
1140 /* correct rx chain count according hw settings
1141 * and chain noise calibration
1142 */
1143 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1144 if (valid_rx_cnt < active_rx_cnt)
1145 active_rx_cnt = valid_rx_cnt;
1146
1147 if (valid_rx_cnt < idle_rx_cnt)
1148 idle_rx_cnt = valid_rx_cnt;
1149
1150 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1151 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1152
1153 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
1154
1155 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1156 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1157 else
1158 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1159
1160 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
1161 ctx->staging.rx_chain,
1162 active_rx_cnt, idle_rx_cnt);
1163
1164 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1165 active_rx_cnt < idle_rx_cnt);
1166}
1167
1168u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant, u8 valid)
1169{
1170 int i;
1171 u8 ind = ant;
1172
1173 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
1174 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
1175 if (valid & BIT(ind))
1176 return ind;
1177 }
1178 return ant;
1179}
1180
1181static const char *il4965_get_fh_string(int cmd)
1182{
1183 switch (cmd) {
1184 IL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1185 IL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1186 IL_CMD(FH_RSCSR_CHNL0_WPTR);
1187 IL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1188 IL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1189 IL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1190 IL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1191 IL_CMD(FH_TSSR_TX_STATUS_REG);
1192 IL_CMD(FH_TSSR_TX_ERROR_REG);
1193 default:
1194 return "UNKNOWN";
1195 }
1196}
1197
1198int il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1199{
1200 int i;
1201#ifdef CONFIG_IWLEGACY_DEBUG
1202 int pos = 0;
1203 size_t bufsz = 0;
1204#endif
1205 static const u32 fh_tbl[] = {
1206 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1207 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1208 FH_RSCSR_CHNL0_WPTR,
1209 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1210 FH_MEM_RSSR_SHARED_CTRL_REG,
1211 FH_MEM_RSSR_RX_STATUS_REG,
1212 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1213 FH_TSSR_TX_STATUS_REG,
1214 FH_TSSR_TX_ERROR_REG
1215 };
1216#ifdef CONFIG_IWLEGACY_DEBUG
1217 if (display) {
1218 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1219 *buf = kmalloc(bufsz, GFP_KERNEL);
1220 if (!*buf)
1221 return -ENOMEM;
1222 pos += scnprintf(*buf + pos, bufsz - pos,
1223 "FH register values:\n");
1224 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1225 pos += scnprintf(*buf + pos, bufsz - pos,
1226 " %34s: 0X%08x\n",
1227 il4965_get_fh_string(fh_tbl[i]),
1228 il_rd(il, fh_tbl[i]));
1229 }
1230 return pos;
1231 }
1232#endif
1233 IL_ERR("FH register values:\n");
1234 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1235 IL_ERR(" %34s: 0X%08x\n",
1236 il4965_get_fh_string(fh_tbl[i]),
1237 il_rd(il, fh_tbl[i]));
1238 }
1239 return 0;
1240}
a1751b22
SG		 1241void il4965_rx_missed_beacon_notif(struct il_priv *il,
1242 struct il_rx_buf *rxb)
1243
1244{
1245 struct il_rx_pkt *pkt = rxb_addr(rxb);
1246 struct il_missed_beacon_notif *missed_beacon;
1247
1248 missed_beacon = &pkt->u.missed_beacon;
1249 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1250 il->missed_beacon_threshold) {
1251 D_CALIB(
1252 "missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1253 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1254 le32_to_cpu(missed_beacon->total_missed_becons),
1255 le32_to_cpu(missed_beacon->num_recvd_beacons),
1256 le32_to_cpu(missed_beacon->num_expected_beacons));
1257 if (!test_bit(STATUS_SCANNING, &il->status))
1258 il4965_init_sensitivity(il);
1259 }
1260}
1261
1262/* Calculate noise level, based on measurements during network silence just
1263 * before arriving beacon. This measurement can be done only if we know
1264 * exactly when to expect beacons, therefore only when we're associated. */
1265static void il4965_rx_calc_noise(struct il_priv *il)
1266{
1267 struct stats_rx_non_phy *rx_info;
1268 int num_active_rx = 0;
1269 int total_silence = 0;
1270 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1271 int last_rx_noise;
1272
1273 rx_info = &(il->_4965.stats.rx.general);
1274 bcn_silence_a =
1275 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1276 bcn_silence_b =
1277 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1278 bcn_silence_c =
1279 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1280
1281 if (bcn_silence_a) {
1282 total_silence += bcn_silence_a;
1283 num_active_rx++;
1284 }
1285 if (bcn_silence_b) {
1286 total_silence += bcn_silence_b;
1287 num_active_rx++;
1288 }
1289 if (bcn_silence_c) {
1290 total_silence += bcn_silence_c;
1291 num_active_rx++;
1292 }
1293
1294 /* Average among active antennas */
1295 if (num_active_rx)
1296 last_rx_noise = (total_silence / num_active_rx) - 107;
1297 else
1298 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1299
1300 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
1301 bcn_silence_a, bcn_silence_b, bcn_silence_c,
1302 last_rx_noise);
1303}
1304
1305#ifdef CONFIG_IWLEGACY_DEBUGFS
1306/*
1307 * based on the assumption of all stats counter are in DWORD
1308 * FIXME: This function is for debugging, do not deal with
1309 * the case of counters roll-over.
1310 */
1311static void il4965_accumulative_stats(struct il_priv *il,
1312 __le32 *stats)
1313{
1314 int i, size;
1315 __le32 *prev_stats;
1316 u32 *accum_stats;
1317 u32 *delta, *max_delta;
1318 struct stats_general_common *general, *accum_general;
1319 struct stats_tx *tx, *accum_tx;
1320
1321 prev_stats = (__le32 *)&il->_4965.stats;
1322 accum_stats = (u32 *)&il->_4965.accum_stats;
1323 size = sizeof(struct il_notif_stats);
1324 general = &il->_4965.stats.general.common;
1325 accum_general = &il->_4965.accum_stats.general.common;
1326 tx = &il->_4965.stats.tx;
1327 accum_tx = &il->_4965.accum_stats.tx;
1328 delta = (u32 *)&il->_4965.delta_stats;
1329 max_delta = (u32 *)&il->_4965.max_delta;
1330
1331 for (i = sizeof(__le32); i < size;
1332 i += sizeof(__le32), stats++, prev_stats++, delta++,
1333 max_delta++, accum_stats++) {
1334 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
1335 *delta = (le32_to_cpu(*stats) -
1336 le32_to_cpu(*prev_stats));
1337 *accum_stats += *delta;
1338 if (*delta > *max_delta)
1339 *max_delta = *delta;
1340 }
1341 }
1342
1343 /* reset accumulative stats for "no-counter" type stats */
1344 accum_general->temperature = general->temperature;
1345 accum_general->ttl_timestamp = general->ttl_timestamp;
1346}
1347#endif
1348
1349#define REG_RECALIB_PERIOD (60)
1350
1351void il4965_rx_stats(struct il_priv *il,
1352 struct il_rx_buf *rxb)
1353{
1354 int change;
1355 struct il_rx_pkt *pkt = rxb_addr(rxb);
1356
1357 D_RX(
1358 "Statistics notification received (%d vs %d).\n",
1359 (int)sizeof(struct il_notif_stats),
1360 le32_to_cpu(pkt->len_n_flags) &
1361 FH_RSCSR_FRAME_SIZE_MSK);
1362
1363 change = ((il->_4965.stats.general.common.temperature !=
1364 pkt->u.stats.general.common.temperature) ||
1365 ((il->_4965.stats.flag &
1366 STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
1367 (pkt->u.stats.flag &
1368 STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
1369#ifdef CONFIG_IWLEGACY_DEBUGFS
1370 il4965_accumulative_stats(il, (__le32 *)&pkt->u.stats);
1371#endif
1372
1373 /* TODO: reading some of stats is unneeded */
1374 memcpy(&il->_4965.stats, &pkt->u.stats,
1375 sizeof(il->_4965.stats));
1376
1377 set_bit(STATUS_STATISTICS, &il->status);
1378
1379 /* Reschedule the stats timer to occur in
1380 * REG_RECALIB_PERIOD seconds to ensure we get a
1381 * thermal update even if the uCode doesn't give
1382 * us one */
1383 mod_timer(&il->stats_periodic, jiffies +
1384 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
1385
1386 if (unlikely(!test_bit(STATUS_SCANNING, &il->status)) &&
1387 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
1388 il4965_rx_calc_noise(il);
1389 queue_work(il->workqueue, &il->run_time_calib_work);
1390 }
1391 if (il->cfg->ops->lib->temp_ops.temperature && change)
1392 il->cfg->ops->lib->temp_ops.temperature(il);
1393}
1394
1395void il4965_reply_stats(struct il_priv *il,
1396 struct il_rx_buf *rxb)
1397{
1398 struct il_rx_pkt *pkt = rxb_addr(rxb);
1399
1400 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) {
1401#ifdef CONFIG_IWLEGACY_DEBUGFS
1402 memset(&il->_4965.accum_stats, 0,
1403 sizeof(struct il_notif_stats));
1404 memset(&il->_4965.delta_stats, 0,
1405 sizeof(struct il_notif_stats));
1406 memset(&il->_4965.max_delta, 0,
1407 sizeof(struct il_notif_stats));
1408#endif
1409 D_RX("Statistics have been cleared\n");
1410 }
1411 il4965_rx_stats(il, rxb);
1412}
1413
1414static const u8 tid_to_ac[] = {
1415 IEEE80211_AC_BE,
1416 IEEE80211_AC_BK,
1417 IEEE80211_AC_BK,
1418 IEEE80211_AC_BE,
1419 IEEE80211_AC_VI,
1420 IEEE80211_AC_VI,
1421 IEEE80211_AC_VO,
1422 IEEE80211_AC_VO
1423};
1424
1425static inline int il4965_get_ac_from_tid(u16 tid)
1426{
1427 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1428 return tid_to_ac[tid];
1429
1430 /* no support for TIDs 8-15 yet */
1431 return -EINVAL;
1432}
1433
1434static inline int
1435il4965_get_fifo_from_tid(struct il_rxon_context *ctx, u16 tid)
1436{
1437 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1438 return ctx->ac_to_fifo[tid_to_ac[tid]];
1439
1440 /* no support for TIDs 8-15 yet */
1441 return -EINVAL;
1442}
1443
1444/*
1445 * handle build REPLY_TX command notification.
1446 */
1447static void il4965_tx_cmd_build_basic(struct il_priv *il,
1448 struct sk_buff *skb,
1449 struct il_tx_cmd *tx_cmd,
1450 struct ieee80211_tx_info *info,
1451 struct ieee80211_hdr *hdr,
1452 u8 std_id)
1453{
1454 __le16 fc = hdr->frame_control;
1455 __le32 tx_flags = tx_cmd->tx_flags;
1456
1457 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1458 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1459 tx_flags |= TX_CMD_FLG_ACK_MSK;
1460 if (ieee80211_is_mgmt(fc))
1461 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1462 if (ieee80211_is_probe_resp(fc) &&
1463 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1464 tx_flags |= TX_CMD_FLG_TSF_MSK;
1465 } else {
1466 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1467 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1468 }
1469
1470 if (ieee80211_is_back_req(fc))
1471 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1472
1473 tx_cmd->sta_id = std_id;
1474 if (ieee80211_has_morefrags(fc))
1475 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1476
1477 if (ieee80211_is_data_qos(fc)) {
1478 u8 *qc = ieee80211_get_qos_ctl(hdr);
1479 tx_cmd->tid_tspec = qc[0] & 0xf;
1480 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1481 } else {
1482 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1483 }
1484
1485 il_tx_cmd_protection(il, info, fc, &tx_flags);
1486
1487 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1488 if (ieee80211_is_mgmt(fc)) {
1489 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1490 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1491 else
1492 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1493 } else {
1494 tx_cmd->timeout.pm_frame_timeout = 0;
1495 }
1496
1497 tx_cmd->driver_txop = 0;
1498 tx_cmd->tx_flags = tx_flags;
1499 tx_cmd->next_frame_len = 0;
1500}
1501
1502#define RTS_DFAULT_RETRY_LIMIT 60
1503
1504static void il4965_tx_cmd_build_rate(struct il_priv *il,
1505 struct il_tx_cmd *tx_cmd,
1506 struct ieee80211_tx_info *info,
1507 __le16 fc)
1508{
1509 u32 rate_flags;
1510 int rate_idx;
1511 u8 rts_retry_limit;
1512 u8 data_retry_limit;
1513 u8 rate_plcp;
1514
1515 /* Set retry limit on DATA packets and Probe Responses*/
1516 if (ieee80211_is_probe_resp(fc))
1517 data_retry_limit = 3;
1518 else
1519 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1520 tx_cmd->data_retry_limit = data_retry_limit;
1521
1522 /* Set retry limit on RTS packets */
1523 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
1524 if (data_retry_limit < rts_retry_limit)
1525 rts_retry_limit = data_retry_limit;
1526 tx_cmd->rts_retry_limit = rts_retry_limit;
1527
1528 /* DATA packets will use the uCode station table for rate/antenna
1529 * selection */
1530 if (ieee80211_is_data(fc)) {
1531 tx_cmd->initial_rate_idx = 0;
1532 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1533 return;
1534 }
1535
1536 /**
1537 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1538 * not really a TX rate. Thus, we use the lowest supported rate for
1539 * this band. Also use the lowest supported rate if the stored rate
1540 * idx is invalid.
1541 */
1542 rate_idx = info->control.rates[0].idx;
1543 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) ||
1544 rate_idx < 0 || rate_idx > RATE_COUNT_LEGACY)
1545 rate_idx = rate_lowest_index(&il->bands[info->band],
1546 info->control.sta);
1547 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1548 if (info->band == IEEE80211_BAND_5GHZ)
1549 rate_idx += IL_FIRST_OFDM_RATE;
1550 /* Get PLCP rate for tx_cmd->rate_n_flags */
1551 rate_plcp = il_rates[rate_idx].plcp;
1552 /* Zero out flags for this packet */
1553 rate_flags = 0;
1554
1555 /* Set CCK flag as needed */
1556 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1557 rate_flags |= RATE_MCS_CCK_MSK;
1558
1559 /* Set up antennas */
1560 il->mgmt_tx_ant = il4965_toggle_tx_ant(il, il->mgmt_tx_ant,
1561 il->hw_params.valid_tx_ant);
1562
1563 rate_flags |= il4965_ant_idx_to_flags(il->mgmt_tx_ant);
1564
1565 /* Set the rate in the TX cmd */
1566 tx_cmd->rate_n_flags = il4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
1567}
1568
1569static void il4965_tx_cmd_build_hwcrypto(struct il_priv *il,
1570 struct ieee80211_tx_info *info,
1571 struct il_tx_cmd *tx_cmd,
1572 struct sk_buff *skb_frag,
1573 int sta_id)
1574{
1575 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1576
1577 switch (keyconf->cipher) {
1578 case WLAN_CIPHER_SUITE_CCMP:
1579 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1580 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1581 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1582 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1583 D_TX("tx_cmd with AES hwcrypto\n");
1584 break;
1585
1586 case WLAN_CIPHER_SUITE_TKIP:
1587 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1588 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1589 D_TX("tx_cmd with tkip hwcrypto\n");
1590 break;
1591
1592 case WLAN_CIPHER_SUITE_WEP104:
1593 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1594 /* fall through */
1595 case WLAN_CIPHER_SUITE_WEP40:
1596 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
1597 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
1598
1599 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1600
1601 D_TX("Configuring packet for WEP encryption "
1602 "with key %d\n", keyconf->keyidx);
1603 break;
1604
1605 default:
1606 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1607 break;
1608 }
1609}
1610
1611/*
1612 * start REPLY_TX command process
1613 */
1614int il4965_tx_skb(struct il_priv *il, struct sk_buff *skb)
1615{
1616 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1617 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1618 struct ieee80211_sta *sta = info->control.sta;
1619 struct il_station_priv *sta_priv = NULL;
1620 struct il_tx_queue *txq;
1621 struct il_queue *q;
1622 struct il_device_cmd *out_cmd;
1623 struct il_cmd_meta *out_meta;
1624 struct il_tx_cmd *tx_cmd;
1625 struct il_rxon_context *ctx = &il->ctx;
1626 int txq_id;
1627 dma_addr_t phys_addr;
1628 dma_addr_t txcmd_phys;
1629 dma_addr_t scratch_phys;
1630 u16 len, firstlen, secondlen;
1631 u16 seq_number = 0;
1632 __le16 fc;
1633 u8 hdr_len;
1634 u8 sta_id;
1635 u8 wait_write_ptr = 0;
1636 u8 tid = 0;
1637 u8 *qc = NULL;
1638 unsigned long flags;
1639 bool is_agg = false;
1640
1641 if (info->control.vif)
1642 ctx = il_rxon_ctx_from_vif(info->control.vif);
1643
1644 spin_lock_irqsave(&il->lock, flags);
1645 if (il_is_rfkill(il)) {
1646 D_DROP("Dropping - RF KILL\n");
1647 goto drop_unlock;
1648 }
1649
1650 fc = hdr->frame_control;
1651
1652#ifdef CONFIG_IWLEGACY_DEBUG
1653 if (ieee80211_is_auth(fc))
1654 D_TX("Sending AUTH frame\n");
1655 else if (ieee80211_is_assoc_req(fc))
1656 D_TX("Sending ASSOC frame\n");
1657 else if (ieee80211_is_reassoc_req(fc))
1658 D_TX("Sending REASSOC frame\n");
1659#endif
1660
1661 hdr_len = ieee80211_hdrlen(fc);
1662
1663 /* For management frames use broadcast id to do not break aggregation */
1664 if (!ieee80211_is_data(fc))
1665 sta_id = ctx->bcast_sta_id;
1666 else {
1667 /* Find idx into station table for destination station */
1668 sta_id = il_sta_id_or_broadcast(il, ctx, info->control.sta);
1669
1670 if (sta_id == IL_INVALID_STATION) {
1671 D_DROP("Dropping - INVALID STATION: %pM\n",
1672 hdr->addr1);
1673 goto drop_unlock;
1674 }
1675 }
1676
1677 D_TX("station Id %d\n", sta_id);
1678
1679 if (sta)
1680 sta_priv = (void *)sta->drv_priv;
1681
1682 if (sta_priv && sta_priv->asleep &&
1683 (info->flags & IEEE80211_TX_CTL_POLL_RESPONSE)) {
1684 /*
1685 * This sends an asynchronous command to the device,
1686 * but we can rely on it being processed before the
1687 * next frame is processed -- and the next frame to
1688 * this station is the one that will consume this
1689 * counter.
1690 * For now set the counter to just 1 since we do not
1691 * support uAPSD yet.
1692 */
1693 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1694 }
1695
1696 /*
1697 * Send this frame after DTIM -- there's a special queue
1698 * reserved for this for contexts that support AP mode.
1699 */
1700 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1701 txq_id = ctx->mcast_queue;
1702 /*
1703 * The microcode will clear the more data
1704 * bit in the last frame it transmits.
1705 */
1706 hdr->frame_control |=
1707 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1708 } else
1709 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
1710
1711 /* irqs already disabled/saved above when locking il->lock */
1712 spin_lock(&il->sta_lock);
1713
1714 if (ieee80211_is_data_qos(fc)) {
1715 qc = ieee80211_get_qos_ctl(hdr);
1716 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1717 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1718 spin_unlock(&il->sta_lock);
1719 goto drop_unlock;
1720 }
1721 seq_number = il->stations[sta_id].tid[tid].seq_number;
1722 seq_number &= IEEE80211_SCTL_SEQ;
1723 hdr->seq_ctrl = hdr->seq_ctrl &
1724 cpu_to_le16(IEEE80211_SCTL_FRAG);
1725 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1726 seq_number += 0x10;
1727 /* aggregation is on for this <sta,tid> */
1728 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1729 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1730 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1731 is_agg = true;
1732 }
1733 }
1734
1735 txq = &il->txq[txq_id];
1736 q = &txq->q;
1737
1738 if (unlikely(il_queue_space(q) < q->high_mark)) {
1739 spin_unlock(&il->sta_lock);
1740 goto drop_unlock;
1741 }
1742
1743 if (ieee80211_is_data_qos(fc)) {
1744 il->stations[sta_id].tid[tid].tfds_in_queue++;
1745 if (!ieee80211_has_morefrags(fc))
1746 il->stations[sta_id].tid[tid].seq_number = seq_number;
1747 }
1748
1749 spin_unlock(&il->sta_lock);
1750
1751 /* Set up driver data for this TFD */
1752 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info));
1753 txq->txb[q->write_ptr].skb = skb;
1754 txq->txb[q->write_ptr].ctx = ctx;
1755
1756 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1757 out_cmd = txq->cmd[q->write_ptr];
1758 out_meta = &txq->meta[q->write_ptr];
1759 tx_cmd = &out_cmd->cmd.tx;
1760 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1761 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1762
1763 /*
1764 * Set up the Tx-command (not MAC!) header.
1765 * Store the chosen Tx queue and TFD idx within the sequence field;
1766 * after Tx, uCode's Tx response will return this value so driver can
1767 * locate the frame within the tx queue and do post-tx processing.
1768 */
1769 out_cmd->hdr.cmd = REPLY_TX;
1770 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1771 IDX_TO_SEQ(q->write_ptr)));
1772
1773 /* Copy MAC header from skb into command buffer */
1774 memcpy(tx_cmd->hdr, hdr, hdr_len);
1775
1776
1777 /* Total # bytes to be transmitted */
1778 len = (u16)skb->len;
1779 tx_cmd->len = cpu_to_le16(len);
1780
1781 if (info->control.hw_key)
1782 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1783
1784 /* TODO need this for burst mode later on */
1785 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1786 il_dbg_log_tx_data_frame(il, len, hdr);
1787
1788 il4965_tx_cmd_build_rate(il, tx_cmd, info, fc);
1789
1790 il_update_stats(il, true, fc, len);
1791 /*
1792 * Use the first empty entry in this queue's command buffer array
1793 * to contain the Tx command and MAC header concatenated together
1794 * (payload data will be in another buffer).
1795 * Size of this varies, due to varying MAC header length.
1796 * If end is not dword aligned, we'll have 2 extra bytes at the end
1797 * of the MAC header (device reads on dword boundaries).
1798 * We'll tell device about this padding later.
1799 */
1800 len = sizeof(struct il_tx_cmd) +
1801 sizeof(struct il_cmd_header) + hdr_len;
1802 firstlen = (len + 3) & ~3;
1803
1804 /* Tell NIC about any 2-byte padding after MAC header */
1805 if (firstlen != len)
1806 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1807
1808 /* Physical address of this Tx command's header (not MAC header!),
1809 * within command buffer array. */
1810 txcmd_phys = pci_map_single(il->pci_dev,
1811 &out_cmd->hdr, firstlen,
1812 PCI_DMA_BIDIRECTIONAL);
1813 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1814 dma_unmap_len_set(out_meta, len, firstlen);
1815 /* Add buffer containing Tx command and MAC(!) header to TFD's
1816 * first entry */
1817 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
1818 txcmd_phys, firstlen, 1, 0);
1819
1820 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1821 txq->need_update = 1;
1822 } else {
1823 wait_write_ptr = 1;
1824 txq->need_update = 0;
1825 }
1826
1827 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1828 * if any (802.11 null frames have no payload). */
1829 secondlen = skb->len - hdr_len;
1830 if (secondlen > 0) {
1831 phys_addr = pci_map_single(il->pci_dev, skb->data + hdr_len,
1832 secondlen, PCI_DMA_TODEVICE);
1833 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
1834 phys_addr, secondlen,
1835 0, 0);
1836 }
1837
1838 scratch_phys = txcmd_phys + sizeof(struct il_cmd_header) +
1839 offsetof(struct il_tx_cmd, scratch);
1840
1841 /* take back ownership of DMA buffer to enable update */
1842 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys,
1843 firstlen, PCI_DMA_BIDIRECTIONAL);
1844 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1845 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1846
1847 D_TX("sequence nr = 0X%x\n",
1848 le16_to_cpu(out_cmd->hdr.sequence));
1849 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1850 il_print_hex_dump(il, IL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1851 il_print_hex_dump(il, IL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1852
1853 /* Set up entry for this TFD in Tx byte-count array */
1854 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1855 il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq,
1856 le16_to_cpu(tx_cmd->len));
1857
1858 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys,
1859 firstlen, PCI_DMA_BIDIRECTIONAL);
1860
1861 /* Tell device the write idx *just past* this latest filled TFD */
1862 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1863 il_txq_update_write_ptr(il, txq);
1864 spin_unlock_irqrestore(&il->lock, flags);
1865
1866 /*
1867 * At this point the frame is "transmitted" successfully
1868 * and we will get a TX status notification eventually,
1869 * regardless of the value of ret. "ret" only indicates
1870 * whether or not we should update the write pointer.
1871 */
1872
1873 /*
1874 * Avoid atomic ops if it isn't an associated client.
1875 * Also, if this is a packet for aggregation, don't
1876 * increase the counter because the ucode will stop
1877 * aggregation queues when their respective station
1878 * goes to sleep.
1879 */
1880 if (sta_priv && sta_priv->client && !is_agg)
1881 atomic_inc(&sta_priv->pending_frames);
1882
1883 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1884 if (wait_write_ptr) {
1885 spin_lock_irqsave(&il->lock, flags);
1886 txq->need_update = 1;
1887 il_txq_update_write_ptr(il, txq);
1888 spin_unlock_irqrestore(&il->lock, flags);
1889 } else {
1890 il_stop_queue(il, txq);
1891 }
1892 }
1893
1894 return 0;
1895
1896drop_unlock:
1897 spin_unlock_irqrestore(&il->lock, flags);
1898 return -1;
1899}
1900
1901static inline int il4965_alloc_dma_ptr(struct il_priv *il,
1902 struct il_dma_ptr *ptr, size_t size)
1903{
1904 ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma,
1905 GFP_KERNEL);
1906 if (!ptr->addr)
1907 return -ENOMEM;
1908 ptr->size = size;
1909 return 0;
1910}
1911
1912static inline void il4965_free_dma_ptr(struct il_priv *il,
1913 struct il_dma_ptr *ptr)
1914{
1915 if (unlikely(!ptr->addr))
1916 return;
1917
1918 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1919 memset(ptr, 0, sizeof(*ptr));
1920}
1921
1922/**
1923 * il4965_hw_txq_ctx_free - Free TXQ Context
1924 *
1925 * Destroy all TX DMA queues and structures
1926 */
1927void il4965_hw_txq_ctx_free(struct il_priv *il)
1928{
1929 int txq_id;
1930
1931 /* Tx queues */
1932 if (il->txq) {
1933 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1934 if (txq_id == il->cmd_queue)
1935 il_cmd_queue_free(il);
1936 else
1937 il_tx_queue_free(il, txq_id);
1938 }
1939 il4965_free_dma_ptr(il, &il->kw);
1940
1941 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1942
1943 /* free tx queue structure */
1944 il_txq_mem(il);
1945}
1946
1947/**
1948 * il4965_txq_ctx_alloc - allocate TX queue context
1949 * Allocate all Tx DMA structures and initialize them
1950 *
1951 * @param il
1952 * @return error code
1953 */
1954int il4965_txq_ctx_alloc(struct il_priv *il)
1955{
1956 int ret;
1957 int txq_id, slots_num;
1958 unsigned long flags;
1959
1960 /* Free all tx/cmd queues and keep-warm buffer */
1961 il4965_hw_txq_ctx_free(il);
1962
1963 ret = il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1964 il->hw_params.scd_bc_tbls_size);
1965 if (ret) {
1966 IL_ERR("Scheduler BC Table allocation failed\n");
1967 goto error_bc_tbls;
1968 }
1969 /* Alloc keep-warm buffer */
1970 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1971 if (ret) {
1972 IL_ERR("Keep Warm allocation failed\n");
1973 goto error_kw;
1974 }
1975
1976 /* allocate tx queue structure */
1977 ret = il_alloc_txq_mem(il);
1978 if (ret)
1979 goto error;
1980
1981 spin_lock_irqsave(&il->lock, flags);
1982
1983 /* Turn off all Tx DMA fifos */
1984 il4965_txq_set_sched(il, 0);
1985
1986 /* Tell NIC where to find the "keep warm" buffer */
1987 il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);
1988
1989 spin_unlock_irqrestore(&il->lock, flags);
1990
1991 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1992 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1993 slots_num = (txq_id == il->cmd_queue) ?
1994 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1995 ret = il_tx_queue_init(il,
1996 &il->txq[txq_id], slots_num,
1997 txq_id);
1998 if (ret) {
1999 IL_ERR("Tx %d queue init failed\n", txq_id);
2000 goto error;
2001 }
2002 }
2003
2004 return ret;
2005
2006 error:
2007 il4965_hw_txq_ctx_free(il);
2008 il4965_free_dma_ptr(il, &il->kw);
2009 error_kw:
2010 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
2011 error_bc_tbls:
2012 return ret;
2013}
2014
2015void il4965_txq_ctx_reset(struct il_priv *il)
2016{
2017 int txq_id, slots_num;
2018 unsigned long flags;
2019
2020 spin_lock_irqsave(&il->lock, flags);
2021
2022 /* Turn off all Tx DMA fifos */
2023 il4965_txq_set_sched(il, 0);
2024
2025 /* Tell NIC where to find the "keep warm" buffer */
2026 il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2027
2028 spin_unlock_irqrestore(&il->lock, flags);
2029
2030 /* Alloc and init all Tx queues, including the command queue (#4) */
2031 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2032 slots_num = txq_id == il->cmd_queue ?
2033 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
2034 il_tx_queue_reset(il, &il->txq[txq_id],
2035 slots_num, txq_id);
2036 }
2037}
2038
2039/**
2040 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2041 */
2042void il4965_txq_ctx_stop(struct il_priv *il)
2043{
2044 int ch, txq_id;
2045 unsigned long flags;
2046
2047 /* Turn off all Tx DMA fifos */
2048 spin_lock_irqsave(&il->lock, flags);
2049
2050 il4965_txq_set_sched(il, 0);
2051
2052 /* Stop each Tx DMA channel, and wait for it to be idle */
2053 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2054 il_wr(il,
2055 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2056 if (il_poll_bit(il, FH_TSSR_TX_STATUS_REG,
2057 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2058 1000))
2059 IL_ERR("Failing on timeout while stopping"
2060 " DMA channel %d [0x%08x]", ch,
2061 il_rd(il,
2062 FH_TSSR_TX_STATUS_REG));
2063 }
2064 spin_unlock_irqrestore(&il->lock, flags);
2065
2066 if (!il->txq)
2067 return;
2068
2069 /* Unmap DMA from host system and free skb's */
2070 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2071 if (txq_id == il->cmd_queue)
2072 il_cmd_queue_unmap(il);
2073 else
2074 il_tx_queue_unmap(il, txq_id);
2075}
2076
2077/*
2078 * Find first available (lowest unused) Tx Queue, mark it "active".
2079 * Called only when finding queue for aggregation.
2080 * Should never return anything < 7, because they should already
2081 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2082 */
2083static int il4965_txq_ctx_activate_free(struct il_priv *il)
2084{
2085 int txq_id;
2086
2087 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2088 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2089 return txq_id;
2090 return -1;
2091}
2092
2093/**
2094 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2095 */
2096static void il4965_tx_queue_stop_scheduler(struct il_priv *il,
2097 u16 txq_id)
2098{
2099 /* Simply stop the queue, but don't change any configuration;
2100 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
2101 il_wr_prph(il,
2102 IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2103 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
2104 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
2105}
2106
2107/**
2108 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2109 */
2110static int il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid,
2111 u16 txq_id)
2112{
2113 u32 tbl_dw_addr;
2114 u32 tbl_dw;
2115 u16 scd_q2ratid;
2116
2117 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2118
2119 tbl_dw_addr = il->scd_base_addr +
2120 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2121
2122 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2123
2124 if (txq_id & 0x1)
2125 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2126 else
2127 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2128
2129 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2130
2131 return 0;
2132}
2133
2134/**
2135 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2136 *
2137 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2138 * i.e. it must be one of the higher queues used for aggregation
2139 */
2140static int il4965_txq_agg_enable(struct il_priv *il, int txq_id,
2141 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
2142{
2143 unsigned long flags;
2144 u16 ra_tid;
2145 int ret;
2146
2147 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2148 (IL49_FIRST_AMPDU_QUEUE +
2149 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
2150 IL_WARN(
2151 "queue number out of range: %d, must be %d to %d\n",
2152 txq_id, IL49_FIRST_AMPDU_QUEUE,
2153 IL49_FIRST_AMPDU_QUEUE +
2154 il->cfg->base_params->num_of_ampdu_queues - 1);
2155 return -EINVAL;
2156 }
2157
2158 ra_tid = BUILD_RAxTID(sta_id, tid);
2159
2160 /* Modify device's station table to Tx this TID */
2161 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2162 if (ret)
2163 return ret;
2164
2165 spin_lock_irqsave(&il->lock, flags);
2166
2167 /* Stop this Tx queue before configuring it */
2168 il4965_tx_queue_stop_scheduler(il, txq_id);
2169
2170 /* Map receiver-address / traffic-ID to this queue */
2171 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2172
2173 /* Set this queue as a chain-building queue */
2174 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2175
2176 /* Place first TFD at idx corresponding to start sequence number.
2177 * Assumes that ssn_idx is valid (!= 0xFFF) */
2178 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2179 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2180 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2181
2182 /* Set up Tx win size and frame limit for this queue */
2183 il_write_targ_mem(il,
2184 il->scd_base_addr + IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2185 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
2186 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
2187
2188 il_write_targ_mem(il, il->scd_base_addr +
2189 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2190 (SCD_FRAME_LIMIT << IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
2191 & IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
2192
2193 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2194
2195 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2196 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2197
2198 spin_unlock_irqrestore(&il->lock, flags);
2199
2200 return 0;
2201}
2202
2203
2204int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2205 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
2206{
2207 int sta_id;
2208 int tx_fifo;
2209 int txq_id;
2210 int ret;
2211 unsigned long flags;
2212 struct il_tid_data *tid_data;
2213
2214 tx_fifo = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid);
2215 if (unlikely(tx_fifo < 0))
2216 return tx_fifo;
2217
2218 IL_WARN("%s on ra = %pM tid = %d\n",
2219 __func__, sta->addr, tid);
2220
2221 sta_id = il_sta_id(sta);
2222 if (sta_id == IL_INVALID_STATION) {
2223 IL_ERR("Start AGG on invalid station\n");
2224 return -ENXIO;
2225 }
2226 if (unlikely(tid >= MAX_TID_COUNT))
2227 return -EINVAL;
2228
2229 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2230 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2231 return -ENXIO;
2232 }
2233
2234 txq_id = il4965_txq_ctx_activate_free(il);
2235 if (txq_id == -1) {
2236 IL_ERR("No free aggregation queue available\n");
2237 return -ENXIO;
2238 }
2239
2240 spin_lock_irqsave(&il->sta_lock, flags);
2241 tid_data = &il->stations[sta_id].tid[tid];
2242 *ssn = SEQ_TO_SN(tid_data->seq_number);
2243 tid_data->agg.txq_id = txq_id;
2244 il_set_swq_id(&il->txq[txq_id],
2245 il4965_get_ac_from_tid(tid), txq_id);
2246 spin_unlock_irqrestore(&il->sta_lock, flags);
2247
2248 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo,
2249 sta_id, tid, *ssn);
2250 if (ret)
2251 return ret;
2252
2253 spin_lock_irqsave(&il->sta_lock, flags);
2254 tid_data = &il->stations[sta_id].tid[tid];
2255 if (tid_data->tfds_in_queue == 0) {
2256 D_HT("HW queue is empty\n");
2257 tid_data->agg.state = IL_AGG_ON;
2258 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2259 } else {
2260 D_HT(
2261 "HW queue is NOT empty: %d packets in HW queue\n",
2262 tid_data->tfds_in_queue);
2263 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2264 }
2265 spin_unlock_irqrestore(&il->sta_lock, flags);
2266 return ret;
2267}
2268
2269/**
2270 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2271 * il->lock must be held by the caller
2272 */
2273static int il4965_txq_agg_disable(struct il_priv *il, u16 txq_id,
2274 u16 ssn_idx, u8 tx_fifo)
2275{
2276 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2277 (IL49_FIRST_AMPDU_QUEUE +
2278 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
2279 IL_WARN(
2280 "queue number out of range: %d, must be %d to %d\n",
2281 txq_id, IL49_FIRST_AMPDU_QUEUE,
2282 IL49_FIRST_AMPDU_QUEUE +
2283 il->cfg->base_params->num_of_ampdu_queues - 1);
2284 return -EINVAL;
2285 }
2286
2287 il4965_tx_queue_stop_scheduler(il, txq_id);
2288
2289 il_clear_bits_prph(il,
2290 IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2291
2292 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2293 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2294 /* supposes that ssn_idx is valid (!= 0xFFF) */
2295 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2296
2297 il_clear_bits_prph(il,
2298 IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2299 il_txq_ctx_deactivate(il, txq_id);
2300 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2301
2302 return 0;
2303}
2304
2305int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2306 struct ieee80211_sta *sta, u16 tid)
2307{
2308 int tx_fifo_id, txq_id, sta_id, ssn;
2309 struct il_tid_data *tid_data;
2310 int write_ptr, read_ptr;
2311 unsigned long flags;
2312
2313 tx_fifo_id = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid);
2314 if (unlikely(tx_fifo_id < 0))
2315 return tx_fifo_id;
2316
2317 sta_id = il_sta_id(sta);
2318
2319 if (sta_id == IL_INVALID_STATION) {
2320 IL_ERR("Invalid station for AGG tid %d\n", tid);
2321 return -ENXIO;
2322 }
2323
2324 spin_lock_irqsave(&il->sta_lock, flags);
2325
2326 tid_data = &il->stations[sta_id].tid[tid];
2327 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2328 txq_id = tid_data->agg.txq_id;
2329
2330 switch (il->stations[sta_id].tid[tid].agg.state) {
2331 case IL_EMPTYING_HW_QUEUE_ADDBA:
2332 /*
2333 * This can happen if the peer stops aggregation
2334 * again before we've had a chance to drain the
2335 * queue we selected previously, i.e. before the
2336 * session was really started completely.
2337 */
2338 D_HT("AGG stop before setup done\n");
2339 goto turn_off;
2340 case IL_AGG_ON:
2341 break;
2342 default:
2343 IL_WARN("Stopping AGG while state not ON or starting\n");
2344 }
2345
2346 write_ptr = il->txq[txq_id].q.write_ptr;
2347 read_ptr = il->txq[txq_id].q.read_ptr;
2348
2349 /* The queue is not empty */
2350 if (write_ptr != read_ptr) {
2351 D_HT("Stopping a non empty AGG HW QUEUE\n");
2352 il->stations[sta_id].tid[tid].agg.state =
2353 IL_EMPTYING_HW_QUEUE_DELBA;
2354 spin_unlock_irqrestore(&il->sta_lock, flags);
2355 return 0;
2356 }
2357
2358 D_HT("HW queue is empty\n");
2359 turn_off:
2360 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2361
2362 /* do not restore/save irqs */
2363 spin_unlock(&il->sta_lock);
2364 spin_lock(&il->lock);
2365
2366 /*
2367 * the only reason this call can fail is queue number out of range,
2368 * which can happen if uCode is reloaded and all the station
2369 * information are lost. if it is outside the range, there is no need
2370 * to deactivate the uCode queue, just return "success" to allow
2371 * mac80211 to clean up it own data.
2372 */
2373 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2374 spin_unlock_irqrestore(&il->lock, flags);
2375
2376 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2377
2378 return 0;
2379}
2380
2381int il4965_txq_check_empty(struct il_priv *il,
2382 int sta_id, u8 tid, int txq_id)
2383{
2384 struct il_queue *q = &il->txq[txq_id].q;
2385 u8 *addr = il->stations[sta_id].sta.sta.addr;
2386 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
2387 struct il_rxon_context *ctx;
2388
2389 ctx = &il->ctx;
2390
2391 lockdep_assert_held(&il->sta_lock);
2392
2393 switch (il->stations[sta_id].tid[tid].agg.state) {
2394 case IL_EMPTYING_HW_QUEUE_DELBA:
2395 /* We are reclaiming the last packet of the */
2396 /* aggregated HW queue */
2397 if (txq_id == tid_data->agg.txq_id &&
2398 q->read_ptr == q->write_ptr) {
2399 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
2400 int tx_fifo = il4965_get_fifo_from_tid(ctx, tid);
2401 D_HT(
2402 "HW queue empty: continue DELBA flow\n");
2403 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2404 tid_data->agg.state = IL_AGG_OFF;
2405 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
2406 }
2407 break;
2408 case IL_EMPTYING_HW_QUEUE_ADDBA:
2409 /* We are reclaiming the last packet of the queue */
2410 if (tid_data->tfds_in_queue == 0) {
2411 D_HT(
2412 "HW queue empty: continue ADDBA flow\n");
2413 tid_data->agg.state = IL_AGG_ON;
2414 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
2415 }
2416 break;
2417 }
2418
2419 return 0;
2420}
2421
2422static void il4965_non_agg_tx_status(struct il_priv *il,
2423 struct il_rxon_context *ctx,
2424 const u8 *addr1)
2425{
2426 struct ieee80211_sta *sta;
2427 struct il_station_priv *sta_priv;
2428
2429 rcu_read_lock();
2430 sta = ieee80211_find_sta(ctx->vif, addr1);
2431 if (sta) {
2432 sta_priv = (void *)sta->drv_priv;
2433 /* avoid atomic ops if this isn't a client */
2434 if (sta_priv->client &&
2435 atomic_dec_return(&sta_priv->pending_frames) == 0)
2436 ieee80211_sta_block_awake(il->hw, sta, false);
2437 }
2438 rcu_read_unlock();
2439}
2440
2441static void
2442il4965_tx_status(struct il_priv *il, struct il_tx_info *tx_info,
2443 bool is_agg)
2444{
2445 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
2446
2447 if (!is_agg)
2448 il4965_non_agg_tx_status(il, tx_info->ctx, hdr->addr1);
2449
2450 ieee80211_tx_status_irqsafe(il->hw, tx_info->skb);
2451}
2452
2453int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2454{
2455 struct il_tx_queue *txq = &il->txq[txq_id];
2456 struct il_queue *q = &txq->q;
2457 struct il_tx_info *tx_info;
2458 int nfreed = 0;
2459 struct ieee80211_hdr *hdr;
2460
2461 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2462 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
2463 "is out of range [0-%d] %d %d.\n", txq_id,
2464 idx, q->n_bd, q->write_ptr, q->read_ptr);
2465 return 0;
2466 }
2467
2468 for (idx = il_queue_inc_wrap(idx, q->n_bd);
2469 q->read_ptr != idx;
2470 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2471
2472 tx_info = &txq->txb[txq->q.read_ptr];
2473
2474 if (WARN_ON_ONCE(tx_info->skb == NULL))
2475 continue;
2476
2477 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
2478 if (ieee80211_is_data_qos(hdr->frame_control))
2479 nfreed++;
2480
2481 il4965_tx_status(il, tx_info,
2482 txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2483 tx_info->skb = NULL;
2484
2485 il->cfg->ops->lib->txq_free_tfd(il, txq);
2486 }
2487 return nfreed;
2488}
2489
2490/**
2491 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2492 *
2493 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2494 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2495 */
2496static int il4965_tx_status_reply_compressed_ba(struct il_priv *il,
2497 struct il_ht_agg *agg,
2498 struct il_compressed_ba_resp *ba_resp)
2499
2500{
2501 int i, sh, ack;
2502 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2503 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2504 int successes = 0;
2505 struct ieee80211_tx_info *info;
2506 u64 bitmap, sent_bitmap;
2507
2508 if (unlikely(!agg->wait_for_ba)) {
2509 if (unlikely(ba_resp->bitmap))
2510 IL_ERR("Received BA when not expected\n");
2511 return -EINVAL;
2512 }
2513
2514 /* Mark that the expected block-ack response arrived */
2515 agg->wait_for_ba = 0;
2516 D_TX_REPLY("BA %d %d\n", agg->start_idx,
2517 ba_resp->seq_ctl);
2518
2519 /* Calculate shift to align block-ack bits with our Tx win bits */
2520 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
2521 if (sh < 0) /* tbw something is wrong with indices */
2522 sh += 0x100;
2523
2524 if (agg->frame_count > (64 - sh)) {
2525 D_TX_REPLY("more frames than bitmap size");
2526 return -1;
2527 }
2528
2529 /* don't use 64-bit values for now */
2530 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2531
2532 /* check for success or failure according to the
2533 * transmitted bitmap and block-ack bitmap */
2534 sent_bitmap = bitmap & agg->bitmap;
2535
2536 /* For each frame attempted in aggregation,
2537 * update driver's record of tx frame's status. */
2538 i = 0;
2539 while (sent_bitmap) {
2540 ack = sent_bitmap & 1ULL;
2541 successes += ack;
2542 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
2543 ack ? "ACK" : "NACK", i,
2544 (agg->start_idx + i) & 0xff,
2545 agg->start_idx + i);
2546 sent_bitmap >>= 1;
2547 ++i;
2548 }
2549
2550 D_TX_REPLY("Bitmap %llx\n",
2551 (unsigned long long)bitmap);
2552
2553 info = IEEE80211_SKB_CB(il->txq[scd_flow].txb[agg->start_idx].skb);
2554 memset(&info->status, 0, sizeof(info->status));
2555 info->flags |= IEEE80211_TX_STAT_ACK;
2556 info->flags |= IEEE80211_TX_STAT_AMPDU;
2557 info->status.ampdu_ack_len = successes;
2558 info->status.ampdu_len = agg->frame_count;
2559 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2560
2561 return 0;
2562}
2563
2564/**
2565 * translate ucode response to mac80211 tx status control values
2566 */
2567void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2568 struct ieee80211_tx_info *info)
2569{
2570 struct ieee80211_tx_rate *r = &info->control.rates[0];
2571
2572 info->antenna_sel_tx =
2573 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
2574 if (rate_n_flags & RATE_MCS_HT_MSK)
2575 r->flags |= IEEE80211_TX_RC_MCS;
2576 if (rate_n_flags & RATE_MCS_GF_MSK)
2577 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2578 if (rate_n_flags & RATE_MCS_HT40_MSK)
2579 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2580 if (rate_n_flags & RATE_MCS_DUP_MSK)
2581 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2582 if (rate_n_flags & RATE_MCS_SGI_MSK)
2583 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2584 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2585}
2586
2587/**
2588 * il4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
2589 *
2590 * Handles block-acknowledge notification from device, which reports success
2591 * of frames sent via aggregation.
2592 */
2593void il4965_rx_reply_compressed_ba(struct il_priv *il,
2594 struct il_rx_buf *rxb)
2595{
2596 struct il_rx_pkt *pkt = rxb_addr(rxb);
2597 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2598 struct il_tx_queue *txq = NULL;
2599 struct il_ht_agg *agg;
2600 int idx;
2601 int sta_id;
2602 int tid;
2603 unsigned long flags;
2604
2605 /* "flow" corresponds to Tx queue */
2606 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2607
2608 /* "ssn" is start of block-ack Tx win, corresponds to idx
2609 * (in Tx queue's circular buffer) of first TFD/frame in win */
2610 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2611
2612 if (scd_flow >= il->hw_params.max_txq_num) {
2613 IL_ERR(
2614 "BUG_ON scd_flow is bigger than number of queues\n");
2615 return;
2616 }
2617
2618 txq = &il->txq[scd_flow];
2619 sta_id = ba_resp->sta_id;
2620 tid = ba_resp->tid;
2621 agg = &il->stations[sta_id].tid[tid].agg;
2622 if (unlikely(agg->txq_id != scd_flow)) {
2623 /*
2624 * FIXME: this is a uCode bug which need to be addressed,
2625 * log the information and return for now!
2626 * since it is possible happen very often and in order
2627 * not to fill the syslog, don't enable the logging by default
2628 */
2629 D_TX_REPLY(
2630 "BA scd_flow %d does not match txq_id %d\n",
2631 scd_flow, agg->txq_id);
2632 return;
2633 }
2634
2635 /* Find idx just before block-ack win */
2636 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2637
2638 spin_lock_irqsave(&il->sta_lock, flags);
2639
2640 D_TX_REPLY("REPLY_COMPRESSED_BA [%d] Received from %pM, "
2641 "sta_id = %d\n",
2642 agg->wait_for_ba,
2643 (u8 *) &ba_resp->sta_addr_lo32,
2644 ba_resp->sta_id);
2645 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx,"
2646 "scd_flow = "
2647 "%d, scd_ssn = %d\n",
2648 ba_resp->tid,
2649 ba_resp->seq_ctl,
2650 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2651 ba_resp->scd_flow,
2652 ba_resp->scd_ssn);
2653 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n",
2654 agg->start_idx,
2655 (unsigned long long)agg->bitmap);
2656
2657 /* Update driver's record of ACK vs. not for each frame in win */
2658 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2659
2660 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2661 * block-ack win (we assume that they've been successfully
2662 * transmitted ... if not, it's too late anyway). */
2663 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2664 /* calculate mac80211 ampdu sw queue to wake */
2665 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2666 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2667
2668 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2669 il->mac80211_registered &&
2670 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2671 il_wake_queue(il, txq);
2672
2673 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2674 }
2675
2676 spin_unlock_irqrestore(&il->sta_lock, flags);
2677}
2678
2679#ifdef CONFIG_IWLEGACY_DEBUG
2680const char *il4965_get_tx_fail_reason(u32 status)
2681{
2682#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2683#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2684
2685 switch (status & TX_STATUS_MSK) {
2686 case TX_STATUS_SUCCESS:
2687 return "SUCCESS";
2688 TX_STATUS_POSTPONE(DELAY);
2689 TX_STATUS_POSTPONE(FEW_BYTES);
2690 TX_STATUS_POSTPONE(QUIET_PERIOD);
2691 TX_STATUS_POSTPONE(CALC_TTAK);
2692 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2693 TX_STATUS_FAIL(SHORT_LIMIT);
2694 TX_STATUS_FAIL(LONG_LIMIT);
2695 TX_STATUS_FAIL(FIFO_UNDERRUN);
2696 TX_STATUS_FAIL(DRAIN_FLOW);
2697 TX_STATUS_FAIL(RFKILL_FLUSH);
2698 TX_STATUS_FAIL(LIFE_EXPIRE);
2699 TX_STATUS_FAIL(DEST_PS);
2700 TX_STATUS_FAIL(HOST_ABORTED);
2701 TX_STATUS_FAIL(BT_RETRY);
2702 TX_STATUS_FAIL(STA_INVALID);
2703 TX_STATUS_FAIL(FRAG_DROPPED);
2704 TX_STATUS_FAIL(TID_DISABLE);
2705 TX_STATUS_FAIL(FIFO_FLUSHED);
2706 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
2707 TX_STATUS_FAIL(PASSIVE_NO_RX);
2708 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
2709 }
2710
2711 return "UNKNOWN";
2712
2713#undef TX_STATUS_FAIL
2714#undef TX_STATUS_POSTPONE
2715}
2716#endif /* CONFIG_IWLEGACY_DEBUG */
2717
eb3cdfb7
SG		 2718static struct il_link_quality_cmd *
2719il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
2720{
2721 int i, r;
2722 struct il_link_quality_cmd *link_cmd;
2723 u32 rate_flags = 0;
2724 __le32 rate_n_flags;
2725
2726 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
2727 if (!link_cmd) {
2728 IL_ERR("Unable to allocate memory for LQ cmd.\n");
2729 return NULL;
2730 }
2731 /* Set up the rate scaling to start at selected rate, fall back
2732 * all the way down to 1M in IEEE order, and then spin on 1M */
2733 if (il->band == IEEE80211_BAND_5GHZ)
2734 r = RATE_6M_IDX;
2735 else
2736 r = RATE_1M_IDX;
2737
2738 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
2739 rate_flags |= RATE_MCS_CCK_MSK;
2740
2741 rate_flags |= il4965_first_antenna(il->hw_params.valid_tx_ant) <<
2742 RATE_MCS_ANT_POS;
2743 rate_n_flags = il4965_hw_set_rate_n_flags(il_rates[r].plcp,
2744 rate_flags);
2745 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
2746 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
2747
2748 link_cmd->general_params.single_stream_ant_msk =
2749 il4965_first_antenna(il->hw_params.valid_tx_ant);
2750
2751 link_cmd->general_params.dual_stream_ant_msk =
2752 il->hw_params.valid_tx_ant &
2753 ~il4965_first_antenna(il->hw_params.valid_tx_ant);
2754 if (!link_cmd->general_params.dual_stream_ant_msk) {
2755 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
2756 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
2757 link_cmd->general_params.dual_stream_ant_msk =
2758 il->hw_params.valid_tx_ant;
2759 }
2760
2761 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
2762 link_cmd->agg_params.agg_time_limit =
2763 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
2764
2765 link_cmd->sta_id = sta_id;
2766
2767 return link_cmd;
2768}
2769
2770/*
2771 * il4965_add_bssid_station - Add the special IBSS BSSID station
2772 *
2773 * Function sleeps.
2774 */
2775int
2776il4965_add_bssid_station(struct il_priv *il, struct il_rxon_context *ctx,
2777 const u8 *addr, u8 *sta_id_r)
2778{
2779 int ret;
2780 u8 sta_id;
2781 struct il_link_quality_cmd *link_cmd;
2782 unsigned long flags;
2783
2784 if (sta_id_r)
2785 *sta_id_r = IL_INVALID_STATION;
2786
2787 ret = il_add_station_common(il, ctx, addr, 0, NULL, &sta_id);
2788 if (ret) {
2789 IL_ERR("Unable to add station %pM\n", addr);
2790 return ret;
2791 }
2792
2793 if (sta_id_r)
2794 *sta_id_r = sta_id;
2795
2796 spin_lock_irqsave(&il->sta_lock, flags);
2797 il->stations[sta_id].used |= IL_STA_LOCAL;
2798 spin_unlock_irqrestore(&il->sta_lock, flags);
2799
2800 /* Set up default rate scaling table in device's station table */
2801 link_cmd = il4965_sta_alloc_lq(il, sta_id);
2802 if (!link_cmd) {
2803 IL_ERR(
2804 "Unable to initialize rate scaling for station %pM.\n",
2805 addr);
2806 return -ENOMEM;
2807 }
2808
2809 ret = il_send_lq_cmd(il, ctx, link_cmd, CMD_SYNC, true);
2810 if (ret)
2811 IL_ERR("Link quality command failed (%d)\n", ret);
2812
2813 spin_lock_irqsave(&il->sta_lock, flags);
2814 il->stations[sta_id].lq = link_cmd;
2815 spin_unlock_irqrestore(&il->sta_lock, flags);
2816
2817 return 0;
2818}
2819
2820static int il4965_static_wepkey_cmd(struct il_priv *il,
2821 struct il_rxon_context *ctx,
2822 bool send_if_empty)
2823{
2824 int i, not_empty = 0;
2825 u8 buff[sizeof(struct il_wep_cmd) +
2826 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
2827 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
2828 size_t cmd_size = sizeof(struct il_wep_cmd);
2829 struct il_host_cmd cmd = {
2830 .id = ctx->wep_key_cmd,
2831 .data = wep_cmd,
2832 .flags = CMD_SYNC,
2833 };
2834
2835 might_sleep();
2836
2837 memset(wep_cmd, 0, cmd_size +
2838 (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
2839
2840 for (i = 0; i < WEP_KEYS_MAX ; i++) {
2841 wep_cmd->key[i].key_idx = i;
2842 if (ctx->wep_keys[i].key_size) {
2843 wep_cmd->key[i].key_offset = i;
2844 not_empty = 1;
2845 } else {
2846 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
2847 }
2848
2849 wep_cmd->key[i].key_size = ctx->wep_keys[i].key_size;
2850 memcpy(&wep_cmd->key[i].key[3], ctx->wep_keys[i].key,
2851 ctx->wep_keys[i].key_size);
2852 }
2853
2854 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
2855 wep_cmd->num_keys = WEP_KEYS_MAX;
2856
2857 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
2858
2859 cmd.len = cmd_size;
2860
2861 if (not_empty || send_if_empty)
2862 return il_send_cmd(il, &cmd);
2863 else
2864 return 0;
2865}
2866
2867int il4965_restore_default_wep_keys(struct il_priv *il,
2868 struct il_rxon_context *ctx)
2869{
2870 lockdep_assert_held(&il->mutex);
2871
2872 return il4965_static_wepkey_cmd(il, ctx, false);
2873}
2874
2875int il4965_remove_default_wep_key(struct il_priv *il,
2876 struct il_rxon_context *ctx,
2877 struct ieee80211_key_conf *keyconf)
2878{
2879 int ret;
2880
2881 lockdep_assert_held(&il->mutex);
2882
2883 D_WEP("Removing default WEP key: idx=%d\n",
2884 keyconf->keyidx);
2885
2886 memset(&ctx->wep_keys[keyconf->keyidx], 0, sizeof(ctx->wep_keys[0]));
2887 if (il_is_rfkill(il)) {
2888 D_WEP(
2889 "Not sending REPLY_WEPKEY command due to RFKILL.\n");
2890 /* but keys in device are clear anyway so return success */
2891 return 0;
2892 }
2893 ret = il4965_static_wepkey_cmd(il, ctx, 1);
2894 D_WEP("Remove default WEP key: idx=%d ret=%d\n",
2895 keyconf->keyidx, ret);
2896
2897 return ret;
2898}
2899
2900int il4965_set_default_wep_key(struct il_priv *il,
2901 struct il_rxon_context *ctx,
2902 struct ieee80211_key_conf *keyconf)
2903{
2904 int ret;
2905
2906 lockdep_assert_held(&il->mutex);
2907
2908 if (keyconf->keylen != WEP_KEY_LEN_128 &&
2909 keyconf->keylen != WEP_KEY_LEN_64) {
2910 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
2911 return -EINVAL;
2912 }
2913
2914 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2915 keyconf->hw_key_idx = HW_KEY_DEFAULT;
2916 il->stations[ctx->ap_sta_id].keyinfo.cipher = keyconf->cipher;
2917
2918 ctx->wep_keys[keyconf->keyidx].key_size = keyconf->keylen;
2919 memcpy(&ctx->wep_keys[keyconf->keyidx].key, &keyconf->key,
2920 keyconf->keylen);
2921
2922 ret = il4965_static_wepkey_cmd(il, ctx, false);
2923 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n",
2924 keyconf->keylen, keyconf->keyidx, ret);
2925
2926 return ret;
2927}
2928
2929static int il4965_set_wep_dynamic_key_info(struct il_priv *il,
2930 struct il_rxon_context *ctx,
2931 struct ieee80211_key_conf *keyconf,
2932 u8 sta_id)
2933{
2934 unsigned long flags;
2935 __le16 key_flags = 0;
2936 struct il_addsta_cmd sta_cmd;
2937
2938 lockdep_assert_held(&il->mutex);
2939
2940 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2941
2942 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
2943 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2944 key_flags &= ~STA_KEY_FLG_INVALID;
2945
2946 if (keyconf->keylen == WEP_KEY_LEN_128)
2947 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
2948
2949 if (sta_id == ctx->bcast_sta_id)
2950 key_flags |= STA_KEY_MULTICAST_MSK;
2951
2952 spin_lock_irqsave(&il->sta_lock, flags);
2953
2954 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
2955 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
2956 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
2957
2958 memcpy(il->stations[sta_id].keyinfo.key,
2959 keyconf->key, keyconf->keylen);
2960
2961 memcpy(&il->stations[sta_id].sta.key.key[3],
2962 keyconf->key, keyconf->keylen);
2963
2964 if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
2965 == STA_KEY_FLG_NO_ENC)
2966 il->stations[sta_id].sta.key.key_offset =
2967 il_get_free_ucode_key_idx(il);
2968 /* else, we are overriding an existing key => no need to allocated room
2969 * in uCode. */
2970
2971 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
2972 "no space for a new key");
2973
2974 il->stations[sta_id].sta.key.key_flags = key_flags;
2975 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
2976 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2977
2978 memcpy(&sta_cmd, &il->stations[sta_id].sta,
2979 sizeof(struct il_addsta_cmd));
2980 spin_unlock_irqrestore(&il->sta_lock, flags);
2981
2982 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2983}
2984
2985static int il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
2986 struct il_rxon_context *ctx,
2987 struct ieee80211_key_conf *keyconf,
2988 u8 sta_id)
2989{
2990 unsigned long flags;
2991 __le16 key_flags = 0;
2992 struct il_addsta_cmd sta_cmd;
2993
2994 lockdep_assert_held(&il->mutex);
2995
2996 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
2997 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2998 key_flags &= ~STA_KEY_FLG_INVALID;
2999
3000 if (sta_id == ctx->bcast_sta_id)
3001 key_flags |= STA_KEY_MULTICAST_MSK;
3002
3003 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3004
3005 spin_lock_irqsave(&il->sta_lock, flags);
3006 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3007 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3008
3009 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key,
3010 keyconf->keylen);
3011
3012 memcpy(il->stations[sta_id].sta.key.key, keyconf->key,
3013 keyconf->keylen);
3014
3015 if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
3016 == STA_KEY_FLG_NO_ENC)
3017 il->stations[sta_id].sta.key.key_offset =
3018 il_get_free_ucode_key_idx(il);
3019 /* else, we are overriding an existing key => no need to allocated room
3020 * in uCode. */
3021
3022 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3023 "no space for a new key");
3024
3025 il->stations[sta_id].sta.key.key_flags = key_flags;
3026 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3027 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3028
3029 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3030 sizeof(struct il_addsta_cmd));
3031 spin_unlock_irqrestore(&il->sta_lock, flags);
3032
3033 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3034}
3035
3036static int il4965_set_tkip_dynamic_key_info(struct il_priv *il,
3037 struct il_rxon_context *ctx,
3038 struct ieee80211_key_conf *keyconf,
3039 u8 sta_id)
3040{
3041 unsigned long flags;
3042 int ret = 0;
3043 __le16 key_flags = 0;
3044
3045 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3046 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3047 key_flags &= ~STA_KEY_FLG_INVALID;
3048
3049 if (sta_id == ctx->bcast_sta_id)
3050 key_flags |= STA_KEY_MULTICAST_MSK;
3051
3052 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3053 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3054
3055 spin_lock_irqsave(&il->sta_lock, flags);
3056
3057 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3058 il->stations[sta_id].keyinfo.keylen = 16;
3059
3060 if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
3061 == STA_KEY_FLG_NO_ENC)
3062 il->stations[sta_id].sta.key.key_offset =
3063 il_get_free_ucode_key_idx(il);
3064 /* else, we are overriding an existing key => no need to allocated room
3065 * in uCode. */
3066
3067 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3068 "no space for a new key");
3069
3070 il->stations[sta_id].sta.key.key_flags = key_flags;
3071
3072
3073 /* This copy is acutally not needed: we get the key with each TX */
3074 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3075
3076 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3077
3078 spin_unlock_irqrestore(&il->sta_lock, flags);
3079
3080 return ret;
3081}
3082
3083void il4965_update_tkip_key(struct il_priv *il,
3084 struct il_rxon_context *ctx,
3085 struct ieee80211_key_conf *keyconf,
3086 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
3087{
3088 u8 sta_id;
3089 unsigned long flags;
3090 int i;
3091
3092 if (il_scan_cancel(il)) {
3093 /* cancel scan failed, just live w/ bad key and rely
3094 briefly on SW decryption */
3095 return;
3096 }
3097
3098 sta_id = il_sta_id_or_broadcast(il, ctx, sta);
3099 if (sta_id == IL_INVALID_STATION)
3100 return;
3101
3102 spin_lock_irqsave(&il->sta_lock, flags);
3103
3104 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3105
3106 for (i = 0; i < 5; i++)
3107 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
3108 cpu_to_le16(phase1key[i]);
3109
3110 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3111 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3112
3113 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3114
3115 spin_unlock_irqrestore(&il->sta_lock, flags);
3116
3117}
3118
3119int il4965_remove_dynamic_key(struct il_priv *il,
3120 struct il_rxon_context *ctx,
3121 struct ieee80211_key_conf *keyconf,
3122 u8 sta_id)
3123{
3124 unsigned long flags;
3125 u16 key_flags;
3126 u8 keyidx;
3127 struct il_addsta_cmd sta_cmd;
3128
3129 lockdep_assert_held(&il->mutex);
3130
3131 ctx->key_mapping_keys--;
3132
3133 spin_lock_irqsave(&il->sta_lock, flags);
3134 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3135 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3136
3137 D_WEP("Remove dynamic key: idx=%d sta=%d\n",
3138 keyconf->keyidx, sta_id);
3139
3140 if (keyconf->keyidx != keyidx) {
3141 /* We need to remove a key with idx different that the one
3142 * in the uCode. This means that the key we need to remove has
3143 * been replaced by another one with different idx.
3144 * Don't do anything and return ok
3145 */
3146 spin_unlock_irqrestore(&il->sta_lock, flags);
3147 return 0;
3148 }
3149
3150 if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) {
3151 IL_WARN("Removing wrong key %d 0x%x\n",
3152 keyconf->keyidx, key_flags);
3153 spin_unlock_irqrestore(&il->sta_lock, flags);
3154 return 0;
3155 }
3156
3157 if (!test_and_clear_bit(il->stations[sta_id].sta.key.key_offset,
3158 &il->ucode_key_table))
3159 IL_ERR("idx %d not used in uCode key table.\n",
3160 il->stations[sta_id].sta.key.key_offset);
3161 memset(&il->stations[sta_id].keyinfo, 0,
3162 sizeof(struct il_hw_key));
3163 memset(&il->stations[sta_id].sta.key, 0,
3164 sizeof(struct il4965_keyinfo));
3165 il->stations[sta_id].sta.key.key_flags =
3166 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
3167 il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
3168 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3169 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3170
3171 if (il_is_rfkill(il)) {
3172 D_WEP(
3173 "Not sending REPLY_ADD_STA command because RFKILL enabled.\n");
3174 spin_unlock_irqrestore(&il->sta_lock, flags);
3175 return 0;
3176 }
3177 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3178 sizeof(struct il_addsta_cmd));
3179 spin_unlock_irqrestore(&il->sta_lock, flags);
3180
3181 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3182}
3183
3184int il4965_set_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx,
3185 struct ieee80211_key_conf *keyconf, u8 sta_id)
3186{
3187 int ret;
3188
3189 lockdep_assert_held(&il->mutex);
3190
3191 ctx->key_mapping_keys++;
3192 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3193
3194 switch (keyconf->cipher) {
3195 case WLAN_CIPHER_SUITE_CCMP:
3196 ret = il4965_set_ccmp_dynamic_key_info(il, ctx,
3197 keyconf, sta_id);
3198 break;
3199 case WLAN_CIPHER_SUITE_TKIP:
3200 ret = il4965_set_tkip_dynamic_key_info(il, ctx,
3201 keyconf, sta_id);
3202 break;
3203 case WLAN_CIPHER_SUITE_WEP40:
3204 case WLAN_CIPHER_SUITE_WEP104:
3205 ret = il4965_set_wep_dynamic_key_info(il, ctx,
3206 keyconf, sta_id);
3207 break;
3208 default:
3209 IL_ERR(
3210 "Unknown alg: %s cipher = %x\n", __func__,
3211 keyconf->cipher);
3212 ret = -EINVAL;
3213 }
3214
3215 D_WEP(
3216 "Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3217 keyconf->cipher, keyconf->keylen, keyconf->keyidx,
3218 sta_id, ret);
3219
3220 return ret;
3221}
3222
3223/**
3224 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3225 *
3226 * This adds the broadcast station into the driver's station table
3227 * and marks it driver active, so that it will be restored to the
3228 * device at the next best time.
3229 */
3230int il4965_alloc_bcast_station(struct il_priv *il,
3231 struct il_rxon_context *ctx)
3232{
3233 struct il_link_quality_cmd *link_cmd;
3234 unsigned long flags;
3235 u8 sta_id;
3236
3237 spin_lock_irqsave(&il->sta_lock, flags);
3238 sta_id = il_prep_station(il, ctx, il_bcast_addr,
3239 false, NULL);
3240 if (sta_id == IL_INVALID_STATION) {
3241 IL_ERR("Unable to prepare broadcast station\n");
3242 spin_unlock_irqrestore(&il->sta_lock, flags);
3243
3244 return -EINVAL;
3245 }
3246
3247 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3248 il->stations[sta_id].used |= IL_STA_BCAST;
3249 spin_unlock_irqrestore(&il->sta_lock, flags);
3250
3251 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3252 if (!link_cmd) {
3253 IL_ERR(
3254 "Unable to initialize rate scaling for bcast station.\n");
3255 return -ENOMEM;
3256 }
3257
3258 spin_lock_irqsave(&il->sta_lock, flags);
3259 il->stations[sta_id].lq = link_cmd;
3260 spin_unlock_irqrestore(&il->sta_lock, flags);
3261
3262 return 0;
3263}
3264
3265/**
3266 * il4965_update_bcast_station - update broadcast station's LQ command
3267 *
3268 * Only used by iwl4965. Placed here to have all bcast station management
3269 * code together.
3270 */
3271static int il4965_update_bcast_station(struct il_priv *il,
3272 struct il_rxon_context *ctx)
3273{
3274 unsigned long flags;
3275 struct il_link_quality_cmd *link_cmd;
3276 u8 sta_id = ctx->bcast_sta_id;
3277
3278 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3279 if (!link_cmd) {
3280 IL_ERR(
3281 "Unable to initialize rate scaling for bcast station.\n");
3282 return -ENOMEM;
3283 }
3284
3285 spin_lock_irqsave(&il->sta_lock, flags);
3286 if (il->stations[sta_id].lq)
3287 kfree(il->stations[sta_id].lq);
3288 else
3289 D_INFO(
3290 "Bcast station rate scaling has not been initialized yet.\n");
3291 il->stations[sta_id].lq = link_cmd;
3292 spin_unlock_irqrestore(&il->sta_lock, flags);
3293
3294 return 0;
3295}
3296
3297int il4965_update_bcast_stations(struct il_priv *il)
3298{
3299 return il4965_update_bcast_station(il, &il->ctx);
3300}
3301
3302/**
3303 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3304 */
3305int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
3306{
3307 unsigned long flags;
3308 struct il_addsta_cmd sta_cmd;
3309
3310 lockdep_assert_held(&il->mutex);
3311
3312 /* Remove "disable" flag, to enable Tx for this TID */
3313 spin_lock_irqsave(&il->sta_lock, flags);
3314 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3315 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3316 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3317 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3318 sizeof(struct il_addsta_cmd));
3319 spin_unlock_irqrestore(&il->sta_lock, flags);
3320
3321 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3322}
3323
3324int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
3325 int tid, u16 ssn)
3326{
3327 unsigned long flags;
3328 int sta_id;
3329 struct il_addsta_cmd sta_cmd;
3330
3331 lockdep_assert_held(&il->mutex);
3332
3333 sta_id = il_sta_id(sta);
3334 if (sta_id == IL_INVALID_STATION)
3335 return -ENXIO;
3336
3337 spin_lock_irqsave(&il->sta_lock, flags);
3338 il->stations[sta_id].sta.station_flags_msk = 0;
3339 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3340 il->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
3341 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3342 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3343 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3344 sizeof(struct il_addsta_cmd));
3345 spin_unlock_irqrestore(&il->sta_lock, flags);
3346
3347 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3348}
3349
3350int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
3351 int tid)
3352{
3353 unsigned long flags;
3354 int sta_id;
3355 struct il_addsta_cmd sta_cmd;
3356
3357 lockdep_assert_held(&il->mutex);
3358
3359 sta_id = il_sta_id(sta);
3360 if (sta_id == IL_INVALID_STATION) {
3361 IL_ERR("Invalid station for AGG tid %d\n", tid);
3362 return -ENXIO;
3363 }
3364
3365 spin_lock_irqsave(&il->sta_lock, flags);
3366 il->stations[sta_id].sta.station_flags_msk = 0;
3367 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3368 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
3369 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3370 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3371 sizeof(struct il_addsta_cmd));
3372 spin_unlock_irqrestore(&il->sta_lock, flags);
3373
3374 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3375}
3376
3377void
3378il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3379{
3380 unsigned long flags;
3381
3382 spin_lock_irqsave(&il->sta_lock, flags);
3383 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3384 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3385 il->stations[sta_id].sta.sta.modify_mask =
3386 STA_MODIFY_SLEEP_TX_COUNT_MSK;
3387 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3388 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3389 il_send_add_sta(il,
3390 &il->stations[sta_id].sta, CMD_ASYNC);
3391 spin_unlock_irqrestore(&il->sta_lock, flags);
3392
3393}
3394
46bc8d4b 3395void il4965_update_chain_flags(struct il_priv *il)
be663ab6 3396{
46bc8d4b 3397 if (il->cfg->ops->hcmd->set_rxon_chain) {
17d6e557
SG		 3398 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
3399 if (il->ctx.active.rx_chain != il->ctx.staging.rx_chain)
3400 il_commit_rxon(il, &il->ctx);
be663ab6
WYG		 3401 }
3402}
3403
46bc8d4b 3404static void il4965_clear_free_frames(struct il_priv *il)
be663ab6
WYG		 3405{
3406 struct list_head *element;
3407
58de00a4 3408 D_INFO("%d frames on pre-allocated heap on clear.\n",
46bc8d4b 3409 il->frames_count);
be663ab6 3410
46bc8d4b
SG		 3411 while (!list_empty(&il->free_frames)) {
3412 element = il->free_frames.next;
be663ab6 3413 list_del(element);
e2ebc833 3414 kfree(list_entry(element, struct il_frame, list));
46bc8d4b 3415 il->frames_count--;
be663ab6
WYG		 3416 }
3417
46bc8d4b 3418 if (il->frames_count) {
9406f797 3419 IL_WARN("%d frames still in use. Did we lose one?\n",
46bc8d4b
SG		 3420 il->frames_count);
3421 il->frames_count = 0;
be663ab6
WYG		 3422 }
3423}
3424
46bc8d4b 3425static struct il_frame *il4965_get_free_frame(struct il_priv *il)
be663ab6 3426{
e2ebc833 3427 struct il_frame *frame;
be663ab6 3428 struct list_head *element;
46bc8d4b 3429 if (list_empty(&il->free_frames)) {
be663ab6
WYG		 3430 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3431 if (!frame) {
9406f797 3432 IL_ERR("Could not allocate frame!\n");
be663ab6
WYG		 3433 return NULL;
3434 }
3435
46bc8d4b 3436 il->frames_count++;
be663ab6
WYG		 3437 return frame;
3438 }
3439
46bc8d4b 3440 element = il->free_frames.next;
be663ab6 3441 list_del(element);
e2ebc833 3442 return list_entry(element, struct il_frame, list);
be663ab6
WYG		 3443}
3444
46bc8d4b 3445static void il4965_free_frame(struct il_priv *il, struct il_frame *frame)
be663ab6
WYG		 3446{
3447 memset(frame, 0, sizeof(*frame));
46bc8d4b 3448 list_add(&frame->list, &il->free_frames);
be663ab6
WYG		 3449}
3450
46bc8d4b 3451static u32 il4965_fill_beacon_frame(struct il_priv *il,
be663ab6
WYG		 3452 struct ieee80211_hdr *hdr,
3453 int left)
3454{
46bc8d4b 3455 lockdep_assert_held(&il->mutex);
be663ab6 3456
46bc8d4b 3457 if (!il->beacon_skb)
be663ab6
WYG		 3458 return 0;
3459
46bc8d4b 3460 if (il->beacon_skb->len > left)
be663ab6
WYG		 3461 return 0;
3462
46bc8d4b 3463 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
be663ab6 3464
46bc8d4b 3465 return il->beacon_skb->len;
be663ab6
WYG		 3466}
3467
3468/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
46bc8d4b 3469static void il4965_set_beacon_tim(struct il_priv *il,
e2ebc833 3470 struct il_tx_beacon_cmd *tx_beacon_cmd,
be663ab6
WYG		 3471 u8 *beacon, u32 frame_size)
3472{
3473 u16 tim_idx;
3474 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3475
3476 /*
0c2c8852 3477 * The idx is relative to frame start but we start looking at the
be663ab6
WYG		 3478 * variable-length part of the beacon.
3479 */
3480 tim_idx = mgmt->u.beacon.variable - beacon;
3481
3482 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3483 while ((tim_idx < (frame_size - 2)) &&
3484 (beacon[tim_idx] != WLAN_EID_TIM))
3485 tim_idx += beacon[tim_idx+1] + 2;
3486
3487 /* If TIM field was found, set variables */
3488 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3489 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
3490 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
3491 } else
9406f797 3492 IL_WARN("Unable to find TIM Element in beacon\n");
be663ab6
WYG		 3493}
3494
46bc8d4b 3495static unsigned int il4965_hw_get_beacon_cmd(struct il_priv *il,
e2ebc833 3496 struct il_frame *frame)
be663ab6 3497{
e2ebc833 3498 struct il_tx_beacon_cmd *tx_beacon_cmd;
be663ab6
WYG		 3499 u32 frame_size;
3500 u32 rate_flags;
3501 u32 rate;
3502 /*
3503 * We have to set up the TX command, the TX Beacon command, and the
3504 * beacon contents.
3505 */
3506
46bc8d4b 3507 lockdep_assert_held(&il->mutex);
be663ab6 3508
46bc8d4b 3509 if (!il->beacon_ctx) {
9406f797 3510 IL_ERR("trying to build beacon w/o beacon context!\n");
be663ab6
WYG		 3511 return 0;
3512 }
3513
3514 /* Initialize memory */
3515 tx_beacon_cmd = &frame->u.beacon;
3516 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3517
3518 /* Set up TX beacon contents */
46bc8d4b 3519 frame_size = il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
be663ab6
WYG		 3520 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3521 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3522 return 0;
3523 if (!frame_size)
3524 return 0;
3525
3526 /* Set up TX command fields */
3527 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
46bc8d4b 3528 tx_beacon_cmd->tx.sta_id = il->beacon_ctx->bcast_sta_id;
be663ab6
WYG		 3529 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3530 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
3531 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
3532
3533 /* Set up TX beacon command fields */
46bc8d4b 3534 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
be663ab6
WYG		 3535 frame_size);
3536
3537 /* Set up packet rate and flags */
46bc8d4b
SG		 3538 rate = il_get_lowest_plcp(il, il->beacon_ctx);
3539 il->mgmt_tx_ant = il4965_toggle_tx_ant(il, il->mgmt_tx_ant,
3540 il->hw_params.valid_tx_ant);
3541 rate_flags = il4965_ant_idx_to_flags(il->mgmt_tx_ant);
e2ebc833 3542 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
be663ab6 3543 rate_flags |= RATE_MCS_CCK_MSK;
e2ebc833 3544 tx_beacon_cmd->tx.rate_n_flags = il4965_hw_set_rate_n_flags(rate,
be663ab6
WYG		 3545 rate_flags);
3546
3547 return sizeof(*tx_beacon_cmd) + frame_size;
3548}
3549
46bc8d4b 3550int il4965_send_beacon_cmd(struct il_priv *il)
be663ab6 3551{
e2ebc833 3552 struct il_frame *frame;
be663ab6
WYG		 3553 unsigned int frame_size;
3554 int rc;
3555
46bc8d4b 3556 frame = il4965_get_free_frame(il);
be663ab6 3557 if (!frame) {
9406f797 3558 IL_ERR("Could not obtain free frame buffer for beacon "
be663ab6
WYG		 3559 "command.\n");
3560 return -ENOMEM;
3561 }
3562
46bc8d4b 3563 frame_size = il4965_hw_get_beacon_cmd(il, frame);
be663ab6 3564 if (!frame_size) {
9406f797 3565 IL_ERR("Error configuring the beacon command\n");
46bc8d4b 3566 il4965_free_frame(il, frame);
be663ab6
WYG		 3567 return -EINVAL;
3568 }
3569
46bc8d4b 3570 rc = il_send_cmd_pdu(il, REPLY_TX_BEACON, frame_size,
be663ab6
WYG		 3571 &frame->u.cmd[0]);
3572
46bc8d4b 3573 il4965_free_frame(il, frame);
be663ab6
WYG		 3574
3575 return rc;
3576}
3577
e2ebc833 3578static inline dma_addr_t il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
be663ab6 3579{
e2ebc833 3580 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3581
3582 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3583 if (sizeof(dma_addr_t) > sizeof(u32))
3584 addr |=
3585 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
3586
3587 return addr;
3588}
3589
e2ebc833 3590static inline u16 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
be663ab6 3591{
e2ebc833 3592 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3593
3594 return le16_to_cpu(tb->hi_n_len) >> 4;
3595}
3596
e2ebc833 3597static inline void il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx,
be663ab6
WYG		 3598 dma_addr_t addr, u16 len)
3599{
e2ebc833 3600 struct il_tfd_tb *tb = &tfd->tbs[idx];
be663ab6
WYG		 3601 u16 hi_n_len = len << 4;
3602
3603 put_unaligned_le32(addr, &tb->lo);
3604 if (sizeof(dma_addr_t) > sizeof(u32))
3605 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3606
3607 tb->hi_n_len = cpu_to_le16(hi_n_len);
3608
3609 tfd->num_tbs = idx + 1;
3610}
3611
e2ebc833 3612static inline u8 il4965_tfd_get_num_tbs(struct il_tfd *tfd)
be663ab6
WYG		 3613{
3614 return tfd->num_tbs & 0x1f;
3615}
3616
3617/**
e2ebc833 3618 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
46bc8d4b 3619 * @il - driver ilate data
be663ab6
WYG		 3620 * @txq - tx queue
3621 *
0c2c8852 3622 * Does NOT advance any TFD circular buffer read/write idxes
be663ab6
WYG		 3623 * Does NOT free the TFD itself (which is within circular buffer)
3624 */
46bc8d4b 3625void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
be663ab6 3626{
e2ebc833
SG		 3627 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3628 struct il_tfd *tfd;
46bc8d4b 3629 struct pci_dev *dev = il->pci_dev;
0c2c8852 3630 int idx = txq->q.read_ptr;
be663ab6
WYG		 3631 int i;
3632 int num_tbs;
3633
0c2c8852 3634 tfd = &tfd_tmp[idx];
be663ab6
WYG		 3635
3636 /* Sanity check on number of chunks */
e2ebc833 3637 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6 3638
e2ebc833 3639 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3640 IL_ERR("Too many chunks: %i\n", num_tbs);
be663ab6
WYG		 3641 /* @todo issue fatal error, it is quite serious situation */
3642 return;
3643 }
3644
3645 /* Unmap tx_cmd */
3646 if (num_tbs)
3647 pci_unmap_single(dev,
0c2c8852
SG		 3648 dma_unmap_addr(&txq->meta[idx], mapping),
3649 dma_unmap_len(&txq->meta[idx], len),
be663ab6
WYG		 3650 PCI_DMA_BIDIRECTIONAL);
3651
3652 /* Unmap chunks, if any. */
3653 for (i = 1; i < num_tbs; i++)
e2ebc833
SG		 3654 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
3655 il4965_tfd_tb_get_len(tfd, i),
be663ab6
WYG		 3656 PCI_DMA_TODEVICE);
3657
3658 /* free SKB */
3659 if (txq->txb) {
3660 struct sk_buff *skb;
3661
3662 skb = txq->txb[txq->q.read_ptr].skb;
3663
3664 /* can be called from irqs-disabled context */
3665 if (skb) {
3666 dev_kfree_skb_any(skb);
3667 txq->txb[txq->q.read_ptr].skb = NULL;
3668 }
3669 }
3670}
3671
46bc8d4b 3672int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il,
e2ebc833 3673 struct il_tx_queue *txq,
be663ab6
WYG		 3674 dma_addr_t addr, u16 len,
3675 u8 reset, u8 pad)
3676{
e2ebc833
SG		 3677 struct il_queue *q;
3678 struct il_tfd *tfd, *tfd_tmp;
be663ab6
WYG		 3679 u32 num_tbs;
3680
3681 q = &txq->q;
e2ebc833 3682 tfd_tmp = (struct il_tfd *)txq->tfds;
be663ab6
WYG		 3683 tfd = &tfd_tmp[q->write_ptr];
3684
3685 if (reset)
3686 memset(tfd, 0, sizeof(*tfd));
3687
e2ebc833 3688 num_tbs = il4965_tfd_get_num_tbs(tfd);
be663ab6
WYG		 3689
3690 /* Each TFD can point to a maximum 20 Tx buffers */
e2ebc833 3691 if (num_tbs >= IL_NUM_OF_TBS) {
9406f797 3692 IL_ERR("Error can not send more than %d chunks\n",
e2ebc833 3693 IL_NUM_OF_TBS);
be663ab6
WYG		 3694 return -EINVAL;
3695 }
3696
3697 BUG_ON(addr & ~DMA_BIT_MASK(36));
e2ebc833 3698 if (unlikely(addr & ~IL_TX_DMA_MASK))
9406f797 3699 IL_ERR("Unaligned address = %llx\n",
be663ab6
WYG		 3700 (unsigned long long)addr);
3701
e2ebc833 3702 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
be663ab6
WYG		 3703
3704 return 0;
3705}
3706
3707/*
3708 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3709 * given Tx queue, and enable the DMA channel used for that queue.
3710 *
3711 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3712 * channels supported in hardware.
3713 */
46bc8d4b 3714int il4965_hw_tx_queue_init(struct il_priv *il,
e2ebc833 3715 struct il_tx_queue *txq)
be663ab6
WYG		 3716{
3717 int txq_id = txq->q.id;
3718
3719 /* Circular buffer (TFD queue in DRAM) physical base address */
0c1a94e2 3720 il_wr(il, FH_MEM_CBBC_QUEUE(txq_id),
be663ab6
WYG		 3721 txq->q.dma_addr >> 8);
3722
3723 return 0;
3724}
3725
3726/******************************************************************************
3727 *
3728 * Generic RX handler implementations
3729 *
3730 ******************************************************************************/
46bc8d4b 3731static void il4965_rx_reply_alive(struct il_priv *il,
b73bb5f1 3732 struct il_rx_buf *rxb)
be663ab6 3733{
dcae1c64 3734 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 3735 struct il_alive_resp *palive;
be663ab6
WYG		 3736 struct delayed_work *pwork;
3737
3738 palive = &pkt->u.alive_frame;
3739
58de00a4 3740 D_INFO("Alive ucode status 0x%08X revision "
be663ab6
WYG		 3741 "0x%01X 0x%01X\n",
3742 palive->is_valid, palive->ver_type,
3743 palive->ver_subtype);
3744
3745 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 3746 D_INFO("Initialization Alive received.\n");
46bc8d4b 3747 memcpy(&il->card_alive_init,
be663ab6 3748 &pkt->u.alive_frame,
e2ebc833 3749 sizeof(struct il_init_alive_resp));
46bc8d4b 3750 pwork = &il->init_alive_start;
be663ab6 3751 } else {
58de00a4 3752 D_INFO("Runtime Alive received.\n");
46bc8d4b 3753 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 3754 sizeof(struct il_alive_resp));
46bc8d4b 3755 pwork = &il->alive_start;
be663ab6
WYG		 3756 }
3757
3758 /* We delay the ALIVE response by 5ms to
3759 * give the HW RF Kill time to activate... */
3760 if (palive->is_valid == UCODE_VALID_OK)
46bc8d4b 3761 queue_delayed_work(il->workqueue, pwork,
be663ab6
WYG		 3762 msecs_to_jiffies(5));
3763 else
9406f797 3764 IL_WARN("uCode did not respond OK.\n");
be663ab6
WYG		 3765}
3766
3767/**
ebf0d90d 3768 * il4965_bg_stats_periodic - Timer callback to queue stats
be663ab6 3769 *
ebf0d90d 3770 * This callback is provided in order to send a stats request.
be663ab6
WYG		 3771 *
3772 * This timer function is continually reset to execute within
3773 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
ebf0d90d 3774 * was received. We need to ensure we receive the stats in order
be663ab6
WYG		 3775 * to update the temperature used for calibrating the TXPOWER.
3776 */
ebf0d90d 3777static void il4965_bg_stats_periodic(unsigned long data)
be663ab6 3778{
46bc8d4b 3779 struct il_priv *il = (struct il_priv *)data;
be663ab6 3780
46bc8d4b 3781 if (test_bit(STATUS_EXIT_PENDING, &il->status))
be663ab6
WYG		 3782 return;
3783
3784 /* dont send host command if rf-kill is on */
46bc8d4b 3785 if (!il_is_ready_rf(il))
be663ab6
WYG		 3786 return;
3787
ebf0d90d 3788 il_send_stats_request(il, CMD_ASYNC, false);
be663ab6
WYG		 3789}
3790
46bc8d4b 3791static void il4965_rx_beacon_notif(struct il_priv *il,
b73bb5f1 3792 struct il_rx_buf *rxb)
be663ab6 3793{
dcae1c64 3794 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833
SG		 3795 struct il4965_beacon_notif *beacon =
3796 (struct il4965_beacon_notif *)pkt->u.raw;
d3175167 3797#ifdef CONFIG_IWLEGACY_DEBUG
e2ebc833 3798 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
be663ab6 3799
58de00a4 3800 D_RX("beacon status %x retries %d iss %d "
be663ab6
WYG		 3801 "tsf %d %d rate %d\n",
3802 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
3803 beacon->beacon_notify_hdr.failure_frame,
3804 le32_to_cpu(beacon->ibss_mgr_status),
3805 le32_to_cpu(beacon->high_tsf),
3806 le32_to_cpu(beacon->low_tsf), rate);
3807#endif
3808
46bc8d4b 3809 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
be663ab6
WYG		 3810}
3811
46bc8d4b 3812static void il4965_perform_ct_kill_task(struct il_priv *il)
be663ab6
WYG		 3813{
3814 unsigned long flags;
3815
58de00a4 3816 D_POWER("Stop all queues\n");
be663ab6 3817
46bc8d4b
SG		 3818 if (il->mac80211_registered)
3819 ieee80211_stop_queues(il->hw);
be663ab6 3820
841b2cca 3821 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
be663ab6 3822 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
841b2cca 3823 _il_rd(il, CSR_UCODE_DRV_GP1);
be663ab6 3824
46bc8d4b 3825 spin_lock_irqsave(&il->reg_lock, flags);
13882269
SG		 3826 if (!_il_grab_nic_access(il))
3827 _il_release_nic_access(il);
46bc8d4b 3828 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6
WYG		 3829}
3830
3831/* Handle notification from uCode that card's power state is changing
3832 * due to software, hardware, or critical temperature RFKILL */
46bc8d4b 3833static void il4965_rx_card_state_notif(struct il_priv *il,
b73bb5f1 3834 struct il_rx_buf *rxb)
be663ab6 3835{
dcae1c64 3836 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 3837 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 3838 unsigned long status = il->status;
be663ab6 3839
58de00a4 3840 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
be663ab6
WYG		 3841 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3842 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
3843 (flags & CT_CARD_DISABLED) ?
3844 "Reached" : "Not reached");
3845
3846 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3847 CT_CARD_DISABLED)) {
3848
841b2cca 3849 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
be663ab6
WYG		 3850 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3851
0c1a94e2 3852 il_wr(il, HBUS_TARG_MBX_C,
be663ab6
WYG		 3853 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3854
3855 if (!(flags & RXON_CARD_DISABLED)) {
841b2cca 3856 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
be663ab6 3857 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0c1a94e2 3858 il_wr(il, HBUS_TARG_MBX_C,
be663ab6
WYG		 3859 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3860 }
3861 }
3862
3863 if (flags & CT_CARD_DISABLED)
46bc8d4b 3864 il4965_perform_ct_kill_task(il);
be663ab6
WYG		 3865
3866 if (flags & HW_CARD_DISABLED)
46bc8d4b 3867 set_bit(STATUS_RF_KILL_HW, &il->status);
be663ab6 3868 else
46bc8d4b 3869 clear_bit(STATUS_RF_KILL_HW, &il->status);
be663ab6
WYG		 3870
3871 if (!(flags & RXON_CARD_DISABLED))
46bc8d4b 3872 il_scan_cancel(il);
be663ab6
WYG		 3873
3874 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
46bc8d4b
SG		 3875 test_bit(STATUS_RF_KILL_HW, &il->status)))
3876 wiphy_rfkill_set_hw_state(il->hw->wiphy,
3877 test_bit(STATUS_RF_KILL_HW, &il->status));
be663ab6 3878 else
46bc8d4b 3879 wake_up(&il->wait_command_queue);
be663ab6
WYG		 3880}
3881
3882/**
e2ebc833 3883 * il4965_setup_rx_handlers - Initialize Rx handler callbacks
be663ab6
WYG		 3884 *
3885 * Setup the RX handlers for each of the reply types sent from the uCode
3886 * to the host.
3887 *
3888 * This function chains into the hardware specific files for them to setup
3889 * any hardware specific handlers as well.
3890 */
46bc8d4b 3891static void il4965_setup_rx_handlers(struct il_priv *il)
be663ab6 3892{
46bc8d4b
SG		 3893 il->rx_handlers[REPLY_ALIVE] = il4965_rx_reply_alive;
3894 il->rx_handlers[REPLY_ERROR] = il_rx_reply_error;
3895 il->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = il_rx_csa;
3896 il->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
e2ebc833 3897 il_rx_spectrum_measure_notif;
46bc8d4b
SG		 3898 il->rx_handlers[PM_SLEEP_NOTIFICATION] = il_rx_pm_sleep_notif;
3899 il->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
ebf0d90d 3900 il_rx_pm_debug_stats_notif;
46bc8d4b 3901 il->rx_handlers[BEACON_NOTIFICATION] = il4965_rx_beacon_notif;
be663ab6
WYG		 3902
3903 /*
3904 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG		 3905 * stats request from the host as well as for the periodic
3906 * stats notifications (after received beacons) from the uCode.
be663ab6 3907 */
ebf0d90d
SG		 3908 il->rx_handlers[REPLY_STATISTICS_CMD] = il4965_reply_stats;
3909 il->rx_handlers[STATISTICS_NOTIFICATION] = il4965_rx_stats;
be663ab6 3910
46bc8d4b 3911 il_setup_rx_scan_handlers(il);
be663ab6
WYG		 3912
3913 /* status change handler */
46bc8d4b 3914 il->rx_handlers[CARD_STATE_NOTIFICATION] =
e2ebc833 3915 il4965_rx_card_state_notif;
be663ab6 3916
46bc8d4b 3917 il->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
e2ebc833 3918 il4965_rx_missed_beacon_notif;
be663ab6 3919 /* Rx handlers */
46bc8d4b
SG		 3920 il->rx_handlers[REPLY_RX_PHY_CMD] = il4965_rx_reply_rx_phy;
3921 il->rx_handlers[REPLY_RX_MPDU_CMD] = il4965_rx_reply_rx;
be663ab6 3922 /* block ack */
46bc8d4b 3923 il->rx_handlers[REPLY_COMPRESSED_BA] = il4965_rx_reply_compressed_ba;
be663ab6 3924 /* Set up hardware specific Rx handlers */
46bc8d4b 3925 il->cfg->ops->lib->rx_handler_setup(il);
be663ab6
WYG		 3926}
3927
3928/**
e2ebc833 3929 * il4965_rx_handle - Main entry function for receiving responses from uCode
be663ab6 3930 *
46bc8d4b 3931 * Uses the il->rx_handlers callback function array to invoke
be663ab6
WYG		 3932 * the appropriate handlers, including command responses,
3933 * frame-received notifications, and other notifications.
3934 */
46bc8d4b 3935void il4965_rx_handle(struct il_priv *il)
be663ab6 3936{
b73bb5f1 3937 struct il_rx_buf *rxb;
dcae1c64 3938 struct il_rx_pkt *pkt;
46bc8d4b 3939 struct il_rx_queue *rxq = &il->rxq;
be663ab6
WYG		 3940 u32 r, i;
3941 int reclaim;
3942 unsigned long flags;
3943 u8 fill_rx = 0;
3944 u32 count = 8;
3945 int total_empty;
3946
0c2c8852 3947 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
be663ab6
WYG		 3948 * buffer that the driver may process (last buffer filled by ucode). */
3949 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
3950 i = rxq->read;
3951
3952 /* Rx interrupt, but nothing sent from uCode */
3953 if (i == r)
58de00a4 3954 D_RX("r = %d, i = %d\n", r, i);
be663ab6
WYG		 3955
3956 /* calculate total frames need to be restock after handling RX */
3957 total_empty = r - rxq->write_actual;
3958 if (total_empty < 0)
3959 total_empty += RX_QUEUE_SIZE;
3960
3961 if (total_empty > (RX_QUEUE_SIZE / 2))
3962 fill_rx = 1;
3963
3964 while (i != r) {
3965 int len;
3966
3967 rxb = rxq->queue[i];
3968
3969 /* If an RXB doesn't have a Rx queue slot associated with it,
3970 * then a bug has been introduced in the queue refilling
3971 * routines -- catch it here */
3972 BUG_ON(rxb == NULL);
3973
3974 rxq->queue[i] = NULL;
3975
46bc8d4b
SG		 3976 pci_unmap_page(il->pci_dev, rxb->page_dma,
3977 PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 3978 PCI_DMA_FROMDEVICE);
3979 pkt = rxb_addr(rxb);
3980
3981 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
3982 len += sizeof(u32); /* account for status word */
be663ab6
WYG		 3983
3984 /* Reclaim a command buffer only if this packet is a response
3985 * to a (driver-originated) command.
3986 * If the packet (e.g. Rx frame) originated from uCode,
3987 * there is no command buffer to reclaim.
3988 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3989 * but apparently a few don't get set; catch them here. */
3990 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3991 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
3992 (pkt->hdr.cmd != REPLY_RX) &&
3993 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
3994 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
3995 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3996 (pkt->hdr.cmd != REPLY_TX);
3997
3998 /* Based on type of command response or notification,
3999 * handle those that need handling via function in
e2ebc833 4000 * rx_handlers table. See il4965_setup_rx_handlers() */
46bc8d4b 4001 if (il->rx_handlers[pkt->hdr.cmd]) {
58de00a4 4002 D_RX("r = %d, i = %d, %s, 0x%02x\n", r,
e2ebc833 4003 i, il_get_cmd_string(pkt->hdr.cmd),
be663ab6 4004 pkt->hdr.cmd);
46bc8d4b
SG		 4005 il->isr_stats.rx_handlers[pkt->hdr.cmd]++;
4006 il->rx_handlers[pkt->hdr.cmd] (il, rxb);
be663ab6
WYG		 4007 } else {
4008 /* No handling needed */
58de00a4 4009 D_RX(
be663ab6 4010 "r %d i %d No handler needed for %s, 0x%02x\n",
e2ebc833 4011 r, i, il_get_cmd_string(pkt->hdr.cmd),
be663ab6
WYG		 4012 pkt->hdr.cmd);
4013 }
4014
4015 /*
4016 * XXX: After here, we should always check rxb->page
4017 * against NULL before touching it or its virtual
4018 * memory (pkt). Because some rx_handler might have
4019 * already taken or freed the pages.
4020 */
4021
4022 if (reclaim) {
4023 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 4024 * and fire off the (possibly) blocking il_send_cmd()
be663ab6
WYG		 4025 * as we reclaim the driver command queue */
4026 if (rxb->page)
46bc8d4b 4027 il_tx_cmd_complete(il, rxb);
be663ab6 4028 else
9406f797 4029 IL_WARN("Claim null rxb?\n");
be663ab6
WYG		 4030 }
4031
4032 /* Reuse the page if possible. For notification packets and
4033 * SKBs that fail to Rx correctly, add them back into the
4034 * rx_free list for reuse later. */
4035 spin_lock_irqsave(&rxq->lock, flags);
4036 if (rxb->page != NULL) {
46bc8d4b
SG		 4037 rxb->page_dma = pci_map_page(il->pci_dev, rxb->page,
4038 0, PAGE_SIZE << il->hw_params.rx_page_order,
be663ab6
WYG		 4039 PCI_DMA_FROMDEVICE);
4040 list_add_tail(&rxb->list, &rxq->rx_free);
4041 rxq->free_count++;
4042 } else
4043 list_add_tail(&rxb->list, &rxq->rx_used);
4044
4045 spin_unlock_irqrestore(&rxq->lock, flags);
4046
4047 i = (i + 1) & RX_QUEUE_MASK;
4048 /* If there are a lot of unused frames,
4049 * restock the Rx queue so ucode wont assert. */
4050 if (fill_rx) {
4051 count++;
4052 if (count >= 8) {
4053 rxq->read = i;
46bc8d4b 4054 il4965_rx_replenish_now(il);
be663ab6
WYG		 4055 count = 0;
4056 }
4057 }
4058 }
4059
4060 /* Backtrack one entry */
4061 rxq->read = i;
4062 if (fill_rx)
46bc8d4b 4063 il4965_rx_replenish_now(il);
be663ab6 4064 else
46bc8d4b 4065 il4965_rx_queue_restock(il);
be663ab6
WYG		 4066}
4067
4068/* call this function to flush any scheduled tasklet */
46bc8d4b 4069static inline void il4965_synchronize_irq(struct il_priv *il)
be663ab6
WYG		 4070{
4071 /* wait to make sure we flush pending tasklet*/
46bc8d4b
SG		 4072 synchronize_irq(il->pci_dev->irq);
4073 tasklet_kill(&il->irq_tasklet);
be663ab6
WYG		 4074}
4075
46bc8d4b 4076static void il4965_irq_tasklet(struct il_priv *il)
be663ab6
WYG		 4077{
4078 u32 inta, handled = 0;
4079 u32 inta_fh;
4080 unsigned long flags;
4081 u32 i;
d3175167 4082#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4083 u32 inta_mask;
4084#endif
4085
46bc8d4b 4086 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4087
4088 /* Ack/clear/reset pending uCode interrupts.
4089 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4090 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG		 4091 inta = _il_rd(il, CSR_INT);
4092 _il_wr(il, CSR_INT, inta);
be663ab6
WYG		 4093
4094 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4095 * Any new interrupts that happen after this, either while we're
4096 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG		 4097 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4098 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
be663ab6 4099
d3175167 4100#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4101 if (il_get_debug_level(il) & IL_DL_ISR) {
be663ab6 4102 /* just for debug */
841b2cca 4103 inta_mask = _il_rd(il, CSR_INT_MASK);
58de00a4 4104 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
be663ab6
WYG		 4105 inta, inta_mask, inta_fh);
4106 }
4107#endif
4108
46bc8d4b 4109 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4110
4111 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4112 * atomic, make sure that inta covers all the interrupts that
4113 * we've discovered, even if FH interrupt came in just after
4114 * reading CSR_INT. */
4115 if (inta_fh & CSR49_FH_INT_RX_MASK)
4116 inta |= CSR_INT_BIT_FH_RX;
4117 if (inta_fh & CSR49_FH_INT_TX_MASK)
4118 inta |= CSR_INT_BIT_FH_TX;
4119
4120 /* Now service all interrupt bits discovered above. */
4121 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 4122 IL_ERR("Hardware error detected. Restarting.\n");
be663ab6
WYG		 4123
4124 /* Tell the device to stop sending interrupts */
46bc8d4b 4125 il_disable_interrupts(il);
be663ab6 4126
46bc8d4b
SG		 4127 il->isr_stats.hw++;
4128 il_irq_handle_error(il);
be663ab6
WYG		 4129
4130 handled |= CSR_INT_BIT_HW_ERR;
4131
4132 return;
4133 }
4134
d3175167 4135#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4136 if (il_get_debug_level(il) & (IL_DL_ISR)) {
be663ab6
WYG		 4137 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4138 if (inta & CSR_INT_BIT_SCD) {
58de00a4 4139 D_ISR("Scheduler finished to transmit "
be663ab6 4140 "the frame/frames.\n");
46bc8d4b 4141 il->isr_stats.sch++;
be663ab6
WYG		 4142 }
4143
4144 /* Alive notification via Rx interrupt will do the real work */
4145 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 4146 D_ISR("Alive interrupt\n");
46bc8d4b 4147 il->isr_stats.alive++;
be663ab6
WYG		 4148 }
4149 }
4150#endif
4151 /* Safely ignore these bits for debug checks below */
4152 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4153
4154 /* HW RF KILL switch toggled */
4155 if (inta & CSR_INT_BIT_RF_KILL) {
4156 int hw_rf_kill = 0;
841b2cca 4157 if (!(_il_rd(il, CSR_GP_CNTRL) &
be663ab6
WYG		 4158 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4159 hw_rf_kill = 1;
4160
9406f797 4161 IL_WARN("RF_KILL bit toggled to %s.\n",
be663ab6
WYG		 4162 hw_rf_kill ? "disable radio" : "enable radio");
4163
46bc8d4b 4164 il->isr_stats.rfkill++;
be663ab6
WYG		 4165
4166 /* driver only loads ucode once setting the interface up.
4167 * the driver allows loading the ucode even if the radio
4168 * is killed. Hence update the killswitch state here. The
4169 * rfkill handler will care about restarting if needed.
4170 */
46bc8d4b 4171 if (!test_bit(STATUS_ALIVE, &il->status)) {
be663ab6 4172 if (hw_rf_kill)
46bc8d4b 4173 set_bit(STATUS_RF_KILL_HW, &il->status);
be663ab6 4174 else
46bc8d4b
SG		 4175 clear_bit(STATUS_RF_KILL_HW, &il->status);
4176 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
be663ab6
WYG		 4177 }
4178
4179 handled |= CSR_INT_BIT_RF_KILL;
4180 }
4181
4182 /* Chip got too hot and stopped itself */
4183 if (inta & CSR_INT_BIT_CT_KILL) {
9406f797 4184 IL_ERR("Microcode CT kill error detected.\n");
46bc8d4b 4185 il->isr_stats.ctkill++;
be663ab6
WYG		 4186 handled |= CSR_INT_BIT_CT_KILL;
4187 }
4188
4189 /* Error detected by uCode */
4190 if (inta & CSR_INT_BIT_SW_ERR) {
9406f797 4191 IL_ERR("Microcode SW error detected. "
be663ab6 4192 " Restarting 0x%X.\n", inta);
46bc8d4b
SG		 4193 il->isr_stats.sw++;
4194 il_irq_handle_error(il);
be663ab6
WYG		 4195 handled |= CSR_INT_BIT_SW_ERR;
4196 }
4197
4198 /*
4199 * uCode wakes up after power-down sleep.
4200 * Tell device about any new tx or host commands enqueued,
4201 * and about any Rx buffers made available while asleep.
4202 */
4203 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 4204 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG		 4205 il_rx_queue_update_write_ptr(il, &il->rxq);
4206 for (i = 0; i < il->hw_params.max_txq_num; i++)
4207 il_txq_update_write_ptr(il, &il->txq[i]);
4208 il->isr_stats.wakeup++;
be663ab6
WYG		 4209 handled |= CSR_INT_BIT_WAKEUP;
4210 }
4211
4212 /* All uCode command responses, including Tx command responses,
4213 * Rx "responses" (frame-received notification), and other
4214 * notifications from uCode come through here*/
4215 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG		 4216 il4965_rx_handle(il);
4217 il->isr_stats.rx++;
be663ab6
WYG		 4218 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4219 }
4220
4221 /* This "Tx" DMA channel is used only for loading uCode */
4222 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 4223 D_ISR("uCode load interrupt\n");
46bc8d4b 4224 il->isr_stats.tx++;
be663ab6
WYG		 4225 handled |= CSR_INT_BIT_FH_TX;
4226 /* Wake up uCode load routine, now that load is complete */
46bc8d4b
SG		 4227 il->ucode_write_complete = 1;
4228 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4229 }
4230
4231 if (inta & ~handled) {
9406f797 4232 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 4233 il->isr_stats.unhandled++;
be663ab6
WYG		 4234 }
4235
46bc8d4b 4236 if (inta & ~(il->inta_mask)) {
9406f797 4237 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
46bc8d4b 4238 inta & ~il->inta_mask);
9406f797 4239 IL_WARN(" with FH_INT = 0x%08x\n", inta_fh);
be663ab6
WYG		 4240 }
4241
4242 /* Re-enable all interrupts */
93fd74e3 4243 /* only Re-enable if disabled by irq */
46bc8d4b
SG		 4244 if (test_bit(STATUS_INT_ENABLED, &il->status))
4245 il_enable_interrupts(il);
a078a1fd
SG		 4246 /* Re-enable RF_KILL if it occurred */
4247 else if (handled & CSR_INT_BIT_RF_KILL)
46bc8d4b 4248 il_enable_rfkill_int(il);
be663ab6 4249
d3175167 4250#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4251 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG		 4252 inta = _il_rd(il, CSR_INT);
4253 inta_mask = _il_rd(il, CSR_INT_MASK);
4254 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
58de00a4 4255 D_ISR(
be663ab6
WYG		 4256 "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4257 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4258 }
4259#endif
4260}
4261
4262/*****************************************************************************
4263 *
4264 * sysfs attributes
4265 *
4266 *****************************************************************************/
4267
d3175167 4268#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4269
4270/*
4271 * The following adds a new attribute to the sysfs representation
4272 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4273 * used for controlling the debug level.
4274 *
4275 * See the level definitions in iwl for details.
4276 *
4277 * The debug_level being managed using sysfs below is a per device debug
4278 * level that is used instead of the global debug level if it (the per
4279 * device debug level) is set.
4280 */
e2ebc833 4281static ssize_t il4965_show_debug_level(struct device *d,
be663ab6
WYG		 4282 struct device_attribute *attr, char *buf)
4283{
46bc8d4b
SG		 4284 struct il_priv *il = dev_get_drvdata(d);
4285 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
be663ab6 4286}
e2ebc833 4287static ssize_t il4965_store_debug_level(struct device *d,
be663ab6
WYG		 4288 struct device_attribute *attr,
4289 const char *buf, size_t count)
4290{
46bc8d4b 4291 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4292 unsigned long val;
4293 int ret;
4294
4295 ret = strict_strtoul(buf, 0, &val);
4296 if (ret)
9406f797 4297 IL_ERR("%s is not in hex or decimal form.\n", buf);
be663ab6 4298 else {
46bc8d4b
SG		 4299 il->debug_level = val;
4300 if (il_alloc_traffic_mem(il))
9406f797 4301 IL_ERR(
be663ab6
WYG		 4302 "Not enough memory to generate traffic log\n");
4303 }
4304 return strnlen(buf, count);
4305}
4306
4307static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
e2ebc833 4308 il4965_show_debug_level, il4965_store_debug_level);
be663ab6
WYG		 4309
4310
d3175167 4311#endif /* CONFIG_IWLEGACY_DEBUG */
be663ab6
WYG		 4312
4313
e2ebc833 4314static ssize_t il4965_show_temperature(struct device *d,
be663ab6
WYG		 4315 struct device_attribute *attr, char *buf)
4316{
46bc8d4b 4317 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4318
46bc8d4b 4319 if (!il_is_alive(il))
be663ab6
WYG		 4320 return -EAGAIN;
4321
46bc8d4b 4322 return sprintf(buf, "%d\n", il->temperature);
be663ab6
WYG		 4323}
4324
e2ebc833 4325static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
be663ab6 4326
e2ebc833 4327static ssize_t il4965_show_tx_power(struct device *d,
be663ab6
WYG		 4328 struct device_attribute *attr, char *buf)
4329{
46bc8d4b 4330 struct il_priv *il = dev_get_drvdata(d);
be663ab6 4331
46bc8d4b 4332 if (!il_is_ready_rf(il))
be663ab6
WYG		 4333 return sprintf(buf, "off\n");
4334 else
46bc8d4b 4335 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
be663ab6
WYG		 4336}
4337
e2ebc833 4338static ssize_t il4965_store_tx_power(struct device *d,
be663ab6
WYG		 4339 struct device_attribute *attr,
4340 const char *buf, size_t count)
4341{
46bc8d4b 4342 struct il_priv *il = dev_get_drvdata(d);
be663ab6
WYG		 4343 unsigned long val;
4344 int ret;
4345
4346 ret = strict_strtoul(buf, 10, &val);
4347 if (ret)
9406f797 4348 IL_INFO("%s is not in decimal form.\n", buf);
be663ab6 4349 else {
46bc8d4b 4350 ret = il_set_tx_power(il, val, false);
be663ab6 4351 if (ret)
9406f797 4352 IL_ERR("failed setting tx power (0x%d).\n",
be663ab6
WYG		 4353 ret);
4354 else
4355 ret = count;
4356 }
4357 return ret;
4358}
4359
4360static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO,
e2ebc833 4361 il4965_show_tx_power, il4965_store_tx_power);
be663ab6 4362
e2ebc833 4363static struct attribute *il_sysfs_entries[] = {
be663ab6
WYG		 4364 &dev_attr_temperature.attr,
4365 &dev_attr_tx_power.attr,
d3175167 4366#ifdef CONFIG_IWLEGACY_DEBUG
be663ab6
WYG		 4367 &dev_attr_debug_level.attr,
4368#endif
4369 NULL
4370};
4371
e2ebc833 4372static struct attribute_group il_attribute_group = {
be663ab6 4373 .name = NULL, /* put in device directory */
e2ebc833 4374 .attrs = il_sysfs_entries,
be663ab6
WYG		 4375};
4376
4377/******************************************************************************
4378 *
4379 * uCode download functions
4380 *
4381 ******************************************************************************/
4382
46bc8d4b 4383static void il4965_dealloc_ucode_pci(struct il_priv *il)
be663ab6 4384{
46bc8d4b
SG		 4385 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4386 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4387 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4388 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4389 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4390 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6
WYG		 4391}
4392
46bc8d4b 4393static void il4965_nic_start(struct il_priv *il)
be663ab6
WYG		 4394{
4395 /* Remove all resets to allow NIC to operate */
841b2cca 4396 _il_wr(il, CSR_RESET, 0);
be663ab6
WYG		 4397}
4398
e2ebc833 4399static void il4965_ucode_callback(const struct firmware *ucode_raw,
be663ab6 4400 void *context);
46bc8d4b 4401static int il4965_mac_setup_register(struct il_priv *il,
be663ab6
WYG		 4402 u32 max_probe_length);
4403
46bc8d4b 4404static int __must_check il4965_request_firmware(struct il_priv *il, bool first)
be663ab6 4405{
46bc8d4b 4406 const char *name_pre = il->cfg->fw_name_pre;
be663ab6
WYG		 4407 char tag[8];
4408
4409 if (first) {
0c2c8852
SG		 4410 il->fw_idx = il->cfg->ucode_api_max;
4411 sprintf(tag, "%d", il->fw_idx);
be663ab6 4412 } else {
0c2c8852
SG		 4413 il->fw_idx--;
4414 sprintf(tag, "%d", il->fw_idx);
be663ab6
WYG		 4415 }
4416
0c2c8852 4417 if (il->fw_idx < il->cfg->ucode_api_min) {
9406f797 4418 IL_ERR("no suitable firmware found!\n");
be663ab6
WYG		 4419 return -ENOENT;
4420 }
4421
46bc8d4b 4422 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
be663ab6 4423
58de00a4 4424 D_INFO("attempting to load firmware '%s'\n",
46bc8d4b 4425 il->firmware_name);
be663ab6 4426
46bc8d4b
SG		 4427 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4428 &il->pci_dev->dev, GFP_KERNEL, il,
e2ebc833 4429 il4965_ucode_callback);
be663ab6
WYG		 4430}
4431
e2ebc833 4432struct il4965_firmware_pieces {
be663ab6
WYG		 4433 const void *inst, *data, *init, *init_data, *boot;
4434 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4435};
4436
46bc8d4b 4437static int il4965_load_firmware(struct il_priv *il,
be663ab6 4438 const struct firmware *ucode_raw,
e2ebc833 4439 struct il4965_firmware_pieces *pieces)
be663ab6 4440{
e2ebc833 4441 struct il_ucode_header *ucode = (void *)ucode_raw->data;
be663ab6
WYG		 4442 u32 api_ver, hdr_size;
4443 const u8 *src;
4444
46bc8d4b
SG		 4445 il->ucode_ver = le32_to_cpu(ucode->ver);
4446 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4447
4448 switch (api_ver) {
4449 default:
4450 case 0:
4451 case 1:
4452 case 2:
4453 hdr_size = 24;
4454 if (ucode_raw->size < hdr_size) {
9406f797 4455 IL_ERR("File size too small!\n");
be663ab6
WYG		 4456 return -EINVAL;
4457 }
4458 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4459 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4460 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
4461 pieces->init_data_size =
4462 le32_to_cpu(ucode->v1.init_data_size);
4463 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4464 src = ucode->v1.data;
4465 break;
4466 }
4467
4468 /* Verify size of file vs. image size info in file's header */
4469 if (ucode_raw->size != hdr_size + pieces->inst_size +
4470 pieces->data_size + pieces->init_size +
4471 pieces->init_data_size + pieces->boot_size) {
4472
9406f797 4473 IL_ERR(
be663ab6
WYG		 4474 "uCode file size %d does not match expected size\n",
4475 (int)ucode_raw->size);
4476 return -EINVAL;
4477 }
4478
4479 pieces->inst = src;
4480 src += pieces->inst_size;
4481 pieces->data = src;
4482 src += pieces->data_size;
4483 pieces->init = src;
4484 src += pieces->init_size;
4485 pieces->init_data = src;
4486 src += pieces->init_data_size;
4487 pieces->boot = src;
4488 src += pieces->boot_size;
4489
4490 return 0;
4491}
4492
4493/**
e2ebc833 4494 * il4965_ucode_callback - callback when firmware was loaded
be663ab6
WYG		 4495 *
4496 * If loaded successfully, copies the firmware into buffers
4497 * for the card to fetch (via DMA).
4498 */
4499static void
e2ebc833 4500il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
be663ab6 4501{
46bc8d4b 4502 struct il_priv *il = context;
e2ebc833 4503 struct il_ucode_header *ucode;
be663ab6 4504 int err;
e2ebc833 4505 struct il4965_firmware_pieces pieces;
46bc8d4b
SG		 4506 const unsigned int api_max = il->cfg->ucode_api_max;
4507 const unsigned int api_min = il->cfg->ucode_api_min;
be663ab6
WYG		 4508 u32 api_ver;
4509
4510 u32 max_probe_length = 200;
4511 u32 standard_phy_calibration_size =
e2ebc833 4512 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
be663ab6
WYG		 4513
4514 memset(&pieces, 0, sizeof(pieces));
4515
4516 if (!ucode_raw) {
0c2c8852 4517 if (il->fw_idx <= il->cfg->ucode_api_max)
9406f797 4518 IL_ERR(
be663ab6 4519 "request for firmware file '%s' failed.\n",
46bc8d4b 4520 il->firmware_name);
be663ab6
WYG		 4521 goto try_again;
4522 }
4523
58de00a4 4524 D_INFO("Loaded firmware file '%s' (%zd bytes).\n",
46bc8d4b 4525 il->firmware_name, ucode_raw->size);
be663ab6
WYG		 4526
4527 /* Make sure that we got at least the API version number */
4528 if (ucode_raw->size < 4) {
9406f797 4529 IL_ERR("File size way too small!\n");
be663ab6
WYG		 4530 goto try_again;
4531 }
4532
4533 /* Data from ucode file: header followed by uCode images */
e2ebc833 4534 ucode = (struct il_ucode_header *)ucode_raw->data;
be663ab6 4535
46bc8d4b 4536 err = il4965_load_firmware(il, ucode_raw, &pieces);
be663ab6
WYG		 4537
4538 if (err)
4539 goto try_again;
4540
46bc8d4b 4541 api_ver = IL_UCODE_API(il->ucode_ver);
be663ab6
WYG		 4542
4543 /*
4544 * api_ver should match the api version forming part of the
4545 * firmware filename ... but we don't check for that and only rely
4546 * on the API version read from firmware header from here on forward
4547 */
4548 if (api_ver < api_min || api_ver > api_max) {
9406f797 4549 IL_ERR(
be663ab6
WYG		 4550 "Driver unable to support your firmware API. "
4551 "Driver supports v%u, firmware is v%u.\n",
4552 api_max, api_ver);
4553 goto try_again;
4554 }
4555
4556 if (api_ver != api_max)
9406f797 4557 IL_ERR(
be663ab6
WYG		 4558 "Firmware has old API version. Expected v%u, "
4559 "got v%u. New firmware can be obtained "
4560 "from http://www.intellinuxwireless.org.\n",
4561 api_max, api_ver);
4562
9406f797 4563 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
46bc8d4b
SG		 4564 IL_UCODE_MAJOR(il->ucode_ver),
4565 IL_UCODE_MINOR(il->ucode_ver),
4566 IL_UCODE_API(il->ucode_ver),
4567 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6 4568
46bc8d4b
SG		 4569 snprintf(il->hw->wiphy->fw_version,
4570 sizeof(il->hw->wiphy->fw_version),
be663ab6 4571 "%u.%u.%u.%u",
46bc8d4b
SG		 4572 IL_UCODE_MAJOR(il->ucode_ver),
4573 IL_UCODE_MINOR(il->ucode_ver),
4574 IL_UCODE_API(il->ucode_ver),
4575 IL_UCODE_SERIAL(il->ucode_ver));
be663ab6
WYG		 4576
4577 /*
4578 * For any of the failures below (before allocating pci memory)
4579 * we will try to load a version with a smaller API -- maybe the
4580 * user just got a corrupted version of the latest API.
4581 */
4582
58de00a4 4583 D_INFO("f/w package hdr ucode version raw = 0x%x\n",
46bc8d4b 4584 il->ucode_ver);
58de00a4 4585 D_INFO("f/w package hdr runtime inst size = %Zd\n",
be663ab6 4586 pieces.inst_size);
58de00a4 4587 D_INFO("f/w package hdr runtime data size = %Zd\n",
be663ab6 4588 pieces.data_size);
58de00a4 4589 D_INFO("f/w package hdr init inst size = %Zd\n",
be663ab6 4590 pieces.init_size);
58de00a4 4591 D_INFO("f/w package hdr init data size = %Zd\n",
be663ab6 4592 pieces.init_data_size);
58de00a4 4593 D_INFO("f/w package hdr boot inst size = %Zd\n",
be663ab6
WYG		 4594 pieces.boot_size);
4595
4596 /* Verify that uCode images will fit in card's SRAM */
46bc8d4b 4597 if (pieces.inst_size > il->hw_params.max_inst_size) {
9406f797 4598 IL_ERR("uCode instr len %Zd too large to fit in\n",
be663ab6
WYG		 4599 pieces.inst_size);
4600 goto try_again;
4601 }
4602
46bc8d4b 4603 if (pieces.data_size > il->hw_params.max_data_size) {
9406f797 4604 IL_ERR("uCode data len %Zd too large to fit in\n",
be663ab6
WYG		 4605 pieces.data_size);
4606 goto try_again;
4607 }
4608
46bc8d4b 4609 if (pieces.init_size > il->hw_params.max_inst_size) {
9406f797 4610 IL_ERR("uCode init instr len %Zd too large to fit in\n",
be663ab6
WYG		 4611 pieces.init_size);
4612 goto try_again;
4613 }
4614
46bc8d4b 4615 if (pieces.init_data_size > il->hw_params.max_data_size) {
9406f797 4616 IL_ERR("uCode init data len %Zd too large to fit in\n",
be663ab6
WYG		 4617 pieces.init_data_size);
4618 goto try_again;
4619 }
4620
46bc8d4b 4621 if (pieces.boot_size > il->hw_params.max_bsm_size) {
9406f797 4622 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
be663ab6
WYG		 4623 pieces.boot_size);
4624 goto try_again;
4625 }
4626
4627 /* Allocate ucode buffers for card's bus-master loading ... */
4628
4629 /* Runtime instructions and 2 copies of data:
4630 * 1) unmodified from disk
4631 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG		 4632 il->ucode_code.len = pieces.inst_size;
4633 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
be663ab6 4634
46bc8d4b
SG		 4635 il->ucode_data.len = pieces.data_size;
4636 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
be663ab6 4637
46bc8d4b
SG		 4638 il->ucode_data_backup.len = pieces.data_size;
4639 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
be663ab6 4640
46bc8d4b
SG		 4641 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4642 !il->ucode_data_backup.v_addr)
be663ab6
WYG		 4643 goto err_pci_alloc;
4644
4645 /* Initialization instructions and data */
4646 if (pieces.init_size && pieces.init_data_size) {
46bc8d4b
SG		 4647 il->ucode_init.len = pieces.init_size;
4648 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
be663ab6 4649
46bc8d4b
SG		 4650 il->ucode_init_data.len = pieces.init_data_size;
4651 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
be663ab6 4652
46bc8d4b 4653 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
be663ab6
WYG		 4654 goto err_pci_alloc;
4655 }
4656
4657 /* Bootstrap (instructions only, no data) */
4658 if (pieces.boot_size) {
46bc8d4b
SG		 4659 il->ucode_boot.len = pieces.boot_size;
4660 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
be663ab6 4661
46bc8d4b 4662 if (!il->ucode_boot.v_addr)
be663ab6
WYG		 4663 goto err_pci_alloc;
4664 }
4665
4666 /* Now that we can no longer fail, copy information */
4667
46bc8d4b 4668 il->sta_key_max_num = STA_KEY_MAX_NUM;
be663ab6
WYG		 4669
4670 /* Copy images into buffers for card's bus-master reads ... */
4671
4672 /* Runtime instructions (first block of data in file) */
58de00a4 4673 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
be663ab6 4674 pieces.inst_size);
46bc8d4b 4675 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
be663ab6 4676
58de00a4 4677 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
46bc8d4b 4678 il->ucode_code.v_addr, (u32)il->ucode_code.p_addr);
be663ab6
WYG		 4679
4680 /*
4681 * Runtime data
e2ebc833 4682 * NOTE: Copy into backup buffer will be done in il_up()
be663ab6 4683 */
58de00a4 4684 D_INFO("Copying (but not loading) uCode data len %Zd\n",
be663ab6 4685 pieces.data_size);
46bc8d4b
SG		 4686 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4687 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
be663ab6
WYG		 4688
4689 /* Initialization instructions */
4690 if (pieces.init_size) {
58de00a4 4691 D_INFO(
be663ab6
WYG		 4692 "Copying (but not loading) init instr len %Zd\n",
4693 pieces.init_size);
46bc8d4b 4694 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
be663ab6
WYG		 4695 }
4696
4697 /* Initialization data */
4698 if (pieces.init_data_size) {
58de00a4 4699 D_INFO(
be663ab6
WYG		 4700 "Copying (but not loading) init data len %Zd\n",
4701 pieces.init_data_size);
46bc8d4b 4702 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
be663ab6
WYG		 4703 pieces.init_data_size);
4704 }
4705
4706 /* Bootstrap instructions */
58de00a4 4707 D_INFO("Copying (but not loading) boot instr len %Zd\n",
be663ab6 4708 pieces.boot_size);
46bc8d4b 4709 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
be663ab6
WYG		 4710
4711 /*
4712 * figure out the offset of chain noise reset and gain commands
4713 * base on the size of standard phy calibration commands table size
4714 */
46bc8d4b 4715 il->_4965.phy_calib_chain_noise_reset_cmd =
be663ab6 4716 standard_phy_calibration_size;
46bc8d4b 4717 il->_4965.phy_calib_chain_noise_gain_cmd =
be663ab6
WYG		 4718 standard_phy_calibration_size + 1;
4719
4720 /**************************************************
4721 * This is still part of probe() in a sense...
4722 *
4723 * 9. Setup and register with mac80211 and debugfs
4724 **************************************************/
46bc8d4b 4725 err = il4965_mac_setup_register(il, max_probe_length);
be663ab6
WYG		 4726 if (err)
4727 goto out_unbind;
4728
46bc8d4b 4729 err = il_dbgfs_register(il, DRV_NAME);
be663ab6 4730 if (err)
9406f797 4731 IL_ERR(
be663ab6
WYG		 4732 "failed to create debugfs files. Ignoring error: %d\n", err);
4733
46bc8d4b 4734 err = sysfs_create_group(&il->pci_dev->dev.kobj,
e2ebc833 4735 &il_attribute_group);
be663ab6 4736 if (err) {
9406f797 4737 IL_ERR("failed to create sysfs device attributes\n");
be663ab6
WYG		 4738 goto out_unbind;
4739 }
4740
4741 /* We have our copies now, allow OS release its copies */
4742 release_firmware(ucode_raw);
46bc8d4b 4743 complete(&il->_4965.firmware_loading_complete);
be663ab6
WYG		 4744 return;
4745
4746 try_again:
4747 /* try next, if any */
46bc8d4b 4748 if (il4965_request_firmware(il, false))
be663ab6
WYG		 4749 goto out_unbind;
4750 release_firmware(ucode_raw);
4751 return;
4752
4753 err_pci_alloc:
9406f797 4754 IL_ERR("failed to allocate pci memory\n");
46bc8d4b 4755 il4965_dealloc_ucode_pci(il);
be663ab6 4756 out_unbind:
46bc8d4b
SG		 4757 complete(&il->_4965.firmware_loading_complete);
4758 device_release_driver(&il->pci_dev->dev);
be663ab6
WYG		 4759 release_firmware(ucode_raw);
4760}
4761
4762static const char * const desc_lookup_text[] = {
4763 "OK",
4764 "FAIL",
4765 "BAD_PARAM",
4766 "BAD_CHECKSUM",
4767 "NMI_INTERRUPT_WDG",
4768 "SYSASSERT",
4769 "FATAL_ERROR",
4770 "BAD_COMMAND",
4771 "HW_ERROR_TUNE_LOCK",
4772 "HW_ERROR_TEMPERATURE",
4773 "ILLEGAL_CHAN_FREQ",
3b98c7f4 4774 "VCC_NOT_STBL",
be663ab6
WYG		 4775 "FH_ERROR",
4776 "NMI_INTERRUPT_HOST",
4777 "NMI_INTERRUPT_ACTION_PT",
4778 "NMI_INTERRUPT_UNKNOWN",
4779 "UCODE_VERSION_MISMATCH",
4780 "HW_ERROR_ABS_LOCK",
4781 "HW_ERROR_CAL_LOCK_FAIL",
4782 "NMI_INTERRUPT_INST_ACTION_PT",
4783 "NMI_INTERRUPT_DATA_ACTION_PT",
4784 "NMI_TRM_HW_ER",
4785 "NMI_INTERRUPT_TRM",
861d9c3f 4786 "NMI_INTERRUPT_BREAK_POINT",
be663ab6
WYG		 4787 "DEBUG_0",
4788 "DEBUG_1",
4789 "DEBUG_2",
4790 "DEBUG_3",
4791};
4792
4793static struct { char *name; u8 num; } advanced_lookup[] = {
4794 { "NMI_INTERRUPT_WDG", 0x34 },
4795 { "SYSASSERT", 0x35 },
4796 { "UCODE_VERSION_MISMATCH", 0x37 },
4797 { "BAD_COMMAND", 0x38 },
4798 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
4799 { "FATAL_ERROR", 0x3D },
4800 { "NMI_TRM_HW_ERR", 0x46 },
4801 { "NMI_INTERRUPT_TRM", 0x4C },
4802 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
4803 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
4804 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
4805 { "NMI_INTERRUPT_HOST", 0x66 },
4806 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
4807 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
4808 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
4809 { "ADVANCED_SYSASSERT", 0 },
4810};
4811
e2ebc833 4812static const char *il4965_desc_lookup(u32 num)
be663ab6
WYG		 4813{
4814 int i;
4815 int max = ARRAY_SIZE(desc_lookup_text);
4816
4817 if (num < max)
4818 return desc_lookup_text[num];
4819
4820 max = ARRAY_SIZE(advanced_lookup) - 1;
4821 for (i = 0; i < max; i++) {
4822 if (advanced_lookup[i].num == num)
4823 break;
4824 }
4825 return advanced_lookup[i].name;
4826}
4827
4828#define ERROR_START_OFFSET (1 * sizeof(u32))
4829#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4830
46bc8d4b 4831void il4965_dump_nic_error_log(struct il_priv *il)
be663ab6
WYG		 4832{
4833 u32 data2, line;
4834 u32 desc, time, count, base, data1;
4835 u32 blink1, blink2, ilink1, ilink2;
4836 u32 pc, hcmd;
4837
46bc8d4b
SG		 4838 if (il->ucode_type == UCODE_INIT) {
4839 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
be663ab6 4840 } else {
46bc8d4b 4841 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
be663ab6
WYG		 4842 }
4843
46bc8d4b 4844 if (!il->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
9406f797 4845 IL_ERR(
be663ab6 4846 "Not valid error log pointer 0x%08X for %s uCode\n",
46bc8d4b 4847 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
be663ab6
WYG		 4848 return;
4849 }
4850
46bc8d4b 4851 count = il_read_targ_mem(il, base);
be663ab6
WYG		 4852
4853 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797
SG		 4854 IL_ERR("Start IWL Error Log Dump:\n");
4855 IL_ERR("Status: 0x%08lX, count: %d\n",
46bc8d4b
SG		 4856 il->status, count);
4857 }
4858
4859 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
4860 il->isr_stats.err_code = desc;
4861 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
4862 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
4863 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
4864 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
4865 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
4866 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
4867 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
4868 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
4869 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
4870 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
4871
9406f797 4872 IL_ERR("Desc Time "
be663ab6 4873 "data1 data2 line\n");
9406f797 4874 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
e2ebc833 4875 il4965_desc_lookup(desc), desc, time, data1, data2, line);
9406f797
SG		 4876 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
4877 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
be663ab6
WYG		 4878 pc, blink1, blink2, ilink1, ilink2, hcmd);
4879}
4880
46bc8d4b 4881static void il4965_rf_kill_ct_config(struct il_priv *il)
be663ab6 4882{
e2ebc833 4883 struct il_ct_kill_config cmd;
be663ab6
WYG		 4884 unsigned long flags;
4885 int ret = 0;
4886
46bc8d4b 4887 spin_lock_irqsave(&il->lock, flags);
841b2cca 4888 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
be663ab6 4889 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
46bc8d4b 4890 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 4891
4892 cmd.critical_temperature_R =
46bc8d4b 4893 cpu_to_le32(il->hw_params.ct_kill_threshold);
be663ab6 4894
46bc8d4b 4895 ret = il_send_cmd_pdu(il, REPLY_CT_KILL_CONFIG_CMD,
be663ab6
WYG		 4896 sizeof(cmd), &cmd);
4897 if (ret)
9406f797 4898 IL_ERR("REPLY_CT_KILL_CONFIG_CMD failed\n");
be663ab6 4899 else
58de00a4 4900 D_INFO("REPLY_CT_KILL_CONFIG_CMD "
be663ab6
WYG		 4901 "succeeded, "
4902 "critical temperature is %d\n",
46bc8d4b 4903 il->hw_params.ct_kill_threshold);
be663ab6
WYG		 4904}
4905
4906static const s8 default_queue_to_tx_fifo[] = {
e2ebc833
SG		 4907 IL_TX_FIFO_VO,
4908 IL_TX_FIFO_VI,
4909 IL_TX_FIFO_BE,
4910 IL_TX_FIFO_BK,
d3175167 4911 IL49_CMD_FIFO_NUM,
e2ebc833
SG		 4912 IL_TX_FIFO_UNUSED,
4913 IL_TX_FIFO_UNUSED,
be663ab6
WYG		 4914};
4915
46bc8d4b 4916static int il4965_alive_notify(struct il_priv *il)
be663ab6
WYG		 4917{
4918 u32 a;
4919 unsigned long flags;
4920 int i, chan;
4921 u32 reg_val;
4922
46bc8d4b 4923 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 4924
4925 /* Clear 4965's internal Tx Scheduler data base */
db54eb57 4926 il->scd_base_addr = il_rd_prph(il,
d3175167
SG		 4927 IL49_SCD_SRAM_BASE_ADDR);
4928 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
4929 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
46bc8d4b 4930 il_write_targ_mem(il, a, 0);
d3175167 4931 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
46bc8d4b
SG		 4932 il_write_targ_mem(il, a, 0);
4933 for (; a < il->scd_base_addr +
d3175167 4934 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); a += 4)
46bc8d4b 4935 il_write_targ_mem(il, a, 0);
be663ab6
WYG		 4936
4937 /* Tel 4965 where to find Tx byte count tables */
d3175167 4938 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR,
46bc8d4b 4939 il->scd_bc_tbls.dma >> 10);
be663ab6
WYG		 4940
4941 /* Enable DMA channel */
4942 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
0c1a94e2 4943 il_wr(il,
be663ab6
WYG		 4944 FH_TCSR_CHNL_TX_CONFIG_REG(chan),
4945 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
4946 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
4947
4948 /* Update FH chicken bits */
0c1a94e2
SG		 4949 reg_val = il_rd(il, FH_TX_CHICKEN_BITS_REG);
4950 il_wr(il, FH_TX_CHICKEN_BITS_REG,
be663ab6
WYG		 4951 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
4952
4953 /* Disable chain mode for all queues */
d3175167 4954 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
be663ab6
WYG		 4955
4956 /* Initialize each Tx queue (including the command queue) */
46bc8d4b 4957 for (i = 0; i < il->hw_params.max_txq_num; i++) {
be663ab6 4958
0c2c8852 4959 /* TFD circular buffer read/write idxes */
d3175167 4960 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
0c1a94e2 4961 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
be663ab6
WYG		 4962
4963 /* Max Tx Window size for Scheduler-ACK mode */
46bc8d4b 4964 il_write_targ_mem(il, il->scd_base_addr +
d3175167 4965 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
be663ab6 4966 (SCD_WIN_SIZE <<
d3175167
SG		 4967 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4968 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
be663ab6
WYG		 4969
4970 /* Frame limit */
46bc8d4b 4971 il_write_targ_mem(il, il->scd_base_addr +
d3175167 4972 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
be663ab6
WYG		 4973 sizeof(u32),
4974 (SCD_FRAME_LIMIT <<
d3175167
SG		 4975 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
4976 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
be663ab6
WYG		 4977
4978 }
d3175167 4979 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
46bc8d4b 4980 (1 << il->hw_params.max_txq_num) - 1);
be663ab6
WYG		 4981
4982 /* Activate all Tx DMA/FIFO channels */
46bc8d4b 4983 il4965_txq_set_sched(il, IL_MASK(0, 6));
be663ab6 4984
46bc8d4b 4985 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
be663ab6
WYG		 4986
4987 /* make sure all queue are not stopped */
46bc8d4b 4988 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
be663ab6 4989 for (i = 0; i < 4; i++)
46bc8d4b 4990 atomic_set(&il->queue_stop_count[i], 0);
be663ab6
WYG		 4991
4992 /* reset to 0 to enable all the queue first */
46bc8d4b 4993 il->txq_ctx_active_msk = 0;
be663ab6
WYG		 4994 /* Map each Tx/cmd queue to its corresponding fifo */
4995 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
4996
4997 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
4998 int ac = default_queue_to_tx_fifo[i];
4999
46bc8d4b 5000 il_txq_ctx_activate(il, i);
be663ab6 5001
e2ebc833 5002 if (ac == IL_TX_FIFO_UNUSED)
be663ab6
WYG		 5003 continue;
5004
46bc8d4b 5005 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
be663ab6
WYG		 5006 }
5007
46bc8d4b 5008 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5009
5010 return 0;
5011}
5012
5013/**
e2ebc833 5014 * il4965_alive_start - called after REPLY_ALIVE notification received
be663ab6 5015 * from protocol/runtime uCode (initialization uCode's
e2ebc833 5016 * Alive gets handled by il_init_alive_start()).
be663ab6 5017 */
46bc8d4b 5018static void il4965_alive_start(struct il_priv *il)
be663ab6
WYG		 5019{
5020 int ret = 0;
7c2cde2e 5021 struct il_rxon_context *ctx = &il->ctx;
be663ab6 5022
58de00a4 5023 D_INFO("Runtime Alive received.\n");
be663ab6 5024
46bc8d4b 5025 if (il->card_alive.is_valid != UCODE_VALID_OK) {
be663ab6
WYG		 5026 /* We had an error bringing up the hardware, so take it
5027 * all the way back down so we can try again */
58de00a4 5028 D_INFO("Alive failed.\n");
be663ab6
WYG		 5029 goto restart;
5030 }
5031
5032 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5033 * This is a paranoid check, because we would not have gotten the
5034 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 5035 if (il4965_verify_ucode(il)) {
be663ab6
WYG		 5036 /* Runtime instruction load was bad;
5037 * take it all the way back down so we can try again */
58de00a4 5038 D_INFO("Bad runtime uCode load.\n");
be663ab6
WYG		 5039 goto restart;
5040 }
5041
46bc8d4b 5042 ret = il4965_alive_notify(il);
be663ab6 5043 if (ret) {
9406f797 5044 IL_WARN(
be663ab6
WYG		 5045 "Could not complete ALIVE transition [ntf]: %d\n", ret);
5046 goto restart;
5047 }
5048
5049
5050 /* After the ALIVE response, we can send host commands to the uCode */
46bc8d4b 5051 set_bit(STATUS_ALIVE, &il->status);
be663ab6
WYG		 5052
5053 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 5054 il_setup_watchdog(il);
be663ab6 5055
46bc8d4b 5056 if (il_is_rfkill(il))
be663ab6
WYG		 5057 return;
5058
46bc8d4b 5059 ieee80211_wake_queues(il->hw);
be663ab6 5060
2eb05816 5061 il->active_rate = RATES_MASK;
be663ab6 5062
e2ebc833
SG		 5063 if (il_is_associated_ctx(ctx)) {
5064 struct il_rxon_cmd *active_rxon =
5065 (struct il_rxon_cmd *)&ctx->active;
be663ab6
WYG		 5066 /* apply any changes in staging */
5067 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
5068 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5069 } else {
be663ab6 5070 /* Initialize our rx_config data */
17d6e557 5071 il_connection_init_rx_config(il, &il->ctx);
be663ab6 5072
46bc8d4b
SG		 5073 if (il->cfg->ops->hcmd->set_rxon_chain)
5074 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6
WYG		 5075 }
5076
5077 /* Configure bluetooth coexistence if enabled */
46bc8d4b 5078 il_send_bt_config(il);
be663ab6 5079
46bc8d4b 5080 il4965_reset_run_time_calib(il);
be663ab6 5081
46bc8d4b 5082 set_bit(STATUS_READY, &il->status);
be663ab6
WYG		 5083
5084 /* Configure the adapter for unassociated operation */
46bc8d4b 5085 il_commit_rxon(il, ctx);
be663ab6
WYG		 5086
5087 /* At this point, the NIC is initialized and operational */
46bc8d4b 5088 il4965_rf_kill_ct_config(il);
be663ab6 5089
58de00a4 5090 D_INFO("ALIVE processing complete.\n");
46bc8d4b 5091 wake_up(&il->wait_command_queue);
be663ab6 5092
46bc8d4b 5093 il_power_update_mode(il, true);
58de00a4 5094 D_INFO("Updated power mode\n");
be663ab6
WYG		 5095
5096 return;
5097
5098 restart:
46bc8d4b 5099 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 5100}
5101
46bc8d4b 5102static void il4965_cancel_deferred_work(struct il_priv *il);
be663ab6 5103
46bc8d4b 5104static void __il4965_down(struct il_priv *il)
be663ab6
WYG		 5105{
5106 unsigned long flags;
ab42b404 5107 int exit_pending;
be663ab6 5108
58de00a4 5109 D_INFO(DRV_NAME " is going down\n");
be663ab6 5110
46bc8d4b 5111 il_scan_cancel_timeout(il, 200);
be663ab6 5112
46bc8d4b 5113 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &il->status);
be663ab6
WYG		 5114
5115 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
5116 * to prevent rearm timer */
46bc8d4b 5117 del_timer_sync(&il->watchdog);
be663ab6 5118
46bc8d4b
SG		 5119 il_clear_ucode_stations(il, NULL);
5120 il_dealloc_bcast_stations(il);
5121 il_clear_driver_stations(il);
be663ab6
WYG		 5122
5123 /* Unblock any waiting calls */
46bc8d4b 5124 wake_up_all(&il->wait_command_queue);
be663ab6
WYG		 5125
5126 /* Wipe out the EXIT_PENDING status bit if we are not actually
5127 * exiting the module */
5128 if (!exit_pending)
46bc8d4b 5129 clear_bit(STATUS_EXIT_PENDING, &il->status);
be663ab6
WYG		 5130
5131 /* stop and reset the on-board processor */
841b2cca 5132 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6
WYG		 5133
5134 /* tell the device to stop sending interrupts */
46bc8d4b
SG		 5135 spin_lock_irqsave(&il->lock, flags);
5136 il_disable_interrupts(il);
5137 spin_unlock_irqrestore(&il->lock, flags);
5138 il4965_synchronize_irq(il);
be663ab6 5139
46bc8d4b
SG		 5140 if (il->mac80211_registered)
5141 ieee80211_stop_queues(il->hw);
be663ab6 5142
e2ebc833 5143 /* If we have not previously called il_init() then
be663ab6 5144 * clear all bits but the RF Kill bit and return */
46bc8d4b
SG		 5145 if (!il_is_init(il)) {
5146 il->status = test_bit(STATUS_RF_KILL_HW, &il->status) <<
be663ab6 5147 STATUS_RF_KILL_HW |
46bc8d4b 5148 test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
be663ab6 5149 STATUS_GEO_CONFIGURED |
46bc8d4b 5150 test_bit(STATUS_EXIT_PENDING, &il->status) <<
be663ab6
WYG		 5151 STATUS_EXIT_PENDING;
5152 goto exit;
5153 }
5154
5155 /* ...otherwise clear out all the status bits but the RF Kill
5156 * bit and continue taking the NIC down. */
46bc8d4b 5157 il->status &= test_bit(STATUS_RF_KILL_HW, &il->status) <<
be663ab6 5158 STATUS_RF_KILL_HW |
46bc8d4b 5159 test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
be663ab6 5160 STATUS_GEO_CONFIGURED |
46bc8d4b 5161 test_bit(STATUS_FW_ERROR, &il->status) <<
be663ab6 5162 STATUS_FW_ERROR |
46bc8d4b 5163 test_bit(STATUS_EXIT_PENDING, &il->status) <<
be663ab6
WYG		 5164 STATUS_EXIT_PENDING;
5165
46bc8d4b
SG		 5166 il4965_txq_ctx_stop(il);
5167 il4965_rxq_stop(il);
be663ab6
WYG		 5168
5169 /* Power-down device's busmaster DMA clocks */
db54eb57 5170 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 5171 udelay(5);
5172
5173 /* Make sure (redundant) we've released our request to stay awake */
46bc8d4b 5174 il_clear_bit(il, CSR_GP_CNTRL,
be663ab6
WYG		 5175 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5176
5177 /* Stop the device, and put it in low power state */
46bc8d4b 5178 il_apm_stop(il);
be663ab6
WYG		 5179
5180 exit:
46bc8d4b 5181 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
be663ab6 5182
46bc8d4b
SG		 5183 dev_kfree_skb(il->beacon_skb);
5184 il->beacon_skb = NULL;
be663ab6
WYG		 5185
5186 /* clear out any free frames */
46bc8d4b 5187 il4965_clear_free_frames(il);
be663ab6
WYG		 5188}
5189
46bc8d4b 5190static void il4965_down(struct il_priv *il)
be663ab6 5191{
46bc8d4b
SG		 5192 mutex_lock(&il->mutex);
5193 __il4965_down(il);
5194 mutex_unlock(&il->mutex);
be663ab6 5195
46bc8d4b 5196 il4965_cancel_deferred_work(il);
be663ab6
WYG		 5197}
5198
5199#define HW_READY_TIMEOUT (50)
5200
46bc8d4b 5201static int il4965_set_hw_ready(struct il_priv *il)
be663ab6
WYG		 5202{
5203 int ret = 0;
5204
46bc8d4b 5205 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
be663ab6
WYG		 5206 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
5207
5208 /* See if we got it */
142b343f 5209 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
be663ab6
WYG		 5210 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5211 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5212 HW_READY_TIMEOUT);
5213 if (ret != -ETIMEDOUT)
46bc8d4b 5214 il->hw_ready = true;
be663ab6 5215 else
46bc8d4b 5216 il->hw_ready = false;
be663ab6 5217
58de00a4 5218 D_INFO("hardware %s\n",
46bc8d4b 5219 (il->hw_ready == 1) ? "ready" : "not ready");
be663ab6
WYG		 5220 return ret;
5221}
5222
46bc8d4b 5223static int il4965_prepare_card_hw(struct il_priv *il)
be663ab6
WYG		 5224{
5225 int ret = 0;
5226
58de00a4 5227 D_INFO("il4965_prepare_card_hw enter\n");
be663ab6 5228
46bc8d4b
SG		 5229 ret = il4965_set_hw_ready(il);
5230 if (il->hw_ready)
be663ab6
WYG		 5231 return ret;
5232
5233 /* If HW is not ready, prepare the conditions to check again */
46bc8d4b 5234 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
be663ab6
WYG		 5235 CSR_HW_IF_CONFIG_REG_PREPARE);
5236
142b343f 5237 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
be663ab6
WYG		 5238 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5239 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
5240
5241 /* HW should be ready by now, check again. */
5242 if (ret != -ETIMEDOUT)
46bc8d4b 5243 il4965_set_hw_ready(il);
be663ab6
WYG		 5244
5245 return ret;
5246}
5247
5248#define MAX_HW_RESTARTS 5
5249
46bc8d4b 5250static int __il4965_up(struct il_priv *il)
be663ab6 5251{
be663ab6
WYG		 5252 int i;
5253 int ret;
5254
46bc8d4b 5255 if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
9406f797 5256 IL_WARN("Exit pending; will not bring the NIC up\n");
be663ab6
WYG		 5257 return -EIO;
5258 }
5259
46bc8d4b 5260 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 5261 IL_ERR("ucode not available for device bringup\n");
be663ab6
WYG		 5262 return -EIO;
5263 }
5264
17d6e557
SG		 5265 ret = il4965_alloc_bcast_station(il, &il->ctx);
5266 if (ret) {
5267 il_dealloc_bcast_stations(il);
5268 return ret;
be663ab6
WYG		 5269 }
5270
46bc8d4b 5271 il4965_prepare_card_hw(il);
be663ab6 5272
46bc8d4b 5273 if (!il->hw_ready) {
9406f797 5274 IL_WARN("Exit HW not ready\n");
be663ab6
WYG		 5275 return -EIO;
5276 }
5277
5278 /* If platform's RF_KILL switch is NOT set to KILL */
841b2cca 5279 if (_il_rd(il,
be663ab6 5280 CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
46bc8d4b 5281 clear_bit(STATUS_RF_KILL_HW, &il->status);
be663ab6 5282 else
46bc8d4b 5283 set_bit(STATUS_RF_KILL_HW, &il->status);
be663ab6 5284
46bc8d4b
SG		 5285 if (il_is_rfkill(il)) {
5286 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
be663ab6 5287
46bc8d4b 5288 il_enable_interrupts(il);
9406f797 5289 IL_WARN("Radio disabled by HW RF Kill switch\n");
be663ab6
WYG		 5290 return 0;
5291 }
5292
841b2cca 5293 _il_wr(il, CSR_INT, 0xFFFFFFFF);
be663ab6 5294
e2ebc833 5295 /* must be initialised before il_hw_nic_init */
46bc8d4b 5296 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
be663ab6 5297
46bc8d4b 5298 ret = il4965_hw_nic_init(il);
be663ab6 5299 if (ret) {
9406f797 5300 IL_ERR("Unable to init nic\n");
be663ab6
WYG		 5301 return ret;
5302 }
5303
5304 /* make sure rfkill handshake bits are cleared */
841b2cca
SG		 5305 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5306 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
be663ab6
WYG		 5307 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5308
5309 /* clear (again), then enable host interrupts */
841b2cca 5310 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5311 il_enable_interrupts(il);
be663ab6
WYG		 5312
5313 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG		 5314 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5315 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
be663ab6
WYG		 5316
5317 /* Copy original ucode data image from disk into backup cache.
5318 * This will be used to initialize the on-board processor's
5319 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG		 5320 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5321 il->ucode_data.len);
be663ab6
WYG		 5322
5323 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5324
5325 /* load bootstrap state machine,
5326 * load bootstrap program into processor's memory,
5327 * prepare to load the "initialize" uCode */
46bc8d4b 5328 ret = il->cfg->ops->lib->load_ucode(il);
be663ab6
WYG		 5329
5330 if (ret) {
9406f797 5331 IL_ERR("Unable to set up bootstrap uCode: %d\n",
be663ab6
WYG		 5332 ret);
5333 continue;
5334 }
5335
5336 /* start card; "initialize" will load runtime ucode */
46bc8d4b 5337 il4965_nic_start(il);
be663ab6 5338
58de00a4 5339 D_INFO(DRV_NAME " is coming up\n");
be663ab6
WYG		 5340
5341 return 0;
5342 }
5343
46bc8d4b
SG		 5344 set_bit(STATUS_EXIT_PENDING, &il->status);
5345 __il4965_down(il);
5346 clear_bit(STATUS_EXIT_PENDING, &il->status);
be663ab6
WYG		 5347
5348 /* tried to restart and config the device for as long as our
5349 * patience could withstand */
9406f797 5350 IL_ERR("Unable to initialize device after %d attempts.\n", i);
be663ab6
WYG		 5351 return -EIO;
5352}
5353
5354
5355/*****************************************************************************
5356 *
5357 * Workqueue callbacks
5358 *
5359 *****************************************************************************/
5360
e2ebc833 5361static void il4965_bg_init_alive_start(struct work_struct *data)
be663ab6 5362{
46bc8d4b 5363 struct il_priv *il =
e2ebc833 5364 container_of(data, struct il_priv, init_alive_start.work);
be663ab6 5365
46bc8d4b
SG		 5366 mutex_lock(&il->mutex);
5367 if (test_bit(STATUS_EXIT_PENDING, &il->status))
28a6e577 5368 goto out;
be663ab6 5369
46bc8d4b 5370 il->cfg->ops->lib->init_alive_start(il);
28a6e577 5371out:
46bc8d4b 5372 mutex_unlock(&il->mutex);
be663ab6
WYG		 5373}
5374
e2ebc833 5375static void il4965_bg_alive_start(struct work_struct *data)
be663ab6 5376{
46bc8d4b 5377 struct il_priv *il =
e2ebc833 5378 container_of(data, struct il_priv, alive_start.work);
be663ab6 5379
46bc8d4b
SG		 5380 mutex_lock(&il->mutex);
5381 if (test_bit(STATUS_EXIT_PENDING, &il->status))
28a6e577 5382 goto out;
be663ab6 5383
46bc8d4b 5384 il4965_alive_start(il);
28a6e577 5385out:
46bc8d4b 5386 mutex_unlock(&il->mutex);
be663ab6
WYG		 5387}
5388
e2ebc833 5389static void il4965_bg_run_time_calib_work(struct work_struct *work)
be663ab6 5390{
46bc8d4b 5391 struct il_priv *il = container_of(work, struct il_priv,
be663ab6
WYG		 5392 run_time_calib_work);
5393
46bc8d4b 5394 mutex_lock(&il->mutex);
be663ab6 5395
46bc8d4b
SG		 5396 if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
5397 test_bit(STATUS_SCANNING, &il->status)) {
5398 mutex_unlock(&il->mutex);
be663ab6
WYG		 5399 return;
5400 }
5401
46bc8d4b
SG		 5402 if (il->start_calib) {
5403 il4965_chain_noise_calibration(il,
ebf0d90d 5404 (void *)&il->_4965.stats);
46bc8d4b 5405 il4965_sensitivity_calibration(il,
ebf0d90d 5406 (void *)&il->_4965.stats);
be663ab6
WYG		 5407 }
5408
46bc8d4b 5409 mutex_unlock(&il->mutex);
be663ab6
WYG		 5410}
5411
e2ebc833 5412static void il4965_bg_restart(struct work_struct *data)
be663ab6 5413{
46bc8d4b 5414 struct il_priv *il = container_of(data, struct il_priv, restart);
be663ab6 5415
46bc8d4b 5416 if (test_bit(STATUS_EXIT_PENDING, &il->status))
be663ab6
WYG		 5417 return;
5418
46bc8d4b 5419 if (test_and_clear_bit(STATUS_FW_ERROR, &il->status)) {
46bc8d4b 5420 mutex_lock(&il->mutex);
17d6e557 5421 il->ctx.vif = NULL;
46bc8d4b 5422 il->is_open = 0;
be663ab6 5423
46bc8d4b 5424 __il4965_down(il);
be663ab6 5425
46bc8d4b
SG		 5426 mutex_unlock(&il->mutex);
5427 il4965_cancel_deferred_work(il);
5428 ieee80211_restart_hw(il->hw);
be663ab6 5429 } else {
46bc8d4b 5430 il4965_down(il);
be663ab6 5431
46bc8d4b
SG		 5432 mutex_lock(&il->mutex);
5433 if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
5434 mutex_unlock(&il->mutex);
be663ab6 5435 return;
28a6e577 5436 }
be663ab6 5437
46bc8d4b
SG		 5438 __il4965_up(il);
5439 mutex_unlock(&il->mutex);
be663ab6
WYG		 5440 }
5441}
5442
e2ebc833 5443static void il4965_bg_rx_replenish(struct work_struct *data)
be663ab6 5444{
46bc8d4b 5445 struct il_priv *il =
e2ebc833 5446 container_of(data, struct il_priv, rx_replenish);
be663ab6 5447
46bc8d4b 5448 if (test_bit(STATUS_EXIT_PENDING, &il->status))
be663ab6
WYG		 5449 return;
5450
46bc8d4b
SG		 5451 mutex_lock(&il->mutex);
5452 il4965_rx_replenish(il);
5453 mutex_unlock(&il->mutex);
be663ab6
WYG		 5454}
5455
5456/*****************************************************************************
5457 *
5458 * mac80211 entry point functions
5459 *
5460 *****************************************************************************/
5461
5462#define UCODE_READY_TIMEOUT (4 * HZ)
5463
5464/*
5465 * Not a mac80211 entry point function, but it fits in with all the
5466 * other mac80211 functions grouped here.
5467 */
46bc8d4b 5468static int il4965_mac_setup_register(struct il_priv *il,
be663ab6
WYG		 5469 u32 max_probe_length)
5470{
5471 int ret;
46bc8d4b 5472 struct ieee80211_hw *hw = il->hw;
be663ab6
WYG		 5473
5474 hw->rate_control_algorithm = "iwl-4965-rs";
5475
5476 /* Tell mac80211 our characteristics */
5477 hw->flags = IEEE80211_HW_SIGNAL_DBM |
5478 IEEE80211_HW_AMPDU_AGGREGATION |
5479 IEEE80211_HW_NEED_DTIM_PERIOD |
5480 IEEE80211_HW_SPECTRUM_MGMT |
5481 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5482
46bc8d4b 5483 if (il->cfg->sku & IL_SKU_N)
be663ab6
WYG		 5484 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5485 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
5486
e2ebc833
SG		 5487 hw->sta_data_size = sizeof(struct il_station_priv);
5488 hw->vif_data_size = sizeof(struct il_vif_priv);
be663ab6 5489
17d6e557
SG		 5490 hw->wiphy->interface_modes |= il->ctx.interface_modes;
5491 hw->wiphy->interface_modes |= il->ctx.exclusive_interface_modes;
be663ab6
WYG		 5492
5493 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5494 WIPHY_FLAG_DISABLE_BEACON_HINTS;
5495
5496 /*
5497 * For now, disable PS by default because it affects
5498 * RX performance significantly.
5499 */
5500 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5501
5502 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5503 /* we create the 802.11 header and a zero-length SSID element */
5504 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5505
5506 /* Default value; 4 EDCA QOS priorities */
5507 hw->queues = 4;
5508
e2ebc833 5509 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
be663ab6 5510
46bc8d4b
SG		 5511 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5512 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5513 &il->bands[IEEE80211_BAND_2GHZ];
5514 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5515 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5516 &il->bands[IEEE80211_BAND_5GHZ];
be663ab6 5517
46bc8d4b 5518 il_leds_init(il);
be663ab6 5519
46bc8d4b 5520 ret = ieee80211_register_hw(il->hw);
be663ab6 5521 if (ret) {
9406f797 5522 IL_ERR("Failed to register hw (error %d)\n", ret);
be663ab6
WYG		 5523 return ret;
5524 }
46bc8d4b 5525 il->mac80211_registered = 1;
be663ab6
WYG		 5526
5527 return 0;
5528}
5529
5530
e2ebc833 5531int il4965_mac_start(struct ieee80211_hw *hw)
be663ab6 5532{
46bc8d4b 5533 struct il_priv *il = hw->priv;
be663ab6
WYG		 5534 int ret;
5535
58de00a4 5536 D_MAC80211("enter\n");
be663ab6
WYG		 5537
5538 /* we should be verifying the device is ready to be opened */
46bc8d4b
SG		 5539 mutex_lock(&il->mutex);
5540 ret = __il4965_up(il);
5541 mutex_unlock(&il->mutex);
be663ab6
WYG		 5542
5543 if (ret)
5544 return ret;
5545
46bc8d4b 5546 if (il_is_rfkill(il))
be663ab6
WYG		 5547 goto out;
5548
58de00a4 5549 D_INFO("Start UP work done.\n");
be663ab6
WYG		 5550
5551 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5552 * mac80211 will not be run successfully. */
46bc8d4b
SG		 5553 ret = wait_event_timeout(il->wait_command_queue,
5554 test_bit(STATUS_READY, &il->status),
be663ab6
WYG		 5555 UCODE_READY_TIMEOUT);
5556 if (!ret) {
46bc8d4b 5557 if (!test_bit(STATUS_READY, &il->status)) {
9406f797 5558 IL_ERR("START_ALIVE timeout after %dms.\n",
be663ab6
WYG		 5559 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5560 return -ETIMEDOUT;
5561 }
5562 }
5563
46bc8d4b 5564 il4965_led_enable(il);
be663ab6
WYG		 5565
5566out:
46bc8d4b 5567 il->is_open = 1;
58de00a4 5568 D_MAC80211("leave\n");
be663ab6
WYG		 5569 return 0;
5570}
5571
e2ebc833 5572void il4965_mac_stop(struct ieee80211_hw *hw)
be663ab6 5573{
46bc8d4b 5574 struct il_priv *il = hw->priv;
be663ab6 5575
58de00a4 5576 D_MAC80211("enter\n");
be663ab6 5577
46bc8d4b 5578 if (!il->is_open)
be663ab6
WYG		 5579 return;
5580
46bc8d4b 5581 il->is_open = 0;
be663ab6 5582
46bc8d4b 5583 il4965_down(il);
be663ab6 5584
46bc8d4b 5585 flush_workqueue(il->workqueue);
be663ab6 5586
a078a1fd
SG		 5587 /* User space software may expect getting rfkill changes
5588 * even if interface is down */
841b2cca 5589 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 5590 il_enable_rfkill_int(il);
be663ab6 5591
58de00a4 5592 D_MAC80211("leave\n");
be663ab6
WYG		 5593}
5594
e2ebc833 5595void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
be663ab6 5596{
46bc8d4b 5597 struct il_priv *il = hw->priv;
be663ab6 5598
58de00a4 5599 D_MACDUMP("enter\n");
be663ab6 5600
58de00a4 5601 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
be663ab6
WYG		 5602 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
5603
46bc8d4b 5604 if (il4965_tx_skb(il, skb))
be663ab6
WYG		 5605 dev_kfree_skb_any(skb);
5606
58de00a4 5607 D_MACDUMP("leave\n");
be663ab6
WYG		 5608}
5609
e2ebc833 5610void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
be663ab6
WYG		 5611 struct ieee80211_vif *vif,
5612 struct ieee80211_key_conf *keyconf,
5613 struct ieee80211_sta *sta,
5614 u32 iv32, u16 *phase1key)
5615{
46bc8d4b 5616 struct il_priv *il = hw->priv;
e2ebc833 5617 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
be663ab6 5618
58de00a4 5619 D_MAC80211("enter\n");
be663ab6 5620
46bc8d4b 5621 il4965_update_tkip_key(il, vif_priv->ctx, keyconf, sta,
be663ab6
WYG		 5622 iv32, phase1key);
5623
58de00a4 5624 D_MAC80211("leave\n");
be663ab6
WYG		 5625}
5626
e2ebc833 5627int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
be663ab6
WYG		 5628 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5629 struct ieee80211_key_conf *key)
5630{
46bc8d4b 5631 struct il_priv *il = hw->priv;
e2ebc833
SG		 5632 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
5633 struct il_rxon_context *ctx = vif_priv->ctx;
be663ab6
WYG		 5634 int ret;
5635 u8 sta_id;
5636 bool is_default_wep_key = false;
5637
58de00a4 5638 D_MAC80211("enter\n");
be663ab6 5639
46bc8d4b 5640 if (il->cfg->mod_params->sw_crypto) {
58de00a4 5641 D_MAC80211("leave - hwcrypto disabled\n");
be663ab6
WYG		 5642 return -EOPNOTSUPP;
5643 }
5644
46bc8d4b 5645 sta_id = il_sta_id_or_broadcast(il, vif_priv->ctx, sta);
e2ebc833 5646 if (sta_id == IL_INVALID_STATION)
be663ab6
WYG		 5647 return -EINVAL;
5648
46bc8d4b
SG		 5649 mutex_lock(&il->mutex);
5650 il_scan_cancel_timeout(il, 100);
be663ab6
WYG		 5651
5652 /*
5653 * If we are getting WEP group key and we didn't receive any key mapping
5654 * so far, we are in legacy wep mode (group key only), otherwise we are
5655 * in 1X mode.
5656 * In legacy wep mode, we use another host command to the uCode.
5657 */
5658 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
5659 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
5660 !sta) {
5661 if (cmd == SET_KEY)
5662 is_default_wep_key = !ctx->key_mapping_keys;
5663 else
5664 is_default_wep_key =
5665 (key->hw_key_idx == HW_KEY_DEFAULT);
5666 }
5667
5668 switch (cmd) {
5669 case SET_KEY:
5670 if (is_default_wep_key)
46bc8d4b 5671 ret = il4965_set_default_wep_key(il,
be663ab6
WYG		 5672 vif_priv->ctx, key);
5673 else
46bc8d4b 5674 ret = il4965_set_dynamic_key(il, vif_priv->ctx,
be663ab6
WYG		 5675 key, sta_id);
5676
58de00a4 5677 D_MAC80211("enable hwcrypto key\n");
be663ab6
WYG		 5678 break;
5679 case DISABLE_KEY:
5680 if (is_default_wep_key)
46bc8d4b 5681 ret = il4965_remove_default_wep_key(il, ctx, key);
be663ab6 5682 else
46bc8d4b 5683 ret = il4965_remove_dynamic_key(il, ctx,
be663ab6
WYG		 5684 key, sta_id);
5685
58de00a4 5686 D_MAC80211("disable hwcrypto key\n");
be663ab6
WYG		 5687 break;
5688 default:
5689 ret = -EINVAL;
5690 }
5691
46bc8d4b 5692 mutex_unlock(&il->mutex);
58de00a4 5693 D_MAC80211("leave\n");
be663ab6
WYG		 5694
5695 return ret;
5696}
5697
e2ebc833 5698int il4965_mac_ampdu_action(struct ieee80211_hw *hw,
be663ab6
WYG		 5699 struct ieee80211_vif *vif,
5700 enum ieee80211_ampdu_mlme_action action,
5701 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5702 u8 buf_size)
5703{
46bc8d4b 5704 struct il_priv *il = hw->priv;
be663ab6
WYG		 5705 int ret = -EINVAL;
5706
58de00a4 5707 D_HT("A-MPDU action on addr %pM tid %d\n",
be663ab6
WYG		 5708 sta->addr, tid);
5709
46bc8d4b 5710 if (!(il->cfg->sku & IL_SKU_N))
be663ab6
WYG		 5711 return -EACCES;
5712
46bc8d4b 5713 mutex_lock(&il->mutex);
be663ab6
WYG		 5714
5715 switch (action) {
5716 case IEEE80211_AMPDU_RX_START:
58de00a4 5717 D_HT("start Rx\n");
46bc8d4b 5718 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
be663ab6
WYG		 5719 break;
5720 case IEEE80211_AMPDU_RX_STOP:
58de00a4 5721 D_HT("stop Rx\n");
46bc8d4b
SG		 5722 ret = il4965_sta_rx_agg_stop(il, sta, tid);
5723 if (test_bit(STATUS_EXIT_PENDING, &il->status))
be663ab6
WYG		 5724 ret = 0;
5725 break;
5726 case IEEE80211_AMPDU_TX_START:
58de00a4 5727 D_HT("start Tx\n");
46bc8d4b 5728 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
be663ab6
WYG		 5729 break;
5730 case IEEE80211_AMPDU_TX_STOP:
58de00a4 5731 D_HT("stop Tx\n");
46bc8d4b
SG		 5732 ret = il4965_tx_agg_stop(il, vif, sta, tid);
5733 if (test_bit(STATUS_EXIT_PENDING, &il->status))
be663ab6
WYG		 5734 ret = 0;
5735 break;
5736 case IEEE80211_AMPDU_TX_OPERATIONAL:
5737 ret = 0;
5738 break;
5739 }
46bc8d4b 5740 mutex_unlock(&il->mutex);
be663ab6
WYG		 5741
5742 return ret;
5743}
5744
e2ebc833 5745int il4965_mac_sta_add(struct ieee80211_hw *hw,
be663ab6
WYG		 5746 struct ieee80211_vif *vif,
5747 struct ieee80211_sta *sta)
5748{
46bc8d4b 5749 struct il_priv *il = hw->priv;
e2ebc833
SG		 5750 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
5751 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
be663ab6
WYG		 5752 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
5753 int ret;
5754 u8 sta_id;
5755
58de00a4 5756 D_INFO("received request to add station %pM\n",
be663ab6 5757 sta->addr);
46bc8d4b 5758 mutex_lock(&il->mutex);
58de00a4 5759 D_INFO("proceeding to add station %pM\n",
be663ab6 5760 sta->addr);
e2ebc833 5761 sta_priv->common.sta_id = IL_INVALID_STATION;
be663ab6
WYG		 5762
5763 atomic_set(&sta_priv->pending_frames, 0);
5764
46bc8d4b 5765 ret = il_add_station_common(il, vif_priv->ctx, sta->addr,
be663ab6
WYG		 5766 is_ap, sta, &sta_id);
5767 if (ret) {
9406f797 5768 IL_ERR("Unable to add station %pM (%d)\n",
be663ab6
WYG		 5769 sta->addr, ret);
5770 /* Should we return success if return code is EEXIST ? */
46bc8d4b 5771 mutex_unlock(&il->mutex);
be663ab6
WYG		 5772 return ret;
5773 }
5774
5775 sta_priv->common.sta_id = sta_id;
5776
5777 /* Initialize rate scaling */
58de00a4 5778 D_INFO("Initializing rate scaling for station %pM\n",
be663ab6 5779 sta->addr);
46bc8d4b
SG		 5780 il4965_rs_rate_init(il, sta, sta_id);
5781 mutex_unlock(&il->mutex);
be663ab6
WYG		 5782
5783 return 0;
5784}
5785
e2ebc833 5786void il4965_mac_channel_switch(struct ieee80211_hw *hw,
be663ab6
WYG		 5787 struct ieee80211_channel_switch *ch_switch)
5788{
46bc8d4b 5789 struct il_priv *il = hw->priv;
e2ebc833 5790 const struct il_channel_info *ch_info;
be663ab6
WYG		 5791 struct ieee80211_conf *conf = &hw->conf;
5792 struct ieee80211_channel *channel = ch_switch->channel;
46bc8d4b 5793 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6 5794
7c2cde2e 5795 struct il_rxon_context *ctx = &il->ctx;
be663ab6 5796 u16 ch;
be663ab6 5797
58de00a4 5798 D_MAC80211("enter\n");
be663ab6 5799
46bc8d4b 5800 mutex_lock(&il->mutex);
28a6e577 5801
46bc8d4b 5802 if (il_is_rfkill(il))
28a6e577 5803 goto out;
be663ab6 5804
46bc8d4b
SG		 5805 if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
5806 test_bit(STATUS_SCANNING, &il->status) ||
5807 test_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status))
28a6e577 5808 goto out;
be663ab6 5809
e2ebc833 5810 if (!il_is_associated_ctx(ctx))
28a6e577 5811 goto out;
be663ab6 5812
46bc8d4b 5813 if (!il->cfg->ops->lib->set_channel_switch)
7f1f9742 5814 goto out;
be663ab6 5815
7f1f9742
SG		 5816 ch = channel->hw_value;
5817 if (le16_to_cpu(ctx->active.channel) == ch)
5818 goto out;
5819
46bc8d4b 5820 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5821 if (!il_is_channel_valid(ch_info)) {
58de00a4 5822 D_MAC80211("invalid channel\n");
7f1f9742
SG		 5823 goto out;
5824 }
5825
46bc8d4b 5826 spin_lock_irq(&il->lock);
7f1f9742 5827
46bc8d4b 5828 il->current_ht_config.smps = conf->smps_mode;
7f1f9742
SG		 5829
5830 /* Configure HT40 channels */
5831 ctx->ht.enabled = conf_is_ht(conf);
5832 if (ctx->ht.enabled) {
5833 if (conf_is_ht40_minus(conf)) {
5834 ctx->ht.extension_chan_offset =
5835 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
5836 ctx->ht.is_40mhz = true;
5837 } else if (conf_is_ht40_plus(conf)) {
5838 ctx->ht.extension_chan_offset =
5839 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
5840 ctx->ht.is_40mhz = true;
5841 } else {
5842 ctx->ht.extension_chan_offset =
5843 IEEE80211_HT_PARAM_CHA_SEC_NONE;
5844 ctx->ht.is_40mhz = false;
be663ab6 5845 }
7f1f9742
SG		 5846 } else
5847 ctx->ht.is_40mhz = false;
5848
5849 if ((le16_to_cpu(ctx->staging.channel) != ch))
5850 ctx->staging.flags = 0;
5851
46bc8d4b
SG		 5852 il_set_rxon_channel(il, channel, ctx);
5853 il_set_rxon_ht(il, ht_conf);
5854 il_set_flags_for_band(il, ctx, channel->band, ctx->vif);
7f1f9742 5855
46bc8d4b 5856 spin_unlock_irq(&il->lock);
7f1f9742 5857
46bc8d4b 5858 il_set_rate(il);
7f1f9742
SG		 5859 /*
5860 * at this point, staging_rxon has the
5861 * configuration for channel switch
5862 */
46bc8d4b
SG		 5863 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status);
5864 il->switch_channel = cpu_to_le16(ch);
5865 if (il->cfg->ops->lib->set_channel_switch(il, ch_switch)) {
5866 clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status);
5867 il->switch_channel = 0;
7f1f9742 5868 ieee80211_chswitch_done(ctx->vif, false);
be663ab6 5869 }
7f1f9742 5870
be663ab6 5871out:
46bc8d4b 5872 mutex_unlock(&il->mutex);
58de00a4 5873 D_MAC80211("leave\n");
be663ab6
WYG		 5874}
5875
e2ebc833 5876void il4965_configure_filter(struct ieee80211_hw *hw,
be663ab6
WYG		 5877 unsigned int changed_flags,
5878 unsigned int *total_flags,
5879 u64 multicast)
5880{
46bc8d4b 5881 struct il_priv *il = hw->priv;
be663ab6 5882 __le32 filter_or = 0, filter_nand = 0;
be663ab6
WYG		 5883
5884#define CHK(test, flag) do { \
5885 if (*total_flags & (test)) \
5886 filter_or |= (flag); \
5887 else \
5888 filter_nand |= (flag); \
5889 } while (0)
5890
58de00a4 5891 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
be663ab6
WYG		 5892 changed_flags, *total_flags);
5893
5894 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
5895 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
5896 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
5897 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
5898
5899#undef CHK
5900
46bc8d4b 5901 mutex_lock(&il->mutex);
be663ab6 5902
17d6e557
SG		 5903 il->ctx.staging.filter_flags &= ~filter_nand;
5904 il->ctx.staging.filter_flags |= filter_or;
be663ab6 5905
17d6e557
SG		 5906 /*
5907 * Not committing directly because hardware can perform a scan,
5908 * but we'll eventually commit the filter flags change anyway.
5909 */
be663ab6 5910
46bc8d4b 5911 mutex_unlock(&il->mutex);
be663ab6
WYG		 5912
5913 /*
5914 * Receiving all multicast frames is always enabled by the
e2ebc833 5915 * default flags setup in il_connection_init_rx_config()
be663ab6
WYG		 5916 * since we currently do not support programming multicast
5917 * filters into the device.
5918 */
5919 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
5920 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
5921}
5922
5923/*****************************************************************************
5924 *
5925 * driver setup and teardown
5926 *
5927 *****************************************************************************/
5928
e2ebc833 5929static void il4965_bg_txpower_work(struct work_struct *work)
be663ab6 5930{
46bc8d4b 5931 struct il_priv *il = container_of(work, struct il_priv,
be663ab6
WYG		 5932 txpower_work);
5933
46bc8d4b 5934 mutex_lock(&il->mutex);
f325757a 5935
be663ab6 5936 /* If a scan happened to start before we got here
ebf0d90d 5937 * then just return; the stats notification will
be663ab6
WYG		 5938 * kick off another scheduled work to compensate for
5939 * any temperature delta we missed here. */
46bc8d4b
SG		 5940 if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
5941 test_bit(STATUS_SCANNING, &il->status))
f325757a 5942 goto out;
be663ab6
WYG		 5943
5944 /* Regardless of if we are associated, we must reconfigure the
5945 * TX power since frames can be sent on non-radar channels while
5946 * not associated */
46bc8d4b 5947 il->cfg->ops->lib->send_tx_power(il);
be663ab6
WYG		 5948
5949 /* Update last_temperature to keep is_calib_needed from running
5950 * when it isn't needed... */
46bc8d4b 5951 il->last_temperature = il->temperature;
f325757a 5952out:
46bc8d4b 5953 mutex_unlock(&il->mutex);
be663ab6
WYG		 5954}
5955
46bc8d4b 5956static void il4965_setup_deferred_work(struct il_priv *il)
be663ab6 5957{
46bc8d4b 5958 il->workqueue = create_singlethread_workqueue(DRV_NAME);
be663ab6 5959
46bc8d4b 5960 init_waitqueue_head(&il->wait_command_queue);
be663ab6 5961
46bc8d4b
SG		 5962 INIT_WORK(&il->restart, il4965_bg_restart);
5963 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
5964 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
5965 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
5966 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
be663ab6 5967
46bc8d4b 5968 il_setup_scan_deferred_work(il);
be663ab6 5969
46bc8d4b 5970 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
be663ab6 5971
ebf0d90d
SG		 5972 init_timer(&il->stats_periodic);
5973 il->stats_periodic.data = (unsigned long)il;
5974 il->stats_periodic.function = il4965_bg_stats_periodic;
be663ab6 5975
46bc8d4b
SG		 5976 init_timer(&il->watchdog);
5977 il->watchdog.data = (unsigned long)il;
5978 il->watchdog.function = il_bg_watchdog;
be663ab6 5979
46bc8d4b
SG		 5980 tasklet_init(&il->irq_tasklet, (void (*)(unsigned long))
5981 il4965_irq_tasklet, (unsigned long)il);
be663ab6
WYG		 5982}
5983
46bc8d4b 5984static void il4965_cancel_deferred_work(struct il_priv *il)
be663ab6 5985{
46bc8d4b
SG		 5986 cancel_work_sync(&il->txpower_work);
5987 cancel_delayed_work_sync(&il->init_alive_start);
5988 cancel_delayed_work(&il->alive_start);
5989 cancel_work_sync(&il->run_time_calib_work);
be663ab6 5990
46bc8d4b 5991 il_cancel_scan_deferred_work(il);
be663ab6 5992
ebf0d90d 5993 del_timer_sync(&il->stats_periodic);
be663ab6
WYG		 5994}
5995
46bc8d4b 5996static void il4965_init_hw_rates(struct il_priv *il,
be663ab6
WYG		 5997 struct ieee80211_rate *rates)
5998{
5999 int i;
6000
2eb05816 6001 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
d2ddf621 6002 rates[i].bitrate = il_rates[i].ieee * 5;
0c2c8852 6003 rates[i].hw_value = i; /* Rate scaling will work on idxes */
be663ab6
WYG		 6004 rates[i].hw_value_short = i;
6005 rates[i].flags = 0;
e2ebc833 6006 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
be663ab6
WYG		 6007 /*
6008 * If CCK != 1M then set short preamble rate flag.
6009 */
6010 rates[i].flags |=
2eb05816 6011 (il_rates[i].plcp == RATE_1M_PLCP) ?
be663ab6
WYG		 6012 0 : IEEE80211_RATE_SHORT_PREAMBLE;
6013 }
6014 }
6015}
6016/*
46bc8d4b 6017 * Acquire il->lock before calling this function !
be663ab6 6018 */
0c2c8852 6019void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
be663ab6 6020{
0c1a94e2 6021 il_wr(il, HBUS_TARG_WRPTR,
0c2c8852
SG		 6022 (idx & 0xff) | (txq_id << 8));
6023 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
be663ab6
WYG		 6024}
6025
46bc8d4b 6026void il4965_tx_queue_set_status(struct il_priv *il,
e2ebc833 6027 struct il_tx_queue *txq,
be663ab6
WYG		 6028 int tx_fifo_id, int scd_retry)
6029{
6030 int txq_id = txq->q.id;
6031
6032 /* Find out whether to activate Tx queue */
46bc8d4b 6033 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
be663ab6
WYG		 6034
6035 /* Set up and activate */
d3175167
SG		 6036 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
6037 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6038 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6039 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6040 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6041 IL49_SCD_QUEUE_STTS_REG_MSK);
be663ab6
WYG		 6042
6043 txq->sched_retry = scd_retry;
6044
58de00a4 6045 D_INFO("%s %s Queue %d on AC %d\n",
be663ab6
WYG		 6046 active ? "Activate" : "Deactivate",
6047 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
6048}
6049
6050
46bc8d4b 6051static int il4965_init_drv(struct il_priv *il)
be663ab6
WYG		 6052{
6053 int ret;
6054
46bc8d4b
SG		 6055 spin_lock_init(&il->sta_lock);
6056 spin_lock_init(&il->hcmd_lock);
be663ab6 6057
46bc8d4b 6058 INIT_LIST_HEAD(&il->free_frames);
be663ab6 6059
46bc8d4b 6060 mutex_init(&il->mutex);
be663ab6 6061
46bc8d4b
SG		 6062 il->ieee_channels = NULL;
6063 il->ieee_rates = NULL;
6064 il->band = IEEE80211_BAND_2GHZ;
be663ab6 6065
46bc8d4b
SG		 6066 il->iw_mode = NL80211_IFTYPE_STATION;
6067 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6068 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
be663ab6
WYG		 6069
6070 /* initialize force reset */
46bc8d4b 6071 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
be663ab6
WYG		 6072
6073 /* Choose which receivers/antennas to use */
46bc8d4b
SG		 6074 if (il->cfg->ops->hcmd->set_rxon_chain)
6075 il->cfg->ops->hcmd->set_rxon_chain(il,
7c2cde2e 6076 &il->ctx);
be663ab6 6077
46bc8d4b 6078 il_init_scan_params(il);
be663ab6 6079
46bc8d4b 6080 ret = il_init_channel_map(il);
be663ab6 6081 if (ret) {
9406f797 6082 IL_ERR("initializing regulatory failed: %d\n", ret);
be663ab6
WYG		 6083 goto err;
6084 }
6085
46bc8d4b 6086 ret = il_init_geos(il);
be663ab6 6087 if (ret) {
9406f797 6088 IL_ERR("initializing geos failed: %d\n", ret);
be663ab6
WYG		 6089 goto err_free_channel_map;
6090 }
46bc8d4b 6091 il4965_init_hw_rates(il, il->ieee_rates);
be663ab6
WYG		 6092
6093 return 0;
6094
6095err_free_channel_map:
46bc8d4b 6096 il_free_channel_map(il);
be663ab6
WYG		 6097err:
6098 return ret;
6099}
6100
46bc8d4b 6101static void il4965_uninit_drv(struct il_priv *il)
be663ab6 6102{
46bc8d4b
SG		 6103 il4965_calib_free_results(il);
6104 il_free_geos(il);
6105 il_free_channel_map(il);
6106 kfree(il->scan_cmd);
be663ab6
WYG		 6107}
6108
46bc8d4b 6109static void il4965_hw_detect(struct il_priv *il)
be663ab6 6110{
841b2cca
SG		 6111 il->hw_rev = _il_rd(il, CSR_HW_REV);
6112 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
46bc8d4b 6113 il->rev_id = il->pci_dev->revision;
58de00a4 6114 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
be663ab6
WYG		 6115}
6116
46bc8d4b 6117static int il4965_set_hw_params(struct il_priv *il)
be663ab6 6118{
46bc8d4b
SG		 6119 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6120 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6121 if (il->cfg->mod_params->amsdu_size_8K)
6122 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
be663ab6 6123 else
46bc8d4b 6124 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
be663ab6 6125
46bc8d4b 6126 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
be663ab6 6127
46bc8d4b
SG		 6128 if (il->cfg->mod_params->disable_11n)
6129 il->cfg->sku &= ~IL_SKU_N;
be663ab6
WYG		 6130
6131 /* Device-specific setup */
46bc8d4b 6132 return il->cfg->ops->lib->set_hw_params(il);
be663ab6
WYG		 6133}
6134
e2ebc833
SG		 6135static const u8 il4965_bss_ac_to_fifo[] = {
6136 IL_TX_FIFO_VO,
6137 IL_TX_FIFO_VI,
6138 IL_TX_FIFO_BE,
6139 IL_TX_FIFO_BK,
be663ab6
WYG		 6140};
6141
e2ebc833 6142static const u8 il4965_bss_ac_to_queue[] = {
be663ab6
WYG		 6143 0, 1, 2, 3,
6144};
6145
6146static int
e2ebc833 6147il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
be663ab6 6148{
7c2cde2e 6149 int err = 0;
46bc8d4b 6150 struct il_priv *il;
be663ab6 6151 struct ieee80211_hw *hw;
e2ebc833 6152 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
be663ab6
WYG		 6153 unsigned long flags;
6154 u16 pci_cmd;
6155
6156 /************************
6157 * 1. Allocating HW data
6158 ************************/
6159
e2ebc833 6160 hw = il_alloc_all(cfg);
be663ab6
WYG		 6161 if (!hw) {
6162 err = -ENOMEM;
6163 goto out;
6164 }
46bc8d4b
SG		 6165 il = hw->priv;
6166 /* At this point both hw and il are allocated. */
be663ab6 6167
7c2cde2e
SG		 6168 il->ctx.ctxid = 0;
6169
6170 il->ctx.always_active = true;
6171 il->ctx.is_active = true;
6172 il->ctx.rxon_cmd = REPLY_RXON;
6173 il->ctx.rxon_timing_cmd = REPLY_RXON_TIMING;
6174 il->ctx.rxon_assoc_cmd = REPLY_RXON_ASSOC;
6175 il->ctx.qos_cmd = REPLY_QOS_PARAM;
6176 il->ctx.ap_sta_id = IL_AP_ID;
6177 il->ctx.wep_key_cmd = REPLY_WEPKEY;
6178 il->ctx.ac_to_fifo = il4965_bss_ac_to_fifo;
6179 il->ctx.ac_to_queue = il4965_bss_ac_to_queue;
6180 il->ctx.exclusive_interface_modes =
be663ab6 6181 BIT(NL80211_IFTYPE_ADHOC);
7c2cde2e 6182 il->ctx.interface_modes =
be663ab6 6183 BIT(NL80211_IFTYPE_STATION);
7c2cde2e
SG		 6184 il->ctx.ap_devtype = RXON_DEV_TYPE_AP;
6185 il->ctx.ibss_devtype = RXON_DEV_TYPE_IBSS;
6186 il->ctx.station_devtype = RXON_DEV_TYPE_ESS;
6187 il->ctx.unused_devtype = RXON_DEV_TYPE_ESS;
be663ab6
WYG		 6188
6189 SET_IEEE80211_DEV(hw, &pdev->dev);
6190
58de00a4 6191 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b
SG		 6192 il->cfg = cfg;
6193 il->pci_dev = pdev;
6194 il->inta_mask = CSR_INI_SET_MASK;
be663ab6 6195
46bc8d4b 6196 if (il_alloc_traffic_mem(il))
9406f797 6197 IL_ERR("Not enough memory to generate traffic log\n");
be663ab6
WYG		 6198
6199 /**************************
6200 * 2. Initializing PCI bus
6201 **************************/
6202 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6203 PCIE_LINK_STATE_CLKPM);
6204
6205 if (pci_enable_device(pdev)) {
6206 err = -ENODEV;
6207 goto out_ieee80211_free_hw;
6208 }
6209
6210 pci_set_master(pdev);
6211
6212 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6213 if (!err)
6214 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6215 if (err) {
6216 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6217 if (!err)
6218 err = pci_set_consistent_dma_mask(pdev,
6219 DMA_BIT_MASK(32));
6220 /* both attempts failed: */
6221 if (err) {
9406f797 6222 IL_WARN("No suitable DMA available.\n");
be663ab6
WYG		 6223 goto out_pci_disable_device;
6224 }
6225 }
6226
6227 err = pci_request_regions(pdev, DRV_NAME);
6228 if (err)
6229 goto out_pci_disable_device;
6230
46bc8d4b 6231 pci_set_drvdata(pdev, il);
be663ab6
WYG		 6232
6233
6234 /***********************
6235 * 3. Read REV register
6236 ***********************/
46bc8d4b
SG		 6237 il->hw_base = pci_iomap(pdev, 0, 0);
6238 if (!il->hw_base) {
be663ab6
WYG		 6239 err = -ENODEV;
6240 goto out_pci_release_regions;
6241 }
6242
58de00a4 6243 D_INFO("pci_resource_len = 0x%08llx\n",
be663ab6 6244 (unsigned long long) pci_resource_len(pdev, 0));
58de00a4 6245 D_INFO("pci_resource_base = %p\n", il->hw_base);
be663ab6
WYG		 6246
6247 /* these spin locks will be used in apm_ops.init and EEPROM access
6248 * we should init now
6249 */
46bc8d4b
SG		 6250 spin_lock_init(&il->reg_lock);
6251 spin_lock_init(&il->lock);
be663ab6
WYG		 6252
6253 /*
6254 * stop and reset the on-board processor just in case it is in a
6255 * strange state ... like being left stranded by a primary kernel
6256 * and this is now the kdump kernel trying to start up
6257 */
841b2cca 6258 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
be663ab6 6259
46bc8d4b 6260 il4965_hw_detect(il);
9406f797 6261 IL_INFO("Detected %s, REV=0x%X\n",
46bc8d4b 6262 il->cfg->name, il->hw_rev);
be663ab6
WYG		 6263
6264 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6265 * PCI Tx retries from interfering with C3 CPU state */
6266 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6267
46bc8d4b
SG		 6268 il4965_prepare_card_hw(il);
6269 if (!il->hw_ready) {
9406f797 6270 IL_WARN("Failed, HW not ready\n");
be663ab6
WYG		 6271 goto out_iounmap;
6272 }
6273
6274 /*****************
6275 * 4. Read EEPROM
6276 *****************/
6277 /* Read the EEPROM */
46bc8d4b 6278 err = il_eeprom_init(il);
be663ab6 6279 if (err) {
9406f797 6280 IL_ERR("Unable to init EEPROM\n");
be663ab6
WYG		 6281 goto out_iounmap;
6282 }
46bc8d4b 6283 err = il4965_eeprom_check_version(il);
be663ab6
WYG		 6284 if (err)
6285 goto out_free_eeprom;
6286
6287 if (err)
6288 goto out_free_eeprom;
6289
6290 /* extract MAC Address */
46bc8d4b 6291 il4965_eeprom_get_mac(il, il->addresses[0].addr);
58de00a4 6292 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
46bc8d4b
SG		 6293 il->hw->wiphy->addresses = il->addresses;
6294 il->hw->wiphy->n_addresses = 1;
be663ab6
WYG		 6295
6296 /************************
6297 * 5. Setup HW constants
6298 ************************/
46bc8d4b 6299 if (il4965_set_hw_params(il)) {
9406f797 6300 IL_ERR("failed to set hw parameters\n");
be663ab6
WYG		 6301 goto out_free_eeprom;
6302 }
6303
6304 /*******************
46bc8d4b 6305 * 6. Setup il
be663ab6
WYG		 6306 *******************/
6307
46bc8d4b 6308 err = il4965_init_drv(il);
be663ab6
WYG		 6309 if (err)
6310 goto out_free_eeprom;
46bc8d4b 6311 /* At this point both hw and il are initialized. */
be663ab6
WYG		 6312
6313 /********************
6314 * 7. Setup services
6315 ********************/
46bc8d4b
SG		 6316 spin_lock_irqsave(&il->lock, flags);
6317 il_disable_interrupts(il);
6318 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6319
46bc8d4b 6320 pci_enable_msi(il->pci_dev);
be663ab6 6321
46bc8d4b
SG		 6322 err = request_irq(il->pci_dev->irq, il_isr,
6323 IRQF_SHARED, DRV_NAME, il);
be663ab6 6324 if (err) {
9406f797 6325 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
be663ab6
WYG		 6326 goto out_disable_msi;
6327 }
6328
46bc8d4b
SG		 6329 il4965_setup_deferred_work(il);
6330 il4965_setup_rx_handlers(il);
be663ab6
WYG		 6331
6332 /*********************************************
6333 * 8. Enable interrupts and read RFKILL state
6334 *********************************************/
6335
a078a1fd 6336 /* enable rfkill interrupt: hw bug w/a */
46bc8d4b 6337 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
be663ab6
WYG		 6338 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6339 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
46bc8d4b 6340 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
be663ab6
WYG		 6341 }
6342
46bc8d4b 6343 il_enable_rfkill_int(il);
be663ab6
WYG		 6344
6345 /* If platform's RF_KILL switch is NOT set to KILL */
841b2cca 6346 if (_il_rd(il, CSR_GP_CNTRL) &
be663ab6 6347 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
46bc8d4b 6348 clear_bit(STATUS_RF_KILL_HW, &il->status);
be663ab6 6349 else
46bc8d4b 6350 set_bit(STATUS_RF_KILL_HW, &il->status);
be663ab6 6351
46bc8d4b
SG		 6352 wiphy_rfkill_set_hw_state(il->hw->wiphy,
6353 test_bit(STATUS_RF_KILL_HW, &il->status));
be663ab6 6354
46bc8d4b 6355 il_power_initialize(il);
be663ab6 6356
46bc8d4b 6357 init_completion(&il->_4965.firmware_loading_complete);
be663ab6 6358
46bc8d4b 6359 err = il4965_request_firmware(il, true);
be663ab6
WYG		 6360 if (err)
6361 goto out_destroy_workqueue;
6362
6363 return 0;
6364
6365 out_destroy_workqueue:
46bc8d4b
SG		 6366 destroy_workqueue(il->workqueue);
6367 il->workqueue = NULL;
6368 free_irq(il->pci_dev->irq, il);
be663ab6 6369 out_disable_msi:
46bc8d4b
SG		 6370 pci_disable_msi(il->pci_dev);
6371 il4965_uninit_drv(il);
be663ab6 6372 out_free_eeprom:
46bc8d4b 6373 il_eeprom_free(il);
be663ab6 6374 out_iounmap:
46bc8d4b 6375 pci_iounmap(pdev, il->hw_base);
be663ab6
WYG		 6376 out_pci_release_regions:
6377 pci_set_drvdata(pdev, NULL);
6378 pci_release_regions(pdev);
6379 out_pci_disable_device:
6380 pci_disable_device(pdev);
6381 out_ieee80211_free_hw:
46bc8d4b
SG		 6382 il_free_traffic_mem(il);
6383 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6384 out:
6385 return err;
6386}
6387
e2ebc833 6388static void __devexit il4965_pci_remove(struct pci_dev *pdev)
be663ab6 6389{
46bc8d4b 6390 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 6391 unsigned long flags;
6392
46bc8d4b 6393 if (!il)
be663ab6
WYG		 6394 return;
6395
46bc8d4b 6396 wait_for_completion(&il->_4965.firmware_loading_complete);
be663ab6 6397
58de00a4 6398 D_INFO("*** UNLOAD DRIVER ***\n");
be663ab6 6399
46bc8d4b 6400 il_dbgfs_unregister(il);
e2ebc833 6401 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
be663ab6 6402
e2ebc833
SG		 6403 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6404 * to be called and il4965_down since we are removing the device
be663ab6
WYG		 6405 * we need to set STATUS_EXIT_PENDING bit.
6406 */
46bc8d4b 6407 set_bit(STATUS_EXIT_PENDING, &il->status);
be663ab6 6408
46bc8d4b 6409 il_leds_exit(il);
be663ab6 6410
46bc8d4b
SG		 6411 if (il->mac80211_registered) {
6412 ieee80211_unregister_hw(il->hw);
6413 il->mac80211_registered = 0;
be663ab6 6414 } else {
46bc8d4b 6415 il4965_down(il);
be663ab6
WYG		 6416 }
6417
6418 /*
6419 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG		 6420 * This may be redundant with il4965_down(), but there are paths to
6421 * run il4965_down() without calling apm_ops.stop(), and there are
6422 * paths to avoid running il4965_down() at all before leaving driver.
be663ab6
WYG		 6423 * This (inexpensive) call *makes sure* device is reset.
6424 */
46bc8d4b 6425 il_apm_stop(il);
be663ab6
WYG		 6426
6427 /* make sure we flush any pending irq or
6428 * tasklet for the driver
6429 */
46bc8d4b
SG		 6430 spin_lock_irqsave(&il->lock, flags);
6431 il_disable_interrupts(il);
6432 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 6433
46bc8d4b 6434 il4965_synchronize_irq(il);
be663ab6 6435
46bc8d4b 6436 il4965_dealloc_ucode_pci(il);
be663ab6 6437
46bc8d4b
SG		 6438 if (il->rxq.bd)
6439 il4965_rx_queue_free(il, &il->rxq);
6440 il4965_hw_txq_ctx_free(il);
be663ab6 6441
46bc8d4b 6442 il_eeprom_free(il);
be663ab6
WYG		 6443
6444
6445 /*netif_stop_queue(dev); */
46bc8d4b 6446 flush_workqueue(il->workqueue);
be663ab6 6447
e2ebc833 6448 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
46bc8d4b 6449 * il->workqueue... so we can't take down the workqueue
be663ab6 6450 * until now... */
46bc8d4b
SG		 6451 destroy_workqueue(il->workqueue);
6452 il->workqueue = NULL;
6453 il_free_traffic_mem(il);
be663ab6 6454
46bc8d4b
SG		 6455 free_irq(il->pci_dev->irq, il);
6456 pci_disable_msi(il->pci_dev);
6457 pci_iounmap(pdev, il->hw_base);
be663ab6
WYG		 6458 pci_release_regions(pdev);
6459 pci_disable_device(pdev);
6460 pci_set_drvdata(pdev, NULL);
6461
46bc8d4b 6462 il4965_uninit_drv(il);
be663ab6 6463
46bc8d4b 6464 dev_kfree_skb(il->beacon_skb);
be663ab6 6465
46bc8d4b 6466 ieee80211_free_hw(il->hw);
be663ab6
WYG		 6467}
6468
6469/*
6470 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
46bc8d4b 6471 * must be called under il->lock and mac access
be663ab6 6472 */
46bc8d4b 6473void il4965_txq_set_sched(struct il_priv *il, u32 mask)
be663ab6 6474{
d3175167 6475 il_wr_prph(il, IL49_SCD_TXFACT, mask);
be663ab6
WYG		 6476}
6477
6478/*****************************************************************************
6479 *
6480 * driver and module entry point
6481 *
6482 *****************************************************************************/
6483
6484/* Hardware specific file defines the PCI IDs table for that hardware module */
e2ebc833 6485static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
e2ebc833
SG		 6486 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6487 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
be663ab6
WYG		 6488 {0}
6489};
e2ebc833 6490MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
be663ab6 6491
e2ebc833 6492static struct pci_driver il4965_driver = {
be663ab6 6493 .name = DRV_NAME,
e2ebc833
SG		 6494 .id_table = il4965_hw_card_ids,
6495 .probe = il4965_pci_probe,
6496 .remove = __devexit_p(il4965_pci_remove),
6497 .driver.pm = IL_LEGACY_PM_OPS,
be663ab6
WYG		 6498};
6499
e2ebc833 6500static int __init il4965_init(void)
be663ab6
WYG		 6501{
6502
6503 int ret;
6504 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6505 pr_info(DRV_COPYRIGHT "\n");
6506
e2ebc833 6507 ret = il4965_rate_control_register();
be663ab6
WYG		 6508 if (ret) {
6509 pr_err("Unable to register rate control algorithm: %d\n", ret);
6510 return ret;
6511 }
6512
e2ebc833 6513 ret = pci_register_driver(&il4965_driver);
be663ab6
WYG		 6514 if (ret) {
6515 pr_err("Unable to initialize PCI module\n");
6516 goto error_register;
6517 }
6518
6519 return ret;
6520
6521error_register:
e2ebc833 6522 il4965_rate_control_unregister();
be663ab6
WYG		 6523 return ret;
6524}
6525
e2ebc833 6526static void __exit il4965_exit(void)
be663ab6 6527{
e2ebc833
SG		 6528 pci_unregister_driver(&il4965_driver);
6529 il4965_rate_control_unregister();
be663ab6
WYG		 6530}
6531
e2ebc833
SG		 6532module_exit(il4965_exit);
6533module_init(il4965_init);
be663ab6 6534
d3175167 6535#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 6536module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
be663ab6
WYG		 6537MODULE_PARM_DESC(debug, "debug output mask");
6538#endif
6539
e2ebc833 6540module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
be663ab6 6541MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
e2ebc833 6542module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
be663ab6 6543MODULE_PARM_DESC(queues_num, "number of hw queues.");
e2ebc833 6544module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
be663ab6 6545MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
e2ebc833 6546module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K,
be663ab6
WYG		 6547 int, S_IRUGO);
6548MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
e2ebc833 6549module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
be663ab6 6550MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
Linux kernel - Deliverables
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