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4bc85c13 WYG |
1 | /****************************************************************************** |
2 | * | |
be663ab6 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
4bc85c13 WYG |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Linux Wireless <ilw@linux.intel.com> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | *****************************************************************************/ | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/netdevice.h> | |
4bc85c13 WYG |
36 | #include <net/mac80211.h> |
37 | #include <linux/etherdevice.h> | |
38 | #include <asm/unaligned.h> | |
39 | ||
98613be0 | 40 | #include "common.h" |
af038f40 | 41 | #include "4965.h" |
4bc85c13 | 42 | |
862d32e6 SG |
43 | /** |
44 | * il_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
45 | * using sample data 100 bytes apart. If these sample points are good, | |
46 | * it's a pretty good bet that everything between them is good, too. | |
47 | */ | |
48 | static int | |
e7392364 | 49 | il4965_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len) |
862d32e6 SG |
50 | { |
51 | u32 val; | |
52 | int ret = 0; | |
53 | u32 errcnt = 0; | |
54 | u32 i; | |
55 | ||
56 | D_INFO("ucode inst image size is %u\n", len); | |
57 | ||
e7392364 | 58 | for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) { |
862d32e6 SG |
59 | /* read data comes through single port, auto-incr addr */ |
60 | /* NOTE: Use the debugless read so we don't flood kernel log | |
61 | * if IL_DL_IO is set */ | |
e7392364 | 62 | il_wr(il, HBUS_TARG_MEM_RADDR, i + IL4965_RTC_INST_LOWER_BOUND); |
862d32e6 SG |
63 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); |
64 | if (val != le32_to_cpu(*image)) { | |
65 | ret = -EIO; | |
66 | errcnt++; | |
67 | if (errcnt >= 3) | |
68 | break; | |
69 | } | |
70 | } | |
71 | ||
72 | return ret; | |
73 | } | |
74 | ||
75 | /** | |
76 | * il4965_verify_inst_full - verify runtime uCode image in card vs. host, | |
77 | * looking at all data. | |
78 | */ | |
e7392364 SG |
79 | static int |
80 | il4965_verify_inst_full(struct il_priv *il, __le32 * image, u32 len) | |
862d32e6 SG |
81 | { |
82 | u32 val; | |
83 | u32 save_len = len; | |
84 | int ret = 0; | |
85 | u32 errcnt; | |
86 | ||
87 | D_INFO("ucode inst image size is %u\n", len); | |
88 | ||
e7392364 | 89 | il_wr(il, HBUS_TARG_MEM_RADDR, IL4965_RTC_INST_LOWER_BOUND); |
862d32e6 SG |
90 | |
91 | errcnt = 0; | |
92 | for (; len > 0; len -= sizeof(u32), image++) { | |
93 | /* read data comes through single port, auto-incr addr */ | |
94 | /* NOTE: Use the debugless read so we don't flood kernel log | |
95 | * if IL_DL_IO is set */ | |
96 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); | |
97 | if (val != le32_to_cpu(*image)) { | |
98 | IL_ERR("uCode INST section is invalid at " | |
e7392364 SG |
99 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
100 | save_len - len, val, le32_to_cpu(*image)); | |
862d32e6 SG |
101 | ret = -EIO; |
102 | errcnt++; | |
103 | if (errcnt >= 20) | |
104 | break; | |
105 | } | |
106 | } | |
107 | ||
108 | if (!errcnt) | |
e7392364 | 109 | D_INFO("ucode image in INSTRUCTION memory is good\n"); |
862d32e6 SG |
110 | |
111 | return ret; | |
112 | } | |
113 | ||
114 | /** | |
115 | * il4965_verify_ucode - determine which instruction image is in SRAM, | |
116 | * and verify its contents | |
117 | */ | |
e7392364 SG |
118 | int |
119 | il4965_verify_ucode(struct il_priv *il) | |
862d32e6 SG |
120 | { |
121 | __le32 *image; | |
122 | u32 len; | |
123 | int ret; | |
124 | ||
125 | /* Try bootstrap */ | |
e7392364 | 126 | image = (__le32 *) il->ucode_boot.v_addr; |
862d32e6 SG |
127 | len = il->ucode_boot.len; |
128 | ret = il4965_verify_inst_sparse(il, image, len); | |
129 | if (!ret) { | |
130 | D_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
131 | return 0; | |
132 | } | |
133 | ||
134 | /* Try initialize */ | |
e7392364 | 135 | image = (__le32 *) il->ucode_init.v_addr; |
862d32e6 SG |
136 | len = il->ucode_init.len; |
137 | ret = il4965_verify_inst_sparse(il, image, len); | |
138 | if (!ret) { | |
139 | D_INFO("Initialize uCode is good in inst SRAM\n"); | |
140 | return 0; | |
141 | } | |
142 | ||
143 | /* Try runtime/protocol */ | |
e7392364 | 144 | image = (__le32 *) il->ucode_code.v_addr; |
862d32e6 SG |
145 | len = il->ucode_code.len; |
146 | ret = il4965_verify_inst_sparse(il, image, len); | |
147 | if (!ret) { | |
148 | D_INFO("Runtime uCode is good in inst SRAM\n"); | |
149 | return 0; | |
150 | } | |
151 | ||
152 | IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
153 | ||
154 | /* Since nothing seems to match, show first several data entries in | |
155 | * instruction SRAM, so maybe visual inspection will give a clue. | |
156 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
e7392364 | 157 | image = (__le32 *) il->ucode_boot.v_addr; |
862d32e6 SG |
158 | len = il->ucode_boot.len; |
159 | ret = il4965_verify_inst_full(il, image, len); | |
160 | ||
161 | return ret; | |
162 | } | |
163 | ||
56e7a8cc SG |
164 | /****************************************************************************** |
165 | * | |
166 | * EEPROM related functions | |
167 | * | |
168 | ******************************************************************************/ | |
169 | ||
170 | /* | |
171 | * The device's EEPROM semaphore prevents conflicts between driver and uCode | |
172 | * when accessing the EEPROM; each access is a series of pulses to/from the | |
173 | * EEPROM chip, not a single event, so even reads could conflict if they | |
174 | * weren't arbitrated by the semaphore. | |
175 | */ | |
e7392364 SG |
176 | int |
177 | il4965_eeprom_acquire_semaphore(struct il_priv *il) | |
56e7a8cc SG |
178 | { |
179 | u16 count; | |
180 | int ret; | |
181 | ||
182 | for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { | |
183 | /* Request semaphore */ | |
184 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, | |
e7392364 | 185 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); |
56e7a8cc SG |
186 | |
187 | /* See if we got it */ | |
e7392364 SG |
188 | ret = |
189 | _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, | |
190 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, | |
191 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, | |
192 | EEPROM_SEM_TIMEOUT); | |
56e7a8cc SG |
193 | if (ret >= 0) |
194 | return ret; | |
195 | } | |
196 | ||
197 | return ret; | |
198 | } | |
199 | ||
e7392364 SG |
200 | void |
201 | il4965_eeprom_release_semaphore(struct il_priv *il) | |
56e7a8cc SG |
202 | { |
203 | il_clear_bit(il, CSR_HW_IF_CONFIG_REG, | |
e7392364 | 204 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); |
56e7a8cc SG |
205 | |
206 | } | |
207 | ||
e7392364 SG |
208 | int |
209 | il4965_eeprom_check_version(struct il_priv *il) | |
56e7a8cc SG |
210 | { |
211 | u16 eeprom_ver; | |
212 | u16 calib_ver; | |
213 | ||
214 | eeprom_ver = il_eeprom_query16(il, EEPROM_VERSION); | |
e7392364 | 215 | calib_ver = il_eeprom_query16(il, EEPROM_4965_CALIB_VERSION_OFFSET); |
56e7a8cc SG |
216 | |
217 | if (eeprom_ver < il->cfg->eeprom_ver || | |
218 | calib_ver < il->cfg->eeprom_calib_ver) | |
219 | goto err; | |
220 | ||
e7392364 | 221 | IL_INFO("device EEPROM VER=0x%x, CALIB=0x%x\n", eeprom_ver, calib_ver); |
56e7a8cc SG |
222 | |
223 | return 0; | |
224 | err: | |
225 | IL_ERR("Unsupported (too old) EEPROM VER=0x%x < 0x%x " | |
e7392364 SG |
226 | "CALIB=0x%x < 0x%x\n", eeprom_ver, il->cfg->eeprom_ver, |
227 | calib_ver, il->cfg->eeprom_calib_ver); | |
56e7a8cc SG |
228 | return -EINVAL; |
229 | ||
230 | } | |
231 | ||
e7392364 SG |
232 | void |
233 | il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac) | |
56e7a8cc SG |
234 | { |
235 | const u8 *addr = il_eeprom_query_addr(il, | |
e7392364 | 236 | EEPROM_MAC_ADDRESS); |
56e7a8cc SG |
237 | memcpy(mac, addr, ETH_ALEN); |
238 | } | |
239 | ||
fc19cbde SG |
240 | /* Send led command */ |
241 | static int | |
242 | il4965_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd) | |
243 | { | |
244 | struct il_host_cmd cmd = { | |
4d69c752 | 245 | .id = C_LEDS, |
fc19cbde SG |
246 | .len = sizeof(struct il_led_cmd), |
247 | .data = led_cmd, | |
248 | .flags = CMD_ASYNC, | |
249 | .callback = NULL, | |
250 | }; | |
251 | u32 reg; | |
252 | ||
253 | reg = _il_rd(il, CSR_LED_REG); | |
254 | if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) | |
255 | _il_wr(il, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); | |
256 | ||
257 | return il_send_cmd(il, &cmd); | |
258 | } | |
259 | ||
260 | /* Set led register off */ | |
e7392364 SG |
261 | void |
262 | il4965_led_enable(struct il_priv *il) | |
fc19cbde SG |
263 | { |
264 | _il_wr(il, CSR_LED_REG, CSR_LED_REG_TRUN_ON); | |
265 | } | |
266 | ||
267 | const struct il_led_ops il4965_led_ops = { | |
268 | .cmd = il4965_send_led_cmd, | |
269 | }; | |
270 | ||
46bc8d4b SG |
271 | static int il4965_send_tx_power(struct il_priv *il); |
272 | static int il4965_hw_get_temperature(struct il_priv *il); | |
4bc85c13 WYG |
273 | |
274 | /* Highest firmware API version supported */ | |
d3175167 | 275 | #define IL4965_UCODE_API_MAX 2 |
4bc85c13 WYG |
276 | |
277 | /* Lowest firmware API version supported */ | |
d3175167 | 278 | #define IL4965_UCODE_API_MIN 2 |
4bc85c13 | 279 | |
d3175167 SG |
280 | #define IL4965_FW_PRE "iwlwifi-4965-" |
281 | #define _IL4965_MODULE_FIRMWARE(api) IL4965_FW_PRE #api ".ucode" | |
282 | #define IL4965_MODULE_FIRMWARE(api) _IL4965_MODULE_FIRMWARE(api) | |
4bc85c13 WYG |
283 | |
284 | /* check contents of special bootstrap uCode SRAM */ | |
e7392364 SG |
285 | static int |
286 | il4965_verify_bsm(struct il_priv *il) | |
4bc85c13 | 287 | { |
46bc8d4b SG |
288 | __le32 *image = il->ucode_boot.v_addr; |
289 | u32 len = il->ucode_boot.len; | |
4bc85c13 WYG |
290 | u32 reg; |
291 | u32 val; | |
292 | ||
58de00a4 | 293 | D_INFO("Begin verify bsm\n"); |
4bc85c13 WYG |
294 | |
295 | /* verify BSM SRAM contents */ | |
db54eb57 | 296 | val = il_rd_prph(il, BSM_WR_DWCOUNT_REG); |
e7392364 | 297 | for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len; |
4bc85c13 | 298 | reg += sizeof(u32), image++) { |
db54eb57 | 299 | val = il_rd_prph(il, reg); |
4bc85c13 | 300 | if (val != le32_to_cpu(*image)) { |
9406f797 | 301 | IL_ERR("BSM uCode verification failed at " |
e7392364 SG |
302 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", |
303 | BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND, | |
304 | len, val, le32_to_cpu(*image)); | |
4bc85c13 WYG |
305 | return -EIO; |
306 | } | |
307 | } | |
308 | ||
58de00a4 | 309 | D_INFO("BSM bootstrap uCode image OK\n"); |
4bc85c13 WYG |
310 | |
311 | return 0; | |
312 | } | |
313 | ||
314 | /** | |
e2ebc833 | 315 | * il4965_load_bsm - Load bootstrap instructions |
4bc85c13 WYG |
316 | * |
317 | * BSM operation: | |
318 | * | |
319 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
320 | * in special SRAM that does not power down during RFKILL. When powering back | |
321 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
322 | * the bootstrap program into the on-board processor, and starts it. | |
323 | * | |
324 | * The bootstrap program loads (via DMA) instructions and data for a new | |
325 | * program from host DRAM locations indicated by the host driver in the | |
326 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
327 | * automatically. | |
328 | * | |
329 | * When initializing the NIC, the host driver points the BSM to the | |
330 | * "initialize" uCode image. This uCode sets up some internal data, then | |
331 | * notifies host via "initialize alive" that it is complete. | |
332 | * | |
333 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
334 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
335 | * (filled initially with starting data values for the on-board processor), | |
336 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
337 | * which begins normal operation. | |
338 | * | |
339 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
340 | * the backup data cache in DRAM before SRAM is powered down. | |
341 | * | |
342 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
343 | * the runtime uCode instructions and the backup data cache into SRAM, | |
344 | * and re-launches the runtime uCode from where it left off. | |
345 | */ | |
e7392364 SG |
346 | static int |
347 | il4965_load_bsm(struct il_priv *il) | |
4bc85c13 | 348 | { |
46bc8d4b SG |
349 | __le32 *image = il->ucode_boot.v_addr; |
350 | u32 len = il->ucode_boot.len; | |
4bc85c13 WYG |
351 | dma_addr_t pinst; |
352 | dma_addr_t pdata; | |
353 | u32 inst_len; | |
354 | u32 data_len; | |
355 | int i; | |
356 | u32 done; | |
357 | u32 reg_offset; | |
358 | int ret; | |
359 | ||
58de00a4 | 360 | D_INFO("Begin load bsm\n"); |
4bc85c13 | 361 | |
46bc8d4b | 362 | il->ucode_type = UCODE_RT; |
4bc85c13 WYG |
363 | |
364 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
d3175167 | 365 | if (len > IL49_MAX_BSM_SIZE) |
4bc85c13 WYG |
366 | return -EINVAL; |
367 | ||
368 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
369 | * in host DRAM ... host DRAM physical address bits 35:4 for 4965. | |
e2ebc833 | 370 | * NOTE: il_init_alive_start() will replace these values, |
4bc85c13 WYG |
371 | * after the "initialize" uCode has run, to point to |
372 | * runtime/protocol instructions and backup data cache. | |
373 | */ | |
46bc8d4b SG |
374 | pinst = il->ucode_init.p_addr >> 4; |
375 | pdata = il->ucode_init_data.p_addr >> 4; | |
376 | inst_len = il->ucode_init.len; | |
377 | data_len = il->ucode_init_data.len; | |
4bc85c13 | 378 | |
db54eb57 SG |
379 | il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst); |
380 | il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata); | |
381 | il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
382 | il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
4bc85c13 WYG |
383 | |
384 | /* Fill BSM memory with bootstrap instructions */ | |
385 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
386 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
387 | reg_offset += sizeof(u32), image++) | |
db54eb57 | 388 | _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); |
4bc85c13 | 389 | |
46bc8d4b | 390 | ret = il4965_verify_bsm(il); |
4bc85c13 WYG |
391 | if (ret) |
392 | return ret; | |
393 | ||
394 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
db54eb57 | 395 | il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0); |
e7392364 | 396 | il_wr_prph(il, BSM_WR_MEM_DST_REG, IL49_RTC_INST_LOWER_BOUND); |
db54eb57 | 397 | il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); |
4bc85c13 WYG |
398 | |
399 | /* Load bootstrap code into instruction SRAM now, | |
400 | * to prepare to load "initialize" uCode */ | |
db54eb57 | 401 | il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START); |
4bc85c13 WYG |
402 | |
403 | /* Wait for load of bootstrap uCode to finish */ | |
404 | for (i = 0; i < 100; i++) { | |
db54eb57 | 405 | done = il_rd_prph(il, BSM_WR_CTRL_REG); |
4bc85c13 WYG |
406 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) |
407 | break; | |
408 | udelay(10); | |
409 | } | |
410 | if (i < 100) | |
58de00a4 | 411 | D_INFO("BSM write complete, poll %d iterations\n", i); |
4bc85c13 | 412 | else { |
9406f797 | 413 | IL_ERR("BSM write did not complete!\n"); |
4bc85c13 WYG |
414 | return -EIO; |
415 | } | |
416 | ||
417 | /* Enable future boot loads whenever power management unit triggers it | |
418 | * (e.g. when powering back up after power-save shutdown) */ | |
e7392364 | 419 | il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); |
4bc85c13 WYG |
420 | |
421 | return 0; | |
422 | } | |
423 | ||
424 | /** | |
e2ebc833 | 425 | * il4965_set_ucode_ptrs - Set uCode address location |
4bc85c13 WYG |
426 | * |
427 | * Tell initialization uCode where to find runtime uCode. | |
428 | * | |
429 | * BSM registers initially contain pointers to initialization uCode. | |
430 | * We need to replace them to load runtime uCode inst and data, | |
431 | * and to save runtime data when powering down. | |
432 | */ | |
e7392364 SG |
433 | static int |
434 | il4965_set_ucode_ptrs(struct il_priv *il) | |
4bc85c13 WYG |
435 | { |
436 | dma_addr_t pinst; | |
437 | dma_addr_t pdata; | |
438 | int ret = 0; | |
439 | ||
440 | /* bits 35:4 for 4965 */ | |
46bc8d4b SG |
441 | pinst = il->ucode_code.p_addr >> 4; |
442 | pdata = il->ucode_data_backup.p_addr >> 4; | |
4bc85c13 WYG |
443 | |
444 | /* Tell bootstrap uCode where to find image to load */ | |
db54eb57 SG |
445 | il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst); |
446 | il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata); | |
e7392364 | 447 | il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len); |
4bc85c13 WYG |
448 | |
449 | /* Inst byte count must be last to set up, bit 31 signals uCode | |
450 | * that all new ptr/size info is in place */ | |
db54eb57 | 451 | il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, |
e7392364 | 452 | il->ucode_code.len | BSM_DRAM_INST_LOAD); |
58de00a4 | 453 | D_INFO("Runtime uCode pointers are set.\n"); |
4bc85c13 WYG |
454 | |
455 | return ret; | |
456 | } | |
457 | ||
458 | /** | |
4d69c752 | 459 | * il4965_init_alive_start - Called after N_ALIVE notification received |
4bc85c13 | 460 | * |
4d69c752 | 461 | * Called after N_ALIVE notification received from "initialize" uCode. |
4bc85c13 WYG |
462 | * |
463 | * The 4965 "initialize" ALIVE reply contains calibration data for: | |
46bc8d4b | 464 | * Voltage, temperature, and MIMO tx gain correction, now stored in il |
4bc85c13 WYG |
465 | * (3945 does not contain this data). |
466 | * | |
467 | * Tell "initialize" uCode to go ahead and load the runtime uCode. | |
468 | */ | |
e7392364 SG |
469 | static void |
470 | il4965_init_alive_start(struct il_priv *il) | |
4bc85c13 WYG |
471 | { |
472 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
473 | * This is a paranoid check, because we would not have gotten the | |
474 | * "initialize" alive if code weren't properly loaded. */ | |
46bc8d4b | 475 | if (il4965_verify_ucode(il)) { |
4bc85c13 WYG |
476 | /* Runtime instruction load was bad; |
477 | * take it all the way back down so we can try again */ | |
58de00a4 | 478 | D_INFO("Bad \"initialize\" uCode load.\n"); |
4bc85c13 WYG |
479 | goto restart; |
480 | } | |
481 | ||
482 | /* Calculate temperature */ | |
46bc8d4b | 483 | il->temperature = il4965_hw_get_temperature(il); |
4bc85c13 WYG |
484 | |
485 | /* Send pointers to protocol/runtime uCode image ... init code will | |
486 | * load and launch runtime uCode, which will send us another "Alive" | |
487 | * notification. */ | |
58de00a4 | 488 | D_INFO("Initialization Alive received.\n"); |
46bc8d4b | 489 | if (il4965_set_ucode_ptrs(il)) { |
4bc85c13 WYG |
490 | /* Runtime instruction load won't happen; |
491 | * take it all the way back down so we can try again */ | |
58de00a4 | 492 | D_INFO("Couldn't set up uCode pointers.\n"); |
4bc85c13 WYG |
493 | goto restart; |
494 | } | |
495 | return; | |
496 | ||
497 | restart: | |
46bc8d4b | 498 | queue_work(il->workqueue, &il->restart); |
4bc85c13 WYG |
499 | } |
500 | ||
e7392364 SG |
501 | static bool |
502 | iw4965_is_ht40_channel(__le32 rxon_flags) | |
4bc85c13 | 503 | { |
e7392364 SG |
504 | int chan_mod = |
505 | le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK) >> | |
506 | RXON_FLG_CHANNEL_MODE_POS; | |
232913b5 SG |
507 | return (chan_mod == CHANNEL_MODE_PURE_40 || |
508 | chan_mod == CHANNEL_MODE_MIXED); | |
4bc85c13 WYG |
509 | } |
510 | ||
f03ee2a8 | 511 | void |
e7392364 | 512 | il4965_nic_config(struct il_priv *il) |
4bc85c13 WYG |
513 | { |
514 | unsigned long flags; | |
515 | u16 radio_cfg; | |
516 | ||
46bc8d4b | 517 | spin_lock_irqsave(&il->lock, flags); |
4bc85c13 | 518 | |
46bc8d4b | 519 | radio_cfg = il_eeprom_query16(il, EEPROM_RADIO_CONFIG); |
4bc85c13 WYG |
520 | |
521 | /* write radio config values to register */ | |
522 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX) | |
46bc8d4b | 523 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
e7392364 SG |
524 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | |
525 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
526 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
4bc85c13 WYG |
527 | |
528 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
46bc8d4b | 529 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
e7392364 SG |
530 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | |
531 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
4bc85c13 | 532 | |
e7392364 | 533 | il->calib_info = |
1722f8e1 SG |
534 | (struct il_eeprom_calib_info *) |
535 | il_eeprom_query_addr(il, EEPROM_4965_CALIB_TXPOWER_OFFSET); | |
4bc85c13 | 536 | |
46bc8d4b | 537 | spin_unlock_irqrestore(&il->lock, flags); |
4bc85c13 WYG |
538 | } |
539 | ||
540 | /* Reset differential Rx gains in NIC to prepare for chain noise calibration. | |
541 | * Called after every association, but this runs only once! | |
542 | * ... once chain noise is calibrated the first time, it's good forever. */ | |
e7392364 SG |
543 | static void |
544 | il4965_chain_noise_reset(struct il_priv *il) | |
4bc85c13 | 545 | { |
46bc8d4b | 546 | struct il_chain_noise_data *data = &(il->chain_noise_data); |
4bc85c13 | 547 | |
e7392364 | 548 | if (data->state == IL_CHAIN_NOISE_ALIVE && il_is_any_associated(il)) { |
e2ebc833 | 549 | struct il_calib_diff_gain_cmd cmd; |
4bc85c13 WYG |
550 | |
551 | /* clear data for chain noise calibration algorithm */ | |
552 | data->chain_noise_a = 0; | |
553 | data->chain_noise_b = 0; | |
554 | data->chain_noise_c = 0; | |
555 | data->chain_signal_a = 0; | |
556 | data->chain_signal_b = 0; | |
557 | data->chain_signal_c = 0; | |
558 | data->beacon_count = 0; | |
559 | ||
560 | memset(&cmd, 0, sizeof(cmd)); | |
e2ebc833 | 561 | cmd.hdr.op_code = IL_PHY_CALIBRATE_DIFF_GAIN_CMD; |
4bc85c13 WYG |
562 | cmd.diff_gain_a = 0; |
563 | cmd.diff_gain_b = 0; | |
564 | cmd.diff_gain_c = 0; | |
e7392364 SG |
565 | if (il_send_cmd_pdu(il, C_PHY_CALIBRATION, sizeof(cmd), &cmd)) |
566 | IL_ERR("Could not send C_PHY_CALIBRATION\n"); | |
e2ebc833 | 567 | data->state = IL_CHAIN_NOISE_ACCUMULATE; |
58de00a4 | 568 | D_CALIB("Run chain_noise_calibrate\n"); |
4bc85c13 WYG |
569 | } |
570 | } | |
571 | ||
e7392364 SG |
572 | static s32 |
573 | il4965_math_div_round(s32 num, s32 denom, s32 * res) | |
4bc85c13 WYG |
574 | { |
575 | s32 sign = 1; | |
576 | ||
577 | if (num < 0) { | |
578 | sign = -sign; | |
579 | num = -num; | |
580 | } | |
581 | if (denom < 0) { | |
582 | sign = -sign; | |
583 | denom = -denom; | |
584 | } | |
585 | *res = 1; | |
586 | *res = ((num * 2 + denom) / (denom * 2)) * sign; | |
587 | ||
588 | return 1; | |
589 | } | |
590 | ||
591 | /** | |
e2ebc833 | 592 | * il4965_get_voltage_compensation - Power supply voltage comp for txpower |
4bc85c13 WYG |
593 | * |
594 | * Determines power supply voltage compensation for txpower calculations. | |
0c2c8852 | 595 | * Returns number of 1/2-dB steps to subtract from gain table idx, |
4bc85c13 WYG |
596 | * to compensate for difference between power supply voltage during |
597 | * factory measurements, vs. current power supply voltage. | |
598 | * | |
599 | * Voltage indication is higher for lower voltage. | |
0c2c8852 | 600 | * Lower voltage requires more gain (lower gain table idx). |
4bc85c13 | 601 | */ |
e7392364 SG |
602 | static s32 |
603 | il4965_get_voltage_compensation(s32 eeprom_voltage, s32 current_voltage) | |
4bc85c13 WYG |
604 | { |
605 | s32 comp = 0; | |
606 | ||
232913b5 SG |
607 | if (TX_POWER_IL_ILLEGAL_VOLTAGE == eeprom_voltage || |
608 | TX_POWER_IL_ILLEGAL_VOLTAGE == current_voltage) | |
4bc85c13 WYG |
609 | return 0; |
610 | ||
e2ebc833 | 611 | il4965_math_div_round(current_voltage - eeprom_voltage, |
e7392364 | 612 | TX_POWER_IL_VOLTAGE_CODES_PER_03V, &comp); |
4bc85c13 WYG |
613 | |
614 | if (current_voltage > eeprom_voltage) | |
615 | comp *= 2; | |
616 | if ((comp < -2) || (comp > 2)) | |
617 | comp = 0; | |
618 | ||
619 | return comp; | |
620 | } | |
621 | ||
e7392364 SG |
622 | static s32 |
623 | il4965_get_tx_atten_grp(u16 channel) | |
4bc85c13 | 624 | { |
e2ebc833 SG |
625 | if (channel >= CALIB_IL_TX_ATTEN_GR5_FCH && |
626 | channel <= CALIB_IL_TX_ATTEN_GR5_LCH) | |
4bc85c13 WYG |
627 | return CALIB_CH_GROUP_5; |
628 | ||
e2ebc833 SG |
629 | if (channel >= CALIB_IL_TX_ATTEN_GR1_FCH && |
630 | channel <= CALIB_IL_TX_ATTEN_GR1_LCH) | |
4bc85c13 WYG |
631 | return CALIB_CH_GROUP_1; |
632 | ||
e2ebc833 SG |
633 | if (channel >= CALIB_IL_TX_ATTEN_GR2_FCH && |
634 | channel <= CALIB_IL_TX_ATTEN_GR2_LCH) | |
4bc85c13 WYG |
635 | return CALIB_CH_GROUP_2; |
636 | ||
e2ebc833 SG |
637 | if (channel >= CALIB_IL_TX_ATTEN_GR3_FCH && |
638 | channel <= CALIB_IL_TX_ATTEN_GR3_LCH) | |
4bc85c13 WYG |
639 | return CALIB_CH_GROUP_3; |
640 | ||
e2ebc833 SG |
641 | if (channel >= CALIB_IL_TX_ATTEN_GR4_FCH && |
642 | channel <= CALIB_IL_TX_ATTEN_GR4_LCH) | |
4bc85c13 WYG |
643 | return CALIB_CH_GROUP_4; |
644 | ||
8e638188 | 645 | return -EINVAL; |
4bc85c13 WYG |
646 | } |
647 | ||
e7392364 SG |
648 | static u32 |
649 | il4965_get_sub_band(const struct il_priv *il, u32 channel) | |
4bc85c13 WYG |
650 | { |
651 | s32 b = -1; | |
652 | ||
653 | for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) { | |
46bc8d4b | 654 | if (il->calib_info->band_info[b].ch_from == 0) |
4bc85c13 WYG |
655 | continue; |
656 | ||
232913b5 SG |
657 | if (channel >= il->calib_info->band_info[b].ch_from && |
658 | channel <= il->calib_info->band_info[b].ch_to) | |
4bc85c13 WYG |
659 | break; |
660 | } | |
661 | ||
662 | return b; | |
663 | } | |
664 | ||
e7392364 SG |
665 | static s32 |
666 | il4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2) | |
4bc85c13 WYG |
667 | { |
668 | s32 val; | |
669 | ||
670 | if (x2 == x1) | |
671 | return y1; | |
672 | else { | |
e2ebc833 | 673 | il4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val); |
4bc85c13 WYG |
674 | return val + y2; |
675 | } | |
676 | } | |
677 | ||
678 | /** | |
e2ebc833 | 679 | * il4965_interpolate_chan - Interpolate factory measurements for one channel |
4bc85c13 WYG |
680 | * |
681 | * Interpolates factory measurements from the two sample channels within a | |
682 | * sub-band, to apply to channel of interest. Interpolation is proportional to | |
683 | * differences in channel frequencies, which is proportional to differences | |
684 | * in channel number. | |
685 | */ | |
e7392364 SG |
686 | static int |
687 | il4965_interpolate_chan(struct il_priv *il, u32 channel, | |
688 | struct il_eeprom_calib_ch_info *chan_info) | |
4bc85c13 WYG |
689 | { |
690 | s32 s = -1; | |
691 | u32 c; | |
692 | u32 m; | |
e2ebc833 SG |
693 | const struct il_eeprom_calib_measure *m1; |
694 | const struct il_eeprom_calib_measure *m2; | |
695 | struct il_eeprom_calib_measure *omeas; | |
4bc85c13 WYG |
696 | u32 ch_i1; |
697 | u32 ch_i2; | |
698 | ||
46bc8d4b | 699 | s = il4965_get_sub_band(il, channel); |
4bc85c13 | 700 | if (s >= EEPROM_TX_POWER_BANDS) { |
9406f797 | 701 | IL_ERR("Tx Power can not find channel %d\n", channel); |
4bc85c13 WYG |
702 | return -1; |
703 | } | |
704 | ||
46bc8d4b SG |
705 | ch_i1 = il->calib_info->band_info[s].ch1.ch_num; |
706 | ch_i2 = il->calib_info->band_info[s].ch2.ch_num; | |
4bc85c13 WYG |
707 | chan_info->ch_num = (u8) channel; |
708 | ||
e7392364 SG |
709 | D_TXPOWER("channel %d subband %d factory cal ch %d & %d\n", channel, s, |
710 | ch_i1, ch_i2); | |
4bc85c13 WYG |
711 | |
712 | for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) { | |
713 | for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) { | |
46bc8d4b | 714 | m1 = &(il->calib_info->band_info[s].ch1. |
4bc85c13 | 715 | measurements[c][m]); |
46bc8d4b | 716 | m2 = &(il->calib_info->band_info[s].ch2. |
4bc85c13 WYG |
717 | measurements[c][m]); |
718 | omeas = &(chan_info->measurements[c][m]); | |
719 | ||
720 | omeas->actual_pow = | |
e2ebc833 | 721 | (u8) il4965_interpolate_value(channel, ch_i1, |
e7392364 SG |
722 | m1->actual_pow, ch_i2, |
723 | m2->actual_pow); | |
4bc85c13 | 724 | omeas->gain_idx = |
e2ebc833 | 725 | (u8) il4965_interpolate_value(channel, ch_i1, |
e7392364 SG |
726 | m1->gain_idx, ch_i2, |
727 | m2->gain_idx); | |
4bc85c13 | 728 | omeas->temperature = |
e2ebc833 | 729 | (u8) il4965_interpolate_value(channel, ch_i1, |
e7392364 SG |
730 | m1->temperature, |
731 | ch_i2, | |
732 | m2->temperature); | |
4bc85c13 | 733 | omeas->pa_det = |
e2ebc833 | 734 | (s8) il4965_interpolate_value(channel, ch_i1, |
e7392364 SG |
735 | m1->pa_det, ch_i2, |
736 | m2->pa_det); | |
737 | ||
738 | D_TXPOWER("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, | |
739 | m, m1->actual_pow, m2->actual_pow, | |
740 | omeas->actual_pow); | |
741 | D_TXPOWER("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, | |
742 | m, m1->gain_idx, m2->gain_idx, | |
743 | omeas->gain_idx); | |
744 | D_TXPOWER("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, | |
745 | m, m1->pa_det, m2->pa_det, omeas->pa_det); | |
746 | D_TXPOWER("chain %d meas %d T1=%d T2=%d T=%d\n", c, | |
747 | m, m1->temperature, m2->temperature, | |
748 | omeas->temperature); | |
4bc85c13 WYG |
749 | } |
750 | } | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | /* bit-rate-dependent table to prevent Tx distortion, in half-dB units, | |
756 | * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */ | |
757 | static s32 back_off_table[] = { | |
758 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */ | |
759 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */ | |
760 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */ | |
761 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */ | |
762 | 10 /* CCK */ | |
763 | }; | |
764 | ||
765 | /* Thermal compensation values for txpower for various frequency ranges ... | |
766 | * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */ | |
e2ebc833 | 767 | static struct il4965_txpower_comp_entry { |
4bc85c13 WYG |
768 | s32 degrees_per_05db_a; |
769 | s32 degrees_per_05db_a_denom; | |
770 | } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = { | |
e7392364 SG |
771 | { |
772 | 9, 2}, /* group 0 5.2, ch 34-43 */ | |
773 | { | |
774 | 4, 1}, /* group 1 5.2, ch 44-70 */ | |
775 | { | |
776 | 4, 1}, /* group 2 5.2, ch 71-124 */ | |
777 | { | |
778 | 4, 1}, /* group 3 5.2, ch 125-200 */ | |
779 | { | |
780 | 3, 1} /* group 4 2.4, ch all */ | |
4bc85c13 WYG |
781 | }; |
782 | ||
e7392364 SG |
783 | static s32 |
784 | get_min_power_idx(s32 rate_power_idx, u32 band) | |
4bc85c13 WYG |
785 | { |
786 | if (!band) { | |
0c2c8852 | 787 | if ((rate_power_idx & 7) <= 4) |
2d09b062 | 788 | return MIN_TX_GAIN_IDX_52GHZ_EXT; |
4bc85c13 | 789 | } |
2d09b062 | 790 | return MIN_TX_GAIN_IDX; |
4bc85c13 WYG |
791 | } |
792 | ||
793 | struct gain_entry { | |
794 | u8 dsp; | |
795 | u8 radio; | |
796 | }; | |
797 | ||
798 | static const struct gain_entry gain_table[2][108] = { | |
0c2c8852 | 799 | /* 5.2GHz power gain idx table */ |
4bc85c13 WYG |
800 | { |
801 | {123, 0x3F}, /* highest txpower */ | |
802 | {117, 0x3F}, | |
803 | {110, 0x3F}, | |
804 | {104, 0x3F}, | |
805 | {98, 0x3F}, | |
806 | {110, 0x3E}, | |
807 | {104, 0x3E}, | |
808 | {98, 0x3E}, | |
809 | {110, 0x3D}, | |
810 | {104, 0x3D}, | |
811 | {98, 0x3D}, | |
812 | {110, 0x3C}, | |
813 | {104, 0x3C}, | |
814 | {98, 0x3C}, | |
815 | {110, 0x3B}, | |
816 | {104, 0x3B}, | |
817 | {98, 0x3B}, | |
818 | {110, 0x3A}, | |
819 | {104, 0x3A}, | |
820 | {98, 0x3A}, | |
821 | {110, 0x39}, | |
822 | {104, 0x39}, | |
823 | {98, 0x39}, | |
824 | {110, 0x38}, | |
825 | {104, 0x38}, | |
826 | {98, 0x38}, | |
827 | {110, 0x37}, | |
828 | {104, 0x37}, | |
829 | {98, 0x37}, | |
830 | {110, 0x36}, | |
831 | {104, 0x36}, | |
832 | {98, 0x36}, | |
833 | {110, 0x35}, | |
834 | {104, 0x35}, | |
835 | {98, 0x35}, | |
836 | {110, 0x34}, | |
837 | {104, 0x34}, | |
838 | {98, 0x34}, | |
839 | {110, 0x33}, | |
840 | {104, 0x33}, | |
841 | {98, 0x33}, | |
842 | {110, 0x32}, | |
843 | {104, 0x32}, | |
844 | {98, 0x32}, | |
845 | {110, 0x31}, | |
846 | {104, 0x31}, | |
847 | {98, 0x31}, | |
848 | {110, 0x30}, | |
849 | {104, 0x30}, | |
850 | {98, 0x30}, | |
851 | {110, 0x25}, | |
852 | {104, 0x25}, | |
853 | {98, 0x25}, | |
854 | {110, 0x24}, | |
855 | {104, 0x24}, | |
856 | {98, 0x24}, | |
857 | {110, 0x23}, | |
858 | {104, 0x23}, | |
859 | {98, 0x23}, | |
860 | {110, 0x22}, | |
861 | {104, 0x18}, | |
862 | {98, 0x18}, | |
863 | {110, 0x17}, | |
864 | {104, 0x17}, | |
865 | {98, 0x17}, | |
866 | {110, 0x16}, | |
867 | {104, 0x16}, | |
868 | {98, 0x16}, | |
869 | {110, 0x15}, | |
870 | {104, 0x15}, | |
871 | {98, 0x15}, | |
872 | {110, 0x14}, | |
873 | {104, 0x14}, | |
874 | {98, 0x14}, | |
875 | {110, 0x13}, | |
876 | {104, 0x13}, | |
877 | {98, 0x13}, | |
878 | {110, 0x12}, | |
879 | {104, 0x08}, | |
880 | {98, 0x08}, | |
881 | {110, 0x07}, | |
882 | {104, 0x07}, | |
883 | {98, 0x07}, | |
884 | {110, 0x06}, | |
885 | {104, 0x06}, | |
886 | {98, 0x06}, | |
887 | {110, 0x05}, | |
888 | {104, 0x05}, | |
889 | {98, 0x05}, | |
890 | {110, 0x04}, | |
891 | {104, 0x04}, | |
892 | {98, 0x04}, | |
893 | {110, 0x03}, | |
894 | {104, 0x03}, | |
895 | {98, 0x03}, | |
896 | {110, 0x02}, | |
897 | {104, 0x02}, | |
898 | {98, 0x02}, | |
899 | {110, 0x01}, | |
900 | {104, 0x01}, | |
901 | {98, 0x01}, | |
902 | {110, 0x00}, | |
903 | {104, 0x00}, | |
904 | {98, 0x00}, | |
905 | {93, 0x00}, | |
906 | {88, 0x00}, | |
907 | {83, 0x00}, | |
908 | {78, 0x00}, | |
909 | }, | |
0c2c8852 | 910 | /* 2.4GHz power gain idx table */ |
4bc85c13 WYG |
911 | { |
912 | {110, 0x3f}, /* highest txpower */ | |
913 | {104, 0x3f}, | |
914 | {98, 0x3f}, | |
915 | {110, 0x3e}, | |
916 | {104, 0x3e}, | |
917 | {98, 0x3e}, | |
918 | {110, 0x3d}, | |
919 | {104, 0x3d}, | |
920 | {98, 0x3d}, | |
921 | {110, 0x3c}, | |
922 | {104, 0x3c}, | |
923 | {98, 0x3c}, | |
924 | {110, 0x3b}, | |
925 | {104, 0x3b}, | |
926 | {98, 0x3b}, | |
927 | {110, 0x3a}, | |
928 | {104, 0x3a}, | |
929 | {98, 0x3a}, | |
930 | {110, 0x39}, | |
931 | {104, 0x39}, | |
932 | {98, 0x39}, | |
933 | {110, 0x38}, | |
934 | {104, 0x38}, | |
935 | {98, 0x38}, | |
936 | {110, 0x37}, | |
937 | {104, 0x37}, | |
938 | {98, 0x37}, | |
939 | {110, 0x36}, | |
940 | {104, 0x36}, | |
941 | {98, 0x36}, | |
942 | {110, 0x35}, | |
943 | {104, 0x35}, | |
944 | {98, 0x35}, | |
945 | {110, 0x34}, | |
946 | {104, 0x34}, | |
947 | {98, 0x34}, | |
948 | {110, 0x33}, | |
949 | {104, 0x33}, | |
950 | {98, 0x33}, | |
951 | {110, 0x32}, | |
952 | {104, 0x32}, | |
953 | {98, 0x32}, | |
954 | {110, 0x31}, | |
955 | {104, 0x31}, | |
956 | {98, 0x31}, | |
957 | {110, 0x30}, | |
958 | {104, 0x30}, | |
959 | {98, 0x30}, | |
960 | {110, 0x6}, | |
961 | {104, 0x6}, | |
962 | {98, 0x6}, | |
963 | {110, 0x5}, | |
964 | {104, 0x5}, | |
965 | {98, 0x5}, | |
966 | {110, 0x4}, | |
967 | {104, 0x4}, | |
968 | {98, 0x4}, | |
969 | {110, 0x3}, | |
970 | {104, 0x3}, | |
971 | {98, 0x3}, | |
972 | {110, 0x2}, | |
973 | {104, 0x2}, | |
974 | {98, 0x2}, | |
975 | {110, 0x1}, | |
976 | {104, 0x1}, | |
977 | {98, 0x1}, | |
978 | {110, 0x0}, | |
979 | {104, 0x0}, | |
980 | {98, 0x0}, | |
981 | {97, 0}, | |
982 | {96, 0}, | |
983 | {95, 0}, | |
984 | {94, 0}, | |
985 | {93, 0}, | |
986 | {92, 0}, | |
987 | {91, 0}, | |
988 | {90, 0}, | |
989 | {89, 0}, | |
990 | {88, 0}, | |
991 | {87, 0}, | |
992 | {86, 0}, | |
993 | {85, 0}, | |
994 | {84, 0}, | |
995 | {83, 0}, | |
996 | {82, 0}, | |
997 | {81, 0}, | |
998 | {80, 0}, | |
999 | {79, 0}, | |
1000 | {78, 0}, | |
1001 | {77, 0}, | |
1002 | {76, 0}, | |
1003 | {75, 0}, | |
1004 | {74, 0}, | |
1005 | {73, 0}, | |
1006 | {72, 0}, | |
1007 | {71, 0}, | |
1008 | {70, 0}, | |
1009 | {69, 0}, | |
1010 | {68, 0}, | |
1011 | {67, 0}, | |
1012 | {66, 0}, | |
1013 | {65, 0}, | |
1014 | {64, 0}, | |
1015 | {63, 0}, | |
1016 | {62, 0}, | |
1017 | {61, 0}, | |
1018 | {60, 0}, | |
1019 | {59, 0}, | |
1020 | } | |
1021 | }; | |
1022 | ||
e7392364 SG |
1023 | static int |
1024 | il4965_fill_txpower_tbl(struct il_priv *il, u8 band, u16 channel, u8 is_ht40, | |
1025 | u8 ctrl_chan_high, | |
1026 | struct il4965_tx_power_db *tx_power_tbl) | |
4bc85c13 WYG |
1027 | { |
1028 | u8 saturation_power; | |
1029 | s32 target_power; | |
1030 | s32 user_target_power; | |
1031 | s32 power_limit; | |
1032 | s32 current_temp; | |
1033 | s32 reg_limit; | |
1034 | s32 current_regulatory; | |
1035 | s32 txatten_grp = CALIB_CH_GROUP_MAX; | |
1036 | int i; | |
1037 | int c; | |
e2ebc833 SG |
1038 | const struct il_channel_info *ch_info = NULL; |
1039 | struct il_eeprom_calib_ch_info ch_eeprom_info; | |
1040 | const struct il_eeprom_calib_measure *measurement; | |
4bc85c13 WYG |
1041 | s16 voltage; |
1042 | s32 init_voltage; | |
1043 | s32 voltage_compensation; | |
1044 | s32 degrees_per_05db_num; | |
1045 | s32 degrees_per_05db_denom; | |
1046 | s32 factory_temp; | |
1047 | s32 temperature_comp[2]; | |
0c2c8852 | 1048 | s32 factory_gain_idx[2]; |
4bc85c13 | 1049 | s32 factory_actual_pwr[2]; |
0c2c8852 | 1050 | s32 power_idx; |
4bc85c13 WYG |
1051 | |
1052 | /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units | |
0c2c8852 | 1053 | * are used for idxing into txpower table) */ |
46bc8d4b | 1054 | user_target_power = 2 * il->tx_power_user_lmt; |
4bc85c13 WYG |
1055 | |
1056 | /* Get current (RXON) channel, band, width */ | |
e7392364 | 1057 | D_TXPOWER("chan %d band %d is_ht40 %d\n", channel, band, is_ht40); |
4bc85c13 | 1058 | |
46bc8d4b | 1059 | ch_info = il_get_channel_info(il, il->band, channel); |
4bc85c13 | 1060 | |
e2ebc833 | 1061 | if (!il_is_channel_valid(ch_info)) |
4bc85c13 WYG |
1062 | return -EINVAL; |
1063 | ||
1064 | /* get txatten group, used to select 1) thermal txpower adjustment | |
1065 | * and 2) mimo txpower balance between Tx chains. */ | |
e2ebc833 | 1066 | txatten_grp = il4965_get_tx_atten_grp(channel); |
4bc85c13 | 1067 | if (txatten_grp < 0) { |
e7392364 | 1068 | IL_ERR("Can't find txatten group for channel %d.\n", channel); |
5c30c76e | 1069 | return txatten_grp; |
4bc85c13 WYG |
1070 | } |
1071 | ||
e7392364 SG |
1072 | D_TXPOWER("channel %d belongs to txatten group %d\n", channel, |
1073 | txatten_grp); | |
4bc85c13 WYG |
1074 | |
1075 | if (is_ht40) { | |
1076 | if (ctrl_chan_high) | |
1077 | channel -= 2; | |
1078 | else | |
1079 | channel += 2; | |
1080 | } | |
1081 | ||
1082 | /* hardware txpower limits ... | |
1083 | * saturation (clipping distortion) txpowers are in half-dBm */ | |
1084 | if (band) | |
46bc8d4b | 1085 | saturation_power = il->calib_info->saturation_power24; |
4bc85c13 | 1086 | else |
46bc8d4b | 1087 | saturation_power = il->calib_info->saturation_power52; |
4bc85c13 | 1088 | |
e2ebc833 SG |
1089 | if (saturation_power < IL_TX_POWER_SATURATION_MIN || |
1090 | saturation_power > IL_TX_POWER_SATURATION_MAX) { | |
4bc85c13 | 1091 | if (band) |
e2ebc833 | 1092 | saturation_power = IL_TX_POWER_DEFAULT_SATURATION_24; |
4bc85c13 | 1093 | else |
e2ebc833 | 1094 | saturation_power = IL_TX_POWER_DEFAULT_SATURATION_52; |
4bc85c13 WYG |
1095 | } |
1096 | ||
1097 | /* regulatory txpower limits ... reg_limit values are in half-dBm, | |
1098 | * max_power_avg values are in dBm, convert * 2 */ | |
1099 | if (is_ht40) | |
1100 | reg_limit = ch_info->ht40_max_power_avg * 2; | |
1101 | else | |
1102 | reg_limit = ch_info->max_power_avg * 2; | |
1103 | ||
e2ebc833 SG |
1104 | if ((reg_limit < IL_TX_POWER_REGULATORY_MIN) || |
1105 | (reg_limit > IL_TX_POWER_REGULATORY_MAX)) { | |
4bc85c13 | 1106 | if (band) |
e2ebc833 | 1107 | reg_limit = IL_TX_POWER_DEFAULT_REGULATORY_24; |
4bc85c13 | 1108 | else |
e2ebc833 | 1109 | reg_limit = IL_TX_POWER_DEFAULT_REGULATORY_52; |
4bc85c13 WYG |
1110 | } |
1111 | ||
1112 | /* Interpolate txpower calibration values for this channel, | |
1113 | * based on factory calibration tests on spaced channels. */ | |
46bc8d4b | 1114 | il4965_interpolate_chan(il, channel, &ch_eeprom_info); |
4bc85c13 WYG |
1115 | |
1116 | /* calculate tx gain adjustment based on power supply voltage */ | |
46bc8d4b | 1117 | voltage = le16_to_cpu(il->calib_info->voltage); |
e7392364 | 1118 | init_voltage = (s32) le32_to_cpu(il->card_alive_init.voltage); |
4bc85c13 | 1119 | voltage_compensation = |
e2ebc833 | 1120 | il4965_get_voltage_compensation(voltage, init_voltage); |
4bc85c13 | 1121 | |
e7392364 SG |
1122 | D_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n", init_voltage, |
1123 | voltage, voltage_compensation); | |
4bc85c13 WYG |
1124 | |
1125 | /* get current temperature (Celsius) */ | |
46bc8d4b SG |
1126 | current_temp = max(il->temperature, IL_TX_POWER_TEMPERATURE_MIN); |
1127 | current_temp = min(il->temperature, IL_TX_POWER_TEMPERATURE_MAX); | |
4bc85c13 WYG |
1128 | current_temp = KELVIN_TO_CELSIUS(current_temp); |
1129 | ||
1130 | /* select thermal txpower adjustment params, based on channel group | |
1131 | * (same frequency group used for mimo txatten adjustment) */ | |
1132 | degrees_per_05db_num = | |
1133 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a; | |
1134 | degrees_per_05db_denom = | |
1135 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom; | |
1136 | ||
1137 | /* get per-chain txpower values from factory measurements */ | |
1138 | for (c = 0; c < 2; c++) { | |
1139 | measurement = &ch_eeprom_info.measurements[c][1]; | |
1140 | ||
1141 | /* txgain adjustment (in half-dB steps) based on difference | |
1142 | * between factory and current temperature */ | |
1143 | factory_temp = measurement->temperature; | |
e7392364 SG |
1144 | il4965_math_div_round((current_temp - |
1145 | factory_temp) * degrees_per_05db_denom, | |
1146 | degrees_per_05db_num, | |
1147 | &temperature_comp[c]); | |
4bc85c13 | 1148 | |
0c2c8852 | 1149 | factory_gain_idx[c] = measurement->gain_idx; |
4bc85c13 WYG |
1150 | factory_actual_pwr[c] = measurement->actual_pow; |
1151 | ||
58de00a4 | 1152 | D_TXPOWER("chain = %d\n", c); |
e7392364 SG |
1153 | D_TXPOWER("fctry tmp %d, " "curr tmp %d, comp %d steps\n", |
1154 | factory_temp, current_temp, temperature_comp[c]); | |
1155 | ||
1156 | D_TXPOWER("fctry idx %d, fctry pwr %d\n", factory_gain_idx[c], | |
1157 | factory_actual_pwr[c]); | |
4bc85c13 WYG |
1158 | } |
1159 | ||
1160 | /* for each of 33 bit-rates (including 1 for CCK) */ | |
3b98c7f4 | 1161 | for (i = 0; i < POWER_TBL_NUM_ENTRIES; i++) { |
4bc85c13 | 1162 | u8 is_mimo_rate; |
e2ebc833 | 1163 | union il4965_tx_power_dual_stream tx_power; |
4bc85c13 WYG |
1164 | |
1165 | /* for mimo, reduce each chain's txpower by half | |
1166 | * (3dB, 6 steps), so total output power is regulatory | |
1167 | * compliant. */ | |
1168 | if (i & 0x8) { | |
e7392364 SG |
1169 | current_regulatory = |
1170 | reg_limit - | |
e2ebc833 | 1171 | IL_TX_POWER_MIMO_REGULATORY_COMPENSATION; |
4bc85c13 WYG |
1172 | is_mimo_rate = 1; |
1173 | } else { | |
1174 | current_regulatory = reg_limit; | |
1175 | is_mimo_rate = 0; | |
1176 | } | |
1177 | ||
1178 | /* find txpower limit, either hardware or regulatory */ | |
1179 | power_limit = saturation_power - back_off_table[i]; | |
1180 | if (power_limit > current_regulatory) | |
1181 | power_limit = current_regulatory; | |
1182 | ||
1183 | /* reduce user's txpower request if necessary | |
1184 | * for this rate on this channel */ | |
1185 | target_power = user_target_power; | |
1186 | if (target_power > power_limit) | |
1187 | target_power = power_limit; | |
1188 | ||
e7392364 SG |
1189 | D_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n", i, |
1190 | saturation_power - back_off_table[i], | |
1191 | current_regulatory, user_target_power, target_power); | |
4bc85c13 WYG |
1192 | |
1193 | /* for each of 2 Tx chains (radio transmitters) */ | |
1194 | for (c = 0; c < 2; c++) { | |
1195 | s32 atten_value; | |
1196 | ||
1197 | if (is_mimo_rate) | |
1198 | atten_value = | |
e7392364 SG |
1199 | (s32) le32_to_cpu(il->card_alive_init. |
1200 | tx_atten[txatten_grp][c]); | |
4bc85c13 WYG |
1201 | else |
1202 | atten_value = 0; | |
1203 | ||
0c2c8852 | 1204 | /* calculate idx; higher idx means lower txpower */ |
e7392364 SG |
1205 | power_idx = |
1206 | (u8) (factory_gain_idx[c] - | |
1207 | (target_power - factory_actual_pwr[c]) - | |
1208 | temperature_comp[c] - voltage_compensation + | |
1209 | atten_value); | |
4bc85c13 | 1210 | |
0c2c8852 SG |
1211 | /* D_TXPOWER("calculated txpower idx %d\n", |
1212 | power_idx); */ | |
4bc85c13 | 1213 | |
0c2c8852 SG |
1214 | if (power_idx < get_min_power_idx(i, band)) |
1215 | power_idx = get_min_power_idx(i, band); | |
4bc85c13 | 1216 | |
0c2c8852 | 1217 | /* adjust 5 GHz idx to support negative idxes */ |
4bc85c13 | 1218 | if (!band) |
0c2c8852 | 1219 | power_idx += 9; |
4bc85c13 WYG |
1220 | |
1221 | /* CCK, rate 32, reduce txpower for CCK */ | |
3b98c7f4 | 1222 | if (i == POWER_TBL_CCK_ENTRY) |
0c2c8852 | 1223 | power_idx += |
e2ebc833 | 1224 | IL_TX_POWER_CCK_COMPENSATION_C_STEP; |
4bc85c13 WYG |
1225 | |
1226 | /* stay within the table! */ | |
0c2c8852 | 1227 | if (power_idx > 107) { |
e7392364 | 1228 | IL_WARN("txpower idx %d > 107\n", power_idx); |
0c2c8852 | 1229 | power_idx = 107; |
4bc85c13 | 1230 | } |
0c2c8852 | 1231 | if (power_idx < 0) { |
e7392364 | 1232 | IL_WARN("txpower idx %d < 0\n", power_idx); |
0c2c8852 | 1233 | power_idx = 0; |
4bc85c13 WYG |
1234 | } |
1235 | ||
1236 | /* fill txpower command for this rate/chain */ | |
1237 | tx_power.s.radio_tx_gain[c] = | |
e7392364 | 1238 | gain_table[band][power_idx].radio; |
4bc85c13 | 1239 | tx_power.s.dsp_predis_atten[c] = |
e7392364 | 1240 | gain_table[band][power_idx].dsp; |
4bc85c13 | 1241 | |
0c2c8852 | 1242 | D_TXPOWER("chain %d mimo %d idx %d " |
e7392364 SG |
1243 | "gain 0x%02x dsp %d\n", c, atten_value, |
1244 | power_idx, tx_power.s.radio_tx_gain[c], | |
1245 | tx_power.s.dsp_predis_atten[c]); | |
1246 | } /* for each chain */ | |
4bc85c13 WYG |
1247 | |
1248 | tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw); | |
1249 | ||
e7392364 | 1250 | } /* for each rate */ |
4bc85c13 WYG |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | /** | |
e2ebc833 | 1256 | * il4965_send_tx_power - Configure the TXPOWER level user limit |
4bc85c13 WYG |
1257 | * |
1258 | * Uses the active RXON for channel, band, and characteristics (ht40, high) | |
46bc8d4b | 1259 | * The power limit is taken from il->tx_power_user_lmt. |
4bc85c13 | 1260 | */ |
e7392364 SG |
1261 | static int |
1262 | il4965_send_tx_power(struct il_priv *il) | |
4bc85c13 | 1263 | { |
e2ebc833 | 1264 | struct il4965_txpowertable_cmd cmd = { 0 }; |
4bc85c13 WYG |
1265 | int ret; |
1266 | u8 band = 0; | |
1267 | bool is_ht40 = false; | |
1268 | u8 ctrl_chan_high = 0; | |
4bc85c13 | 1269 | |
e7392364 SG |
1270 | if (WARN_ONCE |
1271 | (test_bit(S_SCAN_HW, &il->status), | |
1272 | "TX Power requested while scanning!\n")) | |
4bc85c13 WYG |
1273 | return -EAGAIN; |
1274 | ||
46bc8d4b | 1275 | band = il->band == IEEE80211_BAND_2GHZ; |
4bc85c13 | 1276 | |
c8b03958 | 1277 | is_ht40 = iw4965_is_ht40_channel(il->active.flags); |
4bc85c13 | 1278 | |
c8b03958 | 1279 | if (is_ht40 && (il->active.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) |
4bc85c13 WYG |
1280 | ctrl_chan_high = 1; |
1281 | ||
1282 | cmd.band = band; | |
c8b03958 | 1283 | cmd.channel = il->active.channel; |
4bc85c13 | 1284 | |
e7392364 | 1285 | ret = |
c8b03958 | 1286 | il4965_fill_txpower_tbl(il, band, le16_to_cpu(il->active.channel), |
e7392364 | 1287 | is_ht40, ctrl_chan_high, &cmd.tx_power); |
4bc85c13 WYG |
1288 | if (ret) |
1289 | goto out; | |
1290 | ||
e7392364 | 1291 | ret = il_send_cmd_pdu(il, C_TX_PWR_TBL, sizeof(cmd), &cmd); |
4bc85c13 WYG |
1292 | |
1293 | out: | |
1294 | return ret; | |
1295 | } | |
1296 | ||
e7392364 | 1297 | static int |
83007196 | 1298 | il4965_send_rxon_assoc(struct il_priv *il) |
4bc85c13 WYG |
1299 | { |
1300 | int ret = 0; | |
e2ebc833 | 1301 | struct il4965_rxon_assoc_cmd rxon_assoc; |
c8b03958 SG |
1302 | const struct il_rxon_cmd *rxon1 = &il->staging; |
1303 | const struct il_rxon_cmd *rxon2 = &il->active; | |
4bc85c13 | 1304 | |
232913b5 SG |
1305 | if (rxon1->flags == rxon2->flags && |
1306 | rxon1->filter_flags == rxon2->filter_flags && | |
1307 | rxon1->cck_basic_rates == rxon2->cck_basic_rates && | |
1308 | rxon1->ofdm_ht_single_stream_basic_rates == | |
e7392364 | 1309 | rxon2->ofdm_ht_single_stream_basic_rates && |
232913b5 | 1310 | rxon1->ofdm_ht_dual_stream_basic_rates == |
e7392364 | 1311 | rxon2->ofdm_ht_dual_stream_basic_rates && |
232913b5 SG |
1312 | rxon1->rx_chain == rxon2->rx_chain && |
1313 | rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) { | |
58de00a4 | 1314 | D_INFO("Using current RXON_ASSOC. Not resending.\n"); |
4bc85c13 WYG |
1315 | return 0; |
1316 | } | |
1317 | ||
c8b03958 SG |
1318 | rxon_assoc.flags = il->staging.flags; |
1319 | rxon_assoc.filter_flags = il->staging.filter_flags; | |
1320 | rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates; | |
1321 | rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates; | |
4bc85c13 WYG |
1322 | rxon_assoc.reserved = 0; |
1323 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
c8b03958 | 1324 | il->staging.ofdm_ht_single_stream_basic_rates; |
4bc85c13 | 1325 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = |
c8b03958 SG |
1326 | il->staging.ofdm_ht_dual_stream_basic_rates; |
1327 | rxon_assoc.rx_chain_select_flags = il->staging.rx_chain; | |
4bc85c13 | 1328 | |
e7392364 SG |
1329 | ret = |
1330 | il_send_cmd_pdu_async(il, C_RXON_ASSOC, sizeof(rxon_assoc), | |
1331 | &rxon_assoc, NULL); | |
4bc85c13 WYG |
1332 | |
1333 | return ret; | |
1334 | } | |
1335 | ||
e7392364 | 1336 | static int |
83007196 | 1337 | il4965_commit_rxon(struct il_priv *il) |
4bc85c13 WYG |
1338 | { |
1339 | /* cast away the const for active_rxon in this function */ | |
c8b03958 | 1340 | struct il_rxon_cmd *active_rxon = (void *)&il->active; |
4bc85c13 | 1341 | int ret; |
c8b03958 | 1342 | bool new_assoc = !!(il->staging.filter_flags & RXON_FILTER_ASSOC_MSK); |
4bc85c13 | 1343 | |
46bc8d4b | 1344 | if (!il_is_alive(il)) |
4bc85c13 WYG |
1345 | return -EBUSY; |
1346 | ||
4bc85c13 | 1347 | /* always get timestamp with Rx frame */ |
c8b03958 | 1348 | il->staging.flags |= RXON_FLG_TSF2HOST_MSK; |
4bc85c13 | 1349 | |
83007196 | 1350 | ret = il_check_rxon_cmd(il); |
4bc85c13 | 1351 | if (ret) { |
9406f797 | 1352 | IL_ERR("Invalid RXON configuration. Not committing.\n"); |
4bc85c13 WYG |
1353 | return -EINVAL; |
1354 | } | |
1355 | ||
1356 | /* | |
1357 | * receive commit_rxon request | |
1358 | * abort any previous channel switch if still in process | |
1359 | */ | |
a6766ccd | 1360 | if (test_bit(S_CHANNEL_SWITCH_PENDING, &il->status) && |
c8b03958 | 1361 | il->switch_channel != il->staging.channel) { |
58de00a4 | 1362 | D_11H("abort channel switch on %d\n", |
46bc8d4b SG |
1363 | le16_to_cpu(il->switch_channel)); |
1364 | il_chswitch_done(il, false); | |
4bc85c13 WYG |
1365 | } |
1366 | ||
1367 | /* If we don't need to send a full RXON, we can use | |
e2ebc833 | 1368 | * il_rxon_assoc_cmd which is used to reconfigure filter |
4bc85c13 | 1369 | * and other flags for the current radio configuration. */ |
83007196 SG |
1370 | if (!il_full_rxon_required(il)) { |
1371 | ret = il_send_rxon_assoc(il); | |
4bc85c13 | 1372 | if (ret) { |
9406f797 | 1373 | IL_ERR("Error setting RXON_ASSOC (%d)\n", ret); |
4bc85c13 WYG |
1374 | return ret; |
1375 | } | |
1376 | ||
c8b03958 | 1377 | memcpy(active_rxon, &il->staging, sizeof(*active_rxon)); |
83007196 | 1378 | il_print_rx_config_cmd(il); |
17e859a8 SG |
1379 | /* |
1380 | * We do not commit tx power settings while channel changing, | |
1381 | * do it now if tx power changed. | |
1382 | */ | |
46bc8d4b | 1383 | il_set_tx_power(il, il->tx_power_next, false); |
17e859a8 | 1384 | return 0; |
4bc85c13 WYG |
1385 | } |
1386 | ||
1387 | /* If we are currently associated and the new config requires | |
1388 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
1389 | * we must clear the associated from the active configuration | |
1390 | * before we apply the new config */ | |
c8b03958 | 1391 | if (il_is_associated(il) && new_assoc) { |
58de00a4 | 1392 | D_INFO("Toggling associated bit on current RXON\n"); |
4bc85c13 WYG |
1393 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
1394 | ||
e7392364 | 1395 | ret = |
6122d182 | 1396 | il_send_cmd_pdu(il, C_RXON, |
e7392364 | 1397 | sizeof(struct il_rxon_cmd), active_rxon); |
4bc85c13 WYG |
1398 | |
1399 | /* If the mask clearing failed then we set | |
1400 | * active_rxon back to what it was previously */ | |
1401 | if (ret) { | |
1402 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
9406f797 | 1403 | IL_ERR("Error clearing ASSOC_MSK (%d)\n", ret); |
4bc85c13 WYG |
1404 | return ret; |
1405 | } | |
83007196 SG |
1406 | il_clear_ucode_stations(il); |
1407 | il_restore_stations(il); | |
1408 | ret = il4965_restore_default_wep_keys(il); | |
4bc85c13 | 1409 | if (ret) { |
9406f797 | 1410 | IL_ERR("Failed to restore WEP keys (%d)\n", ret); |
4bc85c13 WYG |
1411 | return ret; |
1412 | } | |
1413 | } | |
1414 | ||
e7392364 SG |
1415 | D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n" |
1416 | "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"), | |
c8b03958 | 1417 | le16_to_cpu(il->staging.channel), il->staging.bssid_addr); |
4bc85c13 | 1418 | |
83007196 | 1419 | il_set_rxon_hwcrypto(il, !il->cfg->mod_params->sw_crypto); |
4bc85c13 WYG |
1420 | |
1421 | /* Apply the new configuration | |
1422 | * RXON unassoc clears the station table in uCode so restoration of | |
1423 | * stations is needed after it (the RXON command) completes | |
1424 | */ | |
1425 | if (!new_assoc) { | |
e7392364 | 1426 | ret = |
6122d182 | 1427 | il_send_cmd_pdu(il, C_RXON, |
c8b03958 | 1428 | sizeof(struct il_rxon_cmd), &il->staging); |
4bc85c13 | 1429 | if (ret) { |
9406f797 | 1430 | IL_ERR("Error setting new RXON (%d)\n", ret); |
4bc85c13 WYG |
1431 | return ret; |
1432 | } | |
58de00a4 | 1433 | D_INFO("Return from !new_assoc RXON.\n"); |
c8b03958 | 1434 | memcpy(active_rxon, &il->staging, sizeof(*active_rxon)); |
83007196 SG |
1435 | il_clear_ucode_stations(il); |
1436 | il_restore_stations(il); | |
1437 | ret = il4965_restore_default_wep_keys(il); | |
4bc85c13 | 1438 | if (ret) { |
9406f797 | 1439 | IL_ERR("Failed to restore WEP keys (%d)\n", ret); |
4bc85c13 WYG |
1440 | return ret; |
1441 | } | |
1442 | } | |
1443 | if (new_assoc) { | |
46bc8d4b | 1444 | il->start_calib = 0; |
4bc85c13 WYG |
1445 | /* Apply the new configuration |
1446 | * RXON assoc doesn't clear the station table in uCode, | |
1447 | */ | |
e7392364 | 1448 | ret = |
6122d182 | 1449 | il_send_cmd_pdu(il, C_RXON, |
c8b03958 | 1450 | sizeof(struct il_rxon_cmd), &il->staging); |
4bc85c13 | 1451 | if (ret) { |
9406f797 | 1452 | IL_ERR("Error setting new RXON (%d)\n", ret); |
4bc85c13 WYG |
1453 | return ret; |
1454 | } | |
c8b03958 | 1455 | memcpy(active_rxon, &il->staging, sizeof(*active_rxon)); |
4bc85c13 | 1456 | } |
83007196 | 1457 | il_print_rx_config_cmd(il); |
4bc85c13 | 1458 | |
46bc8d4b | 1459 | il4965_init_sensitivity(il); |
4bc85c13 WYG |
1460 | |
1461 | /* If we issue a new RXON command which required a tune then we must | |
1462 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
46bc8d4b | 1463 | ret = il_set_tx_power(il, il->tx_power_next, true); |
4bc85c13 | 1464 | if (ret) { |
9406f797 | 1465 | IL_ERR("Error sending TX power (%d)\n", ret); |
4bc85c13 WYG |
1466 | return ret; |
1467 | } | |
1468 | ||
1469 | return 0; | |
1470 | } | |
1471 | ||
e7392364 SG |
1472 | static int |
1473 | il4965_hw_channel_switch(struct il_priv *il, | |
1474 | struct ieee80211_channel_switch *ch_switch) | |
4bc85c13 | 1475 | { |
4bc85c13 WYG |
1476 | int rc; |
1477 | u8 band = 0; | |
1478 | bool is_ht40 = false; | |
1479 | u8 ctrl_chan_high = 0; | |
e2ebc833 SG |
1480 | struct il4965_channel_switch_cmd cmd; |
1481 | const struct il_channel_info *ch_info; | |
4bc85c13 WYG |
1482 | u32 switch_time_in_usec, ucode_switch_time; |
1483 | u16 ch; | |
1484 | u32 tsf_low; | |
1485 | u8 switch_count; | |
c8b03958 | 1486 | u16 beacon_interval = le16_to_cpu(il->timing.beacon_interval); |
83007196 SG |
1487 | struct ieee80211_vif *vif = il->vif; |
1488 | band = (il->band == IEEE80211_BAND_2GHZ); | |
1489 | ||
1490 | if (WARN_ON_ONCE(vif == NULL)) | |
1491 | return -EIO; | |
4bc85c13 | 1492 | |
c8b03958 | 1493 | is_ht40 = iw4965_is_ht40_channel(il->staging.flags); |
4bc85c13 | 1494 | |
c8b03958 | 1495 | if (is_ht40 && (il->staging.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) |
4bc85c13 WYG |
1496 | ctrl_chan_high = 1; |
1497 | ||
1498 | cmd.band = band; | |
1499 | cmd.expect_beacon = 0; | |
1500 | ch = ch_switch->channel->hw_value; | |
1501 | cmd.channel = cpu_to_le16(ch); | |
c8b03958 SG |
1502 | cmd.rxon_flags = il->staging.flags; |
1503 | cmd.rxon_filter_flags = il->staging.filter_flags; | |
4bc85c13 WYG |
1504 | switch_count = ch_switch->count; |
1505 | tsf_low = ch_switch->timestamp & 0x0ffffffff; | |
1506 | /* | |
1507 | * calculate the ucode channel switch time | |
1508 | * adding TSF as one of the factor for when to switch | |
1509 | */ | |
232913b5 | 1510 | if (il->ucode_beacon_time > tsf_low && beacon_interval) { |
e7392364 SG |
1511 | if (switch_count > |
1512 | ((il->ucode_beacon_time - tsf_low) / beacon_interval)) { | |
1513 | switch_count -= | |
1514 | (il->ucode_beacon_time - tsf_low) / beacon_interval; | |
4bc85c13 WYG |
1515 | } else |
1516 | switch_count = 0; | |
1517 | } | |
1518 | if (switch_count <= 1) | |
46bc8d4b | 1519 | cmd.switch_time = cpu_to_le32(il->ucode_beacon_time); |
4bc85c13 WYG |
1520 | else { |
1521 | switch_time_in_usec = | |
e7392364 SG |
1522 | vif->bss_conf.beacon_int * switch_count * TIME_UNIT; |
1523 | ucode_switch_time = | |
1524 | il_usecs_to_beacons(il, switch_time_in_usec, | |
1525 | beacon_interval); | |
1526 | cmd.switch_time = | |
1527 | il_add_beacon_time(il, il->ucode_beacon_time, | |
1528 | ucode_switch_time, beacon_interval); | |
4bc85c13 | 1529 | } |
e7392364 | 1530 | D_11H("uCode time for the switch is 0x%x\n", cmd.switch_time); |
46bc8d4b | 1531 | ch_info = il_get_channel_info(il, il->band, ch); |
4bc85c13 | 1532 | if (ch_info) |
e2ebc833 | 1533 | cmd.expect_beacon = il_is_channel_radar(ch_info); |
4bc85c13 | 1534 | else { |
9406f797 | 1535 | IL_ERR("invalid channel switch from %u to %u\n", |
c8b03958 | 1536 | il->active.channel, ch); |
4bc85c13 WYG |
1537 | return -EFAULT; |
1538 | } | |
1539 | ||
e7392364 SG |
1540 | rc = il4965_fill_txpower_tbl(il, band, ch, is_ht40, ctrl_chan_high, |
1541 | &cmd.tx_power); | |
4bc85c13 | 1542 | if (rc) { |
58de00a4 | 1543 | D_11H("error:%d fill txpower_tbl\n", rc); |
4bc85c13 WYG |
1544 | return rc; |
1545 | } | |
1546 | ||
e7392364 | 1547 | return il_send_cmd_pdu(il, C_CHANNEL_SWITCH, sizeof(cmd), &cmd); |
4bc85c13 WYG |
1548 | } |
1549 | ||
1550 | /** | |
e2ebc833 | 1551 | * il4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array |
4bc85c13 | 1552 | */ |
e7392364 SG |
1553 | static void |
1554 | il4965_txq_update_byte_cnt_tbl(struct il_priv *il, struct il_tx_queue *txq, | |
1555 | u16 byte_cnt) | |
4bc85c13 | 1556 | { |
46bc8d4b | 1557 | struct il4965_scd_bc_tbl *scd_bc_tbl = il->scd_bc_tbls.addr; |
4bc85c13 WYG |
1558 | int txq_id = txq->q.id; |
1559 | int write_ptr = txq->q.write_ptr; | |
e2ebc833 | 1560 | int len = byte_cnt + IL_TX_CRC_SIZE + IL_TX_DELIMITER_SIZE; |
4bc85c13 WYG |
1561 | __le16 bc_ent; |
1562 | ||
1563 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); | |
1564 | ||
1565 | bc_ent = cpu_to_le16(len & 0xFFF); | |
1566 | /* Set up byte count within first 256 entries */ | |
1567 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
1568 | ||
1569 | /* If within first 64 entries, duplicate at end */ | |
1570 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
e7392364 SG |
1571 | scd_bc_tbl[txq_id].tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = |
1572 | bc_ent; | |
4bc85c13 WYG |
1573 | } |
1574 | ||
1575 | /** | |
e2ebc833 | 1576 | * il4965_hw_get_temperature - return the calibrated temperature (in Kelvin) |
ebf0d90d | 1577 | * @stats: Provides the temperature reading from the uCode |
4bc85c13 | 1578 | * |
ebf0d90d | 1579 | * A return of <0 indicates bogus data in the stats |
4bc85c13 | 1580 | */ |
e7392364 SG |
1581 | static int |
1582 | il4965_hw_get_temperature(struct il_priv *il) | |
4bc85c13 WYG |
1583 | { |
1584 | s32 temperature; | |
1585 | s32 vt; | |
1586 | s32 R1, R2, R3; | |
1587 | u32 R4; | |
1588 | ||
a6766ccd | 1589 | if (test_bit(S_TEMPERATURE, &il->status) && |
e7392364 | 1590 | (il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)) { |
58de00a4 | 1591 | D_TEMP("Running HT40 temperature calibration\n"); |
e7392364 SG |
1592 | R1 = (s32) le32_to_cpu(il->card_alive_init.therm_r1[1]); |
1593 | R2 = (s32) le32_to_cpu(il->card_alive_init.therm_r2[1]); | |
1594 | R3 = (s32) le32_to_cpu(il->card_alive_init.therm_r3[1]); | |
46bc8d4b | 1595 | R4 = le32_to_cpu(il->card_alive_init.therm_r4[1]); |
4bc85c13 | 1596 | } else { |
58de00a4 | 1597 | D_TEMP("Running temperature calibration\n"); |
e7392364 SG |
1598 | R1 = (s32) le32_to_cpu(il->card_alive_init.therm_r1[0]); |
1599 | R2 = (s32) le32_to_cpu(il->card_alive_init.therm_r2[0]); | |
1600 | R3 = (s32) le32_to_cpu(il->card_alive_init.therm_r3[0]); | |
46bc8d4b | 1601 | R4 = le32_to_cpu(il->card_alive_init.therm_r4[0]); |
4bc85c13 WYG |
1602 | } |
1603 | ||
1604 | /* | |
1605 | * Temperature is only 23 bits, so sign extend out to 32. | |
1606 | * | |
ebf0d90d | 1607 | * NOTE If we haven't received a stats notification yet |
4bc85c13 WYG |
1608 | * with an updated temperature, use R4 provided to us in the |
1609 | * "initialize" ALIVE response. | |
1610 | */ | |
a6766ccd | 1611 | if (!test_bit(S_TEMPERATURE, &il->status)) |
4bc85c13 WYG |
1612 | vt = sign_extend32(R4, 23); |
1613 | else | |
e7392364 SG |
1614 | vt = sign_extend32(le32_to_cpu |
1615 | (il->_4965.stats.general.common.temperature), | |
1616 | 23); | |
4bc85c13 | 1617 | |
58de00a4 | 1618 | D_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt); |
4bc85c13 WYG |
1619 | |
1620 | if (R3 == R1) { | |
9406f797 | 1621 | IL_ERR("Calibration conflict R1 == R3\n"); |
4bc85c13 WYG |
1622 | return -1; |
1623 | } | |
1624 | ||
1625 | /* Calculate temperature in degrees Kelvin, adjust by 97%. | |
1626 | * Add offset to center the adjustment around 0 degrees Centigrade. */ | |
1627 | temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2); | |
1628 | temperature /= (R3 - R1); | |
e7392364 SG |
1629 | temperature = |
1630 | (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET; | |
4bc85c13 | 1631 | |
e7392364 SG |
1632 | D_TEMP("Calibrated temperature: %dK, %dC\n", temperature, |
1633 | KELVIN_TO_CELSIUS(temperature)); | |
4bc85c13 WYG |
1634 | |
1635 | return temperature; | |
1636 | } | |
1637 | ||
1638 | /* Adjust Txpower only if temperature variance is greater than threshold. */ | |
e2ebc833 | 1639 | #define IL_TEMPERATURE_THRESHOLD 3 |
4bc85c13 WYG |
1640 | |
1641 | /** | |
e2ebc833 | 1642 | * il4965_is_temp_calib_needed - determines if new calibration is needed |
4bc85c13 WYG |
1643 | * |
1644 | * If the temperature changed has changed sufficiently, then a recalibration | |
1645 | * is needed. | |
1646 | * | |
46bc8d4b | 1647 | * Assumes caller will replace il->last_temperature once calibration |
4bc85c13 WYG |
1648 | * executed. |
1649 | */ | |
e7392364 SG |
1650 | static int |
1651 | il4965_is_temp_calib_needed(struct il_priv *il) | |
4bc85c13 WYG |
1652 | { |
1653 | int temp_diff; | |
1654 | ||
db7746f7 | 1655 | if (!test_bit(S_STATS, &il->status)) { |
ebf0d90d | 1656 | D_TEMP("Temperature not updated -- no stats.\n"); |
4bc85c13 WYG |
1657 | return 0; |
1658 | } | |
1659 | ||
46bc8d4b | 1660 | temp_diff = il->temperature - il->last_temperature; |
4bc85c13 WYG |
1661 | |
1662 | /* get absolute value */ | |
1663 | if (temp_diff < 0) { | |
58de00a4 | 1664 | D_POWER("Getting cooler, delta %d\n", temp_diff); |
4bc85c13 WYG |
1665 | temp_diff = -temp_diff; |
1666 | } else if (temp_diff == 0) | |
58de00a4 | 1667 | D_POWER("Temperature unchanged\n"); |
4bc85c13 | 1668 | else |
58de00a4 | 1669 | D_POWER("Getting warmer, delta %d\n", temp_diff); |
4bc85c13 | 1670 | |
e2ebc833 | 1671 | if (temp_diff < IL_TEMPERATURE_THRESHOLD) { |
58de00a4 | 1672 | D_POWER(" => thermal txpower calib not needed\n"); |
4bc85c13 WYG |
1673 | return 0; |
1674 | } | |
1675 | ||
58de00a4 | 1676 | D_POWER(" => thermal txpower calib needed\n"); |
4bc85c13 WYG |
1677 | |
1678 | return 1; | |
1679 | } | |
1680 | ||
527901d0 | 1681 | void |
e7392364 | 1682 | il4965_temperature_calib(struct il_priv *il) |
4bc85c13 WYG |
1683 | { |
1684 | s32 temp; | |
1685 | ||
46bc8d4b | 1686 | temp = il4965_hw_get_temperature(il); |
e2ebc833 | 1687 | if (IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(temp)) |
4bc85c13 WYG |
1688 | return; |
1689 | ||
46bc8d4b SG |
1690 | if (il->temperature != temp) { |
1691 | if (il->temperature) | |
e7392364 SG |
1692 | D_TEMP("Temperature changed " "from %dC to %dC\n", |
1693 | KELVIN_TO_CELSIUS(il->temperature), | |
1694 | KELVIN_TO_CELSIUS(temp)); | |
4bc85c13 | 1695 | else |
e7392364 SG |
1696 | D_TEMP("Temperature " "initialized to %dC\n", |
1697 | KELVIN_TO_CELSIUS(temp)); | |
4bc85c13 WYG |
1698 | } |
1699 | ||
46bc8d4b | 1700 | il->temperature = temp; |
a6766ccd | 1701 | set_bit(S_TEMPERATURE, &il->status); |
4bc85c13 | 1702 | |
46bc8d4b | 1703 | if (!il->disable_tx_power_cal && |
e7392364 SG |
1704 | unlikely(!test_bit(S_SCANNING, &il->status)) && |
1705 | il4965_is_temp_calib_needed(il)) | |
46bc8d4b | 1706 | queue_work(il->workqueue, &il->txpower_work); |
4bc85c13 WYG |
1707 | } |
1708 | ||
e7392364 SG |
1709 | static u16 |
1710 | il4965_get_hcmd_size(u8 cmd_id, u16 len) | |
4bc85c13 WYG |
1711 | { |
1712 | switch (cmd_id) { | |
4d69c752 | 1713 | case C_RXON: |
e2ebc833 | 1714 | return (u16) sizeof(struct il4965_rxon_cmd); |
4bc85c13 WYG |
1715 | default: |
1716 | return len; | |
1717 | } | |
1718 | } | |
1719 | ||
e7392364 SG |
1720 | static u16 |
1721 | il4965_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data) | |
4bc85c13 | 1722 | { |
e2ebc833 | 1723 | struct il4965_addsta_cmd *addsta = (struct il4965_addsta_cmd *)data; |
4bc85c13 WYG |
1724 | addsta->mode = cmd->mode; |
1725 | memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify)); | |
e2ebc833 | 1726 | memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo)); |
4bc85c13 WYG |
1727 | addsta->station_flags = cmd->station_flags; |
1728 | addsta->station_flags_msk = cmd->station_flags_msk; | |
1729 | addsta->tid_disable_tx = cmd->tid_disable_tx; | |
1730 | addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid; | |
1731 | addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid; | |
1732 | addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn; | |
1733 | addsta->sleep_tx_count = cmd->sleep_tx_count; | |
1734 | addsta->reserved1 = cpu_to_le16(0); | |
1735 | addsta->reserved2 = cpu_to_le16(0); | |
1736 | ||
e7392364 | 1737 | return (u16) sizeof(struct il4965_addsta_cmd); |
4bc85c13 WYG |
1738 | } |
1739 | ||
e2ebc833 SG |
1740 | static struct il_hcmd_ops il4965_hcmd = { |
1741 | .rxon_assoc = il4965_send_rxon_assoc, | |
1742 | .commit_rxon = il4965_commit_rxon, | |
1743 | .set_rxon_chain = il4965_set_rxon_chain, | |
4bc85c13 WYG |
1744 | }; |
1745 | ||
e7392364 SG |
1746 | static void |
1747 | il4965_post_scan(struct il_priv *il) | |
4bc85c13 | 1748 | { |
4bc85c13 WYG |
1749 | /* |
1750 | * Since setting the RXON may have been deferred while | |
1751 | * performing the scan, fire one off if needed | |
1752 | */ | |
c8b03958 | 1753 | if (memcmp(&il->staging, &il->active, sizeof(il->staging))) |
83007196 | 1754 | il_commit_rxon(il); |
4bc85c13 WYG |
1755 | } |
1756 | ||
e7392364 SG |
1757 | static void |
1758 | il4965_post_associate(struct il_priv *il) | |
4bc85c13 | 1759 | { |
83007196 | 1760 | struct ieee80211_vif *vif = il->vif; |
4bc85c13 WYG |
1761 | struct ieee80211_conf *conf = NULL; |
1762 | int ret = 0; | |
1763 | ||
46bc8d4b | 1764 | if (!vif || !il->is_open) |
4bc85c13 WYG |
1765 | return; |
1766 | ||
a6766ccd | 1767 | if (test_bit(S_EXIT_PENDING, &il->status)) |
4bc85c13 WYG |
1768 | return; |
1769 | ||
46bc8d4b | 1770 | il_scan_cancel_timeout(il, 200); |
4bc85c13 | 1771 | |
6278ddab | 1772 | conf = &il->hw->conf; |
4bc85c13 | 1773 | |
c8b03958 | 1774 | il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
83007196 | 1775 | il_commit_rxon(il); |
4bc85c13 | 1776 | |
83007196 | 1777 | ret = il_send_rxon_timing(il); |
4bc85c13 | 1778 | if (ret) |
e7392364 | 1779 | IL_WARN("RXON timing - " "Attempting to continue.\n"); |
4bc85c13 | 1780 | |
c8b03958 | 1781 | il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
4bc85c13 | 1782 | |
46bc8d4b | 1783 | il_set_rxon_ht(il, &il->current_ht_config); |
4bc85c13 | 1784 | |
c39ae9fd SG |
1785 | if (il->ops->hcmd->set_rxon_chain) |
1786 | il->ops->hcmd->set_rxon_chain(il); | |
4bc85c13 | 1787 | |
c8b03958 | 1788 | il->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid); |
4bc85c13 | 1789 | |
e7392364 SG |
1790 | D_ASSOC("assoc id %d beacon interval %d\n", vif->bss_conf.aid, |
1791 | vif->bss_conf.beacon_int); | |
4bc85c13 WYG |
1792 | |
1793 | if (vif->bss_conf.use_short_preamble) | |
c8b03958 | 1794 | il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
4bc85c13 | 1795 | else |
c8b03958 | 1796 | il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
4bc85c13 | 1797 | |
c8b03958 | 1798 | if (il->staging.flags & RXON_FLG_BAND_24G_MSK) { |
4bc85c13 | 1799 | if (vif->bss_conf.use_short_slot) |
c8b03958 | 1800 | il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
4bc85c13 | 1801 | else |
c8b03958 | 1802 | il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
4bc85c13 WYG |
1803 | } |
1804 | ||
83007196 | 1805 | il_commit_rxon(il); |
4bc85c13 | 1806 | |
e7392364 | 1807 | D_ASSOC("Associated as %d to: %pM\n", vif->bss_conf.aid, |
c8b03958 | 1808 | il->active.bssid_addr); |
4bc85c13 WYG |
1809 | |
1810 | switch (vif->type) { | |
1811 | case NL80211_IFTYPE_STATION: | |
1812 | break; | |
1813 | case NL80211_IFTYPE_ADHOC: | |
46bc8d4b | 1814 | il4965_send_beacon_cmd(il); |
4bc85c13 WYG |
1815 | break; |
1816 | default: | |
e7392364 SG |
1817 | IL_ERR("%s Should not be called in %d mode\n", __func__, |
1818 | vif->type); | |
4bc85c13 WYG |
1819 | break; |
1820 | } | |
1821 | ||
1822 | /* the chain noise calibration will enabled PM upon completion | |
1823 | * If chain noise has already been run, then we need to enable | |
1824 | * power management here */ | |
46bc8d4b SG |
1825 | if (il->chain_noise_data.state == IL_CHAIN_NOISE_DONE) |
1826 | il_power_update_mode(il, false); | |
4bc85c13 WYG |
1827 | |
1828 | /* Enable Rx differential gain and sensitivity calibrations */ | |
46bc8d4b SG |
1829 | il4965_chain_noise_reset(il); |
1830 | il->start_calib = 1; | |
4bc85c13 WYG |
1831 | } |
1832 | ||
e7392364 SG |
1833 | static void |
1834 | il4965_config_ap(struct il_priv *il) | |
4bc85c13 | 1835 | { |
83007196 | 1836 | struct ieee80211_vif *vif = il->vif; |
4bc85c13 WYG |
1837 | int ret = 0; |
1838 | ||
46bc8d4b | 1839 | lockdep_assert_held(&il->mutex); |
4bc85c13 | 1840 | |
a6766ccd | 1841 | if (test_bit(S_EXIT_PENDING, &il->status)) |
4bc85c13 WYG |
1842 | return; |
1843 | ||
1844 | /* The following should be done only at AP bring up */ | |
c8b03958 | 1845 | if (!il_is_associated(il)) { |
4bc85c13 WYG |
1846 | |
1847 | /* RXON - unassoc (to set timing command) */ | |
c8b03958 | 1848 | il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
83007196 | 1849 | il_commit_rxon(il); |
4bc85c13 WYG |
1850 | |
1851 | /* RXON Timing */ | |
83007196 | 1852 | ret = il_send_rxon_timing(il); |
4bc85c13 | 1853 | if (ret) |
9406f797 | 1854 | IL_WARN("RXON timing failed - " |
e7392364 | 1855 | "Attempting to continue.\n"); |
4bc85c13 WYG |
1856 | |
1857 | /* AP has all antennas */ | |
e7392364 | 1858 | il->chain_noise_data.active_chains = il->hw_params.valid_rx_ant; |
46bc8d4b | 1859 | il_set_rxon_ht(il, &il->current_ht_config); |
c39ae9fd SG |
1860 | if (il->ops->hcmd->set_rxon_chain) |
1861 | il->ops->hcmd->set_rxon_chain(il); | |
4bc85c13 | 1862 | |
c8b03958 | 1863 | il->staging.assoc_id = 0; |
4bc85c13 WYG |
1864 | |
1865 | if (vif->bss_conf.use_short_preamble) | |
c8b03958 | 1866 | il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
4bc85c13 | 1867 | else |
c8b03958 | 1868 | il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
4bc85c13 | 1869 | |
c8b03958 | 1870 | if (il->staging.flags & RXON_FLG_BAND_24G_MSK) { |
4bc85c13 | 1871 | if (vif->bss_conf.use_short_slot) |
c8b03958 | 1872 | il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
4bc85c13 | 1873 | else |
c8b03958 | 1874 | il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
4bc85c13 WYG |
1875 | } |
1876 | /* need to send beacon cmd before committing assoc RXON! */ | |
46bc8d4b | 1877 | il4965_send_beacon_cmd(il); |
4bc85c13 | 1878 | /* restore RXON assoc */ |
c8b03958 | 1879 | il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
83007196 | 1880 | il_commit_rxon(il); |
4bc85c13 | 1881 | } |
46bc8d4b | 1882 | il4965_send_beacon_cmd(il); |
4bc85c13 WYG |
1883 | } |
1884 | ||
e2ebc833 SG |
1885 | static struct il_hcmd_utils_ops il4965_hcmd_utils = { |
1886 | .get_hcmd_size = il4965_get_hcmd_size, | |
1887 | .build_addsta_hcmd = il4965_build_addsta_hcmd, | |
1888 | .request_scan = il4965_request_scan, | |
1889 | .post_scan = il4965_post_scan, | |
4bc85c13 WYG |
1890 | }; |
1891 | ||
e2ebc833 | 1892 | static struct il_lib_ops il4965_lib = { |
e2ebc833 SG |
1893 | .txq_update_byte_cnt_tbl = il4965_txq_update_byte_cnt_tbl, |
1894 | .txq_attach_buf_to_tfd = il4965_hw_txq_attach_buf_to_tfd, | |
1895 | .txq_free_tfd = il4965_hw_txq_free_tfd, | |
1896 | .txq_init = il4965_hw_tx_queue_init, | |
e2ebc833 SG |
1897 | .is_valid_rtc_data_addr = il4965_hw_valid_rtc_data_addr, |
1898 | .init_alive_start = il4965_init_alive_start, | |
1899 | .load_ucode = il4965_load_bsm, | |
1900 | .dump_nic_error_log = il4965_dump_nic_error_log, | |
1901 | .dump_fh = il4965_dump_fh, | |
1902 | .set_channel_switch = il4965_hw_channel_switch, | |
f03ee2a8 | 1903 | .apm_init = il_apm_init, |
e7392364 | 1904 | .send_tx_power = il4965_send_tx_power, |
e2ebc833 | 1905 | .update_chain_flags = il4965_update_chain_flags, |
a89268e8 SG |
1906 | .eeprom_acquire_semaphore = il4965_eeprom_acquire_semaphore, |
1907 | .eeprom_release_semaphore = il4965_eeprom_release_semaphore, | |
4bc85c13 WYG |
1908 | }; |
1909 | ||
e2ebc833 SG |
1910 | static const struct il_legacy_ops il4965_legacy_ops = { |
1911 | .post_associate = il4965_post_associate, | |
1912 | .config_ap = il4965_config_ap, | |
1913 | .manage_ibss_station = il4965_manage_ibss_station, | |
1914 | .update_bcast_stations = il4965_update_bcast_stations, | |
4bc85c13 WYG |
1915 | }; |
1916 | ||
c39ae9fd | 1917 | const struct il_ops il4965_ops = { |
e2ebc833 SG |
1918 | .lib = &il4965_lib, |
1919 | .hcmd = &il4965_hcmd, | |
1920 | .utils = &il4965_hcmd_utils, | |
1921 | .led = &il4965_led_ops, | |
1922 | .legacy = &il4965_legacy_ops, | |
4bc85c13 WYG |
1923 | }; |
1924 | ||
e2ebc833 | 1925 | struct il_cfg il4965_cfg = { |
4bc85c13 | 1926 | .name = "Intel(R) Wireless WiFi Link 4965AGN", |
d3175167 SG |
1927 | .fw_name_pre = IL4965_FW_PRE, |
1928 | .ucode_api_max = IL4965_UCODE_API_MAX, | |
1929 | .ucode_api_min = IL4965_UCODE_API_MIN, | |
e7392364 | 1930 | .sku = IL_SKU_A | IL_SKU_G | IL_SKU_N, |
4bc85c13 WYG |
1931 | .valid_tx_ant = ANT_AB, |
1932 | .valid_rx_ant = ANT_ABC, | |
1933 | .eeprom_ver = EEPROM_4965_EEPROM_VERSION, | |
1934 | .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION, | |
e2ebc833 | 1935 | .mod_params = &il4965_mod_params, |
e2ebc833 | 1936 | .led_mode = IL_LED_BLINK, |
4bc85c13 WYG |
1937 | /* |
1938 | * Force use of chains B and C for scan RX on 5 GHz band | |
1939 | * because the device has off-channel reception on chain A. | |
1940 | */ | |
1941 | .scan_rx_antennas[IEEE80211_BAND_5GHZ] = ANT_BC, | |
89ef1ed2 SG |
1942 | |
1943 | .eeprom_size = IL4965_EEPROM_IMG_SIZE, | |
1944 | .num_of_queues = IL49_NUM_QUEUES, | |
1945 | .num_of_ampdu_queues = IL49_NUM_AMPDU_QUEUES, | |
1946 | .pll_cfg_val = 0, | |
1947 | .set_l0s = true, | |
1948 | .use_bsm = true, | |
1949 | .led_compensation = 61, | |
1950 | .chain_noise_num_beacons = IL4965_CAL_NUM_BEACONS, | |
1951 | .wd_timeout = IL_DEF_WD_TIMEOUT, | |
1952 | .temperature_kelvin = true, | |
1953 | .ucode_tracing = true, | |
1954 | .sensitivity_calib_by_driver = true, | |
1955 | .chain_noise_calib_by_driver = true, | |
93a984a4 SG |
1956 | |
1957 | .regulatory_bands = { | |
1958 | EEPROM_REGULATORY_BAND_1_CHANNELS, | |
1959 | EEPROM_REGULATORY_BAND_2_CHANNELS, | |
1960 | EEPROM_REGULATORY_BAND_3_CHANNELS, | |
1961 | EEPROM_REGULATORY_BAND_4_CHANNELS, | |
1962 | EEPROM_REGULATORY_BAND_5_CHANNELS, | |
1963 | EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS, | |
1964 | EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS | |
1965 | }, | |
1966 | ||
4bc85c13 WYG |
1967 | }; |
1968 | ||
1969 | /* Module firmware */ | |
d3175167 | 1970 | MODULE_FIRMWARE(IL4965_MODULE_FIRMWARE(IL4965_UCODE_API_MAX)); |