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iwlegacy: move qos_data out of ctx structure
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
0cdc2136
SG		 34#include <linux/types.h>
35#include <linux/lockdep.h>
36#include <linux/init.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/skbuff.h>
be663ab6
WYG		 41#include <net/mac80211.h>
42
98613be0 43#include "common.h"
be663ab6 44
17d4eca6
SG		 45int
46_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
47{
48 const int interval = 10; /* microseconds */
49 int t = 0;
50
51 do {
52 if ((_il_rd(il, addr) & mask) == (bits & mask))
53 return t;
54 udelay(interval);
55 t += interval;
56 } while (t < timeout);
57
58 return -ETIMEDOUT;
59}
60EXPORT_SYMBOL(_il_poll_bit);
61
62void
63il_set_bit(struct il_priv *p, u32 r, u32 m)
64{
65 unsigned long reg_flags;
66
67 spin_lock_irqsave(&p->reg_lock, reg_flags);
68 _il_set_bit(p, r, m);
69 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
70}
71EXPORT_SYMBOL(il_set_bit);
72
73void
74il_clear_bit(struct il_priv *p, u32 r, u32 m)
75{
76 unsigned long reg_flags;
77
78 spin_lock_irqsave(&p->reg_lock, reg_flags);
79 _il_clear_bit(p, r, m);
80 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
81}
82EXPORT_SYMBOL(il_clear_bit);
83
84int
85_il_grab_nic_access(struct il_priv *il)
86{
87 int ret;
88 u32 val;
89
90 /* this bit wakes up the NIC */
91 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
92
93 /*
94 * These bits say the device is running, and should keep running for
95 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
96 * but they do not indicate that embedded SRAM is restored yet;
97 * 3945 and 4965 have volatile SRAM, and must save/restore contents
98 * to/from host DRAM when sleeping/waking for power-saving.
99 * Each direction takes approximately 1/4 millisecond; with this
100 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
101 * series of register accesses are expected (e.g. reading Event Log),
102 * to keep device from sleeping.
103 *
104 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
105 * SRAM is okay/restored. We don't check that here because this call
106 * is just for hardware register access; but GP1 MAC_SLEEP check is a
107 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
108 *
109 */
110 ret =
111 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
112 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
113 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
114 if (ret < 0) {
115 val = _il_rd(il, CSR_GP_CNTRL);
116 IL_ERR("MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
117 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
118 return -EIO;
119 }
120
121 return 0;
122}
123EXPORT_SYMBOL_GPL(_il_grab_nic_access);
124
125int
126il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
127{
128 const int interval = 10; /* microseconds */
129 int t = 0;
130
131 do {
132 if ((il_rd(il, addr) & mask) == mask)
133 return t;
134 udelay(interval);
135 t += interval;
136 } while (t < timeout);
137
138 return -ETIMEDOUT;
139}
140EXPORT_SYMBOL(il_poll_bit);
141
142u32
143il_rd_prph(struct il_priv *il, u32 reg)
144{
145 unsigned long reg_flags;
146 u32 val;
147
148 spin_lock_irqsave(&il->reg_lock, reg_flags);
149 _il_grab_nic_access(il);
150 val = _il_rd_prph(il, reg);
151 _il_release_nic_access(il);
152 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
153 return val;
154}
155EXPORT_SYMBOL(il_rd_prph);
156
157void
158il_wr_prph(struct il_priv *il, u32 addr, u32 val)
159{
160 unsigned long reg_flags;
161
162 spin_lock_irqsave(&il->reg_lock, reg_flags);
163 if (!_il_grab_nic_access(il)) {
164 _il_wr_prph(il, addr, val);
165 _il_release_nic_access(il);
166 }
167 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
168}
169EXPORT_SYMBOL(il_wr_prph);
170
171u32
172il_read_targ_mem(struct il_priv *il, u32 addr)
173{
174 unsigned long reg_flags;
175 u32 value;
176
177 spin_lock_irqsave(&il->reg_lock, reg_flags);
178 _il_grab_nic_access(il);
179
180 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
181 rmb();
182 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
183
184 _il_release_nic_access(il);
185 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
186 return value;
187}
188EXPORT_SYMBOL(il_read_targ_mem);
189
190void
191il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
192{
193 unsigned long reg_flags;
194
195 spin_lock_irqsave(&il->reg_lock, reg_flags);
196 if (!_il_grab_nic_access(il)) {
197 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
198 wmb();
199 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
200 _il_release_nic_access(il);
201 }
202 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
203}
204EXPORT_SYMBOL(il_write_targ_mem);
205
e7392364
SG		 206const char *
207il_get_cmd_string(u8 cmd)
0cdc2136
SG		 208{
209 switch (cmd) {
210 IL_CMD(N_ALIVE);
211 IL_CMD(N_ERROR);
212 IL_CMD(C_RXON);
213 IL_CMD(C_RXON_ASSOC);
214 IL_CMD(C_QOS_PARAM);
215 IL_CMD(C_RXON_TIMING);
216 IL_CMD(C_ADD_STA);
217 IL_CMD(C_REM_STA);
218 IL_CMD(C_WEPKEY);
219 IL_CMD(N_3945_RX);
220 IL_CMD(C_TX);
221 IL_CMD(C_RATE_SCALE);
222 IL_CMD(C_LEDS);
223 IL_CMD(C_TX_LINK_QUALITY_CMD);
224 IL_CMD(C_CHANNEL_SWITCH);
225 IL_CMD(N_CHANNEL_SWITCH);
226 IL_CMD(C_SPECTRUM_MEASUREMENT);
227 IL_CMD(N_SPECTRUM_MEASUREMENT);
228 IL_CMD(C_POWER_TBL);
229 IL_CMD(N_PM_SLEEP);
230 IL_CMD(N_PM_DEBUG_STATS);
231 IL_CMD(C_SCAN);
232 IL_CMD(C_SCAN_ABORT);
233 IL_CMD(N_SCAN_START);
234 IL_CMD(N_SCAN_RESULTS);
235 IL_CMD(N_SCAN_COMPLETE);
236 IL_CMD(N_BEACON);
237 IL_CMD(C_TX_BEACON);
238 IL_CMD(C_TX_PWR_TBL);
239 IL_CMD(C_BT_CONFIG);
240 IL_CMD(C_STATS);
241 IL_CMD(N_STATS);
242 IL_CMD(N_CARD_STATE);
243 IL_CMD(N_MISSED_BEACONS);
244 IL_CMD(C_CT_KILL_CONFIG);
245 IL_CMD(C_SENSITIVITY);
246 IL_CMD(C_PHY_CALIBRATION);
247 IL_CMD(N_RX_PHY);
248 IL_CMD(N_RX_MPDU);
249 IL_CMD(N_RX);
250 IL_CMD(N_COMPRESSED_BA);
251 default:
252 return "UNKNOWN";
253
254 }
255}
256EXPORT_SYMBOL(il_get_cmd_string);
257
258#define HOST_COMPLETE_TIMEOUT (HZ / 2)
259
e7392364
SG		 260static void
261il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
262 struct il_rx_pkt *pkt)
0cdc2136
SG		 263{
264 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
265 IL_ERR("Bad return from %s (0x%08X)\n",
e7392364 266 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 267 return;
268 }
0cdc2136
SG		 269#ifdef CONFIG_IWLEGACY_DEBUG
270 switch (cmd->hdr.cmd) {
271 case C_TX_LINK_QUALITY_CMD:
272 case C_SENSITIVITY:
273 D_HC_DUMP("back from %s (0x%08X)\n",
e7392364 274 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 275 break;
276 default:
e7392364
SG		 277 D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
278 pkt->hdr.flags);
0cdc2136
SG		 279 }
280#endif
281}
282
283static int
284il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
285{
286 int ret;
287
288 BUG_ON(!(cmd->flags & CMD_ASYNC));
289
290 /* An asynchronous command can not expect an SKB to be set. */
291 BUG_ON(cmd->flags & CMD_WANT_SKB);
292
293 /* Assign a generic callback if one is not provided */
294 if (!cmd->callback)
295 cmd->callback = il_generic_cmd_callback;
296
297 if (test_bit(S_EXIT_PENDING, &il->status))
298 return -EBUSY;
299
300 ret = il_enqueue_hcmd(il, cmd);
301 if (ret < 0) {
302 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 303 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 304 return ret;
305 }
306 return 0;
307}
308
e7392364
SG		 309int
310il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 311{
312 int cmd_idx;
313 int ret;
314
315 lockdep_assert_held(&il->mutex);
316
317 BUG_ON(cmd->flags & CMD_ASYNC);
318
e7392364 319 /* A synchronous command can not have a callback set. */
0cdc2136
SG		 320 BUG_ON(cmd->callback);
321
322 D_INFO("Attempting to send sync command %s\n",
e7392364 323 il_get_cmd_string(cmd->id));
0cdc2136
SG		 324
325 set_bit(S_HCMD_ACTIVE, &il->status);
326 D_INFO("Setting HCMD_ACTIVE for command %s\n",
e7392364 327 il_get_cmd_string(cmd->id));
0cdc2136
SG		 328
329 cmd_idx = il_enqueue_hcmd(il, cmd);
330 if (cmd_idx < 0) {
331 ret = cmd_idx;
332 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 333 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 334 goto out;
335 }
336
337 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 338 !test_bit(S_HCMD_ACTIVE, &il->status),
339 HOST_COMPLETE_TIMEOUT);
0cdc2136
SG		 340 if (!ret) {
341 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
e7392364
SG		 342 IL_ERR("Error sending %s: time out after %dms.\n",
343 il_get_cmd_string(cmd->id),
344 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
0cdc2136
SG		 345
346 clear_bit(S_HCMD_ACTIVE, &il->status);
e7392364
SG		 347 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
348 il_get_cmd_string(cmd->id));
0cdc2136
SG		 349 ret = -ETIMEDOUT;
350 goto cancel;
351 }
352 }
353
354 if (test_bit(S_RF_KILL_HW, &il->status)) {
355 IL_ERR("Command %s aborted: RF KILL Switch\n",
e7392364 356 il_get_cmd_string(cmd->id));
0cdc2136
SG		 357 ret = -ECANCELED;
358 goto fail;
359 }
360 if (test_bit(S_FW_ERROR, &il->status)) {
361 IL_ERR("Command %s failed: FW Error\n",
e7392364 362 il_get_cmd_string(cmd->id));
0cdc2136
SG		 363 ret = -EIO;
364 goto fail;
365 }
366 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
367 IL_ERR("Error: Response NULL in '%s'\n",
e7392364 368 il_get_cmd_string(cmd->id));
0cdc2136
SG		 369 ret = -EIO;
370 goto cancel;
371 }
372
373 ret = 0;
374 goto out;
375
376cancel:
377 if (cmd->flags & CMD_WANT_SKB) {
378 /*
379 * Cancel the CMD_WANT_SKB flag for the cmd in the
380 * TX cmd queue. Otherwise in case the cmd comes
381 * in later, it will possibly set an invalid
382 * address (cmd->meta.source).
383 */
e7392364 384 il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
0cdc2136
SG		 385 }
386fail:
387 if (cmd->reply_page) {
388 il_free_pages(il, cmd->reply_page);
389 cmd->reply_page = 0;
390 }
391out:
392 return ret;
393}
394EXPORT_SYMBOL(il_send_cmd_sync);
395
e7392364
SG		 396int
397il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 398{
399 if (cmd->flags & CMD_ASYNC)
400 return il_send_cmd_async(il, cmd);
401
402 return il_send_cmd_sync(il, cmd);
403}
404EXPORT_SYMBOL(il_send_cmd);
405
406int
407il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
408{
409 struct il_host_cmd cmd = {
410 .id = id,
411 .len = len,
412 .data = data,
413 };
414
415 return il_send_cmd_sync(il, &cmd);
416}
417EXPORT_SYMBOL(il_send_cmd_pdu);
418
e7392364
SG		 419int
420il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 421 void (*callback) (struct il_priv *il,
422 struct il_device_cmd *cmd,
423 struct il_rx_pkt *pkt))
0cdc2136
SG		 424{
425 struct il_host_cmd cmd = {
426 .id = id,
427 .len = len,
428 .data = data,
429 };
430
431 cmd.flags |= CMD_ASYNC;
432 cmd.callback = callback;
433
434 return il_send_cmd_async(il, &cmd);
435}
436EXPORT_SYMBOL(il_send_cmd_pdu_async);
437
438/* default: IL_LED_BLINK(0) using blinking idx table */
439static int led_mode;
440module_param(led_mode, int, S_IRUGO);
e7392364
SG		 441MODULE_PARM_DESC(led_mode,
442 "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
0cdc2136
SG		 443
444/* Throughput OFF time(ms) ON time (ms)
445 * >300 25 25
446 * >200 to 300 40 40
447 * >100 to 200 55 55
448 * >70 to 100 65 65
449 * >50 to 70 75 75
450 * >20 to 50 85 85
451 * >10 to 20 95 95
452 * >5 to 10 110 110
453 * >1 to 5 130 130
454 * >0 to 1 167 167
455 * <=0 SOLID ON
456 */
457static const struct ieee80211_tpt_blink il_blink[] = {
1722f8e1
SG		 458 {.throughput = 0, .blink_time = 334},
459 {.throughput = 1 * 1024 - 1, .blink_time = 260},
460 {.throughput = 5 * 1024 - 1, .blink_time = 220},
461 {.throughput = 10 * 1024 - 1, .blink_time = 190},
462 {.throughput = 20 * 1024 - 1, .blink_time = 170},
463 {.throughput = 50 * 1024 - 1, .blink_time = 150},
464 {.throughput = 70 * 1024 - 1, .blink_time = 130},
465 {.throughput = 100 * 1024 - 1, .blink_time = 110},
466 {.throughput = 200 * 1024 - 1, .blink_time = 80},
467 {.throughput = 300 * 1024 - 1, .blink_time = 50},
0cdc2136
SG		 468};
469
470/*
471 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
472 * Led blink rate analysis showed an average deviation of 0% on 3945,
473 * 5% on 4965 HW.
474 * Need to compensate on the led on/off time per HW according to the deviation
475 * to achieve the desired led frequency
476 * The calculation is: (100-averageDeviation)/100 * blinkTime
477 * For code efficiency the calculation will be:
478 * compensation = (100 - averageDeviation) * 64 / 100
479 * NewBlinkTime = (compensation * BlinkTime) / 64
480 */
e7392364
SG		 481static inline u8
482il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
0cdc2136
SG		 483{
484 if (!compensation) {
485 IL_ERR("undefined blink compensation: "
e7392364 486 "use pre-defined blinking time\n");
0cdc2136
SG		 487 return time;
488 }
489
e7392364 490 return (u8) ((time * compensation) >> 6);
0cdc2136
SG		 491}
492
493/* Set led pattern command */
e7392364
SG		 494static int
495il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
0cdc2136
SG		 496{
497 struct il_led_cmd led_cmd = {
498 .id = IL_LED_LINK,
499 .interval = IL_DEF_LED_INTRVL
500 };
501 int ret;
502
503 if (!test_bit(S_READY, &il->status))
504 return -EBUSY;
505
506 if (il->blink_on == on && il->blink_off == off)
507 return 0;
508
509 if (off == 0) {
510 /* led is SOLID_ON */
511 on = IL_LED_SOLID;
512 }
513
514 D_LED("Led blink time compensation=%u\n",
e7392364
SG		 515 il->cfg->base_params->led_compensation);
516 led_cmd.on =
517 il_blink_compensation(il, on,
518 il->cfg->base_params->led_compensation);
519 led_cmd.off =
520 il_blink_compensation(il, off,
521 il->cfg->base_params->led_compensation);
0cdc2136
SG		 522
523 ret = il->cfg->ops->led->cmd(il, &led_cmd);
524 if (!ret) {
525 il->blink_on = on;
526 il->blink_off = off;
527 }
528 return ret;
529}
530
e7392364
SG		 531static void
532il_led_brightness_set(struct led_classdev *led_cdev,
533 enum led_brightness brightness)
0cdc2136
SG		 534{
535 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
536 unsigned long on = 0;
537
538 if (brightness > 0)
539 on = IL_LED_SOLID;
540
541 il_led_cmd(il, on, 0);
542}
543
e7392364
SG		 544static int
545il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
546 unsigned long *delay_off)
0cdc2136
SG		 547{
548 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
549
550 return il_led_cmd(il, *delay_on, *delay_off);
551}
552
e7392364
SG		 553void
554il_leds_init(struct il_priv *il)
0cdc2136
SG		 555{
556 int mode = led_mode;
557 int ret;
558
559 if (mode == IL_LED_DEFAULT)
560 mode = il->cfg->led_mode;
561
e7392364
SG		 562 il->led.name =
563 kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
0cdc2136
SG		 564 il->led.brightness_set = il_led_brightness_set;
565 il->led.blink_set = il_led_blink_set;
566 il->led.max_brightness = 1;
567
568 switch (mode) {
569 case IL_LED_DEFAULT:
570 WARN_ON(1);
571 break;
572 case IL_LED_BLINK:
573 il->led.default_trigger =
e7392364
SG		 574 ieee80211_create_tpt_led_trigger(il->hw,
575 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
576 il_blink,
577 ARRAY_SIZE(il_blink));
0cdc2136
SG		 578 break;
579 case IL_LED_RF_STATE:
e7392364 580 il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
0cdc2136
SG		 581 break;
582 }
583
584 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
585 if (ret) {
586 kfree(il->led.name);
587 return;
588 }
589
590 il->led_registered = true;
591}
592EXPORT_SYMBOL(il_leds_init);
593
e7392364
SG		 594void
595il_leds_exit(struct il_priv *il)
0cdc2136
SG		 596{
597 if (!il->led_registered)
598 return;
599
600 led_classdev_unregister(&il->led);
601 kfree(il->led.name);
602}
603EXPORT_SYMBOL(il_leds_exit);
604
605/************************** EEPROM BANDS ****************************
606 *
607 * The il_eeprom_band definitions below provide the mapping from the
608 * EEPROM contents to the specific channel number supported for each
609 * band.
610 *
611 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
612 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
613 * The specific geography and calibration information for that channel
614 * is contained in the eeprom map itself.
615 *
616 * During init, we copy the eeprom information and channel map
617 * information into il->channel_info_24/52 and il->channel_map_24/52
618 *
619 * channel_map_24/52 provides the idx in the channel_info array for a
620 * given channel. We have to have two separate maps as there is channel
621 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
622 * band_2
623 *
624 * A value of 0xff stored in the channel_map indicates that the channel
625 * is not supported by the hardware at all.
626 *
627 * A value of 0xfe in the channel_map indicates that the channel is not
628 * valid for Tx with the current hardware. This means that
629 * while the system can tune and receive on a given channel, it may not
630 * be able to associate or transmit any frames on that
631 * channel. There is no corresponding channel information for that
632 * entry.
633 *
634 *********************************************************************/
635
636/* 2.4 GHz */
637const u8 il_eeprom_band_1[14] = {
638 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
639};
640
641/* 5.2 GHz bands */
642static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
643 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
644};
645
646static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
647 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
648};
649
650static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
651 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
652};
653
654static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
655 145, 149, 153, 157, 161, 165
656};
657
e7392364 658static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
0cdc2136
SG		 659 1, 2, 3, 4, 5, 6, 7
660};
661
e7392364 662static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
0cdc2136
SG		 663 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
664};
665
666/******************************************************************************
667 *
668 * EEPROM related functions
669 *
670******************************************************************************/
671
e7392364
SG		 672static int
673il_eeprom_verify_signature(struct il_priv *il)
0cdc2136
SG		 674{
675 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
676 int ret = 0;
677
678 D_EEPROM("EEPROM signature=0x%08x\n", gp);
679 switch (gp) {
680 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
681 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
682 break;
683 default:
e7392364 684 IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
0cdc2136
SG		 685 ret = -ENOENT;
686 break;
687 }
688 return ret;
689}
690
e7392364
SG		 691const u8 *
692il_eeprom_query_addr(const struct il_priv *il, size_t offset)
0cdc2136
SG		 693{
694 BUG_ON(offset >= il->cfg->base_params->eeprom_size);
695 return &il->eeprom[offset];
696}
697EXPORT_SYMBOL(il_eeprom_query_addr);
698
e7392364 699u16
1722f8e1 700il_eeprom_query16(const struct il_priv *il, size_t offset)
0cdc2136
SG		 701{
702 if (!il->eeprom)
703 return 0;
e7392364 704 return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
0cdc2136
SG		 705}
706EXPORT_SYMBOL(il_eeprom_query16);
707
708/**
709 * il_eeprom_init - read EEPROM contents
710 *
711 * Load the EEPROM contents from adapter into il->eeprom
712 *
713 * NOTE: This routine uses the non-debug IO access functions.
714 */
e7392364
SG		 715int
716il_eeprom_init(struct il_priv *il)
0cdc2136
SG		 717{
718 __le16 *e;
719 u32 gp = _il_rd(il, CSR_EEPROM_GP);
720 int sz;
721 int ret;
722 u16 addr;
723
724 /* allocate eeprom */
725 sz = il->cfg->base_params->eeprom_size;
726 D_EEPROM("NVM size = %d\n", sz);
727 il->eeprom = kzalloc(sz, GFP_KERNEL);
728 if (!il->eeprom) {
729 ret = -ENOMEM;
730 goto alloc_err;
731 }
e7392364 732 e = (__le16 *) il->eeprom;
0cdc2136
SG		 733
734 il->cfg->ops->lib->apm_ops.init(il);
735
736 ret = il_eeprom_verify_signature(il);
737 if (ret < 0) {
738 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
739 ret = -ENOENT;
740 goto err;
741 }
742
743 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
744 ret = il->cfg->ops->lib->eeprom_ops.acquire_semaphore(il);
745 if (ret < 0) {
746 IL_ERR("Failed to acquire EEPROM semaphore.\n");
747 ret = -ENOENT;
748 goto err;
749 }
750
751 /* eeprom is an array of 16bit values */
752 for (addr = 0; addr < sz; addr += sizeof(u16)) {
753 u32 r;
754
755 _il_wr(il, CSR_EEPROM_REG,
e7392364 756 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0cdc2136 757
e7392364
SG		 758 ret =
759 _il_poll_bit(il, CSR_EEPROM_REG,
760 CSR_EEPROM_REG_READ_VALID_MSK,
761 CSR_EEPROM_REG_READ_VALID_MSK,
762 IL_EEPROM_ACCESS_TIMEOUT);
0cdc2136 763 if (ret < 0) {
e7392364 764 IL_ERR("Time out reading EEPROM[%d]\n", addr);
0cdc2136
SG		 765 goto done;
766 }
767 r = _il_rd(il, CSR_EEPROM_REG);
768 e[addr / 2] = cpu_to_le16(r >> 16);
769 }
770
e7392364
SG		 771 D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
772 il_eeprom_query16(il, EEPROM_VERSION));
0cdc2136
SG		 773
774 ret = 0;
775done:
776 il->cfg->ops->lib->eeprom_ops.release_semaphore(il);
777
778err:
779 if (ret)
780 il_eeprom_free(il);
781 /* Reset chip to save power until we load uCode during "up". */
782 il_apm_stop(il);
783alloc_err:
784 return ret;
785}
786EXPORT_SYMBOL(il_eeprom_init);
787
e7392364
SG		 788void
789il_eeprom_free(struct il_priv *il)
0cdc2136
SG		 790{
791 kfree(il->eeprom);
792 il->eeprom = NULL;
793}
794EXPORT_SYMBOL(il_eeprom_free);
795
e7392364
SG		 796static void
797il_init_band_reference(const struct il_priv *il, int eep_band,
798 int *eeprom_ch_count,
799 const struct il_eeprom_channel **eeprom_ch_info,
1722f8e1 800 const u8 **eeprom_ch_idx)
0cdc2136 801{
e7392364
SG		 802 u32 offset =
803 il->cfg->ops->lib->eeprom_ops.regulatory_bands[eep_band - 1];
0cdc2136
SG		 804 switch (eep_band) {
805 case 1: /* 2.4GHz band */
806 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
e7392364
SG		 807 *eeprom_ch_info =
808 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
809 offset);
0cdc2136
SG		 810 *eeprom_ch_idx = il_eeprom_band_1;
811 break;
812 case 2: /* 4.9GHz band */
813 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
e7392364
SG		 814 *eeprom_ch_info =
815 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
816 offset);
0cdc2136
SG		 817 *eeprom_ch_idx = il_eeprom_band_2;
818 break;
819 case 3: /* 5.2GHz band */
820 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
e7392364
SG		 821 *eeprom_ch_info =
822 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
823 offset);
0cdc2136
SG		 824 *eeprom_ch_idx = il_eeprom_band_3;
825 break;
826 case 4: /* 5.5GHz band */
827 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
e7392364
SG		 828 *eeprom_ch_info =
829 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
830 offset);
0cdc2136
SG		 831 *eeprom_ch_idx = il_eeprom_band_4;
832 break;
833 case 5: /* 5.7GHz band */
834 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
e7392364
SG		 835 *eeprom_ch_info =
836 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
837 offset);
0cdc2136
SG		 838 *eeprom_ch_idx = il_eeprom_band_5;
839 break;
840 case 6: /* 2.4GHz ht40 channels */
841 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
e7392364
SG		 842 *eeprom_ch_info =
843 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
844 offset);
0cdc2136
SG		 845 *eeprom_ch_idx = il_eeprom_band_6;
846 break;
847 case 7: /* 5 GHz ht40 channels */
848 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
e7392364
SG		 849 *eeprom_ch_info =
850 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
851 offset);
0cdc2136
SG		 852 *eeprom_ch_idx = il_eeprom_band_7;
853 break;
854 default:
855 BUG();
856 }
857}
858
859#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
860 ? # x " " : "")
861/**
862 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
863 *
864 * Does not set up a command, or touch hardware.
865 */
e7392364
SG		 866static int
867il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
868 const struct il_eeprom_channel *eeprom_ch,
869 u8 clear_ht40_extension_channel)
0cdc2136
SG		 870{
871 struct il_channel_info *ch_info;
872
e7392364
SG		 873 ch_info =
874 (struct il_channel_info *)il_get_channel_info(il, band, channel);
0cdc2136
SG		 875
876 if (!il_is_channel_valid(ch_info))
877 return -1;
878
879 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
e7392364
SG		 880 " Ad-Hoc %ssupported\n", ch_info->channel,
881 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
882 CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
883 CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
884 CHECK_AND_PRINT(DFS), eeprom_ch->flags,
885 eeprom_ch->max_power_avg,
886 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
887 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
0cdc2136
SG		 888
889 ch_info->ht40_eeprom = *eeprom_ch;
890 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
891 ch_info->ht40_flags = eeprom_ch->flags;
892 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
893 ch_info->ht40_extension_channel &=
e7392364 894 ~clear_ht40_extension_channel;
0cdc2136
SG		 895
896 return 0;
897}
898
899#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
900 ? # x " " : "")
901
902/**
903 * il_init_channel_map - Set up driver's info for all possible channels
904 */
e7392364
SG		 905int
906il_init_channel_map(struct il_priv *il)
0cdc2136
SG		 907{
908 int eeprom_ch_count = 0;
909 const u8 *eeprom_ch_idx = NULL;
910 const struct il_eeprom_channel *eeprom_ch_info = NULL;
911 int band, ch;
912 struct il_channel_info *ch_info;
913
914 if (il->channel_count) {
915 D_EEPROM("Channel map already initialized.\n");
916 return 0;
917 }
918
919 D_EEPROM("Initializing regulatory info from EEPROM\n");
920
921 il->channel_count =
e7392364
SG		 922 ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
923 ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
0cdc2136
SG		 924 ARRAY_SIZE(il_eeprom_band_5);
925
e7392364 926 D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
0cdc2136 927
e7392364
SG		 928 il->channel_info =
929 kzalloc(sizeof(struct il_channel_info) * il->channel_count,
930 GFP_KERNEL);
0cdc2136
SG		 931 if (!il->channel_info) {
932 IL_ERR("Could not allocate channel_info\n");
933 il->channel_count = 0;
934 return -ENOMEM;
935 }
936
937 ch_info = il->channel_info;
938
939 /* Loop through the 5 EEPROM bands adding them in order to the
940 * channel map we maintain (that contains additional information than
941 * what just in the EEPROM) */
942 for (band = 1; band <= 5; band++) {
943
944 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 945 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 946
947 /* Loop through each band adding each of the channels */
948 for (ch = 0; ch < eeprom_ch_count; ch++) {
949 ch_info->channel = eeprom_ch_idx[ch];
e7392364
SG		 950 ch_info->band =
951 (band ==
952 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 953
954 /* permanently store EEPROM's channel regulatory flags
955 * and max power in channel info database. */
956 ch_info->eeprom = eeprom_ch_info[ch];
957
958 /* Copy the run-time flags so they are there even on
959 * invalid channels */
960 ch_info->flags = eeprom_ch_info[ch].flags;
961 /* First write that ht40 is not enabled, and then enable
962 * one by one */
963 ch_info->ht40_extension_channel =
e7392364 964 IEEE80211_CHAN_NO_HT40;
0cdc2136
SG		 965
966 if (!(il_is_channel_valid(ch_info))) {
e7392364
SG		 967 D_EEPROM("Ch. %d Flags %x [%sGHz] - "
968 "No traffic\n", ch_info->channel,
969 ch_info->flags,
970 il_is_channel_a_band(ch_info) ? "5.2" :
971 "2.4");
0cdc2136
SG		 972 ch_info++;
973 continue;
974 }
975
976 /* Initialize regulatory-based run-time data */
977 ch_info->max_power_avg = ch_info->curr_txpow =
978 eeprom_ch_info[ch].max_power_avg;
979 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
980 ch_info->min_power = 0;
981
e7392364
SG		 982 D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
983 " Ad-Hoc %ssupported\n", ch_info->channel,
984 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
985 CHECK_AND_PRINT_I(VALID),
986 CHECK_AND_PRINT_I(IBSS),
987 CHECK_AND_PRINT_I(ACTIVE),
988 CHECK_AND_PRINT_I(RADAR),
989 CHECK_AND_PRINT_I(WIDE),
990 CHECK_AND_PRINT_I(DFS),
991 eeprom_ch_info[ch].flags,
992 eeprom_ch_info[ch].max_power_avg,
993 ((eeprom_ch_info[ch].
994 flags & EEPROM_CHANNEL_IBSS) &&
995 !(eeprom_ch_info[ch].
996 flags & EEPROM_CHANNEL_RADAR)) ? "" :
997 "not ");
0cdc2136
SG		 998
999 ch_info++;
1000 }
1001 }
1002
1003 /* Check if we do have HT40 channels */
1004 if (il->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
1005 EEPROM_REGULATORY_BAND_NO_HT40 &&
1006 il->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
1007 EEPROM_REGULATORY_BAND_NO_HT40)
1008 return 0;
1009
1010 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1011 for (band = 6; band <= 7; band++) {
1012 enum ieee80211_band ieeeband;
1013
1014 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 1015 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 1016
1017 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1018 ieeeband =
e7392364 1019 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 1020
1021 /* Loop through each band adding each of the channels */
1022 for (ch = 0; ch < eeprom_ch_count; ch++) {
1023 /* Set up driver's info for lower half */
e7392364
SG		 1024 il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
1025 &eeprom_ch_info[ch],
1026 IEEE80211_CHAN_NO_HT40PLUS);
0cdc2136
SG		 1027
1028 /* Set up driver's info for upper half */
1029 il_mod_ht40_chan_info(il, ieeeband,
e7392364
SG		 1030 eeprom_ch_idx[ch] + 4,
1031 &eeprom_ch_info[ch],
1032 IEEE80211_CHAN_NO_HT40MINUS);
0cdc2136
SG		 1033 }
1034 }
1035
1036 return 0;
1037}
1038EXPORT_SYMBOL(il_init_channel_map);
1039
1040/*
1041 * il_free_channel_map - undo allocations in il_init_channel_map
1042 */
e7392364
SG		 1043void
1044il_free_channel_map(struct il_priv *il)
0cdc2136
SG		 1045{
1046 kfree(il->channel_info);
1047 il->channel_count = 0;
1048}
1049EXPORT_SYMBOL(il_free_channel_map);
1050
1051/**
1052 * il_get_channel_info - Find driver's ilate channel info
1053 *
1054 * Based on band and channel number.
1055 */
e7392364
SG		 1056const struct il_channel_info *
1057il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
1058 u16 channel)
0cdc2136
SG		 1059{
1060 int i;
1061
1062 switch (band) {
1063 case IEEE80211_BAND_5GHZ:
1064 for (i = 14; i < il->channel_count; i++) {
1065 if (il->channel_info[i].channel == channel)
1066 return &il->channel_info[i];
1067 }
1068 break;
1069 case IEEE80211_BAND_2GHZ:
1070 if (channel >= 1 && channel <= 14)
1071 return &il->channel_info[channel - 1];
1072 break;
1073 default:
1074 BUG();
1075 }
1076
1077 return NULL;
1078}
1079EXPORT_SYMBOL(il_get_channel_info);
1080
1081/*
1082 * Setting power level allows the card to go to sleep when not busy.
1083 *
1084 * We calculate a sleep command based on the required latency, which
1085 * we get from mac80211. In order to handle thermal throttling, we can
1086 * also use pre-defined power levels.
1087 */
1088
1089/*
1090 * This defines the old power levels. They are still used by default
1091 * (level 1) and for thermal throttle (levels 3 through 5)
1092 */
1093
1094struct il_power_vec_entry {
1095 struct il_powertable_cmd cmd;
e7392364 1096 u8 no_dtim; /* number of skip dtim */
0cdc2136
SG		 1097};
1098
e7392364
SG		 1099static void
1100il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
0cdc2136
SG		 1101{
1102 memset(cmd, 0, sizeof(*cmd));
1103
1104 if (il->power_data.pci_pm)
1105 cmd->flags |= IL_POWER_PCI_PM_MSK;
1106
1107 D_POWER("Sleep command for CAM\n");
1108}
1109
1110static int
1111il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
1112{
1113 D_POWER("Sending power/sleep command\n");
1114 D_POWER("Flags value = 0x%08X\n", cmd->flags);
e7392364
SG		 1115 D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1116 D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1117 D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1118 le32_to_cpu(cmd->sleep_interval[0]),
1119 le32_to_cpu(cmd->sleep_interval[1]),
1120 le32_to_cpu(cmd->sleep_interval[2]),
1121 le32_to_cpu(cmd->sleep_interval[3]),
1122 le32_to_cpu(cmd->sleep_interval[4]));
0cdc2136
SG		 1123
1124 return il_send_cmd_pdu(il, C_POWER_TBL,
e7392364 1125 sizeof(struct il_powertable_cmd), cmd);
0cdc2136
SG		 1126}
1127
1128int
e7392364 1129il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
0cdc2136
SG		 1130{
1131 int ret;
1132 bool update_chains;
1133
1134 lockdep_assert_held(&il->mutex);
1135
1136 /* Don't update the RX chain when chain noise calibration is running */
1137 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
e7392364 1138 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
0cdc2136
SG		 1139
1140 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
1141 return 0;
1142
1143 if (!il_is_ready_rf(il))
1144 return -EIO;
1145
1146 /* scan complete use sleep_power_next, need to be updated */
1147 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
1148 if (test_bit(S_SCANNING, &il->status) && !force) {
1149 D_INFO("Defer power set mode while scanning\n");
1150 return 0;
1151 }
1152
1153 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1154 set_bit(S_POWER_PMI, &il->status);
1155
1156 ret = il_set_power(il, cmd);
1157 if (!ret) {
1158 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1159 clear_bit(S_POWER_PMI, &il->status);
1160
1161 if (il->cfg->ops->lib->update_chain_flags && update_chains)
1162 il->cfg->ops->lib->update_chain_flags(il);
1163 else if (il->cfg->ops->lib->update_chain_flags)
e7392364
SG		 1164 D_POWER("Cannot update the power, chain noise "
1165 "calibration running: %d\n",
1166 il->chain_noise_data.state);
0cdc2136
SG		 1167
1168 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1169 } else
1170 IL_ERR("set power fail, ret = %d", ret);
1171
1172 return ret;
1173}
1174
e7392364
SG		 1175int
1176il_power_update_mode(struct il_priv *il, bool force)
0cdc2136
SG		 1177{
1178 struct il_powertable_cmd cmd;
1179
1180 il_power_sleep_cam_cmd(il, &cmd);
1181 return il_power_set_mode(il, &cmd, force);
1182}
1183EXPORT_SYMBOL(il_power_update_mode);
1184
1185/* initialize to default */
e7392364
SG		 1186void
1187il_power_initialize(struct il_priv *il)
0cdc2136
SG		 1188{
1189 u16 lctl = il_pcie_link_ctl(il);
1190
1191 il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
1192
1193 il->power_data.debug_sleep_level_override = -1;
1194
e7392364 1195 memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
0cdc2136
SG		 1196}
1197EXPORT_SYMBOL(il_power_initialize);
1198
1199/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1200 * sending probe req. This should be set long enough to hear probe responses
1201 * from more than one AP. */
e7392364 1202#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
0cdc2136
SG		 1203#define IL_ACTIVE_DWELL_TIME_52 (20)
1204
1205#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1206#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1207
1208/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1209 * Must be set longer than active dwell time.
1210 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
e7392364 1211#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
0cdc2136
SG		 1212#define IL_PASSIVE_DWELL_TIME_52 (10)
1213#define IL_PASSIVE_DWELL_BASE (100)
1214#define IL_CHANNEL_TUNE_TIME 5
1215
e7392364
SG		 1216static int
1217il_send_scan_abort(struct il_priv *il)
0cdc2136
SG		 1218{
1219 int ret;
1220 struct il_rx_pkt *pkt;
1221 struct il_host_cmd cmd = {
1222 .id = C_SCAN_ABORT,
1223 .flags = CMD_WANT_SKB,
1224 };
1225
1226 /* Exit instantly with error when device is not ready
1227 * to receive scan abort command or it does not perform
1228 * hardware scan currently */
1229 if (!test_bit(S_READY, &il->status) ||
1230 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1231 !test_bit(S_SCAN_HW, &il->status) ||
1232 test_bit(S_FW_ERROR, &il->status) ||
1233 test_bit(S_EXIT_PENDING, &il->status))
1234 return -EIO;
1235
1236 ret = il_send_cmd_sync(il, &cmd);
1237 if (ret)
1238 return ret;
1239
1240 pkt = (struct il_rx_pkt *)cmd.reply_page;
1241 if (pkt->u.status != CAN_ABORT_STATUS) {
1242 /* The scan abort will return 1 for success or
1243 * 2 for "failure". A failure condition can be
1244 * due to simply not being in an active scan which
1245 * can occur if we send the scan abort before we
1246 * the microcode has notified us that a scan is
1247 * completed. */
1248 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1249 ret = -EIO;
1250 }
1251
1252 il_free_pages(il, cmd.reply_page);
1253 return ret;
1254}
1255
e7392364
SG		 1256static void
1257il_complete_scan(struct il_priv *il, bool aborted)
0cdc2136
SG		 1258{
1259 /* check if scan was requested from mac80211 */
1260 if (il->scan_request) {
1261 D_SCAN("Complete scan in mac80211\n");
1262 ieee80211_scan_completed(il->hw, aborted);
1263 }
1264
1265 il->scan_vif = NULL;
1266 il->scan_request = NULL;
1267}
1268
e7392364
SG		 1269void
1270il_force_scan_end(struct il_priv *il)
0cdc2136
SG		 1271{
1272 lockdep_assert_held(&il->mutex);
1273
1274 if (!test_bit(S_SCANNING, &il->status)) {
1275 D_SCAN("Forcing scan end while not scanning\n");
1276 return;
1277 }
1278
1279 D_SCAN("Forcing scan end\n");
1280 clear_bit(S_SCANNING, &il->status);
1281 clear_bit(S_SCAN_HW, &il->status);
1282 clear_bit(S_SCAN_ABORTING, &il->status);
1283 il_complete_scan(il, true);
1284}
1285
e7392364
SG		 1286static void
1287il_do_scan_abort(struct il_priv *il)
0cdc2136
SG		 1288{
1289 int ret;
1290
1291 lockdep_assert_held(&il->mutex);
1292
1293 if (!test_bit(S_SCANNING, &il->status)) {
1294 D_SCAN("Not performing scan to abort\n");
1295 return;
1296 }
1297
1298 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1299 D_SCAN("Scan abort in progress\n");
1300 return;
1301 }
1302
1303 ret = il_send_scan_abort(il);
1304 if (ret) {
1305 D_SCAN("Send scan abort failed %d\n", ret);
1306 il_force_scan_end(il);
1307 } else
1308 D_SCAN("Successfully send scan abort\n");
1309}
1310
1311/**
1312 * il_scan_cancel - Cancel any currently executing HW scan
1313 */
e7392364
SG		 1314int
1315il_scan_cancel(struct il_priv *il)
0cdc2136
SG		 1316{
1317 D_SCAN("Queuing abort scan\n");
1318 queue_work(il->workqueue, &il->abort_scan);
1319 return 0;
1320}
1321EXPORT_SYMBOL(il_scan_cancel);
1322
1323/**
1324 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1325 * @ms: amount of time to wait (in milliseconds) for scan to abort
1326 *
1327 */
e7392364
SG		 1328int
1329il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
0cdc2136
SG		 1330{
1331 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1332
1333 lockdep_assert_held(&il->mutex);
1334
1335 D_SCAN("Scan cancel timeout\n");
1336
1337 il_do_scan_abort(il);
1338
1339 while (time_before_eq(jiffies, timeout)) {
1340 if (!test_bit(S_SCAN_HW, &il->status))
1341 break;
1342 msleep(20);
1343 }
1344
1345 return test_bit(S_SCAN_HW, &il->status);
1346}
1347EXPORT_SYMBOL(il_scan_cancel_timeout);
1348
1349/* Service response to C_SCAN (0x80) */
e7392364
SG		 1350static void
1351il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1352{
1353#ifdef CONFIG_IWLEGACY_DEBUG
1354 struct il_rx_pkt *pkt = rxb_addr(rxb);
1355 struct il_scanreq_notification *notif =
1356 (struct il_scanreq_notification *)pkt->u.raw;
1357
1358 D_SCAN("Scan request status = 0x%x\n", notif->status);
1359#endif
1360}
1361
1362/* Service N_SCAN_START (0x82) */
e7392364
SG		 1363static void
1364il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1365{
1366 struct il_rx_pkt *pkt = rxb_addr(rxb);
1367 struct il_scanstart_notification *notif =
1368 (struct il_scanstart_notification *)pkt->u.raw;
1369 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
e7392364
SG		 1370 D_SCAN("Scan start: " "%d [802.11%s] "
1371 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
1372 notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
1373 le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
0cdc2136
SG		 1374}
1375
1376/* Service N_SCAN_RESULTS (0x83) */
e7392364
SG		 1377static void
1378il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1379{
1380#ifdef CONFIG_IWLEGACY_DEBUG
1381 struct il_rx_pkt *pkt = rxb_addr(rxb);
1382 struct il_scanresults_notification *notif =
1383 (struct il_scanresults_notification *)pkt->u.raw;
1384
e7392364
SG		 1385 D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
1386 "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
1387 le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
1388 le32_to_cpu(notif->stats[0]),
1389 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
0cdc2136
SG		 1390#endif
1391}
1392
1393/* Service N_SCAN_COMPLETE (0x84) */
e7392364
SG		 1394static void
1395il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1396{
1397
1398#ifdef CONFIG_IWLEGACY_DEBUG
1399 struct il_rx_pkt *pkt = rxb_addr(rxb);
1400 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1401#endif
1402
e7392364
SG		 1403 D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1404 scan_notif->scanned_channels, scan_notif->tsf_low,
1405 scan_notif->tsf_high, scan_notif->status);
0cdc2136
SG		 1406
1407 /* The HW is no longer scanning */
1408 clear_bit(S_SCAN_HW, &il->status);
1409
1410 D_SCAN("Scan on %sGHz took %dms\n",
e7392364
SG		 1411 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1412 jiffies_to_msecs(jiffies - il->scan_start));
0cdc2136
SG		 1413
1414 queue_work(il->workqueue, &il->scan_completed);
1415}
1416
e7392364
SG		 1417void
1418il_setup_rx_scan_handlers(struct il_priv *il)
0cdc2136
SG		 1419{
1420 /* scan handlers */
1421 il->handlers[C_SCAN] = il_hdl_scan;
e7392364
SG		 1422 il->handlers[N_SCAN_START] = il_hdl_scan_start;
1423 il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
1424 il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
0cdc2136
SG		 1425}
1426EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1427
e7392364
SG		 1428inline u16
1429il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1430 u8 n_probes)
0cdc2136
SG		 1431{
1432 if (band == IEEE80211_BAND_5GHZ)
1433 return IL_ACTIVE_DWELL_TIME_52 +
e7392364 1434 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
0cdc2136
SG		 1435 else
1436 return IL_ACTIVE_DWELL_TIME_24 +
e7392364 1437 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
0cdc2136
SG		 1438}
1439EXPORT_SYMBOL(il_get_active_dwell_time);
1440
e7392364 1441u16
1722f8e1
SG		 1442il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1443 struct ieee80211_vif *vif)
0cdc2136
SG		 1444{
1445 struct il_rxon_context *ctx = &il->ctx;
1446 u16 value;
1447
e7392364
SG		 1448 u16 passive =
1449 (band ==
1450 IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
1451 IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
1452 IL_PASSIVE_DWELL_TIME_52;
0cdc2136
SG		 1453
1454 if (il_is_any_associated(il)) {
1455 /*
1456 * If we're associated, we clamp the maximum passive
1457 * dwell time to be 98% of the smallest beacon interval
1458 * (minus 2 * channel tune time)
1459 */
1460 value = ctx->vif ? ctx->vif->bss_conf.beacon_int : 0;
1461 if (value > IL_PASSIVE_DWELL_BASE || !value)
1462 value = IL_PASSIVE_DWELL_BASE;
1463 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1464 passive = min(value, passive);
1465 }
1466
1467 return passive;
1468}
1469EXPORT_SYMBOL(il_get_passive_dwell_time);
1470
e7392364
SG		 1471void
1472il_init_scan_params(struct il_priv *il)
0cdc2136
SG		 1473{
1474 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1475 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1476 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1477 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1478 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1479}
1480EXPORT_SYMBOL(il_init_scan_params);
1481
e7392364
SG		 1482static int
1483il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
0cdc2136
SG		 1484{
1485 int ret;
1486
1487 lockdep_assert_held(&il->mutex);
1488
1489 if (WARN_ON(!il->cfg->ops->utils->request_scan))
1490 return -EOPNOTSUPP;
1491
1492 cancel_delayed_work(&il->scan_check);
1493
1494 if (!il_is_ready_rf(il)) {
1495 IL_WARN("Request scan called when driver not ready.\n");
1496 return -EIO;
1497 }
1498
1499 if (test_bit(S_SCAN_HW, &il->status)) {
e7392364 1500 D_SCAN("Multiple concurrent scan requests in parallel.\n");
0cdc2136
SG		 1501 return -EBUSY;
1502 }
1503
1504 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1505 D_SCAN("Scan request while abort pending.\n");
1506 return -EBUSY;
1507 }
1508
1509 D_SCAN("Starting scan...\n");
1510
1511 set_bit(S_SCANNING, &il->status);
1512 il->scan_start = jiffies;
1513
1514 ret = il->cfg->ops->utils->request_scan(il, vif);
1515 if (ret) {
1516 clear_bit(S_SCANNING, &il->status);
1517 return ret;
1518 }
1519
1520 queue_delayed_work(il->workqueue, &il->scan_check,
1521 IL_SCAN_CHECK_WATCHDOG);
1522
1523 return 0;
1524}
1525
e7392364
SG		 1526int
1527il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1528 struct cfg80211_scan_request *req)
0cdc2136
SG		 1529{
1530 struct il_priv *il = hw->priv;
1531 int ret;
1532
1533 D_MAC80211("enter\n");
1534
1535 if (req->n_channels == 0)
1536 return -EINVAL;
1537
1538 mutex_lock(&il->mutex);
1539
1540 if (test_bit(S_SCANNING, &il->status)) {
1541 D_SCAN("Scan already in progress.\n");
1542 ret = -EAGAIN;
1543 goto out_unlock;
1544 }
1545
1546 /* mac80211 will only ask for one band at a time */
1547 il->scan_request = req;
1548 il->scan_vif = vif;
1549 il->scan_band = req->channels[0]->band;
1550
1551 ret = il_scan_initiate(il, vif);
1552
1553 D_MAC80211("leave\n");
1554
1555out_unlock:
1556 mutex_unlock(&il->mutex);
1557
1558 return ret;
1559}
1560EXPORT_SYMBOL(il_mac_hw_scan);
1561
e7392364
SG		 1562static void
1563il_bg_scan_check(struct work_struct *data)
0cdc2136
SG		 1564{
1565 struct il_priv *il =
1566 container_of(data, struct il_priv, scan_check.work);
1567
1568 D_SCAN("Scan check work\n");
1569
1570 /* Since we are here firmware does not finish scan and
1571 * most likely is in bad shape, so we don't bother to
1572 * send abort command, just force scan complete to mac80211 */
1573 mutex_lock(&il->mutex);
1574 il_force_scan_end(il);
1575 mutex_unlock(&il->mutex);
1576}
1577
1578/**
1579 * il_fill_probe_req - fill in all required fields and IE for probe request
1580 */
1581
1582u16
1583il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1584 const u8 *ta, const u8 *ies, int ie_len, int left)
0cdc2136
SG		 1585{
1586 int len = 0;
1587 u8 *pos = NULL;
1588
1589 /* Make sure there is enough space for the probe request,
1590 * two mandatory IEs and the data */
1591 left -= 24;
1592 if (left < 0)
1593 return 0;
1594
1595 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1596 memcpy(frame->da, il_bcast_addr, ETH_ALEN);
1597 memcpy(frame->sa, ta, ETH_ALEN);
1598 memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
1599 frame->seq_ctrl = 0;
1600
1601 len += 24;
1602
1603 /* ...next IE... */
1604 pos = &frame->u.probe_req.variable[0];
1605
1606 /* fill in our indirect SSID IE */
1607 left -= 2;
1608 if (left < 0)
1609 return 0;
1610 *pos++ = WLAN_EID_SSID;
1611 *pos++ = 0;
1612
1613 len += 2;
1614
1615 if (WARN_ON(left < ie_len))
1616 return len;
1617
1618 if (ies && ie_len) {
1619 memcpy(pos, ies, ie_len);
1620 len += ie_len;
1621 }
1622
e7392364 1623 return (u16) len;
0cdc2136
SG		 1624}
1625EXPORT_SYMBOL(il_fill_probe_req);
1626
e7392364
SG		 1627static void
1628il_bg_abort_scan(struct work_struct *work)
0cdc2136
SG		 1629{
1630 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1631
1632 D_SCAN("Abort scan work\n");
1633
1634 /* We keep scan_check work queued in case when firmware will not
1635 * report back scan completed notification */
1636 mutex_lock(&il->mutex);
1637 il_scan_cancel_timeout(il, 200);
1638 mutex_unlock(&il->mutex);
1639}
1640
e7392364
SG		 1641static void
1642il_bg_scan_completed(struct work_struct *work)
0cdc2136 1643{
e7392364 1644 struct il_priv *il = container_of(work, struct il_priv, scan_completed);
0cdc2136
SG		 1645 bool aborted;
1646
1647 D_SCAN("Completed scan.\n");
1648
1649 cancel_delayed_work(&il->scan_check);
1650
1651 mutex_lock(&il->mutex);
1652
1653 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1654 if (aborted)
1655 D_SCAN("Aborted scan completed.\n");
1656
1657 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1658 D_SCAN("Scan already completed.\n");
1659 goto out_settings;
1660 }
1661
1662 il_complete_scan(il, aborted);
1663
1664out_settings:
1665 /* Can we still talk to firmware ? */
1666 if (!il_is_ready_rf(il))
1667 goto out;
1668
1669 /*
1670 * We do not commit power settings while scan is pending,
1671 * do it now if the settings changed.
1672 */
1673 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1674 il_set_tx_power(il, il->tx_power_next, false);
1675
1676 il->cfg->ops->utils->post_scan(il);
1677
1678out:
1679 mutex_unlock(&il->mutex);
1680}
1681
e7392364
SG		 1682void
1683il_setup_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1684{
1685 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1686 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1687 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1688}
1689EXPORT_SYMBOL(il_setup_scan_deferred_work);
1690
e7392364
SG		 1691void
1692il_cancel_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1693{
1694 cancel_work_sync(&il->abort_scan);
1695 cancel_work_sync(&il->scan_completed);
1696
1697 if (cancel_delayed_work_sync(&il->scan_check)) {
1698 mutex_lock(&il->mutex);
1699 il_force_scan_end(il);
1700 mutex_unlock(&il->mutex);
1701 }
1702}
1703EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1704
1705/* il->sta_lock must be held */
e7392364
SG		 1706static void
1707il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 1708{
1709
1710 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
e7392364
SG		 1711 IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
1712 sta_id, il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1713
1714 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
e7392364
SG		 1715 D_ASSOC("STA id %u addr %pM already present"
1716 " in uCode (according to driver)\n", sta_id,
1717 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1718 } else {
1719 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
e7392364
SG		 1720 D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
1721 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1722 }
1723}
1724
e7392364
SG		 1725static int
1726il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
1727 struct il_rx_pkt *pkt, bool sync)
0cdc2136
SG		 1728{
1729 u8 sta_id = addsta->sta.sta_id;
1730 unsigned long flags;
1731 int ret = -EIO;
1732
1733 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 1734 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 1735 return ret;
1736 }
1737
e7392364 1738 D_INFO("Processing response for adding station %u\n", sta_id);
0cdc2136
SG		 1739
1740 spin_lock_irqsave(&il->sta_lock, flags);
1741
1742 switch (pkt->u.add_sta.status) {
1743 case ADD_STA_SUCCESS_MSK:
1744 D_INFO("C_ADD_STA PASSED\n");
1745 il_sta_ucode_activate(il, sta_id);
1746 ret = 0;
1747 break;
1748 case ADD_STA_NO_ROOM_IN_TBL:
e7392364 1749 IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
0cdc2136
SG		 1750 break;
1751 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
e7392364
SG		 1752 IL_ERR("Adding station %d failed, no block ack resource.\n",
1753 sta_id);
0cdc2136
SG		 1754 break;
1755 case ADD_STA_MODIFY_NON_EXIST_STA:
1756 IL_ERR("Attempting to modify non-existing station %d\n",
e7392364 1757 sta_id);
0cdc2136
SG		 1758 break;
1759 default:
e7392364 1760 D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
0cdc2136
SG		 1761 break;
1762 }
1763
1764 D_INFO("%s station id %u addr %pM\n",
e7392364
SG		 1765 il->stations[sta_id].sta.mode ==
1766 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
1767 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1768
1769 /*
1770 * XXX: The MAC address in the command buffer is often changed from
1771 * the original sent to the device. That is, the MAC address
1772 * written to the command buffer often is not the same MAC address
1773 * read from the command buffer when the command returns. This
1774 * issue has not yet been resolved and this debugging is left to
1775 * observe the problem.
1776 */
1777 D_INFO("%s station according to cmd buffer %pM\n",
e7392364
SG		 1778 il->stations[sta_id].sta.mode ==
1779 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
0cdc2136
SG		 1780 spin_unlock_irqrestore(&il->sta_lock, flags);
1781
1782 return ret;
1783}
1784
e7392364
SG		 1785static void
1786il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
1787 struct il_rx_pkt *pkt)
0cdc2136 1788{
e7392364 1789 struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
0cdc2136
SG		 1790
1791 il_process_add_sta_resp(il, addsta, pkt, false);
1792
1793}
1794
e7392364
SG		 1795int
1796il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
0cdc2136
SG		 1797{
1798 struct il_rx_pkt *pkt = NULL;
1799 int ret = 0;
1800 u8 data[sizeof(*sta)];
1801 struct il_host_cmd cmd = {
1802 .id = C_ADD_STA,
1803 .flags = flags,
1804 .data = data,
1805 };
1806 u8 sta_id __maybe_unused = sta->sta.sta_id;
1807
e7392364
SG		 1808 D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
1809 flags & CMD_ASYNC ? "a" : "");
0cdc2136
SG		 1810
1811 if (flags & CMD_ASYNC)
1812 cmd.callback = il_add_sta_callback;
1813 else {
1814 cmd.flags |= CMD_WANT_SKB;
1815 might_sleep();
1816 }
1817
1818 cmd.len = il->cfg->ops->utils->build_addsta_hcmd(sta, data);
1819 ret = il_send_cmd(il, &cmd);
1820
1821 if (ret || (flags & CMD_ASYNC))
1822 return ret;
1823
1824 if (ret == 0) {
1825 pkt = (struct il_rx_pkt *)cmd.reply_page;
1826 ret = il_process_add_sta_resp(il, sta, pkt, true);
1827 }
1828 il_free_pages(il, cmd.reply_page);
1829
1830 return ret;
1831}
1832EXPORT_SYMBOL(il_send_add_sta);
1833
e7392364
SG		 1834static void
1835il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta,
1836 struct il_rxon_context *ctx)
0cdc2136
SG		 1837{
1838 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1839 __le32 sta_flags;
1840 u8 mimo_ps_mode;
1841
1842 if (!sta || !sta_ht_inf->ht_supported)
1843 goto done;
1844
1845 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
1846 D_ASSOC("spatial multiplexing power save mode: %s\n",
1722f8e1
SG		 1847 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ? "static" :
1848 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ? "dynamic" :
1849 "disabled");
0cdc2136
SG		 1850
1851 sta_flags = il->stations[idx].sta.station_flags;
1852
1853 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1854
1855 switch (mimo_ps_mode) {
1856 case WLAN_HT_CAP_SM_PS_STATIC:
1857 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1858 break;
1859 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1860 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1861 break;
1862 case WLAN_HT_CAP_SM_PS_DISABLED:
1863 break;
1864 default:
1865 IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
1866 break;
1867 }
1868
e7392364
SG		 1869 sta_flags |=
1870 cpu_to_le32((u32) sta_ht_inf->
1871 ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
0cdc2136 1872
e7392364
SG		 1873 sta_flags |=
1874 cpu_to_le32((u32) sta_ht_inf->
1875 ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
0cdc2136
SG		 1876
1877 if (il_is_ht40_tx_allowed(il, ctx, &sta->ht_cap))
1878 sta_flags |= STA_FLG_HT40_EN_MSK;
1879 else
1880 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1881
1882 il->stations[idx].sta.station_flags = sta_flags;
e7392364 1883done:
0cdc2136
SG		 1884 return;
1885}
1886
1887/**
1888 * il_prep_station - Prepare station information for addition
1889 *
1890 * should be called with sta_lock held
1891 */
e7392364 1892u8
1722f8e1
SG		 1893il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
1894 const u8 *addr, bool is_ap, struct ieee80211_sta *sta)
0cdc2136
SG		 1895{
1896 struct il_station_entry *station;
1897 int i;
1898 u8 sta_id = IL_INVALID_STATION;
1899 u16 rate;
1900
1901 if (is_ap)
8f9e5645 1902 sta_id = IL_AP_ID;
0cdc2136 1903 else if (is_broadcast_ether_addr(addr))
b16db50a 1904 sta_id = il->hw_params.bcast_id;
0cdc2136
SG		 1905 else
1906 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
e7392364
SG		 1907 if (!compare_ether_addr
1908 (il->stations[i].sta.sta.addr, addr)) {
0cdc2136
SG		 1909 sta_id = i;
1910 break;
1911 }
1912
1913 if (!il->stations[i].used &&
1914 sta_id == IL_INVALID_STATION)
1915 sta_id = i;
1916 }
1917
1918 /*
1919 * These two conditions have the same outcome, but keep them
1920 * separate
1921 */
1922 if (unlikely(sta_id == IL_INVALID_STATION))
1923 return sta_id;
1924
1925 /*
1926 * uCode is not able to deal with multiple requests to add a
1927 * station. Keep track if one is in progress so that we do not send
1928 * another.
1929 */
1930 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1931 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1932 return sta_id;
1933 }
1934
1935 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1936 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
1937 !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) {
e7392364
SG		 1938 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
1939 sta_id, addr);
0cdc2136
SG		 1940 return sta_id;
1941 }
1942
1943 station = &il->stations[sta_id];
1944 station->used = IL_STA_DRIVER_ACTIVE;
e7392364 1945 D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
0cdc2136
SG		 1946 il->num_stations++;
1947
1948 /* Set up the C_ADD_STA command to send to device */
1949 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1950 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1951 station->sta.mode = 0;
1952 station->sta.sta.sta_id = sta_id;
fd6415bc 1953 station->sta.station_flags = 0;
0cdc2136
SG		 1954
1955 if (sta) {
1956 struct il_station_priv_common *sta_priv;
1957
1958 sta_priv = (void *)sta->drv_priv;
1959 sta_priv->ctx = ctx;
1960 }
1961
1962 /*
1963 * OK to call unconditionally, since local stations (IBSS BSSID
1964 * STA and broadcast STA) pass in a NULL sta, and mac80211
1965 * doesn't allow HT IBSS.
1966 */
1967 il_set_ht_add_station(il, sta_id, sta, ctx);
1968
1969 /* 3945 only */
e7392364 1970 rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
0cdc2136
SG		 1971 /* Turn on both antennas for the station... */
1972 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
1973
1974 return sta_id;
1975
1976}
1977EXPORT_SYMBOL_GPL(il_prep_station);
1978
1979#define STA_WAIT_TIMEOUT (HZ/2)
1980
1981/**
1982 * il_add_station_common -
1983 */
1984int
e7392364 1985il_add_station_common(struct il_priv *il, struct il_rxon_context *ctx,
1722f8e1
SG		 1986 const u8 *addr, bool is_ap, struct ieee80211_sta *sta,
1987 u8 *sta_id_r)
0cdc2136
SG		 1988{
1989 unsigned long flags_spin;
1990 int ret = 0;
1991 u8 sta_id;
1992 struct il_addsta_cmd sta_cmd;
1993
1994 *sta_id_r = 0;
1995 spin_lock_irqsave(&il->sta_lock, flags_spin);
1996 sta_id = il_prep_station(il, ctx, addr, is_ap, sta);
1997 if (sta_id == IL_INVALID_STATION) {
e7392364 1998 IL_ERR("Unable to prepare station %pM for addition\n", addr);
0cdc2136
SG		 1999 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2000 return -EINVAL;
2001 }
2002
2003 /*
2004 * uCode is not able to deal with multiple requests to add a
2005 * station. Keep track if one is in progress so that we do not send
2006 * another.
2007 */
2008 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 2009 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 2010 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2011 return -EEXIST;
2012 }
2013
2014 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
2015 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2016 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
0cdc2136
SG		 2017 sta_id, addr);
2018 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2019 return -EEXIST;
2020 }
2021
2022 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
2023 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 2024 sizeof(struct il_addsta_cmd));
0cdc2136
SG		 2025 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2026
2027 /* Add station to device's station table */
2028 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2029 if (ret) {
2030 spin_lock_irqsave(&il->sta_lock, flags_spin);
2031 IL_ERR("Adding station %pM failed.\n",
e7392364 2032 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 2033 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2034 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2035 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2036 }
2037 *sta_id_r = sta_id;
2038 return ret;
2039}
2040EXPORT_SYMBOL(il_add_station_common);
2041
2042/**
2043 * il_sta_ucode_deactivate - deactivate ucode status for a station
2044 *
2045 * il->sta_lock must be held
2046 */
e7392364
SG		 2047static void
2048il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 2049{
2050 /* Ucode must be active and driver must be non active */
e7392364
SG		 2051 if ((il->stations[sta_id].
2052 used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
2053 IL_STA_UCODE_ACTIVE)
0cdc2136
SG		 2054 IL_ERR("removed non active STA %u\n", sta_id);
2055
2056 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
2057
2058 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
2059 D_ASSOC("Removed STA %u\n", sta_id);
2060}
2061
e7392364
SG		 2062static int
2063il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
2064 bool temporary)
0cdc2136
SG		 2065{
2066 struct il_rx_pkt *pkt;
2067 int ret;
2068
2069 unsigned long flags_spin;
2070 struct il_rem_sta_cmd rm_sta_cmd;
2071
2072 struct il_host_cmd cmd = {
2073 .id = C_REM_STA,
2074 .len = sizeof(struct il_rem_sta_cmd),
2075 .flags = CMD_SYNC,
2076 .data = &rm_sta_cmd,
2077 };
2078
2079 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
2080 rm_sta_cmd.num_sta = 1;
2081 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
2082
2083 cmd.flags |= CMD_WANT_SKB;
2084
2085 ret = il_send_cmd(il, &cmd);
2086
2087 if (ret)
2088 return ret;
2089
2090 pkt = (struct il_rx_pkt *)cmd.reply_page;
2091 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 2092 IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 2093 ret = -EIO;
2094 }
2095
2096 if (!ret) {
2097 switch (pkt->u.rem_sta.status) {
2098 case REM_STA_SUCCESS_MSK:
2099 if (!temporary) {
2100 spin_lock_irqsave(&il->sta_lock, flags_spin);
2101 il_sta_ucode_deactivate(il, sta_id);
2102 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2103 flags_spin);
0cdc2136
SG		 2104 }
2105 D_ASSOC("C_REM_STA PASSED\n");
2106 break;
2107 default:
2108 ret = -EIO;
2109 IL_ERR("C_REM_STA failed\n");
2110 break;
2111 }
2112 }
2113 il_free_pages(il, cmd.reply_page);
2114
2115 return ret;
2116}
2117
2118/**
2119 * il_remove_station - Remove driver's knowledge of station.
2120 */
e7392364
SG		 2121int
2122il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
0cdc2136
SG		 2123{
2124 unsigned long flags;
2125
2126 if (!il_is_ready(il)) {
e7392364
SG		 2127 D_INFO("Unable to remove station %pM, device not ready.\n",
2128 addr);
0cdc2136
SG		 2129 /*
2130 * It is typical for stations to be removed when we are
2131 * going down. Return success since device will be down
2132 * soon anyway
2133 */
2134 return 0;
2135 }
2136
e7392364 2137 D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
0cdc2136
SG		 2138
2139 if (WARN_ON(sta_id == IL_INVALID_STATION))
2140 return -EINVAL;
2141
2142 spin_lock_irqsave(&il->sta_lock, flags);
2143
2144 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
e7392364 2145 D_INFO("Removing %pM but non DRIVER active\n", addr);
0cdc2136
SG		 2146 goto out_err;
2147 }
2148
2149 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2150 D_INFO("Removing %pM but non UCODE active\n", addr);
0cdc2136
SG		 2151 goto out_err;
2152 }
2153
2154 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2155 kfree(il->stations[sta_id].lq);
2156 il->stations[sta_id].lq = NULL;
2157 }
2158
2159 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2160
2161 il->num_stations--;
2162
2163 BUG_ON(il->num_stations < 0);
2164
2165 spin_unlock_irqrestore(&il->sta_lock, flags);
2166
2167 return il_send_remove_station(il, addr, sta_id, false);
2168out_err:
2169 spin_unlock_irqrestore(&il->sta_lock, flags);
2170 return -EINVAL;
2171}
2172EXPORT_SYMBOL_GPL(il_remove_station);
2173
2174/**
2175 * il_clear_ucode_stations - clear ucode station table bits
2176 *
2177 * This function clears all the bits in the driver indicating
2178 * which stations are active in the ucode. Call when something
2179 * other than explicit station management would cause this in
2180 * the ucode, e.g. unassociated RXON.
2181 */
e7392364
SG		 2182void
2183il_clear_ucode_stations(struct il_priv *il, struct il_rxon_context *ctx)
0cdc2136
SG		 2184{
2185 int i;
2186 unsigned long flags_spin;
2187 bool cleared = false;
2188
2189 D_INFO("Clearing ucode stations in driver\n");
2190
2191 spin_lock_irqsave(&il->sta_lock, flags_spin);
2192 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136 2193 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
e7392364 2194 D_INFO("Clearing ucode active for station %d\n", i);
0cdc2136
SG		 2195 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2196 cleared = true;
2197 }
2198 }
2199 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2200
2201 if (!cleared)
e7392364 2202 D_INFO("No active stations found to be cleared\n");
0cdc2136
SG		 2203}
2204EXPORT_SYMBOL(il_clear_ucode_stations);
2205
2206/**
2207 * il_restore_stations() - Restore driver known stations to device
2208 *
2209 * All stations considered active by driver, but not present in ucode, is
2210 * restored.
2211 *
2212 * Function sleeps.
2213 */
2214void
2215il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx)
2216{
2217 struct il_addsta_cmd sta_cmd;
2218 struct il_link_quality_cmd lq;
2219 unsigned long flags_spin;
2220 int i;
2221 bool found = false;
2222 int ret;
2223 bool send_lq;
2224
2225 if (!il_is_ready(il)) {
e7392364 2226 D_INFO("Not ready yet, not restoring any stations.\n");
0cdc2136
SG		 2227 return;
2228 }
2229
2230 D_ASSOC("Restoring all known stations ... start.\n");
2231 spin_lock_irqsave(&il->sta_lock, flags_spin);
2232 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136
SG		 2233 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2234 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2235 D_ASSOC("Restoring sta %pM\n",
e7392364 2236 il->stations[i].sta.sta.addr);
0cdc2136
SG		 2237 il->stations[i].sta.mode = 0;
2238 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2239 found = true;
2240 }
2241 }
2242
2243 for (i = 0; i < il->hw_params.max_stations; i++) {
2244 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2245 memcpy(&sta_cmd, &il->stations[i].sta,
2246 sizeof(struct il_addsta_cmd));
2247 send_lq = false;
2248 if (il->stations[i].lq) {
2249 memcpy(&lq, il->stations[i].lq,
2250 sizeof(struct il_link_quality_cmd));
2251 send_lq = true;
2252 }
2253 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2254 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2255 if (ret) {
2256 spin_lock_irqsave(&il->sta_lock, flags_spin);
2257 IL_ERR("Adding station %pM failed.\n",
e7392364
SG		 2258 il->stations[i].sta.sta.addr);
2259 il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
0cdc2136 2260 il->stations[i].used &=
e7392364 2261 ~IL_STA_UCODE_INPROGRESS;
0cdc2136 2262 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2263 flags_spin);
0cdc2136
SG		 2264 }
2265 /*
2266 * Rate scaling has already been initialized, send
2267 * current LQ command
2268 */
2269 if (send_lq)
e7392364 2270 il_send_lq_cmd(il, ctx, &lq, CMD_SYNC, true);
0cdc2136
SG		 2271 spin_lock_irqsave(&il->sta_lock, flags_spin);
2272 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2273 }
2274 }
2275
2276 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2277 if (!found)
2278 D_INFO("Restoring all known stations"
e7392364 2279 " .... no stations to be restored.\n");
0cdc2136 2280 else
e7392364 2281 D_INFO("Restoring all known stations" " .... complete.\n");
0cdc2136
SG		 2282}
2283EXPORT_SYMBOL(il_restore_stations);
2284
e7392364
SG		 2285int
2286il_get_free_ucode_key_idx(struct il_priv *il)
0cdc2136
SG		 2287{
2288 int i;
2289
2290 for (i = 0; i < il->sta_key_max_num; i++)
2291 if (!test_and_set_bit(i, &il->ucode_key_table))
2292 return i;
2293
2294 return WEP_INVALID_OFFSET;
2295}
2296EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2297
e7392364
SG		 2298void
2299il_dealloc_bcast_stations(struct il_priv *il)
0cdc2136
SG		 2300{
2301 unsigned long flags;
2302 int i;
2303
2304 spin_lock_irqsave(&il->sta_lock, flags);
2305 for (i = 0; i < il->hw_params.max_stations; i++) {
2306 if (!(il->stations[i].used & IL_STA_BCAST))
2307 continue;
2308
2309 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2310 il->num_stations--;
2311 BUG_ON(il->num_stations < 0);
2312 kfree(il->stations[i].lq);
2313 il->stations[i].lq = NULL;
2314 }
2315 spin_unlock_irqrestore(&il->sta_lock, flags);
2316}
2317EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2318
2319#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2320static void
2321il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2322{
2323 int i;
2324 D_RATE("lq station id 0x%x\n", lq->sta_id);
e7392364
SG		 2325 D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
2326 lq->general_params.dual_stream_ant_msk);
0cdc2136
SG		 2327
2328 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
e7392364 2329 D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
0cdc2136
SG		 2330}
2331#else
e7392364
SG		 2332static inline void
2333il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2334{
2335}
2336#endif
2337
2338/**
2339 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2340 *
2341 * It sometimes happens when a HT rate has been in use and we
2342 * loose connectivity with AP then mac80211 will first tell us that the
2343 * current channel is not HT anymore before removing the station. In such a
2344 * scenario the RXON flags will be updated to indicate we are not
2345 * communicating HT anymore, but the LQ command may still contain HT rates.
2346 * Test for this to prevent driver from sending LQ command between the time
2347 * RXON flags are updated and when LQ command is updated.
2348 */
e7392364
SG		 2349static bool
2350il_is_lq_table_valid(struct il_priv *il, struct il_rxon_context *ctx,
2351 struct il_link_quality_cmd *lq)
0cdc2136
SG		 2352{
2353 int i;
2354
2355 if (ctx->ht.enabled)
2356 return true;
2357
c8b03958 2358 D_INFO("Channel %u is not an HT channel\n", il->active.channel);
0cdc2136 2359 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
e7392364
SG		 2360 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
2361 D_INFO("idx %d of LQ expects HT channel\n", i);
0cdc2136
SG		 2362 return false;
2363 }
2364 }
2365 return true;
2366}
2367
2368/**
2369 * il_send_lq_cmd() - Send link quality command
2370 * @init: This command is sent as part of station initialization right
2371 * after station has been added.
2372 *
2373 * The link quality command is sent as the last step of station creation.
2374 * This is the special case in which init is set and we call a callback in
2375 * this case to clear the state indicating that station creation is in
2376 * progress.
2377 */
e7392364
SG		 2378int
2379il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
2380 struct il_link_quality_cmd *lq, u8 flags, bool init)
0cdc2136
SG		 2381{
2382 int ret = 0;
2383 unsigned long flags_spin;
2384
2385 struct il_host_cmd cmd = {
2386 .id = C_TX_LINK_QUALITY_CMD,
2387 .len = sizeof(struct il_link_quality_cmd),
2388 .flags = flags,
2389 .data = lq,
2390 };
2391
2392 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2393 return -EINVAL;
2394
0cdc2136
SG		 2395 spin_lock_irqsave(&il->sta_lock, flags_spin);
2396 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2397 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2398 return -EINVAL;
2399 }
2400 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2401
2402 il_dump_lq_cmd(il, lq);
2403 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2404
2405 if (il_is_lq_table_valid(il, ctx, lq))
2406 ret = il_send_cmd(il, &cmd);
2407 else
2408 ret = -EINVAL;
2409
2410 if (cmd.flags & CMD_ASYNC)
2411 return ret;
2412
2413 if (init) {
2414 D_INFO("init LQ command complete,"
e7392364
SG		 2415 " clearing sta addition status for sta %d\n",
2416 lq->sta_id);
0cdc2136
SG		 2417 spin_lock_irqsave(&il->sta_lock, flags_spin);
2418 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2419 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2420 }
2421 return ret;
2422}
2423EXPORT_SYMBOL(il_send_lq_cmd);
2424
e7392364
SG		 2425int
2426il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2427 struct ieee80211_sta *sta)
0cdc2136
SG		 2428{
2429 struct il_priv *il = hw->priv;
2430 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2431 int ret;
2432
e7392364 2433 D_INFO("received request to remove station %pM\n", sta->addr);
0cdc2136 2434 mutex_lock(&il->mutex);
e7392364 2435 D_INFO("proceeding to remove station %pM\n", sta->addr);
0cdc2136
SG		 2436 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2437 if (ret)
e7392364 2438 IL_ERR("Error removing station %pM\n", sta->addr);
0cdc2136
SG		 2439 mutex_unlock(&il->mutex);
2440 return ret;
2441}
2442EXPORT_SYMBOL(il_mac_sta_remove);
2443
2444/************************** RX-FUNCTIONS ****************************/
2445/*
2446 * Rx theory of operation
2447 *
2448 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2449 * each of which point to Receive Buffers to be filled by the NIC. These get
2450 * used not only for Rx frames, but for any command response or notification
2451 * from the NIC. The driver and NIC manage the Rx buffers by means
2452 * of idxes into the circular buffer.
2453 *
2454 * Rx Queue Indexes
2455 * The host/firmware share two idx registers for managing the Rx buffers.
2456 *
2457 * The READ idx maps to the first position that the firmware may be writing
2458 * to -- the driver can read up to (but not including) this position and get
2459 * good data.
2460 * The READ idx is managed by the firmware once the card is enabled.
2461 *
2462 * The WRITE idx maps to the last position the driver has read from -- the
2463 * position preceding WRITE is the last slot the firmware can place a packet.
2464 *
2465 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2466 * WRITE = READ.
2467 *
2468 * During initialization, the host sets up the READ queue position to the first
2469 * IDX position, and WRITE to the last (READ - 1 wrapped)
2470 *
2471 * When the firmware places a packet in a buffer, it will advance the READ idx
2472 * and fire the RX interrupt. The driver can then query the READ idx and
2473 * process as many packets as possible, moving the WRITE idx forward as it
2474 * resets the Rx queue buffers with new memory.
2475 *
2476 * The management in the driver is as follows:
2477 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2478 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2479 * to replenish the iwl->rxq->rx_free.
2480 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2481 * iwl->rxq is replenished and the READ IDX is updated (updating the
2482 * 'processed' and 'read' driver idxes as well)
2483 * + A received packet is processed and handed to the kernel network stack,
2484 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2485 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2486 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2487 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2488 * were enough free buffers and RX_STALLED is set it is cleared.
2489 *
2490 *
2491 * Driver sequence:
2492 *
2493 * il_rx_queue_alloc() Allocates rx_free
2494 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2495 * il_rx_queue_restock
2496 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2497 * queue, updates firmware pointers, and updates
2498 * the WRITE idx. If insufficient rx_free buffers
2499 * are available, schedules il_rx_replenish
2500 *
2501 * -- enable interrupts --
2502 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2503 * READ IDX, detaching the SKB from the pool.
2504 * Moves the packet buffer from queue to rx_used.
2505 * Calls il_rx_queue_restock to refill any empty
2506 * slots.
2507 * ...
2508 *
2509 */
2510
2511/**
2512 * il_rx_queue_space - Return number of free slots available in queue.
2513 */
e7392364
SG		 2514int
2515il_rx_queue_space(const struct il_rx_queue *q)
0cdc2136
SG		 2516{
2517 int s = q->read - q->write;
2518 if (s <= 0)
2519 s += RX_QUEUE_SIZE;
2520 /* keep some buffer to not confuse full and empty queue */
2521 s -= 2;
2522 if (s < 0)
2523 s = 0;
2524 return s;
2525}
2526EXPORT_SYMBOL(il_rx_queue_space);
2527
2528/**
2529 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2530 */
2531void
e7392364 2532il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
0cdc2136
SG		 2533{
2534 unsigned long flags;
2535 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2536 u32 reg;
2537
2538 spin_lock_irqsave(&q->lock, flags);
2539
2540 if (q->need_update == 0)
2541 goto exit_unlock;
2542
2543 /* If power-saving is in use, make sure device is awake */
2544 if (test_bit(S_POWER_PMI, &il->status)) {
2545 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2546
2547 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2548 D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
2549 reg);
0cdc2136 2550 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2551 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2552 goto exit_unlock;
2553 }
2554
2555 q->write_actual = (q->write & ~0x7);
e7392364 2556 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136 2557
e7392364 2558 /* Else device is assumed to be awake */
0cdc2136
SG		 2559 } else {
2560 /* Device expects a multiple of 8 */
2561 q->write_actual = (q->write & ~0x7);
e7392364 2562 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136
SG		 2563 }
2564
2565 q->need_update = 0;
2566
e7392364 2567exit_unlock:
0cdc2136
SG		 2568 spin_unlock_irqrestore(&q->lock, flags);
2569}
2570EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2571
e7392364
SG		 2572int
2573il_rx_queue_alloc(struct il_priv *il)
0cdc2136
SG		 2574{
2575 struct il_rx_queue *rxq = &il->rxq;
2576 struct device *dev = &il->pci_dev->dev;
2577 int i;
2578
2579 spin_lock_init(&rxq->lock);
2580 INIT_LIST_HEAD(&rxq->rx_free);
2581 INIT_LIST_HEAD(&rxq->rx_used);
2582
2583 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
e7392364
SG		 2584 rxq->bd =
2585 dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2586 GFP_KERNEL);
0cdc2136
SG		 2587 if (!rxq->bd)
2588 goto err_bd;
2589
e7392364
SG		 2590 rxq->rb_stts =
2591 dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2592 &rxq->rb_stts_dma, GFP_KERNEL);
0cdc2136
SG		 2593 if (!rxq->rb_stts)
2594 goto err_rb;
2595
2596 /* Fill the rx_used queue with _all_ of the Rx buffers */
2597 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2598 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2599
2600 /* Set us so that we have processed and used all buffers, but have
2601 * not restocked the Rx queue with fresh buffers */
2602 rxq->read = rxq->write = 0;
2603 rxq->write_actual = 0;
2604 rxq->free_count = 0;
2605 rxq->need_update = 0;
2606 return 0;
2607
2608err_rb:
2609 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2610 rxq->bd_dma);
2611err_bd:
2612 return -ENOMEM;
2613}
e7392364 2614EXPORT_SYMBOL(il_rx_queue_alloc);
0cdc2136 2615
e7392364
SG		 2616void
2617il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 2618{
2619 struct il_rx_pkt *pkt = rxb_addr(rxb);
2620 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2621
2622 if (!report->state) {
e7392364 2623 D_11H("Spectrum Measure Notification: Start\n");
0cdc2136
SG		 2624 return;
2625 }
2626
2627 memcpy(&il->measure_report, report, sizeof(*report));
2628 il->measurement_status |= MEASUREMENT_READY;
2629}
2630EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2631
2632/*
2633 * returns non-zero if packet should be dropped
2634 */
e7392364
SG		 2635int
2636il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
2637 u32 decrypt_res, struct ieee80211_rx_status *stats)
0cdc2136
SG		 2638{
2639 u16 fc = le16_to_cpu(hdr->frame_control);
2640
2641 /*
2642 * All contexts have the same setting here due to it being
2643 * a module parameter, so OK to check any context.
2644 */
c8b03958 2645 if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
0cdc2136
SG		 2646 return 0;
2647
2648 if (!(fc & IEEE80211_FCTL_PROTECTED))
2649 return 0;
2650
2651 D_RX("decrypt_res:0x%x\n", decrypt_res);
2652 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2653 case RX_RES_STATUS_SEC_TYPE_TKIP:
2654 /* The uCode has got a bad phase 1 Key, pushes the packet.
2655 * Decryption will be done in SW. */
2656 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2657 RX_RES_STATUS_BAD_KEY_TTAK)
2658 break;
2659
2660 case RX_RES_STATUS_SEC_TYPE_WEP:
2661 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2662 RX_RES_STATUS_BAD_ICV_MIC) {
2663 /* bad ICV, the packet is destroyed since the
2664 * decryption is inplace, drop it */
2665 D_RX("Packet destroyed\n");
2666 return -1;
2667 }
2668 case RX_RES_STATUS_SEC_TYPE_CCMP:
2669 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2670 RX_RES_STATUS_DECRYPT_OK) {
2671 D_RX("hw decrypt successfully!!!\n");
2672 stats->flag |= RX_FLAG_DECRYPTED;
2673 }
2674 break;
2675
2676 default:
2677 break;
2678 }
2679 return 0;
2680}
2681EXPORT_SYMBOL(il_set_decrypted_flag);
2682
2683/**
2684 * il_txq_update_write_ptr - Send new write idx to hardware
2685 */
2686void
2687il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2688{
2689 u32 reg = 0;
2690 int txq_id = txq->q.id;
2691
2692 if (txq->need_update == 0)
2693 return;
2694
2695 /* if we're trying to save power */
2696 if (test_bit(S_POWER_PMI, &il->status)) {
2697 /* wake up nic if it's powered down ...
2698 * uCode will wake up, and interrupt us again, so next
2699 * time we'll skip this part. */
2700 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2701
2702 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2703 D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
2704 txq_id, reg);
0cdc2136 2705 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2706 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2707 return;
2708 }
2709
e7392364 2710 il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2711
2712 /*
2713 * else not in power-save mode,
2714 * uCode will never sleep when we're
2715 * trying to tx (during RFKILL, we're not trying to tx).
2716 */
2717 } else
e7392364 2718 _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2719 txq->need_update = 0;
2720}
2721EXPORT_SYMBOL(il_txq_update_write_ptr);
2722
2723/**
2724 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2725 */
e7392364
SG		 2726void
2727il_tx_queue_unmap(struct il_priv *il, int txq_id)
0cdc2136
SG		 2728{
2729 struct il_tx_queue *txq = &il->txq[txq_id];
2730 struct il_queue *q = &txq->q;
2731
2732 if (q->n_bd == 0)
2733 return;
2734
2735 while (q->write_ptr != q->read_ptr) {
2736 il->cfg->ops->lib->txq_free_tfd(il, txq);
2737 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2738 }
2739}
2740EXPORT_SYMBOL(il_tx_queue_unmap);
2741
2742/**
2743 * il_tx_queue_free - Deallocate DMA queue.
2744 * @txq: Transmit queue to deallocate.
2745 *
2746 * Empty queue by removing and destroying all BD's.
2747 * Free all buffers.
2748 * 0-fill, but do not free "txq" descriptor structure.
2749 */
e7392364
SG		 2750void
2751il_tx_queue_free(struct il_priv *il, int txq_id)
0cdc2136
SG		 2752{
2753 struct il_tx_queue *txq = &il->txq[txq_id];
2754 struct device *dev = &il->pci_dev->dev;
2755 int i;
2756
2757 il_tx_queue_unmap(il, txq_id);
2758
2759 /* De-alloc array of command/tx buffers */
2760 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2761 kfree(txq->cmd[i]);
2762
2763 /* De-alloc circular buffer of TFDs */
2764 if (txq->q.n_bd)
e7392364
SG		 2765 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2766 txq->tfds, txq->q.dma_addr);
0cdc2136
SG		 2767
2768 /* De-alloc array of per-TFD driver data */
2769 kfree(txq->txb);
2770 txq->txb = NULL;
2771
2772 /* deallocate arrays */
2773 kfree(txq->cmd);
2774 kfree(txq->meta);
2775 txq->cmd = NULL;
2776 txq->meta = NULL;
2777
2778 /* 0-fill queue descriptor structure */
2779 memset(txq, 0, sizeof(*txq));
2780}
2781EXPORT_SYMBOL(il_tx_queue_free);
2782
2783/**
2784 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2785 */
e7392364
SG		 2786void
2787il_cmd_queue_unmap(struct il_priv *il)
0cdc2136
SG		 2788{
2789 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2790 struct il_queue *q = &txq->q;
2791 int i;
2792
2793 if (q->n_bd == 0)
2794 return;
2795
2796 while (q->read_ptr != q->write_ptr) {
2797 i = il_get_cmd_idx(q, q->read_ptr, 0);
2798
2799 if (txq->meta[i].flags & CMD_MAPPED) {
2800 pci_unmap_single(il->pci_dev,
2801 dma_unmap_addr(&txq->meta[i], mapping),
2802 dma_unmap_len(&txq->meta[i], len),
2803 PCI_DMA_BIDIRECTIONAL);
2804 txq->meta[i].flags = 0;
2805 }
2806
2807 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2808 }
2809
2810 i = q->n_win;
2811 if (txq->meta[i].flags & CMD_MAPPED) {
2812 pci_unmap_single(il->pci_dev,
2813 dma_unmap_addr(&txq->meta[i], mapping),
2814 dma_unmap_len(&txq->meta[i], len),
2815 PCI_DMA_BIDIRECTIONAL);
2816 txq->meta[i].flags = 0;
2817 }
2818}
2819EXPORT_SYMBOL(il_cmd_queue_unmap);
2820
2821/**
2822 * il_cmd_queue_free - Deallocate DMA queue.
2823 * @txq: Transmit queue to deallocate.
2824 *
2825 * Empty queue by removing and destroying all BD's.
2826 * Free all buffers.
2827 * 0-fill, but do not free "txq" descriptor structure.
2828 */
e7392364
SG		 2829void
2830il_cmd_queue_free(struct il_priv *il)
0cdc2136
SG		 2831{
2832 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2833 struct device *dev = &il->pci_dev->dev;
2834 int i;
2835
2836 il_cmd_queue_unmap(il);
2837
2838 /* De-alloc array of command/tx buffers */
2839 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2840 kfree(txq->cmd[i]);
2841
2842 /* De-alloc circular buffer of TFDs */
2843 if (txq->q.n_bd)
2844 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2845 txq->tfds, txq->q.dma_addr);
2846
2847 /* deallocate arrays */
2848 kfree(txq->cmd);
2849 kfree(txq->meta);
2850 txq->cmd = NULL;
2851 txq->meta = NULL;
2852
2853 /* 0-fill queue descriptor structure */
2854 memset(txq, 0, sizeof(*txq));
2855}
2856EXPORT_SYMBOL(il_cmd_queue_free);
2857
2858/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2859 * DMA services
2860 *
2861 * Theory of operation
2862 *
2863 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2864 * of buffer descriptors, each of which points to one or more data buffers for
2865 * the device to read from or fill. Driver and device exchange status of each
2866 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2867 * entries in each circular buffer, to protect against confusing empty and full
2868 * queue states.
2869 *
2870 * The device reads or writes the data in the queues via the device's several
2871 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2872 *
2873 * For Tx queue, there are low mark and high mark limits. If, after queuing
2874 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2875 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2876 * Tx queue resumed.
2877 *
2878 * See more detailed info in 4965.h.
2879 ***************************************************/
2880
e7392364
SG		 2881int
2882il_queue_space(const struct il_queue *q)
0cdc2136
SG		 2883{
2884 int s = q->read_ptr - q->write_ptr;
2885
2886 if (q->read_ptr > q->write_ptr)
2887 s -= q->n_bd;
2888
2889 if (s <= 0)
2890 s += q->n_win;
2891 /* keep some reserve to not confuse empty and full situations */
2892 s -= 2;
2893 if (s < 0)
2894 s = 0;
2895 return s;
2896}
2897EXPORT_SYMBOL(il_queue_space);
2898
2899
2900/**
2901 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2902 */
e7392364
SG		 2903static int
2904il_queue_init(struct il_priv *il, struct il_queue *q, int count, int slots_num,
2905 u32 id)
0cdc2136
SG		 2906{
2907 q->n_bd = count;
2908 q->n_win = slots_num;
2909 q->id = id;
2910
2911 /* count must be power-of-two size, otherwise il_queue_inc_wrap
2912 * and il_queue_dec_wrap are broken. */
2913 BUG_ON(!is_power_of_2(count));
2914
2915 /* slots_num must be power-of-two size, otherwise
2916 * il_get_cmd_idx is broken. */
2917 BUG_ON(!is_power_of_2(slots_num));
2918
2919 q->low_mark = q->n_win / 4;
2920 if (q->low_mark < 4)
2921 q->low_mark = 4;
2922
2923 q->high_mark = q->n_win / 8;
2924 if (q->high_mark < 2)
2925 q->high_mark = 2;
2926
2927 q->write_ptr = q->read_ptr = 0;
2928
2929 return 0;
2930}
2931
2932/**
2933 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2934 */
e7392364
SG		 2935static int
2936il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
0cdc2136
SG		 2937{
2938 struct device *dev = &il->pci_dev->dev;
2939 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2940
2941 /* Driver ilate data, only for Tx (not command) queues,
2942 * not shared with device. */
2943 if (id != il->cmd_queue) {
2b50b8f5
TM		 2944 txq->txb = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->txb[0]),
2945 GFP_KERNEL);
0cdc2136
SG		 2946 if (!txq->txb) {
2947 IL_ERR("kmalloc for auxiliary BD "
e7392364 2948 "structures failed\n");
0cdc2136
SG		 2949 goto error;
2950 }
2951 } else {
2952 txq->txb = NULL;
2953 }
2954
2955 /* Circular buffer of transmit frame descriptors (TFDs),
2956 * shared with device */
e7392364
SG		 2957 txq->tfds =
2958 dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
0cdc2136
SG		 2959 if (!txq->tfds) {
2960 IL_ERR("pci_alloc_consistent(%zd) failed\n", tfd_sz);
2961 goto error;
2962 }
2963 txq->q.id = id;
2964
2965 return 0;
2966
e7392364 2967error:
0cdc2136
SG		 2968 kfree(txq->txb);
2969 txq->txb = NULL;
2970
2971 return -ENOMEM;
2972}
2973
2974/**
2975 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
2976 */
e7392364
SG		 2977int
2978il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
2979 u32 txq_id)
0cdc2136
SG		 2980{
2981 int i, len;
2982 int ret;
2983 int actual_slots = slots_num;
2984
2985 /*
2986 * Alloc buffer array for commands (Tx or other types of commands).
2987 * For the command queue (#4/#9), allocate command space + one big
2988 * command for scan, since scan command is very huge; the system will
2989 * not have two scans at the same time, so only one is needed.
2990 * For normal Tx queues (all other queues), no super-size command
2991 * space is needed.
2992 */
2993 if (txq_id == il->cmd_queue)
2994 actual_slots++;
2995
e7392364
SG		 2996 txq->meta =
2997 kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
2998 txq->cmd =
2999 kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
0cdc2136
SG		 3000
3001 if (!txq->meta || !txq->cmd)
3002 goto out_free_arrays;
3003
3004 len = sizeof(struct il_device_cmd);
3005 for (i = 0; i < actual_slots; i++) {
3006 /* only happens for cmd queue */
3007 if (i == slots_num)
3008 len = IL_MAX_CMD_SIZE;
3009
3010 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
3011 if (!txq->cmd[i])
3012 goto err;
3013 }
3014
3015 /* Alloc driver data array and TFD circular buffer */
3016 ret = il_tx_queue_alloc(il, txq, txq_id);
3017 if (ret)
3018 goto err;
3019
3020 txq->need_update = 0;
3021
3022 /*
3023 * For the default queues 0-3, set up the swq_id
3024 * already -- all others need to get one later
3025 * (if they need one at all).
3026 */
3027 if (txq_id < 4)
3028 il_set_swq_id(txq, txq_id, txq_id);
3029
3030 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
3031 * il_queue_inc_wrap and il_queue_dec_wrap are broken. */
3032 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
3033
3034 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3035 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG		 3036
3037 /* Tell device where to find queue */
3038 il->cfg->ops->lib->txq_init(il, txq);
3039
3040 return 0;
3041err:
3042 for (i = 0; i < actual_slots; i++)
3043 kfree(txq->cmd[i]);
3044out_free_arrays:
3045 kfree(txq->meta);
3046 kfree(txq->cmd);
3047
3048 return -ENOMEM;
3049}
3050EXPORT_SYMBOL(il_tx_queue_init);
3051
e7392364
SG		 3052void
3053il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
3054 u32 txq_id)
0cdc2136
SG		 3055{
3056 int actual_slots = slots_num;
3057
3058 if (txq_id == il->cmd_queue)
3059 actual_slots++;
3060
3061 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
3062
3063 txq->need_update = 0;
3064
3065 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3066 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG		 3067
3068 /* Tell device where to find queue */
3069 il->cfg->ops->lib->txq_init(il, txq);
3070}
3071EXPORT_SYMBOL(il_tx_queue_reset);
3072
3073/*************** HOST COMMAND QUEUE FUNCTIONS *****/
3074
3075/**
3076 * il_enqueue_hcmd - enqueue a uCode command
3077 * @il: device ilate data point
3078 * @cmd: a point to the ucode command structure
3079 *
3080 * The function returns < 0 values to indicate the operation is
3081 * failed. On success, it turns the idx (> 0) of command in the
3082 * command queue.
3083 */
e7392364
SG		 3084int
3085il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 3086{
3087 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3088 struct il_queue *q = &txq->q;
3089 struct il_device_cmd *out_cmd;
3090 struct il_cmd_meta *out_meta;
3091 dma_addr_t phys_addr;
3092 unsigned long flags;
3093 int len;
3094 u32 idx;
3095 u16 fix_size;
3096
3097 cmd->len = il->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
e7392364 3098 fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
0cdc2136
SG		 3099
3100 /* If any of the command structures end up being larger than
3101 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
3102 * we will need to increase the size of the TFD entries
3103 * Also, check to see if command buffer should not exceed the size
3104 * of device_cmd and max_cmd_size. */
3105 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
3106 !(cmd->flags & CMD_SIZE_HUGE));
3107 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
3108
3109 if (il_is_rfkill(il) || il_is_ctkill(il)) {
3110 IL_WARN("Not sending command - %s KILL\n",
e7392364 3111 il_is_rfkill(il) ? "RF" : "CT");
0cdc2136
SG		 3112 return -EIO;
3113 }
3114
3115 spin_lock_irqsave(&il->hcmd_lock, flags);
3116
3117 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3118 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3119
3120 IL_ERR("Restarting adapter due to command queue full\n");
3121 queue_work(il->workqueue, &il->restart);
3122 return -ENOSPC;
3123 }
3124
3125 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3126 out_cmd = txq->cmd[idx];
3127 out_meta = &txq->meta[idx];
3128
3129 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3130 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3131 return -ENOSPC;
3132 }
3133
3134 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3135 out_meta->flags = cmd->flags | CMD_MAPPED;
3136 if (cmd->flags & CMD_WANT_SKB)
3137 out_meta->source = cmd;
3138 if (cmd->flags & CMD_ASYNC)
3139 out_meta->callback = cmd->callback;
3140
3141 out_cmd->hdr.cmd = cmd->id;
3142 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3143
3144 /* At this point, the out_cmd now has all of the incoming cmd
3145 * information */
3146
3147 out_cmd->hdr.flags = 0;
e7392364
SG		 3148 out_cmd->hdr.sequence =
3149 cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
0cdc2136
SG		 3150 if (cmd->flags & CMD_SIZE_HUGE)
3151 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3152 len = sizeof(struct il_device_cmd);
3153 if (idx == TFD_CMD_SLOTS)
3154 len = IL_MAX_CMD_SIZE;
3155
3156#ifdef CONFIG_IWLEGACY_DEBUG
3157 switch (out_cmd->hdr.cmd) {
3158 case C_TX_LINK_QUALITY_CMD:
3159 case C_SENSITIVITY:
e7392364
SG		 3160 D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
3161 "%d bytes at %d[%d]:%d\n",
3162 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3163 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3164 q->write_ptr, idx, il->cmd_queue);
0cdc2136
SG		 3165 break;
3166 default:
3167 D_HC("Sending command %s (#%x), seq: 0x%04X, "
e7392364
SG		 3168 "%d bytes at %d[%d]:%d\n",
3169 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3170 le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
3171 idx, il->cmd_queue);
0cdc2136
SG		 3172 }
3173#endif
3174 txq->need_update = 1;
3175
3176 if (il->cfg->ops->lib->txq_update_byte_cnt_tbl)
3177 /* Set up entry in queue's byte count circular buffer */
3178 il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0);
3179
e7392364
SG		 3180 phys_addr =
3181 pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
3182 PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3183 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3184 dma_unmap_len_set(out_meta, len, fix_size);
3185
e7392364
SG		 3186 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size,
3187 1, U32_PAD(cmd->len));
0cdc2136
SG		 3188
3189 /* Increment and update queue's write idx */
3190 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3191 il_txq_update_write_ptr(il, txq);
3192
3193 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3194 return idx;
3195}
3196
3197/**
3198 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3199 *
3200 * When FW advances 'R' idx, all entries between old and new 'R' idx
3201 * need to be reclaimed. As result, some free space forms. If there is
3202 * enough free space (> low mark), wake the stack that feeds us.
3203 */
e7392364
SG		 3204static void
3205il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
0cdc2136
SG		 3206{
3207 struct il_tx_queue *txq = &il->txq[txq_id];
3208 struct il_queue *q = &txq->q;
3209 int nfreed = 0;
3210
3211 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3212 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 3213 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
3214 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3215 return;
3216 }
3217
3218 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3219 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3220
3221 if (nfreed++ > 0) {
3222 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
e7392364 3223 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3224 queue_work(il->workqueue, &il->restart);
3225 }
3226
3227 }
3228}
3229
3230/**
3231 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3232 * @rxb: Rx buffer to reclaim
3233 *
3234 * If an Rx buffer has an async callback associated with it the callback
3235 * will be executed. The attached skb (if present) will only be freed
3236 * if the callback returns 1
3237 */
3238void
3239il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3240{
3241 struct il_rx_pkt *pkt = rxb_addr(rxb);
3242 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3243 int txq_id = SEQ_TO_QUEUE(sequence);
3244 int idx = SEQ_TO_IDX(sequence);
3245 int cmd_idx;
3246 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3247 struct il_device_cmd *cmd;
3248 struct il_cmd_meta *meta;
3249 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3250 unsigned long flags;
3251
3252 /* If a Tx command is being handled and it isn't in the actual
3253 * command queue then there a command routing bug has been introduced
3254 * in the queue management code. */
e7392364
SG		 3255 if (WARN
3256 (txq_id != il->cmd_queue,
3257 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3258 txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
3259 il->txq[il->cmd_queue].q.write_ptr)) {
0cdc2136
SG		 3260 il_print_hex_error(il, pkt, 32);
3261 return;
3262 }
3263
3264 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3265 cmd = txq->cmd[cmd_idx];
3266 meta = &txq->meta[cmd_idx];
3267
3268 txq->time_stamp = jiffies;
3269
e7392364
SG		 3270 pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
3271 dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3272
3273 /* Input error checking is done when commands are added to queue. */
3274 if (meta->flags & CMD_WANT_SKB) {
3275 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3276 rxb->page = NULL;
3277 } else if (meta->callback)
3278 meta->callback(il, cmd, pkt);
3279
3280 spin_lock_irqsave(&il->hcmd_lock, flags);
3281
3282 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3283
3284 if (!(meta->flags & CMD_ASYNC)) {
3285 clear_bit(S_HCMD_ACTIVE, &il->status);
3286 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
e7392364 3287 il_get_cmd_string(cmd->hdr.cmd));
0cdc2136
SG		 3288 wake_up(&il->wait_command_queue);
3289 }
3290
3291 /* Mark as unmapped */
3292 meta->flags = 0;
3293
3294 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3295}
3296EXPORT_SYMBOL(il_tx_cmd_complete);
be663ab6
WYG		 3297
3298MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3299MODULE_VERSION(IWLWIFI_VERSION);
3300MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3301MODULE_LICENSE("GPL");
3302
3303/*
3304 * set bt_coex_active to true, uCode will do kill/defer
3305 * every time the priority line is asserted (BT is sending signals on the
3306 * priority line in the PCIx).
3307 * set bt_coex_active to false, uCode will ignore the BT activity and
3308 * perform the normal operation
3309 *
3310 * User might experience transmit issue on some platform due to WiFi/BT
3311 * co-exist problem. The possible behaviors are:
3312 * Able to scan and finding all the available AP
3313 * Not able to associate with any AP
3314 * On those platforms, WiFi communication can be restored by set
3315 * "bt_coex_active" module parameter to "false"
3316 *
3317 * default: bt_coex_active = true (BT_COEX_ENABLE)
3318 */
ef33417d 3319static bool bt_coex_active = true;
be663ab6
WYG		 3320module_param(bt_coex_active, bool, S_IRUGO);
3321MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3322
d2ddf621
SG		 3323u32 il_debug_level;
3324EXPORT_SYMBOL(il_debug_level);
be663ab6 3325
d2ddf621 3326const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
e7392364 3327EXPORT_SYMBOL(il_bcast_addr);
be663ab6 3328
46bc8d4b 3329/* This function both allocates and initializes hw and il. */
e7392364
SG		 3330struct ieee80211_hw *
3331il_alloc_all(struct il_cfg *cfg)
be663ab6 3332{
46bc8d4b 3333 struct il_priv *il;
be663ab6 3334 /* mac80211 allocates memory for this device instance, including
46bc8d4b 3335 * space for this driver's ilate structure */
be663ab6
WYG		 3336 struct ieee80211_hw *hw;
3337
e2ebc833 3338 hw = ieee80211_alloc_hw(sizeof(struct il_priv),
be663ab6
WYG		 3339 cfg->ops->ieee80211_ops);
3340 if (hw == NULL) {
e7392364 3341 pr_err("%s: Can not allocate network device\n", cfg->name);
be663ab6
WYG		 3342 goto out;
3343 }
3344
46bc8d4b
SG		 3345 il = hw->priv;
3346 il->hw = hw;
be663ab6
WYG		 3347
3348out:
3349 return hw;
3350}
e2ebc833 3351EXPORT_SYMBOL(il_alloc_all);
be663ab6 3352
e7392364
SG		 3353#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3354#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
3355static void
3356il_init_ht_hw_capab(const struct il_priv *il,
3357 struct ieee80211_sta_ht_cap *ht_info,
3358 enum ieee80211_band band)
be663ab6
WYG		 3359{
3360 u16 max_bit_rate = 0;
46bc8d4b
SG		 3361 u8 rx_chains_num = il->hw_params.rx_chains_num;
3362 u8 tx_chains_num = il->hw_params.tx_chains_num;
be663ab6
WYG		 3363
3364 ht_info->cap = 0;
3365 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3366
3367 ht_info->ht_supported = true;
3368
3369 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3370 max_bit_rate = MAX_BIT_RATE_20_MHZ;
46bc8d4b 3371 if (il->hw_params.ht40_channel & BIT(band)) {
be663ab6
WYG		 3372 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3373 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3374 ht_info->mcs.rx_mask[4] = 0x01;
3375 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3376 }
3377
46bc8d4b 3378 if (il->cfg->mod_params->amsdu_size_8K)
be663ab6
WYG		 3379 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3380
3381 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3382 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3383
3384 ht_info->mcs.rx_mask[0] = 0xFF;
3385 if (rx_chains_num >= 2)
3386 ht_info->mcs.rx_mask[1] = 0xFF;
3387 if (rx_chains_num >= 3)
3388 ht_info->mcs.rx_mask[2] = 0xFF;
3389
3390 /* Highest supported Rx data rate */
3391 max_bit_rate *= rx_chains_num;
3392 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3393 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3394
3395 /* Tx MCS capabilities */
3396 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3397 if (tx_chains_num != rx_chains_num) {
3398 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
e7392364
SG		 3399 ht_info->mcs.tx_params |=
3400 ((tx_chains_num -
3401 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
be663ab6
WYG		 3402 }
3403}
3404
3405/**
e2ebc833 3406 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
be663ab6 3407 */
e7392364
SG		 3408int
3409il_init_geos(struct il_priv *il)
be663ab6 3410{
e2ebc833 3411 struct il_channel_info *ch;
be663ab6
WYG		 3412 struct ieee80211_supported_band *sband;
3413 struct ieee80211_channel *channels;
3414 struct ieee80211_channel *geo_ch;
3415 struct ieee80211_rate *rates;
3416 int i = 0;
332704a5 3417 s8 max_tx_power = 0;
be663ab6 3418
46bc8d4b
SG		 3419 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3420 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
58de00a4 3421 D_INFO("Geography modes already initialized.\n");
a6766ccd 3422 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3423 return 0;
3424 }
3425
e7392364
SG		 3426 channels =
3427 kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
3428 GFP_KERNEL);
be663ab6
WYG		 3429 if (!channels)
3430 return -ENOMEM;
3431
e7392364
SG		 3432 rates =
3433 kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
3434 GFP_KERNEL);
be663ab6
WYG		 3435 if (!rates) {
3436 kfree(channels);
3437 return -ENOMEM;
3438 }
3439
3440 /* 5.2GHz channels start after the 2.4GHz channels */
46bc8d4b 3441 sband = &il->bands[IEEE80211_BAND_5GHZ];
d2ddf621 3442 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
be663ab6 3443 /* just OFDM */
e2ebc833 3444 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
2eb05816 3445 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
be663ab6 3446
46bc8d4b 3447 if (il->cfg->sku & IL_SKU_N)
e7392364 3448 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
be663ab6 3449
46bc8d4b 3450 sband = &il->bands[IEEE80211_BAND_2GHZ];
be663ab6
WYG		 3451 sband->channels = channels;
3452 /* OFDM & CCK */
3453 sband->bitrates = rates;
2eb05816 3454 sband->n_bitrates = RATE_COUNT_LEGACY;
be663ab6 3455
46bc8d4b 3456 if (il->cfg->sku & IL_SKU_N)
e7392364 3457 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
be663ab6 3458
46bc8d4b
SG		 3459 il->ieee_channels = channels;
3460 il->ieee_rates = rates;
be663ab6 3461
e7392364 3462 for (i = 0; i < il->channel_count; i++) {
46bc8d4b 3463 ch = &il->channel_info[i];
be663ab6 3464
e2ebc833 3465 if (!il_is_channel_valid(ch))
be663ab6
WYG		 3466 continue;
3467
46bc8d4b 3468 sband = &il->bands[ch->band];
be663ab6
WYG		 3469
3470 geo_ch = &sband->channels[sband->n_channels++];
3471
3472 geo_ch->center_freq =
e7392364 3473 ieee80211_channel_to_frequency(ch->channel, ch->band);
be663ab6
WYG		 3474 geo_ch->max_power = ch->max_power_avg;
3475 geo_ch->max_antenna_gain = 0xff;
3476 geo_ch->hw_value = ch->channel;
3477
e2ebc833 3478 if (il_is_channel_valid(ch)) {
be663ab6
WYG		 3479 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3480 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
3481
3482 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3483 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3484
3485 if (ch->flags & EEPROM_CHANNEL_RADAR)
3486 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3487
3488 geo_ch->flags |= ch->ht40_extension_channel;
3489
332704a5
SG		 3490 if (ch->max_power_avg > max_tx_power)
3491 max_tx_power = ch->max_power_avg;
be663ab6
WYG		 3492 } else {
3493 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3494 }
3495
e7392364
SG		 3496 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
3497 geo_ch->center_freq,
3498 il_is_channel_a_band(ch) ? "5.2" : "2.4",
3499 geo_ch->
3500 flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
3501 geo_ch->flags);
be663ab6
WYG		 3502 }
3503
46bc8d4b
SG		 3504 il->tx_power_device_lmt = max_tx_power;
3505 il->tx_power_user_lmt = max_tx_power;
3506 il->tx_power_next = max_tx_power;
332704a5 3507
232913b5
SG		 3508 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3509 (il->cfg->sku & IL_SKU_A)) {
9406f797 3510 IL_INFO("Incorrectly detected BG card as ABG. "
be663ab6 3511 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
e7392364 3512 il->pci_dev->device, il->pci_dev->subsystem_device);
46bc8d4b 3513 il->cfg->sku &= ~IL_SKU_A;
be663ab6
WYG		 3514 }
3515
9406f797 3516 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
e7392364
SG		 3517 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3518 il->bands[IEEE80211_BAND_5GHZ].n_channels);
be663ab6 3519
a6766ccd 3520 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3521
3522 return 0;
3523}
e2ebc833 3524EXPORT_SYMBOL(il_init_geos);
be663ab6
WYG		 3525
3526/*
e2ebc833 3527 * il_free_geos - undo allocations in il_init_geos
be663ab6 3528 */
e7392364
SG		 3529void
3530il_free_geos(struct il_priv *il)
be663ab6 3531{
46bc8d4b
SG		 3532 kfree(il->ieee_channels);
3533 kfree(il->ieee_rates);
a6766ccd 3534 clear_bit(S_GEO_CONFIGURED, &il->status);
be663ab6 3535}
e2ebc833 3536EXPORT_SYMBOL(il_free_geos);
be663ab6 3537
e7392364
SG		 3538static bool
3539il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
3540 u16 channel, u8 extension_chan_offset)
be663ab6 3541{
e2ebc833 3542 const struct il_channel_info *ch_info;
be663ab6 3543
46bc8d4b 3544 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3545 if (!il_is_channel_valid(ch_info))
be663ab6
WYG		 3546 return false;
3547
3548 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
e7392364
SG		 3549 return !(ch_info->
3550 ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
be663ab6 3551 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
e7392364
SG		 3552 return !(ch_info->
3553 ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
be663ab6
WYG		 3554
3555 return false;
3556}
3557
e7392364 3558bool
1722f8e1
SG		 3559il_is_ht40_tx_allowed(struct il_priv *il, struct il_rxon_context *ctx,
3560 struct ieee80211_sta_ht_cap *ht_cap)
be663ab6
WYG		 3561{
3562 if (!ctx->ht.enabled || !ctx->ht.is_40mhz)
3563 return false;
3564
3565 /*
3566 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3567 * the bit will not set if it is pure 40MHz case
3568 */
3569 if (ht_cap && !ht_cap->ht_supported)
3570 return false;
3571
d3175167 3572#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b 3573 if (il->disable_ht40)
be663ab6
WYG		 3574 return false;
3575#endif
3576
46bc8d4b 3577 return il_is_channel_extension(il, il->band,
c8b03958 3578 le16_to_cpu(il->staging.channel),
e7392364 3579 ctx->ht.extension_chan_offset);
be663ab6 3580}
e2ebc833 3581EXPORT_SYMBOL(il_is_ht40_tx_allowed);
be663ab6 3582
e7392364
SG		 3583static u16
3584il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
be663ab6
WYG		 3585{
3586 u16 new_val;
3587 u16 beacon_factor;
3588
3589 /*
3590 * If mac80211 hasn't given us a beacon interval, program
3591 * the default into the device.
3592 */
3593 if (!beacon_val)
3594 return DEFAULT_BEACON_INTERVAL;
3595
3596 /*
3597 * If the beacon interval we obtained from the peer
3598 * is too large, we'll have to wake up more often
3599 * (and in IBSS case, we'll beacon too much)
3600 *
3601 * For example, if max_beacon_val is 4096, and the
3602 * requested beacon interval is 7000, we'll have to
3603 * use 3500 to be able to wake up on the beacons.
3604 *
3605 * This could badly influence beacon detection stats.
3606 */
3607
3608 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3609 new_val = beacon_val / beacon_factor;
3610
3611 if (!new_val)
3612 new_val = max_beacon_val;
3613
3614 return new_val;
3615}
3616
3617int
46bc8d4b 3618il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG		 3619{
3620 u64 tsf;
3621 s32 interval_tm, rem;
3622 struct ieee80211_conf *conf = NULL;
3623 u16 beacon_int;
3624 struct ieee80211_vif *vif = ctx->vif;
3625
6278ddab 3626 conf = &il->hw->conf;
be663ab6 3627
46bc8d4b 3628 lockdep_assert_held(&il->mutex);
be663ab6 3629
c8b03958 3630 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
be663ab6 3631
c8b03958
SG		 3632 il->timing.timestamp = cpu_to_le64(il->timestamp);
3633 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
be663ab6
WYG		 3634
3635 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3636
3637 /*
6ce1dc45 3638 * TODO: For IBSS we need to get atim_win from mac80211,
e7392364 3639 * for now just always use 0
be663ab6 3640 */
c8b03958 3641 il->timing.atim_win = 0;
be663ab6 3642
e7392364
SG		 3643 beacon_int =
3644 il_adjust_beacon_interval(beacon_int,
3645 il->hw_params.max_beacon_itrvl *
3646 TIME_UNIT);
c8b03958 3647 il->timing.beacon_interval = cpu_to_le16(beacon_int);
be663ab6 3648
e7392364 3649 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
be663ab6
WYG		 3650 interval_tm = beacon_int * TIME_UNIT;
3651 rem = do_div(tsf, interval_tm);
c8b03958 3652 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
be663ab6 3653
c8b03958 3654 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
be663ab6 3655
e7392364 3656 D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
c8b03958
SG		 3657 le16_to_cpu(il->timing.beacon_interval),
3658 le32_to_cpu(il->timing.beacon_init_val),
3659 le16_to_cpu(il->timing.atim_win));
be663ab6 3660
63d0f0c5 3661 return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
c8b03958 3662 &il->timing);
be663ab6 3663}
e2ebc833 3664EXPORT_SYMBOL(il_send_rxon_timing);
be663ab6
WYG		 3665
3666void
e7392364
SG		 3667il_set_rxon_hwcrypto(struct il_priv *il, struct il_rxon_context *ctx,
3668 int hw_decrypt)
be663ab6 3669{
c8b03958 3670 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3671
3672 if (hw_decrypt)
3673 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3674 else
3675 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3676
3677}
e2ebc833 3678EXPORT_SYMBOL(il_set_rxon_hwcrypto);
be663ab6
WYG		 3679
3680/* validate RXON structure is valid */
3681int
46bc8d4b 3682il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 3683{
c8b03958 3684 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3685 bool error = false;
3686
3687 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3688 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
9406f797 3689 IL_WARN("check 2.4G: wrong narrow\n");
be663ab6
WYG		 3690 error = true;
3691 }
3692 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
9406f797 3693 IL_WARN("check 2.4G: wrong radar\n");
be663ab6
WYG		 3694 error = true;
3695 }
3696 } else {
3697 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3698 IL_WARN("check 5.2G: not short slot!\n");
be663ab6
WYG		 3699 error = true;
3700 }
3701 if (rxon->flags & RXON_FLG_CCK_MSK) {
9406f797 3702 IL_WARN("check 5.2G: CCK!\n");
be663ab6
WYG		 3703 error = true;
3704 }
3705 }
3706 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
9406f797 3707 IL_WARN("mac/bssid mcast!\n");
be663ab6
WYG		 3708 error = true;
3709 }
3710
3711 /* make sure basic rates 6Mbps and 1Mbps are supported */
2eb05816
SG		 3712 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3713 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
9406f797 3714 IL_WARN("neither 1 nor 6 are basic\n");
be663ab6
WYG		 3715 error = true;
3716 }
3717
3718 if (le16_to_cpu(rxon->assoc_id) > 2007) {
9406f797 3719 IL_WARN("aid > 2007\n");
be663ab6
WYG		 3720 error = true;
3721 }
3722
e7392364
SG		 3723 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
3724 (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3725 IL_WARN("CCK and short slot\n");
be663ab6
WYG		 3726 error = true;
3727 }
3728
e7392364
SG		 3729 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
3730 (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
9406f797 3731 IL_WARN("CCK and auto detect");
be663ab6
WYG		 3732 error = true;
3733 }
3734
e7392364
SG		 3735 if ((rxon->
3736 flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
3737 RXON_FLG_TGG_PROTECT_MSK) {
9406f797 3738 IL_WARN("TGg but no auto-detect\n");
be663ab6
WYG		 3739 error = true;
3740 }
3741
3742 if (error)
e7392364 3743 IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
be663ab6
WYG		 3744
3745 if (error) {
9406f797 3746 IL_ERR("Invalid RXON\n");
be663ab6
WYG		 3747 return -EINVAL;
3748 }
3749 return 0;
3750}
e2ebc833 3751EXPORT_SYMBOL(il_check_rxon_cmd);
be663ab6
WYG		 3752
3753/**
e2ebc833 3754 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
46bc8d4b 3755 * @il: staging_rxon is compared to active_rxon
be663ab6
WYG		 3756 *
3757 * If the RXON structure is changing enough to require a new tune,
3758 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3759 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3760 */
e7392364
SG		 3761int
3762il_full_rxon_required(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 3763{
c8b03958
SG		 3764 const struct il_rxon_cmd *staging = &il->staging;
3765 const struct il_rxon_cmd *active = &il->active;
be663ab6
WYG		 3766
3767#define CHK(cond) \
3768 if ((cond)) { \
58de00a4 3769 D_INFO("need full RXON - " #cond "\n"); \
be663ab6
WYG		 3770 return 1; \
3771 }
3772
3773#define CHK_NEQ(c1, c2) \
3774 if ((c1) != (c2)) { \
58de00a4 3775 D_INFO("need full RXON - " \
be663ab6
WYG		 3776 #c1 " != " #c2 " - %d != %d\n", \
3777 (c1), (c2)); \
3778 return 1; \
3779 }
3780
3781 /* These items are only settable from the full RXON command */
c8b03958 3782 CHK(!il_is_associated(il));
be663ab6
WYG		 3783 CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
3784 CHK(compare_ether_addr(staging->node_addr, active->node_addr));
e7392364
SG		 3785 CHK(compare_ether_addr
3786 (staging->wlap_bssid_addr, active->wlap_bssid_addr));
be663ab6
WYG		 3787 CHK_NEQ(staging->dev_type, active->dev_type);
3788 CHK_NEQ(staging->channel, active->channel);
3789 CHK_NEQ(staging->air_propagation, active->air_propagation);
3790 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3791 active->ofdm_ht_single_stream_basic_rates);
3792 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3793 active->ofdm_ht_dual_stream_basic_rates);
3794 CHK_NEQ(staging->assoc_id, active->assoc_id);
3795
3796 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3797 * be updated with the RXON_ASSOC command -- however only some
3798 * flag transitions are allowed using RXON_ASSOC */
3799
3800 /* Check if we are not switching bands */
3801 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3802 active->flags & RXON_FLG_BAND_24G_MSK);
3803
3804 /* Check if we are switching association toggle */
3805 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3806 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3807
3808#undef CHK
3809#undef CHK_NEQ
3810
3811 return 0;
3812}
e2ebc833 3813EXPORT_SYMBOL(il_full_rxon_required);
be663ab6 3814
e7392364 3815u8
1722f8e1 3816il_get_lowest_plcp(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG		 3817{
3818 /*
3819 * Assign the lowest rate -- should really get this from
3820 * the beacon skb from mac80211.
3821 */
c8b03958 3822 if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
2eb05816 3823 return RATE_1M_PLCP;
be663ab6 3824 else
2eb05816 3825 return RATE_6M_PLCP;
be663ab6 3826}
e2ebc833 3827EXPORT_SYMBOL(il_get_lowest_plcp);
be663ab6 3828
e7392364
SG		 3829static void
3830_il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf,
3831 struct il_rxon_context *ctx)
be663ab6 3832{
c8b03958 3833 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3834
3835 if (!ctx->ht.enabled) {
e7392364
SG		 3836 rxon->flags &=
3837 ~(RXON_FLG_CHANNEL_MODE_MSK |
3838 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
3839 | RXON_FLG_HT_PROT_MSK);
be663ab6
WYG		 3840 return;
3841 }
3842
e7392364
SG		 3843 rxon->flags |=
3844 cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
be663ab6
WYG		 3845
3846 /* Set up channel bandwidth:
3847 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3848 /* clear the HT channel mode before set the mode */
e7392364
SG		 3849 rxon->flags &=
3850 ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
46bc8d4b 3851 if (il_is_ht40_tx_allowed(il, ctx, NULL)) {
be663ab6 3852 /* pure ht40 */
e7392364 3853 if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
be663ab6
WYG		 3854 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3855 /* Note: control channel is opposite of extension channel */
3856 switch (ctx->ht.extension_chan_offset) {
3857 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3858 rxon->flags &=
e7392364 3859 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3860 break;
3861 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3862 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3863 break;
3864 }
3865 } else {
3866 /* Note: control channel is opposite of extension channel */
3867 switch (ctx->ht.extension_chan_offset) {
3868 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3869 rxon->flags &=
e7392364 3870 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
be663ab6
WYG		 3871 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3872 break;
3873 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3874 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3875 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3876 break;
3877 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3878 default:
3879 /* channel location only valid if in Mixed mode */
e7392364 3880 IL_ERR("invalid extension channel offset\n");
be663ab6
WYG		 3881 break;
3882 }
3883 }
3884 } else {
3885 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3886 }
3887
46bc8d4b
SG		 3888 if (il->cfg->ops->hcmd->set_rxon_chain)
3889 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6 3890
58de00a4 3891 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
e7392364
SG		 3892 "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
3893 ctx->ht.protection, ctx->ht.extension_chan_offset);
be663ab6
WYG		 3894}
3895
e7392364
SG		 3896void
3897il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3898{
17d6e557 3899 _il_set_rxon_ht(il, ht_conf, &il->ctx);
be663ab6 3900}
e2ebc833 3901EXPORT_SYMBOL(il_set_rxon_ht);
be663ab6
WYG		 3902
3903/* Return valid, unused, channel for a passive scan to reset the RF */
e7392364
SG		 3904u8
3905il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
be663ab6 3906{
e2ebc833 3907 const struct il_channel_info *ch_info;
be663ab6
WYG		 3908 int i;
3909 u8 channel = 0;
3910 u8 min, max;
be663ab6
WYG		 3911
3912 if (band == IEEE80211_BAND_5GHZ) {
3913 min = 14;
46bc8d4b 3914 max = il->channel_count;
be663ab6
WYG		 3915 } else {
3916 min = 0;
3917 max = 14;
3918 }
3919
3920 for (i = min; i < max; i++) {
17d6e557 3921 channel = il->channel_info[i].channel;
c8b03958 3922 if (channel == le16_to_cpu(il->staging.channel))
be663ab6
WYG		 3923 continue;
3924
46bc8d4b 3925 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3926 if (il_is_channel_valid(ch_info))
be663ab6
WYG		 3927 break;
3928 }
3929
3930 return channel;
3931}
e2ebc833 3932EXPORT_SYMBOL(il_get_single_channel_number);
be663ab6
WYG		 3933
3934/**
e2ebc833 3935 * il_set_rxon_channel - Set the band and channel values in staging RXON
be663ab6
WYG		 3936 * @ch: requested channel as a pointer to struct ieee80211_channel
3937
3938 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3939 * in the staging RXON flag structure based on the ch->band
3940 */
3941int
46bc8d4b 3942il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
e7392364 3943 struct il_rxon_context *ctx)
be663ab6
WYG		 3944{
3945 enum ieee80211_band band = ch->band;
3946 u16 channel = ch->hw_value;
3947
c8b03958 3948 if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
be663ab6
WYG		 3949 return 0;
3950
c8b03958 3951 il->staging.channel = cpu_to_le16(channel);
be663ab6 3952 if (band == IEEE80211_BAND_5GHZ)
c8b03958 3953 il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
be663ab6 3954 else
c8b03958 3955 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
be663ab6 3956
46bc8d4b 3957 il->band = band;
be663ab6 3958
58de00a4 3959 D_INFO("Staging channel set to %d [%d]\n", channel, band);
be663ab6
WYG		 3960
3961 return 0;
3962}
e2ebc833 3963EXPORT_SYMBOL(il_set_rxon_channel);
be663ab6 3964
e7392364
SG		 3965void
3966il_set_flags_for_band(struct il_priv *il, struct il_rxon_context *ctx,
3967 enum ieee80211_band band, struct ieee80211_vif *vif)
be663ab6
WYG		 3968{
3969 if (band == IEEE80211_BAND_5GHZ) {
c8b03958 3970 il->staging.flags &=
e7392364
SG		 3971 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
3972 RXON_FLG_CCK_MSK);
c8b03958 3973 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3974 } else {
e2ebc833 3975 /* Copied from il_post_associate() */
be663ab6 3976 if (vif && vif->bss_conf.use_short_slot)
c8b03958 3977 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3978 else
c8b03958 3979 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3980
c8b03958
SG		 3981 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3982 il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
3983 il->staging.flags &= ~RXON_FLG_CCK_MSK;
be663ab6
WYG		 3984 }
3985}
e2ebc833 3986EXPORT_SYMBOL(il_set_flags_for_band);
be663ab6
WYG		 3987
3988/*
3989 * initialize rxon structure with default values from eeprom
3990 */
e7392364
SG		 3991void
3992il_connection_init_rx_config(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 3993{
e2ebc833 3994 const struct il_channel_info *ch_info;
be663ab6 3995
c8b03958 3996 memset(&il->staging, 0, sizeof(il->staging));
be663ab6
WYG		 3997
3998 if (!ctx->vif) {
0f8b90f5 3999 il->staging.dev_type = RXON_DEV_TYPE_ESS;
be663ab6 4000 } else
e7392364 4001 switch (ctx->vif->type) {
be663ab6 4002
e7392364 4003 case NL80211_IFTYPE_STATION:
0f8b90f5 4004 il->staging.dev_type = RXON_DEV_TYPE_ESS;
c8b03958 4005 il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
e7392364 4006 break;
be663ab6 4007
e7392364 4008 case NL80211_IFTYPE_ADHOC:
0f8b90f5 4009 il->staging.dev_type = RXON_DEV_TYPE_IBSS;
c8b03958
SG		 4010 il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
4011 il->staging.filter_flags =
e7392364
SG		 4012 RXON_FILTER_BCON_AWARE_MSK |
4013 RXON_FILTER_ACCEPT_GRP_MSK;
4014 break;
be663ab6 4015
e7392364
SG		 4016 default:
4017 IL_ERR("Unsupported interface type %d\n",
4018 ctx->vif->type);
4019 break;
4020 }
be663ab6
WYG		 4021
4022#if 0
4023 /* TODO: Figure out when short_preamble would be set and cache from
4024 * that */
46bc8d4b 4025 if (!hw_to_local(il->hw)->short_preamble)
c8b03958 4026 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 4027 else
c8b03958 4028 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 4029#endif
4030
e7392364 4031 ch_info =
c8b03958 4032 il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
be663ab6
WYG		 4033
4034 if (!ch_info)
46bc8d4b 4035 ch_info = &il->channel_info[0];
be663ab6 4036
c8b03958 4037 il->staging.channel = cpu_to_le16(ch_info->channel);
46bc8d4b 4038 il->band = ch_info->band;
be663ab6 4039
46bc8d4b 4040 il_set_flags_for_band(il, ctx, il->band, ctx->vif);
be663ab6 4041
c8b03958 4042 il->staging.ofdm_basic_rates =
e2ebc833 4043 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
c8b03958 4044 il->staging.cck_basic_rates =
e2ebc833 4045 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6
WYG		 4046
4047 /* clear both MIX and PURE40 mode flag */
c8b03958 4048 il->staging.flags &=
e7392364 4049 ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
be663ab6 4050 if (ctx->vif)
c8b03958 4051 memcpy(il->staging.node_addr, ctx->vif->addr, ETH_ALEN);
be663ab6 4052
c8b03958
SG		 4053 il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
4054 il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
be663ab6 4055}
e2ebc833 4056EXPORT_SYMBOL(il_connection_init_rx_config);
be663ab6 4057
e7392364
SG		 4058void
4059il_set_rate(struct il_priv *il)
be663ab6
WYG		 4060{
4061 const struct ieee80211_supported_band *hw = NULL;
4062 struct ieee80211_rate *rate;
be663ab6
WYG		 4063 int i;
4064
46bc8d4b 4065 hw = il_get_hw_mode(il, il->band);
be663ab6 4066 if (!hw) {
9406f797 4067 IL_ERR("Failed to set rate: unable to get hw mode\n");
be663ab6
WYG		 4068 return;
4069 }
4070
46bc8d4b 4071 il->active_rate = 0;
be663ab6
WYG		 4072
4073 for (i = 0; i < hw->n_bitrates; i++) {
4074 rate = &(hw->bitrates[i]);
2eb05816 4075 if (rate->hw_value < RATE_COUNT_LEGACY)
46bc8d4b 4076 il->active_rate |= (1 << rate->hw_value);
be663ab6
WYG		 4077 }
4078
58de00a4 4079 D_RATE("Set active_rate = %0x\n", il->active_rate);
be663ab6 4080
c8b03958 4081 il->staging.cck_basic_rates =
e7392364 4082 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6 4083
c8b03958 4084 il->staging.ofdm_basic_rates =
e7392364 4085 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 4086}
e2ebc833 4087EXPORT_SYMBOL(il_set_rate);
be663ab6 4088
e7392364
SG		 4089void
4090il_chswitch_done(struct il_priv *il, bool is_success)
be663ab6 4091{
7c2cde2e 4092 struct il_rxon_context *ctx = &il->ctx;
be663ab6 4093
a6766ccd 4094 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4095 return;
4096
a6766ccd 4097 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
be663ab6 4098 ieee80211_chswitch_done(ctx->vif, is_success);
be663ab6 4099}
e2ebc833 4100EXPORT_SYMBOL(il_chswitch_done);
be663ab6 4101
e7392364
SG		 4102void
4103il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4104{
dcae1c64 4105 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4106 struct il_csa_notification *csa = &(pkt->u.csa_notif);
c8b03958 4107 struct il_rxon_cmd *rxon = (void *)&il->active;
be663ab6 4108
a6766ccd 4109 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
51e65257
SG		 4110 return;
4111
46bc8d4b 4112 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
51e65257 4113 rxon->channel = csa->channel;
c8b03958 4114 il->staging.channel = csa->channel;
e7392364 4115 D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
46bc8d4b 4116 il_chswitch_done(il, true);
51e65257 4117 } else {
9406f797 4118 IL_ERR("CSA notif (fail) : channel %d\n",
e7392364 4119 le16_to_cpu(csa->channel));
46bc8d4b 4120 il_chswitch_done(il, false);
be663ab6
WYG		 4121 }
4122}
d2dfb33e 4123EXPORT_SYMBOL(il_hdl_csa);
be663ab6 4124
d3175167 4125#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 4126void
4127il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 4128{
c8b03958 4129 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 4130
58de00a4 4131 D_RADIO("RX CONFIG:\n");
46bc8d4b 4132 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e7392364 4133 D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
58de00a4 4134 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
e7392364 4135 D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
58de00a4 4136 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
e7392364
SG		 4137 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
4138 D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
58de00a4
SG		 4139 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4140 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
e7392364 4141 D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
be663ab6 4142}
e2ebc833 4143EXPORT_SYMBOL(il_print_rx_config_cmd);
be663ab6
WYG		 4144#endif
4145/**
e2ebc833 4146 * il_irq_handle_error - called for HW or SW error interrupt from card
be663ab6 4147 */
e7392364
SG		 4148void
4149il_irq_handle_error(struct il_priv *il)
be663ab6 4150{
e2ebc833 4151 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4152 set_bit(S_FW_ERROR, &il->status);
be663ab6
WYG		 4153
4154 /* Cancel currently queued command. */
a6766ccd 4155 clear_bit(S_HCMD_ACTIVE, &il->status);
be663ab6 4156
e7392364 4157 IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
be663ab6 4158
46bc8d4b
SG		 4159 il->cfg->ops->lib->dump_nic_error_log(il);
4160 if (il->cfg->ops->lib->dump_fh)
4161 il->cfg->ops->lib->dump_fh(il, NULL, false);
d3175167 4162#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4163 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
e7392364 4164 il_print_rx_config_cmd(il, &il->ctx);
be663ab6
WYG		 4165#endif
4166
46bc8d4b 4167 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4168
4169 /* Keep the restart process from trying to send host
4170 * commands by clearing the INIT status bit */
a6766ccd 4171 clear_bit(S_READY, &il->status);
be663ab6 4172
a6766ccd 4173 if (!test_bit(S_EXIT_PENDING, &il->status)) {
58de00a4 4174 IL_DBG(IL_DL_FW_ERRORS,
e7392364 4175 "Restarting adapter due to uCode error.\n");
be663ab6 4176
46bc8d4b
SG		 4177 if (il->cfg->mod_params->restart_fw)
4178 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 4179 }
4180}
e2ebc833 4181EXPORT_SYMBOL(il_irq_handle_error);
be663ab6 4182
e7392364
SG		 4183static int
4184il_apm_stop_master(struct il_priv *il)
be663ab6
WYG		 4185{
4186 int ret = 0;
4187
4188 /* stop device's busmaster DMA activity */
46bc8d4b 4189 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
be663ab6 4190
e7392364
SG		 4191 ret =
4192 _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
4193 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
be663ab6 4194 if (ret)
9406f797 4195 IL_WARN("Master Disable Timed Out, 100 usec\n");
be663ab6 4196
58de00a4 4197 D_INFO("stop master\n");
be663ab6
WYG		 4198
4199 return ret;
4200}
4201
e7392364
SG		 4202void
4203il_apm_stop(struct il_priv *il)
be663ab6 4204{
58de00a4 4205 D_INFO("Stop card, put in low power state\n");
be663ab6
WYG		 4206
4207 /* Stop device's DMA activity */
46bc8d4b 4208 il_apm_stop_master(il);
be663ab6
WYG		 4209
4210 /* Reset the entire device */
46bc8d4b 4211 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
be663ab6
WYG		 4212
4213 udelay(10);
4214
4215 /*
4216 * Clear "initialization complete" bit to move adapter from
4217 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4218 */
e7392364 4219 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6 4220}
e7392364 4221EXPORT_SYMBOL(il_apm_stop);
be663ab6
WYG		 4222
4223/*
4224 * Start up NIC's basic functionality after it has been reset
e2ebc833 4225 * (e.g. after platform boot, or shutdown via il_apm_stop())
be663ab6
WYG		 4226 * NOTE: This does not load uCode nor start the embedded processor
4227 */
e7392364
SG		 4228int
4229il_apm_init(struct il_priv *il)
be663ab6
WYG		 4230{
4231 int ret = 0;
4232 u16 lctl;
4233
58de00a4 4234 D_INFO("Init card's basic functions\n");
be663ab6
WYG		 4235
4236 /*
4237 * Use "set_bit" below rather than "write", to preserve any hardware
4238 * bits already set by default after reset.
4239 */
4240
4241 /* Disable L0S exit timer (platform NMI Work/Around) */
46bc8d4b 4242 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4243 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
be663ab6
WYG		 4244
4245 /*
4246 * Disable L0s without affecting L1;
4247 * don't wait for ICH L0s (ICH bug W/A)
4248 */
46bc8d4b 4249 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4250 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
be663ab6
WYG		 4251
4252 /* Set FH wait threshold to maximum (HW error during stress W/A) */
e7392364 4253 il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
be663ab6
WYG		 4254
4255 /*
4256 * Enable HAP INTA (interrupt from management bus) to
4257 * wake device's PCI Express link L1a -> L0s
25985edc 4258 * NOTE: This is no-op for 3945 (non-existent bit)
be663ab6 4259 */
46bc8d4b 4260 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 4261 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
be663ab6
WYG		 4262
4263 /*
4264 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4265 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4266 * If so (likely), disable L0S, so device moves directly L0->L1;
4267 * costs negligible amount of power savings.
4268 * If not (unlikely), enable L0S, so there is at least some
4269 * power savings, even without L1.
4270 */
46bc8d4b
SG		 4271 if (il->cfg->base_params->set_l0s) {
4272 lctl = il_pcie_link_ctl(il);
be663ab6 4273 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
e7392364 4274 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
be663ab6 4275 /* L1-ASPM enabled; disable(!) L0S */
46bc8d4b 4276 il_set_bit(il, CSR_GIO_REG,
e7392364 4277 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4278 D_POWER("L1 Enabled; Disabling L0S\n");
be663ab6
WYG		 4279 } else {
4280 /* L1-ASPM disabled; enable(!) L0S */
46bc8d4b 4281 il_clear_bit(il, CSR_GIO_REG,
e7392364 4282 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4283 D_POWER("L1 Disabled; Enabling L0S\n");
be663ab6
WYG		 4284 }
4285 }
4286
4287 /* Configure analog phase-lock-loop before activating to D0A */
46bc8d4b
SG		 4288 if (il->cfg->base_params->pll_cfg_val)
4289 il_set_bit(il, CSR_ANA_PLL_CFG,
e7392364 4290 il->cfg->base_params->pll_cfg_val);
be663ab6
WYG		 4291
4292 /*
4293 * Set "initialization complete" bit to move adapter from
4294 * D0U* --> D0A* (powered-up active) state.
4295 */
46bc8d4b 4296 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6
WYG		 4297
4298 /*
4299 * Wait for clock stabilization; once stabilized, access to
db54eb57 4300 * device-internal resources is supported, e.g. il_wr_prph()
be663ab6
WYG		 4301 * and accesses to uCode SRAM.
4302 */
e7392364
SG		 4303 ret =
4304 _il_poll_bit(il, CSR_GP_CNTRL,
4305 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4306 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
be663ab6 4307 if (ret < 0) {
58de00a4 4308 D_INFO("Failed to init the card\n");
be663ab6
WYG		 4309 goto out;
4310 }
4311
4312 /*
4313 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4314 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4315 *
4316 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4317 * do not disable clocks. This preserves any hardware bits already
4318 * set by default in "CLK_CTRL_REG" after reset.
4319 */
46bc8d4b 4320 if (il->cfg->base_params->use_bsm)
db54eb57 4321 il_wr_prph(il, APMG_CLK_EN_REG,
e7392364 4322 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
be663ab6 4323 else
e7392364 4324 il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 4325 udelay(20);
4326
4327 /* Disable L1-Active */
46bc8d4b 4328 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
e7392364 4329 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
be663ab6
WYG		 4330
4331out:
4332 return ret;
4333}
e7392364 4334EXPORT_SYMBOL(il_apm_init);
be663ab6 4335
e7392364
SG		 4336int
4337il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
be663ab6
WYG		 4338{
4339 int ret;
4340 s8 prev_tx_power;
43f12d47 4341 bool defer;
be663ab6 4342
46bc8d4b 4343 lockdep_assert_held(&il->mutex);
be663ab6 4344
46bc8d4b 4345 if (il->tx_power_user_lmt == tx_power && !force)
be663ab6
WYG		 4346 return 0;
4347
46bc8d4b 4348 if (!il->cfg->ops->lib->send_tx_power)
be663ab6
WYG		 4349 return -EOPNOTSUPP;
4350
332704a5
SG		 4351 /* 0 dBm mean 1 milliwatt */
4352 if (tx_power < 0) {
e7392364 4353 IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
be663ab6
WYG		 4354 return -EINVAL;
4355 }
4356
46bc8d4b 4357 if (tx_power > il->tx_power_device_lmt) {
e7392364
SG		 4358 IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
4359 tx_power, il->tx_power_device_lmt);
be663ab6
WYG		 4360 return -EINVAL;
4361 }
4362
46bc8d4b 4363 if (!il_is_ready_rf(il))
be663ab6
WYG		 4364 return -EIO;
4365
43f12d47
SG		 4366 /* scan complete and commit_rxon use tx_power_next value,
4367 * it always need to be updated for newest request */
46bc8d4b 4368 il->tx_power_next = tx_power;
43f12d47
SG		 4369
4370 /* do not set tx power when scanning or channel changing */
a6766ccd 4371 defer = test_bit(S_SCANNING, &il->status) ||
c8b03958 4372 memcmp(&il->active, &il->staging, sizeof(il->staging));
43f12d47 4373 if (defer && !force) {
58de00a4 4374 D_INFO("Deferring tx power set\n");
be663ab6
WYG		 4375 return 0;
4376 }
4377
46bc8d4b
SG		 4378 prev_tx_power = il->tx_power_user_lmt;
4379 il->tx_power_user_lmt = tx_power;
be663ab6 4380
46bc8d4b 4381 ret = il->cfg->ops->lib->send_tx_power(il);
be663ab6
WYG		 4382
4383 /* if fail to set tx_power, restore the orig. tx power */
4384 if (ret) {
46bc8d4b
SG		 4385 il->tx_power_user_lmt = prev_tx_power;
4386 il->tx_power_next = prev_tx_power;
be663ab6
WYG		 4387 }
4388 return ret;
4389}
e2ebc833 4390EXPORT_SYMBOL(il_set_tx_power);
be663ab6 4391
e7392364
SG		 4392void
4393il_send_bt_config(struct il_priv *il)
be663ab6 4394{
e2ebc833 4395 struct il_bt_cmd bt_cmd = {
be663ab6
WYG		 4396 .lead_time = BT_LEAD_TIME_DEF,
4397 .max_kill = BT_MAX_KILL_DEF,
4398 .kill_ack_mask = 0,
4399 .kill_cts_mask = 0,
4400 };
4401
4402 if (!bt_coex_active)
4403 bt_cmd.flags = BT_COEX_DISABLE;
4404 else
4405 bt_cmd.flags = BT_COEX_ENABLE;
4406
58de00a4 4407 D_INFO("BT coex %s\n",
e7392364 4408 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
be663ab6 4409
e7392364 4410 if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
9406f797 4411 IL_ERR("failed to send BT Coex Config\n");
be663ab6 4412}
e2ebc833 4413EXPORT_SYMBOL(il_send_bt_config);
be663ab6 4414
e7392364
SG		 4415int
4416il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
be663ab6 4417{
ebf0d90d 4418 struct il_stats_cmd stats_cmd = {
e7392364 4419 .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
be663ab6
WYG		 4420 };
4421
4422 if (flags & CMD_ASYNC)
e7392364
SG		 4423 return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
4424 &stats_cmd, NULL);
be663ab6 4425 else
e7392364
SG		 4426 return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
4427 &stats_cmd);
be663ab6 4428}
ebf0d90d 4429EXPORT_SYMBOL(il_send_stats_request);
be663ab6 4430
e7392364
SG		 4431void
4432il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4433{
d3175167 4434#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 4435 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4436 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
58de00a4 4437 D_RX("sleep mode: %d, src: %d\n",
1722f8e1 4438 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
be663ab6
WYG		 4439#endif
4440}
d2dfb33e 4441EXPORT_SYMBOL(il_hdl_pm_sleep);
be663ab6 4442
e7392364
SG		 4443void
4444il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4445{
dcae1c64 4446 struct il_rx_pkt *pkt = rxb_addr(rxb);
e94a4099 4447 u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364
SG		 4448 D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
4449 il_get_cmd_string(pkt->hdr.cmd));
46bc8d4b 4450 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
be663ab6 4451}
d2dfb33e 4452EXPORT_SYMBOL(il_hdl_pm_debug_stats);
be663ab6 4453
e7392364
SG		 4454void
4455il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4456{
dcae1c64 4457 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4458
9406f797 4459 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
e7392364
SG		 4460 "seq 0x%04X ser 0x%08X\n",
4461 le32_to_cpu(pkt->u.err_resp.error_type),
4462 il_get_cmd_string(pkt->u.err_resp.cmd_id),
4463 pkt->u.err_resp.cmd_id,
4464 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4465 le32_to_cpu(pkt->u.err_resp.error_info));
be663ab6 4466}
6e9848b4 4467EXPORT_SYMBOL(il_hdl_error);
be663ab6 4468
e7392364
SG		 4469void
4470il_clear_isr_stats(struct il_priv *il)
be663ab6 4471{
46bc8d4b 4472 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
be663ab6
WYG		 4473}
4474
e7392364
SG		 4475int
4476il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
4477 const struct ieee80211_tx_queue_params *params)
be663ab6 4478{
46bc8d4b 4479 struct il_priv *il = hw->priv;
be663ab6
WYG		 4480 unsigned long flags;
4481 int q;
4482
58de00a4 4483 D_MAC80211("enter\n");
be663ab6 4484
46bc8d4b 4485 if (!il_is_ready_rf(il)) {
58de00a4 4486 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 4487 return -EIO;
4488 }
4489
4490 if (queue >= AC_NUM) {
58de00a4 4491 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
be663ab6
WYG		 4492 return 0;
4493 }
4494
4495 q = AC_NUM - 1 - queue;
4496
46bc8d4b 4497 spin_lock_irqsave(&il->lock, flags);
be663ab6 4498
8d44f2bd 4499 il->qos_data.def_qos_parm.ac[q].cw_min =
e7392364 4500 cpu_to_le16(params->cw_min);
8d44f2bd 4501 il->qos_data.def_qos_parm.ac[q].cw_max =
e7392364 4502 cpu_to_le16(params->cw_max);
8d44f2bd
SG		 4503 il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4504 il->qos_data.def_qos_parm.ac[q].edca_txop =
e7392364 4505 cpu_to_le16((params->txop * 32));
be663ab6 4506
8d44f2bd 4507 il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
be663ab6 4508
46bc8d4b 4509 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 4510
58de00a4 4511 D_MAC80211("leave\n");
be663ab6
WYG		 4512 return 0;
4513}
e2ebc833 4514EXPORT_SYMBOL(il_mac_conf_tx);
be663ab6 4515
e7392364
SG		 4516int
4517il_mac_tx_last_beacon(struct ieee80211_hw *hw)
be663ab6 4518{
46bc8d4b 4519 struct il_priv *il = hw->priv;
be663ab6 4520
46bc8d4b 4521 return il->ibss_manager == IL_IBSS_MANAGER;
be663ab6 4522}
e2ebc833 4523EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
be663ab6
WYG		 4524
4525static int
46bc8d4b 4526il_set_mode(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 4527{
46bc8d4b 4528 il_connection_init_rx_config(il, ctx);
be663ab6 4529
46bc8d4b
SG		 4530 if (il->cfg->ops->hcmd->set_rxon_chain)
4531 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6 4532
46bc8d4b 4533 return il_commit_rxon(il, ctx);
be663ab6
WYG		 4534}
4535
e7392364
SG		 4536static int
4537il_setup_interface(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG		 4538{
4539 struct ieee80211_vif *vif = ctx->vif;
4540 int err;
4541
46bc8d4b 4542 lockdep_assert_held(&il->mutex);
be663ab6
WYG		 4543
4544 /*
4545 * This variable will be correct only when there's just
4546 * a single context, but all code using it is for hardware
4547 * that supports only one context.
4548 */
46bc8d4b 4549 il->iw_mode = vif->type;
be663ab6
WYG		 4550
4551 ctx->is_active = true;
4552
46bc8d4b 4553 err = il_set_mode(il, ctx);
be663ab6
WYG		 4554 if (err) {
4555 if (!ctx->always_active)
4556 ctx->is_active = false;
4557 return err;
4558 }
4559
4560 return 0;
4561}
4562
4563int
e2ebc833 4564il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4565{
46bc8d4b 4566 struct il_priv *il = hw->priv;
e2ebc833 4567 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
be663ab6
WYG		 4568 int err;
4569
e7392364 4570 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4571
46bc8d4b 4572 mutex_lock(&il->mutex);
be663ab6 4573
46bc8d4b 4574 if (!il_is_ready_rf(il)) {
9406f797 4575 IL_WARN("Try to add interface when device not ready\n");
be663ab6
WYG		 4576 err = -EINVAL;
4577 goto out;
4578 }
4579
8c9c48d5 4580 if (il->ctx.vif) {
be663ab6
WYG		 4581 err = -EOPNOTSUPP;
4582 goto out;
4583 }
4584
17d6e557
SG		 4585 vif_priv->ctx = &il->ctx;
4586 il->ctx.vif = vif;
be663ab6 4587
17d6e557
SG		 4588 err = il_setup_interface(il, &il->ctx);
4589 if (err) {
4590 il->ctx.vif = NULL;
4591 il->iw_mode = NL80211_IFTYPE_STATION;
4592 }
be663ab6 4593
e7392364 4594out:
46bc8d4b 4595 mutex_unlock(&il->mutex);
be663ab6 4596
58de00a4 4597 D_MAC80211("leave\n");
be663ab6
WYG		 4598 return err;
4599}
e2ebc833 4600EXPORT_SYMBOL(il_mac_add_interface);
be663ab6 4601
e7392364
SG		 4602static void
4603il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif,
4604 bool mode_change)
be663ab6 4605{
e2ebc833 4606 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 4607
46bc8d4b 4608 lockdep_assert_held(&il->mutex);
be663ab6 4609
46bc8d4b
SG		 4610 if (il->scan_vif == vif) {
4611 il_scan_cancel_timeout(il, 200);
4612 il_force_scan_end(il);
be663ab6
WYG		 4613 }
4614
4615 if (!mode_change) {
46bc8d4b 4616 il_set_mode(il, ctx);
be663ab6
WYG		 4617 if (!ctx->always_active)
4618 ctx->is_active = false;
4619 }
4620}
4621
e7392364
SG		 4622void
4623il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4624{
46bc8d4b 4625 struct il_priv *il = hw->priv;
e2ebc833 4626 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 4627
58de00a4 4628 D_MAC80211("enter\n");
be663ab6 4629
46bc8d4b 4630 mutex_lock(&il->mutex);
be663ab6
WYG		 4631
4632 WARN_ON(ctx->vif != vif);
4633 ctx->vif = NULL;
4634
46bc8d4b 4635 il_teardown_interface(il, vif, false);
be663ab6 4636
46bc8d4b
SG		 4637 memset(il->bssid, 0, ETH_ALEN);
4638 mutex_unlock(&il->mutex);
be663ab6 4639
58de00a4 4640 D_MAC80211("leave\n");
be663ab6
WYG		 4641
4642}
e2ebc833 4643EXPORT_SYMBOL(il_mac_remove_interface);
be663ab6 4644
e7392364
SG		 4645int
4646il_alloc_txq_mem(struct il_priv *il)
be663ab6 4647{
46bc8d4b 4648 if (!il->txq)
e7392364
SG		 4649 il->txq =
4650 kzalloc(sizeof(struct il_tx_queue) *
4651 il->cfg->base_params->num_of_queues, GFP_KERNEL);
46bc8d4b 4652 if (!il->txq) {
9406f797 4653 IL_ERR("Not enough memory for txq\n");
be663ab6
WYG		 4654 return -ENOMEM;
4655 }
4656 return 0;
4657}
e2ebc833 4658EXPORT_SYMBOL(il_alloc_txq_mem);
be663ab6 4659
e7392364
SG		 4660void
4661il_txq_mem(struct il_priv *il)
be663ab6 4662{
46bc8d4b
SG		 4663 kfree(il->txq);
4664 il->txq = NULL;
be663ab6 4665}
e2ebc833 4666EXPORT_SYMBOL(il_txq_mem);
be663ab6 4667
d3175167 4668#ifdef CONFIG_IWLEGACY_DEBUGFS
be663ab6 4669
e2ebc833 4670#define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES)
be663ab6 4671
e7392364
SG		 4672void
4673il_reset_traffic_log(struct il_priv *il)
be663ab6 4674{
46bc8d4b
SG		 4675 il->tx_traffic_idx = 0;
4676 il->rx_traffic_idx = 0;
4677 if (il->tx_traffic)
4678 memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
4679 if (il->rx_traffic)
4680 memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
be663ab6
WYG		 4681}
4682
e7392364
SG		 4683int
4684il_alloc_traffic_mem(struct il_priv *il)
be663ab6 4685{
e2ebc833 4686 u32 traffic_size = IL_TRAFFIC_DUMP_SIZE;
be663ab6 4687
d2ddf621 4688 if (il_debug_level & IL_DL_TX) {
46bc8d4b 4689 if (!il->tx_traffic) {
e7392364 4690 il->tx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4691 if (!il->tx_traffic)
be663ab6
WYG		 4692 return -ENOMEM;
4693 }
4694 }
d2ddf621 4695 if (il_debug_level & IL_DL_RX) {
46bc8d4b 4696 if (!il->rx_traffic) {
e7392364 4697 il->rx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4698 if (!il->rx_traffic)
be663ab6
WYG		 4699 return -ENOMEM;
4700 }
4701 }
46bc8d4b 4702 il_reset_traffic_log(il);
be663ab6
WYG		 4703 return 0;
4704}
e2ebc833 4705EXPORT_SYMBOL(il_alloc_traffic_mem);
be663ab6 4706
e7392364
SG		 4707void
4708il_free_traffic_mem(struct il_priv *il)
be663ab6 4709{
46bc8d4b
SG		 4710 kfree(il->tx_traffic);
4711 il->tx_traffic = NULL;
be663ab6 4712
46bc8d4b
SG		 4713 kfree(il->rx_traffic);
4714 il->rx_traffic = NULL;
be663ab6 4715}
e2ebc833 4716EXPORT_SYMBOL(il_free_traffic_mem);
be663ab6 4717
e7392364
SG		 4718void
4719il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
4720 struct ieee80211_hdr *header)
be663ab6
WYG		 4721{
4722 __le16 fc;
4723 u16 len;
4724
d2ddf621 4725 if (likely(!(il_debug_level & IL_DL_TX)))
be663ab6
WYG		 4726 return;
4727
46bc8d4b 4728 if (!il->tx_traffic)
be663ab6
WYG		 4729 return;
4730
4731 fc = header->frame_control;
4732 if (ieee80211_is_data(fc)) {
e7392364
SG		 4733 len =
4734 (length >
4735 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4736 memcpy((il->tx_traffic +
e7392364
SG		 4737 (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4738 len);
46bc8d4b 4739 il->tx_traffic_idx =
e7392364 4740 (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4741 }
4742}
e2ebc833 4743EXPORT_SYMBOL(il_dbg_log_tx_data_frame);
be663ab6 4744
e7392364
SG		 4745void
4746il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
4747 struct ieee80211_hdr *header)
be663ab6
WYG		 4748{
4749 __le16 fc;
4750 u16 len;
4751
d2ddf621 4752 if (likely(!(il_debug_level & IL_DL_RX)))
be663ab6
WYG		 4753 return;
4754
46bc8d4b 4755 if (!il->rx_traffic)
be663ab6
WYG		 4756 return;
4757
4758 fc = header->frame_control;
4759 if (ieee80211_is_data(fc)) {
e7392364
SG		 4760 len =
4761 (length >
4762 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4763 memcpy((il->rx_traffic +
e7392364
SG		 4764 (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4765 len);
46bc8d4b 4766 il->rx_traffic_idx =
e7392364 4767 (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4768 }
4769}
e2ebc833 4770EXPORT_SYMBOL(il_dbg_log_rx_data_frame);
be663ab6 4771
e7392364
SG		 4772const char *
4773il_get_mgmt_string(int cmd)
be663ab6
WYG		 4774{
4775 switch (cmd) {
e2ebc833
SG		 4776 IL_CMD(MANAGEMENT_ASSOC_REQ);
4777 IL_CMD(MANAGEMENT_ASSOC_RESP);
4778 IL_CMD(MANAGEMENT_REASSOC_REQ);
4779 IL_CMD(MANAGEMENT_REASSOC_RESP);
4780 IL_CMD(MANAGEMENT_PROBE_REQ);
4781 IL_CMD(MANAGEMENT_PROBE_RESP);
4782 IL_CMD(MANAGEMENT_BEACON);
4783 IL_CMD(MANAGEMENT_ATIM);
4784 IL_CMD(MANAGEMENT_DISASSOC);
4785 IL_CMD(MANAGEMENT_AUTH);
4786 IL_CMD(MANAGEMENT_DEAUTH);
4787 IL_CMD(MANAGEMENT_ACTION);
be663ab6
WYG		 4788 default:
4789 return "UNKNOWN";
4790
4791 }
4792}
4793
e7392364
SG		 4794const char *
4795il_get_ctrl_string(int cmd)
be663ab6
WYG		 4796{
4797 switch (cmd) {
e2ebc833
SG		 4798 IL_CMD(CONTROL_BACK_REQ);
4799 IL_CMD(CONTROL_BACK);
4800 IL_CMD(CONTROL_PSPOLL);
4801 IL_CMD(CONTROL_RTS);
4802 IL_CMD(CONTROL_CTS);
4803 IL_CMD(CONTROL_ACK);
4804 IL_CMD(CONTROL_CFEND);
4805 IL_CMD(CONTROL_CFENDACK);
be663ab6
WYG		 4806 default:
4807 return "UNKNOWN";
4808
4809 }
4810}
4811
e7392364
SG		 4812void
4813il_clear_traffic_stats(struct il_priv *il)
be663ab6 4814{
46bc8d4b
SG		 4815 memset(&il->tx_stats, 0, sizeof(struct traffic_stats));
4816 memset(&il->rx_stats, 0, sizeof(struct traffic_stats));
be663ab6
WYG		 4817}
4818
4819/*
d3175167 4820 * if CONFIG_IWLEGACY_DEBUGFS defined,
e2ebc833 4821 * il_update_stats function will
be663ab6 4822 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass
ebf0d90d 4823 * Use debugFs to display the rx/rx_stats
d3175167 4824 * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL
be663ab6 4825 * information will be recorded, but DATA pkt still will be recorded
e2ebc833 4826 * for the reason of il_led.c need to control the led blinking based on
be663ab6
WYG		 4827 * number of tx and rx data.
4828 *
4829 */
4830void
46bc8d4b 4831il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6 4832{
e7392364 4833 struct traffic_stats *stats;
be663ab6
WYG		 4834
4835 if (is_tx)
46bc8d4b 4836 stats = &il->tx_stats;
be663ab6 4837 else
46bc8d4b 4838 stats = &il->rx_stats;
be663ab6
WYG		 4839
4840 if (ieee80211_is_mgmt(fc)) {
4841 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4842 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
4843 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
4844 break;
4845 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
4846 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
4847 break;
4848 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
4849 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
4850 break;
4851 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
4852 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
4853 break;
4854 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
4855 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
4856 break;
4857 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
4858 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
4859 break;
4860 case cpu_to_le16(IEEE80211_STYPE_BEACON):
4861 stats->mgmt[MANAGEMENT_BEACON]++;
4862 break;
4863 case cpu_to_le16(IEEE80211_STYPE_ATIM):
4864 stats->mgmt[MANAGEMENT_ATIM]++;
4865 break;
4866 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
4867 stats->mgmt[MANAGEMENT_DISASSOC]++;
4868 break;
4869 case cpu_to_le16(IEEE80211_STYPE_AUTH):
4870 stats->mgmt[MANAGEMENT_AUTH]++;
4871 break;
4872 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
4873 stats->mgmt[MANAGEMENT_DEAUTH]++;
4874 break;
4875 case cpu_to_le16(IEEE80211_STYPE_ACTION):
4876 stats->mgmt[MANAGEMENT_ACTION]++;
4877 break;
4878 }
4879 } else if (ieee80211_is_ctl(fc)) {
4880 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4881 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
4882 stats->ctrl[CONTROL_BACK_REQ]++;
4883 break;
4884 case cpu_to_le16(IEEE80211_STYPE_BACK):
4885 stats->ctrl[CONTROL_BACK]++;
4886 break;
4887 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
4888 stats->ctrl[CONTROL_PSPOLL]++;
4889 break;
4890 case cpu_to_le16(IEEE80211_STYPE_RTS):
4891 stats->ctrl[CONTROL_RTS]++;
4892 break;
4893 case cpu_to_le16(IEEE80211_STYPE_CTS):
4894 stats->ctrl[CONTROL_CTS]++;
4895 break;
4896 case cpu_to_le16(IEEE80211_STYPE_ACK):
4897 stats->ctrl[CONTROL_ACK]++;
4898 break;
4899 case cpu_to_le16(IEEE80211_STYPE_CFEND):
4900 stats->ctrl[CONTROL_CFEND]++;
4901 break;
4902 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
4903 stats->ctrl[CONTROL_CFENDACK]++;
4904 break;
4905 }
4906 } else {
4907 /* data */
4908 stats->data_cnt++;
4909 stats->data_bytes += len;
4910 }
4911}
e2ebc833 4912EXPORT_SYMBOL(il_update_stats);
be663ab6
WYG		 4913#endif
4914
e7392364
SG		 4915int
4916il_force_reset(struct il_priv *il, bool external)
be663ab6 4917{
e2ebc833 4918 struct il_force_reset *force_reset;
be663ab6 4919
a6766ccd 4920 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4921 return -EINVAL;
4922
46bc8d4b 4923 force_reset = &il->force_reset;
be663ab6
WYG		 4924 force_reset->reset_request_count++;
4925 if (!external) {
4926 if (force_reset->last_force_reset_jiffies &&
4927 time_after(force_reset->last_force_reset_jiffies +
e7392364 4928 force_reset->reset_duration, jiffies)) {
58de00a4 4929 D_INFO("force reset rejected\n");
be663ab6
WYG		 4930 force_reset->reset_reject_count++;
4931 return -EAGAIN;
4932 }
4933 }
4934 force_reset->reset_success_count++;
4935 force_reset->last_force_reset_jiffies = jiffies;
dd6d2a8a
SG		 4936
4937 /*
4938 * if the request is from external(ex: debugfs),
4939 * then always perform the request in regardless the module
4940 * parameter setting
4941 * if the request is from internal (uCode error or driver
4942 * detect failure), then fw_restart module parameter
4943 * need to be check before performing firmware reload
4944 */
4945
46bc8d4b 4946 if (!external && !il->cfg->mod_params->restart_fw) {
58de00a4 4947 D_INFO("Cancel firmware reload based on "
e7392364 4948 "module parameter setting\n");
dd6d2a8a 4949 return 0;
be663ab6 4950 }
dd6d2a8a 4951
9406f797 4952 IL_ERR("On demand firmware reload\n");
dd6d2a8a 4953
e2ebc833 4954 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4955 set_bit(S_FW_ERROR, &il->status);
46bc8d4b 4956 wake_up(&il->wait_command_queue);
dd6d2a8a
SG		 4957 /*
4958 * Keep the restart process from trying to send host
4959 * commands by clearing the INIT status bit
4960 */
a6766ccd 4961 clear_bit(S_READY, &il->status);
46bc8d4b 4962 queue_work(il->workqueue, &il->restart);
dd6d2a8a 4963
be663ab6
WYG		 4964 return 0;
4965}
4966
4967int
e7392364 4968il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
be663ab6
WYG		 4969 enum nl80211_iftype newtype, bool newp2p)
4970{
46bc8d4b 4971 struct il_priv *il = hw->priv;
e2ebc833 4972 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6
WYG		 4973 int err;
4974
8c9c48d5
SG		 4975 if (newp2p)
4976 return -EOPNOTSUPP;
be663ab6 4977
46bc8d4b 4978 mutex_lock(&il->mutex);
be663ab6 4979
46bc8d4b 4980 if (!ctx->vif || !il_is_ready_rf(il)) {
ffd8c746
JB		 4981 /*
4982 * Huh? But wait ... this can maybe happen when
4983 * we're in the middle of a firmware restart!
4984 */
4985 err = -EBUSY;
4986 goto out;
4987 }
4988
be663ab6 4989 /* success */
46bc8d4b 4990 il_teardown_interface(il, vif, true);
be663ab6 4991 vif->type = newtype;
8c9c48d5 4992 vif->p2p = false;
46bc8d4b 4993 err = il_setup_interface(il, ctx);
be663ab6
WYG		 4994 WARN_ON(err);
4995 /*
4996 * We've switched internally, but submitting to the
4997 * device may have failed for some reason. Mask this
4998 * error, because otherwise mac80211 will not switch
4999 * (and set the interface type back) and we'll be
5000 * out of sync with it.
5001 */
5002 err = 0;
5003
e7392364 5004out:
46bc8d4b 5005 mutex_unlock(&il->mutex);
be663ab6
WYG		 5006 return err;
5007}
e2ebc833 5008EXPORT_SYMBOL(il_mac_change_interface);
be663ab6
WYG		 5009
5010/*
5011 * On every watchdog tick we check (latest) time stamp. If it does not
5012 * change during timeout period and queue is not empty we reset firmware.
5013 */
e7392364
SG		 5014static int
5015il_check_stuck_queue(struct il_priv *il, int cnt)
be663ab6 5016{
46bc8d4b 5017 struct il_tx_queue *txq = &il->txq[cnt];
e2ebc833 5018 struct il_queue *q = &txq->q;
be663ab6
WYG		 5019 unsigned long timeout;
5020 int ret;
5021
5022 if (q->read_ptr == q->write_ptr) {
5023 txq->time_stamp = jiffies;
5024 return 0;
5025 }
5026
e7392364
SG		 5027 timeout =
5028 txq->time_stamp +
5029 msecs_to_jiffies(il->cfg->base_params->wd_timeout);
be663ab6
WYG		 5030
5031 if (time_after(jiffies, timeout)) {
e7392364
SG		 5032 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
5033 il->cfg->base_params->wd_timeout);
46bc8d4b 5034 ret = il_force_reset(il, false);
be663ab6
WYG		 5035 return (ret == -EAGAIN) ? 0 : 1;
5036 }
5037
5038 return 0;
5039}
5040
5041/*
5042 * Making watchdog tick be a quarter of timeout assure we will
5043 * discover the queue hung between timeout and 1.25*timeout
5044 */
e2ebc833 5045#define IL_WD_TICK(timeout) ((timeout) / 4)
be663ab6
WYG		 5046
5047/*
5048 * Watchdog timer callback, we check each tx queue for stuck, if if hung
5049 * we reset the firmware. If everything is fine just rearm the timer.
5050 */
e7392364
SG		 5051void
5052il_bg_watchdog(unsigned long data)
be663ab6 5053{
46bc8d4b 5054 struct il_priv *il = (struct il_priv *)data;
be663ab6
WYG		 5055 int cnt;
5056 unsigned long timeout;
5057
a6766ccd 5058 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5059 return;
5060
46bc8d4b 5061 timeout = il->cfg->base_params->wd_timeout;
be663ab6
WYG		 5062 if (timeout == 0)
5063 return;
5064
5065 /* monitor and check for stuck cmd queue */
46bc8d4b 5066 if (il_check_stuck_queue(il, il->cmd_queue))
be663ab6
WYG		 5067 return;
5068
5069 /* monitor and check for other stuck queues */
46bc8d4b
SG		 5070 if (il_is_any_associated(il)) {
5071 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
be663ab6 5072 /* skip as we already checked the command queue */
46bc8d4b 5073 if (cnt == il->cmd_queue)
be663ab6 5074 continue;
46bc8d4b 5075 if (il_check_stuck_queue(il, cnt))
be663ab6
WYG		 5076 return;
5077 }
5078 }
5079
e7392364
SG		 5080 mod_timer(&il->watchdog,
5081 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 5082}
e2ebc833 5083EXPORT_SYMBOL(il_bg_watchdog);
be663ab6 5084
e7392364
SG		 5085void
5086il_setup_watchdog(struct il_priv *il)
be663ab6 5087{
46bc8d4b 5088 unsigned int timeout = il->cfg->base_params->wd_timeout;
be663ab6
WYG		 5089
5090 if (timeout)
46bc8d4b 5091 mod_timer(&il->watchdog,
e2ebc833 5092 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 5093 else
46bc8d4b 5094 del_timer(&il->watchdog);
be663ab6 5095}
e2ebc833 5096EXPORT_SYMBOL(il_setup_watchdog);
be663ab6
WYG		 5097
5098/*
5099 * extended beacon time format
5100 * time in usec will be changed into a 32-bit value in extended:internal format
5101 * the extended part is the beacon counts
5102 * the internal part is the time in usec within one beacon interval
5103 */
5104u32
e7392364 5105il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
be663ab6
WYG		 5106{
5107 u32 quot;
5108 u32 rem;
5109 u32 interval = beacon_interval * TIME_UNIT;
5110
5111 if (!interval || !usec)
5112 return 0;
5113
e7392364
SG		 5114 quot =
5115 (usec /
5116 interval) & (il_beacon_time_mask_high(il,
5117 il->hw_params.
5118 beacon_time_tsf_bits) >> il->
5119 hw_params.beacon_time_tsf_bits);
5120 rem =
5121 (usec % interval) & il_beacon_time_mask_low(il,
5122 il->hw_params.
5123 beacon_time_tsf_bits);
be663ab6 5124
46bc8d4b 5125 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
be663ab6 5126}
e2ebc833 5127EXPORT_SYMBOL(il_usecs_to_beacons);
be663ab6
WYG		 5128
5129/* base is usually what we get from ucode with each received frame,
5130 * the same as HW timer counter counting down
5131 */
e7392364 5132__le32
1722f8e1 5133il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
e7392364 5134 u32 beacon_interval)
be663ab6 5135{
46bc8d4b 5136 u32 base_low = base & il_beacon_time_mask_low(il,
e7392364
SG		 5137 il->hw_params.
5138 beacon_time_tsf_bits);
46bc8d4b 5139 u32 addon_low = addon & il_beacon_time_mask_low(il,
e7392364
SG		 5140 il->hw_params.
5141 beacon_time_tsf_bits);
be663ab6 5142 u32 interval = beacon_interval * TIME_UNIT;
46bc8d4b 5143 u32 res = (base & il_beacon_time_mask_high(il,
e7392364
SG		 5144 il->hw_params.
5145 beacon_time_tsf_bits)) +
5146 (addon & il_beacon_time_mask_high(il,
5147 il->hw_params.
5148 beacon_time_tsf_bits));
be663ab6
WYG		 5149
5150 if (base_low > addon_low)
5151 res += base_low - addon_low;
5152 else if (base_low < addon_low) {
5153 res += interval + base_low - addon_low;
46bc8d4b 5154 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6 5155 } else
46bc8d4b 5156 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6
WYG		 5157
5158 return cpu_to_le32(res);
5159}
e2ebc833 5160EXPORT_SYMBOL(il_add_beacon_time);
be663ab6
WYG		 5161
5162#ifdef CONFIG_PM
5163
e7392364
SG		 5164int
5165il_pci_suspend(struct device *device)
be663ab6
WYG		 5166{
5167 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5168 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5169
5170 /*
5171 * This function is called when system goes into suspend state
e2ebc833
SG		 5172 * mac80211 will call il_mac_stop() from the mac80211 suspend function
5173 * first but since il_mac_stop() has no knowledge of who the caller is,
be663ab6
WYG		 5174 * it will not call apm_ops.stop() to stop the DMA operation.
5175 * Calling apm_ops.stop here to make sure we stop the DMA.
5176 */
46bc8d4b 5177 il_apm_stop(il);
be663ab6
WYG		 5178
5179 return 0;
5180}
e2ebc833 5181EXPORT_SYMBOL(il_pci_suspend);
be663ab6 5182
e7392364
SG		 5183int
5184il_pci_resume(struct device *device)
be663ab6
WYG		 5185{
5186 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5187 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5188 bool hw_rfkill = false;
5189
5190 /*
5191 * We disable the RETRY_TIMEOUT register (0x41) to keep
5192 * PCI Tx retries from interfering with C3 CPU state.
5193 */
5194 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
5195
46bc8d4b 5196 il_enable_interrupts(il);
be663ab6 5197
e7392364 5198 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 5199 hw_rfkill = true;
5200
5201 if (hw_rfkill)
a6766ccd 5202 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 5203 else
a6766ccd 5204 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 5205
46bc8d4b 5206 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
be663ab6
WYG		 5207
5208 return 0;
5209}
e2ebc833 5210EXPORT_SYMBOL(il_pci_resume);
be663ab6 5211
e2ebc833
SG		 5212const struct dev_pm_ops il_pm_ops = {
5213 .suspend = il_pci_suspend,
5214 .resume = il_pci_resume,
5215 .freeze = il_pci_suspend,
5216 .thaw = il_pci_resume,
5217 .poweroff = il_pci_suspend,
5218 .restore = il_pci_resume,
be663ab6 5219};
e2ebc833 5220EXPORT_SYMBOL(il_pm_ops);
be663ab6
WYG		 5221
5222#endif /* CONFIG_PM */
5223
5224static void
46bc8d4b 5225il_update_qos(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 5226{
a6766ccd 5227 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5228 return;
5229
5230 if (!ctx->is_active)
5231 return;
5232
8d44f2bd 5233 il->qos_data.def_qos_parm.qos_flags = 0;
be663ab6 5234
8d44f2bd
SG		 5235 if (il->qos_data.qos_active)
5236 il->qos_data.def_qos_parm.qos_flags |=
e7392364 5237 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
be663ab6
WYG		 5238
5239 if (ctx->ht.enabled)
8d44f2bd 5240 il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
be663ab6 5241
58de00a4 5242 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
8d44f2bd 5243 il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
be663ab6 5244
b96ed60c 5245 il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
8d44f2bd 5246 &il->qos_data.def_qos_parm, NULL);
be663ab6
WYG		 5247}
5248
5249/**
e2ebc833 5250 * il_mac_config - mac80211 config callback
be663ab6 5251 */
e7392364
SG		 5252int
5253il_mac_config(struct ieee80211_hw *hw, u32 changed)
be663ab6 5254{
46bc8d4b 5255 struct il_priv *il = hw->priv;
e2ebc833 5256 const struct il_channel_info *ch_info;
be663ab6
WYG		 5257 struct ieee80211_conf *conf = &hw->conf;
5258 struct ieee80211_channel *channel = conf->channel;
46bc8d4b 5259 struct il_ht_config *ht_conf = &il->current_ht_config;
17d6e557 5260 struct il_rxon_context *ctx = &il->ctx;
be663ab6
WYG		 5261 unsigned long flags = 0;
5262 int ret = 0;
5263 u16 ch;
5264 int scan_active = 0;
7c2cde2e 5265 bool ht_changed = false;
be663ab6 5266
46bc8d4b 5267 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG		 5268 return -EOPNOTSUPP;
5269
46bc8d4b 5270 mutex_lock(&il->mutex);
be663ab6 5271
e7392364
SG		 5272 D_MAC80211("enter to channel %d changed 0x%X\n", channel->hw_value,
5273 changed);
be663ab6 5274
a6766ccd 5275 if (unlikely(test_bit(S_SCANNING, &il->status))) {
be663ab6 5276 scan_active = 1;
58de00a4 5277 D_MAC80211("scan active\n");
be663ab6
WYG		 5278 }
5279
e7392364
SG		 5280 if (changed &
5281 (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
be663ab6 5282 /* mac80211 uses static for non-HT which is what we want */
46bc8d4b 5283 il->current_ht_config.smps = conf->smps_mode;
be663ab6
WYG		 5284
5285 /*
5286 * Recalculate chain counts.
5287 *
5288 * If monitor mode is enabled then mac80211 will
5289 * set up the SM PS mode to OFF if an HT channel is
5290 * configured.
5291 */
46bc8d4b 5292 if (il->cfg->ops->hcmd->set_rxon_chain)
17d6e557 5293 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
be663ab6
WYG		 5294 }
5295
5296 /* during scanning mac80211 will delay channel setting until
5297 * scan finish with changed = 0
5298 */
5299 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
17d6e557 5300
be663ab6
WYG		 5301 if (scan_active)
5302 goto set_ch_out;
5303
5304 ch = channel->hw_value;
46bc8d4b 5305 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5306 if (!il_is_channel_valid(ch_info)) {
58de00a4 5307 D_MAC80211("leave - invalid channel\n");
be663ab6
WYG		 5308 ret = -EINVAL;
5309 goto set_ch_out;
5310 }
5311
46bc8d4b 5312 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
e2ebc833 5313 !il_is_channel_ibss(ch_info)) {
58de00a4 5314 D_MAC80211("leave - not IBSS channel\n");
eb85de3f
SG		 5315 ret = -EINVAL;
5316 goto set_ch_out;
5317 }
5318
46bc8d4b 5319 spin_lock_irqsave(&il->lock, flags);
be663ab6 5320
17d6e557
SG		 5321 /* Configure HT40 channels */
5322 if (ctx->ht.enabled != conf_is_ht(conf)) {
5323 ctx->ht.enabled = conf_is_ht(conf);
5324 ht_changed = true;
5325 }
5326 if (ctx->ht.enabled) {
5327 if (conf_is_ht40_minus(conf)) {
5328 ctx->ht.extension_chan_offset =
e7392364 5329 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
17d6e557
SG		 5330 ctx->ht.is_40mhz = true;
5331 } else if (conf_is_ht40_plus(conf)) {
5332 ctx->ht.extension_chan_offset =
e7392364 5333 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
17d6e557
SG		 5334 ctx->ht.is_40mhz = true;
5335 } else {
5336 ctx->ht.extension_chan_offset =
e7392364 5337 IEEE80211_HT_PARAM_CHA_SEC_NONE;
be663ab6 5338 ctx->ht.is_40mhz = false;
17d6e557
SG		 5339 }
5340 } else
5341 ctx->ht.is_40mhz = false;
be663ab6 5342
17d6e557
SG		 5343 /*
5344 * Default to no protection. Protection mode will
5345 * later be set from BSS config in il_ht_conf
5346 */
e7392364 5347 ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
be663ab6 5348
17d6e557
SG		 5349 /* if we are switching from ht to 2.4 clear flags
5350 * from any ht related info since 2.4 does not
5351 * support ht */
c8b03958
SG		 5352 if ((le16_to_cpu(il->staging.channel) != ch))
5353 il->staging.flags = 0;
be663ab6 5354
17d6e557
SG		 5355 il_set_rxon_channel(il, channel, ctx);
5356 il_set_rxon_ht(il, ht_conf);
be663ab6 5357
e7392364 5358 il_set_flags_for_band(il, ctx, channel->band, ctx->vif);
be663ab6 5359
46bc8d4b 5360 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5361
46bc8d4b 5362 if (il->cfg->ops->legacy->update_bcast_stations)
e7392364 5363 ret = il->cfg->ops->legacy->update_bcast_stations(il);
be663ab6 5364
e7392364 5365set_ch_out:
be663ab6
WYG		 5366 /* The list of supported rates and rate mask can be different
5367 * for each band; since the band may have changed, reset
5368 * the rate mask to what mac80211 lists */
46bc8d4b 5369 il_set_rate(il);
be663ab6
WYG		 5370 }
5371
e7392364 5372 if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
46bc8d4b 5373 ret = il_power_update_mode(il, false);
be663ab6 5374 if (ret)
58de00a4 5375 D_MAC80211("Error setting sleep level\n");
be663ab6
WYG		 5376 }
5377
5378 if (changed & IEEE80211_CONF_CHANGE_POWER) {
e7392364
SG		 5379 D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
5380 conf->power_level);
be663ab6 5381
46bc8d4b 5382 il_set_tx_power(il, conf->power_level, false);
be663ab6
WYG		 5383 }
5384
46bc8d4b 5385 if (!il_is_ready(il)) {
58de00a4 5386 D_MAC80211("leave - not ready\n");
be663ab6
WYG		 5387 goto out;
5388 }
5389
5390 if (scan_active)
5391 goto out;
5392
c8b03958 5393 if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
17d6e557
SG		 5394 il_commit_rxon(il, ctx);
5395 else
5396 D_INFO("Not re-sending same RXON configuration.\n");
5397 if (ht_changed)
5398 il_update_qos(il, ctx);
be663ab6
WYG		 5399
5400out:
58de00a4 5401 D_MAC80211("leave\n");
46bc8d4b 5402 mutex_unlock(&il->mutex);
be663ab6
WYG		 5403 return ret;
5404}
e2ebc833 5405EXPORT_SYMBOL(il_mac_config);
be663ab6 5406
e7392364
SG		 5407void
5408il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5409{
46bc8d4b 5410 struct il_priv *il = hw->priv;
be663ab6 5411 unsigned long flags;
7c2cde2e 5412 struct il_rxon_context *ctx = &il->ctx;
be663ab6 5413
46bc8d4b 5414 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG		 5415 return;
5416
46bc8d4b 5417 mutex_lock(&il->mutex);
58de00a4 5418 D_MAC80211("enter\n");
be663ab6 5419
46bc8d4b
SG		 5420 spin_lock_irqsave(&il->lock, flags);
5421 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
5422 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5423
46bc8d4b 5424 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5425
5426 /* new association get rid of ibss beacon skb */
46bc8d4b
SG		 5427 if (il->beacon_skb)
5428 dev_kfree_skb(il->beacon_skb);
be663ab6 5429
46bc8d4b 5430 il->beacon_skb = NULL;
be663ab6 5431
46bc8d4b 5432 il->timestamp = 0;
be663ab6 5433
46bc8d4b 5434 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5435
46bc8d4b
SG		 5436 il_scan_cancel_timeout(il, 100);
5437 if (!il_is_ready_rf(il)) {
58de00a4 5438 D_MAC80211("leave - not ready\n");
46bc8d4b 5439 mutex_unlock(&il->mutex);
be663ab6
WYG		 5440 return;
5441 }
5442
5443 /* we are restarting association process
5444 * clear RXON_FILTER_ASSOC_MSK bit
5445 */
c8b03958 5446 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
46bc8d4b 5447 il_commit_rxon(il, ctx);
be663ab6 5448
46bc8d4b 5449 il_set_rate(il);
be663ab6 5450
46bc8d4b 5451 mutex_unlock(&il->mutex);
be663ab6 5452
58de00a4 5453 D_MAC80211("leave\n");
be663ab6 5454}
e2ebc833 5455EXPORT_SYMBOL(il_mac_reset_tsf);
be663ab6 5456
e7392364
SG		 5457static void
5458il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5459{
46bc8d4b 5460 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5461 struct ieee80211_sta *sta;
5462 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
e2ebc833 5463 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 5464
58de00a4 5465 D_ASSOC("enter:\n");
be663ab6
WYG		 5466
5467 if (!ctx->ht.enabled)
5468 return;
5469
5470 ctx->ht.protection =
e7392364 5471 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
be663ab6 5472 ctx->ht.non_gf_sta_present =
e7392364
SG		 5473 !!(bss_conf->
5474 ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
be663ab6
WYG		 5475
5476 ht_conf->single_chain_sufficient = false;
5477
5478 switch (vif->type) {
5479 case NL80211_IFTYPE_STATION:
5480 rcu_read_lock();
5481 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5482 if (sta) {
5483 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5484 int maxstreams;
5485
e7392364
SG		 5486 maxstreams =
5487 (ht_cap->mcs.
5488 tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5489 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
be663ab6
WYG		 5490 maxstreams += 1;
5491
232913b5
SG		 5492 if (ht_cap->mcs.rx_mask[1] == 0 &&
5493 ht_cap->mcs.rx_mask[2] == 0)
be663ab6
WYG		 5494 ht_conf->single_chain_sufficient = true;
5495 if (maxstreams <= 1)
5496 ht_conf->single_chain_sufficient = true;
5497 } else {
5498 /*
5499 * If at all, this can only happen through a race
5500 * when the AP disconnects us while we're still
5501 * setting up the connection, in that case mac80211
5502 * will soon tell us about that.
5503 */
5504 ht_conf->single_chain_sufficient = true;
5505 }
5506 rcu_read_unlock();
5507 break;
5508 case NL80211_IFTYPE_ADHOC:
5509 ht_conf->single_chain_sufficient = true;
5510 break;
5511 default:
5512 break;
5513 }
5514
58de00a4 5515 D_ASSOC("leave\n");
be663ab6
WYG		 5516}
5517
e7392364
SG		 5518static inline void
5519il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5520{
e2ebc833 5521 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6
WYG		 5522
5523 /*
5524 * inform the ucode that there is no longer an
5525 * association and that no more packets should be
5526 * sent
5527 */
c8b03958
SG		 5528 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5529 il->staging.assoc_id = 0;
46bc8d4b 5530 il_commit_rxon(il, ctx);
be663ab6
WYG		 5531}
5532
e7392364
SG		 5533static void
5534il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5535{
46bc8d4b 5536 struct il_priv *il = hw->priv;
be663ab6
WYG		 5537 unsigned long flags;
5538 __le64 timestamp;
5539 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5540
5541 if (!skb)
5542 return;
5543
58de00a4 5544 D_MAC80211("enter\n");
be663ab6 5545
46bc8d4b 5546 lockdep_assert_held(&il->mutex);
be663ab6 5547
46bc8d4b 5548 if (!il->beacon_ctx) {
9406f797 5549 IL_ERR("update beacon but no beacon context!\n");
be663ab6
WYG		 5550 dev_kfree_skb(skb);
5551 return;
5552 }
5553
46bc8d4b 5554 spin_lock_irqsave(&il->lock, flags);
be663ab6 5555
46bc8d4b
SG		 5556 if (il->beacon_skb)
5557 dev_kfree_skb(il->beacon_skb);
be663ab6 5558
46bc8d4b 5559 il->beacon_skb = skb;
be663ab6
WYG		 5560
5561 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
46bc8d4b 5562 il->timestamp = le64_to_cpu(timestamp);
be663ab6 5563
58de00a4 5564 D_MAC80211("leave\n");
46bc8d4b 5565 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5566
46bc8d4b 5567 if (!il_is_ready_rf(il)) {
58de00a4 5568 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 5569 return;
5570 }
5571
46bc8d4b 5572 il->cfg->ops->legacy->post_associate(il);
be663ab6
WYG		 5573}
5574
e7392364
SG		 5575void
5576il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5577 struct ieee80211_bss_conf *bss_conf, u32 changes)
be663ab6 5578{
46bc8d4b 5579 struct il_priv *il = hw->priv;
e2ebc833 5580 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6
WYG		 5581 int ret;
5582
46bc8d4b 5583 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG		 5584 return;
5585
58de00a4 5586 D_MAC80211("changes = 0x%X\n", changes);
be663ab6 5587
46bc8d4b 5588 mutex_lock(&il->mutex);
be663ab6 5589
46bc8d4b
SG		 5590 if (!il_is_alive(il)) {
5591 mutex_unlock(&il->mutex);
28a6e577
SG		 5592 return;
5593 }
5594
be663ab6
WYG		 5595 if (changes & BSS_CHANGED_QOS) {
5596 unsigned long flags;
5597
46bc8d4b 5598 spin_lock_irqsave(&il->lock, flags);
8d44f2bd 5599 il->qos_data.qos_active = bss_conf->qos;
46bc8d4b
SG		 5600 il_update_qos(il, ctx);
5601 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5602 }
5603
5604 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5605 /*
5606 * the add_interface code must make sure we only ever
5607 * have a single interface that could be beaconing at
5608 * any time.
5609 */
5610 if (vif->bss_conf.enable_beacon)
46bc8d4b 5611 il->beacon_ctx = ctx;
be663ab6 5612 else
46bc8d4b 5613 il->beacon_ctx = NULL;
be663ab6
WYG		 5614 }
5615
5616 if (changes & BSS_CHANGED_BSSID) {
58de00a4 5617 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
be663ab6
WYG		 5618
5619 /*
5620 * If there is currently a HW scan going on in the
5621 * background then we need to cancel it else the RXON
5622 * below/in post_associate will fail.
5623 */
46bc8d4b 5624 if (il_scan_cancel_timeout(il, 100)) {
e7392364
SG		 5625 IL_WARN("Aborted scan still in progress after 100ms\n");
5626 D_MAC80211("leaving - scan abort failed.\n");
46bc8d4b 5627 mutex_unlock(&il->mutex);
be663ab6
WYG		 5628 return;
5629 }
5630
5631 /* mac80211 only sets assoc when in STATION mode */
5632 if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
c8b03958 5633 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5634 ETH_ALEN);
be663ab6
WYG		 5635
5636 /* currently needed in a few places */
46bc8d4b 5637 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
be663ab6 5638 } else {
c8b03958 5639 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5640 }
5641
5642 }
5643
5644 /*
5645 * This needs to be after setting the BSSID in case
5646 * mac80211 decides to do both changes at once because
5647 * it will invoke post_associate.
5648 */
232913b5 5649 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
e2ebc833 5650 il_beacon_update(hw, vif);
be663ab6
WYG		 5651
5652 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
e7392364 5653 D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
be663ab6 5654 if (bss_conf->use_short_preamble)
c8b03958 5655 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 5656 else
c8b03958 5657 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 5658 }
5659
5660 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
e7392364 5661 D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
232913b5 5662 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
c8b03958 5663 il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5664 else
c8b03958 5665 il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5666 if (bss_conf->use_cts_prot)
c8b03958 5667 il->staging.flags |= RXON_FLG_SELF_CTS_EN;
be663ab6 5668 else
c8b03958 5669 il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
be663ab6
WYG		 5670 }
5671
5672 if (changes & BSS_CHANGED_BASIC_RATES) {
5673 /* XXX use this information
5674 *
e2ebc833 5675 * To do that, remove code from il_set_rate() and put something
be663ab6
WYG		 5676 * like this here:
5677 *
e7392364 5678 if (A-band)
c8b03958 5679 il->staging.ofdm_basic_rates =
e7392364
SG		 5680 bss_conf->basic_rates;
5681 else
c8b03958 5682 il->staging.ofdm_basic_rates =
e7392364 5683 bss_conf->basic_rates >> 4;
c8b03958 5684 il->staging.cck_basic_rates =
e7392364 5685 bss_conf->basic_rates & 0xF;
be663ab6
WYG		 5686 */
5687 }
5688
5689 if (changes & BSS_CHANGED_HT) {
46bc8d4b 5690 il_ht_conf(il, vif);
be663ab6 5691
46bc8d4b
SG		 5692 if (il->cfg->ops->hcmd->set_rxon_chain)
5693 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6
WYG		 5694 }
5695
5696 if (changes & BSS_CHANGED_ASSOC) {
58de00a4 5697 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
be663ab6 5698 if (bss_conf->assoc) {
46bc8d4b 5699 il->timestamp = bss_conf->timestamp;
be663ab6 5700
46bc8d4b
SG		 5701 if (!il_is_rfkill(il))
5702 il->cfg->ops->legacy->post_associate(il);
be663ab6 5703 } else
46bc8d4b 5704 il_set_no_assoc(il, vif);
be663ab6
WYG		 5705 }
5706
c8b03958 5707 if (changes && il_is_associated(il) && bss_conf->aid) {
e7392364 5708 D_MAC80211("Changes (%#x) while associated\n", changes);
46bc8d4b 5709 ret = il_send_rxon_assoc(il, ctx);
be663ab6
WYG		 5710 if (!ret) {
5711 /* Sync active_rxon with latest change. */
c8b03958 5712 memcpy((void *)&il->active, &il->staging,
e7392364 5713 sizeof(struct il_rxon_cmd));
be663ab6
WYG		 5714 }
5715 }
5716
5717 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5718 if (vif->bss_conf.enable_beacon) {
c8b03958 5719 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5720 ETH_ALEN);
46bc8d4b
SG		 5721 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
5722 il->cfg->ops->legacy->config_ap(il);
be663ab6 5723 } else
46bc8d4b 5724 il_set_no_assoc(il, vif);
be663ab6
WYG		 5725 }
5726
5727 if (changes & BSS_CHANGED_IBSS) {
e7392364
SG		 5728 ret =
5729 il->cfg->ops->legacy->manage_ibss_station(il, vif,
5730 bss_conf->
5731 ibss_joined);
be663ab6 5732 if (ret)
9406f797 5733 IL_ERR("failed to %s IBSS station %pM\n",
e7392364
SG		 5734 bss_conf->ibss_joined ? "add" : "remove",
5735 bss_conf->bssid);
be663ab6
WYG		 5736 }
5737
46bc8d4b 5738 mutex_unlock(&il->mutex);
be663ab6 5739
58de00a4 5740 D_MAC80211("leave\n");
be663ab6 5741}
e2ebc833 5742EXPORT_SYMBOL(il_mac_bss_info_changed);
be663ab6 5743
e7392364
SG		 5744irqreturn_t
5745il_isr(int irq, void *data)
be663ab6 5746{
46bc8d4b 5747 struct il_priv *il = data;
be663ab6
WYG		 5748 u32 inta, inta_mask;
5749 u32 inta_fh;
5750 unsigned long flags;
46bc8d4b 5751 if (!il)
be663ab6
WYG		 5752 return IRQ_NONE;
5753
46bc8d4b 5754 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5755
5756 /* Disable (but don't clear!) interrupts here to avoid
5757 * back-to-back ISRs and sporadic interrupts from our NIC.
5758 * If we have something to service, the tasklet will re-enable ints.
5759 * If we *don't* have something, we'll re-enable before leaving here. */
e7392364 5760 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
841b2cca 5761 _il_wr(il, CSR_INT_MASK, 0x00000000);
be663ab6
WYG		 5762
5763 /* Discover which interrupts are active/pending */
841b2cca
SG		 5764 inta = _il_rd(il, CSR_INT);
5765 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
be663ab6
WYG		 5766
5767 /* Ignore interrupt if there's nothing in NIC to service.
5768 * This may be due to IRQ shared with another device,
5769 * or due to sporadic interrupts thrown from our NIC. */
5770 if (!inta && !inta_fh) {
e7392364 5771 D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
be663ab6
WYG		 5772 goto none;
5773 }
5774
232913b5 5775 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
be663ab6
WYG		 5776 /* Hardware disappeared. It might have already raised
5777 * an interrupt */
9406f797 5778 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
be663ab6
WYG		 5779 goto unplugged;
5780 }
5781
e7392364
SG		 5782 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
5783 inta_fh);
be663ab6
WYG		 5784
5785 inta &= ~CSR_INT_BIT_SCD;
5786
e2ebc833 5787 /* il_irq_tasklet() will service interrupts and re-enable them */
be663ab6 5788 if (likely(inta || inta_fh))
46bc8d4b 5789 tasklet_schedule(&il->irq_tasklet);
be663ab6
WYG		 5790
5791unplugged:
46bc8d4b 5792 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5793 return IRQ_HANDLED;
5794
5795none:
5796 /* re-enable interrupts here since we don't have anything to service. */
93fd74e3 5797 /* only Re-enable if disabled by irq */
a6766ccd 5798 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b
SG		 5799 il_enable_interrupts(il);
5800 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5801 return IRQ_NONE;
5802}
e2ebc833 5803EXPORT_SYMBOL(il_isr);
be663ab6
WYG		 5804
5805/*
e2ebc833 5806 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
be663ab6
WYG		 5807 * function.
5808 */
e7392364
SG		 5809void
5810il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 5811 __le16 fc, __le32 *tx_flags)
be663ab6
WYG		 5812{
5813 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5814 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5815 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5816 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5817
5818 if (!ieee80211_is_mgmt(fc))
5819 return;
5820
5821 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5822 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5823 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5824 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5825 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5826 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5827 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5828 break;
5829 }
e7392364
SG		 5830 } else if (info->control.rates[0].
5831 flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
be663ab6
WYG		 5832 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5833 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5834 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5835 }
5836}
e2ebc833 5837EXPORT_SYMBOL(il_tx_cmd_protection);
Linux kernel - Deliverables
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