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iwlegacy: rename iwl-core.h to common.h
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.c
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be663ab6
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
0cdc2136
SG		 34#include <linux/types.h>
35#include <linux/lockdep.h>
36#include <linux/init.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/skbuff.h>
be663ab6
WYG		 41#include <net/mac80211.h>
42
43#include "iwl-eeprom.h"
44#include "iwl-dev.h"
45#include "iwl-debug.h"
98613be0 46#include "common.h"
be663ab6
WYG		 47#include "iwl-io.h"
48#include "iwl-power.h"
49#include "iwl-sta.h"
50#include "iwl-helpers.h"
51
0cdc2136
SG		 52const char *il_get_cmd_string(u8 cmd)
53{
54 switch (cmd) {
55 IL_CMD(N_ALIVE);
56 IL_CMD(N_ERROR);
57 IL_CMD(C_RXON);
58 IL_CMD(C_RXON_ASSOC);
59 IL_CMD(C_QOS_PARAM);
60 IL_CMD(C_RXON_TIMING);
61 IL_CMD(C_ADD_STA);
62 IL_CMD(C_REM_STA);
63 IL_CMD(C_WEPKEY);
64 IL_CMD(N_3945_RX);
65 IL_CMD(C_TX);
66 IL_CMD(C_RATE_SCALE);
67 IL_CMD(C_LEDS);
68 IL_CMD(C_TX_LINK_QUALITY_CMD);
69 IL_CMD(C_CHANNEL_SWITCH);
70 IL_CMD(N_CHANNEL_SWITCH);
71 IL_CMD(C_SPECTRUM_MEASUREMENT);
72 IL_CMD(N_SPECTRUM_MEASUREMENT);
73 IL_CMD(C_POWER_TBL);
74 IL_CMD(N_PM_SLEEP);
75 IL_CMD(N_PM_DEBUG_STATS);
76 IL_CMD(C_SCAN);
77 IL_CMD(C_SCAN_ABORT);
78 IL_CMD(N_SCAN_START);
79 IL_CMD(N_SCAN_RESULTS);
80 IL_CMD(N_SCAN_COMPLETE);
81 IL_CMD(N_BEACON);
82 IL_CMD(C_TX_BEACON);
83 IL_CMD(C_TX_PWR_TBL);
84 IL_CMD(C_BT_CONFIG);
85 IL_CMD(C_STATS);
86 IL_CMD(N_STATS);
87 IL_CMD(N_CARD_STATE);
88 IL_CMD(N_MISSED_BEACONS);
89 IL_CMD(C_CT_KILL_CONFIG);
90 IL_CMD(C_SENSITIVITY);
91 IL_CMD(C_PHY_CALIBRATION);
92 IL_CMD(N_RX_PHY);
93 IL_CMD(N_RX_MPDU);
94 IL_CMD(N_RX);
95 IL_CMD(N_COMPRESSED_BA);
96 default:
97 return "UNKNOWN";
98
99 }
100}
101EXPORT_SYMBOL(il_get_cmd_string);
102
103#define HOST_COMPLETE_TIMEOUT (HZ / 2)
104
105static void il_generic_cmd_callback(struct il_priv *il,
106 struct il_device_cmd *cmd,
107 struct il_rx_pkt *pkt)
108{
109 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
110 IL_ERR("Bad return from %s (0x%08X)\n",
111 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
112 return;
113 }
114
115#ifdef CONFIG_IWLEGACY_DEBUG
116 switch (cmd->hdr.cmd) {
117 case C_TX_LINK_QUALITY_CMD:
118 case C_SENSITIVITY:
119 D_HC_DUMP("back from %s (0x%08X)\n",
120 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
121 break;
122 default:
123 D_HC("back from %s (0x%08X)\n",
124 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
125 }
126#endif
127}
128
129static int
130il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
131{
132 int ret;
133
134 BUG_ON(!(cmd->flags & CMD_ASYNC));
135
136 /* An asynchronous command can not expect an SKB to be set. */
137 BUG_ON(cmd->flags & CMD_WANT_SKB);
138
139 /* Assign a generic callback if one is not provided */
140 if (!cmd->callback)
141 cmd->callback = il_generic_cmd_callback;
142
143 if (test_bit(S_EXIT_PENDING, &il->status))
144 return -EBUSY;
145
146 ret = il_enqueue_hcmd(il, cmd);
147 if (ret < 0) {
148 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
149 il_get_cmd_string(cmd->id), ret);
150 return ret;
151 }
152 return 0;
153}
154
155int il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
156{
157 int cmd_idx;
158 int ret;
159
160 lockdep_assert_held(&il->mutex);
161
162 BUG_ON(cmd->flags & CMD_ASYNC);
163
164 /* A synchronous command can not have a callback set. */
165 BUG_ON(cmd->callback);
166
167 D_INFO("Attempting to send sync command %s\n",
168 il_get_cmd_string(cmd->id));
169
170 set_bit(S_HCMD_ACTIVE, &il->status);
171 D_INFO("Setting HCMD_ACTIVE for command %s\n",
172 il_get_cmd_string(cmd->id));
173
174 cmd_idx = il_enqueue_hcmd(il, cmd);
175 if (cmd_idx < 0) {
176 ret = cmd_idx;
177 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
178 il_get_cmd_string(cmd->id), ret);
179 goto out;
180 }
181
182 ret = wait_event_timeout(il->wait_command_queue,
183 !test_bit(S_HCMD_ACTIVE, &il->status),
184 HOST_COMPLETE_TIMEOUT);
185 if (!ret) {
186 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
187 IL_ERR(
188 "Error sending %s: time out after %dms.\n",
189 il_get_cmd_string(cmd->id),
190 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
191
192 clear_bit(S_HCMD_ACTIVE, &il->status);
193 D_INFO(
194 "Clearing HCMD_ACTIVE for command %s\n",
195 il_get_cmd_string(cmd->id));
196 ret = -ETIMEDOUT;
197 goto cancel;
198 }
199 }
200
201 if (test_bit(S_RF_KILL_HW, &il->status)) {
202 IL_ERR("Command %s aborted: RF KILL Switch\n",
203 il_get_cmd_string(cmd->id));
204 ret = -ECANCELED;
205 goto fail;
206 }
207 if (test_bit(S_FW_ERROR, &il->status)) {
208 IL_ERR("Command %s failed: FW Error\n",
209 il_get_cmd_string(cmd->id));
210 ret = -EIO;
211 goto fail;
212 }
213 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
214 IL_ERR("Error: Response NULL in '%s'\n",
215 il_get_cmd_string(cmd->id));
216 ret = -EIO;
217 goto cancel;
218 }
219
220 ret = 0;
221 goto out;
222
223cancel:
224 if (cmd->flags & CMD_WANT_SKB) {
225 /*
226 * Cancel the CMD_WANT_SKB flag for the cmd in the
227 * TX cmd queue. Otherwise in case the cmd comes
228 * in later, it will possibly set an invalid
229 * address (cmd->meta.source).
230 */
231 il->txq[il->cmd_queue].meta[cmd_idx].flags &=
232 ~CMD_WANT_SKB;
233 }
234fail:
235 if (cmd->reply_page) {
236 il_free_pages(il, cmd->reply_page);
237 cmd->reply_page = 0;
238 }
239out:
240 return ret;
241}
242EXPORT_SYMBOL(il_send_cmd_sync);
243
244int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
245{
246 if (cmd->flags & CMD_ASYNC)
247 return il_send_cmd_async(il, cmd);
248
249 return il_send_cmd_sync(il, cmd);
250}
251EXPORT_SYMBOL(il_send_cmd);
252
253int
254il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
255{
256 struct il_host_cmd cmd = {
257 .id = id,
258 .len = len,
259 .data = data,
260 };
261
262 return il_send_cmd_sync(il, &cmd);
263}
264EXPORT_SYMBOL(il_send_cmd_pdu);
265
266int il_send_cmd_pdu_async(struct il_priv *il,
267 u8 id, u16 len, const void *data,
268 void (*callback)(struct il_priv *il,
269 struct il_device_cmd *cmd,
270 struct il_rx_pkt *pkt))
271{
272 struct il_host_cmd cmd = {
273 .id = id,
274 .len = len,
275 .data = data,
276 };
277
278 cmd.flags |= CMD_ASYNC;
279 cmd.callback = callback;
280
281 return il_send_cmd_async(il, &cmd);
282}
283EXPORT_SYMBOL(il_send_cmd_pdu_async);
284
285/* default: IL_LED_BLINK(0) using blinking idx table */
286static int led_mode;
287module_param(led_mode, int, S_IRUGO);
288MODULE_PARM_DESC(led_mode, "0=system default, "
289 "1=On(RF On)/Off(RF Off), 2=blinking");
290
291/* Throughput OFF time(ms) ON time (ms)
292 * >300 25 25
293 * >200 to 300 40 40
294 * >100 to 200 55 55
295 * >70 to 100 65 65
296 * >50 to 70 75 75
297 * >20 to 50 85 85
298 * >10 to 20 95 95
299 * >5 to 10 110 110
300 * >1 to 5 130 130
301 * >0 to 1 167 167
302 * <=0 SOLID ON
303 */
304static const struct ieee80211_tpt_blink il_blink[] = {
305 { .throughput = 0, .blink_time = 334 },
306 { .throughput = 1 * 1024 - 1, .blink_time = 260 },
307 { .throughput = 5 * 1024 - 1, .blink_time = 220 },
308 { .throughput = 10 * 1024 - 1, .blink_time = 190 },
309 { .throughput = 20 * 1024 - 1, .blink_time = 170 },
310 { .throughput = 50 * 1024 - 1, .blink_time = 150 },
311 { .throughput = 70 * 1024 - 1, .blink_time = 130 },
312 { .throughput = 100 * 1024 - 1, .blink_time = 110 },
313 { .throughput = 200 * 1024 - 1, .blink_time = 80 },
314 { .throughput = 300 * 1024 - 1, .blink_time = 50 },
315};
316
317/*
318 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
319 * Led blink rate analysis showed an average deviation of 0% on 3945,
320 * 5% on 4965 HW.
321 * Need to compensate on the led on/off time per HW according to the deviation
322 * to achieve the desired led frequency
323 * The calculation is: (100-averageDeviation)/100 * blinkTime
324 * For code efficiency the calculation will be:
325 * compensation = (100 - averageDeviation) * 64 / 100
326 * NewBlinkTime = (compensation * BlinkTime) / 64
327 */
328static inline u8 il_blink_compensation(struct il_priv *il,
329 u8 time, u16 compensation)
330{
331 if (!compensation) {
332 IL_ERR("undefined blink compensation: "
333 "use pre-defined blinking time\n");
334 return time;
335 }
336
337 return (u8)((time * compensation) >> 6);
338}
339
340/* Set led pattern command */
341static int il_led_cmd(struct il_priv *il,
342 unsigned long on,
343 unsigned long off)
344{
345 struct il_led_cmd led_cmd = {
346 .id = IL_LED_LINK,
347 .interval = IL_DEF_LED_INTRVL
348 };
349 int ret;
350
351 if (!test_bit(S_READY, &il->status))
352 return -EBUSY;
353
354 if (il->blink_on == on && il->blink_off == off)
355 return 0;
356
357 if (off == 0) {
358 /* led is SOLID_ON */
359 on = IL_LED_SOLID;
360 }
361
362 D_LED("Led blink time compensation=%u\n",
363 il->cfg->base_params->led_compensation);
364 led_cmd.on = il_blink_compensation(il, on,
365 il->cfg->base_params->led_compensation);
366 led_cmd.off = il_blink_compensation(il, off,
367 il->cfg->base_params->led_compensation);
368
369 ret = il->cfg->ops->led->cmd(il, &led_cmd);
370 if (!ret) {
371 il->blink_on = on;
372 il->blink_off = off;
373 }
374 return ret;
375}
376
377static void il_led_brightness_set(struct led_classdev *led_cdev,
378 enum led_brightness brightness)
379{
380 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
381 unsigned long on = 0;
382
383 if (brightness > 0)
384 on = IL_LED_SOLID;
385
386 il_led_cmd(il, on, 0);
387}
388
389static int il_led_blink_set(struct led_classdev *led_cdev,
390 unsigned long *delay_on,
391 unsigned long *delay_off)
392{
393 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
394
395 return il_led_cmd(il, *delay_on, *delay_off);
396}
397
398void il_leds_init(struct il_priv *il)
399{
400 int mode = led_mode;
401 int ret;
402
403 if (mode == IL_LED_DEFAULT)
404 mode = il->cfg->led_mode;
405
406 il->led.name = kasprintf(GFP_KERNEL, "%s-led",
407 wiphy_name(il->hw->wiphy));
408 il->led.brightness_set = il_led_brightness_set;
409 il->led.blink_set = il_led_blink_set;
410 il->led.max_brightness = 1;
411
412 switch (mode) {
413 case IL_LED_DEFAULT:
414 WARN_ON(1);
415 break;
416 case IL_LED_BLINK:
417 il->led.default_trigger =
418 ieee80211_create_tpt_led_trigger(il->hw,
419 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
420 il_blink, ARRAY_SIZE(il_blink));
421 break;
422 case IL_LED_RF_STATE:
423 il->led.default_trigger =
424 ieee80211_get_radio_led_name(il->hw);
425 break;
426 }
427
428 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
429 if (ret) {
430 kfree(il->led.name);
431 return;
432 }
433
434 il->led_registered = true;
435}
436EXPORT_SYMBOL(il_leds_init);
437
438void il_leds_exit(struct il_priv *il)
439{
440 if (!il->led_registered)
441 return;
442
443 led_classdev_unregister(&il->led);
444 kfree(il->led.name);
445}
446EXPORT_SYMBOL(il_leds_exit);
447
448/************************** EEPROM BANDS ****************************
449 *
450 * The il_eeprom_band definitions below provide the mapping from the
451 * EEPROM contents to the specific channel number supported for each
452 * band.
453 *
454 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
455 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
456 * The specific geography and calibration information for that channel
457 * is contained in the eeprom map itself.
458 *
459 * During init, we copy the eeprom information and channel map
460 * information into il->channel_info_24/52 and il->channel_map_24/52
461 *
462 * channel_map_24/52 provides the idx in the channel_info array for a
463 * given channel. We have to have two separate maps as there is channel
464 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
465 * band_2
466 *
467 * A value of 0xff stored in the channel_map indicates that the channel
468 * is not supported by the hardware at all.
469 *
470 * A value of 0xfe in the channel_map indicates that the channel is not
471 * valid for Tx with the current hardware. This means that
472 * while the system can tune and receive on a given channel, it may not
473 * be able to associate or transmit any frames on that
474 * channel. There is no corresponding channel information for that
475 * entry.
476 *
477 *********************************************************************/
478
479/* 2.4 GHz */
480const u8 il_eeprom_band_1[14] = {
481 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
482};
483
484/* 5.2 GHz bands */
485static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
486 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
487};
488
489static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
490 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
491};
492
493static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
494 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
495};
496
497static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
498 145, 149, 153, 157, 161, 165
499};
500
501static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
502 1, 2, 3, 4, 5, 6, 7
503};
504
505static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
506 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
507};
508
509/******************************************************************************
510 *
511 * EEPROM related functions
512 *
513******************************************************************************/
514
515static int il_eeprom_verify_signature(struct il_priv *il)
516{
517 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
518 int ret = 0;
519
520 D_EEPROM("EEPROM signature=0x%08x\n", gp);
521 switch (gp) {
522 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
523 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
524 break;
525 default:
526 IL_ERR("bad EEPROM signature,"
527 "EEPROM_GP=0x%08x\n", gp);
528 ret = -ENOENT;
529 break;
530 }
531 return ret;
532}
533
534const u8
535*il_eeprom_query_addr(const struct il_priv *il, size_t offset)
536{
537 BUG_ON(offset >= il->cfg->base_params->eeprom_size);
538 return &il->eeprom[offset];
539}
540EXPORT_SYMBOL(il_eeprom_query_addr);
541
542u16 il_eeprom_query16(const struct il_priv *il, size_t offset)
543{
544 if (!il->eeprom)
545 return 0;
546 return (u16)il->eeprom[offset] | ((u16)il->eeprom[offset + 1] << 8);
547}
548EXPORT_SYMBOL(il_eeprom_query16);
549
550/**
551 * il_eeprom_init - read EEPROM contents
552 *
553 * Load the EEPROM contents from adapter into il->eeprom
554 *
555 * NOTE: This routine uses the non-debug IO access functions.
556 */
557int il_eeprom_init(struct il_priv *il)
558{
559 __le16 *e;
560 u32 gp = _il_rd(il, CSR_EEPROM_GP);
561 int sz;
562 int ret;
563 u16 addr;
564
565 /* allocate eeprom */
566 sz = il->cfg->base_params->eeprom_size;
567 D_EEPROM("NVM size = %d\n", sz);
568 il->eeprom = kzalloc(sz, GFP_KERNEL);
569 if (!il->eeprom) {
570 ret = -ENOMEM;
571 goto alloc_err;
572 }
573 e = (__le16 *)il->eeprom;
574
575 il->cfg->ops->lib->apm_ops.init(il);
576
577 ret = il_eeprom_verify_signature(il);
578 if (ret < 0) {
579 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
580 ret = -ENOENT;
581 goto err;
582 }
583
584 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
585 ret = il->cfg->ops->lib->eeprom_ops.acquire_semaphore(il);
586 if (ret < 0) {
587 IL_ERR("Failed to acquire EEPROM semaphore.\n");
588 ret = -ENOENT;
589 goto err;
590 }
591
592 /* eeprom is an array of 16bit values */
593 for (addr = 0; addr < sz; addr += sizeof(u16)) {
594 u32 r;
595
596 _il_wr(il, CSR_EEPROM_REG,
597 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
598
599 ret = _il_poll_bit(il, CSR_EEPROM_REG,
600 CSR_EEPROM_REG_READ_VALID_MSK,
601 CSR_EEPROM_REG_READ_VALID_MSK,
602 IL_EEPROM_ACCESS_TIMEOUT);
603 if (ret < 0) {
604 IL_ERR("Time out reading EEPROM[%d]\n",
605 addr);
606 goto done;
607 }
608 r = _il_rd(il, CSR_EEPROM_REG);
609 e[addr / 2] = cpu_to_le16(r >> 16);
610 }
611
612 D_EEPROM("NVM Type: %s, version: 0x%x\n",
613 "EEPROM",
614 il_eeprom_query16(il, EEPROM_VERSION));
615
616 ret = 0;
617done:
618 il->cfg->ops->lib->eeprom_ops.release_semaphore(il);
619
620err:
621 if (ret)
622 il_eeprom_free(il);
623 /* Reset chip to save power until we load uCode during "up". */
624 il_apm_stop(il);
625alloc_err:
626 return ret;
627}
628EXPORT_SYMBOL(il_eeprom_init);
629
630void il_eeprom_free(struct il_priv *il)
631{
632 kfree(il->eeprom);
633 il->eeprom = NULL;
634}
635EXPORT_SYMBOL(il_eeprom_free);
636
637static void il_init_band_reference(const struct il_priv *il,
638 int eep_band, int *eeprom_ch_count,
639 const struct il_eeprom_channel **eeprom_ch_info,
640 const u8 **eeprom_ch_idx)
641{
642 u32 offset = il->cfg->ops->lib->
643 eeprom_ops.regulatory_bands[eep_band - 1];
644 switch (eep_band) {
645 case 1: /* 2.4GHz band */
646 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
647 *eeprom_ch_info = (struct il_eeprom_channel *)
648 il_eeprom_query_addr(il, offset);
649 *eeprom_ch_idx = il_eeprom_band_1;
650 break;
651 case 2: /* 4.9GHz band */
652 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
653 *eeprom_ch_info = (struct il_eeprom_channel *)
654 il_eeprom_query_addr(il, offset);
655 *eeprom_ch_idx = il_eeprom_band_2;
656 break;
657 case 3: /* 5.2GHz band */
658 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
659 *eeprom_ch_info = (struct il_eeprom_channel *)
660 il_eeprom_query_addr(il, offset);
661 *eeprom_ch_idx = il_eeprom_band_3;
662 break;
663 case 4: /* 5.5GHz band */
664 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
665 *eeprom_ch_info = (struct il_eeprom_channel *)
666 il_eeprom_query_addr(il, offset);
667 *eeprom_ch_idx = il_eeprom_band_4;
668 break;
669 case 5: /* 5.7GHz band */
670 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
671 *eeprom_ch_info = (struct il_eeprom_channel *)
672 il_eeprom_query_addr(il, offset);
673 *eeprom_ch_idx = il_eeprom_band_5;
674 break;
675 case 6: /* 2.4GHz ht40 channels */
676 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
677 *eeprom_ch_info = (struct il_eeprom_channel *)
678 il_eeprom_query_addr(il, offset);
679 *eeprom_ch_idx = il_eeprom_band_6;
680 break;
681 case 7: /* 5 GHz ht40 channels */
682 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
683 *eeprom_ch_info = (struct il_eeprom_channel *)
684 il_eeprom_query_addr(il, offset);
685 *eeprom_ch_idx = il_eeprom_band_7;
686 break;
687 default:
688 BUG();
689 }
690}
691
692#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
693 ? # x " " : "")
694/**
695 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
696 *
697 * Does not set up a command, or touch hardware.
698 */
699static int il_mod_ht40_chan_info(struct il_priv *il,
700 enum ieee80211_band band, u16 channel,
701 const struct il_eeprom_channel *eeprom_ch,
702 u8 clear_ht40_extension_channel)
703{
704 struct il_channel_info *ch_info;
705
706 ch_info = (struct il_channel_info *)
707 il_get_channel_info(il, band, channel);
708
709 if (!il_is_channel_valid(ch_info))
710 return -1;
711
712 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
713 " Ad-Hoc %ssupported\n",
714 ch_info->channel,
715 il_is_channel_a_band(ch_info) ?
716 "5.2" : "2.4",
717 CHECK_AND_PRINT(IBSS),
718 CHECK_AND_PRINT(ACTIVE),
719 CHECK_AND_PRINT(RADAR),
720 CHECK_AND_PRINT(WIDE),
721 CHECK_AND_PRINT(DFS),
722 eeprom_ch->flags,
723 eeprom_ch->max_power_avg,
724 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
725 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
726 "" : "not ");
727
728 ch_info->ht40_eeprom = *eeprom_ch;
729 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
730 ch_info->ht40_flags = eeprom_ch->flags;
731 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
732 ch_info->ht40_extension_channel &=
733 ~clear_ht40_extension_channel;
734
735 return 0;
736}
737
738#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
739 ? # x " " : "")
740
741/**
742 * il_init_channel_map - Set up driver's info for all possible channels
743 */
744int il_init_channel_map(struct il_priv *il)
745{
746 int eeprom_ch_count = 0;
747 const u8 *eeprom_ch_idx = NULL;
748 const struct il_eeprom_channel *eeprom_ch_info = NULL;
749 int band, ch;
750 struct il_channel_info *ch_info;
751
752 if (il->channel_count) {
753 D_EEPROM("Channel map already initialized.\n");
754 return 0;
755 }
756
757 D_EEPROM("Initializing regulatory info from EEPROM\n");
758
759 il->channel_count =
760 ARRAY_SIZE(il_eeprom_band_1) +
761 ARRAY_SIZE(il_eeprom_band_2) +
762 ARRAY_SIZE(il_eeprom_band_3) +
763 ARRAY_SIZE(il_eeprom_band_4) +
764 ARRAY_SIZE(il_eeprom_band_5);
765
766 D_EEPROM("Parsing data for %d channels.\n",
767 il->channel_count);
768
769 il->channel_info = kzalloc(sizeof(struct il_channel_info) *
770 il->channel_count, GFP_KERNEL);
771 if (!il->channel_info) {
772 IL_ERR("Could not allocate channel_info\n");
773 il->channel_count = 0;
774 return -ENOMEM;
775 }
776
777 ch_info = il->channel_info;
778
779 /* Loop through the 5 EEPROM bands adding them in order to the
780 * channel map we maintain (that contains additional information than
781 * what just in the EEPROM) */
782 for (band = 1; band <= 5; band++) {
783
784 il_init_band_reference(il, band, &eeprom_ch_count,
785 &eeprom_ch_info, &eeprom_ch_idx);
786
787 /* Loop through each band adding each of the channels */
788 for (ch = 0; ch < eeprom_ch_count; ch++) {
789 ch_info->channel = eeprom_ch_idx[ch];
790 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
791 IEEE80211_BAND_5GHZ;
792
793 /* permanently store EEPROM's channel regulatory flags
794 * and max power in channel info database. */
795 ch_info->eeprom = eeprom_ch_info[ch];
796
797 /* Copy the run-time flags so they are there even on
798 * invalid channels */
799 ch_info->flags = eeprom_ch_info[ch].flags;
800 /* First write that ht40 is not enabled, and then enable
801 * one by one */
802 ch_info->ht40_extension_channel =
803 IEEE80211_CHAN_NO_HT40;
804
805 if (!(il_is_channel_valid(ch_info))) {
806 D_EEPROM(
807 "Ch. %d Flags %x [%sGHz] - "
808 "No traffic\n",
809 ch_info->channel,
810 ch_info->flags,
811 il_is_channel_a_band(ch_info) ?
812 "5.2" : "2.4");
813 ch_info++;
814 continue;
815 }
816
817 /* Initialize regulatory-based run-time data */
818 ch_info->max_power_avg = ch_info->curr_txpow =
819 eeprom_ch_info[ch].max_power_avg;
820 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
821 ch_info->min_power = 0;
822
823 D_EEPROM("Ch. %d [%sGHz] "
824 "%s%s%s%s%s%s(0x%02x %ddBm):"
825 " Ad-Hoc %ssupported\n",
826 ch_info->channel,
827 il_is_channel_a_band(ch_info) ?
828 "5.2" : "2.4",
829 CHECK_AND_PRINT_I(VALID),
830 CHECK_AND_PRINT_I(IBSS),
831 CHECK_AND_PRINT_I(ACTIVE),
832 CHECK_AND_PRINT_I(RADAR),
833 CHECK_AND_PRINT_I(WIDE),
834 CHECK_AND_PRINT_I(DFS),
835 eeprom_ch_info[ch].flags,
836 eeprom_ch_info[ch].max_power_avg,
837 ((eeprom_ch_info[ch].
838 flags & EEPROM_CHANNEL_IBSS)
839 && !(eeprom_ch_info[ch].
840 flags & EEPROM_CHANNEL_RADAR))
841 ? "" : "not ");
842
843 ch_info++;
844 }
845 }
846
847 /* Check if we do have HT40 channels */
848 if (il->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
849 EEPROM_REGULATORY_BAND_NO_HT40 &&
850 il->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
851 EEPROM_REGULATORY_BAND_NO_HT40)
852 return 0;
853
854 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
855 for (band = 6; band <= 7; band++) {
856 enum ieee80211_band ieeeband;
857
858 il_init_band_reference(il, band, &eeprom_ch_count,
859 &eeprom_ch_info, &eeprom_ch_idx);
860
861 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
862 ieeeband =
863 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
864
865 /* Loop through each band adding each of the channels */
866 for (ch = 0; ch < eeprom_ch_count; ch++) {
867 /* Set up driver's info for lower half */
868 il_mod_ht40_chan_info(il, ieeeband,
869 eeprom_ch_idx[ch],
870 &eeprom_ch_info[ch],
871 IEEE80211_CHAN_NO_HT40PLUS);
872
873 /* Set up driver's info for upper half */
874 il_mod_ht40_chan_info(il, ieeeband,
875 eeprom_ch_idx[ch] + 4,
876 &eeprom_ch_info[ch],
877 IEEE80211_CHAN_NO_HT40MINUS);
878 }
879 }
880
881 return 0;
882}
883EXPORT_SYMBOL(il_init_channel_map);
884
885/*
886 * il_free_channel_map - undo allocations in il_init_channel_map
887 */
888void il_free_channel_map(struct il_priv *il)
889{
890 kfree(il->channel_info);
891 il->channel_count = 0;
892}
893EXPORT_SYMBOL(il_free_channel_map);
894
895/**
896 * il_get_channel_info - Find driver's ilate channel info
897 *
898 * Based on band and channel number.
899 */
900const struct
901il_channel_info *il_get_channel_info(const struct il_priv *il,
902 enum ieee80211_band band, u16 channel)
903{
904 int i;
905
906 switch (band) {
907 case IEEE80211_BAND_5GHZ:
908 for (i = 14; i < il->channel_count; i++) {
909 if (il->channel_info[i].channel == channel)
910 return &il->channel_info[i];
911 }
912 break;
913 case IEEE80211_BAND_2GHZ:
914 if (channel >= 1 && channel <= 14)
915 return &il->channel_info[channel - 1];
916 break;
917 default:
918 BUG();
919 }
920
921 return NULL;
922}
923EXPORT_SYMBOL(il_get_channel_info);
924
925/*
926 * Setting power level allows the card to go to sleep when not busy.
927 *
928 * We calculate a sleep command based on the required latency, which
929 * we get from mac80211. In order to handle thermal throttling, we can
930 * also use pre-defined power levels.
931 */
932
933/*
934 * This defines the old power levels. They are still used by default
935 * (level 1) and for thermal throttle (levels 3 through 5)
936 */
937
938struct il_power_vec_entry {
939 struct il_powertable_cmd cmd;
940 u8 no_dtim; /* number of skip dtim */
941};
942
943static void il_power_sleep_cam_cmd(struct il_priv *il,
944 struct il_powertable_cmd *cmd)
945{
946 memset(cmd, 0, sizeof(*cmd));
947
948 if (il->power_data.pci_pm)
949 cmd->flags |= IL_POWER_PCI_PM_MSK;
950
951 D_POWER("Sleep command for CAM\n");
952}
953
954static int
955il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
956{
957 D_POWER("Sending power/sleep command\n");
958 D_POWER("Flags value = 0x%08X\n", cmd->flags);
959 D_POWER("Tx timeout = %u\n",
960 le32_to_cpu(cmd->tx_data_timeout));
961 D_POWER("Rx timeout = %u\n",
962 le32_to_cpu(cmd->rx_data_timeout));
963 D_POWER(
964 "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
965 le32_to_cpu(cmd->sleep_interval[0]),
966 le32_to_cpu(cmd->sleep_interval[1]),
967 le32_to_cpu(cmd->sleep_interval[2]),
968 le32_to_cpu(cmd->sleep_interval[3]),
969 le32_to_cpu(cmd->sleep_interval[4]));
970
971 return il_send_cmd_pdu(il, C_POWER_TBL,
972 sizeof(struct il_powertable_cmd), cmd);
973}
974
975int
976il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd,
977 bool force)
978{
979 int ret;
980 bool update_chains;
981
982 lockdep_assert_held(&il->mutex);
983
984 /* Don't update the RX chain when chain noise calibration is running */
985 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
986 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
987
988 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
989 return 0;
990
991 if (!il_is_ready_rf(il))
992 return -EIO;
993
994 /* scan complete use sleep_power_next, need to be updated */
995 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
996 if (test_bit(S_SCANNING, &il->status) && !force) {
997 D_INFO("Defer power set mode while scanning\n");
998 return 0;
999 }
1000
1001 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1002 set_bit(S_POWER_PMI, &il->status);
1003
1004 ret = il_set_power(il, cmd);
1005 if (!ret) {
1006 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1007 clear_bit(S_POWER_PMI, &il->status);
1008
1009 if (il->cfg->ops->lib->update_chain_flags && update_chains)
1010 il->cfg->ops->lib->update_chain_flags(il);
1011 else if (il->cfg->ops->lib->update_chain_flags)
1012 D_POWER(
1013 "Cannot update the power, chain noise "
1014 "calibration running: %d\n",
1015 il->chain_noise_data.state);
1016
1017 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1018 } else
1019 IL_ERR("set power fail, ret = %d", ret);
1020
1021 return ret;
1022}
1023
1024int il_power_update_mode(struct il_priv *il, bool force)
1025{
1026 struct il_powertable_cmd cmd;
1027
1028 il_power_sleep_cam_cmd(il, &cmd);
1029 return il_power_set_mode(il, &cmd, force);
1030}
1031EXPORT_SYMBOL(il_power_update_mode);
1032
1033/* initialize to default */
1034void il_power_initialize(struct il_priv *il)
1035{
1036 u16 lctl = il_pcie_link_ctl(il);
1037
1038 il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
1039
1040 il->power_data.debug_sleep_level_override = -1;
1041
1042 memset(&il->power_data.sleep_cmd, 0,
1043 sizeof(il->power_data.sleep_cmd));
1044}
1045EXPORT_SYMBOL(il_power_initialize);
1046
1047/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1048 * sending probe req. This should be set long enough to hear probe responses
1049 * from more than one AP. */
1050#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
1051#define IL_ACTIVE_DWELL_TIME_52 (20)
1052
1053#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1054#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1055
1056/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1057 * Must be set longer than active dwell time.
1058 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
1059#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
1060#define IL_PASSIVE_DWELL_TIME_52 (10)
1061#define IL_PASSIVE_DWELL_BASE (100)
1062#define IL_CHANNEL_TUNE_TIME 5
1063
1064static int il_send_scan_abort(struct il_priv *il)
1065{
1066 int ret;
1067 struct il_rx_pkt *pkt;
1068 struct il_host_cmd cmd = {
1069 .id = C_SCAN_ABORT,
1070 .flags = CMD_WANT_SKB,
1071 };
1072
1073 /* Exit instantly with error when device is not ready
1074 * to receive scan abort command or it does not perform
1075 * hardware scan currently */
1076 if (!test_bit(S_READY, &il->status) ||
1077 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1078 !test_bit(S_SCAN_HW, &il->status) ||
1079 test_bit(S_FW_ERROR, &il->status) ||
1080 test_bit(S_EXIT_PENDING, &il->status))
1081 return -EIO;
1082
1083 ret = il_send_cmd_sync(il, &cmd);
1084 if (ret)
1085 return ret;
1086
1087 pkt = (struct il_rx_pkt *)cmd.reply_page;
1088 if (pkt->u.status != CAN_ABORT_STATUS) {
1089 /* The scan abort will return 1 for success or
1090 * 2 for "failure". A failure condition can be
1091 * due to simply not being in an active scan which
1092 * can occur if we send the scan abort before we
1093 * the microcode has notified us that a scan is
1094 * completed. */
1095 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1096 ret = -EIO;
1097 }
1098
1099 il_free_pages(il, cmd.reply_page);
1100 return ret;
1101}
1102
1103static void il_complete_scan(struct il_priv *il, bool aborted)
1104{
1105 /* check if scan was requested from mac80211 */
1106 if (il->scan_request) {
1107 D_SCAN("Complete scan in mac80211\n");
1108 ieee80211_scan_completed(il->hw, aborted);
1109 }
1110
1111 il->scan_vif = NULL;
1112 il->scan_request = NULL;
1113}
1114
1115void il_force_scan_end(struct il_priv *il)
1116{
1117 lockdep_assert_held(&il->mutex);
1118
1119 if (!test_bit(S_SCANNING, &il->status)) {
1120 D_SCAN("Forcing scan end while not scanning\n");
1121 return;
1122 }
1123
1124 D_SCAN("Forcing scan end\n");
1125 clear_bit(S_SCANNING, &il->status);
1126 clear_bit(S_SCAN_HW, &il->status);
1127 clear_bit(S_SCAN_ABORTING, &il->status);
1128 il_complete_scan(il, true);
1129}
1130
1131static void il_do_scan_abort(struct il_priv *il)
1132{
1133 int ret;
1134
1135 lockdep_assert_held(&il->mutex);
1136
1137 if (!test_bit(S_SCANNING, &il->status)) {
1138 D_SCAN("Not performing scan to abort\n");
1139 return;
1140 }
1141
1142 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1143 D_SCAN("Scan abort in progress\n");
1144 return;
1145 }
1146
1147 ret = il_send_scan_abort(il);
1148 if (ret) {
1149 D_SCAN("Send scan abort failed %d\n", ret);
1150 il_force_scan_end(il);
1151 } else
1152 D_SCAN("Successfully send scan abort\n");
1153}
1154
1155/**
1156 * il_scan_cancel - Cancel any currently executing HW scan
1157 */
1158int il_scan_cancel(struct il_priv *il)
1159{
1160 D_SCAN("Queuing abort scan\n");
1161 queue_work(il->workqueue, &il->abort_scan);
1162 return 0;
1163}
1164EXPORT_SYMBOL(il_scan_cancel);
1165
1166/**
1167 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1168 * @ms: amount of time to wait (in milliseconds) for scan to abort
1169 *
1170 */
1171int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
1172{
1173 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1174
1175 lockdep_assert_held(&il->mutex);
1176
1177 D_SCAN("Scan cancel timeout\n");
1178
1179 il_do_scan_abort(il);
1180
1181 while (time_before_eq(jiffies, timeout)) {
1182 if (!test_bit(S_SCAN_HW, &il->status))
1183 break;
1184 msleep(20);
1185 }
1186
1187 return test_bit(S_SCAN_HW, &il->status);
1188}
1189EXPORT_SYMBOL(il_scan_cancel_timeout);
1190
1191/* Service response to C_SCAN (0x80) */
1192static void il_hdl_scan(struct il_priv *il,
1193 struct il_rx_buf *rxb)
1194{
1195#ifdef CONFIG_IWLEGACY_DEBUG
1196 struct il_rx_pkt *pkt = rxb_addr(rxb);
1197 struct il_scanreq_notification *notif =
1198 (struct il_scanreq_notification *)pkt->u.raw;
1199
1200 D_SCAN("Scan request status = 0x%x\n", notif->status);
1201#endif
1202}
1203
1204/* Service N_SCAN_START (0x82) */
1205static void il_hdl_scan_start(struct il_priv *il,
1206 struct il_rx_buf *rxb)
1207{
1208 struct il_rx_pkt *pkt = rxb_addr(rxb);
1209 struct il_scanstart_notification *notif =
1210 (struct il_scanstart_notification *)pkt->u.raw;
1211 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
1212 D_SCAN("Scan start: "
1213 "%d [802.11%s] "
1214 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
1215 notif->channel,
1216 notif->band ? "bg" : "a",
1217 le32_to_cpu(notif->tsf_high),
1218 le32_to_cpu(notif->tsf_low),
1219 notif->status, notif->beacon_timer);
1220}
1221
1222/* Service N_SCAN_RESULTS (0x83) */
1223static void il_hdl_scan_results(struct il_priv *il,
1224 struct il_rx_buf *rxb)
1225{
1226#ifdef CONFIG_IWLEGACY_DEBUG
1227 struct il_rx_pkt *pkt = rxb_addr(rxb);
1228 struct il_scanresults_notification *notif =
1229 (struct il_scanresults_notification *)pkt->u.raw;
1230
1231 D_SCAN("Scan ch.res: "
1232 "%d [802.11%s] "
1233 "(TSF: 0x%08X:%08X) - %d "
1234 "elapsed=%lu usec\n",
1235 notif->channel,
1236 notif->band ? "bg" : "a",
1237 le32_to_cpu(notif->tsf_high),
1238 le32_to_cpu(notif->tsf_low),
1239 le32_to_cpu(notif->stats[0]),
1240 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
1241#endif
1242}
1243
1244/* Service N_SCAN_COMPLETE (0x84) */
1245static void il_hdl_scan_complete(struct il_priv *il,
1246 struct il_rx_buf *rxb)
1247{
1248
1249#ifdef CONFIG_IWLEGACY_DEBUG
1250 struct il_rx_pkt *pkt = rxb_addr(rxb);
1251 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1252#endif
1253
1254 D_SCAN(
1255 "Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1256 scan_notif->scanned_channels,
1257 scan_notif->tsf_low,
1258 scan_notif->tsf_high, scan_notif->status);
1259
1260 /* The HW is no longer scanning */
1261 clear_bit(S_SCAN_HW, &il->status);
1262
1263 D_SCAN("Scan on %sGHz took %dms\n",
1264 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1265 jiffies_to_msecs(jiffies - il->scan_start));
1266
1267 queue_work(il->workqueue, &il->scan_completed);
1268}
1269
1270void il_setup_rx_scan_handlers(struct il_priv *il)
1271{
1272 /* scan handlers */
1273 il->handlers[C_SCAN] = il_hdl_scan;
1274 il->handlers[N_SCAN_START] =
1275 il_hdl_scan_start;
1276 il->handlers[N_SCAN_RESULTS] =
1277 il_hdl_scan_results;
1278 il->handlers[N_SCAN_COMPLETE] =
1279 il_hdl_scan_complete;
1280}
1281EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1282
1283inline u16 il_get_active_dwell_time(struct il_priv *il,
1284 enum ieee80211_band band,
1285 u8 n_probes)
1286{
1287 if (band == IEEE80211_BAND_5GHZ)
1288 return IL_ACTIVE_DWELL_TIME_52 +
1289 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
1290 else
1291 return IL_ACTIVE_DWELL_TIME_24 +
1292 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
1293}
1294EXPORT_SYMBOL(il_get_active_dwell_time);
1295
1296u16 il_get_passive_dwell_time(struct il_priv *il,
1297 enum ieee80211_band band,
1298 struct ieee80211_vif *vif)
1299{
1300 struct il_rxon_context *ctx = &il->ctx;
1301 u16 value;
1302
1303 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
1304 IL_PASSIVE_DWELL_BASE + IL_PASSIVE_DWELL_TIME_24 :
1305 IL_PASSIVE_DWELL_BASE + IL_PASSIVE_DWELL_TIME_52;
1306
1307 if (il_is_any_associated(il)) {
1308 /*
1309 * If we're associated, we clamp the maximum passive
1310 * dwell time to be 98% of the smallest beacon interval
1311 * (minus 2 * channel tune time)
1312 */
1313 value = ctx->vif ? ctx->vif->bss_conf.beacon_int : 0;
1314 if (value > IL_PASSIVE_DWELL_BASE || !value)
1315 value = IL_PASSIVE_DWELL_BASE;
1316 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1317 passive = min(value, passive);
1318 }
1319
1320 return passive;
1321}
1322EXPORT_SYMBOL(il_get_passive_dwell_time);
1323
1324void il_init_scan_params(struct il_priv *il)
1325{
1326 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1327 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1328 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1329 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1330 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1331}
1332EXPORT_SYMBOL(il_init_scan_params);
1333
1334static int il_scan_initiate(struct il_priv *il,
1335 struct ieee80211_vif *vif)
1336{
1337 int ret;
1338
1339 lockdep_assert_held(&il->mutex);
1340
1341 if (WARN_ON(!il->cfg->ops->utils->request_scan))
1342 return -EOPNOTSUPP;
1343
1344 cancel_delayed_work(&il->scan_check);
1345
1346 if (!il_is_ready_rf(il)) {
1347 IL_WARN("Request scan called when driver not ready.\n");
1348 return -EIO;
1349 }
1350
1351 if (test_bit(S_SCAN_HW, &il->status)) {
1352 D_SCAN(
1353 "Multiple concurrent scan requests in parallel.\n");
1354 return -EBUSY;
1355 }
1356
1357 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1358 D_SCAN("Scan request while abort pending.\n");
1359 return -EBUSY;
1360 }
1361
1362 D_SCAN("Starting scan...\n");
1363
1364 set_bit(S_SCANNING, &il->status);
1365 il->scan_start = jiffies;
1366
1367 ret = il->cfg->ops->utils->request_scan(il, vif);
1368 if (ret) {
1369 clear_bit(S_SCANNING, &il->status);
1370 return ret;
1371 }
1372
1373 queue_delayed_work(il->workqueue, &il->scan_check,
1374 IL_SCAN_CHECK_WATCHDOG);
1375
1376 return 0;
1377}
1378
1379int il_mac_hw_scan(struct ieee80211_hw *hw,
1380 struct ieee80211_vif *vif,
1381 struct cfg80211_scan_request *req)
1382{
1383 struct il_priv *il = hw->priv;
1384 int ret;
1385
1386 D_MAC80211("enter\n");
1387
1388 if (req->n_channels == 0)
1389 return -EINVAL;
1390
1391 mutex_lock(&il->mutex);
1392
1393 if (test_bit(S_SCANNING, &il->status)) {
1394 D_SCAN("Scan already in progress.\n");
1395 ret = -EAGAIN;
1396 goto out_unlock;
1397 }
1398
1399 /* mac80211 will only ask for one band at a time */
1400 il->scan_request = req;
1401 il->scan_vif = vif;
1402 il->scan_band = req->channels[0]->band;
1403
1404 ret = il_scan_initiate(il, vif);
1405
1406 D_MAC80211("leave\n");
1407
1408out_unlock:
1409 mutex_unlock(&il->mutex);
1410
1411 return ret;
1412}
1413EXPORT_SYMBOL(il_mac_hw_scan);
1414
1415static void il_bg_scan_check(struct work_struct *data)
1416{
1417 struct il_priv *il =
1418 container_of(data, struct il_priv, scan_check.work);
1419
1420 D_SCAN("Scan check work\n");
1421
1422 /* Since we are here firmware does not finish scan and
1423 * most likely is in bad shape, so we don't bother to
1424 * send abort command, just force scan complete to mac80211 */
1425 mutex_lock(&il->mutex);
1426 il_force_scan_end(il);
1427 mutex_unlock(&il->mutex);
1428}
1429
1430/**
1431 * il_fill_probe_req - fill in all required fields and IE for probe request
1432 */
1433
1434u16
1435il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1436 const u8 *ta, const u8 *ies, int ie_len, int left)
1437{
1438 int len = 0;
1439 u8 *pos = NULL;
1440
1441 /* Make sure there is enough space for the probe request,
1442 * two mandatory IEs and the data */
1443 left -= 24;
1444 if (left < 0)
1445 return 0;
1446
1447 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1448 memcpy(frame->da, il_bcast_addr, ETH_ALEN);
1449 memcpy(frame->sa, ta, ETH_ALEN);
1450 memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
1451 frame->seq_ctrl = 0;
1452
1453 len += 24;
1454
1455 /* ...next IE... */
1456 pos = &frame->u.probe_req.variable[0];
1457
1458 /* fill in our indirect SSID IE */
1459 left -= 2;
1460 if (left < 0)
1461 return 0;
1462 *pos++ = WLAN_EID_SSID;
1463 *pos++ = 0;
1464
1465 len += 2;
1466
1467 if (WARN_ON(left < ie_len))
1468 return len;
1469
1470 if (ies && ie_len) {
1471 memcpy(pos, ies, ie_len);
1472 len += ie_len;
1473 }
1474
1475 return (u16)len;
1476}
1477EXPORT_SYMBOL(il_fill_probe_req);
1478
1479static void il_bg_abort_scan(struct work_struct *work)
1480{
1481 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1482
1483 D_SCAN("Abort scan work\n");
1484
1485 /* We keep scan_check work queued in case when firmware will not
1486 * report back scan completed notification */
1487 mutex_lock(&il->mutex);
1488 il_scan_cancel_timeout(il, 200);
1489 mutex_unlock(&il->mutex);
1490}
1491
1492static void il_bg_scan_completed(struct work_struct *work)
1493{
1494 struct il_priv *il =
1495 container_of(work, struct il_priv, scan_completed);
1496 bool aborted;
1497
1498 D_SCAN("Completed scan.\n");
1499
1500 cancel_delayed_work(&il->scan_check);
1501
1502 mutex_lock(&il->mutex);
1503
1504 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1505 if (aborted)
1506 D_SCAN("Aborted scan completed.\n");
1507
1508 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1509 D_SCAN("Scan already completed.\n");
1510 goto out_settings;
1511 }
1512
1513 il_complete_scan(il, aborted);
1514
1515out_settings:
1516 /* Can we still talk to firmware ? */
1517 if (!il_is_ready_rf(il))
1518 goto out;
1519
1520 /*
1521 * We do not commit power settings while scan is pending,
1522 * do it now if the settings changed.
1523 */
1524 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1525 il_set_tx_power(il, il->tx_power_next, false);
1526
1527 il->cfg->ops->utils->post_scan(il);
1528
1529out:
1530 mutex_unlock(&il->mutex);
1531}
1532
1533void il_setup_scan_deferred_work(struct il_priv *il)
1534{
1535 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1536 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1537 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1538}
1539EXPORT_SYMBOL(il_setup_scan_deferred_work);
1540
1541void il_cancel_scan_deferred_work(struct il_priv *il)
1542{
1543 cancel_work_sync(&il->abort_scan);
1544 cancel_work_sync(&il->scan_completed);
1545
1546 if (cancel_delayed_work_sync(&il->scan_check)) {
1547 mutex_lock(&il->mutex);
1548 il_force_scan_end(il);
1549 mutex_unlock(&il->mutex);
1550 }
1551}
1552EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1553
1554/* il->sta_lock must be held */
1555static void il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
1556{
1557
1558 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
1559 IL_ERR(
1560 "ACTIVATE a non DRIVER active station id %u addr %pM\n",
1561 sta_id, il->stations[sta_id].sta.sta.addr);
1562
1563 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
1564 D_ASSOC(
1565 "STA id %u addr %pM already present"
1566 " in uCode (according to driver)\n",
1567 sta_id, il->stations[sta_id].sta.sta.addr);
1568 } else {
1569 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
1570 D_ASSOC("Added STA id %u addr %pM to uCode\n",
1571 sta_id, il->stations[sta_id].sta.sta.addr);
1572 }
1573}
1574
1575static int il_process_add_sta_resp(struct il_priv *il,
1576 struct il_addsta_cmd *addsta,
1577 struct il_rx_pkt *pkt,
1578 bool sync)
1579{
1580 u8 sta_id = addsta->sta.sta_id;
1581 unsigned long flags;
1582 int ret = -EIO;
1583
1584 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1585 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n",
1586 pkt->hdr.flags);
1587 return ret;
1588 }
1589
1590 D_INFO("Processing response for adding station %u\n",
1591 sta_id);
1592
1593 spin_lock_irqsave(&il->sta_lock, flags);
1594
1595 switch (pkt->u.add_sta.status) {
1596 case ADD_STA_SUCCESS_MSK:
1597 D_INFO("C_ADD_STA PASSED\n");
1598 il_sta_ucode_activate(il, sta_id);
1599 ret = 0;
1600 break;
1601 case ADD_STA_NO_ROOM_IN_TBL:
1602 IL_ERR("Adding station %d failed, no room in table.\n",
1603 sta_id);
1604 break;
1605 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
1606 IL_ERR(
1607 "Adding station %d failed, no block ack resource.\n",
1608 sta_id);
1609 break;
1610 case ADD_STA_MODIFY_NON_EXIST_STA:
1611 IL_ERR("Attempting to modify non-existing station %d\n",
1612 sta_id);
1613 break;
1614 default:
1615 D_ASSOC("Received C_ADD_STA:(0x%08X)\n",
1616 pkt->u.add_sta.status);
1617 break;
1618 }
1619
1620 D_INFO("%s station id %u addr %pM\n",
1621 il->stations[sta_id].sta.mode ==
1622 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added",
1623 sta_id, il->stations[sta_id].sta.sta.addr);
1624
1625 /*
1626 * XXX: The MAC address in the command buffer is often changed from
1627 * the original sent to the device. That is, the MAC address
1628 * written to the command buffer often is not the same MAC address
1629 * read from the command buffer when the command returns. This
1630 * issue has not yet been resolved and this debugging is left to
1631 * observe the problem.
1632 */
1633 D_INFO("%s station according to cmd buffer %pM\n",
1634 il->stations[sta_id].sta.mode ==
1635 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added",
1636 addsta->sta.addr);
1637 spin_unlock_irqrestore(&il->sta_lock, flags);
1638
1639 return ret;
1640}
1641
1642static void il_add_sta_callback(struct il_priv *il,
1643 struct il_device_cmd *cmd,
1644 struct il_rx_pkt *pkt)
1645{
1646 struct il_addsta_cmd *addsta =
1647 (struct il_addsta_cmd *)cmd->cmd.payload;
1648
1649 il_process_add_sta_resp(il, addsta, pkt, false);
1650
1651}
1652
1653int il_send_add_sta(struct il_priv *il,
1654 struct il_addsta_cmd *sta, u8 flags)
1655{
1656 struct il_rx_pkt *pkt = NULL;
1657 int ret = 0;
1658 u8 data[sizeof(*sta)];
1659 struct il_host_cmd cmd = {
1660 .id = C_ADD_STA,
1661 .flags = flags,
1662 .data = data,
1663 };
1664 u8 sta_id __maybe_unused = sta->sta.sta_id;
1665
1666 D_INFO("Adding sta %u (%pM) %ssynchronously\n",
1667 sta_id, sta->sta.addr, flags & CMD_ASYNC ? "a" : "");
1668
1669 if (flags & CMD_ASYNC)
1670 cmd.callback = il_add_sta_callback;
1671 else {
1672 cmd.flags |= CMD_WANT_SKB;
1673 might_sleep();
1674 }
1675
1676 cmd.len = il->cfg->ops->utils->build_addsta_hcmd(sta, data);
1677 ret = il_send_cmd(il, &cmd);
1678
1679 if (ret || (flags & CMD_ASYNC))
1680 return ret;
1681
1682 if (ret == 0) {
1683 pkt = (struct il_rx_pkt *)cmd.reply_page;
1684 ret = il_process_add_sta_resp(il, sta, pkt, true);
1685 }
1686 il_free_pages(il, cmd.reply_page);
1687
1688 return ret;
1689}
1690EXPORT_SYMBOL(il_send_add_sta);
1691
1692static void il_set_ht_add_station(struct il_priv *il, u8 idx,
1693 struct ieee80211_sta *sta,
1694 struct il_rxon_context *ctx)
1695{
1696 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1697 __le32 sta_flags;
1698 u8 mimo_ps_mode;
1699
1700 if (!sta || !sta_ht_inf->ht_supported)
1701 goto done;
1702
1703 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
1704 D_ASSOC("spatial multiplexing power save mode: %s\n",
1705 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ?
1706 "static" :
1707 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ?
1708 "dynamic" : "disabled");
1709
1710 sta_flags = il->stations[idx].sta.station_flags;
1711
1712 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1713
1714 switch (mimo_ps_mode) {
1715 case WLAN_HT_CAP_SM_PS_STATIC:
1716 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1717 break;
1718 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1719 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1720 break;
1721 case WLAN_HT_CAP_SM_PS_DISABLED:
1722 break;
1723 default:
1724 IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
1725 break;
1726 }
1727
1728 sta_flags |= cpu_to_le32(
1729 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
1730
1731 sta_flags |= cpu_to_le32(
1732 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
1733
1734 if (il_is_ht40_tx_allowed(il, ctx, &sta->ht_cap))
1735 sta_flags |= STA_FLG_HT40_EN_MSK;
1736 else
1737 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1738
1739 il->stations[idx].sta.station_flags = sta_flags;
1740 done:
1741 return;
1742}
1743
1744/**
1745 * il_prep_station - Prepare station information for addition
1746 *
1747 * should be called with sta_lock held
1748 */
1749u8 il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
1750 const u8 *addr, bool is_ap, struct ieee80211_sta *sta)
1751{
1752 struct il_station_entry *station;
1753 int i;
1754 u8 sta_id = IL_INVALID_STATION;
1755 u16 rate;
1756
1757 if (is_ap)
1758 sta_id = ctx->ap_sta_id;
1759 else if (is_broadcast_ether_addr(addr))
1760 sta_id = ctx->bcast_sta_id;
1761 else
1762 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
1763 if (!compare_ether_addr(il->stations[i].sta.sta.addr,
1764 addr)) {
1765 sta_id = i;
1766 break;
1767 }
1768
1769 if (!il->stations[i].used &&
1770 sta_id == IL_INVALID_STATION)
1771 sta_id = i;
1772 }
1773
1774 /*
1775 * These two conditions have the same outcome, but keep them
1776 * separate
1777 */
1778 if (unlikely(sta_id == IL_INVALID_STATION))
1779 return sta_id;
1780
1781 /*
1782 * uCode is not able to deal with multiple requests to add a
1783 * station. Keep track if one is in progress so that we do not send
1784 * another.
1785 */
1786 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
1787 D_INFO(
1788 "STA %d already in process of being added.\n",
1789 sta_id);
1790 return sta_id;
1791 }
1792
1793 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1794 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
1795 !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) {
1796 D_ASSOC(
1797 "STA %d (%pM) already added, not adding again.\n",
1798 sta_id, addr);
1799 return sta_id;
1800 }
1801
1802 station = &il->stations[sta_id];
1803 station->used = IL_STA_DRIVER_ACTIVE;
1804 D_ASSOC("Add STA to driver ID %d: %pM\n",
1805 sta_id, addr);
1806 il->num_stations++;
1807
1808 /* Set up the C_ADD_STA command to send to device */
1809 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1810 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1811 station->sta.mode = 0;
1812 station->sta.sta.sta_id = sta_id;
1813 station->sta.station_flags = ctx->station_flags;
1814 station->ctxid = ctx->ctxid;
1815
1816 if (sta) {
1817 struct il_station_priv_common *sta_priv;
1818
1819 sta_priv = (void *)sta->drv_priv;
1820 sta_priv->ctx = ctx;
1821 }
1822
1823 /*
1824 * OK to call unconditionally, since local stations (IBSS BSSID
1825 * STA and broadcast STA) pass in a NULL sta, and mac80211
1826 * doesn't allow HT IBSS.
1827 */
1828 il_set_ht_add_station(il, sta_id, sta, ctx);
1829
1830 /* 3945 only */
1831 rate = (il->band == IEEE80211_BAND_5GHZ) ?
1832 RATE_6M_PLCP : RATE_1M_PLCP;
1833 /* Turn on both antennas for the station... */
1834 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
1835
1836 return sta_id;
1837
1838}
1839EXPORT_SYMBOL_GPL(il_prep_station);
1840
1841#define STA_WAIT_TIMEOUT (HZ/2)
1842
1843/**
1844 * il_add_station_common -
1845 */
1846int
1847il_add_station_common(struct il_priv *il,
1848 struct il_rxon_context *ctx,
1849 const u8 *addr, bool is_ap,
1850 struct ieee80211_sta *sta, u8 *sta_id_r)
1851{
1852 unsigned long flags_spin;
1853 int ret = 0;
1854 u8 sta_id;
1855 struct il_addsta_cmd sta_cmd;
1856
1857 *sta_id_r = 0;
1858 spin_lock_irqsave(&il->sta_lock, flags_spin);
1859 sta_id = il_prep_station(il, ctx, addr, is_ap, sta);
1860 if (sta_id == IL_INVALID_STATION) {
1861 IL_ERR("Unable to prepare station %pM for addition\n",
1862 addr);
1863 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1864 return -EINVAL;
1865 }
1866
1867 /*
1868 * uCode is not able to deal with multiple requests to add a
1869 * station. Keep track if one is in progress so that we do not send
1870 * another.
1871 */
1872 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
1873 D_INFO(
1874 "STA %d already in process of being added.\n",
1875 sta_id);
1876 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1877 return -EEXIST;
1878 }
1879
1880 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1881 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
1882 D_ASSOC(
1883 "STA %d (%pM) already added, not adding again.\n",
1884 sta_id, addr);
1885 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1886 return -EEXIST;
1887 }
1888
1889 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
1890 memcpy(&sta_cmd, &il->stations[sta_id].sta,
1891 sizeof(struct il_addsta_cmd));
1892 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1893
1894 /* Add station to device's station table */
1895 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
1896 if (ret) {
1897 spin_lock_irqsave(&il->sta_lock, flags_spin);
1898 IL_ERR("Adding station %pM failed.\n",
1899 il->stations[sta_id].sta.sta.addr);
1900 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
1901 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
1902 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1903 }
1904 *sta_id_r = sta_id;
1905 return ret;
1906}
1907EXPORT_SYMBOL(il_add_station_common);
1908
1909/**
1910 * il_sta_ucode_deactivate - deactivate ucode status for a station
1911 *
1912 * il->sta_lock must be held
1913 */
1914static void il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
1915{
1916 /* Ucode must be active and driver must be non active */
1917 if ((il->stations[sta_id].used &
1918 (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
1919 IL_STA_UCODE_ACTIVE)
1920 IL_ERR("removed non active STA %u\n", sta_id);
1921
1922 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
1923
1924 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
1925 D_ASSOC("Removed STA %u\n", sta_id);
1926}
1927
1928static int il_send_remove_station(struct il_priv *il,
1929 const u8 *addr, int sta_id,
1930 bool temporary)
1931{
1932 struct il_rx_pkt *pkt;
1933 int ret;
1934
1935 unsigned long flags_spin;
1936 struct il_rem_sta_cmd rm_sta_cmd;
1937
1938 struct il_host_cmd cmd = {
1939 .id = C_REM_STA,
1940 .len = sizeof(struct il_rem_sta_cmd),
1941 .flags = CMD_SYNC,
1942 .data = &rm_sta_cmd,
1943 };
1944
1945 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
1946 rm_sta_cmd.num_sta = 1;
1947 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
1948
1949 cmd.flags |= CMD_WANT_SKB;
1950
1951 ret = il_send_cmd(il, &cmd);
1952
1953 if (ret)
1954 return ret;
1955
1956 pkt = (struct il_rx_pkt *)cmd.reply_page;
1957 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1958 IL_ERR("Bad return from C_REM_STA (0x%08X)\n",
1959 pkt->hdr.flags);
1960 ret = -EIO;
1961 }
1962
1963 if (!ret) {
1964 switch (pkt->u.rem_sta.status) {
1965 case REM_STA_SUCCESS_MSK:
1966 if (!temporary) {
1967 spin_lock_irqsave(&il->sta_lock, flags_spin);
1968 il_sta_ucode_deactivate(il, sta_id);
1969 spin_unlock_irqrestore(&il->sta_lock,
1970 flags_spin);
1971 }
1972 D_ASSOC("C_REM_STA PASSED\n");
1973 break;
1974 default:
1975 ret = -EIO;
1976 IL_ERR("C_REM_STA failed\n");
1977 break;
1978 }
1979 }
1980 il_free_pages(il, cmd.reply_page);
1981
1982 return ret;
1983}
1984
1985/**
1986 * il_remove_station - Remove driver's knowledge of station.
1987 */
1988int il_remove_station(struct il_priv *il, const u8 sta_id,
1989 const u8 *addr)
1990{
1991 unsigned long flags;
1992
1993 if (!il_is_ready(il)) {
1994 D_INFO(
1995 "Unable to remove station %pM, device not ready.\n",
1996 addr);
1997 /*
1998 * It is typical for stations to be removed when we are
1999 * going down. Return success since device will be down
2000 * soon anyway
2001 */
2002 return 0;
2003 }
2004
2005 D_ASSOC("Removing STA from driver:%d %pM\n",
2006 sta_id, addr);
2007
2008 if (WARN_ON(sta_id == IL_INVALID_STATION))
2009 return -EINVAL;
2010
2011 spin_lock_irqsave(&il->sta_lock, flags);
2012
2013 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2014 D_INFO("Removing %pM but non DRIVER active\n",
2015 addr);
2016 goto out_err;
2017 }
2018
2019 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
2020 D_INFO("Removing %pM but non UCODE active\n",
2021 addr);
2022 goto out_err;
2023 }
2024
2025 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2026 kfree(il->stations[sta_id].lq);
2027 il->stations[sta_id].lq = NULL;
2028 }
2029
2030 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2031
2032 il->num_stations--;
2033
2034 BUG_ON(il->num_stations < 0);
2035
2036 spin_unlock_irqrestore(&il->sta_lock, flags);
2037
2038 return il_send_remove_station(il, addr, sta_id, false);
2039out_err:
2040 spin_unlock_irqrestore(&il->sta_lock, flags);
2041 return -EINVAL;
2042}
2043EXPORT_SYMBOL_GPL(il_remove_station);
2044
2045/**
2046 * il_clear_ucode_stations - clear ucode station table bits
2047 *
2048 * This function clears all the bits in the driver indicating
2049 * which stations are active in the ucode. Call when something
2050 * other than explicit station management would cause this in
2051 * the ucode, e.g. unassociated RXON.
2052 */
2053void il_clear_ucode_stations(struct il_priv *il,
2054 struct il_rxon_context *ctx)
2055{
2056 int i;
2057 unsigned long flags_spin;
2058 bool cleared = false;
2059
2060 D_INFO("Clearing ucode stations in driver\n");
2061
2062 spin_lock_irqsave(&il->sta_lock, flags_spin);
2063 for (i = 0; i < il->hw_params.max_stations; i++) {
2064 if (ctx && ctx->ctxid != il->stations[i].ctxid)
2065 continue;
2066
2067 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
2068 D_INFO(
2069 "Clearing ucode active for station %d\n", i);
2070 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2071 cleared = true;
2072 }
2073 }
2074 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2075
2076 if (!cleared)
2077 D_INFO(
2078 "No active stations found to be cleared\n");
2079}
2080EXPORT_SYMBOL(il_clear_ucode_stations);
2081
2082/**
2083 * il_restore_stations() - Restore driver known stations to device
2084 *
2085 * All stations considered active by driver, but not present in ucode, is
2086 * restored.
2087 *
2088 * Function sleeps.
2089 */
2090void
2091il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx)
2092{
2093 struct il_addsta_cmd sta_cmd;
2094 struct il_link_quality_cmd lq;
2095 unsigned long flags_spin;
2096 int i;
2097 bool found = false;
2098 int ret;
2099 bool send_lq;
2100
2101 if (!il_is_ready(il)) {
2102 D_INFO(
2103 "Not ready yet, not restoring any stations.\n");
2104 return;
2105 }
2106
2107 D_ASSOC("Restoring all known stations ... start.\n");
2108 spin_lock_irqsave(&il->sta_lock, flags_spin);
2109 for (i = 0; i < il->hw_params.max_stations; i++) {
2110 if (ctx->ctxid != il->stations[i].ctxid)
2111 continue;
2112 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2113 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2114 D_ASSOC("Restoring sta %pM\n",
2115 il->stations[i].sta.sta.addr);
2116 il->stations[i].sta.mode = 0;
2117 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2118 found = true;
2119 }
2120 }
2121
2122 for (i = 0; i < il->hw_params.max_stations; i++) {
2123 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2124 memcpy(&sta_cmd, &il->stations[i].sta,
2125 sizeof(struct il_addsta_cmd));
2126 send_lq = false;
2127 if (il->stations[i].lq) {
2128 memcpy(&lq, il->stations[i].lq,
2129 sizeof(struct il_link_quality_cmd));
2130 send_lq = true;
2131 }
2132 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2133 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2134 if (ret) {
2135 spin_lock_irqsave(&il->sta_lock, flags_spin);
2136 IL_ERR("Adding station %pM failed.\n",
2137 il->stations[i].sta.sta.addr);
2138 il->stations[i].used &=
2139 ~IL_STA_DRIVER_ACTIVE;
2140 il->stations[i].used &=
2141 ~IL_STA_UCODE_INPROGRESS;
2142 spin_unlock_irqrestore(&il->sta_lock,
2143 flags_spin);
2144 }
2145 /*
2146 * Rate scaling has already been initialized, send
2147 * current LQ command
2148 */
2149 if (send_lq)
2150 il_send_lq_cmd(il, ctx, &lq,
2151 CMD_SYNC, true);
2152 spin_lock_irqsave(&il->sta_lock, flags_spin);
2153 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2154 }
2155 }
2156
2157 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2158 if (!found)
2159 D_INFO("Restoring all known stations"
2160 " .... no stations to be restored.\n");
2161 else
2162 D_INFO("Restoring all known stations"
2163 " .... complete.\n");
2164}
2165EXPORT_SYMBOL(il_restore_stations);
2166
2167int il_get_free_ucode_key_idx(struct il_priv *il)
2168{
2169 int i;
2170
2171 for (i = 0; i < il->sta_key_max_num; i++)
2172 if (!test_and_set_bit(i, &il->ucode_key_table))
2173 return i;
2174
2175 return WEP_INVALID_OFFSET;
2176}
2177EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2178
2179void il_dealloc_bcast_stations(struct il_priv *il)
2180{
2181 unsigned long flags;
2182 int i;
2183
2184 spin_lock_irqsave(&il->sta_lock, flags);
2185 for (i = 0; i < il->hw_params.max_stations; i++) {
2186 if (!(il->stations[i].used & IL_STA_BCAST))
2187 continue;
2188
2189 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2190 il->num_stations--;
2191 BUG_ON(il->num_stations < 0);
2192 kfree(il->stations[i].lq);
2193 il->stations[i].lq = NULL;
2194 }
2195 spin_unlock_irqrestore(&il->sta_lock, flags);
2196}
2197EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2198
2199#ifdef CONFIG_IWLEGACY_DEBUG
2200static void il_dump_lq_cmd(struct il_priv *il,
2201 struct il_link_quality_cmd *lq)
2202{
2203 int i;
2204 D_RATE("lq station id 0x%x\n", lq->sta_id);
2205 D_RATE("lq ant 0x%X 0x%X\n",
2206 lq->general_params.single_stream_ant_msk,
2207 lq->general_params.dual_stream_ant_msk);
2208
2209 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
2210 D_RATE("lq idx %d 0x%X\n",
2211 i, lq->rs_table[i].rate_n_flags);
2212}
2213#else
2214static inline void il_dump_lq_cmd(struct il_priv *il,
2215 struct il_link_quality_cmd *lq)
2216{
2217}
2218#endif
2219
2220/**
2221 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2222 *
2223 * It sometimes happens when a HT rate has been in use and we
2224 * loose connectivity with AP then mac80211 will first tell us that the
2225 * current channel is not HT anymore before removing the station. In such a
2226 * scenario the RXON flags will be updated to indicate we are not
2227 * communicating HT anymore, but the LQ command may still contain HT rates.
2228 * Test for this to prevent driver from sending LQ command between the time
2229 * RXON flags are updated and when LQ command is updated.
2230 */
2231static bool il_is_lq_table_valid(struct il_priv *il,
2232 struct il_rxon_context *ctx,
2233 struct il_link_quality_cmd *lq)
2234{
2235 int i;
2236
2237 if (ctx->ht.enabled)
2238 return true;
2239
2240 D_INFO("Channel %u is not an HT channel\n",
2241 ctx->active.channel);
2242 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
2243 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) &
2244 RATE_MCS_HT_MSK) {
2245 D_INFO(
2246 "idx %d of LQ expects HT channel\n",
2247 i);
2248 return false;
2249 }
2250 }
2251 return true;
2252}
2253
2254/**
2255 * il_send_lq_cmd() - Send link quality command
2256 * @init: This command is sent as part of station initialization right
2257 * after station has been added.
2258 *
2259 * The link quality command is sent as the last step of station creation.
2260 * This is the special case in which init is set and we call a callback in
2261 * this case to clear the state indicating that station creation is in
2262 * progress.
2263 */
2264int il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
2265 struct il_link_quality_cmd *lq, u8 flags, bool init)
2266{
2267 int ret = 0;
2268 unsigned long flags_spin;
2269
2270 struct il_host_cmd cmd = {
2271 .id = C_TX_LINK_QUALITY_CMD,
2272 .len = sizeof(struct il_link_quality_cmd),
2273 .flags = flags,
2274 .data = lq,
2275 };
2276
2277 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2278 return -EINVAL;
2279
2280
2281 spin_lock_irqsave(&il->sta_lock, flags_spin);
2282 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2283 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2284 return -EINVAL;
2285 }
2286 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2287
2288 il_dump_lq_cmd(il, lq);
2289 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2290
2291 if (il_is_lq_table_valid(il, ctx, lq))
2292 ret = il_send_cmd(il, &cmd);
2293 else
2294 ret = -EINVAL;
2295
2296 if (cmd.flags & CMD_ASYNC)
2297 return ret;
2298
2299 if (init) {
2300 D_INFO("init LQ command complete,"
2301 " clearing sta addition status for sta %d\n",
2302 lq->sta_id);
2303 spin_lock_irqsave(&il->sta_lock, flags_spin);
2304 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2305 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2306 }
2307 return ret;
2308}
2309EXPORT_SYMBOL(il_send_lq_cmd);
2310
2311int il_mac_sta_remove(struct ieee80211_hw *hw,
2312 struct ieee80211_vif *vif,
2313 struct ieee80211_sta *sta)
2314{
2315 struct il_priv *il = hw->priv;
2316 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2317 int ret;
2318
2319 D_INFO("received request to remove station %pM\n",
2320 sta->addr);
2321 mutex_lock(&il->mutex);
2322 D_INFO("proceeding to remove station %pM\n",
2323 sta->addr);
2324 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2325 if (ret)
2326 IL_ERR("Error removing station %pM\n",
2327 sta->addr);
2328 mutex_unlock(&il->mutex);
2329 return ret;
2330}
2331EXPORT_SYMBOL(il_mac_sta_remove);
2332
2333/************************** RX-FUNCTIONS ****************************/
2334/*
2335 * Rx theory of operation
2336 *
2337 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2338 * each of which point to Receive Buffers to be filled by the NIC. These get
2339 * used not only for Rx frames, but for any command response or notification
2340 * from the NIC. The driver and NIC manage the Rx buffers by means
2341 * of idxes into the circular buffer.
2342 *
2343 * Rx Queue Indexes
2344 * The host/firmware share two idx registers for managing the Rx buffers.
2345 *
2346 * The READ idx maps to the first position that the firmware may be writing
2347 * to -- the driver can read up to (but not including) this position and get
2348 * good data.
2349 * The READ idx is managed by the firmware once the card is enabled.
2350 *
2351 * The WRITE idx maps to the last position the driver has read from -- the
2352 * position preceding WRITE is the last slot the firmware can place a packet.
2353 *
2354 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2355 * WRITE = READ.
2356 *
2357 * During initialization, the host sets up the READ queue position to the first
2358 * IDX position, and WRITE to the last (READ - 1 wrapped)
2359 *
2360 * When the firmware places a packet in a buffer, it will advance the READ idx
2361 * and fire the RX interrupt. The driver can then query the READ idx and
2362 * process as many packets as possible, moving the WRITE idx forward as it
2363 * resets the Rx queue buffers with new memory.
2364 *
2365 * The management in the driver is as follows:
2366 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2367 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2368 * to replenish the iwl->rxq->rx_free.
2369 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2370 * iwl->rxq is replenished and the READ IDX is updated (updating the
2371 * 'processed' and 'read' driver idxes as well)
2372 * + A received packet is processed and handed to the kernel network stack,
2373 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2374 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2375 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2376 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2377 * were enough free buffers and RX_STALLED is set it is cleared.
2378 *
2379 *
2380 * Driver sequence:
2381 *
2382 * il_rx_queue_alloc() Allocates rx_free
2383 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2384 * il_rx_queue_restock
2385 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2386 * queue, updates firmware pointers, and updates
2387 * the WRITE idx. If insufficient rx_free buffers
2388 * are available, schedules il_rx_replenish
2389 *
2390 * -- enable interrupts --
2391 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2392 * READ IDX, detaching the SKB from the pool.
2393 * Moves the packet buffer from queue to rx_used.
2394 * Calls il_rx_queue_restock to refill any empty
2395 * slots.
2396 * ...
2397 *
2398 */
2399
2400/**
2401 * il_rx_queue_space - Return number of free slots available in queue.
2402 */
2403int il_rx_queue_space(const struct il_rx_queue *q)
2404{
2405 int s = q->read - q->write;
2406 if (s <= 0)
2407 s += RX_QUEUE_SIZE;
2408 /* keep some buffer to not confuse full and empty queue */
2409 s -= 2;
2410 if (s < 0)
2411 s = 0;
2412 return s;
2413}
2414EXPORT_SYMBOL(il_rx_queue_space);
2415
2416/**
2417 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2418 */
2419void
2420il_rx_queue_update_write_ptr(struct il_priv *il,
2421 struct il_rx_queue *q)
2422{
2423 unsigned long flags;
2424 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2425 u32 reg;
2426
2427 spin_lock_irqsave(&q->lock, flags);
2428
2429 if (q->need_update == 0)
2430 goto exit_unlock;
2431
2432 /* If power-saving is in use, make sure device is awake */
2433 if (test_bit(S_POWER_PMI, &il->status)) {
2434 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2435
2436 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
2437 D_INFO(
2438 "Rx queue requesting wakeup,"
2439 " GP1 = 0x%x\n", reg);
2440 il_set_bit(il, CSR_GP_CNTRL,
2441 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2442 goto exit_unlock;
2443 }
2444
2445 q->write_actual = (q->write & ~0x7);
2446 il_wr(il, rx_wrt_ptr_reg,
2447 q->write_actual);
2448
2449 /* Else device is assumed to be awake */
2450 } else {
2451 /* Device expects a multiple of 8 */
2452 q->write_actual = (q->write & ~0x7);
2453 il_wr(il, rx_wrt_ptr_reg,
2454 q->write_actual);
2455 }
2456
2457 q->need_update = 0;
2458
2459 exit_unlock:
2460 spin_unlock_irqrestore(&q->lock, flags);
2461}
2462EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2463
2464int il_rx_queue_alloc(struct il_priv *il)
2465{
2466 struct il_rx_queue *rxq = &il->rxq;
2467 struct device *dev = &il->pci_dev->dev;
2468 int i;
2469
2470 spin_lock_init(&rxq->lock);
2471 INIT_LIST_HEAD(&rxq->rx_free);
2472 INIT_LIST_HEAD(&rxq->rx_used);
2473
2474 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
2475 rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2476 GFP_KERNEL);
2477 if (!rxq->bd)
2478 goto err_bd;
2479
2480 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2481 &rxq->rb_stts_dma, GFP_KERNEL);
2482 if (!rxq->rb_stts)
2483 goto err_rb;
2484
2485 /* Fill the rx_used queue with _all_ of the Rx buffers */
2486 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2487 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2488
2489 /* Set us so that we have processed and used all buffers, but have
2490 * not restocked the Rx queue with fresh buffers */
2491 rxq->read = rxq->write = 0;
2492 rxq->write_actual = 0;
2493 rxq->free_count = 0;
2494 rxq->need_update = 0;
2495 return 0;
2496
2497err_rb:
2498 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2499 rxq->bd_dma);
2500err_bd:
2501 return -ENOMEM;
2502}
2503EXPORT_SYMBOL(il_rx_queue_alloc);
2504
2505
2506void il_hdl_spectrum_measurement(struct il_priv *il,
2507 struct il_rx_buf *rxb)
2508{
2509 struct il_rx_pkt *pkt = rxb_addr(rxb);
2510 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2511
2512 if (!report->state) {
2513 D_11H(
2514 "Spectrum Measure Notification: Start\n");
2515 return;
2516 }
2517
2518 memcpy(&il->measure_report, report, sizeof(*report));
2519 il->measurement_status |= MEASUREMENT_READY;
2520}
2521EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2522
2523/*
2524 * returns non-zero if packet should be dropped
2525 */
2526int il_set_decrypted_flag(struct il_priv *il,
2527 struct ieee80211_hdr *hdr,
2528 u32 decrypt_res,
2529 struct ieee80211_rx_status *stats)
2530{
2531 u16 fc = le16_to_cpu(hdr->frame_control);
2532
2533 /*
2534 * All contexts have the same setting here due to it being
2535 * a module parameter, so OK to check any context.
2536 */
2537 if (il->ctx.active.filter_flags &
2538 RXON_FILTER_DIS_DECRYPT_MSK)
2539 return 0;
2540
2541 if (!(fc & IEEE80211_FCTL_PROTECTED))
2542 return 0;
2543
2544 D_RX("decrypt_res:0x%x\n", decrypt_res);
2545 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2546 case RX_RES_STATUS_SEC_TYPE_TKIP:
2547 /* The uCode has got a bad phase 1 Key, pushes the packet.
2548 * Decryption will be done in SW. */
2549 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2550 RX_RES_STATUS_BAD_KEY_TTAK)
2551 break;
2552
2553 case RX_RES_STATUS_SEC_TYPE_WEP:
2554 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2555 RX_RES_STATUS_BAD_ICV_MIC) {
2556 /* bad ICV, the packet is destroyed since the
2557 * decryption is inplace, drop it */
2558 D_RX("Packet destroyed\n");
2559 return -1;
2560 }
2561 case RX_RES_STATUS_SEC_TYPE_CCMP:
2562 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2563 RX_RES_STATUS_DECRYPT_OK) {
2564 D_RX("hw decrypt successfully!!!\n");
2565 stats->flag |= RX_FLAG_DECRYPTED;
2566 }
2567 break;
2568
2569 default:
2570 break;
2571 }
2572 return 0;
2573}
2574EXPORT_SYMBOL(il_set_decrypted_flag);
2575
2576/**
2577 * il_txq_update_write_ptr - Send new write idx to hardware
2578 */
2579void
2580il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2581{
2582 u32 reg = 0;
2583 int txq_id = txq->q.id;
2584
2585 if (txq->need_update == 0)
2586 return;
2587
2588 /* if we're trying to save power */
2589 if (test_bit(S_POWER_PMI, &il->status)) {
2590 /* wake up nic if it's powered down ...
2591 * uCode will wake up, and interrupt us again, so next
2592 * time we'll skip this part. */
2593 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2594
2595 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
2596 D_INFO(
2597 "Tx queue %d requesting wakeup,"
2598 " GP1 = 0x%x\n", txq_id, reg);
2599 il_set_bit(il, CSR_GP_CNTRL,
2600 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2601 return;
2602 }
2603
2604 il_wr(il, HBUS_TARG_WRPTR,
2605 txq->q.write_ptr | (txq_id << 8));
2606
2607 /*
2608 * else not in power-save mode,
2609 * uCode will never sleep when we're
2610 * trying to tx (during RFKILL, we're not trying to tx).
2611 */
2612 } else
2613 _il_wr(il, HBUS_TARG_WRPTR,
2614 txq->q.write_ptr | (txq_id << 8));
2615 txq->need_update = 0;
2616}
2617EXPORT_SYMBOL(il_txq_update_write_ptr);
2618
2619/**
2620 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2621 */
2622void il_tx_queue_unmap(struct il_priv *il, int txq_id)
2623{
2624 struct il_tx_queue *txq = &il->txq[txq_id];
2625 struct il_queue *q = &txq->q;
2626
2627 if (q->n_bd == 0)
2628 return;
2629
2630 while (q->write_ptr != q->read_ptr) {
2631 il->cfg->ops->lib->txq_free_tfd(il, txq);
2632 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2633 }
2634}
2635EXPORT_SYMBOL(il_tx_queue_unmap);
2636
2637/**
2638 * il_tx_queue_free - Deallocate DMA queue.
2639 * @txq: Transmit queue to deallocate.
2640 *
2641 * Empty queue by removing and destroying all BD's.
2642 * Free all buffers.
2643 * 0-fill, but do not free "txq" descriptor structure.
2644 */
2645void il_tx_queue_free(struct il_priv *il, int txq_id)
2646{
2647 struct il_tx_queue *txq = &il->txq[txq_id];
2648 struct device *dev = &il->pci_dev->dev;
2649 int i;
2650
2651 il_tx_queue_unmap(il, txq_id);
2652
2653 /* De-alloc array of command/tx buffers */
2654 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2655 kfree(txq->cmd[i]);
2656
2657 /* De-alloc circular buffer of TFDs */
2658 if (txq->q.n_bd)
2659 dma_free_coherent(dev, il->hw_params.tfd_size *
2660 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
2661
2662 /* De-alloc array of per-TFD driver data */
2663 kfree(txq->txb);
2664 txq->txb = NULL;
2665
2666 /* deallocate arrays */
2667 kfree(txq->cmd);
2668 kfree(txq->meta);
2669 txq->cmd = NULL;
2670 txq->meta = NULL;
2671
2672 /* 0-fill queue descriptor structure */
2673 memset(txq, 0, sizeof(*txq));
2674}
2675EXPORT_SYMBOL(il_tx_queue_free);
2676
2677/**
2678 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2679 */
2680void il_cmd_queue_unmap(struct il_priv *il)
2681{
2682 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2683 struct il_queue *q = &txq->q;
2684 int i;
2685
2686 if (q->n_bd == 0)
2687 return;
2688
2689 while (q->read_ptr != q->write_ptr) {
2690 i = il_get_cmd_idx(q, q->read_ptr, 0);
2691
2692 if (txq->meta[i].flags & CMD_MAPPED) {
2693 pci_unmap_single(il->pci_dev,
2694 dma_unmap_addr(&txq->meta[i], mapping),
2695 dma_unmap_len(&txq->meta[i], len),
2696 PCI_DMA_BIDIRECTIONAL);
2697 txq->meta[i].flags = 0;
2698 }
2699
2700 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2701 }
2702
2703 i = q->n_win;
2704 if (txq->meta[i].flags & CMD_MAPPED) {
2705 pci_unmap_single(il->pci_dev,
2706 dma_unmap_addr(&txq->meta[i], mapping),
2707 dma_unmap_len(&txq->meta[i], len),
2708 PCI_DMA_BIDIRECTIONAL);
2709 txq->meta[i].flags = 0;
2710 }
2711}
2712EXPORT_SYMBOL(il_cmd_queue_unmap);
2713
2714/**
2715 * il_cmd_queue_free - Deallocate DMA queue.
2716 * @txq: Transmit queue to deallocate.
2717 *
2718 * Empty queue by removing and destroying all BD's.
2719 * Free all buffers.
2720 * 0-fill, but do not free "txq" descriptor structure.
2721 */
2722void il_cmd_queue_free(struct il_priv *il)
2723{
2724 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2725 struct device *dev = &il->pci_dev->dev;
2726 int i;
2727
2728 il_cmd_queue_unmap(il);
2729
2730 /* De-alloc array of command/tx buffers */
2731 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2732 kfree(txq->cmd[i]);
2733
2734 /* De-alloc circular buffer of TFDs */
2735 if (txq->q.n_bd)
2736 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2737 txq->tfds, txq->q.dma_addr);
2738
2739 /* deallocate arrays */
2740 kfree(txq->cmd);
2741 kfree(txq->meta);
2742 txq->cmd = NULL;
2743 txq->meta = NULL;
2744
2745 /* 0-fill queue descriptor structure */
2746 memset(txq, 0, sizeof(*txq));
2747}
2748EXPORT_SYMBOL(il_cmd_queue_free);
2749
2750/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2751 * DMA services
2752 *
2753 * Theory of operation
2754 *
2755 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2756 * of buffer descriptors, each of which points to one or more data buffers for
2757 * the device to read from or fill. Driver and device exchange status of each
2758 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2759 * entries in each circular buffer, to protect against confusing empty and full
2760 * queue states.
2761 *
2762 * The device reads or writes the data in the queues via the device's several
2763 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2764 *
2765 * For Tx queue, there are low mark and high mark limits. If, after queuing
2766 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2767 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2768 * Tx queue resumed.
2769 *
2770 * See more detailed info in 4965.h.
2771 ***************************************************/
2772
2773int il_queue_space(const struct il_queue *q)
2774{
2775 int s = q->read_ptr - q->write_ptr;
2776
2777 if (q->read_ptr > q->write_ptr)
2778 s -= q->n_bd;
2779
2780 if (s <= 0)
2781 s += q->n_win;
2782 /* keep some reserve to not confuse empty and full situations */
2783 s -= 2;
2784 if (s < 0)
2785 s = 0;
2786 return s;
2787}
2788EXPORT_SYMBOL(il_queue_space);
2789
2790
2791/**
2792 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2793 */
2794static int il_queue_init(struct il_priv *il, struct il_queue *q,
2795 int count, int slots_num, u32 id)
2796{
2797 q->n_bd = count;
2798 q->n_win = slots_num;
2799 q->id = id;
2800
2801 /* count must be power-of-two size, otherwise il_queue_inc_wrap
2802 * and il_queue_dec_wrap are broken. */
2803 BUG_ON(!is_power_of_2(count));
2804
2805 /* slots_num must be power-of-two size, otherwise
2806 * il_get_cmd_idx is broken. */
2807 BUG_ON(!is_power_of_2(slots_num));
2808
2809 q->low_mark = q->n_win / 4;
2810 if (q->low_mark < 4)
2811 q->low_mark = 4;
2812
2813 q->high_mark = q->n_win / 8;
2814 if (q->high_mark < 2)
2815 q->high_mark = 2;
2816
2817 q->write_ptr = q->read_ptr = 0;
2818
2819 return 0;
2820}
2821
2822/**
2823 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2824 */
2825static int il_tx_queue_alloc(struct il_priv *il,
2826 struct il_tx_queue *txq, u32 id)
2827{
2828 struct device *dev = &il->pci_dev->dev;
2829 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2830
2831 /* Driver ilate data, only for Tx (not command) queues,
2832 * not shared with device. */
2833 if (id != il->cmd_queue) {
2834 txq->txb = kzalloc(sizeof(txq->txb[0]) *
2835 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
2836 if (!txq->txb) {
2837 IL_ERR("kmalloc for auxiliary BD "
2838 "structures failed\n");
2839 goto error;
2840 }
2841 } else {
2842 txq->txb = NULL;
2843 }
2844
2845 /* Circular buffer of transmit frame descriptors (TFDs),
2846 * shared with device */
2847 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
2848 GFP_KERNEL);
2849 if (!txq->tfds) {
2850 IL_ERR("pci_alloc_consistent(%zd) failed\n", tfd_sz);
2851 goto error;
2852 }
2853 txq->q.id = id;
2854
2855 return 0;
2856
2857 error:
2858 kfree(txq->txb);
2859 txq->txb = NULL;
2860
2861 return -ENOMEM;
2862}
2863
2864/**
2865 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
2866 */
2867int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq,
2868 int slots_num, u32 txq_id)
2869{
2870 int i, len;
2871 int ret;
2872 int actual_slots = slots_num;
2873
2874 /*
2875 * Alloc buffer array for commands (Tx or other types of commands).
2876 * For the command queue (#4/#9), allocate command space + one big
2877 * command for scan, since scan command is very huge; the system will
2878 * not have two scans at the same time, so only one is needed.
2879 * For normal Tx queues (all other queues), no super-size command
2880 * space is needed.
2881 */
2882 if (txq_id == il->cmd_queue)
2883 actual_slots++;
2884
2885 txq->meta = kzalloc(sizeof(struct il_cmd_meta) * actual_slots,
2886 GFP_KERNEL);
2887 txq->cmd = kzalloc(sizeof(struct il_device_cmd *) * actual_slots,
2888 GFP_KERNEL);
2889
2890 if (!txq->meta || !txq->cmd)
2891 goto out_free_arrays;
2892
2893 len = sizeof(struct il_device_cmd);
2894 for (i = 0; i < actual_slots; i++) {
2895 /* only happens for cmd queue */
2896 if (i == slots_num)
2897 len = IL_MAX_CMD_SIZE;
2898
2899 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
2900 if (!txq->cmd[i])
2901 goto err;
2902 }
2903
2904 /* Alloc driver data array and TFD circular buffer */
2905 ret = il_tx_queue_alloc(il, txq, txq_id);
2906 if (ret)
2907 goto err;
2908
2909 txq->need_update = 0;
2910
2911 /*
2912 * For the default queues 0-3, set up the swq_id
2913 * already -- all others need to get one later
2914 * (if they need one at all).
2915 */
2916 if (txq_id < 4)
2917 il_set_swq_id(txq, txq_id, txq_id);
2918
2919 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
2920 * il_queue_inc_wrap and il_queue_dec_wrap are broken. */
2921 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
2922
2923 /* Initialize queue's high/low-water marks, and head/tail idxes */
2924 il_queue_init(il, &txq->q,
2925 TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
2926
2927 /* Tell device where to find queue */
2928 il->cfg->ops->lib->txq_init(il, txq);
2929
2930 return 0;
2931err:
2932 for (i = 0; i < actual_slots; i++)
2933 kfree(txq->cmd[i]);
2934out_free_arrays:
2935 kfree(txq->meta);
2936 kfree(txq->cmd);
2937
2938 return -ENOMEM;
2939}
2940EXPORT_SYMBOL(il_tx_queue_init);
2941
2942void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
2943 int slots_num, u32 txq_id)
2944{
2945 int actual_slots = slots_num;
2946
2947 if (txq_id == il->cmd_queue)
2948 actual_slots++;
2949
2950 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
2951
2952 txq->need_update = 0;
2953
2954 /* Initialize queue's high/low-water marks, and head/tail idxes */
2955 il_queue_init(il, &txq->q,
2956 TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
2957
2958 /* Tell device where to find queue */
2959 il->cfg->ops->lib->txq_init(il, txq);
2960}
2961EXPORT_SYMBOL(il_tx_queue_reset);
2962
2963/*************** HOST COMMAND QUEUE FUNCTIONS *****/
2964
2965/**
2966 * il_enqueue_hcmd - enqueue a uCode command
2967 * @il: device ilate data point
2968 * @cmd: a point to the ucode command structure
2969 *
2970 * The function returns < 0 values to indicate the operation is
2971 * failed. On success, it turns the idx (> 0) of command in the
2972 * command queue.
2973 */
2974int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
2975{
2976 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2977 struct il_queue *q = &txq->q;
2978 struct il_device_cmd *out_cmd;
2979 struct il_cmd_meta *out_meta;
2980 dma_addr_t phys_addr;
2981 unsigned long flags;
2982 int len;
2983 u32 idx;
2984 u16 fix_size;
2985
2986 cmd->len = il->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
2987 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
2988
2989 /* If any of the command structures end up being larger than
2990 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
2991 * we will need to increase the size of the TFD entries
2992 * Also, check to see if command buffer should not exceed the size
2993 * of device_cmd and max_cmd_size. */
2994 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
2995 !(cmd->flags & CMD_SIZE_HUGE));
2996 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
2997
2998 if (il_is_rfkill(il) || il_is_ctkill(il)) {
2999 IL_WARN("Not sending command - %s KILL\n",
3000 il_is_rfkill(il) ? "RF" : "CT");
3001 return -EIO;
3002 }
3003
3004 spin_lock_irqsave(&il->hcmd_lock, flags);
3005
3006 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3007 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3008
3009 IL_ERR("Restarting adapter due to command queue full\n");
3010 queue_work(il->workqueue, &il->restart);
3011 return -ENOSPC;
3012 }
3013
3014 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3015 out_cmd = txq->cmd[idx];
3016 out_meta = &txq->meta[idx];
3017
3018 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3019 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3020 return -ENOSPC;
3021 }
3022
3023 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3024 out_meta->flags = cmd->flags | CMD_MAPPED;
3025 if (cmd->flags & CMD_WANT_SKB)
3026 out_meta->source = cmd;
3027 if (cmd->flags & CMD_ASYNC)
3028 out_meta->callback = cmd->callback;
3029
3030 out_cmd->hdr.cmd = cmd->id;
3031 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3032
3033 /* At this point, the out_cmd now has all of the incoming cmd
3034 * information */
3035
3036 out_cmd->hdr.flags = 0;
3037 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) |
3038 IDX_TO_SEQ(q->write_ptr));
3039 if (cmd->flags & CMD_SIZE_HUGE)
3040 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3041 len = sizeof(struct il_device_cmd);
3042 if (idx == TFD_CMD_SLOTS)
3043 len = IL_MAX_CMD_SIZE;
3044
3045#ifdef CONFIG_IWLEGACY_DEBUG
3046 switch (out_cmd->hdr.cmd) {
3047 case C_TX_LINK_QUALITY_CMD:
3048 case C_SENSITIVITY:
3049 D_HC_DUMP(
3050 "Sending command %s (#%x), seq: 0x%04X, "
3051 "%d bytes at %d[%d]:%d\n",
3052 il_get_cmd_string(out_cmd->hdr.cmd),
3053 out_cmd->hdr.cmd,
3054 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3055 q->write_ptr, idx, il->cmd_queue);
3056 break;
3057 default:
3058 D_HC("Sending command %s (#%x), seq: 0x%04X, "
3059 "%d bytes at %d[%d]:%d\n",
3060 il_get_cmd_string(out_cmd->hdr.cmd),
3061 out_cmd->hdr.cmd,
3062 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3063 q->write_ptr, idx, il->cmd_queue);
3064 }
3065#endif
3066 txq->need_update = 1;
3067
3068 if (il->cfg->ops->lib->txq_update_byte_cnt_tbl)
3069 /* Set up entry in queue's byte count circular buffer */
3070 il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0);
3071
3072 phys_addr = pci_map_single(il->pci_dev, &out_cmd->hdr,
3073 fix_size, PCI_DMA_BIDIRECTIONAL);
3074 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3075 dma_unmap_len_set(out_meta, len, fix_size);
3076
3077 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
3078 phys_addr, fix_size, 1,
3079 U32_PAD(cmd->len));
3080
3081 /* Increment and update queue's write idx */
3082 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3083 il_txq_update_write_ptr(il, txq);
3084
3085 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3086 return idx;
3087}
3088
3089/**
3090 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3091 *
3092 * When FW advances 'R' idx, all entries between old and new 'R' idx
3093 * need to be reclaimed. As result, some free space forms. If there is
3094 * enough free space (> low mark), wake the stack that feeds us.
3095 */
3096static void il_hcmd_queue_reclaim(struct il_priv *il, int txq_id,
3097 int idx, int cmd_idx)
3098{
3099 struct il_tx_queue *txq = &il->txq[txq_id];
3100 struct il_queue *q = &txq->q;
3101 int nfreed = 0;
3102
3103 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3104 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
3105 "is out of range [0-%d] %d %d.\n", txq_id,
3106 idx, q->n_bd, q->write_ptr, q->read_ptr);
3107 return;
3108 }
3109
3110 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3111 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3112
3113 if (nfreed++ > 0) {
3114 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
3115 q->write_ptr, q->read_ptr);
3116 queue_work(il->workqueue, &il->restart);
3117 }
3118
3119 }
3120}
3121
3122/**
3123 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3124 * @rxb: Rx buffer to reclaim
3125 *
3126 * If an Rx buffer has an async callback associated with it the callback
3127 * will be executed. The attached skb (if present) will only be freed
3128 * if the callback returns 1
3129 */
3130void
3131il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3132{
3133 struct il_rx_pkt *pkt = rxb_addr(rxb);
3134 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3135 int txq_id = SEQ_TO_QUEUE(sequence);
3136 int idx = SEQ_TO_IDX(sequence);
3137 int cmd_idx;
3138 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3139 struct il_device_cmd *cmd;
3140 struct il_cmd_meta *meta;
3141 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3142 unsigned long flags;
3143
3144 /* If a Tx command is being handled and it isn't in the actual
3145 * command queue then there a command routing bug has been introduced
3146 * in the queue management code. */
3147 if (WARN(txq_id != il->cmd_queue,
3148 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3149 txq_id, il->cmd_queue, sequence,
3150 il->txq[il->cmd_queue].q.read_ptr,
3151 il->txq[il->cmd_queue].q.write_ptr)) {
3152 il_print_hex_error(il, pkt, 32);
3153 return;
3154 }
3155
3156 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3157 cmd = txq->cmd[cmd_idx];
3158 meta = &txq->meta[cmd_idx];
3159
3160 txq->time_stamp = jiffies;
3161
3162 pci_unmap_single(il->pci_dev,
3163 dma_unmap_addr(meta, mapping),
3164 dma_unmap_len(meta, len),
3165 PCI_DMA_BIDIRECTIONAL);
3166
3167 /* Input error checking is done when commands are added to queue. */
3168 if (meta->flags & CMD_WANT_SKB) {
3169 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3170 rxb->page = NULL;
3171 } else if (meta->callback)
3172 meta->callback(il, cmd, pkt);
3173
3174 spin_lock_irqsave(&il->hcmd_lock, flags);
3175
3176 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3177
3178 if (!(meta->flags & CMD_ASYNC)) {
3179 clear_bit(S_HCMD_ACTIVE, &il->status);
3180 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
3181 il_get_cmd_string(cmd->hdr.cmd));
3182 wake_up(&il->wait_command_queue);
3183 }
3184
3185 /* Mark as unmapped */
3186 meta->flags = 0;
3187
3188 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3189}
3190EXPORT_SYMBOL(il_tx_cmd_complete);
be663ab6
WYG		 3191
3192MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3193MODULE_VERSION(IWLWIFI_VERSION);
3194MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3195MODULE_LICENSE("GPL");
3196
3197/*
3198 * set bt_coex_active to true, uCode will do kill/defer
3199 * every time the priority line is asserted (BT is sending signals on the
3200 * priority line in the PCIx).
3201 * set bt_coex_active to false, uCode will ignore the BT activity and
3202 * perform the normal operation
3203 *
3204 * User might experience transmit issue on some platform due to WiFi/BT
3205 * co-exist problem. The possible behaviors are:
3206 * Able to scan and finding all the available AP
3207 * Not able to associate with any AP
3208 * On those platforms, WiFi communication can be restored by set
3209 * "bt_coex_active" module parameter to "false"
3210 *
3211 * default: bt_coex_active = true (BT_COEX_ENABLE)
3212 */
ef33417d 3213static bool bt_coex_active = true;
be663ab6
WYG		 3214module_param(bt_coex_active, bool, S_IRUGO);
3215MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3216
d2ddf621
SG		 3217u32 il_debug_level;
3218EXPORT_SYMBOL(il_debug_level);
be663ab6 3219
d2ddf621
SG		 3220const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3221EXPORT_SYMBOL(il_bcast_addr);
be663ab6
WYG		 3222
3223
46bc8d4b 3224/* This function both allocates and initializes hw and il. */
e2ebc833 3225struct ieee80211_hw *il_alloc_all(struct il_cfg *cfg)
be663ab6 3226{
46bc8d4b 3227 struct il_priv *il;
be663ab6 3228 /* mac80211 allocates memory for this device instance, including
46bc8d4b 3229 * space for this driver's ilate structure */
be663ab6
WYG		 3230 struct ieee80211_hw *hw;
3231
e2ebc833 3232 hw = ieee80211_alloc_hw(sizeof(struct il_priv),
be663ab6
WYG		 3233 cfg->ops->ieee80211_ops);
3234 if (hw == NULL) {
3235 pr_err("%s: Can not allocate network device\n",
3236 cfg->name);
3237 goto out;
3238 }
3239
46bc8d4b
SG		 3240 il = hw->priv;
3241 il->hw = hw;
be663ab6
WYG		 3242
3243out:
3244 return hw;
3245}
e2ebc833 3246EXPORT_SYMBOL(il_alloc_all);
be663ab6
WYG		 3247
3248#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3249#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
46bc8d4b 3250static void il_init_ht_hw_capab(const struct il_priv *il,
be663ab6
WYG		 3251 struct ieee80211_sta_ht_cap *ht_info,
3252 enum ieee80211_band band)
3253{
3254 u16 max_bit_rate = 0;
46bc8d4b
SG		 3255 u8 rx_chains_num = il->hw_params.rx_chains_num;
3256 u8 tx_chains_num = il->hw_params.tx_chains_num;
be663ab6
WYG		 3257
3258 ht_info->cap = 0;
3259 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3260
3261 ht_info->ht_supported = true;
3262
3263 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3264 max_bit_rate = MAX_BIT_RATE_20_MHZ;
46bc8d4b 3265 if (il->hw_params.ht40_channel & BIT(band)) {
be663ab6
WYG		 3266 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3267 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3268 ht_info->mcs.rx_mask[4] = 0x01;
3269 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3270 }
3271
46bc8d4b 3272 if (il->cfg->mod_params->amsdu_size_8K)
be663ab6
WYG		 3273 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3274
3275 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3276 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3277
3278 ht_info->mcs.rx_mask[0] = 0xFF;
3279 if (rx_chains_num >= 2)
3280 ht_info->mcs.rx_mask[1] = 0xFF;
3281 if (rx_chains_num >= 3)
3282 ht_info->mcs.rx_mask[2] = 0xFF;
3283
3284 /* Highest supported Rx data rate */
3285 max_bit_rate *= rx_chains_num;
3286 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3287 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3288
3289 /* Tx MCS capabilities */
3290 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3291 if (tx_chains_num != rx_chains_num) {
3292 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
3293 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
3294 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3295 }
3296}
3297
3298/**
e2ebc833 3299 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
be663ab6 3300 */
46bc8d4b 3301int il_init_geos(struct il_priv *il)
be663ab6 3302{
e2ebc833 3303 struct il_channel_info *ch;
be663ab6
WYG		 3304 struct ieee80211_supported_band *sband;
3305 struct ieee80211_channel *channels;
3306 struct ieee80211_channel *geo_ch;
3307 struct ieee80211_rate *rates;
3308 int i = 0;
332704a5 3309 s8 max_tx_power = 0;
be663ab6 3310
46bc8d4b
SG		 3311 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3312 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
58de00a4 3313 D_INFO("Geography modes already initialized.\n");
a6766ccd 3314 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3315 return 0;
3316 }
3317
3318 channels = kzalloc(sizeof(struct ieee80211_channel) *
46bc8d4b 3319 il->channel_count, GFP_KERNEL);
be663ab6
WYG		 3320 if (!channels)
3321 return -ENOMEM;
3322
2eb05816 3323 rates = kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
be663ab6
WYG		 3324 GFP_KERNEL);
3325 if (!rates) {
3326 kfree(channels);
3327 return -ENOMEM;
3328 }
3329
3330 /* 5.2GHz channels start after the 2.4GHz channels */
46bc8d4b 3331 sband = &il->bands[IEEE80211_BAND_5GHZ];
d2ddf621 3332 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
be663ab6 3333 /* just OFDM */
e2ebc833 3334 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
2eb05816 3335 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
be663ab6 3336
46bc8d4b
SG		 3337 if (il->cfg->sku & IL_SKU_N)
3338 il_init_ht_hw_capab(il, &sband->ht_cap,
be663ab6
WYG		 3339 IEEE80211_BAND_5GHZ);
3340
46bc8d4b 3341 sband = &il->bands[IEEE80211_BAND_2GHZ];
be663ab6
WYG		 3342 sband->channels = channels;
3343 /* OFDM & CCK */
3344 sband->bitrates = rates;
2eb05816 3345 sband->n_bitrates = RATE_COUNT_LEGACY;
be663ab6 3346
46bc8d4b
SG		 3347 if (il->cfg->sku & IL_SKU_N)
3348 il_init_ht_hw_capab(il, &sband->ht_cap,
be663ab6
WYG		 3349 IEEE80211_BAND_2GHZ);
3350
46bc8d4b
SG		 3351 il->ieee_channels = channels;
3352 il->ieee_rates = rates;
be663ab6 3353
46bc8d4b
SG		 3354 for (i = 0; i < il->channel_count; i++) {
3355 ch = &il->channel_info[i];
be663ab6 3356
e2ebc833 3357 if (!il_is_channel_valid(ch))
be663ab6
WYG		 3358 continue;
3359
46bc8d4b 3360 sband = &il->bands[ch->band];
be663ab6
WYG		 3361
3362 geo_ch = &sband->channels[sband->n_channels++];
3363
3364 geo_ch->center_freq =
3365 ieee80211_channel_to_frequency(ch->channel, ch->band);
3366 geo_ch->max_power = ch->max_power_avg;
3367 geo_ch->max_antenna_gain = 0xff;
3368 geo_ch->hw_value = ch->channel;
3369
e2ebc833 3370 if (il_is_channel_valid(ch)) {
be663ab6
WYG		 3371 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3372 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
3373
3374 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3375 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3376
3377 if (ch->flags & EEPROM_CHANNEL_RADAR)
3378 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3379
3380 geo_ch->flags |= ch->ht40_extension_channel;
3381
332704a5
SG		 3382 if (ch->max_power_avg > max_tx_power)
3383 max_tx_power = ch->max_power_avg;
be663ab6
WYG		 3384 } else {
3385 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3386 }
3387
58de00a4 3388 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
be663ab6 3389 ch->channel, geo_ch->center_freq,
e2ebc833 3390 il_is_channel_a_band(ch) ? "5.2" : "2.4",
be663ab6
WYG		 3391 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
3392 "restricted" : "valid",
3393 geo_ch->flags);
3394 }
3395
46bc8d4b
SG		 3396 il->tx_power_device_lmt = max_tx_power;
3397 il->tx_power_user_lmt = max_tx_power;
3398 il->tx_power_next = max_tx_power;
332704a5 3399
232913b5
SG		 3400 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3401 (il->cfg->sku & IL_SKU_A)) {
9406f797 3402 IL_INFO("Incorrectly detected BG card as ABG. "
be663ab6 3403 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
46bc8d4b
SG		 3404 il->pci_dev->device,
3405 il->pci_dev->subsystem_device);
3406 il->cfg->sku &= ~IL_SKU_A;
be663ab6
WYG		 3407 }
3408
9406f797 3409 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
46bc8d4b
SG		 3410 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3411 il->bands[IEEE80211_BAND_5GHZ].n_channels);
be663ab6 3412
a6766ccd 3413 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3414
3415 return 0;
3416}
e2ebc833 3417EXPORT_SYMBOL(il_init_geos);
be663ab6
WYG		 3418
3419/*
e2ebc833 3420 * il_free_geos - undo allocations in il_init_geos
be663ab6 3421 */
46bc8d4b 3422void il_free_geos(struct il_priv *il)
be663ab6 3423{
46bc8d4b
SG		 3424 kfree(il->ieee_channels);
3425 kfree(il->ieee_rates);
a6766ccd 3426 clear_bit(S_GEO_CONFIGURED, &il->status);
be663ab6 3427}
e2ebc833 3428EXPORT_SYMBOL(il_free_geos);
be663ab6 3429
46bc8d4b 3430static bool il_is_channel_extension(struct il_priv *il,
be663ab6
WYG		 3431 enum ieee80211_band band,
3432 u16 channel, u8 extension_chan_offset)
3433{
e2ebc833 3434 const struct il_channel_info *ch_info;
be663ab6 3435
46bc8d4b 3436 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3437 if (!il_is_channel_valid(ch_info))
be663ab6
WYG		 3438 return false;
3439
3440 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
3441 return !(ch_info->ht40_extension_channel &
3442 IEEE80211_CHAN_NO_HT40PLUS);
3443 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
3444 return !(ch_info->ht40_extension_channel &
3445 IEEE80211_CHAN_NO_HT40MINUS);
3446
3447 return false;
3448}
3449
46bc8d4b 3450bool il_is_ht40_tx_allowed(struct il_priv *il,
e2ebc833 3451 struct il_rxon_context *ctx,
be663ab6
WYG		 3452 struct ieee80211_sta_ht_cap *ht_cap)
3453{
3454 if (!ctx->ht.enabled || !ctx->ht.is_40mhz)
3455 return false;
3456
3457 /*
3458 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3459 * the bit will not set if it is pure 40MHz case
3460 */
3461 if (ht_cap && !ht_cap->ht_supported)
3462 return false;
3463
d3175167 3464#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b 3465 if (il->disable_ht40)
be663ab6
WYG		 3466 return false;
3467#endif
3468
46bc8d4b 3469 return il_is_channel_extension(il, il->band,
be663ab6
WYG		 3470 le16_to_cpu(ctx->staging.channel),
3471 ctx->ht.extension_chan_offset);
3472}
e2ebc833 3473EXPORT_SYMBOL(il_is_ht40_tx_allowed);
be663ab6 3474
e2ebc833 3475static u16 il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
be663ab6
WYG		 3476{
3477 u16 new_val;
3478 u16 beacon_factor;
3479
3480 /*
3481 * If mac80211 hasn't given us a beacon interval, program
3482 * the default into the device.
3483 */
3484 if (!beacon_val)
3485 return DEFAULT_BEACON_INTERVAL;
3486
3487 /*
3488 * If the beacon interval we obtained from the peer
3489 * is too large, we'll have to wake up more often
3490 * (and in IBSS case, we'll beacon too much)
3491 *
3492 * For example, if max_beacon_val is 4096, and the
3493 * requested beacon interval is 7000, we'll have to
3494 * use 3500 to be able to wake up on the beacons.
3495 *
3496 * This could badly influence beacon detection stats.
3497 */
3498
3499 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3500 new_val = beacon_val / beacon_factor;
3501
3502 if (!new_val)
3503 new_val = max_beacon_val;
3504
3505 return new_val;
3506}
3507
3508int
46bc8d4b 3509il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG		 3510{
3511 u64 tsf;
3512 s32 interval_tm, rem;
3513 struct ieee80211_conf *conf = NULL;
3514 u16 beacon_int;
3515 struct ieee80211_vif *vif = ctx->vif;
3516
6278ddab 3517 conf = &il->hw->conf;
be663ab6 3518
46bc8d4b 3519 lockdep_assert_held(&il->mutex);
be663ab6 3520
e2ebc833 3521 memset(&ctx->timing, 0, sizeof(struct il_rxon_time_cmd));
be663ab6 3522
46bc8d4b 3523 ctx->timing.timestamp = cpu_to_le64(il->timestamp);
be663ab6
WYG		 3524 ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval);
3525
3526 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3527
3528 /*
6ce1dc45 3529 * TODO: For IBSS we need to get atim_win from mac80211,
be663ab6
WYG		 3530 * for now just always use 0
3531 */
6ce1dc45 3532 ctx->timing.atim_win = 0;
be663ab6 3533
e2ebc833 3534 beacon_int = il_adjust_beacon_interval(beacon_int,
46bc8d4b 3535 il->hw_params.max_beacon_itrvl * TIME_UNIT);
be663ab6
WYG		 3536 ctx->timing.beacon_interval = cpu_to_le16(beacon_int);
3537
46bc8d4b 3538 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
be663ab6
WYG		 3539 interval_tm = beacon_int * TIME_UNIT;
3540 rem = do_div(tsf, interval_tm);
3541 ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
3542
3543 ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1;
3544
58de00a4 3545 D_ASSOC(
be663ab6
WYG		 3546 "beacon interval %d beacon timer %d beacon tim %d\n",
3547 le16_to_cpu(ctx->timing.beacon_interval),
3548 le32_to_cpu(ctx->timing.beacon_init_val),
6ce1dc45 3549 le16_to_cpu(ctx->timing.atim_win));
be663ab6 3550
46bc8d4b 3551 return il_send_cmd_pdu(il, ctx->rxon_timing_cmd,
be663ab6
WYG		 3552 sizeof(ctx->timing), &ctx->timing);
3553}
e2ebc833 3554EXPORT_SYMBOL(il_send_rxon_timing);
be663ab6
WYG		 3555
3556void
46bc8d4b 3557il_set_rxon_hwcrypto(struct il_priv *il,
e2ebc833 3558 struct il_rxon_context *ctx,
be663ab6
WYG		 3559 int hw_decrypt)
3560{
e2ebc833 3561 struct il_rxon_cmd *rxon = &ctx->staging;
be663ab6
WYG		 3562
3563 if (hw_decrypt)
3564 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3565 else
3566 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3567
3568}
e2ebc833 3569EXPORT_SYMBOL(il_set_rxon_hwcrypto);
be663ab6
WYG		 3570
3571/* validate RXON structure is valid */
3572int
46bc8d4b 3573il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 3574{
e2ebc833 3575 struct il_rxon_cmd *rxon = &ctx->staging;
be663ab6
WYG		 3576 bool error = false;
3577
3578 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3579 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
9406f797 3580 IL_WARN("check 2.4G: wrong narrow\n");
be663ab6
WYG		 3581 error = true;
3582 }
3583 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
9406f797 3584 IL_WARN("check 2.4G: wrong radar\n");
be663ab6
WYG		 3585 error = true;
3586 }
3587 } else {
3588 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3589 IL_WARN("check 5.2G: not short slot!\n");
be663ab6
WYG		 3590 error = true;
3591 }
3592 if (rxon->flags & RXON_FLG_CCK_MSK) {
9406f797 3593 IL_WARN("check 5.2G: CCK!\n");
be663ab6
WYG		 3594 error = true;
3595 }
3596 }
3597 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
9406f797 3598 IL_WARN("mac/bssid mcast!\n");
be663ab6
WYG		 3599 error = true;
3600 }
3601
3602 /* make sure basic rates 6Mbps and 1Mbps are supported */
2eb05816
SG		 3603 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3604 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
9406f797 3605 IL_WARN("neither 1 nor 6 are basic\n");
be663ab6
WYG		 3606 error = true;
3607 }
3608
3609 if (le16_to_cpu(rxon->assoc_id) > 2007) {
9406f797 3610 IL_WARN("aid > 2007\n");
be663ab6
WYG		 3611 error = true;
3612 }
3613
3614 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
3615 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3616 IL_WARN("CCK and short slot\n");
be663ab6
WYG		 3617 error = true;
3618 }
3619
3620 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
3621 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
9406f797 3622 IL_WARN("CCK and auto detect");
be663ab6
WYG		 3623 error = true;
3624 }
3625
3626 if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
3627 RXON_FLG_TGG_PROTECT_MSK)) ==
3628 RXON_FLG_TGG_PROTECT_MSK) {
9406f797 3629 IL_WARN("TGg but no auto-detect\n");
be663ab6
WYG		 3630 error = true;
3631 }
3632
3633 if (error)
9406f797 3634 IL_WARN("Tuning to channel %d\n",
be663ab6
WYG		 3635 le16_to_cpu(rxon->channel));
3636
3637 if (error) {
9406f797 3638 IL_ERR("Invalid RXON\n");
be663ab6
WYG		 3639 return -EINVAL;
3640 }
3641 return 0;
3642}
e2ebc833 3643EXPORT_SYMBOL(il_check_rxon_cmd);
be663ab6
WYG		 3644
3645/**
e2ebc833 3646 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
46bc8d4b 3647 * @il: staging_rxon is compared to active_rxon
be663ab6
WYG		 3648 *
3649 * If the RXON structure is changing enough to require a new tune,
3650 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3651 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3652 */
46bc8d4b 3653int il_full_rxon_required(struct il_priv *il,
e2ebc833 3654 struct il_rxon_context *ctx)
be663ab6 3655{
e2ebc833
SG		 3656 const struct il_rxon_cmd *staging = &ctx->staging;
3657 const struct il_rxon_cmd *active = &ctx->active;
be663ab6
WYG		 3658
3659#define CHK(cond) \
3660 if ((cond)) { \
58de00a4 3661 D_INFO("need full RXON - " #cond "\n"); \
be663ab6
WYG		 3662 return 1; \
3663 }
3664
3665#define CHK_NEQ(c1, c2) \
3666 if ((c1) != (c2)) { \
58de00a4 3667 D_INFO("need full RXON - " \
be663ab6
WYG		 3668 #c1 " != " #c2 " - %d != %d\n", \
3669 (c1), (c2)); \
3670 return 1; \
3671 }
3672
3673 /* These items are only settable from the full RXON command */
e2ebc833 3674 CHK(!il_is_associated_ctx(ctx));
be663ab6
WYG		 3675 CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
3676 CHK(compare_ether_addr(staging->node_addr, active->node_addr));
3677 CHK(compare_ether_addr(staging->wlap_bssid_addr,
3678 active->wlap_bssid_addr));
3679 CHK_NEQ(staging->dev_type, active->dev_type);
3680 CHK_NEQ(staging->channel, active->channel);
3681 CHK_NEQ(staging->air_propagation, active->air_propagation);
3682 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3683 active->ofdm_ht_single_stream_basic_rates);
3684 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3685 active->ofdm_ht_dual_stream_basic_rates);
3686 CHK_NEQ(staging->assoc_id, active->assoc_id);
3687
3688 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3689 * be updated with the RXON_ASSOC command -- however only some
3690 * flag transitions are allowed using RXON_ASSOC */
3691
3692 /* Check if we are not switching bands */
3693 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3694 active->flags & RXON_FLG_BAND_24G_MSK);
3695
3696 /* Check if we are switching association toggle */
3697 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3698 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3699
3700#undef CHK
3701#undef CHK_NEQ
3702
3703 return 0;
3704}
e2ebc833 3705EXPORT_SYMBOL(il_full_rxon_required);
be663ab6 3706
46bc8d4b 3707u8 il_get_lowest_plcp(struct il_priv *il,
e2ebc833 3708 struct il_rxon_context *ctx)
be663ab6
WYG		 3709{
3710 /*
3711 * Assign the lowest rate -- should really get this from
3712 * the beacon skb from mac80211.
3713 */
3714 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK)
2eb05816 3715 return RATE_1M_PLCP;
be663ab6 3716 else
2eb05816 3717 return RATE_6M_PLCP;
be663ab6 3718}
e2ebc833 3719EXPORT_SYMBOL(il_get_lowest_plcp);
be663ab6 3720
46bc8d4b 3721static void _il_set_rxon_ht(struct il_priv *il,
e2ebc833
SG		 3722 struct il_ht_config *ht_conf,
3723 struct il_rxon_context *ctx)
be663ab6 3724{
e2ebc833 3725 struct il_rxon_cmd *rxon = &ctx->staging;
be663ab6
WYG		 3726
3727 if (!ctx->ht.enabled) {
3728 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
3729 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
3730 RXON_FLG_HT40_PROT_MSK |
3731 RXON_FLG_HT_PROT_MSK);
3732 return;
3733 }
3734
3735 rxon->flags |= cpu_to_le32(ctx->ht.protection <<
3736 RXON_FLG_HT_OPERATING_MODE_POS);
3737
3738 /* Set up channel bandwidth:
3739 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3740 /* clear the HT channel mode before set the mode */
3741 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
3742 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
46bc8d4b 3743 if (il_is_ht40_tx_allowed(il, ctx, NULL)) {
be663ab6
WYG		 3744 /* pure ht40 */
3745 if (ctx->ht.protection ==
3746 IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
3747 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3748 /* Note: control channel is opposite of extension channel */
3749 switch (ctx->ht.extension_chan_offset) {
3750 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3751 rxon->flags &=
3752 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3753 break;
3754 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
3755 rxon->flags |=
3756 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3757 break;
3758 }
3759 } else {
3760 /* Note: control channel is opposite of extension channel */
3761 switch (ctx->ht.extension_chan_offset) {
3762 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3763 rxon->flags &=
3764 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3765 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3766 break;
3767 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
3768 rxon->flags |=
3769 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3770 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3771 break;
3772 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3773 default:
3774 /* channel location only valid if in Mixed mode */
9406f797 3775 IL_ERR(
be663ab6
WYG		 3776 "invalid extension channel offset\n");
3777 break;
3778 }
3779 }
3780 } else {
3781 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3782 }
3783
46bc8d4b
SG		 3784 if (il->cfg->ops->hcmd->set_rxon_chain)
3785 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6 3786
58de00a4 3787 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
be663ab6
WYG		 3788 "extension channel offset 0x%x\n",
3789 le32_to_cpu(rxon->flags), ctx->ht.protection,
3790 ctx->ht.extension_chan_offset);
3791}
3792
46bc8d4b 3793void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3794{
17d6e557 3795 _il_set_rxon_ht(il, ht_conf, &il->ctx);
be663ab6 3796}
e2ebc833 3797EXPORT_SYMBOL(il_set_rxon_ht);
be663ab6
WYG		 3798
3799/* Return valid, unused, channel for a passive scan to reset the RF */
46bc8d4b 3800u8 il_get_single_channel_number(struct il_priv *il,
be663ab6
WYG		 3801 enum ieee80211_band band)
3802{
e2ebc833 3803 const struct il_channel_info *ch_info;
be663ab6
WYG		 3804 int i;
3805 u8 channel = 0;
3806 u8 min, max;
be663ab6
WYG		 3807
3808 if (band == IEEE80211_BAND_5GHZ) {
3809 min = 14;
46bc8d4b 3810 max = il->channel_count;
be663ab6
WYG		 3811 } else {
3812 min = 0;
3813 max = 14;
3814 }
3815
3816 for (i = min; i < max; i++) {
17d6e557
SG		 3817 channel = il->channel_info[i].channel;
3818 if (channel == le16_to_cpu(il->ctx.staging.channel))
be663ab6
WYG		 3819 continue;
3820
46bc8d4b 3821 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3822 if (il_is_channel_valid(ch_info))
be663ab6
WYG		 3823 break;
3824 }
3825
3826 return channel;
3827}
e2ebc833 3828EXPORT_SYMBOL(il_get_single_channel_number);
be663ab6
WYG		 3829
3830/**
e2ebc833 3831 * il_set_rxon_channel - Set the band and channel values in staging RXON
be663ab6
WYG		 3832 * @ch: requested channel as a pointer to struct ieee80211_channel
3833
3834 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3835 * in the staging RXON flag structure based on the ch->band
3836 */
3837int
46bc8d4b 3838il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
e2ebc833 3839 struct il_rxon_context *ctx)
be663ab6
WYG		 3840{
3841 enum ieee80211_band band = ch->band;
3842 u16 channel = ch->hw_value;
3843
232913b5 3844 if (le16_to_cpu(ctx->staging.channel) == channel && il->band == band)
be663ab6
WYG		 3845 return 0;
3846
3847 ctx->staging.channel = cpu_to_le16(channel);
3848 if (band == IEEE80211_BAND_5GHZ)
3849 ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
3850 else
3851 ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
3852
46bc8d4b 3853 il->band = band;
be663ab6 3854
58de00a4 3855 D_INFO("Staging channel set to %d [%d]\n", channel, band);
be663ab6
WYG		 3856
3857 return 0;
3858}
e2ebc833 3859EXPORT_SYMBOL(il_set_rxon_channel);
be663ab6 3860
46bc8d4b 3861void il_set_flags_for_band(struct il_priv *il,
e2ebc833 3862 struct il_rxon_context *ctx,
be663ab6
WYG		 3863 enum ieee80211_band band,
3864 struct ieee80211_vif *vif)
3865{
3866 if (band == IEEE80211_BAND_5GHZ) {
3867 ctx->staging.flags &=
3868 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
3869 | RXON_FLG_CCK_MSK);
3870 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3871 } else {
e2ebc833 3872 /* Copied from il_post_associate() */
be663ab6
WYG		 3873 if (vif && vif->bss_conf.use_short_slot)
3874 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3875 else
3876 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3877
3878 ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
3879 ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
3880 ctx->staging.flags &= ~RXON_FLG_CCK_MSK;
3881 }
3882}
e2ebc833 3883EXPORT_SYMBOL(il_set_flags_for_band);
be663ab6
WYG		 3884
3885/*
3886 * initialize rxon structure with default values from eeprom
3887 */
46bc8d4b 3888void il_connection_init_rx_config(struct il_priv *il,
e2ebc833 3889 struct il_rxon_context *ctx)
be663ab6 3890{
e2ebc833 3891 const struct il_channel_info *ch_info;
be663ab6
WYG		 3892
3893 memset(&ctx->staging, 0, sizeof(ctx->staging));
3894
3895 if (!ctx->vif) {
3896 ctx->staging.dev_type = ctx->unused_devtype;
3897 } else
3898 switch (ctx->vif->type) {
3899
3900 case NL80211_IFTYPE_STATION:
3901 ctx->staging.dev_type = ctx->station_devtype;
3902 ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
3903 break;
3904
3905 case NL80211_IFTYPE_ADHOC:
3906 ctx->staging.dev_type = ctx->ibss_devtype;
3907 ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
3908 ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
3909 RXON_FILTER_ACCEPT_GRP_MSK;
3910 break;
3911
3912 default:
9406f797 3913 IL_ERR("Unsupported interface type %d\n",
be663ab6
WYG		 3914 ctx->vif->type);
3915 break;
3916 }
3917
3918#if 0
3919 /* TODO: Figure out when short_preamble would be set and cache from
3920 * that */
46bc8d4b 3921 if (!hw_to_local(il->hw)->short_preamble)
be663ab6
WYG		 3922 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3923 else
3924 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3925#endif
3926
46bc8d4b 3927 ch_info = il_get_channel_info(il, il->band,
be663ab6
WYG		 3928 le16_to_cpu(ctx->active.channel));
3929
3930 if (!ch_info)
46bc8d4b 3931 ch_info = &il->channel_info[0];
be663ab6
WYG		 3932
3933 ctx->staging.channel = cpu_to_le16(ch_info->channel);
46bc8d4b 3934 il->band = ch_info->band;
be663ab6 3935
46bc8d4b 3936 il_set_flags_for_band(il, ctx, il->band, ctx->vif);
be663ab6
WYG		 3937
3938 ctx->staging.ofdm_basic_rates =
e2ebc833 3939 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 3940 ctx->staging.cck_basic_rates =
e2ebc833 3941 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6
WYG		 3942
3943 /* clear both MIX and PURE40 mode flag */
3944 ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
3945 RXON_FLG_CHANNEL_MODE_PURE_40);
3946 if (ctx->vif)
3947 memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN);
3948
3949 ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff;
3950 ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
3951}
e2ebc833 3952EXPORT_SYMBOL(il_connection_init_rx_config);
be663ab6 3953
46bc8d4b 3954void il_set_rate(struct il_priv *il)
be663ab6
WYG		 3955{
3956 const struct ieee80211_supported_band *hw = NULL;
3957 struct ieee80211_rate *rate;
be663ab6
WYG		 3958 int i;
3959
46bc8d4b 3960 hw = il_get_hw_mode(il, il->band);
be663ab6 3961 if (!hw) {
9406f797 3962 IL_ERR("Failed to set rate: unable to get hw mode\n");
be663ab6
WYG		 3963 return;
3964 }
3965
46bc8d4b 3966 il->active_rate = 0;
be663ab6
WYG		 3967
3968 for (i = 0; i < hw->n_bitrates; i++) {
3969 rate = &(hw->bitrates[i]);
2eb05816 3970 if (rate->hw_value < RATE_COUNT_LEGACY)
46bc8d4b 3971 il->active_rate |= (1 << rate->hw_value);
be663ab6
WYG		 3972 }
3973
58de00a4 3974 D_RATE("Set active_rate = %0x\n", il->active_rate);
be663ab6 3975
17d6e557 3976 il->ctx.staging.cck_basic_rates =
e2ebc833 3977 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6 3978
17d6e557 3979 il->ctx.staging.ofdm_basic_rates =
e2ebc833 3980 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 3981}
e2ebc833 3982EXPORT_SYMBOL(il_set_rate);
be663ab6 3983
46bc8d4b 3984void il_chswitch_done(struct il_priv *il, bool is_success)
be663ab6 3985{
7c2cde2e 3986 struct il_rxon_context *ctx = &il->ctx;
be663ab6 3987
a6766ccd 3988 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 3989 return;
3990
a6766ccd 3991 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
be663ab6 3992 ieee80211_chswitch_done(ctx->vif, is_success);
be663ab6 3993}
e2ebc833 3994EXPORT_SYMBOL(il_chswitch_done);
be663ab6 3995
d2dfb33e 3996void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 3997{
dcae1c64 3998 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 3999 struct il_csa_notification *csa = &(pkt->u.csa_notif);
be663ab6 4000
7c2cde2e 4001 struct il_rxon_context *ctx = &il->ctx;
e2ebc833 4002 struct il_rxon_cmd *rxon = (void *)&ctx->active;
be663ab6 4003
a6766ccd 4004 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
51e65257
SG		 4005 return;
4006
46bc8d4b 4007 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
51e65257
SG		 4008 rxon->channel = csa->channel;
4009 ctx->staging.channel = csa->channel;
58de00a4 4010 D_11H("CSA notif: channel %d\n",
be663ab6 4011 le16_to_cpu(csa->channel));
46bc8d4b 4012 il_chswitch_done(il, true);
51e65257 4013 } else {
9406f797 4014 IL_ERR("CSA notif (fail) : channel %d\n",
51e65257 4015 le16_to_cpu(csa->channel));
46bc8d4b 4016 il_chswitch_done(il, false);
be663ab6
WYG		 4017 }
4018}
d2dfb33e 4019EXPORT_SYMBOL(il_hdl_csa);
be663ab6 4020
d3175167 4021#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4022void il_print_rx_config_cmd(struct il_priv *il,
e2ebc833 4023 struct il_rxon_context *ctx)
be663ab6 4024{
e2ebc833 4025 struct il_rxon_cmd *rxon = &ctx->staging;
be663ab6 4026
58de00a4 4027 D_RADIO("RX CONFIG:\n");
46bc8d4b 4028 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
58de00a4 4029 D_RADIO("u16 channel: 0x%x\n",
be663ab6 4030 le16_to_cpu(rxon->channel));
58de00a4
SG		 4031 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4032 D_RADIO("u32 filter_flags: 0x%08x\n",
be663ab6 4033 le32_to_cpu(rxon->filter_flags));
58de00a4
SG		 4034 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4035 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
be663ab6 4036 rxon->ofdm_basic_rates);
58de00a4 4037 D_RADIO("u8 cck_basic_rates: 0x%02x\n",
be663ab6 4038 rxon->cck_basic_rates);
58de00a4
SG		 4039 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4040 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
4041 D_RADIO("u16 assoc_id: 0x%x\n",
be663ab6
WYG		 4042 le16_to_cpu(rxon->assoc_id));
4043}
e2ebc833 4044EXPORT_SYMBOL(il_print_rx_config_cmd);
be663ab6
WYG		 4045#endif
4046/**
e2ebc833 4047 * il_irq_handle_error - called for HW or SW error interrupt from card
be663ab6 4048 */
46bc8d4b 4049void il_irq_handle_error(struct il_priv *il)
be663ab6 4050{
e2ebc833 4051 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4052 set_bit(S_FW_ERROR, &il->status);
be663ab6
WYG		 4053
4054 /* Cancel currently queued command. */
a6766ccd 4055 clear_bit(S_HCMD_ACTIVE, &il->status);
be663ab6 4056
9406f797 4057 IL_ERR("Loaded firmware version: %s\n",
46bc8d4b 4058 il->hw->wiphy->fw_version);
be663ab6 4059
46bc8d4b
SG		 4060 il->cfg->ops->lib->dump_nic_error_log(il);
4061 if (il->cfg->ops->lib->dump_fh)
4062 il->cfg->ops->lib->dump_fh(il, NULL, false);
d3175167 4063#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b
SG		 4064 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
4065 il_print_rx_config_cmd(il,
7c2cde2e 4066 &il->ctx);
be663ab6
WYG		 4067#endif
4068
46bc8d4b 4069 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4070
4071 /* Keep the restart process from trying to send host
4072 * commands by clearing the INIT status bit */
a6766ccd 4073 clear_bit(S_READY, &il->status);
be663ab6 4074
a6766ccd 4075 if (!test_bit(S_EXIT_PENDING, &il->status)) {
58de00a4 4076 IL_DBG(IL_DL_FW_ERRORS,
be663ab6
WYG		 4077 "Restarting adapter due to uCode error.\n");
4078
46bc8d4b
SG		 4079 if (il->cfg->mod_params->restart_fw)
4080 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 4081 }
4082}
e2ebc833 4083EXPORT_SYMBOL(il_irq_handle_error);
be663ab6 4084
46bc8d4b 4085static int il_apm_stop_master(struct il_priv *il)
be663ab6
WYG		 4086{
4087 int ret = 0;
4088
4089 /* stop device's busmaster DMA activity */
46bc8d4b 4090 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
be663ab6 4091
142b343f 4092 ret = _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
be663ab6
WYG		 4093 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
4094 if (ret)
9406f797 4095 IL_WARN("Master Disable Timed Out, 100 usec\n");
be663ab6 4096
58de00a4 4097 D_INFO("stop master\n");
be663ab6
WYG		 4098
4099 return ret;
4100}
4101
46bc8d4b 4102void il_apm_stop(struct il_priv *il)
be663ab6 4103{
58de00a4 4104 D_INFO("Stop card, put in low power state\n");
be663ab6
WYG		 4105
4106 /* Stop device's DMA activity */
46bc8d4b 4107 il_apm_stop_master(il);
be663ab6
WYG		 4108
4109 /* Reset the entire device */
46bc8d4b 4110 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
be663ab6
WYG		 4111
4112 udelay(10);
4113
4114 /*
4115 * Clear "initialization complete" bit to move adapter from
4116 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4117 */
46bc8d4b 4118 il_clear_bit(il, CSR_GP_CNTRL,
be663ab6
WYG		 4119 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4120}
e2ebc833 4121EXPORT_SYMBOL(il_apm_stop);
be663ab6
WYG		 4122
4123
4124/*
4125 * Start up NIC's basic functionality after it has been reset
e2ebc833 4126 * (e.g. after platform boot, or shutdown via il_apm_stop())
be663ab6
WYG		 4127 * NOTE: This does not load uCode nor start the embedded processor
4128 */
46bc8d4b 4129int il_apm_init(struct il_priv *il)
be663ab6
WYG		 4130{
4131 int ret = 0;
4132 u16 lctl;
4133
58de00a4 4134 D_INFO("Init card's basic functions\n");
be663ab6
WYG		 4135
4136 /*
4137 * Use "set_bit" below rather than "write", to preserve any hardware
4138 * bits already set by default after reset.
4139 */
4140
4141 /* Disable L0S exit timer (platform NMI Work/Around) */
46bc8d4b 4142 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
be663ab6
WYG		 4143 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
4144
4145 /*
4146 * Disable L0s without affecting L1;
4147 * don't wait for ICH L0s (ICH bug W/A)
4148 */
46bc8d4b 4149 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
be663ab6
WYG		 4150 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
4151
4152 /* Set FH wait threshold to maximum (HW error during stress W/A) */
46bc8d4b 4153 il_set_bit(il, CSR_DBG_HPET_MEM_REG,
be663ab6
WYG		 4154 CSR_DBG_HPET_MEM_REG_VAL);
4155
4156 /*
4157 * Enable HAP INTA (interrupt from management bus) to
4158 * wake device's PCI Express link L1a -> L0s
25985edc 4159 * NOTE: This is no-op for 3945 (non-existent bit)
be663ab6 4160 */
46bc8d4b 4161 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
be663ab6
WYG		 4162 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
4163
4164 /*
4165 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4166 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4167 * If so (likely), disable L0S, so device moves directly L0->L1;
4168 * costs negligible amount of power savings.
4169 * If not (unlikely), enable L0S, so there is at least some
4170 * power savings, even without L1.
4171 */
46bc8d4b
SG		 4172 if (il->cfg->base_params->set_l0s) {
4173 lctl = il_pcie_link_ctl(il);
be663ab6
WYG		 4174 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
4175 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
4176 /* L1-ASPM enabled; disable(!) L0S */
46bc8d4b 4177 il_set_bit(il, CSR_GIO_REG,
be663ab6 4178 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4179 D_POWER("L1 Enabled; Disabling L0S\n");
be663ab6
WYG		 4180 } else {
4181 /* L1-ASPM disabled; enable(!) L0S */
46bc8d4b 4182 il_clear_bit(il, CSR_GIO_REG,
be663ab6 4183 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4184 D_POWER("L1 Disabled; Enabling L0S\n");
be663ab6
WYG		 4185 }
4186 }
4187
4188 /* Configure analog phase-lock-loop before activating to D0A */
46bc8d4b
SG		 4189 if (il->cfg->base_params->pll_cfg_val)
4190 il_set_bit(il, CSR_ANA_PLL_CFG,
4191 il->cfg->base_params->pll_cfg_val);
be663ab6
WYG		 4192
4193 /*
4194 * Set "initialization complete" bit to move adapter from
4195 * D0U* --> D0A* (powered-up active) state.
4196 */
46bc8d4b 4197 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6
WYG		 4198
4199 /*
4200 * Wait for clock stabilization; once stabilized, access to
db54eb57 4201 * device-internal resources is supported, e.g. il_wr_prph()
be663ab6
WYG		 4202 * and accesses to uCode SRAM.
4203 */
142b343f 4204 ret = _il_poll_bit(il, CSR_GP_CNTRL,
be663ab6
WYG		 4205 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4206 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
4207 if (ret < 0) {
58de00a4 4208 D_INFO("Failed to init the card\n");
be663ab6
WYG		 4209 goto out;
4210 }
4211
4212 /*
4213 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4214 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4215 *
4216 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4217 * do not disable clocks. This preserves any hardware bits already
4218 * set by default in "CLK_CTRL_REG" after reset.
4219 */
46bc8d4b 4220 if (il->cfg->base_params->use_bsm)
db54eb57 4221 il_wr_prph(il, APMG_CLK_EN_REG,
be663ab6
WYG		 4222 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
4223 else
db54eb57 4224 il_wr_prph(il, APMG_CLK_EN_REG,
be663ab6
WYG		 4225 APMG_CLK_VAL_DMA_CLK_RQT);
4226 udelay(20);
4227
4228 /* Disable L1-Active */
46bc8d4b 4229 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
be663ab6
WYG		 4230 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
4231
4232out:
4233 return ret;
4234}
e2ebc833 4235EXPORT_SYMBOL(il_apm_init);
be663ab6
WYG		 4236
4237
46bc8d4b 4238int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
be663ab6
WYG		 4239{
4240 int ret;
4241 s8 prev_tx_power;
43f12d47 4242 bool defer;
7c2cde2e 4243 struct il_rxon_context *ctx = &il->ctx;
be663ab6 4244
46bc8d4b 4245 lockdep_assert_held(&il->mutex);
be663ab6 4246
46bc8d4b 4247 if (il->tx_power_user_lmt == tx_power && !force)
be663ab6
WYG		 4248 return 0;
4249
46bc8d4b 4250 if (!il->cfg->ops->lib->send_tx_power)
be663ab6
WYG		 4251 return -EOPNOTSUPP;
4252
332704a5
SG		 4253 /* 0 dBm mean 1 milliwatt */
4254 if (tx_power < 0) {
9406f797 4255 IL_WARN(
332704a5
SG		 4256 "Requested user TXPOWER %d below 1 mW.\n",
4257 tx_power);
be663ab6
WYG		 4258 return -EINVAL;
4259 }
4260
46bc8d4b 4261 if (tx_power > il->tx_power_device_lmt) {
9406f797 4262 IL_WARN(
be663ab6 4263 "Requested user TXPOWER %d above upper limit %d.\n",
46bc8d4b 4264 tx_power, il->tx_power_device_lmt);
be663ab6
WYG		 4265 return -EINVAL;
4266 }
4267
46bc8d4b 4268 if (!il_is_ready_rf(il))
be663ab6
WYG		 4269 return -EIO;
4270
43f12d47
SG		 4271 /* scan complete and commit_rxon use tx_power_next value,
4272 * it always need to be updated for newest request */
46bc8d4b 4273 il->tx_power_next = tx_power;
43f12d47
SG		 4274
4275 /* do not set tx power when scanning or channel changing */
a6766ccd 4276 defer = test_bit(S_SCANNING, &il->status) ||
43f12d47
SG		 4277 memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging));
4278 if (defer && !force) {
58de00a4 4279 D_INFO("Deferring tx power set\n");
be663ab6
WYG		 4280 return 0;
4281 }
4282
46bc8d4b
SG		 4283 prev_tx_power = il->tx_power_user_lmt;
4284 il->tx_power_user_lmt = tx_power;
be663ab6 4285
46bc8d4b 4286 ret = il->cfg->ops->lib->send_tx_power(il);
be663ab6
WYG		 4287
4288 /* if fail to set tx_power, restore the orig. tx power */
4289 if (ret) {
46bc8d4b
SG		 4290 il->tx_power_user_lmt = prev_tx_power;
4291 il->tx_power_next = prev_tx_power;
be663ab6
WYG		 4292 }
4293 return ret;
4294}
e2ebc833 4295EXPORT_SYMBOL(il_set_tx_power);
be663ab6 4296
46bc8d4b 4297void il_send_bt_config(struct il_priv *il)
be663ab6 4298{
e2ebc833 4299 struct il_bt_cmd bt_cmd = {
be663ab6
WYG		 4300 .lead_time = BT_LEAD_TIME_DEF,
4301 .max_kill = BT_MAX_KILL_DEF,
4302 .kill_ack_mask = 0,
4303 .kill_cts_mask = 0,
4304 };
4305
4306 if (!bt_coex_active)
4307 bt_cmd.flags = BT_COEX_DISABLE;
4308 else
4309 bt_cmd.flags = BT_COEX_ENABLE;
4310
58de00a4 4311 D_INFO("BT coex %s\n",
be663ab6
WYG		 4312 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
4313
4d69c752 4314 if (il_send_cmd_pdu(il, C_BT_CONFIG,
e2ebc833 4315 sizeof(struct il_bt_cmd), &bt_cmd))
9406f797 4316 IL_ERR("failed to send BT Coex Config\n");
be663ab6 4317}
e2ebc833 4318EXPORT_SYMBOL(il_send_bt_config);
be663ab6 4319
ebf0d90d 4320int il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
be663ab6 4321{
ebf0d90d 4322 struct il_stats_cmd stats_cmd = {
be663ab6 4323 .configuration_flags =
e2ebc833 4324 clear ? IL_STATS_CONF_CLEAR_STATS : 0,
be663ab6
WYG		 4325 };
4326
4327 if (flags & CMD_ASYNC)
4d69c752 4328 return il_send_cmd_pdu_async(il, C_STATS,
ebf0d90d
SG		 4329 sizeof(struct il_stats_cmd),
4330 &stats_cmd, NULL);
be663ab6 4331 else
4d69c752 4332 return il_send_cmd_pdu(il, C_STATS,
ebf0d90d
SG		 4333 sizeof(struct il_stats_cmd),
4334 &stats_cmd);
be663ab6 4335}
ebf0d90d 4336EXPORT_SYMBOL(il_send_stats_request);
be663ab6 4337
d2dfb33e 4338void il_hdl_pm_sleep(struct il_priv *il,
b73bb5f1 4339 struct il_rx_buf *rxb)
be663ab6 4340{
d3175167 4341#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 4342 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4343 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
58de00a4 4344 D_RX("sleep mode: %d, src: %d\n",
be663ab6
WYG		 4345 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
4346#endif
4347}
d2dfb33e 4348EXPORT_SYMBOL(il_hdl_pm_sleep);
be663ab6 4349
d2dfb33e 4350void il_hdl_pm_debug_stats(struct il_priv *il,
b73bb5f1 4351 struct il_rx_buf *rxb)
be663ab6 4352{
dcae1c64 4353 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4354 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
58de00a4 4355 D_RADIO("Dumping %d bytes of unhandled "
be663ab6 4356 "notification for %s:\n", len,
e2ebc833 4357 il_get_cmd_string(pkt->hdr.cmd));
46bc8d4b 4358 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
be663ab6 4359}
d2dfb33e 4360EXPORT_SYMBOL(il_hdl_pm_debug_stats);
be663ab6 4361
6e9848b4 4362void il_hdl_error(struct il_priv *il,
b73bb5f1 4363 struct il_rx_buf *rxb)
be663ab6 4364{
dcae1c64 4365 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4366
9406f797 4367 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
be663ab6
WYG		 4368 "seq 0x%04X ser 0x%08X\n",
4369 le32_to_cpu(pkt->u.err_resp.error_type),
e2ebc833 4370 il_get_cmd_string(pkt->u.err_resp.cmd_id),
be663ab6
WYG		 4371 pkt->u.err_resp.cmd_id,
4372 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4373 le32_to_cpu(pkt->u.err_resp.error_info));
4374}
6e9848b4 4375EXPORT_SYMBOL(il_hdl_error);
be663ab6 4376
46bc8d4b 4377void il_clear_isr_stats(struct il_priv *il)
be663ab6 4378{
46bc8d4b 4379 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
be663ab6
WYG		 4380}
4381
e2ebc833 4382int il_mac_conf_tx(struct ieee80211_hw *hw,
8a3a3c85 4383 struct ieee80211_vif *vif, u16 queue,
be663ab6
WYG		 4384 const struct ieee80211_tx_queue_params *params)
4385{
46bc8d4b 4386 struct il_priv *il = hw->priv;
be663ab6
WYG		 4387 unsigned long flags;
4388 int q;
4389
58de00a4 4390 D_MAC80211("enter\n");
be663ab6 4391
46bc8d4b 4392 if (!il_is_ready_rf(il)) {
58de00a4 4393 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 4394 return -EIO;
4395 }
4396
4397 if (queue >= AC_NUM) {
58de00a4 4398 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
be663ab6
WYG		 4399 return 0;
4400 }
4401
4402 q = AC_NUM - 1 - queue;
4403
46bc8d4b 4404 spin_lock_irqsave(&il->lock, flags);
be663ab6 4405
17d6e557 4406 il->ctx.qos_data.def_qos_parm.ac[q].cw_min =
be663ab6 4407 cpu_to_le16(params->cw_min);
17d6e557 4408 il->ctx.qos_data.def_qos_parm.ac[q].cw_max =
be663ab6 4409 cpu_to_le16(params->cw_max);
17d6e557
SG		 4410 il->ctx.qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4411 il->ctx.qos_data.def_qos_parm.ac[q].edca_txop =
be663ab6
WYG		 4412 cpu_to_le16((params->txop * 32));
4413
17d6e557 4414 il->ctx.qos_data.def_qos_parm.ac[q].reserved1 = 0;
be663ab6 4415
46bc8d4b 4416 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 4417
58de00a4 4418 D_MAC80211("leave\n");
be663ab6
WYG		 4419 return 0;
4420}
e2ebc833 4421EXPORT_SYMBOL(il_mac_conf_tx);
be663ab6 4422
e2ebc833 4423int il_mac_tx_last_beacon(struct ieee80211_hw *hw)
be663ab6 4424{
46bc8d4b 4425 struct il_priv *il = hw->priv;
be663ab6 4426
46bc8d4b 4427 return il->ibss_manager == IL_IBSS_MANAGER;
be663ab6 4428}
e2ebc833 4429EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
be663ab6
WYG		 4430
4431static int
46bc8d4b 4432il_set_mode(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 4433{
46bc8d4b 4434 il_connection_init_rx_config(il, ctx);
be663ab6 4435
46bc8d4b
SG		 4436 if (il->cfg->ops->hcmd->set_rxon_chain)
4437 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6 4438
46bc8d4b 4439 return il_commit_rxon(il, ctx);
be663ab6
WYG		 4440}
4441
46bc8d4b 4442static int il_setup_interface(struct il_priv *il,
e2ebc833 4443 struct il_rxon_context *ctx)
be663ab6
WYG		 4444{
4445 struct ieee80211_vif *vif = ctx->vif;
4446 int err;
4447
46bc8d4b 4448 lockdep_assert_held(&il->mutex);
be663ab6
WYG		 4449
4450 /*
4451 * This variable will be correct only when there's just
4452 * a single context, but all code using it is for hardware
4453 * that supports only one context.
4454 */
46bc8d4b 4455 il->iw_mode = vif->type;
be663ab6
WYG		 4456
4457 ctx->is_active = true;
4458
46bc8d4b 4459 err = il_set_mode(il, ctx);
be663ab6
WYG		 4460 if (err) {
4461 if (!ctx->always_active)
4462 ctx->is_active = false;
4463 return err;
4464 }
4465
4466 return 0;
4467}
4468
4469int
e2ebc833 4470il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4471{
46bc8d4b 4472 struct il_priv *il = hw->priv;
e2ebc833 4473 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
be663ab6 4474 int err;
17d6e557 4475 u32 modes;
be663ab6 4476
58de00a4 4477 D_MAC80211("enter: type %d, addr %pM\n",
be663ab6
WYG		 4478 vif->type, vif->addr);
4479
46bc8d4b 4480 mutex_lock(&il->mutex);
be663ab6 4481
46bc8d4b 4482 if (!il_is_ready_rf(il)) {
9406f797 4483 IL_WARN("Try to add interface when device not ready\n");
be663ab6
WYG		 4484 err = -EINVAL;
4485 goto out;
4486 }
4487
be663ab6 4488
17d6e557
SG		 4489 /* check if busy context is exclusive */
4490 if (il->ctx.vif &&
4491 (il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type))) {
4492 err = -EINVAL;
4493 goto out;
be663ab6
WYG		 4494 }
4495
17d6e557
SG		 4496 modes = il->ctx.interface_modes | il->ctx.exclusive_interface_modes;
4497 if (!(modes & BIT(vif->type))) {
be663ab6
WYG		 4498 err = -EOPNOTSUPP;
4499 goto out;
4500 }
4501
17d6e557
SG		 4502 vif_priv->ctx = &il->ctx;
4503 il->ctx.vif = vif;
be663ab6 4504
17d6e557
SG		 4505 err = il_setup_interface(il, &il->ctx);
4506 if (err) {
4507 il->ctx.vif = NULL;
4508 il->iw_mode = NL80211_IFTYPE_STATION;
4509 }
be663ab6 4510
be663ab6 4511 out:
46bc8d4b 4512 mutex_unlock(&il->mutex);
be663ab6 4513
58de00a4 4514 D_MAC80211("leave\n");
be663ab6
WYG		 4515 return err;
4516}
e2ebc833 4517EXPORT_SYMBOL(il_mac_add_interface);
be663ab6 4518
46bc8d4b 4519static void il_teardown_interface(struct il_priv *il,
be663ab6
WYG		 4520 struct ieee80211_vif *vif,
4521 bool mode_change)
4522{
e2ebc833 4523 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 4524
46bc8d4b 4525 lockdep_assert_held(&il->mutex);
be663ab6 4526
46bc8d4b
SG		 4527 if (il->scan_vif == vif) {
4528 il_scan_cancel_timeout(il, 200);
4529 il_force_scan_end(il);
be663ab6
WYG		 4530 }
4531
4532 if (!mode_change) {
46bc8d4b 4533 il_set_mode(il, ctx);
be663ab6
WYG		 4534 if (!ctx->always_active)
4535 ctx->is_active = false;
4536 }
4537}
4538
e2ebc833 4539void il_mac_remove_interface(struct ieee80211_hw *hw,
be663ab6
WYG		 4540 struct ieee80211_vif *vif)
4541{
46bc8d4b 4542 struct il_priv *il = hw->priv;
e2ebc833 4543 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 4544
58de00a4 4545 D_MAC80211("enter\n");
be663ab6 4546
46bc8d4b 4547 mutex_lock(&il->mutex);
be663ab6
WYG		 4548
4549 WARN_ON(ctx->vif != vif);
4550 ctx->vif = NULL;
4551
46bc8d4b 4552 il_teardown_interface(il, vif, false);
be663ab6 4553
46bc8d4b
SG		 4554 memset(il->bssid, 0, ETH_ALEN);
4555 mutex_unlock(&il->mutex);
be663ab6 4556
58de00a4 4557 D_MAC80211("leave\n");
be663ab6
WYG		 4558
4559}
e2ebc833 4560EXPORT_SYMBOL(il_mac_remove_interface);
be663ab6 4561
46bc8d4b 4562int il_alloc_txq_mem(struct il_priv *il)
be663ab6 4563{
46bc8d4b
SG		 4564 if (!il->txq)
4565 il->txq = kzalloc(
e2ebc833 4566 sizeof(struct il_tx_queue) *
46bc8d4b 4567 il->cfg->base_params->num_of_queues,
be663ab6 4568 GFP_KERNEL);
46bc8d4b 4569 if (!il->txq) {
9406f797 4570 IL_ERR("Not enough memory for txq\n");
be663ab6
WYG		 4571 return -ENOMEM;
4572 }
4573 return 0;
4574}
e2ebc833 4575EXPORT_SYMBOL(il_alloc_txq_mem);
be663ab6 4576
46bc8d4b 4577void il_txq_mem(struct il_priv *il)
be663ab6 4578{
46bc8d4b
SG		 4579 kfree(il->txq);
4580 il->txq = NULL;
be663ab6 4581}
e2ebc833 4582EXPORT_SYMBOL(il_txq_mem);
be663ab6 4583
d3175167 4584#ifdef CONFIG_IWLEGACY_DEBUGFS
be663ab6 4585
e2ebc833 4586#define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES)
be663ab6 4587
46bc8d4b 4588void il_reset_traffic_log(struct il_priv *il)
be663ab6 4589{
46bc8d4b
SG		 4590 il->tx_traffic_idx = 0;
4591 il->rx_traffic_idx = 0;
4592 if (il->tx_traffic)
4593 memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
4594 if (il->rx_traffic)
4595 memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
be663ab6
WYG		 4596}
4597
46bc8d4b 4598int il_alloc_traffic_mem(struct il_priv *il)
be663ab6 4599{
e2ebc833 4600 u32 traffic_size = IL_TRAFFIC_DUMP_SIZE;
be663ab6 4601
d2ddf621 4602 if (il_debug_level & IL_DL_TX) {
46bc8d4b
SG		 4603 if (!il->tx_traffic) {
4604 il->tx_traffic =
be663ab6 4605 kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4606 if (!il->tx_traffic)
be663ab6
WYG		 4607 return -ENOMEM;
4608 }
4609 }
d2ddf621 4610 if (il_debug_level & IL_DL_RX) {
46bc8d4b
SG		 4611 if (!il->rx_traffic) {
4612 il->rx_traffic =
be663ab6 4613 kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4614 if (!il->rx_traffic)
be663ab6
WYG		 4615 return -ENOMEM;
4616 }
4617 }
46bc8d4b 4618 il_reset_traffic_log(il);
be663ab6
WYG		 4619 return 0;
4620}
e2ebc833 4621EXPORT_SYMBOL(il_alloc_traffic_mem);
be663ab6 4622
46bc8d4b 4623void il_free_traffic_mem(struct il_priv *il)
be663ab6 4624{
46bc8d4b
SG		 4625 kfree(il->tx_traffic);
4626 il->tx_traffic = NULL;
be663ab6 4627
46bc8d4b
SG		 4628 kfree(il->rx_traffic);
4629 il->rx_traffic = NULL;
be663ab6 4630}
e2ebc833 4631EXPORT_SYMBOL(il_free_traffic_mem);
be663ab6 4632
46bc8d4b 4633void il_dbg_log_tx_data_frame(struct il_priv *il,
be663ab6
WYG		 4634 u16 length, struct ieee80211_hdr *header)
4635{
4636 __le16 fc;
4637 u16 len;
4638
d2ddf621 4639 if (likely(!(il_debug_level & IL_DL_TX)))
be663ab6
WYG		 4640 return;
4641
46bc8d4b 4642 if (!il->tx_traffic)
be663ab6
WYG		 4643 return;
4644
4645 fc = header->frame_control;
4646 if (ieee80211_is_data(fc)) {
e2ebc833
SG		 4647 len = (length > IL_TRAFFIC_ENTRY_SIZE)
4648 ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b
SG		 4649 memcpy((il->tx_traffic +
4650 (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)),
be663ab6 4651 header, len);
46bc8d4b
SG		 4652 il->tx_traffic_idx =
4653 (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4654 }
4655}
e2ebc833 4656EXPORT_SYMBOL(il_dbg_log_tx_data_frame);
be663ab6 4657
46bc8d4b 4658void il_dbg_log_rx_data_frame(struct il_priv *il,
be663ab6
WYG		 4659 u16 length, struct ieee80211_hdr *header)
4660{
4661 __le16 fc;
4662 u16 len;
4663
d2ddf621 4664 if (likely(!(il_debug_level & IL_DL_RX)))
be663ab6
WYG		 4665 return;
4666
46bc8d4b 4667 if (!il->rx_traffic)
be663ab6
WYG		 4668 return;
4669
4670 fc = header->frame_control;
4671 if (ieee80211_is_data(fc)) {
e2ebc833
SG		 4672 len = (length > IL_TRAFFIC_ENTRY_SIZE)
4673 ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b
SG		 4674 memcpy((il->rx_traffic +
4675 (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)),
be663ab6 4676 header, len);
46bc8d4b
SG		 4677 il->rx_traffic_idx =
4678 (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4679 }
4680}
e2ebc833 4681EXPORT_SYMBOL(il_dbg_log_rx_data_frame);
be663ab6 4682
e2ebc833 4683const char *il_get_mgmt_string(int cmd)
be663ab6
WYG		 4684{
4685 switch (cmd) {
e2ebc833
SG		 4686 IL_CMD(MANAGEMENT_ASSOC_REQ);
4687 IL_CMD(MANAGEMENT_ASSOC_RESP);
4688 IL_CMD(MANAGEMENT_REASSOC_REQ);
4689 IL_CMD(MANAGEMENT_REASSOC_RESP);
4690 IL_CMD(MANAGEMENT_PROBE_REQ);
4691 IL_CMD(MANAGEMENT_PROBE_RESP);
4692 IL_CMD(MANAGEMENT_BEACON);
4693 IL_CMD(MANAGEMENT_ATIM);
4694 IL_CMD(MANAGEMENT_DISASSOC);
4695 IL_CMD(MANAGEMENT_AUTH);
4696 IL_CMD(MANAGEMENT_DEAUTH);
4697 IL_CMD(MANAGEMENT_ACTION);
be663ab6
WYG		 4698 default:
4699 return "UNKNOWN";
4700
4701 }
4702}
4703
e2ebc833 4704const char *il_get_ctrl_string(int cmd)
be663ab6
WYG		 4705{
4706 switch (cmd) {
e2ebc833
SG		 4707 IL_CMD(CONTROL_BACK_REQ);
4708 IL_CMD(CONTROL_BACK);
4709 IL_CMD(CONTROL_PSPOLL);
4710 IL_CMD(CONTROL_RTS);
4711 IL_CMD(CONTROL_CTS);
4712 IL_CMD(CONTROL_ACK);
4713 IL_CMD(CONTROL_CFEND);
4714 IL_CMD(CONTROL_CFENDACK);
be663ab6
WYG		 4715 default:
4716 return "UNKNOWN";
4717
4718 }
4719}
4720
46bc8d4b 4721void il_clear_traffic_stats(struct il_priv *il)
be663ab6 4722{
46bc8d4b
SG		 4723 memset(&il->tx_stats, 0, sizeof(struct traffic_stats));
4724 memset(&il->rx_stats, 0, sizeof(struct traffic_stats));
be663ab6
WYG		 4725}
4726
4727/*
d3175167 4728 * if CONFIG_IWLEGACY_DEBUGFS defined,
e2ebc833 4729 * il_update_stats function will
be663ab6 4730 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass
ebf0d90d 4731 * Use debugFs to display the rx/rx_stats
d3175167 4732 * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL
be663ab6 4733 * information will be recorded, but DATA pkt still will be recorded
e2ebc833 4734 * for the reason of il_led.c need to control the led blinking based on
be663ab6
WYG		 4735 * number of tx and rx data.
4736 *
4737 */
4738void
46bc8d4b 4739il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6
WYG		 4740{
4741 struct traffic_stats *stats;
4742
4743 if (is_tx)
46bc8d4b 4744 stats = &il->tx_stats;
be663ab6 4745 else
46bc8d4b 4746 stats = &il->rx_stats;
be663ab6
WYG		 4747
4748 if (ieee80211_is_mgmt(fc)) {
4749 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4750 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
4751 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
4752 break;
4753 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
4754 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
4755 break;
4756 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
4757 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
4758 break;
4759 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
4760 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
4761 break;
4762 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
4763 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
4764 break;
4765 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
4766 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
4767 break;
4768 case cpu_to_le16(IEEE80211_STYPE_BEACON):
4769 stats->mgmt[MANAGEMENT_BEACON]++;
4770 break;
4771 case cpu_to_le16(IEEE80211_STYPE_ATIM):
4772 stats->mgmt[MANAGEMENT_ATIM]++;
4773 break;
4774 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
4775 stats->mgmt[MANAGEMENT_DISASSOC]++;
4776 break;
4777 case cpu_to_le16(IEEE80211_STYPE_AUTH):
4778 stats->mgmt[MANAGEMENT_AUTH]++;
4779 break;
4780 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
4781 stats->mgmt[MANAGEMENT_DEAUTH]++;
4782 break;
4783 case cpu_to_le16(IEEE80211_STYPE_ACTION):
4784 stats->mgmt[MANAGEMENT_ACTION]++;
4785 break;
4786 }
4787 } else if (ieee80211_is_ctl(fc)) {
4788 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4789 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
4790 stats->ctrl[CONTROL_BACK_REQ]++;
4791 break;
4792 case cpu_to_le16(IEEE80211_STYPE_BACK):
4793 stats->ctrl[CONTROL_BACK]++;
4794 break;
4795 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
4796 stats->ctrl[CONTROL_PSPOLL]++;
4797 break;
4798 case cpu_to_le16(IEEE80211_STYPE_RTS):
4799 stats->ctrl[CONTROL_RTS]++;
4800 break;
4801 case cpu_to_le16(IEEE80211_STYPE_CTS):
4802 stats->ctrl[CONTROL_CTS]++;
4803 break;
4804 case cpu_to_le16(IEEE80211_STYPE_ACK):
4805 stats->ctrl[CONTROL_ACK]++;
4806 break;
4807 case cpu_to_le16(IEEE80211_STYPE_CFEND):
4808 stats->ctrl[CONTROL_CFEND]++;
4809 break;
4810 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
4811 stats->ctrl[CONTROL_CFENDACK]++;
4812 break;
4813 }
4814 } else {
4815 /* data */
4816 stats->data_cnt++;
4817 stats->data_bytes += len;
4818 }
4819}
e2ebc833 4820EXPORT_SYMBOL(il_update_stats);
be663ab6
WYG		 4821#endif
4822
46bc8d4b 4823int il_force_reset(struct il_priv *il, bool external)
be663ab6 4824{
e2ebc833 4825 struct il_force_reset *force_reset;
be663ab6 4826
a6766ccd 4827 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4828 return -EINVAL;
4829
46bc8d4b 4830 force_reset = &il->force_reset;
be663ab6
WYG		 4831 force_reset->reset_request_count++;
4832 if (!external) {
4833 if (force_reset->last_force_reset_jiffies &&
4834 time_after(force_reset->last_force_reset_jiffies +
4835 force_reset->reset_duration, jiffies)) {
58de00a4 4836 D_INFO("force reset rejected\n");
be663ab6
WYG		 4837 force_reset->reset_reject_count++;
4838 return -EAGAIN;
4839 }
4840 }
4841 force_reset->reset_success_count++;
4842 force_reset->last_force_reset_jiffies = jiffies;
dd6d2a8a
SG		 4843
4844 /*
4845 * if the request is from external(ex: debugfs),
4846 * then always perform the request in regardless the module
4847 * parameter setting
4848 * if the request is from internal (uCode error or driver
4849 * detect failure), then fw_restart module parameter
4850 * need to be check before performing firmware reload
4851 */
4852
46bc8d4b 4853 if (!external && !il->cfg->mod_params->restart_fw) {
58de00a4 4854 D_INFO("Cancel firmware reload based on "
dd6d2a8a
SG		 4855 "module parameter setting\n");
4856 return 0;
be663ab6 4857 }
dd6d2a8a 4858
9406f797 4859 IL_ERR("On demand firmware reload\n");
dd6d2a8a 4860
e2ebc833 4861 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4862 set_bit(S_FW_ERROR, &il->status);
46bc8d4b 4863 wake_up(&il->wait_command_queue);
dd6d2a8a
SG		 4864 /*
4865 * Keep the restart process from trying to send host
4866 * commands by clearing the INIT status bit
4867 */
a6766ccd 4868 clear_bit(S_READY, &il->status);
46bc8d4b 4869 queue_work(il->workqueue, &il->restart);
dd6d2a8a 4870
be663ab6
WYG		 4871 return 0;
4872}
4873
4874int
e2ebc833 4875il_mac_change_interface(struct ieee80211_hw *hw,
be663ab6
WYG		 4876 struct ieee80211_vif *vif,
4877 enum nl80211_iftype newtype, bool newp2p)
4878{
46bc8d4b 4879 struct il_priv *il = hw->priv;
e2ebc833 4880 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
17d6e557 4881 u32 modes;
be663ab6
WYG		 4882 int err;
4883
4884 newtype = ieee80211_iftype_p2p(newtype, newp2p);
4885
46bc8d4b 4886 mutex_lock(&il->mutex);
be663ab6 4887
46bc8d4b 4888 if (!ctx->vif || !il_is_ready_rf(il)) {
ffd8c746
JB		 4889 /*
4890 * Huh? But wait ... this can maybe happen when
4891 * we're in the middle of a firmware restart!
4892 */
4893 err = -EBUSY;
4894 goto out;
4895 }
4896
17d6e557
SG		 4897 modes = ctx->interface_modes | ctx->exclusive_interface_modes;
4898 if (!(modes & BIT(newtype))) {
4899 err = -EOPNOTSUPP;
be663ab6
WYG		 4900 goto out;
4901 }
4902
17d6e557
SG		 4903 if ((il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type)) ||
4904 (il->ctx.exclusive_interface_modes & BIT(newtype))) {
4905 err = -EINVAL;
4906 goto out;
be663ab6
WYG		 4907 }
4908
4909 /* success */
46bc8d4b 4910 il_teardown_interface(il, vif, true);
be663ab6 4911 vif->type = newtype;
ffd8c746 4912 vif->p2p = newp2p;
46bc8d4b 4913 err = il_setup_interface(il, ctx);
be663ab6
WYG		 4914 WARN_ON(err);
4915 /*
4916 * We've switched internally, but submitting to the
4917 * device may have failed for some reason. Mask this
4918 * error, because otherwise mac80211 will not switch
4919 * (and set the interface type back) and we'll be
4920 * out of sync with it.
4921 */
4922 err = 0;
4923
4924 out:
46bc8d4b 4925 mutex_unlock(&il->mutex);
be663ab6
WYG		 4926 return err;
4927}
e2ebc833 4928EXPORT_SYMBOL(il_mac_change_interface);
be663ab6
WYG		 4929
4930/*
4931 * On every watchdog tick we check (latest) time stamp. If it does not
4932 * change during timeout period and queue is not empty we reset firmware.
4933 */
46bc8d4b 4934static int il_check_stuck_queue(struct il_priv *il, int cnt)
be663ab6 4935{
46bc8d4b 4936 struct il_tx_queue *txq = &il->txq[cnt];
e2ebc833 4937 struct il_queue *q = &txq->q;
be663ab6
WYG		 4938 unsigned long timeout;
4939 int ret;
4940
4941 if (q->read_ptr == q->write_ptr) {
4942 txq->time_stamp = jiffies;
4943 return 0;
4944 }
4945
4946 timeout = txq->time_stamp +
46bc8d4b 4947 msecs_to_jiffies(il->cfg->base_params->wd_timeout);
be663ab6
WYG		 4948
4949 if (time_after(jiffies, timeout)) {
9406f797 4950 IL_ERR("Queue %d stuck for %u ms.\n",
46bc8d4b
SG		 4951 q->id, il->cfg->base_params->wd_timeout);
4952 ret = il_force_reset(il, false);
be663ab6
WYG		 4953 return (ret == -EAGAIN) ? 0 : 1;
4954 }
4955
4956 return 0;
4957}
4958
4959/*
4960 * Making watchdog tick be a quarter of timeout assure we will
4961 * discover the queue hung between timeout and 1.25*timeout
4962 */
e2ebc833 4963#define IL_WD_TICK(timeout) ((timeout) / 4)
be663ab6
WYG		 4964
4965/*
4966 * Watchdog timer callback, we check each tx queue for stuck, if if hung
4967 * we reset the firmware. If everything is fine just rearm the timer.
4968 */
e2ebc833 4969void il_bg_watchdog(unsigned long data)
be663ab6 4970{
46bc8d4b 4971 struct il_priv *il = (struct il_priv *)data;
be663ab6
WYG		 4972 int cnt;
4973 unsigned long timeout;
4974
a6766ccd 4975 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4976 return;
4977
46bc8d4b 4978 timeout = il->cfg->base_params->wd_timeout;
be663ab6
WYG		 4979 if (timeout == 0)
4980 return;
4981
4982 /* monitor and check for stuck cmd queue */
46bc8d4b 4983 if (il_check_stuck_queue(il, il->cmd_queue))
be663ab6
WYG		 4984 return;
4985
4986 /* monitor and check for other stuck queues */
46bc8d4b
SG		 4987 if (il_is_any_associated(il)) {
4988 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
be663ab6 4989 /* skip as we already checked the command queue */
46bc8d4b 4990 if (cnt == il->cmd_queue)
be663ab6 4991 continue;
46bc8d4b 4992 if (il_check_stuck_queue(il, cnt))
be663ab6
WYG		 4993 return;
4994 }
4995 }
4996
46bc8d4b 4997 mod_timer(&il->watchdog, jiffies +
e2ebc833 4998 msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 4999}
e2ebc833 5000EXPORT_SYMBOL(il_bg_watchdog);
be663ab6 5001
46bc8d4b 5002void il_setup_watchdog(struct il_priv *il)
be663ab6 5003{
46bc8d4b 5004 unsigned int timeout = il->cfg->base_params->wd_timeout;
be663ab6
WYG		 5005
5006 if (timeout)
46bc8d4b 5007 mod_timer(&il->watchdog,
e2ebc833 5008 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 5009 else
46bc8d4b 5010 del_timer(&il->watchdog);
be663ab6 5011}
e2ebc833 5012EXPORT_SYMBOL(il_setup_watchdog);
be663ab6
WYG		 5013
5014/*
5015 * extended beacon time format
5016 * time in usec will be changed into a 32-bit value in extended:internal format
5017 * the extended part is the beacon counts
5018 * the internal part is the time in usec within one beacon interval
5019 */
5020u32
46bc8d4b 5021il_usecs_to_beacons(struct il_priv *il,
be663ab6
WYG		 5022 u32 usec, u32 beacon_interval)
5023{
5024 u32 quot;
5025 u32 rem;
5026 u32 interval = beacon_interval * TIME_UNIT;
5027
5028 if (!interval || !usec)
5029 return 0;
5030
5031 quot = (usec / interval) &
46bc8d4b
SG		 5032 (il_beacon_time_mask_high(il,
5033 il->hw_params.beacon_time_tsf_bits) >>
5034 il->hw_params.beacon_time_tsf_bits);
5035 rem = (usec % interval) & il_beacon_time_mask_low(il,
5036 il->hw_params.beacon_time_tsf_bits);
be663ab6 5037
46bc8d4b 5038 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
be663ab6 5039}
e2ebc833 5040EXPORT_SYMBOL(il_usecs_to_beacons);
be663ab6
WYG		 5041
5042/* base is usually what we get from ucode with each received frame,
5043 * the same as HW timer counter counting down
5044 */
46bc8d4b 5045__le32 il_add_beacon_time(struct il_priv *il, u32 base,
be663ab6
WYG		 5046 u32 addon, u32 beacon_interval)
5047{
46bc8d4b
SG		 5048 u32 base_low = base & il_beacon_time_mask_low(il,
5049 il->hw_params.beacon_time_tsf_bits);
5050 u32 addon_low = addon & il_beacon_time_mask_low(il,
5051 il->hw_params.beacon_time_tsf_bits);
be663ab6 5052 u32 interval = beacon_interval * TIME_UNIT;
46bc8d4b
SG		 5053 u32 res = (base & il_beacon_time_mask_high(il,
5054 il->hw_params.beacon_time_tsf_bits)) +
5055 (addon & il_beacon_time_mask_high(il,
5056 il->hw_params.beacon_time_tsf_bits));
be663ab6
WYG		 5057
5058 if (base_low > addon_low)
5059 res += base_low - addon_low;
5060 else if (base_low < addon_low) {
5061 res += interval + base_low - addon_low;
46bc8d4b 5062 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6 5063 } else
46bc8d4b 5064 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6
WYG		 5065
5066 return cpu_to_le32(res);
5067}
e2ebc833 5068EXPORT_SYMBOL(il_add_beacon_time);
be663ab6
WYG		 5069
5070#ifdef CONFIG_PM
5071
e2ebc833 5072int il_pci_suspend(struct device *device)
be663ab6
WYG		 5073{
5074 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5075 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5076
5077 /*
5078 * This function is called when system goes into suspend state
e2ebc833
SG		 5079 * mac80211 will call il_mac_stop() from the mac80211 suspend function
5080 * first but since il_mac_stop() has no knowledge of who the caller is,
be663ab6
WYG		 5081 * it will not call apm_ops.stop() to stop the DMA operation.
5082 * Calling apm_ops.stop here to make sure we stop the DMA.
5083 */
46bc8d4b 5084 il_apm_stop(il);
be663ab6
WYG		 5085
5086 return 0;
5087}
e2ebc833 5088EXPORT_SYMBOL(il_pci_suspend);
be663ab6 5089
e2ebc833 5090int il_pci_resume(struct device *device)
be663ab6
WYG		 5091{
5092 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5093 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5094 bool hw_rfkill = false;
5095
5096 /*
5097 * We disable the RETRY_TIMEOUT register (0x41) to keep
5098 * PCI Tx retries from interfering with C3 CPU state.
5099 */
5100 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
5101
46bc8d4b 5102 il_enable_interrupts(il);
be663ab6 5103
841b2cca 5104 if (!(_il_rd(il, CSR_GP_CNTRL) &
be663ab6
WYG		 5105 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
5106 hw_rfkill = true;
5107
5108 if (hw_rfkill)
a6766ccd 5109 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 5110 else
a6766ccd 5111 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 5112
46bc8d4b 5113 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
be663ab6
WYG		 5114
5115 return 0;
5116}
e2ebc833 5117EXPORT_SYMBOL(il_pci_resume);
be663ab6 5118
e2ebc833
SG		 5119const struct dev_pm_ops il_pm_ops = {
5120 .suspend = il_pci_suspend,
5121 .resume = il_pci_resume,
5122 .freeze = il_pci_suspend,
5123 .thaw = il_pci_resume,
5124 .poweroff = il_pci_suspend,
5125 .restore = il_pci_resume,
be663ab6 5126};
e2ebc833 5127EXPORT_SYMBOL(il_pm_ops);
be663ab6
WYG		 5128
5129#endif /* CONFIG_PM */
5130
5131static void
46bc8d4b 5132il_update_qos(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 5133{
a6766ccd 5134 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5135 return;
5136
5137 if (!ctx->is_active)
5138 return;
5139
5140 ctx->qos_data.def_qos_parm.qos_flags = 0;
5141
5142 if (ctx->qos_data.qos_active)
5143 ctx->qos_data.def_qos_parm.qos_flags |=
5144 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
5145
5146 if (ctx->ht.enabled)
5147 ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
5148
58de00a4 5149 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
be663ab6
WYG		 5150 ctx->qos_data.qos_active,
5151 ctx->qos_data.def_qos_parm.qos_flags);
5152
46bc8d4b 5153 il_send_cmd_pdu_async(il, ctx->qos_cmd,
e2ebc833 5154 sizeof(struct il_qosparam_cmd),
be663ab6
WYG		 5155 &ctx->qos_data.def_qos_parm, NULL);
5156}
5157
5158/**
e2ebc833 5159 * il_mac_config - mac80211 config callback
be663ab6 5160 */
e2ebc833 5161int il_mac_config(struct ieee80211_hw *hw, u32 changed)
be663ab6 5162{
46bc8d4b 5163 struct il_priv *il = hw->priv;
e2ebc833 5164 const struct il_channel_info *ch_info;
be663ab6
WYG		 5165 struct ieee80211_conf *conf = &hw->conf;
5166 struct ieee80211_channel *channel = conf->channel;
46bc8d4b 5167 struct il_ht_config *ht_conf = &il->current_ht_config;
17d6e557 5168 struct il_rxon_context *ctx = &il->ctx;
be663ab6
WYG		 5169 unsigned long flags = 0;
5170 int ret = 0;
5171 u16 ch;
5172 int scan_active = 0;
7c2cde2e 5173 bool ht_changed = false;
be663ab6 5174
46bc8d4b 5175 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG		 5176 return -EOPNOTSUPP;
5177
46bc8d4b 5178 mutex_lock(&il->mutex);
be663ab6 5179
58de00a4 5180 D_MAC80211("enter to channel %d changed 0x%X\n",
be663ab6
WYG		 5181 channel->hw_value, changed);
5182
a6766ccd 5183 if (unlikely(test_bit(S_SCANNING, &il->status))) {
be663ab6 5184 scan_active = 1;
58de00a4 5185 D_MAC80211("scan active\n");
be663ab6
WYG		 5186 }
5187
5188 if (changed & (IEEE80211_CONF_CHANGE_SMPS |
5189 IEEE80211_CONF_CHANGE_CHANNEL)) {
5190 /* mac80211 uses static for non-HT which is what we want */
46bc8d4b 5191 il->current_ht_config.smps = conf->smps_mode;
be663ab6
WYG		 5192
5193 /*
5194 * Recalculate chain counts.
5195 *
5196 * If monitor mode is enabled then mac80211 will
5197 * set up the SM PS mode to OFF if an HT channel is
5198 * configured.
5199 */
46bc8d4b 5200 if (il->cfg->ops->hcmd->set_rxon_chain)
17d6e557 5201 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
be663ab6
WYG		 5202 }
5203
5204 /* during scanning mac80211 will delay channel setting until
5205 * scan finish with changed = 0
5206 */
5207 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
17d6e557 5208
be663ab6
WYG		 5209 if (scan_active)
5210 goto set_ch_out;
5211
5212 ch = channel->hw_value;
46bc8d4b 5213 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5214 if (!il_is_channel_valid(ch_info)) {
58de00a4 5215 D_MAC80211("leave - invalid channel\n");
be663ab6
WYG		 5216 ret = -EINVAL;
5217 goto set_ch_out;
5218 }
5219
46bc8d4b 5220 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
e2ebc833 5221 !il_is_channel_ibss(ch_info)) {
58de00a4 5222 D_MAC80211("leave - not IBSS channel\n");
eb85de3f
SG		 5223 ret = -EINVAL;
5224 goto set_ch_out;
5225 }
5226
46bc8d4b 5227 spin_lock_irqsave(&il->lock, flags);
be663ab6 5228
17d6e557
SG		 5229 /* Configure HT40 channels */
5230 if (ctx->ht.enabled != conf_is_ht(conf)) {
5231 ctx->ht.enabled = conf_is_ht(conf);
5232 ht_changed = true;
5233 }
5234 if (ctx->ht.enabled) {
5235 if (conf_is_ht40_minus(conf)) {
5236 ctx->ht.extension_chan_offset =
5237 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
5238 ctx->ht.is_40mhz = true;
5239 } else if (conf_is_ht40_plus(conf)) {
5240 ctx->ht.extension_chan_offset =
5241 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
5242 ctx->ht.is_40mhz = true;
5243 } else {
5244 ctx->ht.extension_chan_offset =
5245 IEEE80211_HT_PARAM_CHA_SEC_NONE;
be663ab6 5246 ctx->ht.is_40mhz = false;
17d6e557
SG		 5247 }
5248 } else
5249 ctx->ht.is_40mhz = false;
be663ab6 5250
17d6e557
SG		 5251 /*
5252 * Default to no protection. Protection mode will
5253 * later be set from BSS config in il_ht_conf
5254 */
5255 ctx->ht.protection =
5256 IEEE80211_HT_OP_MODE_PROTECTION_NONE;
be663ab6 5257
17d6e557
SG		 5258 /* if we are switching from ht to 2.4 clear flags
5259 * from any ht related info since 2.4 does not
5260 * support ht */
5261 if ((le16_to_cpu(ctx->staging.channel) != ch))
5262 ctx->staging.flags = 0;
be663ab6 5263
17d6e557
SG		 5264 il_set_rxon_channel(il, channel, ctx);
5265 il_set_rxon_ht(il, ht_conf);
be663ab6 5266
17d6e557
SG		 5267 il_set_flags_for_band(il, ctx, channel->band,
5268 ctx->vif);
be663ab6 5269
46bc8d4b 5270 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5271
46bc8d4b 5272 if (il->cfg->ops->legacy->update_bcast_stations)
be663ab6 5273 ret =
46bc8d4b 5274 il->cfg->ops->legacy->update_bcast_stations(il);
be663ab6
WYG		 5275
5276 set_ch_out:
5277 /* The list of supported rates and rate mask can be different
5278 * for each band; since the band may have changed, reset
5279 * the rate mask to what mac80211 lists */
46bc8d4b 5280 il_set_rate(il);
be663ab6
WYG		 5281 }
5282
5283 if (changed & (IEEE80211_CONF_CHANGE_PS |
5284 IEEE80211_CONF_CHANGE_IDLE)) {
46bc8d4b 5285 ret = il_power_update_mode(il, false);
be663ab6 5286 if (ret)
58de00a4 5287 D_MAC80211("Error setting sleep level\n");
be663ab6
WYG		 5288 }
5289
5290 if (changed & IEEE80211_CONF_CHANGE_POWER) {
58de00a4 5291 D_MAC80211("TX Power old=%d new=%d\n",
46bc8d4b 5292 il->tx_power_user_lmt, conf->power_level);
be663ab6 5293
46bc8d4b 5294 il_set_tx_power(il, conf->power_level, false);
be663ab6
WYG		 5295 }
5296
46bc8d4b 5297 if (!il_is_ready(il)) {
58de00a4 5298 D_MAC80211("leave - not ready\n");
be663ab6
WYG		 5299 goto out;
5300 }
5301
5302 if (scan_active)
5303 goto out;
5304
17d6e557
SG		 5305 if (memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)))
5306 il_commit_rxon(il, ctx);
5307 else
5308 D_INFO("Not re-sending same RXON configuration.\n");
5309 if (ht_changed)
5310 il_update_qos(il, ctx);
be663ab6
WYG		 5311
5312out:
58de00a4 5313 D_MAC80211("leave\n");
46bc8d4b 5314 mutex_unlock(&il->mutex);
be663ab6
WYG		 5315 return ret;
5316}
e2ebc833 5317EXPORT_SYMBOL(il_mac_config);
be663ab6 5318
e2ebc833 5319void il_mac_reset_tsf(struct ieee80211_hw *hw,
37a41b4a 5320 struct ieee80211_vif *vif)
be663ab6 5321{
46bc8d4b 5322 struct il_priv *il = hw->priv;
be663ab6 5323 unsigned long flags;
7c2cde2e 5324 struct il_rxon_context *ctx = &il->ctx;
be663ab6 5325
46bc8d4b 5326 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG		 5327 return;
5328
46bc8d4b 5329 mutex_lock(&il->mutex);
58de00a4 5330 D_MAC80211("enter\n");
be663ab6 5331
46bc8d4b
SG		 5332 spin_lock_irqsave(&il->lock, flags);
5333 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
5334 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5335
46bc8d4b 5336 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5337
5338 /* new association get rid of ibss beacon skb */
46bc8d4b
SG		 5339 if (il->beacon_skb)
5340 dev_kfree_skb(il->beacon_skb);
be663ab6 5341
46bc8d4b 5342 il->beacon_skb = NULL;
be663ab6 5343
46bc8d4b 5344 il->timestamp = 0;
be663ab6 5345
46bc8d4b 5346 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5347
46bc8d4b
SG		 5348 il_scan_cancel_timeout(il, 100);
5349 if (!il_is_ready_rf(il)) {
58de00a4 5350 D_MAC80211("leave - not ready\n");
46bc8d4b 5351 mutex_unlock(&il->mutex);
be663ab6
WYG		 5352 return;
5353 }
5354
5355 /* we are restarting association process
5356 * clear RXON_FILTER_ASSOC_MSK bit
5357 */
5358 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
46bc8d4b 5359 il_commit_rxon(il, ctx);
be663ab6 5360
46bc8d4b 5361 il_set_rate(il);
be663ab6 5362
46bc8d4b 5363 mutex_unlock(&il->mutex);
be663ab6 5364
58de00a4 5365 D_MAC80211("leave\n");
be663ab6 5366}
e2ebc833 5367EXPORT_SYMBOL(il_mac_reset_tsf);
be663ab6 5368
46bc8d4b 5369static void il_ht_conf(struct il_priv *il,
be663ab6
WYG		 5370 struct ieee80211_vif *vif)
5371{
46bc8d4b 5372 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5373 struct ieee80211_sta *sta;
5374 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
e2ebc833 5375 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 5376
58de00a4 5377 D_ASSOC("enter:\n");
be663ab6
WYG		 5378
5379 if (!ctx->ht.enabled)
5380 return;
5381
5382 ctx->ht.protection =
5383 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
5384 ctx->ht.non_gf_sta_present =
5385 !!(bss_conf->ht_operation_mode &
5386 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5387
5388 ht_conf->single_chain_sufficient = false;
5389
5390 switch (vif->type) {
5391 case NL80211_IFTYPE_STATION:
5392 rcu_read_lock();
5393 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5394 if (sta) {
5395 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5396 int maxstreams;
5397
5398 maxstreams = (ht_cap->mcs.tx_params &
5399 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5400 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
5401 maxstreams += 1;
5402
232913b5
SG		 5403 if (ht_cap->mcs.rx_mask[1] == 0 &&
5404 ht_cap->mcs.rx_mask[2] == 0)
be663ab6
WYG		 5405 ht_conf->single_chain_sufficient = true;
5406 if (maxstreams <= 1)
5407 ht_conf->single_chain_sufficient = true;
5408 } else {
5409 /*
5410 * If at all, this can only happen through a race
5411 * when the AP disconnects us while we're still
5412 * setting up the connection, in that case mac80211
5413 * will soon tell us about that.
5414 */
5415 ht_conf->single_chain_sufficient = true;
5416 }
5417 rcu_read_unlock();
5418 break;
5419 case NL80211_IFTYPE_ADHOC:
5420 ht_conf->single_chain_sufficient = true;
5421 break;
5422 default:
5423 break;
5424 }
5425
58de00a4 5426 D_ASSOC("leave\n");
be663ab6
WYG		 5427}
5428
46bc8d4b 5429static inline void il_set_no_assoc(struct il_priv *il,
be663ab6
WYG		 5430 struct ieee80211_vif *vif)
5431{
e2ebc833 5432 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6
WYG		 5433
5434 /*
5435 * inform the ucode that there is no longer an
5436 * association and that no more packets should be
5437 * sent
5438 */
5439 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5440 ctx->staging.assoc_id = 0;
46bc8d4b 5441 il_commit_rxon(il, ctx);
be663ab6
WYG		 5442}
5443
e2ebc833 5444static void il_beacon_update(struct ieee80211_hw *hw,
be663ab6
WYG		 5445 struct ieee80211_vif *vif)
5446{
46bc8d4b 5447 struct il_priv *il = hw->priv;
be663ab6
WYG		 5448 unsigned long flags;
5449 __le64 timestamp;
5450 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5451
5452 if (!skb)
5453 return;
5454
58de00a4 5455 D_MAC80211("enter\n");
be663ab6 5456
46bc8d4b 5457 lockdep_assert_held(&il->mutex);
be663ab6 5458
46bc8d4b 5459 if (!il->beacon_ctx) {
9406f797 5460 IL_ERR("update beacon but no beacon context!\n");
be663ab6
WYG		 5461 dev_kfree_skb(skb);
5462 return;
5463 }
5464
46bc8d4b 5465 spin_lock_irqsave(&il->lock, flags);
be663ab6 5466
46bc8d4b
SG		 5467 if (il->beacon_skb)
5468 dev_kfree_skb(il->beacon_skb);
be663ab6 5469
46bc8d4b 5470 il->beacon_skb = skb;
be663ab6
WYG		 5471
5472 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
46bc8d4b 5473 il->timestamp = le64_to_cpu(timestamp);
be663ab6 5474
58de00a4 5475 D_MAC80211("leave\n");
46bc8d4b 5476 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5477
46bc8d4b 5478 if (!il_is_ready_rf(il)) {
58de00a4 5479 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 5480 return;
5481 }
5482
46bc8d4b 5483 il->cfg->ops->legacy->post_associate(il);
be663ab6
WYG		 5484}
5485
e2ebc833 5486void il_mac_bss_info_changed(struct ieee80211_hw *hw,
be663ab6
WYG		 5487 struct ieee80211_vif *vif,
5488 struct ieee80211_bss_conf *bss_conf,
5489 u32 changes)
5490{
46bc8d4b 5491 struct il_priv *il = hw->priv;
e2ebc833 5492 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6
WYG		 5493 int ret;
5494
46bc8d4b 5495 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG		 5496 return;
5497
58de00a4 5498 D_MAC80211("changes = 0x%X\n", changes);
be663ab6 5499
46bc8d4b 5500 mutex_lock(&il->mutex);
be663ab6 5501
46bc8d4b
SG		 5502 if (!il_is_alive(il)) {
5503 mutex_unlock(&il->mutex);
28a6e577
SG		 5504 return;
5505 }
5506
be663ab6
WYG		 5507 if (changes & BSS_CHANGED_QOS) {
5508 unsigned long flags;
5509
46bc8d4b 5510 spin_lock_irqsave(&il->lock, flags);
be663ab6 5511 ctx->qos_data.qos_active = bss_conf->qos;
46bc8d4b
SG		 5512 il_update_qos(il, ctx);
5513 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5514 }
5515
5516 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5517 /*
5518 * the add_interface code must make sure we only ever
5519 * have a single interface that could be beaconing at
5520 * any time.
5521 */
5522 if (vif->bss_conf.enable_beacon)
46bc8d4b 5523 il->beacon_ctx = ctx;
be663ab6 5524 else
46bc8d4b 5525 il->beacon_ctx = NULL;
be663ab6
WYG		 5526 }
5527
5528 if (changes & BSS_CHANGED_BSSID) {
58de00a4 5529 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
be663ab6
WYG		 5530
5531 /*
5532 * If there is currently a HW scan going on in the
5533 * background then we need to cancel it else the RXON
5534 * below/in post_associate will fail.
5535 */
46bc8d4b 5536 if (il_scan_cancel_timeout(il, 100)) {
9406f797 5537 IL_WARN(
be663ab6 5538 "Aborted scan still in progress after 100ms\n");
58de00a4 5539 D_MAC80211(
be663ab6 5540 "leaving - scan abort failed.\n");
46bc8d4b 5541 mutex_unlock(&il->mutex);
be663ab6
WYG		 5542 return;
5543 }
5544
5545 /* mac80211 only sets assoc when in STATION mode */
5546 if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
5547 memcpy(ctx->staging.bssid_addr,
5548 bss_conf->bssid, ETH_ALEN);
5549
5550 /* currently needed in a few places */
46bc8d4b 5551 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
be663ab6
WYG		 5552 } else {
5553 ctx->staging.filter_flags &=
5554 ~RXON_FILTER_ASSOC_MSK;
5555 }
5556
5557 }
5558
5559 /*
5560 * This needs to be after setting the BSSID in case
5561 * mac80211 decides to do both changes at once because
5562 * it will invoke post_associate.
5563 */
232913b5 5564 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
e2ebc833 5565 il_beacon_update(hw, vif);
be663ab6
WYG		 5566
5567 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
58de00a4 5568 D_MAC80211("ERP_PREAMBLE %d\n",
be663ab6
WYG		 5569 bss_conf->use_short_preamble);
5570 if (bss_conf->use_short_preamble)
5571 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
5572 else
5573 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
5574 }
5575
5576 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
58de00a4 5577 D_MAC80211(
be663ab6 5578 "ERP_CTS %d\n", bss_conf->use_cts_prot);
232913b5 5579 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
be663ab6
WYG		 5580 ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
5581 else
5582 ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
5583 if (bss_conf->use_cts_prot)
5584 ctx->staging.flags |= RXON_FLG_SELF_CTS_EN;
5585 else
5586 ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
5587 }
5588
5589 if (changes & BSS_CHANGED_BASIC_RATES) {
5590 /* XXX use this information
5591 *
e2ebc833 5592 * To do that, remove code from il_set_rate() and put something
be663ab6
WYG		 5593 * like this here:
5594 *
5595 if (A-band)
5596 ctx->staging.ofdm_basic_rates =
5597 bss_conf->basic_rates;
5598 else
5599 ctx->staging.ofdm_basic_rates =
5600 bss_conf->basic_rates >> 4;
5601 ctx->staging.cck_basic_rates =
5602 bss_conf->basic_rates & 0xF;
5603 */
5604 }
5605
5606 if (changes & BSS_CHANGED_HT) {
46bc8d4b 5607 il_ht_conf(il, vif);
be663ab6 5608
46bc8d4b
SG		 5609 if (il->cfg->ops->hcmd->set_rxon_chain)
5610 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6
WYG		 5611 }
5612
5613 if (changes & BSS_CHANGED_ASSOC) {
58de00a4 5614 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
be663ab6 5615 if (bss_conf->assoc) {
46bc8d4b 5616 il->timestamp = bss_conf->timestamp;
be663ab6 5617
46bc8d4b
SG		 5618 if (!il_is_rfkill(il))
5619 il->cfg->ops->legacy->post_associate(il);
be663ab6 5620 } else
46bc8d4b 5621 il_set_no_assoc(il, vif);
be663ab6
WYG		 5622 }
5623
e2ebc833 5624 if (changes && il_is_associated_ctx(ctx) && bss_conf->aid) {
58de00a4 5625 D_MAC80211("Changes (%#x) while associated\n",
be663ab6 5626 changes);
46bc8d4b 5627 ret = il_send_rxon_assoc(il, ctx);
be663ab6
WYG		 5628 if (!ret) {
5629 /* Sync active_rxon with latest change. */
5630 memcpy((void *)&ctx->active,
5631 &ctx->staging,
e2ebc833 5632 sizeof(struct il_rxon_cmd));
be663ab6
WYG		 5633 }
5634 }
5635
5636 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5637 if (vif->bss_conf.enable_beacon) {
5638 memcpy(ctx->staging.bssid_addr,
5639 bss_conf->bssid, ETH_ALEN);
46bc8d4b
SG		 5640 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
5641 il->cfg->ops->legacy->config_ap(il);
be663ab6 5642 } else
46bc8d4b 5643 il_set_no_assoc(il, vif);
be663ab6
WYG		 5644 }
5645
5646 if (changes & BSS_CHANGED_IBSS) {
46bc8d4b 5647 ret = il->cfg->ops->legacy->manage_ibss_station(il, vif,
be663ab6
WYG		 5648 bss_conf->ibss_joined);
5649 if (ret)
9406f797 5650 IL_ERR("failed to %s IBSS station %pM\n",
be663ab6
WYG		 5651 bss_conf->ibss_joined ? "add" : "remove",
5652 bss_conf->bssid);
5653 }
5654
46bc8d4b 5655 mutex_unlock(&il->mutex);
be663ab6 5656
58de00a4 5657 D_MAC80211("leave\n");
be663ab6 5658}
e2ebc833 5659EXPORT_SYMBOL(il_mac_bss_info_changed);
be663ab6 5660
e2ebc833 5661irqreturn_t il_isr(int irq, void *data)
be663ab6 5662{
46bc8d4b 5663 struct il_priv *il = data;
be663ab6
WYG		 5664 u32 inta, inta_mask;
5665 u32 inta_fh;
5666 unsigned long flags;
46bc8d4b 5667 if (!il)
be663ab6
WYG		 5668 return IRQ_NONE;
5669
46bc8d4b 5670 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5671
5672 /* Disable (but don't clear!) interrupts here to avoid
5673 * back-to-back ISRs and sporadic interrupts from our NIC.
5674 * If we have something to service, the tasklet will re-enable ints.
5675 * If we *don't* have something, we'll re-enable before leaving here. */
841b2cca
SG		 5676 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
5677 _il_wr(il, CSR_INT_MASK, 0x00000000);
be663ab6
WYG		 5678
5679 /* Discover which interrupts are active/pending */
841b2cca
SG		 5680 inta = _il_rd(il, CSR_INT);
5681 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
be663ab6
WYG		 5682
5683 /* Ignore interrupt if there's nothing in NIC to service.
5684 * This may be due to IRQ shared with another device,
5685 * or due to sporadic interrupts thrown from our NIC. */
5686 if (!inta && !inta_fh) {
58de00a4 5687 D_ISR(
be663ab6
WYG		 5688 "Ignore interrupt, inta == 0, inta_fh == 0\n");
5689 goto none;
5690 }
5691
232913b5 5692 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
be663ab6
WYG		 5693 /* Hardware disappeared. It might have already raised
5694 * an interrupt */
9406f797 5695 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
be663ab6
WYG		 5696 goto unplugged;
5697 }
5698
58de00a4 5699 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
be663ab6
WYG		 5700 inta, inta_mask, inta_fh);
5701
5702 inta &= ~CSR_INT_BIT_SCD;
5703
e2ebc833 5704 /* il_irq_tasklet() will service interrupts and re-enable them */
be663ab6 5705 if (likely(inta || inta_fh))
46bc8d4b 5706 tasklet_schedule(&il->irq_tasklet);
be663ab6
WYG		 5707
5708unplugged:
46bc8d4b 5709 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5710 return IRQ_HANDLED;
5711
5712none:
5713 /* re-enable interrupts here since we don't have anything to service. */
93fd74e3 5714 /* only Re-enable if disabled by irq */
a6766ccd 5715 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b
SG		 5716 il_enable_interrupts(il);
5717 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5718 return IRQ_NONE;
5719}
e2ebc833 5720EXPORT_SYMBOL(il_isr);
be663ab6
WYG		 5721
5722/*
e2ebc833 5723 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
be663ab6
WYG		 5724 * function.
5725 */
46bc8d4b 5726void il_tx_cmd_protection(struct il_priv *il,
be663ab6
WYG		 5727 struct ieee80211_tx_info *info,
5728 __le16 fc, __le32 *tx_flags)
5729{
5730 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5731 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5732 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5733 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5734
5735 if (!ieee80211_is_mgmt(fc))
5736 return;
5737
5738 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5739 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5740 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5741 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5742 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5743 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5744 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5745 break;
5746 }
5747 } else if (info->control.rates[0].flags &
5748 IEEE80211_TX_RC_USE_CTS_PROTECT) {
5749 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5750 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5751 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5752 }
5753}
e2ebc833 5754EXPORT_SYMBOL(il_tx_cmd_protection);
Linux kernel - Deliverables
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