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be663ab6 WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/sched.h> | |
33 | #include <linux/slab.h> | |
0cdc2136 SG |
34 | #include <linux/types.h> |
35 | #include <linux/lockdep.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/skbuff.h> | |
be663ab6 WYG |
41 | #include <net/mac80211.h> |
42 | ||
98613be0 | 43 | #include "common.h" |
be663ab6 | 44 | |
17d4eca6 SG |
45 | int |
46 | _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout) | |
47 | { | |
48 | const int interval = 10; /* microseconds */ | |
49 | int t = 0; | |
50 | ||
51 | do { | |
52 | if ((_il_rd(il, addr) & mask) == (bits & mask)) | |
53 | return t; | |
54 | udelay(interval); | |
55 | t += interval; | |
56 | } while (t < timeout); | |
57 | ||
58 | return -ETIMEDOUT; | |
59 | } | |
60 | EXPORT_SYMBOL(_il_poll_bit); | |
61 | ||
62 | void | |
63 | il_set_bit(struct il_priv *p, u32 r, u32 m) | |
64 | { | |
65 | unsigned long reg_flags; | |
66 | ||
67 | spin_lock_irqsave(&p->reg_lock, reg_flags); | |
68 | _il_set_bit(p, r, m); | |
69 | spin_unlock_irqrestore(&p->reg_lock, reg_flags); | |
70 | } | |
71 | EXPORT_SYMBOL(il_set_bit); | |
72 | ||
73 | void | |
74 | il_clear_bit(struct il_priv *p, u32 r, u32 m) | |
75 | { | |
76 | unsigned long reg_flags; | |
77 | ||
78 | spin_lock_irqsave(&p->reg_lock, reg_flags); | |
79 | _il_clear_bit(p, r, m); | |
80 | spin_unlock_irqrestore(&p->reg_lock, reg_flags); | |
81 | } | |
82 | EXPORT_SYMBOL(il_clear_bit); | |
83 | ||
84 | int | |
85 | _il_grab_nic_access(struct il_priv *il) | |
86 | { | |
87 | int ret; | |
88 | u32 val; | |
89 | ||
90 | /* this bit wakes up the NIC */ | |
91 | _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
92 | ||
93 | /* | |
94 | * These bits say the device is running, and should keep running for | |
95 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
96 | * but they do not indicate that embedded SRAM is restored yet; | |
97 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
98 | * to/from host DRAM when sleeping/waking for power-saving. | |
99 | * Each direction takes approximately 1/4 millisecond; with this | |
100 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
101 | * series of register accesses are expected (e.g. reading Event Log), | |
102 | * to keep device from sleeping. | |
103 | * | |
104 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
105 | * SRAM is okay/restored. We don't check that here because this call | |
106 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
107 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
108 | * | |
109 | */ | |
110 | ret = | |
111 | _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
112 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
113 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
b6603036 | 114 | if (unlikely(ret < 0)) { |
17d4eca6 | 115 | val = _il_rd(il, CSR_GP_CNTRL); |
b6603036 SG |
116 | WARN_ONCE(1, "Timeout waiting for ucode processor access " |
117 | "(CSR_GP_CNTRL 0x%08x)\n", val); | |
17d4eca6 SG |
118 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); |
119 | return -EIO; | |
120 | } | |
121 | ||
122 | return 0; | |
123 | } | |
124 | EXPORT_SYMBOL_GPL(_il_grab_nic_access); | |
125 | ||
126 | int | |
127 | il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout) | |
128 | { | |
129 | const int interval = 10; /* microseconds */ | |
130 | int t = 0; | |
131 | ||
132 | do { | |
133 | if ((il_rd(il, addr) & mask) == mask) | |
134 | return t; | |
135 | udelay(interval); | |
136 | t += interval; | |
137 | } while (t < timeout); | |
138 | ||
139 | return -ETIMEDOUT; | |
140 | } | |
141 | EXPORT_SYMBOL(il_poll_bit); | |
142 | ||
143 | u32 | |
144 | il_rd_prph(struct il_priv *il, u32 reg) | |
145 | { | |
146 | unsigned long reg_flags; | |
147 | u32 val; | |
148 | ||
149 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
150 | _il_grab_nic_access(il); | |
151 | val = _il_rd_prph(il, reg); | |
152 | _il_release_nic_access(il); | |
153 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
154 | return val; | |
155 | } | |
156 | EXPORT_SYMBOL(il_rd_prph); | |
157 | ||
158 | void | |
159 | il_wr_prph(struct il_priv *il, u32 addr, u32 val) | |
160 | { | |
161 | unsigned long reg_flags; | |
162 | ||
163 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
164 | if (!_il_grab_nic_access(il)) { | |
165 | _il_wr_prph(il, addr, val); | |
166 | _il_release_nic_access(il); | |
167 | } | |
168 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
169 | } | |
170 | EXPORT_SYMBOL(il_wr_prph); | |
171 | ||
172 | u32 | |
173 | il_read_targ_mem(struct il_priv *il, u32 addr) | |
174 | { | |
175 | unsigned long reg_flags; | |
176 | u32 value; | |
177 | ||
178 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
179 | _il_grab_nic_access(il); | |
180 | ||
181 | _il_wr(il, HBUS_TARG_MEM_RADDR, addr); | |
182 | rmb(); | |
183 | value = _il_rd(il, HBUS_TARG_MEM_RDAT); | |
184 | ||
185 | _il_release_nic_access(il); | |
186 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
187 | return value; | |
188 | } | |
189 | EXPORT_SYMBOL(il_read_targ_mem); | |
190 | ||
191 | void | |
192 | il_write_targ_mem(struct il_priv *il, u32 addr, u32 val) | |
193 | { | |
194 | unsigned long reg_flags; | |
195 | ||
196 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
197 | if (!_il_grab_nic_access(il)) { | |
198 | _il_wr(il, HBUS_TARG_MEM_WADDR, addr); | |
199 | wmb(); | |
200 | _il_wr(il, HBUS_TARG_MEM_WDAT, val); | |
201 | _il_release_nic_access(il); | |
202 | } | |
203 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
204 | } | |
205 | EXPORT_SYMBOL(il_write_targ_mem); | |
206 | ||
e7392364 SG |
207 | const char * |
208 | il_get_cmd_string(u8 cmd) | |
0cdc2136 SG |
209 | { |
210 | switch (cmd) { | |
211 | IL_CMD(N_ALIVE); | |
212 | IL_CMD(N_ERROR); | |
213 | IL_CMD(C_RXON); | |
214 | IL_CMD(C_RXON_ASSOC); | |
215 | IL_CMD(C_QOS_PARAM); | |
216 | IL_CMD(C_RXON_TIMING); | |
217 | IL_CMD(C_ADD_STA); | |
218 | IL_CMD(C_REM_STA); | |
219 | IL_CMD(C_WEPKEY); | |
220 | IL_CMD(N_3945_RX); | |
221 | IL_CMD(C_TX); | |
222 | IL_CMD(C_RATE_SCALE); | |
223 | IL_CMD(C_LEDS); | |
224 | IL_CMD(C_TX_LINK_QUALITY_CMD); | |
225 | IL_CMD(C_CHANNEL_SWITCH); | |
226 | IL_CMD(N_CHANNEL_SWITCH); | |
227 | IL_CMD(C_SPECTRUM_MEASUREMENT); | |
228 | IL_CMD(N_SPECTRUM_MEASUREMENT); | |
229 | IL_CMD(C_POWER_TBL); | |
230 | IL_CMD(N_PM_SLEEP); | |
231 | IL_CMD(N_PM_DEBUG_STATS); | |
232 | IL_CMD(C_SCAN); | |
233 | IL_CMD(C_SCAN_ABORT); | |
234 | IL_CMD(N_SCAN_START); | |
235 | IL_CMD(N_SCAN_RESULTS); | |
236 | IL_CMD(N_SCAN_COMPLETE); | |
237 | IL_CMD(N_BEACON); | |
238 | IL_CMD(C_TX_BEACON); | |
239 | IL_CMD(C_TX_PWR_TBL); | |
240 | IL_CMD(C_BT_CONFIG); | |
241 | IL_CMD(C_STATS); | |
242 | IL_CMD(N_STATS); | |
243 | IL_CMD(N_CARD_STATE); | |
244 | IL_CMD(N_MISSED_BEACONS); | |
245 | IL_CMD(C_CT_KILL_CONFIG); | |
246 | IL_CMD(C_SENSITIVITY); | |
247 | IL_CMD(C_PHY_CALIBRATION); | |
248 | IL_CMD(N_RX_PHY); | |
249 | IL_CMD(N_RX_MPDU); | |
250 | IL_CMD(N_RX); | |
251 | IL_CMD(N_COMPRESSED_BA); | |
252 | default: | |
253 | return "UNKNOWN"; | |
254 | ||
255 | } | |
256 | } | |
257 | EXPORT_SYMBOL(il_get_cmd_string); | |
258 | ||
259 | #define HOST_COMPLETE_TIMEOUT (HZ / 2) | |
260 | ||
e7392364 SG |
261 | static void |
262 | il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd, | |
263 | struct il_rx_pkt *pkt) | |
0cdc2136 SG |
264 | { |
265 | if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { | |
266 | IL_ERR("Bad return from %s (0x%08X)\n", | |
e7392364 | 267 | il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
0cdc2136 SG |
268 | return; |
269 | } | |
0cdc2136 SG |
270 | #ifdef CONFIG_IWLEGACY_DEBUG |
271 | switch (cmd->hdr.cmd) { | |
272 | case C_TX_LINK_QUALITY_CMD: | |
273 | case C_SENSITIVITY: | |
274 | D_HC_DUMP("back from %s (0x%08X)\n", | |
e7392364 | 275 | il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
0cdc2136 SG |
276 | break; |
277 | default: | |
e7392364 SG |
278 | D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd), |
279 | pkt->hdr.flags); | |
0cdc2136 SG |
280 | } |
281 | #endif | |
282 | } | |
283 | ||
284 | static int | |
285 | il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd) | |
286 | { | |
287 | int ret; | |
288 | ||
289 | BUG_ON(!(cmd->flags & CMD_ASYNC)); | |
290 | ||
291 | /* An asynchronous command can not expect an SKB to be set. */ | |
292 | BUG_ON(cmd->flags & CMD_WANT_SKB); | |
293 | ||
294 | /* Assign a generic callback if one is not provided */ | |
295 | if (!cmd->callback) | |
296 | cmd->callback = il_generic_cmd_callback; | |
297 | ||
298 | if (test_bit(S_EXIT_PENDING, &il->status)) | |
299 | return -EBUSY; | |
300 | ||
301 | ret = il_enqueue_hcmd(il, cmd); | |
302 | if (ret < 0) { | |
303 | IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n", | |
e7392364 | 304 | il_get_cmd_string(cmd->id), ret); |
0cdc2136 SG |
305 | return ret; |
306 | } | |
307 | return 0; | |
308 | } | |
309 | ||
e7392364 SG |
310 | int |
311 | il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd) | |
0cdc2136 SG |
312 | { |
313 | int cmd_idx; | |
314 | int ret; | |
315 | ||
316 | lockdep_assert_held(&il->mutex); | |
317 | ||
318 | BUG_ON(cmd->flags & CMD_ASYNC); | |
319 | ||
e7392364 | 320 | /* A synchronous command can not have a callback set. */ |
0cdc2136 SG |
321 | BUG_ON(cmd->callback); |
322 | ||
323 | D_INFO("Attempting to send sync command %s\n", | |
e7392364 | 324 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
325 | |
326 | set_bit(S_HCMD_ACTIVE, &il->status); | |
327 | D_INFO("Setting HCMD_ACTIVE for command %s\n", | |
e7392364 | 328 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
329 | |
330 | cmd_idx = il_enqueue_hcmd(il, cmd); | |
331 | if (cmd_idx < 0) { | |
332 | ret = cmd_idx; | |
333 | IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n", | |
e7392364 | 334 | il_get_cmd_string(cmd->id), ret); |
0cdc2136 SG |
335 | goto out; |
336 | } | |
337 | ||
338 | ret = wait_event_timeout(il->wait_command_queue, | |
e7392364 SG |
339 | !test_bit(S_HCMD_ACTIVE, &il->status), |
340 | HOST_COMPLETE_TIMEOUT); | |
0cdc2136 SG |
341 | if (!ret) { |
342 | if (test_bit(S_HCMD_ACTIVE, &il->status)) { | |
e7392364 SG |
343 | IL_ERR("Error sending %s: time out after %dms.\n", |
344 | il_get_cmd_string(cmd->id), | |
345 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
0cdc2136 SG |
346 | |
347 | clear_bit(S_HCMD_ACTIVE, &il->status); | |
e7392364 SG |
348 | D_INFO("Clearing HCMD_ACTIVE for command %s\n", |
349 | il_get_cmd_string(cmd->id)); | |
0cdc2136 SG |
350 | ret = -ETIMEDOUT; |
351 | goto cancel; | |
352 | } | |
353 | } | |
354 | ||
355 | if (test_bit(S_RF_KILL_HW, &il->status)) { | |
356 | IL_ERR("Command %s aborted: RF KILL Switch\n", | |
e7392364 | 357 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
358 | ret = -ECANCELED; |
359 | goto fail; | |
360 | } | |
361 | if (test_bit(S_FW_ERROR, &il->status)) { | |
362 | IL_ERR("Command %s failed: FW Error\n", | |
e7392364 | 363 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
364 | ret = -EIO; |
365 | goto fail; | |
366 | } | |
367 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) { | |
368 | IL_ERR("Error: Response NULL in '%s'\n", | |
e7392364 | 369 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
370 | ret = -EIO; |
371 | goto cancel; | |
372 | } | |
373 | ||
374 | ret = 0; | |
375 | goto out; | |
376 | ||
377 | cancel: | |
378 | if (cmd->flags & CMD_WANT_SKB) { | |
379 | /* | |
380 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
381 | * TX cmd queue. Otherwise in case the cmd comes | |
382 | * in later, it will possibly set an invalid | |
383 | * address (cmd->meta.source). | |
384 | */ | |
e7392364 | 385 | il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB; |
0cdc2136 SG |
386 | } |
387 | fail: | |
388 | if (cmd->reply_page) { | |
389 | il_free_pages(il, cmd->reply_page); | |
390 | cmd->reply_page = 0; | |
391 | } | |
392 | out: | |
393 | return ret; | |
394 | } | |
395 | EXPORT_SYMBOL(il_send_cmd_sync); | |
396 | ||
e7392364 SG |
397 | int |
398 | il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd) | |
0cdc2136 SG |
399 | { |
400 | if (cmd->flags & CMD_ASYNC) | |
401 | return il_send_cmd_async(il, cmd); | |
402 | ||
403 | return il_send_cmd_sync(il, cmd); | |
404 | } | |
405 | EXPORT_SYMBOL(il_send_cmd); | |
406 | ||
407 | int | |
408 | il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data) | |
409 | { | |
410 | struct il_host_cmd cmd = { | |
411 | .id = id, | |
412 | .len = len, | |
413 | .data = data, | |
414 | }; | |
415 | ||
416 | return il_send_cmd_sync(il, &cmd); | |
417 | } | |
418 | EXPORT_SYMBOL(il_send_cmd_pdu); | |
419 | ||
e7392364 SG |
420 | int |
421 | il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data, | |
1722f8e1 SG |
422 | void (*callback) (struct il_priv *il, |
423 | struct il_device_cmd *cmd, | |
424 | struct il_rx_pkt *pkt)) | |
0cdc2136 SG |
425 | { |
426 | struct il_host_cmd cmd = { | |
427 | .id = id, | |
428 | .len = len, | |
429 | .data = data, | |
430 | }; | |
431 | ||
432 | cmd.flags |= CMD_ASYNC; | |
433 | cmd.callback = callback; | |
434 | ||
435 | return il_send_cmd_async(il, &cmd); | |
436 | } | |
437 | EXPORT_SYMBOL(il_send_cmd_pdu_async); | |
438 | ||
439 | /* default: IL_LED_BLINK(0) using blinking idx table */ | |
440 | static int led_mode; | |
441 | module_param(led_mode, int, S_IRUGO); | |
e7392364 SG |
442 | MODULE_PARM_DESC(led_mode, |
443 | "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking"); | |
0cdc2136 SG |
444 | |
445 | /* Throughput OFF time(ms) ON time (ms) | |
446 | * >300 25 25 | |
447 | * >200 to 300 40 40 | |
448 | * >100 to 200 55 55 | |
449 | * >70 to 100 65 65 | |
450 | * >50 to 70 75 75 | |
451 | * >20 to 50 85 85 | |
452 | * >10 to 20 95 95 | |
453 | * >5 to 10 110 110 | |
454 | * >1 to 5 130 130 | |
455 | * >0 to 1 167 167 | |
456 | * <=0 SOLID ON | |
457 | */ | |
458 | static const struct ieee80211_tpt_blink il_blink[] = { | |
1722f8e1 SG |
459 | {.throughput = 0, .blink_time = 334}, |
460 | {.throughput = 1 * 1024 - 1, .blink_time = 260}, | |
461 | {.throughput = 5 * 1024 - 1, .blink_time = 220}, | |
462 | {.throughput = 10 * 1024 - 1, .blink_time = 190}, | |
463 | {.throughput = 20 * 1024 - 1, .blink_time = 170}, | |
464 | {.throughput = 50 * 1024 - 1, .blink_time = 150}, | |
465 | {.throughput = 70 * 1024 - 1, .blink_time = 130}, | |
466 | {.throughput = 100 * 1024 - 1, .blink_time = 110}, | |
467 | {.throughput = 200 * 1024 - 1, .blink_time = 80}, | |
468 | {.throughput = 300 * 1024 - 1, .blink_time = 50}, | |
0cdc2136 SG |
469 | }; |
470 | ||
471 | /* | |
472 | * Adjust led blink rate to compensate on a MAC Clock difference on every HW | |
473 | * Led blink rate analysis showed an average deviation of 0% on 3945, | |
474 | * 5% on 4965 HW. | |
475 | * Need to compensate on the led on/off time per HW according to the deviation | |
476 | * to achieve the desired led frequency | |
477 | * The calculation is: (100-averageDeviation)/100 * blinkTime | |
478 | * For code efficiency the calculation will be: | |
479 | * compensation = (100 - averageDeviation) * 64 / 100 | |
480 | * NewBlinkTime = (compensation * BlinkTime) / 64 | |
481 | */ | |
e7392364 SG |
482 | static inline u8 |
483 | il_blink_compensation(struct il_priv *il, u8 time, u16 compensation) | |
0cdc2136 SG |
484 | { |
485 | if (!compensation) { | |
486 | IL_ERR("undefined blink compensation: " | |
e7392364 | 487 | "use pre-defined blinking time\n"); |
0cdc2136 SG |
488 | return time; |
489 | } | |
490 | ||
e7392364 | 491 | return (u8) ((time * compensation) >> 6); |
0cdc2136 SG |
492 | } |
493 | ||
494 | /* Set led pattern command */ | |
e7392364 SG |
495 | static int |
496 | il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off) | |
0cdc2136 SG |
497 | { |
498 | struct il_led_cmd led_cmd = { | |
499 | .id = IL_LED_LINK, | |
500 | .interval = IL_DEF_LED_INTRVL | |
501 | }; | |
502 | int ret; | |
503 | ||
504 | if (!test_bit(S_READY, &il->status)) | |
505 | return -EBUSY; | |
506 | ||
507 | if (il->blink_on == on && il->blink_off == off) | |
508 | return 0; | |
509 | ||
510 | if (off == 0) { | |
511 | /* led is SOLID_ON */ | |
512 | on = IL_LED_SOLID; | |
513 | } | |
514 | ||
515 | D_LED("Led blink time compensation=%u\n", | |
89ef1ed2 | 516 | il->cfg->led_compensation); |
e7392364 SG |
517 | led_cmd.on = |
518 | il_blink_compensation(il, on, | |
89ef1ed2 | 519 | il->cfg->led_compensation); |
e7392364 SG |
520 | led_cmd.off = |
521 | il_blink_compensation(il, off, | |
89ef1ed2 | 522 | il->cfg->led_compensation); |
0cdc2136 | 523 | |
c39ae9fd | 524 | ret = il->ops->led->cmd(il, &led_cmd); |
0cdc2136 SG |
525 | if (!ret) { |
526 | il->blink_on = on; | |
527 | il->blink_off = off; | |
528 | } | |
529 | return ret; | |
530 | } | |
531 | ||
e7392364 SG |
532 | static void |
533 | il_led_brightness_set(struct led_classdev *led_cdev, | |
534 | enum led_brightness brightness) | |
0cdc2136 SG |
535 | { |
536 | struct il_priv *il = container_of(led_cdev, struct il_priv, led); | |
537 | unsigned long on = 0; | |
538 | ||
539 | if (brightness > 0) | |
540 | on = IL_LED_SOLID; | |
541 | ||
542 | il_led_cmd(il, on, 0); | |
543 | } | |
544 | ||
e7392364 SG |
545 | static int |
546 | il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on, | |
547 | unsigned long *delay_off) | |
0cdc2136 SG |
548 | { |
549 | struct il_priv *il = container_of(led_cdev, struct il_priv, led); | |
550 | ||
551 | return il_led_cmd(il, *delay_on, *delay_off); | |
552 | } | |
553 | ||
e7392364 SG |
554 | void |
555 | il_leds_init(struct il_priv *il) | |
0cdc2136 SG |
556 | { |
557 | int mode = led_mode; | |
558 | int ret; | |
559 | ||
560 | if (mode == IL_LED_DEFAULT) | |
561 | mode = il->cfg->led_mode; | |
562 | ||
e7392364 SG |
563 | il->led.name = |
564 | kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy)); | |
0cdc2136 SG |
565 | il->led.brightness_set = il_led_brightness_set; |
566 | il->led.blink_set = il_led_blink_set; | |
567 | il->led.max_brightness = 1; | |
568 | ||
569 | switch (mode) { | |
570 | case IL_LED_DEFAULT: | |
571 | WARN_ON(1); | |
572 | break; | |
573 | case IL_LED_BLINK: | |
574 | il->led.default_trigger = | |
e7392364 SG |
575 | ieee80211_create_tpt_led_trigger(il->hw, |
576 | IEEE80211_TPT_LEDTRIG_FL_CONNECTED, | |
577 | il_blink, | |
578 | ARRAY_SIZE(il_blink)); | |
0cdc2136 SG |
579 | break; |
580 | case IL_LED_RF_STATE: | |
e7392364 | 581 | il->led.default_trigger = ieee80211_get_radio_led_name(il->hw); |
0cdc2136 SG |
582 | break; |
583 | } | |
584 | ||
585 | ret = led_classdev_register(&il->pci_dev->dev, &il->led); | |
586 | if (ret) { | |
587 | kfree(il->led.name); | |
588 | return; | |
589 | } | |
590 | ||
591 | il->led_registered = true; | |
592 | } | |
593 | EXPORT_SYMBOL(il_leds_init); | |
594 | ||
e7392364 SG |
595 | void |
596 | il_leds_exit(struct il_priv *il) | |
0cdc2136 SG |
597 | { |
598 | if (!il->led_registered) | |
599 | return; | |
600 | ||
601 | led_classdev_unregister(&il->led); | |
602 | kfree(il->led.name); | |
603 | } | |
604 | EXPORT_SYMBOL(il_leds_exit); | |
605 | ||
606 | /************************** EEPROM BANDS **************************** | |
607 | * | |
608 | * The il_eeprom_band definitions below provide the mapping from the | |
609 | * EEPROM contents to the specific channel number supported for each | |
610 | * band. | |
611 | * | |
612 | * For example, il_priv->eeprom.band_3_channels[4] from the band_3 | |
613 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. | |
614 | * The specific geography and calibration information for that channel | |
615 | * is contained in the eeprom map itself. | |
616 | * | |
617 | * During init, we copy the eeprom information and channel map | |
618 | * information into il->channel_info_24/52 and il->channel_map_24/52 | |
619 | * | |
620 | * channel_map_24/52 provides the idx in the channel_info array for a | |
621 | * given channel. We have to have two separate maps as there is channel | |
622 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
623 | * band_2 | |
624 | * | |
625 | * A value of 0xff stored in the channel_map indicates that the channel | |
626 | * is not supported by the hardware at all. | |
627 | * | |
628 | * A value of 0xfe in the channel_map indicates that the channel is not | |
629 | * valid for Tx with the current hardware. This means that | |
630 | * while the system can tune and receive on a given channel, it may not | |
631 | * be able to associate or transmit any frames on that | |
632 | * channel. There is no corresponding channel information for that | |
633 | * entry. | |
634 | * | |
635 | *********************************************************************/ | |
636 | ||
637 | /* 2.4 GHz */ | |
638 | const u8 il_eeprom_band_1[14] = { | |
639 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
640 | }; | |
641 | ||
642 | /* 5.2 GHz bands */ | |
643 | static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */ | |
644 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 | |
645 | }; | |
646 | ||
647 | static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */ | |
648 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
649 | }; | |
650 | ||
651 | static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */ | |
652 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
653 | }; | |
654 | ||
655 | static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */ | |
656 | 145, 149, 153, 157, 161, 165 | |
657 | }; | |
658 | ||
e7392364 | 659 | static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */ |
0cdc2136 SG |
660 | 1, 2, 3, 4, 5, 6, 7 |
661 | }; | |
662 | ||
e7392364 | 663 | static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */ |
0cdc2136 SG |
664 | 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 |
665 | }; | |
666 | ||
667 | /****************************************************************************** | |
668 | * | |
669 | * EEPROM related functions | |
670 | * | |
671 | ******************************************************************************/ | |
672 | ||
e7392364 SG |
673 | static int |
674 | il_eeprom_verify_signature(struct il_priv *il) | |
0cdc2136 SG |
675 | { |
676 | u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; | |
677 | int ret = 0; | |
678 | ||
679 | D_EEPROM("EEPROM signature=0x%08x\n", gp); | |
680 | switch (gp) { | |
681 | case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: | |
682 | case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: | |
683 | break; | |
684 | default: | |
e7392364 | 685 | IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp); |
0cdc2136 SG |
686 | ret = -ENOENT; |
687 | break; | |
688 | } | |
689 | return ret; | |
690 | } | |
691 | ||
e7392364 SG |
692 | const u8 * |
693 | il_eeprom_query_addr(const struct il_priv *il, size_t offset) | |
0cdc2136 | 694 | { |
89ef1ed2 | 695 | BUG_ON(offset >= il->cfg->eeprom_size); |
0cdc2136 SG |
696 | return &il->eeprom[offset]; |
697 | } | |
698 | EXPORT_SYMBOL(il_eeprom_query_addr); | |
699 | ||
e7392364 | 700 | u16 |
1722f8e1 | 701 | il_eeprom_query16(const struct il_priv *il, size_t offset) |
0cdc2136 SG |
702 | { |
703 | if (!il->eeprom) | |
704 | return 0; | |
e7392364 | 705 | return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8); |
0cdc2136 SG |
706 | } |
707 | EXPORT_SYMBOL(il_eeprom_query16); | |
708 | ||
709 | /** | |
710 | * il_eeprom_init - read EEPROM contents | |
711 | * | |
712 | * Load the EEPROM contents from adapter into il->eeprom | |
713 | * | |
714 | * NOTE: This routine uses the non-debug IO access functions. | |
715 | */ | |
e7392364 SG |
716 | int |
717 | il_eeprom_init(struct il_priv *il) | |
0cdc2136 SG |
718 | { |
719 | __le16 *e; | |
720 | u32 gp = _il_rd(il, CSR_EEPROM_GP); | |
721 | int sz; | |
722 | int ret; | |
723 | u16 addr; | |
724 | ||
725 | /* allocate eeprom */ | |
89ef1ed2 | 726 | sz = il->cfg->eeprom_size; |
0cdc2136 SG |
727 | D_EEPROM("NVM size = %d\n", sz); |
728 | il->eeprom = kzalloc(sz, GFP_KERNEL); | |
729 | if (!il->eeprom) { | |
730 | ret = -ENOMEM; | |
731 | goto alloc_err; | |
732 | } | |
e7392364 | 733 | e = (__le16 *) il->eeprom; |
0cdc2136 | 734 | |
c39ae9fd | 735 | il->ops->lib->apm_ops.init(il); |
0cdc2136 SG |
736 | |
737 | ret = il_eeprom_verify_signature(il); | |
738 | if (ret < 0) { | |
739 | IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp); | |
740 | ret = -ENOENT; | |
741 | goto err; | |
742 | } | |
743 | ||
744 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ | |
c39ae9fd | 745 | ret = il->ops->lib->eeprom_ops.acquire_semaphore(il); |
0cdc2136 SG |
746 | if (ret < 0) { |
747 | IL_ERR("Failed to acquire EEPROM semaphore.\n"); | |
748 | ret = -ENOENT; | |
749 | goto err; | |
750 | } | |
751 | ||
752 | /* eeprom is an array of 16bit values */ | |
753 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
754 | u32 r; | |
755 | ||
756 | _il_wr(il, CSR_EEPROM_REG, | |
e7392364 | 757 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); |
0cdc2136 | 758 | |
e7392364 SG |
759 | ret = |
760 | _il_poll_bit(il, CSR_EEPROM_REG, | |
761 | CSR_EEPROM_REG_READ_VALID_MSK, | |
762 | CSR_EEPROM_REG_READ_VALID_MSK, | |
763 | IL_EEPROM_ACCESS_TIMEOUT); | |
0cdc2136 | 764 | if (ret < 0) { |
e7392364 | 765 | IL_ERR("Time out reading EEPROM[%d]\n", addr); |
0cdc2136 SG |
766 | goto done; |
767 | } | |
768 | r = _il_rd(il, CSR_EEPROM_REG); | |
769 | e[addr / 2] = cpu_to_le16(r >> 16); | |
770 | } | |
771 | ||
e7392364 SG |
772 | D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM", |
773 | il_eeprom_query16(il, EEPROM_VERSION)); | |
0cdc2136 SG |
774 | |
775 | ret = 0; | |
776 | done: | |
c39ae9fd | 777 | il->ops->lib->eeprom_ops.release_semaphore(il); |
0cdc2136 SG |
778 | |
779 | err: | |
780 | if (ret) | |
781 | il_eeprom_free(il); | |
782 | /* Reset chip to save power until we load uCode during "up". */ | |
783 | il_apm_stop(il); | |
784 | alloc_err: | |
785 | return ret; | |
786 | } | |
787 | EXPORT_SYMBOL(il_eeprom_init); | |
788 | ||
e7392364 SG |
789 | void |
790 | il_eeprom_free(struct il_priv *il) | |
0cdc2136 SG |
791 | { |
792 | kfree(il->eeprom); | |
793 | il->eeprom = NULL; | |
794 | } | |
795 | EXPORT_SYMBOL(il_eeprom_free); | |
796 | ||
e7392364 SG |
797 | static void |
798 | il_init_band_reference(const struct il_priv *il, int eep_band, | |
799 | int *eeprom_ch_count, | |
800 | const struct il_eeprom_channel **eeprom_ch_info, | |
1722f8e1 | 801 | const u8 **eeprom_ch_idx) |
0cdc2136 | 802 | { |
e7392364 | 803 | u32 offset = |
c39ae9fd | 804 | il->ops->lib->eeprom_ops.regulatory_bands[eep_band - 1]; |
0cdc2136 SG |
805 | switch (eep_band) { |
806 | case 1: /* 2.4GHz band */ | |
807 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1); | |
e7392364 SG |
808 | *eeprom_ch_info = |
809 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
810 | offset); | |
0cdc2136 SG |
811 | *eeprom_ch_idx = il_eeprom_band_1; |
812 | break; | |
813 | case 2: /* 4.9GHz band */ | |
814 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2); | |
e7392364 SG |
815 | *eeprom_ch_info = |
816 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
817 | offset); | |
0cdc2136 SG |
818 | *eeprom_ch_idx = il_eeprom_band_2; |
819 | break; | |
820 | case 3: /* 5.2GHz band */ | |
821 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3); | |
e7392364 SG |
822 | *eeprom_ch_info = |
823 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
824 | offset); | |
0cdc2136 SG |
825 | *eeprom_ch_idx = il_eeprom_band_3; |
826 | break; | |
827 | case 4: /* 5.5GHz band */ | |
828 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4); | |
e7392364 SG |
829 | *eeprom_ch_info = |
830 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
831 | offset); | |
0cdc2136 SG |
832 | *eeprom_ch_idx = il_eeprom_band_4; |
833 | break; | |
834 | case 5: /* 5.7GHz band */ | |
835 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5); | |
e7392364 SG |
836 | *eeprom_ch_info = |
837 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
838 | offset); | |
0cdc2136 SG |
839 | *eeprom_ch_idx = il_eeprom_band_5; |
840 | break; | |
841 | case 6: /* 2.4GHz ht40 channels */ | |
842 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6); | |
e7392364 SG |
843 | *eeprom_ch_info = |
844 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
845 | offset); | |
0cdc2136 SG |
846 | *eeprom_ch_idx = il_eeprom_band_6; |
847 | break; | |
848 | case 7: /* 5 GHz ht40 channels */ | |
849 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7); | |
e7392364 SG |
850 | *eeprom_ch_info = |
851 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
852 | offset); | |
0cdc2136 SG |
853 | *eeprom_ch_idx = il_eeprom_band_7; |
854 | break; | |
855 | default: | |
856 | BUG(); | |
857 | } | |
858 | } | |
859 | ||
860 | #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \ | |
861 | ? # x " " : "") | |
862 | /** | |
863 | * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il. | |
864 | * | |
865 | * Does not set up a command, or touch hardware. | |
866 | */ | |
e7392364 SG |
867 | static int |
868 | il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel, | |
869 | const struct il_eeprom_channel *eeprom_ch, | |
870 | u8 clear_ht40_extension_channel) | |
0cdc2136 SG |
871 | { |
872 | struct il_channel_info *ch_info; | |
873 | ||
e7392364 SG |
874 | ch_info = |
875 | (struct il_channel_info *)il_get_channel_info(il, band, channel); | |
0cdc2136 SG |
876 | |
877 | if (!il_is_channel_valid(ch_info)) | |
878 | return -1; | |
879 | ||
880 | D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):" | |
e7392364 SG |
881 | " Ad-Hoc %ssupported\n", ch_info->channel, |
882 | il_is_channel_a_band(ch_info) ? "5.2" : "2.4", | |
883 | CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE), | |
884 | CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE), | |
885 | CHECK_AND_PRINT(DFS), eeprom_ch->flags, | |
886 | eeprom_ch->max_power_avg, | |
887 | ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) && | |
888 | !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not "); | |
0cdc2136 SG |
889 | |
890 | ch_info->ht40_eeprom = *eeprom_ch; | |
891 | ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg; | |
892 | ch_info->ht40_flags = eeprom_ch->flags; | |
893 | if (eeprom_ch->flags & EEPROM_CHANNEL_VALID) | |
894 | ch_info->ht40_extension_channel &= | |
e7392364 | 895 | ~clear_ht40_extension_channel; |
0cdc2136 SG |
896 | |
897 | return 0; | |
898 | } | |
899 | ||
900 | #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
901 | ? # x " " : "") | |
902 | ||
903 | /** | |
904 | * il_init_channel_map - Set up driver's info for all possible channels | |
905 | */ | |
e7392364 SG |
906 | int |
907 | il_init_channel_map(struct il_priv *il) | |
0cdc2136 SG |
908 | { |
909 | int eeprom_ch_count = 0; | |
910 | const u8 *eeprom_ch_idx = NULL; | |
911 | const struct il_eeprom_channel *eeprom_ch_info = NULL; | |
912 | int band, ch; | |
913 | struct il_channel_info *ch_info; | |
914 | ||
915 | if (il->channel_count) { | |
916 | D_EEPROM("Channel map already initialized.\n"); | |
917 | return 0; | |
918 | } | |
919 | ||
920 | D_EEPROM("Initializing regulatory info from EEPROM\n"); | |
921 | ||
922 | il->channel_count = | |
e7392364 SG |
923 | ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) + |
924 | ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) + | |
0cdc2136 SG |
925 | ARRAY_SIZE(il_eeprom_band_5); |
926 | ||
e7392364 | 927 | D_EEPROM("Parsing data for %d channels.\n", il->channel_count); |
0cdc2136 | 928 | |
e7392364 SG |
929 | il->channel_info = |
930 | kzalloc(sizeof(struct il_channel_info) * il->channel_count, | |
931 | GFP_KERNEL); | |
0cdc2136 SG |
932 | if (!il->channel_info) { |
933 | IL_ERR("Could not allocate channel_info\n"); | |
934 | il->channel_count = 0; | |
935 | return -ENOMEM; | |
936 | } | |
937 | ||
938 | ch_info = il->channel_info; | |
939 | ||
940 | /* Loop through the 5 EEPROM bands adding them in order to the | |
941 | * channel map we maintain (that contains additional information than | |
942 | * what just in the EEPROM) */ | |
943 | for (band = 1; band <= 5; band++) { | |
944 | ||
945 | il_init_band_reference(il, band, &eeprom_ch_count, | |
e7392364 | 946 | &eeprom_ch_info, &eeprom_ch_idx); |
0cdc2136 SG |
947 | |
948 | /* Loop through each band adding each of the channels */ | |
949 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
950 | ch_info->channel = eeprom_ch_idx[ch]; | |
e7392364 SG |
951 | ch_info->band = |
952 | (band == | |
953 | 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
0cdc2136 SG |
954 | |
955 | /* permanently store EEPROM's channel regulatory flags | |
956 | * and max power in channel info database. */ | |
957 | ch_info->eeprom = eeprom_ch_info[ch]; | |
958 | ||
959 | /* Copy the run-time flags so they are there even on | |
960 | * invalid channels */ | |
961 | ch_info->flags = eeprom_ch_info[ch].flags; | |
962 | /* First write that ht40 is not enabled, and then enable | |
963 | * one by one */ | |
964 | ch_info->ht40_extension_channel = | |
e7392364 | 965 | IEEE80211_CHAN_NO_HT40; |
0cdc2136 SG |
966 | |
967 | if (!(il_is_channel_valid(ch_info))) { | |
e7392364 SG |
968 | D_EEPROM("Ch. %d Flags %x [%sGHz] - " |
969 | "No traffic\n", ch_info->channel, | |
970 | ch_info->flags, | |
971 | il_is_channel_a_band(ch_info) ? "5.2" : | |
972 | "2.4"); | |
0cdc2136 SG |
973 | ch_info++; |
974 | continue; | |
975 | } | |
976 | ||
977 | /* Initialize regulatory-based run-time data */ | |
978 | ch_info->max_power_avg = ch_info->curr_txpow = | |
979 | eeprom_ch_info[ch].max_power_avg; | |
980 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
981 | ch_info->min_power = 0; | |
982 | ||
e7392364 SG |
983 | D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):" |
984 | " Ad-Hoc %ssupported\n", ch_info->channel, | |
985 | il_is_channel_a_band(ch_info) ? "5.2" : "2.4", | |
986 | CHECK_AND_PRINT_I(VALID), | |
987 | CHECK_AND_PRINT_I(IBSS), | |
988 | CHECK_AND_PRINT_I(ACTIVE), | |
989 | CHECK_AND_PRINT_I(RADAR), | |
990 | CHECK_AND_PRINT_I(WIDE), | |
991 | CHECK_AND_PRINT_I(DFS), | |
992 | eeprom_ch_info[ch].flags, | |
993 | eeprom_ch_info[ch].max_power_avg, | |
994 | ((eeprom_ch_info[ch]. | |
995 | flags & EEPROM_CHANNEL_IBSS) && | |
996 | !(eeprom_ch_info[ch]. | |
997 | flags & EEPROM_CHANNEL_RADAR)) ? "" : | |
998 | "not "); | |
0cdc2136 SG |
999 | |
1000 | ch_info++; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | /* Check if we do have HT40 channels */ | |
c39ae9fd | 1005 | if (il->ops->lib->eeprom_ops.regulatory_bands[5] == |
0cdc2136 | 1006 | EEPROM_REGULATORY_BAND_NO_HT40 && |
c39ae9fd | 1007 | il->ops->lib->eeprom_ops.regulatory_bands[6] == |
0cdc2136 SG |
1008 | EEPROM_REGULATORY_BAND_NO_HT40) |
1009 | return 0; | |
1010 | ||
1011 | /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */ | |
1012 | for (band = 6; band <= 7; band++) { | |
1013 | enum ieee80211_band ieeeband; | |
1014 | ||
1015 | il_init_band_reference(il, band, &eeprom_ch_count, | |
e7392364 | 1016 | &eeprom_ch_info, &eeprom_ch_idx); |
0cdc2136 SG |
1017 | |
1018 | /* EEPROM band 6 is 2.4, band 7 is 5 GHz */ | |
1019 | ieeeband = | |
e7392364 | 1020 | (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; |
0cdc2136 SG |
1021 | |
1022 | /* Loop through each band adding each of the channels */ | |
1023 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
1024 | /* Set up driver's info for lower half */ | |
e7392364 SG |
1025 | il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch], |
1026 | &eeprom_ch_info[ch], | |
1027 | IEEE80211_CHAN_NO_HT40PLUS); | |
0cdc2136 SG |
1028 | |
1029 | /* Set up driver's info for upper half */ | |
1030 | il_mod_ht40_chan_info(il, ieeeband, | |
e7392364 SG |
1031 | eeprom_ch_idx[ch] + 4, |
1032 | &eeprom_ch_info[ch], | |
1033 | IEEE80211_CHAN_NO_HT40MINUS); | |
0cdc2136 SG |
1034 | } |
1035 | } | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | EXPORT_SYMBOL(il_init_channel_map); | |
1040 | ||
1041 | /* | |
1042 | * il_free_channel_map - undo allocations in il_init_channel_map | |
1043 | */ | |
e7392364 SG |
1044 | void |
1045 | il_free_channel_map(struct il_priv *il) | |
0cdc2136 SG |
1046 | { |
1047 | kfree(il->channel_info); | |
1048 | il->channel_count = 0; | |
1049 | } | |
1050 | EXPORT_SYMBOL(il_free_channel_map); | |
1051 | ||
1052 | /** | |
1053 | * il_get_channel_info - Find driver's ilate channel info | |
1054 | * | |
1055 | * Based on band and channel number. | |
1056 | */ | |
e7392364 SG |
1057 | const struct il_channel_info * |
1058 | il_get_channel_info(const struct il_priv *il, enum ieee80211_band band, | |
1059 | u16 channel) | |
0cdc2136 SG |
1060 | { |
1061 | int i; | |
1062 | ||
1063 | switch (band) { | |
1064 | case IEEE80211_BAND_5GHZ: | |
1065 | for (i = 14; i < il->channel_count; i++) { | |
1066 | if (il->channel_info[i].channel == channel) | |
1067 | return &il->channel_info[i]; | |
1068 | } | |
1069 | break; | |
1070 | case IEEE80211_BAND_2GHZ: | |
1071 | if (channel >= 1 && channel <= 14) | |
1072 | return &il->channel_info[channel - 1]; | |
1073 | break; | |
1074 | default: | |
1075 | BUG(); | |
1076 | } | |
1077 | ||
1078 | return NULL; | |
1079 | } | |
1080 | EXPORT_SYMBOL(il_get_channel_info); | |
1081 | ||
1082 | /* | |
1083 | * Setting power level allows the card to go to sleep when not busy. | |
1084 | * | |
1085 | * We calculate a sleep command based on the required latency, which | |
1086 | * we get from mac80211. In order to handle thermal throttling, we can | |
1087 | * also use pre-defined power levels. | |
1088 | */ | |
1089 | ||
1090 | /* | |
1091 | * This defines the old power levels. They are still used by default | |
1092 | * (level 1) and for thermal throttle (levels 3 through 5) | |
1093 | */ | |
1094 | ||
1095 | struct il_power_vec_entry { | |
1096 | struct il_powertable_cmd cmd; | |
e7392364 | 1097 | u8 no_dtim; /* number of skip dtim */ |
0cdc2136 SG |
1098 | }; |
1099 | ||
e7392364 SG |
1100 | static void |
1101 | il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd) | |
0cdc2136 SG |
1102 | { |
1103 | memset(cmd, 0, sizeof(*cmd)); | |
1104 | ||
1105 | if (il->power_data.pci_pm) | |
1106 | cmd->flags |= IL_POWER_PCI_PM_MSK; | |
1107 | ||
1108 | D_POWER("Sleep command for CAM\n"); | |
1109 | } | |
1110 | ||
1111 | static int | |
1112 | il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd) | |
1113 | { | |
1114 | D_POWER("Sending power/sleep command\n"); | |
1115 | D_POWER("Flags value = 0x%08X\n", cmd->flags); | |
e7392364 SG |
1116 | D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); |
1117 | D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1118 | D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1119 | le32_to_cpu(cmd->sleep_interval[0]), | |
1120 | le32_to_cpu(cmd->sleep_interval[1]), | |
1121 | le32_to_cpu(cmd->sleep_interval[2]), | |
1122 | le32_to_cpu(cmd->sleep_interval[3]), | |
1123 | le32_to_cpu(cmd->sleep_interval[4])); | |
0cdc2136 SG |
1124 | |
1125 | return il_send_cmd_pdu(il, C_POWER_TBL, | |
e7392364 | 1126 | sizeof(struct il_powertable_cmd), cmd); |
0cdc2136 SG |
1127 | } |
1128 | ||
1129 | int | |
e7392364 | 1130 | il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force) |
0cdc2136 SG |
1131 | { |
1132 | int ret; | |
1133 | bool update_chains; | |
1134 | ||
1135 | lockdep_assert_held(&il->mutex); | |
1136 | ||
1137 | /* Don't update the RX chain when chain noise calibration is running */ | |
1138 | update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE || | |
e7392364 | 1139 | il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE; |
0cdc2136 SG |
1140 | |
1141 | if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force) | |
1142 | return 0; | |
1143 | ||
1144 | if (!il_is_ready_rf(il)) | |
1145 | return -EIO; | |
1146 | ||
1147 | /* scan complete use sleep_power_next, need to be updated */ | |
1148 | memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd)); | |
1149 | if (test_bit(S_SCANNING, &il->status) && !force) { | |
1150 | D_INFO("Defer power set mode while scanning\n"); | |
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK) | |
1155 | set_bit(S_POWER_PMI, &il->status); | |
1156 | ||
1157 | ret = il_set_power(il, cmd); | |
1158 | if (!ret) { | |
1159 | if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)) | |
1160 | clear_bit(S_POWER_PMI, &il->status); | |
1161 | ||
c39ae9fd SG |
1162 | if (il->ops->lib->update_chain_flags && update_chains) |
1163 | il->ops->lib->update_chain_flags(il); | |
1164 | else if (il->ops->lib->update_chain_flags) | |
e7392364 SG |
1165 | D_POWER("Cannot update the power, chain noise " |
1166 | "calibration running: %d\n", | |
1167 | il->chain_noise_data.state); | |
0cdc2136 SG |
1168 | |
1169 | memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)); | |
1170 | } else | |
1171 | IL_ERR("set power fail, ret = %d", ret); | |
1172 | ||
1173 | return ret; | |
1174 | } | |
1175 | ||
e7392364 SG |
1176 | int |
1177 | il_power_update_mode(struct il_priv *il, bool force) | |
0cdc2136 SG |
1178 | { |
1179 | struct il_powertable_cmd cmd; | |
1180 | ||
1181 | il_power_sleep_cam_cmd(il, &cmd); | |
1182 | return il_power_set_mode(il, &cmd, force); | |
1183 | } | |
1184 | EXPORT_SYMBOL(il_power_update_mode); | |
1185 | ||
1186 | /* initialize to default */ | |
e7392364 SG |
1187 | void |
1188 | il_power_initialize(struct il_priv *il) | |
0cdc2136 SG |
1189 | { |
1190 | u16 lctl = il_pcie_link_ctl(il); | |
1191 | ||
1192 | il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); | |
1193 | ||
1194 | il->power_data.debug_sleep_level_override = -1; | |
1195 | ||
e7392364 | 1196 | memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd)); |
0cdc2136 SG |
1197 | } |
1198 | EXPORT_SYMBOL(il_power_initialize); | |
1199 | ||
1200 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after | |
1201 | * sending probe req. This should be set long enough to hear probe responses | |
1202 | * from more than one AP. */ | |
e7392364 | 1203 | #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ |
0cdc2136 SG |
1204 | #define IL_ACTIVE_DWELL_TIME_52 (20) |
1205 | ||
1206 | #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3) | |
1207 | #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2) | |
1208 | ||
1209 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
1210 | * Must be set longer than active dwell time. | |
1211 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
e7392364 | 1212 | #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ |
0cdc2136 SG |
1213 | #define IL_PASSIVE_DWELL_TIME_52 (10) |
1214 | #define IL_PASSIVE_DWELL_BASE (100) | |
1215 | #define IL_CHANNEL_TUNE_TIME 5 | |
1216 | ||
e7392364 SG |
1217 | static int |
1218 | il_send_scan_abort(struct il_priv *il) | |
0cdc2136 SG |
1219 | { |
1220 | int ret; | |
1221 | struct il_rx_pkt *pkt; | |
1222 | struct il_host_cmd cmd = { | |
1223 | .id = C_SCAN_ABORT, | |
1224 | .flags = CMD_WANT_SKB, | |
1225 | }; | |
1226 | ||
1227 | /* Exit instantly with error when device is not ready | |
1228 | * to receive scan abort command or it does not perform | |
1229 | * hardware scan currently */ | |
1230 | if (!test_bit(S_READY, &il->status) || | |
1231 | !test_bit(S_GEO_CONFIGURED, &il->status) || | |
1232 | !test_bit(S_SCAN_HW, &il->status) || | |
1233 | test_bit(S_FW_ERROR, &il->status) || | |
1234 | test_bit(S_EXIT_PENDING, &il->status)) | |
1235 | return -EIO; | |
1236 | ||
1237 | ret = il_send_cmd_sync(il, &cmd); | |
1238 | if (ret) | |
1239 | return ret; | |
1240 | ||
1241 | pkt = (struct il_rx_pkt *)cmd.reply_page; | |
1242 | if (pkt->u.status != CAN_ABORT_STATUS) { | |
1243 | /* The scan abort will return 1 for success or | |
1244 | * 2 for "failure". A failure condition can be | |
1245 | * due to simply not being in an active scan which | |
1246 | * can occur if we send the scan abort before we | |
1247 | * the microcode has notified us that a scan is | |
1248 | * completed. */ | |
1249 | D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status); | |
1250 | ret = -EIO; | |
1251 | } | |
1252 | ||
1253 | il_free_pages(il, cmd.reply_page); | |
1254 | return ret; | |
1255 | } | |
1256 | ||
e7392364 SG |
1257 | static void |
1258 | il_complete_scan(struct il_priv *il, bool aborted) | |
0cdc2136 SG |
1259 | { |
1260 | /* check if scan was requested from mac80211 */ | |
1261 | if (il->scan_request) { | |
1262 | D_SCAN("Complete scan in mac80211\n"); | |
1263 | ieee80211_scan_completed(il->hw, aborted); | |
1264 | } | |
1265 | ||
1266 | il->scan_vif = NULL; | |
1267 | il->scan_request = NULL; | |
1268 | } | |
1269 | ||
e7392364 SG |
1270 | void |
1271 | il_force_scan_end(struct il_priv *il) | |
0cdc2136 SG |
1272 | { |
1273 | lockdep_assert_held(&il->mutex); | |
1274 | ||
1275 | if (!test_bit(S_SCANNING, &il->status)) { | |
1276 | D_SCAN("Forcing scan end while not scanning\n"); | |
1277 | return; | |
1278 | } | |
1279 | ||
1280 | D_SCAN("Forcing scan end\n"); | |
1281 | clear_bit(S_SCANNING, &il->status); | |
1282 | clear_bit(S_SCAN_HW, &il->status); | |
1283 | clear_bit(S_SCAN_ABORTING, &il->status); | |
1284 | il_complete_scan(il, true); | |
1285 | } | |
1286 | ||
e7392364 SG |
1287 | static void |
1288 | il_do_scan_abort(struct il_priv *il) | |
0cdc2136 SG |
1289 | { |
1290 | int ret; | |
1291 | ||
1292 | lockdep_assert_held(&il->mutex); | |
1293 | ||
1294 | if (!test_bit(S_SCANNING, &il->status)) { | |
1295 | D_SCAN("Not performing scan to abort\n"); | |
1296 | return; | |
1297 | } | |
1298 | ||
1299 | if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) { | |
1300 | D_SCAN("Scan abort in progress\n"); | |
1301 | return; | |
1302 | } | |
1303 | ||
1304 | ret = il_send_scan_abort(il); | |
1305 | if (ret) { | |
1306 | D_SCAN("Send scan abort failed %d\n", ret); | |
1307 | il_force_scan_end(il); | |
1308 | } else | |
1309 | D_SCAN("Successfully send scan abort\n"); | |
1310 | } | |
1311 | ||
1312 | /** | |
1313 | * il_scan_cancel - Cancel any currently executing HW scan | |
1314 | */ | |
e7392364 SG |
1315 | int |
1316 | il_scan_cancel(struct il_priv *il) | |
0cdc2136 SG |
1317 | { |
1318 | D_SCAN("Queuing abort scan\n"); | |
1319 | queue_work(il->workqueue, &il->abort_scan); | |
1320 | return 0; | |
1321 | } | |
1322 | EXPORT_SYMBOL(il_scan_cancel); | |
1323 | ||
1324 | /** | |
1325 | * il_scan_cancel_timeout - Cancel any currently executing HW scan | |
1326 | * @ms: amount of time to wait (in milliseconds) for scan to abort | |
1327 | * | |
1328 | */ | |
e7392364 SG |
1329 | int |
1330 | il_scan_cancel_timeout(struct il_priv *il, unsigned long ms) | |
0cdc2136 SG |
1331 | { |
1332 | unsigned long timeout = jiffies + msecs_to_jiffies(ms); | |
1333 | ||
1334 | lockdep_assert_held(&il->mutex); | |
1335 | ||
1336 | D_SCAN("Scan cancel timeout\n"); | |
1337 | ||
1338 | il_do_scan_abort(il); | |
1339 | ||
1340 | while (time_before_eq(jiffies, timeout)) { | |
1341 | if (!test_bit(S_SCAN_HW, &il->status)) | |
1342 | break; | |
1343 | msleep(20); | |
1344 | } | |
1345 | ||
1346 | return test_bit(S_SCAN_HW, &il->status); | |
1347 | } | |
1348 | EXPORT_SYMBOL(il_scan_cancel_timeout); | |
1349 | ||
1350 | /* Service response to C_SCAN (0x80) */ | |
e7392364 SG |
1351 | static void |
1352 | il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1353 | { |
1354 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1355 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1356 | struct il_scanreq_notification *notif = | |
1357 | (struct il_scanreq_notification *)pkt->u.raw; | |
1358 | ||
1359 | D_SCAN("Scan request status = 0x%x\n", notif->status); | |
1360 | #endif | |
1361 | } | |
1362 | ||
1363 | /* Service N_SCAN_START (0x82) */ | |
e7392364 SG |
1364 | static void |
1365 | il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1366 | { |
1367 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1368 | struct il_scanstart_notification *notif = | |
1369 | (struct il_scanstart_notification *)pkt->u.raw; | |
1370 | il->scan_start_tsf = le32_to_cpu(notif->tsf_low); | |
e7392364 SG |
1371 | D_SCAN("Scan start: " "%d [802.11%s] " |
1372 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel, | |
1373 | notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high), | |
1374 | le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer); | |
0cdc2136 SG |
1375 | } |
1376 | ||
1377 | /* Service N_SCAN_RESULTS (0x83) */ | |
e7392364 SG |
1378 | static void |
1379 | il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1380 | { |
1381 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1382 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1383 | struct il_scanresults_notification *notif = | |
1384 | (struct il_scanresults_notification *)pkt->u.raw; | |
1385 | ||
e7392364 SG |
1386 | D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d " |
1387 | "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a", | |
1388 | le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low), | |
1389 | le32_to_cpu(notif->stats[0]), | |
1390 | le32_to_cpu(notif->tsf_low) - il->scan_start_tsf); | |
0cdc2136 SG |
1391 | #endif |
1392 | } | |
1393 | ||
1394 | /* Service N_SCAN_COMPLETE (0x84) */ | |
e7392364 SG |
1395 | static void |
1396 | il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1397 | { |
1398 | ||
1399 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1400 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1401 | struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
1402 | #endif | |
1403 | ||
e7392364 SG |
1404 | D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", |
1405 | scan_notif->scanned_channels, scan_notif->tsf_low, | |
1406 | scan_notif->tsf_high, scan_notif->status); | |
0cdc2136 SG |
1407 | |
1408 | /* The HW is no longer scanning */ | |
1409 | clear_bit(S_SCAN_HW, &il->status); | |
1410 | ||
1411 | D_SCAN("Scan on %sGHz took %dms\n", | |
e7392364 SG |
1412 | (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2", |
1413 | jiffies_to_msecs(jiffies - il->scan_start)); | |
0cdc2136 SG |
1414 | |
1415 | queue_work(il->workqueue, &il->scan_completed); | |
1416 | } | |
1417 | ||
e7392364 SG |
1418 | void |
1419 | il_setup_rx_scan_handlers(struct il_priv *il) | |
0cdc2136 SG |
1420 | { |
1421 | /* scan handlers */ | |
1422 | il->handlers[C_SCAN] = il_hdl_scan; | |
e7392364 SG |
1423 | il->handlers[N_SCAN_START] = il_hdl_scan_start; |
1424 | il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results; | |
1425 | il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete; | |
0cdc2136 SG |
1426 | } |
1427 | EXPORT_SYMBOL(il_setup_rx_scan_handlers); | |
1428 | ||
e7392364 SG |
1429 | inline u16 |
1430 | il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band, | |
1431 | u8 n_probes) | |
0cdc2136 SG |
1432 | { |
1433 | if (band == IEEE80211_BAND_5GHZ) | |
1434 | return IL_ACTIVE_DWELL_TIME_52 + | |
e7392364 | 1435 | IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1); |
0cdc2136 SG |
1436 | else |
1437 | return IL_ACTIVE_DWELL_TIME_24 + | |
e7392364 | 1438 | IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1); |
0cdc2136 SG |
1439 | } |
1440 | EXPORT_SYMBOL(il_get_active_dwell_time); | |
1441 | ||
e7392364 | 1442 | u16 |
1722f8e1 SG |
1443 | il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band, |
1444 | struct ieee80211_vif *vif) | |
0cdc2136 | 1445 | { |
0cdc2136 SG |
1446 | u16 value; |
1447 | ||
e7392364 SG |
1448 | u16 passive = |
1449 | (band == | |
1450 | IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE + | |
1451 | IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE + | |
1452 | IL_PASSIVE_DWELL_TIME_52; | |
0cdc2136 SG |
1453 | |
1454 | if (il_is_any_associated(il)) { | |
1455 | /* | |
1456 | * If we're associated, we clamp the maximum passive | |
1457 | * dwell time to be 98% of the smallest beacon interval | |
1458 | * (minus 2 * channel tune time) | |
1459 | */ | |
83007196 | 1460 | value = il->vif ? il->vif->bss_conf.beacon_int : 0; |
0cdc2136 SG |
1461 | if (value > IL_PASSIVE_DWELL_BASE || !value) |
1462 | value = IL_PASSIVE_DWELL_BASE; | |
1463 | value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2; | |
1464 | passive = min(value, passive); | |
1465 | } | |
1466 | ||
1467 | return passive; | |
1468 | } | |
1469 | EXPORT_SYMBOL(il_get_passive_dwell_time); | |
1470 | ||
e7392364 SG |
1471 | void |
1472 | il_init_scan_params(struct il_priv *il) | |
0cdc2136 SG |
1473 | { |
1474 | u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1; | |
1475 | if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ]) | |
1476 | il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx; | |
1477 | if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ]) | |
1478 | il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx; | |
1479 | } | |
1480 | EXPORT_SYMBOL(il_init_scan_params); | |
1481 | ||
e7392364 SG |
1482 | static int |
1483 | il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif) | |
0cdc2136 SG |
1484 | { |
1485 | int ret; | |
1486 | ||
1487 | lockdep_assert_held(&il->mutex); | |
1488 | ||
c39ae9fd | 1489 | if (WARN_ON(!il->ops->utils->request_scan)) |
0cdc2136 SG |
1490 | return -EOPNOTSUPP; |
1491 | ||
1492 | cancel_delayed_work(&il->scan_check); | |
1493 | ||
1494 | if (!il_is_ready_rf(il)) { | |
1495 | IL_WARN("Request scan called when driver not ready.\n"); | |
1496 | return -EIO; | |
1497 | } | |
1498 | ||
1499 | if (test_bit(S_SCAN_HW, &il->status)) { | |
e7392364 | 1500 | D_SCAN("Multiple concurrent scan requests in parallel.\n"); |
0cdc2136 SG |
1501 | return -EBUSY; |
1502 | } | |
1503 | ||
1504 | if (test_bit(S_SCAN_ABORTING, &il->status)) { | |
1505 | D_SCAN("Scan request while abort pending.\n"); | |
1506 | return -EBUSY; | |
1507 | } | |
1508 | ||
1509 | D_SCAN("Starting scan...\n"); | |
1510 | ||
1511 | set_bit(S_SCANNING, &il->status); | |
1512 | il->scan_start = jiffies; | |
1513 | ||
c39ae9fd | 1514 | ret = il->ops->utils->request_scan(il, vif); |
0cdc2136 SG |
1515 | if (ret) { |
1516 | clear_bit(S_SCANNING, &il->status); | |
1517 | return ret; | |
1518 | } | |
1519 | ||
1520 | queue_delayed_work(il->workqueue, &il->scan_check, | |
1521 | IL_SCAN_CHECK_WATCHDOG); | |
1522 | ||
1523 | return 0; | |
1524 | } | |
1525 | ||
e7392364 SG |
1526 | int |
1527 | il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
1528 | struct cfg80211_scan_request *req) | |
0cdc2136 SG |
1529 | { |
1530 | struct il_priv *il = hw->priv; | |
1531 | int ret; | |
1532 | ||
1533 | D_MAC80211("enter\n"); | |
1534 | ||
1535 | if (req->n_channels == 0) | |
1536 | return -EINVAL; | |
1537 | ||
1538 | mutex_lock(&il->mutex); | |
1539 | ||
1540 | if (test_bit(S_SCANNING, &il->status)) { | |
1541 | D_SCAN("Scan already in progress.\n"); | |
1542 | ret = -EAGAIN; | |
1543 | goto out_unlock; | |
1544 | } | |
1545 | ||
1546 | /* mac80211 will only ask for one band at a time */ | |
1547 | il->scan_request = req; | |
1548 | il->scan_vif = vif; | |
1549 | il->scan_band = req->channels[0]->band; | |
1550 | ||
1551 | ret = il_scan_initiate(il, vif); | |
1552 | ||
1553 | D_MAC80211("leave\n"); | |
1554 | ||
1555 | out_unlock: | |
1556 | mutex_unlock(&il->mutex); | |
1557 | ||
1558 | return ret; | |
1559 | } | |
1560 | EXPORT_SYMBOL(il_mac_hw_scan); | |
1561 | ||
e7392364 SG |
1562 | static void |
1563 | il_bg_scan_check(struct work_struct *data) | |
0cdc2136 SG |
1564 | { |
1565 | struct il_priv *il = | |
1566 | container_of(data, struct il_priv, scan_check.work); | |
1567 | ||
1568 | D_SCAN("Scan check work\n"); | |
1569 | ||
1570 | /* Since we are here firmware does not finish scan and | |
1571 | * most likely is in bad shape, so we don't bother to | |
1572 | * send abort command, just force scan complete to mac80211 */ | |
1573 | mutex_lock(&il->mutex); | |
1574 | il_force_scan_end(il); | |
1575 | mutex_unlock(&il->mutex); | |
1576 | } | |
1577 | ||
1578 | /** | |
1579 | * il_fill_probe_req - fill in all required fields and IE for probe request | |
1580 | */ | |
1581 | ||
1582 | u16 | |
1583 | il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame, | |
1722f8e1 | 1584 | const u8 *ta, const u8 *ies, int ie_len, int left) |
0cdc2136 SG |
1585 | { |
1586 | int len = 0; | |
1587 | u8 *pos = NULL; | |
1588 | ||
1589 | /* Make sure there is enough space for the probe request, | |
1590 | * two mandatory IEs and the data */ | |
1591 | left -= 24; | |
1592 | if (left < 0) | |
1593 | return 0; | |
1594 | ||
1595 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
1596 | memcpy(frame->da, il_bcast_addr, ETH_ALEN); | |
1597 | memcpy(frame->sa, ta, ETH_ALEN); | |
1598 | memcpy(frame->bssid, il_bcast_addr, ETH_ALEN); | |
1599 | frame->seq_ctrl = 0; | |
1600 | ||
1601 | len += 24; | |
1602 | ||
1603 | /* ...next IE... */ | |
1604 | pos = &frame->u.probe_req.variable[0]; | |
1605 | ||
1606 | /* fill in our indirect SSID IE */ | |
1607 | left -= 2; | |
1608 | if (left < 0) | |
1609 | return 0; | |
1610 | *pos++ = WLAN_EID_SSID; | |
1611 | *pos++ = 0; | |
1612 | ||
1613 | len += 2; | |
1614 | ||
1615 | if (WARN_ON(left < ie_len)) | |
1616 | return len; | |
1617 | ||
1618 | if (ies && ie_len) { | |
1619 | memcpy(pos, ies, ie_len); | |
1620 | len += ie_len; | |
1621 | } | |
1622 | ||
e7392364 | 1623 | return (u16) len; |
0cdc2136 SG |
1624 | } |
1625 | EXPORT_SYMBOL(il_fill_probe_req); | |
1626 | ||
e7392364 SG |
1627 | static void |
1628 | il_bg_abort_scan(struct work_struct *work) | |
0cdc2136 SG |
1629 | { |
1630 | struct il_priv *il = container_of(work, struct il_priv, abort_scan); | |
1631 | ||
1632 | D_SCAN("Abort scan work\n"); | |
1633 | ||
1634 | /* We keep scan_check work queued in case when firmware will not | |
1635 | * report back scan completed notification */ | |
1636 | mutex_lock(&il->mutex); | |
1637 | il_scan_cancel_timeout(il, 200); | |
1638 | mutex_unlock(&il->mutex); | |
1639 | } | |
1640 | ||
e7392364 SG |
1641 | static void |
1642 | il_bg_scan_completed(struct work_struct *work) | |
0cdc2136 | 1643 | { |
e7392364 | 1644 | struct il_priv *il = container_of(work, struct il_priv, scan_completed); |
0cdc2136 SG |
1645 | bool aborted; |
1646 | ||
1647 | D_SCAN("Completed scan.\n"); | |
1648 | ||
1649 | cancel_delayed_work(&il->scan_check); | |
1650 | ||
1651 | mutex_lock(&il->mutex); | |
1652 | ||
1653 | aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status); | |
1654 | if (aborted) | |
1655 | D_SCAN("Aborted scan completed.\n"); | |
1656 | ||
1657 | if (!test_and_clear_bit(S_SCANNING, &il->status)) { | |
1658 | D_SCAN("Scan already completed.\n"); | |
1659 | goto out_settings; | |
1660 | } | |
1661 | ||
1662 | il_complete_scan(il, aborted); | |
1663 | ||
1664 | out_settings: | |
1665 | /* Can we still talk to firmware ? */ | |
1666 | if (!il_is_ready_rf(il)) | |
1667 | goto out; | |
1668 | ||
1669 | /* | |
1670 | * We do not commit power settings while scan is pending, | |
1671 | * do it now if the settings changed. | |
1672 | */ | |
1673 | il_power_set_mode(il, &il->power_data.sleep_cmd_next, false); | |
1674 | il_set_tx_power(il, il->tx_power_next, false); | |
1675 | ||
c39ae9fd | 1676 | il->ops->utils->post_scan(il); |
0cdc2136 SG |
1677 | |
1678 | out: | |
1679 | mutex_unlock(&il->mutex); | |
1680 | } | |
1681 | ||
e7392364 SG |
1682 | void |
1683 | il_setup_scan_deferred_work(struct il_priv *il) | |
0cdc2136 SG |
1684 | { |
1685 | INIT_WORK(&il->scan_completed, il_bg_scan_completed); | |
1686 | INIT_WORK(&il->abort_scan, il_bg_abort_scan); | |
1687 | INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check); | |
1688 | } | |
1689 | EXPORT_SYMBOL(il_setup_scan_deferred_work); | |
1690 | ||
e7392364 SG |
1691 | void |
1692 | il_cancel_scan_deferred_work(struct il_priv *il) | |
0cdc2136 SG |
1693 | { |
1694 | cancel_work_sync(&il->abort_scan); | |
1695 | cancel_work_sync(&il->scan_completed); | |
1696 | ||
1697 | if (cancel_delayed_work_sync(&il->scan_check)) { | |
1698 | mutex_lock(&il->mutex); | |
1699 | il_force_scan_end(il); | |
1700 | mutex_unlock(&il->mutex); | |
1701 | } | |
1702 | } | |
1703 | EXPORT_SYMBOL(il_cancel_scan_deferred_work); | |
1704 | ||
1705 | /* il->sta_lock must be held */ | |
e7392364 SG |
1706 | static void |
1707 | il_sta_ucode_activate(struct il_priv *il, u8 sta_id) | |
0cdc2136 SG |
1708 | { |
1709 | ||
1710 | if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) | |
e7392364 SG |
1711 | IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n", |
1712 | sta_id, il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1713 | |
1714 | if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) { | |
e7392364 SG |
1715 | D_ASSOC("STA id %u addr %pM already present" |
1716 | " in uCode (according to driver)\n", sta_id, | |
1717 | il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1718 | } else { |
1719 | il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE; | |
e7392364 SG |
1720 | D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id, |
1721 | il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1722 | } |
1723 | } | |
1724 | ||
e7392364 SG |
1725 | static int |
1726 | il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta, | |
1727 | struct il_rx_pkt *pkt, bool sync) | |
0cdc2136 SG |
1728 | { |
1729 | u8 sta_id = addsta->sta.sta_id; | |
1730 | unsigned long flags; | |
1731 | int ret = -EIO; | |
1732 | ||
1733 | if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { | |
e7392364 | 1734 | IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags); |
0cdc2136 SG |
1735 | return ret; |
1736 | } | |
1737 | ||
e7392364 | 1738 | D_INFO("Processing response for adding station %u\n", sta_id); |
0cdc2136 SG |
1739 | |
1740 | spin_lock_irqsave(&il->sta_lock, flags); | |
1741 | ||
1742 | switch (pkt->u.add_sta.status) { | |
1743 | case ADD_STA_SUCCESS_MSK: | |
1744 | D_INFO("C_ADD_STA PASSED\n"); | |
1745 | il_sta_ucode_activate(il, sta_id); | |
1746 | ret = 0; | |
1747 | break; | |
1748 | case ADD_STA_NO_ROOM_IN_TBL: | |
e7392364 | 1749 | IL_ERR("Adding station %d failed, no room in table.\n", sta_id); |
0cdc2136 SG |
1750 | break; |
1751 | case ADD_STA_NO_BLOCK_ACK_RESOURCE: | |
e7392364 SG |
1752 | IL_ERR("Adding station %d failed, no block ack resource.\n", |
1753 | sta_id); | |
0cdc2136 SG |
1754 | break; |
1755 | case ADD_STA_MODIFY_NON_EXIST_STA: | |
1756 | IL_ERR("Attempting to modify non-existing station %d\n", | |
e7392364 | 1757 | sta_id); |
0cdc2136 SG |
1758 | break; |
1759 | default: | |
e7392364 | 1760 | D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status); |
0cdc2136 SG |
1761 | break; |
1762 | } | |
1763 | ||
1764 | D_INFO("%s station id %u addr %pM\n", | |
e7392364 SG |
1765 | il->stations[sta_id].sta.mode == |
1766 | STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id, | |
1767 | il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1768 | |
1769 | /* | |
1770 | * XXX: The MAC address in the command buffer is often changed from | |
1771 | * the original sent to the device. That is, the MAC address | |
1772 | * written to the command buffer often is not the same MAC address | |
1773 | * read from the command buffer when the command returns. This | |
1774 | * issue has not yet been resolved and this debugging is left to | |
1775 | * observe the problem. | |
1776 | */ | |
1777 | D_INFO("%s station according to cmd buffer %pM\n", | |
e7392364 SG |
1778 | il->stations[sta_id].sta.mode == |
1779 | STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr); | |
0cdc2136 SG |
1780 | spin_unlock_irqrestore(&il->sta_lock, flags); |
1781 | ||
1782 | return ret; | |
1783 | } | |
1784 | ||
e7392364 SG |
1785 | static void |
1786 | il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd, | |
1787 | struct il_rx_pkt *pkt) | |
0cdc2136 | 1788 | { |
e7392364 | 1789 | struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload; |
0cdc2136 SG |
1790 | |
1791 | il_process_add_sta_resp(il, addsta, pkt, false); | |
1792 | ||
1793 | } | |
1794 | ||
e7392364 SG |
1795 | int |
1796 | il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags) | |
0cdc2136 SG |
1797 | { |
1798 | struct il_rx_pkt *pkt = NULL; | |
1799 | int ret = 0; | |
1800 | u8 data[sizeof(*sta)]; | |
1801 | struct il_host_cmd cmd = { | |
1802 | .id = C_ADD_STA, | |
1803 | .flags = flags, | |
1804 | .data = data, | |
1805 | }; | |
1806 | u8 sta_id __maybe_unused = sta->sta.sta_id; | |
1807 | ||
e7392364 SG |
1808 | D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr, |
1809 | flags & CMD_ASYNC ? "a" : ""); | |
0cdc2136 SG |
1810 | |
1811 | if (flags & CMD_ASYNC) | |
1812 | cmd.callback = il_add_sta_callback; | |
1813 | else { | |
1814 | cmd.flags |= CMD_WANT_SKB; | |
1815 | might_sleep(); | |
1816 | } | |
1817 | ||
c39ae9fd | 1818 | cmd.len = il->ops->utils->build_addsta_hcmd(sta, data); |
0cdc2136 SG |
1819 | ret = il_send_cmd(il, &cmd); |
1820 | ||
1821 | if (ret || (flags & CMD_ASYNC)) | |
1822 | return ret; | |
1823 | ||
1824 | if (ret == 0) { | |
1825 | pkt = (struct il_rx_pkt *)cmd.reply_page; | |
1826 | ret = il_process_add_sta_resp(il, sta, pkt, true); | |
1827 | } | |
1828 | il_free_pages(il, cmd.reply_page); | |
1829 | ||
1830 | return ret; | |
1831 | } | |
1832 | EXPORT_SYMBOL(il_send_add_sta); | |
1833 | ||
e7392364 | 1834 | static void |
83007196 | 1835 | il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta) |
0cdc2136 SG |
1836 | { |
1837 | struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap; | |
1838 | __le32 sta_flags; | |
1839 | u8 mimo_ps_mode; | |
1840 | ||
1841 | if (!sta || !sta_ht_inf->ht_supported) | |
1842 | goto done; | |
1843 | ||
1844 | mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2; | |
1845 | D_ASSOC("spatial multiplexing power save mode: %s\n", | |
1722f8e1 SG |
1846 | (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ? "static" : |
1847 | (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ? "dynamic" : | |
1848 | "disabled"); | |
0cdc2136 SG |
1849 | |
1850 | sta_flags = il->stations[idx].sta.station_flags; | |
1851 | ||
1852 | sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK); | |
1853 | ||
1854 | switch (mimo_ps_mode) { | |
1855 | case WLAN_HT_CAP_SM_PS_STATIC: | |
1856 | sta_flags |= STA_FLG_MIMO_DIS_MSK; | |
1857 | break; | |
1858 | case WLAN_HT_CAP_SM_PS_DYNAMIC: | |
1859 | sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK; | |
1860 | break; | |
1861 | case WLAN_HT_CAP_SM_PS_DISABLED: | |
1862 | break; | |
1863 | default: | |
1864 | IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode); | |
1865 | break; | |
1866 | } | |
1867 | ||
e7392364 SG |
1868 | sta_flags |= |
1869 | cpu_to_le32((u32) sta_ht_inf-> | |
1870 | ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS); | |
0cdc2136 | 1871 | |
e7392364 SG |
1872 | sta_flags |= |
1873 | cpu_to_le32((u32) sta_ht_inf-> | |
1874 | ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS); | |
0cdc2136 | 1875 | |
83007196 | 1876 | if (il_is_ht40_tx_allowed(il, &sta->ht_cap)) |
0cdc2136 SG |
1877 | sta_flags |= STA_FLG_HT40_EN_MSK; |
1878 | else | |
1879 | sta_flags &= ~STA_FLG_HT40_EN_MSK; | |
1880 | ||
1881 | il->stations[idx].sta.station_flags = sta_flags; | |
e7392364 | 1882 | done: |
0cdc2136 SG |
1883 | return; |
1884 | } | |
1885 | ||
1886 | /** | |
1887 | * il_prep_station - Prepare station information for addition | |
1888 | * | |
1889 | * should be called with sta_lock held | |
1890 | */ | |
e7392364 | 1891 | u8 |
83007196 SG |
1892 | il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap, |
1893 | struct ieee80211_sta *sta) | |
0cdc2136 SG |
1894 | { |
1895 | struct il_station_entry *station; | |
1896 | int i; | |
1897 | u8 sta_id = IL_INVALID_STATION; | |
1898 | u16 rate; | |
1899 | ||
1900 | if (is_ap) | |
8f9e5645 | 1901 | sta_id = IL_AP_ID; |
0cdc2136 | 1902 | else if (is_broadcast_ether_addr(addr)) |
b16db50a | 1903 | sta_id = il->hw_params.bcast_id; |
0cdc2136 SG |
1904 | else |
1905 | for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) { | |
e7392364 SG |
1906 | if (!compare_ether_addr |
1907 | (il->stations[i].sta.sta.addr, addr)) { | |
0cdc2136 SG |
1908 | sta_id = i; |
1909 | break; | |
1910 | } | |
1911 | ||
1912 | if (!il->stations[i].used && | |
1913 | sta_id == IL_INVALID_STATION) | |
1914 | sta_id = i; | |
1915 | } | |
1916 | ||
1917 | /* | |
1918 | * These two conditions have the same outcome, but keep them | |
1919 | * separate | |
1920 | */ | |
1921 | if (unlikely(sta_id == IL_INVALID_STATION)) | |
1922 | return sta_id; | |
1923 | ||
1924 | /* | |
1925 | * uCode is not able to deal with multiple requests to add a | |
1926 | * station. Keep track if one is in progress so that we do not send | |
1927 | * another. | |
1928 | */ | |
1929 | if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) { | |
e7392364 | 1930 | D_INFO("STA %d already in process of being added.\n", sta_id); |
0cdc2136 SG |
1931 | return sta_id; |
1932 | } | |
1933 | ||
1934 | if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) && | |
1935 | (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) && | |
1936 | !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) { | |
e7392364 SG |
1937 | D_ASSOC("STA %d (%pM) already added, not adding again.\n", |
1938 | sta_id, addr); | |
0cdc2136 SG |
1939 | return sta_id; |
1940 | } | |
1941 | ||
1942 | station = &il->stations[sta_id]; | |
1943 | station->used = IL_STA_DRIVER_ACTIVE; | |
e7392364 | 1944 | D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr); |
0cdc2136 SG |
1945 | il->num_stations++; |
1946 | ||
1947 | /* Set up the C_ADD_STA command to send to device */ | |
1948 | memset(&station->sta, 0, sizeof(struct il_addsta_cmd)); | |
1949 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); | |
1950 | station->sta.mode = 0; | |
1951 | station->sta.sta.sta_id = sta_id; | |
fd6415bc | 1952 | station->sta.station_flags = 0; |
0cdc2136 | 1953 | |
0cdc2136 SG |
1954 | /* |
1955 | * OK to call unconditionally, since local stations (IBSS BSSID | |
1956 | * STA and broadcast STA) pass in a NULL sta, and mac80211 | |
1957 | * doesn't allow HT IBSS. | |
1958 | */ | |
83007196 | 1959 | il_set_ht_add_station(il, sta_id, sta); |
0cdc2136 SG |
1960 | |
1961 | /* 3945 only */ | |
e7392364 | 1962 | rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP; |
0cdc2136 SG |
1963 | /* Turn on both antennas for the station... */ |
1964 | station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK); | |
1965 | ||
1966 | return sta_id; | |
1967 | ||
1968 | } | |
1969 | EXPORT_SYMBOL_GPL(il_prep_station); | |
1970 | ||
1971 | #define STA_WAIT_TIMEOUT (HZ/2) | |
1972 | ||
1973 | /** | |
1974 | * il_add_station_common - | |
1975 | */ | |
1976 | int | |
83007196 SG |
1977 | il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap, |
1978 | struct ieee80211_sta *sta, u8 *sta_id_r) | |
0cdc2136 SG |
1979 | { |
1980 | unsigned long flags_spin; | |
1981 | int ret = 0; | |
1982 | u8 sta_id; | |
1983 | struct il_addsta_cmd sta_cmd; | |
1984 | ||
1985 | *sta_id_r = 0; | |
1986 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
83007196 | 1987 | sta_id = il_prep_station(il, addr, is_ap, sta); |
0cdc2136 | 1988 | if (sta_id == IL_INVALID_STATION) { |
e7392364 | 1989 | IL_ERR("Unable to prepare station %pM for addition\n", addr); |
0cdc2136 SG |
1990 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); |
1991 | return -EINVAL; | |
1992 | } | |
1993 | ||
1994 | /* | |
1995 | * uCode is not able to deal with multiple requests to add a | |
1996 | * station. Keep track if one is in progress so that we do not send | |
1997 | * another. | |
1998 | */ | |
1999 | if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) { | |
e7392364 | 2000 | D_INFO("STA %d already in process of being added.\n", sta_id); |
0cdc2136 SG |
2001 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); |
2002 | return -EEXIST; | |
2003 | } | |
2004 | ||
2005 | if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) && | |
2006 | (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) { | |
e7392364 | 2007 | D_ASSOC("STA %d (%pM) already added, not adding again.\n", |
0cdc2136 SG |
2008 | sta_id, addr); |
2009 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2010 | return -EEXIST; | |
2011 | } | |
2012 | ||
2013 | il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS; | |
2014 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 2015 | sizeof(struct il_addsta_cmd)); |
0cdc2136 SG |
2016 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); |
2017 | ||
2018 | /* Add station to device's station table */ | |
2019 | ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
2020 | if (ret) { | |
2021 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2022 | IL_ERR("Adding station %pM failed.\n", | |
e7392364 | 2023 | il->stations[sta_id].sta.sta.addr); |
0cdc2136 SG |
2024 | il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE; |
2025 | il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS; | |
2026 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2027 | } | |
2028 | *sta_id_r = sta_id; | |
2029 | return ret; | |
2030 | } | |
2031 | EXPORT_SYMBOL(il_add_station_common); | |
2032 | ||
2033 | /** | |
2034 | * il_sta_ucode_deactivate - deactivate ucode status for a station | |
2035 | * | |
2036 | * il->sta_lock must be held | |
2037 | */ | |
e7392364 SG |
2038 | static void |
2039 | il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id) | |
0cdc2136 SG |
2040 | { |
2041 | /* Ucode must be active and driver must be non active */ | |
e7392364 SG |
2042 | if ((il->stations[sta_id]. |
2043 | used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) != | |
2044 | IL_STA_UCODE_ACTIVE) | |
0cdc2136 SG |
2045 | IL_ERR("removed non active STA %u\n", sta_id); |
2046 | ||
2047 | il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE; | |
2048 | ||
2049 | memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry)); | |
2050 | D_ASSOC("Removed STA %u\n", sta_id); | |
2051 | } | |
2052 | ||
e7392364 SG |
2053 | static int |
2054 | il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id, | |
2055 | bool temporary) | |
0cdc2136 SG |
2056 | { |
2057 | struct il_rx_pkt *pkt; | |
2058 | int ret; | |
2059 | ||
2060 | unsigned long flags_spin; | |
2061 | struct il_rem_sta_cmd rm_sta_cmd; | |
2062 | ||
2063 | struct il_host_cmd cmd = { | |
2064 | .id = C_REM_STA, | |
2065 | .len = sizeof(struct il_rem_sta_cmd), | |
2066 | .flags = CMD_SYNC, | |
2067 | .data = &rm_sta_cmd, | |
2068 | }; | |
2069 | ||
2070 | memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd)); | |
2071 | rm_sta_cmd.num_sta = 1; | |
2072 | memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN); | |
2073 | ||
2074 | cmd.flags |= CMD_WANT_SKB; | |
2075 | ||
2076 | ret = il_send_cmd(il, &cmd); | |
2077 | ||
2078 | if (ret) | |
2079 | return ret; | |
2080 | ||
2081 | pkt = (struct il_rx_pkt *)cmd.reply_page; | |
2082 | if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { | |
e7392364 | 2083 | IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags); |
0cdc2136 SG |
2084 | ret = -EIO; |
2085 | } | |
2086 | ||
2087 | if (!ret) { | |
2088 | switch (pkt->u.rem_sta.status) { | |
2089 | case REM_STA_SUCCESS_MSK: | |
2090 | if (!temporary) { | |
2091 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2092 | il_sta_ucode_deactivate(il, sta_id); | |
2093 | spin_unlock_irqrestore(&il->sta_lock, | |
e7392364 | 2094 | flags_spin); |
0cdc2136 SG |
2095 | } |
2096 | D_ASSOC("C_REM_STA PASSED\n"); | |
2097 | break; | |
2098 | default: | |
2099 | ret = -EIO; | |
2100 | IL_ERR("C_REM_STA failed\n"); | |
2101 | break; | |
2102 | } | |
2103 | } | |
2104 | il_free_pages(il, cmd.reply_page); | |
2105 | ||
2106 | return ret; | |
2107 | } | |
2108 | ||
2109 | /** | |
2110 | * il_remove_station - Remove driver's knowledge of station. | |
2111 | */ | |
e7392364 SG |
2112 | int |
2113 | il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr) | |
0cdc2136 SG |
2114 | { |
2115 | unsigned long flags; | |
2116 | ||
2117 | if (!il_is_ready(il)) { | |
e7392364 SG |
2118 | D_INFO("Unable to remove station %pM, device not ready.\n", |
2119 | addr); | |
0cdc2136 SG |
2120 | /* |
2121 | * It is typical for stations to be removed when we are | |
2122 | * going down. Return success since device will be down | |
2123 | * soon anyway | |
2124 | */ | |
2125 | return 0; | |
2126 | } | |
2127 | ||
e7392364 | 2128 | D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr); |
0cdc2136 SG |
2129 | |
2130 | if (WARN_ON(sta_id == IL_INVALID_STATION)) | |
2131 | return -EINVAL; | |
2132 | ||
2133 | spin_lock_irqsave(&il->sta_lock, flags); | |
2134 | ||
2135 | if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) { | |
e7392364 | 2136 | D_INFO("Removing %pM but non DRIVER active\n", addr); |
0cdc2136 SG |
2137 | goto out_err; |
2138 | } | |
2139 | ||
2140 | if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) { | |
e7392364 | 2141 | D_INFO("Removing %pM but non UCODE active\n", addr); |
0cdc2136 SG |
2142 | goto out_err; |
2143 | } | |
2144 | ||
2145 | if (il->stations[sta_id].used & IL_STA_LOCAL) { | |
2146 | kfree(il->stations[sta_id].lq); | |
2147 | il->stations[sta_id].lq = NULL; | |
2148 | } | |
2149 | ||
2150 | il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE; | |
2151 | ||
2152 | il->num_stations--; | |
2153 | ||
2154 | BUG_ON(il->num_stations < 0); | |
2155 | ||
2156 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2157 | ||
2158 | return il_send_remove_station(il, addr, sta_id, false); | |
2159 | out_err: | |
2160 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2161 | return -EINVAL; | |
2162 | } | |
2163 | EXPORT_SYMBOL_GPL(il_remove_station); | |
2164 | ||
2165 | /** | |
2166 | * il_clear_ucode_stations - clear ucode station table bits | |
2167 | * | |
2168 | * This function clears all the bits in the driver indicating | |
2169 | * which stations are active in the ucode. Call when something | |
2170 | * other than explicit station management would cause this in | |
2171 | * the ucode, e.g. unassociated RXON. | |
2172 | */ | |
e7392364 | 2173 | void |
83007196 | 2174 | il_clear_ucode_stations(struct il_priv *il) |
0cdc2136 SG |
2175 | { |
2176 | int i; | |
2177 | unsigned long flags_spin; | |
2178 | bool cleared = false; | |
2179 | ||
2180 | D_INFO("Clearing ucode stations in driver\n"); | |
2181 | ||
2182 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2183 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
0cdc2136 | 2184 | if (il->stations[i].used & IL_STA_UCODE_ACTIVE) { |
e7392364 | 2185 | D_INFO("Clearing ucode active for station %d\n", i); |
0cdc2136 SG |
2186 | il->stations[i].used &= ~IL_STA_UCODE_ACTIVE; |
2187 | cleared = true; | |
2188 | } | |
2189 | } | |
2190 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2191 | ||
2192 | if (!cleared) | |
e7392364 | 2193 | D_INFO("No active stations found to be cleared\n"); |
0cdc2136 SG |
2194 | } |
2195 | EXPORT_SYMBOL(il_clear_ucode_stations); | |
2196 | ||
2197 | /** | |
2198 | * il_restore_stations() - Restore driver known stations to device | |
2199 | * | |
2200 | * All stations considered active by driver, but not present in ucode, is | |
2201 | * restored. | |
2202 | * | |
2203 | * Function sleeps. | |
2204 | */ | |
2205 | void | |
83007196 | 2206 | il_restore_stations(struct il_priv *il) |
0cdc2136 SG |
2207 | { |
2208 | struct il_addsta_cmd sta_cmd; | |
2209 | struct il_link_quality_cmd lq; | |
2210 | unsigned long flags_spin; | |
2211 | int i; | |
2212 | bool found = false; | |
2213 | int ret; | |
2214 | bool send_lq; | |
2215 | ||
2216 | if (!il_is_ready(il)) { | |
e7392364 | 2217 | D_INFO("Not ready yet, not restoring any stations.\n"); |
0cdc2136 SG |
2218 | return; |
2219 | } | |
2220 | ||
2221 | D_ASSOC("Restoring all known stations ... start.\n"); | |
2222 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2223 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
0cdc2136 SG |
2224 | if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) && |
2225 | !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) { | |
2226 | D_ASSOC("Restoring sta %pM\n", | |
e7392364 | 2227 | il->stations[i].sta.sta.addr); |
0cdc2136 SG |
2228 | il->stations[i].sta.mode = 0; |
2229 | il->stations[i].used |= IL_STA_UCODE_INPROGRESS; | |
2230 | found = true; | |
2231 | } | |
2232 | } | |
2233 | ||
2234 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
2235 | if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) { | |
2236 | memcpy(&sta_cmd, &il->stations[i].sta, | |
2237 | sizeof(struct il_addsta_cmd)); | |
2238 | send_lq = false; | |
2239 | if (il->stations[i].lq) { | |
2240 | memcpy(&lq, il->stations[i].lq, | |
2241 | sizeof(struct il_link_quality_cmd)); | |
2242 | send_lq = true; | |
2243 | } | |
2244 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2245 | ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
2246 | if (ret) { | |
2247 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2248 | IL_ERR("Adding station %pM failed.\n", | |
e7392364 SG |
2249 | il->stations[i].sta.sta.addr); |
2250 | il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE; | |
0cdc2136 | 2251 | il->stations[i].used &= |
e7392364 | 2252 | ~IL_STA_UCODE_INPROGRESS; |
0cdc2136 | 2253 | spin_unlock_irqrestore(&il->sta_lock, |
e7392364 | 2254 | flags_spin); |
0cdc2136 SG |
2255 | } |
2256 | /* | |
2257 | * Rate scaling has already been initialized, send | |
2258 | * current LQ command | |
2259 | */ | |
2260 | if (send_lq) | |
83007196 | 2261 | il_send_lq_cmd(il, &lq, CMD_SYNC, true); |
0cdc2136 SG |
2262 | spin_lock_irqsave(&il->sta_lock, flags_spin); |
2263 | il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS; | |
2264 | } | |
2265 | } | |
2266 | ||
2267 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2268 | if (!found) | |
2269 | D_INFO("Restoring all known stations" | |
e7392364 | 2270 | " .... no stations to be restored.\n"); |
0cdc2136 | 2271 | else |
e7392364 | 2272 | D_INFO("Restoring all known stations" " .... complete.\n"); |
0cdc2136 SG |
2273 | } |
2274 | EXPORT_SYMBOL(il_restore_stations); | |
2275 | ||
e7392364 SG |
2276 | int |
2277 | il_get_free_ucode_key_idx(struct il_priv *il) | |
0cdc2136 SG |
2278 | { |
2279 | int i; | |
2280 | ||
2281 | for (i = 0; i < il->sta_key_max_num; i++) | |
2282 | if (!test_and_set_bit(i, &il->ucode_key_table)) | |
2283 | return i; | |
2284 | ||
2285 | return WEP_INVALID_OFFSET; | |
2286 | } | |
2287 | EXPORT_SYMBOL(il_get_free_ucode_key_idx); | |
2288 | ||
e7392364 SG |
2289 | void |
2290 | il_dealloc_bcast_stations(struct il_priv *il) | |
0cdc2136 SG |
2291 | { |
2292 | unsigned long flags; | |
2293 | int i; | |
2294 | ||
2295 | spin_lock_irqsave(&il->sta_lock, flags); | |
2296 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
2297 | if (!(il->stations[i].used & IL_STA_BCAST)) | |
2298 | continue; | |
2299 | ||
2300 | il->stations[i].used &= ~IL_STA_UCODE_ACTIVE; | |
2301 | il->num_stations--; | |
2302 | BUG_ON(il->num_stations < 0); | |
2303 | kfree(il->stations[i].lq); | |
2304 | il->stations[i].lq = NULL; | |
2305 | } | |
2306 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2307 | } | |
2308 | EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations); | |
2309 | ||
2310 | #ifdef CONFIG_IWLEGACY_DEBUG | |
e7392364 SG |
2311 | static void |
2312 | il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq) | |
0cdc2136 SG |
2313 | { |
2314 | int i; | |
2315 | D_RATE("lq station id 0x%x\n", lq->sta_id); | |
e7392364 SG |
2316 | D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk, |
2317 | lq->general_params.dual_stream_ant_msk); | |
0cdc2136 SG |
2318 | |
2319 | for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) | |
e7392364 | 2320 | D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags); |
0cdc2136 SG |
2321 | } |
2322 | #else | |
e7392364 SG |
2323 | static inline void |
2324 | il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq) | |
0cdc2136 SG |
2325 | { |
2326 | } | |
2327 | #endif | |
2328 | ||
2329 | /** | |
2330 | * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity | |
2331 | * | |
2332 | * It sometimes happens when a HT rate has been in use and we | |
2333 | * loose connectivity with AP then mac80211 will first tell us that the | |
2334 | * current channel is not HT anymore before removing the station. In such a | |
2335 | * scenario the RXON flags will be updated to indicate we are not | |
2336 | * communicating HT anymore, but the LQ command may still contain HT rates. | |
2337 | * Test for this to prevent driver from sending LQ command between the time | |
2338 | * RXON flags are updated and when LQ command is updated. | |
2339 | */ | |
e7392364 | 2340 | static bool |
83007196 | 2341 | il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq) |
0cdc2136 SG |
2342 | { |
2343 | int i; | |
2344 | ||
1c03c462 | 2345 | if (il->ht.enabled) |
0cdc2136 SG |
2346 | return true; |
2347 | ||
c8b03958 | 2348 | D_INFO("Channel %u is not an HT channel\n", il->active.channel); |
0cdc2136 | 2349 | for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) { |
e7392364 SG |
2350 | if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) { |
2351 | D_INFO("idx %d of LQ expects HT channel\n", i); | |
0cdc2136 SG |
2352 | return false; |
2353 | } | |
2354 | } | |
2355 | return true; | |
2356 | } | |
2357 | ||
2358 | /** | |
2359 | * il_send_lq_cmd() - Send link quality command | |
2360 | * @init: This command is sent as part of station initialization right | |
2361 | * after station has been added. | |
2362 | * | |
2363 | * The link quality command is sent as the last step of station creation. | |
2364 | * This is the special case in which init is set and we call a callback in | |
2365 | * this case to clear the state indicating that station creation is in | |
2366 | * progress. | |
2367 | */ | |
e7392364 | 2368 | int |
83007196 SG |
2369 | il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq, |
2370 | u8 flags, bool init) | |
0cdc2136 SG |
2371 | { |
2372 | int ret = 0; | |
2373 | unsigned long flags_spin; | |
2374 | ||
2375 | struct il_host_cmd cmd = { | |
2376 | .id = C_TX_LINK_QUALITY_CMD, | |
2377 | .len = sizeof(struct il_link_quality_cmd), | |
2378 | .flags = flags, | |
2379 | .data = lq, | |
2380 | }; | |
2381 | ||
2382 | if (WARN_ON(lq->sta_id == IL_INVALID_STATION)) | |
2383 | return -EINVAL; | |
2384 | ||
0cdc2136 SG |
2385 | spin_lock_irqsave(&il->sta_lock, flags_spin); |
2386 | if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) { | |
2387 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2388 | return -EINVAL; | |
2389 | } | |
2390 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2391 | ||
2392 | il_dump_lq_cmd(il, lq); | |
2393 | BUG_ON(init && (cmd.flags & CMD_ASYNC)); | |
2394 | ||
83007196 | 2395 | if (il_is_lq_table_valid(il, lq)) |
0cdc2136 SG |
2396 | ret = il_send_cmd(il, &cmd); |
2397 | else | |
2398 | ret = -EINVAL; | |
2399 | ||
2400 | if (cmd.flags & CMD_ASYNC) | |
2401 | return ret; | |
2402 | ||
2403 | if (init) { | |
2404 | D_INFO("init LQ command complete," | |
e7392364 SG |
2405 | " clearing sta addition status for sta %d\n", |
2406 | lq->sta_id); | |
0cdc2136 SG |
2407 | spin_lock_irqsave(&il->sta_lock, flags_spin); |
2408 | il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS; | |
2409 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2410 | } | |
2411 | return ret; | |
2412 | } | |
2413 | EXPORT_SYMBOL(il_send_lq_cmd); | |
2414 | ||
e7392364 SG |
2415 | int |
2416 | il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
2417 | struct ieee80211_sta *sta) | |
0cdc2136 SG |
2418 | { |
2419 | struct il_priv *il = hw->priv; | |
2420 | struct il_station_priv_common *sta_common = (void *)sta->drv_priv; | |
2421 | int ret; | |
2422 | ||
e7392364 | 2423 | D_INFO("received request to remove station %pM\n", sta->addr); |
0cdc2136 | 2424 | mutex_lock(&il->mutex); |
e7392364 | 2425 | D_INFO("proceeding to remove station %pM\n", sta->addr); |
0cdc2136 SG |
2426 | ret = il_remove_station(il, sta_common->sta_id, sta->addr); |
2427 | if (ret) | |
e7392364 | 2428 | IL_ERR("Error removing station %pM\n", sta->addr); |
0cdc2136 SG |
2429 | mutex_unlock(&il->mutex); |
2430 | return ret; | |
2431 | } | |
2432 | EXPORT_SYMBOL(il_mac_sta_remove); | |
2433 | ||
2434 | /************************** RX-FUNCTIONS ****************************/ | |
2435 | /* | |
2436 | * Rx theory of operation | |
2437 | * | |
2438 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
2439 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
2440 | * used not only for Rx frames, but for any command response or notification | |
2441 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
2442 | * of idxes into the circular buffer. | |
2443 | * | |
2444 | * Rx Queue Indexes | |
2445 | * The host/firmware share two idx registers for managing the Rx buffers. | |
2446 | * | |
2447 | * The READ idx maps to the first position that the firmware may be writing | |
2448 | * to -- the driver can read up to (but not including) this position and get | |
2449 | * good data. | |
2450 | * The READ idx is managed by the firmware once the card is enabled. | |
2451 | * | |
2452 | * The WRITE idx maps to the last position the driver has read from -- the | |
2453 | * position preceding WRITE is the last slot the firmware can place a packet. | |
2454 | * | |
2455 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
2456 | * WRITE = READ. | |
2457 | * | |
2458 | * During initialization, the host sets up the READ queue position to the first | |
2459 | * IDX position, and WRITE to the last (READ - 1 wrapped) | |
2460 | * | |
2461 | * When the firmware places a packet in a buffer, it will advance the READ idx | |
2462 | * and fire the RX interrupt. The driver can then query the READ idx and | |
2463 | * process as many packets as possible, moving the WRITE idx forward as it | |
2464 | * resets the Rx queue buffers with new memory. | |
2465 | * | |
2466 | * The management in the driver is as follows: | |
2467 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
2468 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
2469 | * to replenish the iwl->rxq->rx_free. | |
2470 | * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the | |
2471 | * iwl->rxq is replenished and the READ IDX is updated (updating the | |
2472 | * 'processed' and 'read' driver idxes as well) | |
2473 | * + A received packet is processed and handed to the kernel network stack, | |
2474 | * detached from the iwl->rxq. The driver 'processed' idx is updated. | |
2475 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
2476 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
2477 | * IDX is not incremented and iwl->status(RX_STALLED) is set. If there | |
2478 | * were enough free buffers and RX_STALLED is set it is cleared. | |
2479 | * | |
2480 | * | |
2481 | * Driver sequence: | |
2482 | * | |
2483 | * il_rx_queue_alloc() Allocates rx_free | |
2484 | * il_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
2485 | * il_rx_queue_restock | |
2486 | * il_rx_queue_restock() Moves available buffers from rx_free into Rx | |
2487 | * queue, updates firmware pointers, and updates | |
2488 | * the WRITE idx. If insufficient rx_free buffers | |
2489 | * are available, schedules il_rx_replenish | |
2490 | * | |
2491 | * -- enable interrupts -- | |
2492 | * ISR - il_rx() Detach il_rx_bufs from pool up to the | |
2493 | * READ IDX, detaching the SKB from the pool. | |
2494 | * Moves the packet buffer from queue to rx_used. | |
2495 | * Calls il_rx_queue_restock to refill any empty | |
2496 | * slots. | |
2497 | * ... | |
2498 | * | |
2499 | */ | |
2500 | ||
2501 | /** | |
2502 | * il_rx_queue_space - Return number of free slots available in queue. | |
2503 | */ | |
e7392364 SG |
2504 | int |
2505 | il_rx_queue_space(const struct il_rx_queue *q) | |
0cdc2136 SG |
2506 | { |
2507 | int s = q->read - q->write; | |
2508 | if (s <= 0) | |
2509 | s += RX_QUEUE_SIZE; | |
2510 | /* keep some buffer to not confuse full and empty queue */ | |
2511 | s -= 2; | |
2512 | if (s < 0) | |
2513 | s = 0; | |
2514 | return s; | |
2515 | } | |
2516 | EXPORT_SYMBOL(il_rx_queue_space); | |
2517 | ||
2518 | /** | |
2519 | * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
2520 | */ | |
2521 | void | |
e7392364 | 2522 | il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q) |
0cdc2136 SG |
2523 | { |
2524 | unsigned long flags; | |
2525 | u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg; | |
2526 | u32 reg; | |
2527 | ||
2528 | spin_lock_irqsave(&q->lock, flags); | |
2529 | ||
2530 | if (q->need_update == 0) | |
2531 | goto exit_unlock; | |
2532 | ||
2533 | /* If power-saving is in use, make sure device is awake */ | |
2534 | if (test_bit(S_POWER_PMI, &il->status)) { | |
2535 | reg = _il_rd(il, CSR_UCODE_DRV_GP1); | |
2536 | ||
2537 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
e7392364 SG |
2538 | D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n", |
2539 | reg); | |
0cdc2136 | 2540 | il_set_bit(il, CSR_GP_CNTRL, |
e7392364 | 2541 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
0cdc2136 SG |
2542 | goto exit_unlock; |
2543 | } | |
2544 | ||
2545 | q->write_actual = (q->write & ~0x7); | |
e7392364 | 2546 | il_wr(il, rx_wrt_ptr_reg, q->write_actual); |
0cdc2136 | 2547 | |
e7392364 | 2548 | /* Else device is assumed to be awake */ |
0cdc2136 SG |
2549 | } else { |
2550 | /* Device expects a multiple of 8 */ | |
2551 | q->write_actual = (q->write & ~0x7); | |
e7392364 | 2552 | il_wr(il, rx_wrt_ptr_reg, q->write_actual); |
0cdc2136 SG |
2553 | } |
2554 | ||
2555 | q->need_update = 0; | |
2556 | ||
e7392364 | 2557 | exit_unlock: |
0cdc2136 SG |
2558 | spin_unlock_irqrestore(&q->lock, flags); |
2559 | } | |
2560 | EXPORT_SYMBOL(il_rx_queue_update_write_ptr); | |
2561 | ||
e7392364 SG |
2562 | int |
2563 | il_rx_queue_alloc(struct il_priv *il) | |
0cdc2136 SG |
2564 | { |
2565 | struct il_rx_queue *rxq = &il->rxq; | |
2566 | struct device *dev = &il->pci_dev->dev; | |
2567 | int i; | |
2568 | ||
2569 | spin_lock_init(&rxq->lock); | |
2570 | INIT_LIST_HEAD(&rxq->rx_free); | |
2571 | INIT_LIST_HEAD(&rxq->rx_used); | |
2572 | ||
2573 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
e7392364 SG |
2574 | rxq->bd = |
2575 | dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma, | |
2576 | GFP_KERNEL); | |
0cdc2136 SG |
2577 | if (!rxq->bd) |
2578 | goto err_bd; | |
2579 | ||
e7392364 SG |
2580 | rxq->rb_stts = |
2581 | dma_alloc_coherent(dev, sizeof(struct il_rb_status), | |
2582 | &rxq->rb_stts_dma, GFP_KERNEL); | |
0cdc2136 SG |
2583 | if (!rxq->rb_stts) |
2584 | goto err_rb; | |
2585 | ||
2586 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
2587 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
2588 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
2589 | ||
2590 | /* Set us so that we have processed and used all buffers, but have | |
2591 | * not restocked the Rx queue with fresh buffers */ | |
2592 | rxq->read = rxq->write = 0; | |
2593 | rxq->write_actual = 0; | |
2594 | rxq->free_count = 0; | |
2595 | rxq->need_update = 0; | |
2596 | return 0; | |
2597 | ||
2598 | err_rb: | |
2599 | dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
2600 | rxq->bd_dma); | |
2601 | err_bd: | |
2602 | return -ENOMEM; | |
2603 | } | |
e7392364 | 2604 | EXPORT_SYMBOL(il_rx_queue_alloc); |
0cdc2136 | 2605 | |
e7392364 SG |
2606 | void |
2607 | il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
2608 | { |
2609 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
2610 | struct il_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
2611 | ||
2612 | if (!report->state) { | |
e7392364 | 2613 | D_11H("Spectrum Measure Notification: Start\n"); |
0cdc2136 SG |
2614 | return; |
2615 | } | |
2616 | ||
2617 | memcpy(&il->measure_report, report, sizeof(*report)); | |
2618 | il->measurement_status |= MEASUREMENT_READY; | |
2619 | } | |
2620 | EXPORT_SYMBOL(il_hdl_spectrum_measurement); | |
2621 | ||
2622 | /* | |
2623 | * returns non-zero if packet should be dropped | |
2624 | */ | |
e7392364 SG |
2625 | int |
2626 | il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr, | |
2627 | u32 decrypt_res, struct ieee80211_rx_status *stats) | |
0cdc2136 SG |
2628 | { |
2629 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2630 | ||
2631 | /* | |
2632 | * All contexts have the same setting here due to it being | |
2633 | * a module parameter, so OK to check any context. | |
2634 | */ | |
c8b03958 | 2635 | if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) |
0cdc2136 SG |
2636 | return 0; |
2637 | ||
2638 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2639 | return 0; | |
2640 | ||
2641 | D_RX("decrypt_res:0x%x\n", decrypt_res); | |
2642 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2643 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
2644 | /* The uCode has got a bad phase 1 Key, pushes the packet. | |
2645 | * Decryption will be done in SW. */ | |
2646 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2647 | RX_RES_STATUS_BAD_KEY_TTAK) | |
2648 | break; | |
2649 | ||
2650 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2651 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2652 | RX_RES_STATUS_BAD_ICV_MIC) { | |
2653 | /* bad ICV, the packet is destroyed since the | |
2654 | * decryption is inplace, drop it */ | |
2655 | D_RX("Packet destroyed\n"); | |
2656 | return -1; | |
2657 | } | |
2658 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2659 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2660 | RX_RES_STATUS_DECRYPT_OK) { | |
2661 | D_RX("hw decrypt successfully!!!\n"); | |
2662 | stats->flag |= RX_FLAG_DECRYPTED; | |
2663 | } | |
2664 | break; | |
2665 | ||
2666 | default: | |
2667 | break; | |
2668 | } | |
2669 | return 0; | |
2670 | } | |
2671 | EXPORT_SYMBOL(il_set_decrypted_flag); | |
2672 | ||
2673 | /** | |
2674 | * il_txq_update_write_ptr - Send new write idx to hardware | |
2675 | */ | |
2676 | void | |
2677 | il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq) | |
2678 | { | |
2679 | u32 reg = 0; | |
2680 | int txq_id = txq->q.id; | |
2681 | ||
2682 | if (txq->need_update == 0) | |
2683 | return; | |
2684 | ||
2685 | /* if we're trying to save power */ | |
2686 | if (test_bit(S_POWER_PMI, &il->status)) { | |
2687 | /* wake up nic if it's powered down ... | |
2688 | * uCode will wake up, and interrupt us again, so next | |
2689 | * time we'll skip this part. */ | |
2690 | reg = _il_rd(il, CSR_UCODE_DRV_GP1); | |
2691 | ||
2692 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
e7392364 SG |
2693 | D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n", |
2694 | txq_id, reg); | |
0cdc2136 | 2695 | il_set_bit(il, CSR_GP_CNTRL, |
e7392364 | 2696 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
0cdc2136 SG |
2697 | return; |
2698 | } | |
2699 | ||
e7392364 | 2700 | il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); |
0cdc2136 SG |
2701 | |
2702 | /* | |
2703 | * else not in power-save mode, | |
2704 | * uCode will never sleep when we're | |
2705 | * trying to tx (during RFKILL, we're not trying to tx). | |
2706 | */ | |
2707 | } else | |
e7392364 | 2708 | _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); |
0cdc2136 SG |
2709 | txq->need_update = 0; |
2710 | } | |
2711 | EXPORT_SYMBOL(il_txq_update_write_ptr); | |
2712 | ||
2713 | /** | |
2714 | * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
2715 | */ | |
e7392364 SG |
2716 | void |
2717 | il_tx_queue_unmap(struct il_priv *il, int txq_id) | |
0cdc2136 SG |
2718 | { |
2719 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
2720 | struct il_queue *q = &txq->q; | |
2721 | ||
2722 | if (q->n_bd == 0) | |
2723 | return; | |
2724 | ||
2725 | while (q->write_ptr != q->read_ptr) { | |
c39ae9fd | 2726 | il->ops->lib->txq_free_tfd(il, txq); |
0cdc2136 SG |
2727 | q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd); |
2728 | } | |
2729 | } | |
2730 | EXPORT_SYMBOL(il_tx_queue_unmap); | |
2731 | ||
2732 | /** | |
2733 | * il_tx_queue_free - Deallocate DMA queue. | |
2734 | * @txq: Transmit queue to deallocate. | |
2735 | * | |
2736 | * Empty queue by removing and destroying all BD's. | |
2737 | * Free all buffers. | |
2738 | * 0-fill, but do not free "txq" descriptor structure. | |
2739 | */ | |
e7392364 SG |
2740 | void |
2741 | il_tx_queue_free(struct il_priv *il, int txq_id) | |
0cdc2136 SG |
2742 | { |
2743 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
2744 | struct device *dev = &il->pci_dev->dev; | |
2745 | int i; | |
2746 | ||
2747 | il_tx_queue_unmap(il, txq_id); | |
2748 | ||
2749 | /* De-alloc array of command/tx buffers */ | |
2750 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) | |
2751 | kfree(txq->cmd[i]); | |
2752 | ||
2753 | /* De-alloc circular buffer of TFDs */ | |
2754 | if (txq->q.n_bd) | |
e7392364 SG |
2755 | dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd, |
2756 | txq->tfds, txq->q.dma_addr); | |
0cdc2136 SG |
2757 | |
2758 | /* De-alloc array of per-TFD driver data */ | |
00ea99e1 SG |
2759 | kfree(txq->skbs); |
2760 | txq->skbs = NULL; | |
0cdc2136 SG |
2761 | |
2762 | /* deallocate arrays */ | |
2763 | kfree(txq->cmd); | |
2764 | kfree(txq->meta); | |
2765 | txq->cmd = NULL; | |
2766 | txq->meta = NULL; | |
2767 | ||
2768 | /* 0-fill queue descriptor structure */ | |
2769 | memset(txq, 0, sizeof(*txq)); | |
2770 | } | |
2771 | EXPORT_SYMBOL(il_tx_queue_free); | |
2772 | ||
2773 | /** | |
2774 | * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue | |
2775 | */ | |
e7392364 SG |
2776 | void |
2777 | il_cmd_queue_unmap(struct il_priv *il) | |
0cdc2136 SG |
2778 | { |
2779 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
2780 | struct il_queue *q = &txq->q; | |
2781 | int i; | |
2782 | ||
2783 | if (q->n_bd == 0) | |
2784 | return; | |
2785 | ||
2786 | while (q->read_ptr != q->write_ptr) { | |
2787 | i = il_get_cmd_idx(q, q->read_ptr, 0); | |
2788 | ||
2789 | if (txq->meta[i].flags & CMD_MAPPED) { | |
2790 | pci_unmap_single(il->pci_dev, | |
2791 | dma_unmap_addr(&txq->meta[i], mapping), | |
2792 | dma_unmap_len(&txq->meta[i], len), | |
2793 | PCI_DMA_BIDIRECTIONAL); | |
2794 | txq->meta[i].flags = 0; | |
2795 | } | |
2796 | ||
2797 | q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd); | |
2798 | } | |
2799 | ||
2800 | i = q->n_win; | |
2801 | if (txq->meta[i].flags & CMD_MAPPED) { | |
2802 | pci_unmap_single(il->pci_dev, | |
2803 | dma_unmap_addr(&txq->meta[i], mapping), | |
2804 | dma_unmap_len(&txq->meta[i], len), | |
2805 | PCI_DMA_BIDIRECTIONAL); | |
2806 | txq->meta[i].flags = 0; | |
2807 | } | |
2808 | } | |
2809 | EXPORT_SYMBOL(il_cmd_queue_unmap); | |
2810 | ||
2811 | /** | |
2812 | * il_cmd_queue_free - Deallocate DMA queue. | |
2813 | * @txq: Transmit queue to deallocate. | |
2814 | * | |
2815 | * Empty queue by removing and destroying all BD's. | |
2816 | * Free all buffers. | |
2817 | * 0-fill, but do not free "txq" descriptor structure. | |
2818 | */ | |
e7392364 SG |
2819 | void |
2820 | il_cmd_queue_free(struct il_priv *il) | |
0cdc2136 SG |
2821 | { |
2822 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
2823 | struct device *dev = &il->pci_dev->dev; | |
2824 | int i; | |
2825 | ||
2826 | il_cmd_queue_unmap(il); | |
2827 | ||
2828 | /* De-alloc array of command/tx buffers */ | |
2829 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
2830 | kfree(txq->cmd[i]); | |
2831 | ||
2832 | /* De-alloc circular buffer of TFDs */ | |
2833 | if (txq->q.n_bd) | |
2834 | dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd, | |
2835 | txq->tfds, txq->q.dma_addr); | |
2836 | ||
2837 | /* deallocate arrays */ | |
2838 | kfree(txq->cmd); | |
2839 | kfree(txq->meta); | |
2840 | txq->cmd = NULL; | |
2841 | txq->meta = NULL; | |
2842 | ||
2843 | /* 0-fill queue descriptor structure */ | |
2844 | memset(txq, 0, sizeof(*txq)); | |
2845 | } | |
2846 | EXPORT_SYMBOL(il_cmd_queue_free); | |
2847 | ||
2848 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** | |
2849 | * DMA services | |
2850 | * | |
2851 | * Theory of operation | |
2852 | * | |
2853 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
2854 | * of buffer descriptors, each of which points to one or more data buffers for | |
2855 | * the device to read from or fill. Driver and device exchange status of each | |
2856 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
2857 | * entries in each circular buffer, to protect against confusing empty and full | |
2858 | * queue states. | |
2859 | * | |
2860 | * The device reads or writes the data in the queues via the device's several | |
2861 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
2862 | * | |
2863 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
2864 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
2865 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
2866 | * Tx queue resumed. | |
2867 | * | |
2868 | * See more detailed info in 4965.h. | |
2869 | ***************************************************/ | |
2870 | ||
e7392364 SG |
2871 | int |
2872 | il_queue_space(const struct il_queue *q) | |
0cdc2136 SG |
2873 | { |
2874 | int s = q->read_ptr - q->write_ptr; | |
2875 | ||
2876 | if (q->read_ptr > q->write_ptr) | |
2877 | s -= q->n_bd; | |
2878 | ||
2879 | if (s <= 0) | |
2880 | s += q->n_win; | |
2881 | /* keep some reserve to not confuse empty and full situations */ | |
2882 | s -= 2; | |
2883 | if (s < 0) | |
2884 | s = 0; | |
2885 | return s; | |
2886 | } | |
2887 | EXPORT_SYMBOL(il_queue_space); | |
2888 | ||
2889 | ||
2890 | /** | |
2891 | * il_queue_init - Initialize queue's high/low-water and read/write idxes | |
2892 | */ | |
e7392364 SG |
2893 | static int |
2894 | il_queue_init(struct il_priv *il, struct il_queue *q, int count, int slots_num, | |
2895 | u32 id) | |
0cdc2136 SG |
2896 | { |
2897 | q->n_bd = count; | |
2898 | q->n_win = slots_num; | |
2899 | q->id = id; | |
2900 | ||
2901 | /* count must be power-of-two size, otherwise il_queue_inc_wrap | |
2902 | * and il_queue_dec_wrap are broken. */ | |
2903 | BUG_ON(!is_power_of_2(count)); | |
2904 | ||
2905 | /* slots_num must be power-of-two size, otherwise | |
2906 | * il_get_cmd_idx is broken. */ | |
2907 | BUG_ON(!is_power_of_2(slots_num)); | |
2908 | ||
2909 | q->low_mark = q->n_win / 4; | |
2910 | if (q->low_mark < 4) | |
2911 | q->low_mark = 4; | |
2912 | ||
2913 | q->high_mark = q->n_win / 8; | |
2914 | if (q->high_mark < 2) | |
2915 | q->high_mark = 2; | |
2916 | ||
2917 | q->write_ptr = q->read_ptr = 0; | |
2918 | ||
2919 | return 0; | |
2920 | } | |
2921 | ||
2922 | /** | |
2923 | * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
2924 | */ | |
e7392364 SG |
2925 | static int |
2926 | il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id) | |
0cdc2136 SG |
2927 | { |
2928 | struct device *dev = &il->pci_dev->dev; | |
2929 | size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; | |
2930 | ||
2931 | /* Driver ilate data, only for Tx (not command) queues, | |
2932 | * not shared with device. */ | |
2933 | if (id != il->cmd_queue) { | |
00ea99e1 SG |
2934 | txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(struct skb *), |
2935 | GFP_KERNEL); | |
2936 | if (!txq->skbs) { | |
2937 | IL_ERR("Fail to alloc skbs\n"); | |
0cdc2136 SG |
2938 | goto error; |
2939 | } | |
00ea99e1 SG |
2940 | } else |
2941 | txq->skbs = NULL; | |
0cdc2136 SG |
2942 | |
2943 | /* Circular buffer of transmit frame descriptors (TFDs), | |
2944 | * shared with device */ | |
e7392364 SG |
2945 | txq->tfds = |
2946 | dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL); | |
0cdc2136 | 2947 | if (!txq->tfds) { |
00ea99e1 | 2948 | IL_ERR("Fail to alloc TFDs\n"); |
0cdc2136 SG |
2949 | goto error; |
2950 | } | |
2951 | txq->q.id = id; | |
2952 | ||
2953 | return 0; | |
2954 | ||
e7392364 | 2955 | error: |
00ea99e1 SG |
2956 | kfree(txq->skbs); |
2957 | txq->skbs = NULL; | |
0cdc2136 SG |
2958 | |
2959 | return -ENOMEM; | |
2960 | } | |
2961 | ||
2962 | /** | |
2963 | * il_tx_queue_init - Allocate and initialize one tx/cmd queue | |
2964 | */ | |
e7392364 SG |
2965 | int |
2966 | il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num, | |
2967 | u32 txq_id) | |
0cdc2136 SG |
2968 | { |
2969 | int i, len; | |
2970 | int ret; | |
2971 | int actual_slots = slots_num; | |
2972 | ||
2973 | /* | |
2974 | * Alloc buffer array for commands (Tx or other types of commands). | |
2975 | * For the command queue (#4/#9), allocate command space + one big | |
2976 | * command for scan, since scan command is very huge; the system will | |
2977 | * not have two scans at the same time, so only one is needed. | |
2978 | * For normal Tx queues (all other queues), no super-size command | |
2979 | * space is needed. | |
2980 | */ | |
2981 | if (txq_id == il->cmd_queue) | |
2982 | actual_slots++; | |
2983 | ||
e7392364 SG |
2984 | txq->meta = |
2985 | kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL); | |
2986 | txq->cmd = | |
2987 | kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL); | |
0cdc2136 SG |
2988 | |
2989 | if (!txq->meta || !txq->cmd) | |
2990 | goto out_free_arrays; | |
2991 | ||
2992 | len = sizeof(struct il_device_cmd); | |
2993 | for (i = 0; i < actual_slots; i++) { | |
2994 | /* only happens for cmd queue */ | |
2995 | if (i == slots_num) | |
2996 | len = IL_MAX_CMD_SIZE; | |
2997 | ||
2998 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); | |
2999 | if (!txq->cmd[i]) | |
3000 | goto err; | |
3001 | } | |
3002 | ||
3003 | /* Alloc driver data array and TFD circular buffer */ | |
3004 | ret = il_tx_queue_alloc(il, txq, txq_id); | |
3005 | if (ret) | |
3006 | goto err; | |
3007 | ||
3008 | txq->need_update = 0; | |
3009 | ||
3010 | /* | |
3011 | * For the default queues 0-3, set up the swq_id | |
3012 | * already -- all others need to get one later | |
3013 | * (if they need one at all). | |
3014 | */ | |
3015 | if (txq_id < 4) | |
3016 | il_set_swq_id(txq, txq_id, txq_id); | |
3017 | ||
3018 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
3019 | * il_queue_inc_wrap and il_queue_dec_wrap are broken. */ | |
3020 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
3021 | ||
3022 | /* Initialize queue's high/low-water marks, and head/tail idxes */ | |
e7392364 | 3023 | il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
0cdc2136 SG |
3024 | |
3025 | /* Tell device where to find queue */ | |
c39ae9fd | 3026 | il->ops->lib->txq_init(il, txq); |
0cdc2136 SG |
3027 | |
3028 | return 0; | |
3029 | err: | |
3030 | for (i = 0; i < actual_slots; i++) | |
3031 | kfree(txq->cmd[i]); | |
3032 | out_free_arrays: | |
3033 | kfree(txq->meta); | |
3034 | kfree(txq->cmd); | |
3035 | ||
3036 | return -ENOMEM; | |
3037 | } | |
3038 | EXPORT_SYMBOL(il_tx_queue_init); | |
3039 | ||
e7392364 SG |
3040 | void |
3041 | il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq, int slots_num, | |
3042 | u32 txq_id) | |
0cdc2136 SG |
3043 | { |
3044 | int actual_slots = slots_num; | |
3045 | ||
3046 | if (txq_id == il->cmd_queue) | |
3047 | actual_slots++; | |
3048 | ||
3049 | memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots); | |
3050 | ||
3051 | txq->need_update = 0; | |
3052 | ||
3053 | /* Initialize queue's high/low-water marks, and head/tail idxes */ | |
e7392364 | 3054 | il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
0cdc2136 SG |
3055 | |
3056 | /* Tell device where to find queue */ | |
c39ae9fd | 3057 | il->ops->lib->txq_init(il, txq); |
0cdc2136 SG |
3058 | } |
3059 | EXPORT_SYMBOL(il_tx_queue_reset); | |
3060 | ||
3061 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
3062 | ||
3063 | /** | |
3064 | * il_enqueue_hcmd - enqueue a uCode command | |
3065 | * @il: device ilate data point | |
3066 | * @cmd: a point to the ucode command structure | |
3067 | * | |
3068 | * The function returns < 0 values to indicate the operation is | |
3069 | * failed. On success, it turns the idx (> 0) of command in the | |
3070 | * command queue. | |
3071 | */ | |
e7392364 SG |
3072 | int |
3073 | il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd) | |
0cdc2136 SG |
3074 | { |
3075 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
3076 | struct il_queue *q = &txq->q; | |
3077 | struct il_device_cmd *out_cmd; | |
3078 | struct il_cmd_meta *out_meta; | |
3079 | dma_addr_t phys_addr; | |
3080 | unsigned long flags; | |
3081 | int len; | |
3082 | u32 idx; | |
3083 | u16 fix_size; | |
3084 | ||
c39ae9fd | 3085 | cmd->len = il->ops->utils->get_hcmd_size(cmd->id, cmd->len); |
e7392364 | 3086 | fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr)); |
0cdc2136 SG |
3087 | |
3088 | /* If any of the command structures end up being larger than | |
3089 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
3090 | * we will need to increase the size of the TFD entries | |
3091 | * Also, check to see if command buffer should not exceed the size | |
3092 | * of device_cmd and max_cmd_size. */ | |
3093 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
3094 | !(cmd->flags & CMD_SIZE_HUGE)); | |
3095 | BUG_ON(fix_size > IL_MAX_CMD_SIZE); | |
3096 | ||
3097 | if (il_is_rfkill(il) || il_is_ctkill(il)) { | |
3098 | IL_WARN("Not sending command - %s KILL\n", | |
e7392364 | 3099 | il_is_rfkill(il) ? "RF" : "CT"); |
0cdc2136 SG |
3100 | return -EIO; |
3101 | } | |
3102 | ||
3103 | spin_lock_irqsave(&il->hcmd_lock, flags); | |
3104 | ||
3105 | if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { | |
3106 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3107 | ||
3108 | IL_ERR("Restarting adapter due to command queue full\n"); | |
3109 | queue_work(il->workqueue, &il->restart); | |
3110 | return -ENOSPC; | |
3111 | } | |
3112 | ||
3113 | idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); | |
3114 | out_cmd = txq->cmd[idx]; | |
3115 | out_meta = &txq->meta[idx]; | |
3116 | ||
3117 | if (WARN_ON(out_meta->flags & CMD_MAPPED)) { | |
3118 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3119 | return -ENOSPC; | |
3120 | } | |
3121 | ||
3122 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ | |
3123 | out_meta->flags = cmd->flags | CMD_MAPPED; | |
3124 | if (cmd->flags & CMD_WANT_SKB) | |
3125 | out_meta->source = cmd; | |
3126 | if (cmd->flags & CMD_ASYNC) | |
3127 | out_meta->callback = cmd->callback; | |
3128 | ||
3129 | out_cmd->hdr.cmd = cmd->id; | |
3130 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
3131 | ||
3132 | /* At this point, the out_cmd now has all of the incoming cmd | |
3133 | * information */ | |
3134 | ||
3135 | out_cmd->hdr.flags = 0; | |
e7392364 SG |
3136 | out_cmd->hdr.sequence = |
3137 | cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr)); | |
0cdc2136 SG |
3138 | if (cmd->flags & CMD_SIZE_HUGE) |
3139 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; | |
3140 | len = sizeof(struct il_device_cmd); | |
3141 | if (idx == TFD_CMD_SLOTS) | |
3142 | len = IL_MAX_CMD_SIZE; | |
3143 | ||
3144 | #ifdef CONFIG_IWLEGACY_DEBUG | |
3145 | switch (out_cmd->hdr.cmd) { | |
3146 | case C_TX_LINK_QUALITY_CMD: | |
3147 | case C_SENSITIVITY: | |
e7392364 SG |
3148 | D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, " |
3149 | "%d bytes at %d[%d]:%d\n", | |
3150 | il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd, | |
3151 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
3152 | q->write_ptr, idx, il->cmd_queue); | |
0cdc2136 SG |
3153 | break; |
3154 | default: | |
3155 | D_HC("Sending command %s (#%x), seq: 0x%04X, " | |
e7392364 SG |
3156 | "%d bytes at %d[%d]:%d\n", |
3157 | il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd, | |
3158 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr, | |
3159 | idx, il->cmd_queue); | |
0cdc2136 SG |
3160 | } |
3161 | #endif | |
3162 | txq->need_update = 1; | |
3163 | ||
c39ae9fd | 3164 | if (il->ops->lib->txq_update_byte_cnt_tbl) |
0cdc2136 | 3165 | /* Set up entry in queue's byte count circular buffer */ |
c39ae9fd | 3166 | il->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0); |
0cdc2136 | 3167 | |
e7392364 SG |
3168 | phys_addr = |
3169 | pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size, | |
3170 | PCI_DMA_BIDIRECTIONAL); | |
0cdc2136 SG |
3171 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
3172 | dma_unmap_len_set(out_meta, len, fix_size); | |
3173 | ||
c39ae9fd SG |
3174 | il->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1, |
3175 | U32_PAD(cmd->len)); | |
0cdc2136 SG |
3176 | |
3177 | /* Increment and update queue's write idx */ | |
3178 | q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd); | |
3179 | il_txq_update_write_ptr(il, txq); | |
3180 | ||
3181 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3182 | return idx; | |
3183 | } | |
3184 | ||
3185 | /** | |
3186 | * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
3187 | * | |
3188 | * When FW advances 'R' idx, all entries between old and new 'R' idx | |
3189 | * need to be reclaimed. As result, some free space forms. If there is | |
3190 | * enough free space (> low mark), wake the stack that feeds us. | |
3191 | */ | |
e7392364 SG |
3192 | static void |
3193 | il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx) | |
0cdc2136 SG |
3194 | { |
3195 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
3196 | struct il_queue *q = &txq->q; | |
3197 | int nfreed = 0; | |
3198 | ||
3199 | if (idx >= q->n_bd || il_queue_used(q, idx) == 0) { | |
3200 | IL_ERR("Read idx for DMA queue txq id (%d), idx %d, " | |
e7392364 SG |
3201 | "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd, |
3202 | q->write_ptr, q->read_ptr); | |
0cdc2136 SG |
3203 | return; |
3204 | } | |
3205 | ||
3206 | for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; | |
3207 | q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
3208 | ||
3209 | if (nfreed++ > 0) { | |
3210 | IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx, | |
e7392364 | 3211 | q->write_ptr, q->read_ptr); |
0cdc2136 SG |
3212 | queue_work(il->workqueue, &il->restart); |
3213 | } | |
3214 | ||
3215 | } | |
3216 | } | |
3217 | ||
3218 | /** | |
3219 | * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
3220 | * @rxb: Rx buffer to reclaim | |
3221 | * | |
3222 | * If an Rx buffer has an async callback associated with it the callback | |
3223 | * will be executed. The attached skb (if present) will only be freed | |
3224 | * if the callback returns 1 | |
3225 | */ | |
3226 | void | |
3227 | il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb) | |
3228 | { | |
3229 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
3230 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
3231 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3232 | int idx = SEQ_TO_IDX(sequence); | |
3233 | int cmd_idx; | |
3234 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); | |
3235 | struct il_device_cmd *cmd; | |
3236 | struct il_cmd_meta *meta; | |
3237 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
3238 | unsigned long flags; | |
3239 | ||
3240 | /* If a Tx command is being handled and it isn't in the actual | |
3241 | * command queue then there a command routing bug has been introduced | |
3242 | * in the queue management code. */ | |
e7392364 SG |
3243 | if (WARN |
3244 | (txq_id != il->cmd_queue, | |
3245 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
3246 | txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr, | |
3247 | il->txq[il->cmd_queue].q.write_ptr)) { | |
0cdc2136 SG |
3248 | il_print_hex_error(il, pkt, 32); |
3249 | return; | |
3250 | } | |
3251 | ||
3252 | cmd_idx = il_get_cmd_idx(&txq->q, idx, huge); | |
3253 | cmd = txq->cmd[cmd_idx]; | |
3254 | meta = &txq->meta[cmd_idx]; | |
3255 | ||
3256 | txq->time_stamp = jiffies; | |
3257 | ||
e7392364 SG |
3258 | pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping), |
3259 | dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL); | |
0cdc2136 SG |
3260 | |
3261 | /* Input error checking is done when commands are added to queue. */ | |
3262 | if (meta->flags & CMD_WANT_SKB) { | |
3263 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); | |
3264 | rxb->page = NULL; | |
3265 | } else if (meta->callback) | |
3266 | meta->callback(il, cmd, pkt); | |
3267 | ||
3268 | spin_lock_irqsave(&il->hcmd_lock, flags); | |
3269 | ||
3270 | il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx); | |
3271 | ||
3272 | if (!(meta->flags & CMD_ASYNC)) { | |
3273 | clear_bit(S_HCMD_ACTIVE, &il->status); | |
3274 | D_INFO("Clearing HCMD_ACTIVE for command %s\n", | |
e7392364 | 3275 | il_get_cmd_string(cmd->hdr.cmd)); |
0cdc2136 SG |
3276 | wake_up(&il->wait_command_queue); |
3277 | } | |
3278 | ||
3279 | /* Mark as unmapped */ | |
3280 | meta->flags = 0; | |
3281 | ||
3282 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3283 | } | |
3284 | EXPORT_SYMBOL(il_tx_cmd_complete); | |
be663ab6 WYG |
3285 | |
3286 | MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965"); | |
3287 | MODULE_VERSION(IWLWIFI_VERSION); | |
3288 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); | |
3289 | MODULE_LICENSE("GPL"); | |
3290 | ||
3291 | /* | |
3292 | * set bt_coex_active to true, uCode will do kill/defer | |
3293 | * every time the priority line is asserted (BT is sending signals on the | |
3294 | * priority line in the PCIx). | |
3295 | * set bt_coex_active to false, uCode will ignore the BT activity and | |
3296 | * perform the normal operation | |
3297 | * | |
3298 | * User might experience transmit issue on some platform due to WiFi/BT | |
3299 | * co-exist problem. The possible behaviors are: | |
3300 | * Able to scan and finding all the available AP | |
3301 | * Not able to associate with any AP | |
3302 | * On those platforms, WiFi communication can be restored by set | |
3303 | * "bt_coex_active" module parameter to "false" | |
3304 | * | |
3305 | * default: bt_coex_active = true (BT_COEX_ENABLE) | |
3306 | */ | |
ef33417d | 3307 | static bool bt_coex_active = true; |
be663ab6 WYG |
3308 | module_param(bt_coex_active, bool, S_IRUGO); |
3309 | MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist"); | |
3310 | ||
d2ddf621 SG |
3311 | u32 il_debug_level; |
3312 | EXPORT_SYMBOL(il_debug_level); | |
be663ab6 | 3313 | |
d2ddf621 | 3314 | const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
e7392364 | 3315 | EXPORT_SYMBOL(il_bcast_addr); |
be663ab6 | 3316 | |
e7392364 SG |
3317 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
3318 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
3319 | static void | |
3320 | il_init_ht_hw_capab(const struct il_priv *il, | |
3321 | struct ieee80211_sta_ht_cap *ht_info, | |
3322 | enum ieee80211_band band) | |
be663ab6 WYG |
3323 | { |
3324 | u16 max_bit_rate = 0; | |
46bc8d4b SG |
3325 | u8 rx_chains_num = il->hw_params.rx_chains_num; |
3326 | u8 tx_chains_num = il->hw_params.tx_chains_num; | |
be663ab6 WYG |
3327 | |
3328 | ht_info->cap = 0; | |
3329 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
3330 | ||
3331 | ht_info->ht_supported = true; | |
3332 | ||
3333 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
3334 | max_bit_rate = MAX_BIT_RATE_20_MHZ; | |
46bc8d4b | 3335 | if (il->hw_params.ht40_channel & BIT(band)) { |
be663ab6 WYG |
3336 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
3337 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
3338 | ht_info->mcs.rx_mask[4] = 0x01; | |
3339 | max_bit_rate = MAX_BIT_RATE_40_MHZ; | |
3340 | } | |
3341 | ||
46bc8d4b | 3342 | if (il->cfg->mod_params->amsdu_size_8K) |
be663ab6 WYG |
3343 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
3344 | ||
3345 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
3346 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
3347 | ||
3348 | ht_info->mcs.rx_mask[0] = 0xFF; | |
3349 | if (rx_chains_num >= 2) | |
3350 | ht_info->mcs.rx_mask[1] = 0xFF; | |
3351 | if (rx_chains_num >= 3) | |
3352 | ht_info->mcs.rx_mask[2] = 0xFF; | |
3353 | ||
3354 | /* Highest supported Rx data rate */ | |
3355 | max_bit_rate *= rx_chains_num; | |
3356 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); | |
3357 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
3358 | ||
3359 | /* Tx MCS capabilities */ | |
3360 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
3361 | if (tx_chains_num != rx_chains_num) { | |
3362 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
e7392364 SG |
3363 | ht_info->mcs.tx_params |= |
3364 | ((tx_chains_num - | |
3365 | 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
be663ab6 WYG |
3366 | } |
3367 | } | |
3368 | ||
3369 | /** | |
e2ebc833 | 3370 | * il_init_geos - Initialize mac80211's geo/channel info based from eeprom |
be663ab6 | 3371 | */ |
e7392364 SG |
3372 | int |
3373 | il_init_geos(struct il_priv *il) | |
be663ab6 | 3374 | { |
e2ebc833 | 3375 | struct il_channel_info *ch; |
be663ab6 WYG |
3376 | struct ieee80211_supported_band *sband; |
3377 | struct ieee80211_channel *channels; | |
3378 | struct ieee80211_channel *geo_ch; | |
3379 | struct ieee80211_rate *rates; | |
3380 | int i = 0; | |
332704a5 | 3381 | s8 max_tx_power = 0; |
be663ab6 | 3382 | |
46bc8d4b SG |
3383 | if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
3384 | il->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
58de00a4 | 3385 | D_INFO("Geography modes already initialized.\n"); |
a6766ccd | 3386 | set_bit(S_GEO_CONFIGURED, &il->status); |
be663ab6 WYG |
3387 | return 0; |
3388 | } | |
3389 | ||
e7392364 SG |
3390 | channels = |
3391 | kzalloc(sizeof(struct ieee80211_channel) * il->channel_count, | |
3392 | GFP_KERNEL); | |
be663ab6 WYG |
3393 | if (!channels) |
3394 | return -ENOMEM; | |
3395 | ||
e7392364 SG |
3396 | rates = |
3397 | kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY), | |
3398 | GFP_KERNEL); | |
be663ab6 WYG |
3399 | if (!rates) { |
3400 | kfree(channels); | |
3401 | return -ENOMEM; | |
3402 | } | |
3403 | ||
3404 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
46bc8d4b | 3405 | sband = &il->bands[IEEE80211_BAND_5GHZ]; |
d2ddf621 | 3406 | sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)]; |
be663ab6 | 3407 | /* just OFDM */ |
e2ebc833 | 3408 | sband->bitrates = &rates[IL_FIRST_OFDM_RATE]; |
2eb05816 | 3409 | sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE; |
be663ab6 | 3410 | |
46bc8d4b | 3411 | if (il->cfg->sku & IL_SKU_N) |
e7392364 | 3412 | il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ); |
be663ab6 | 3413 | |
46bc8d4b | 3414 | sband = &il->bands[IEEE80211_BAND_2GHZ]; |
be663ab6 WYG |
3415 | sband->channels = channels; |
3416 | /* OFDM & CCK */ | |
3417 | sband->bitrates = rates; | |
2eb05816 | 3418 | sband->n_bitrates = RATE_COUNT_LEGACY; |
be663ab6 | 3419 | |
46bc8d4b | 3420 | if (il->cfg->sku & IL_SKU_N) |
e7392364 | 3421 | il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ); |
be663ab6 | 3422 | |
46bc8d4b SG |
3423 | il->ieee_channels = channels; |
3424 | il->ieee_rates = rates; | |
be663ab6 | 3425 | |
e7392364 | 3426 | for (i = 0; i < il->channel_count; i++) { |
46bc8d4b | 3427 | ch = &il->channel_info[i]; |
be663ab6 | 3428 | |
e2ebc833 | 3429 | if (!il_is_channel_valid(ch)) |
be663ab6 WYG |
3430 | continue; |
3431 | ||
46bc8d4b | 3432 | sband = &il->bands[ch->band]; |
be663ab6 WYG |
3433 | |
3434 | geo_ch = &sband->channels[sband->n_channels++]; | |
3435 | ||
3436 | geo_ch->center_freq = | |
e7392364 | 3437 | ieee80211_channel_to_frequency(ch->channel, ch->band); |
be663ab6 WYG |
3438 | geo_ch->max_power = ch->max_power_avg; |
3439 | geo_ch->max_antenna_gain = 0xff; | |
3440 | geo_ch->hw_value = ch->channel; | |
3441 | ||
e2ebc833 | 3442 | if (il_is_channel_valid(ch)) { |
be663ab6 WYG |
3443 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
3444 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
3445 | ||
3446 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
3447 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
3448 | ||
3449 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
3450 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
3451 | ||
3452 | geo_ch->flags |= ch->ht40_extension_channel; | |
3453 | ||
332704a5 SG |
3454 | if (ch->max_power_avg > max_tx_power) |
3455 | max_tx_power = ch->max_power_avg; | |
be663ab6 WYG |
3456 | } else { |
3457 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
3458 | } | |
3459 | ||
e7392364 SG |
3460 | D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel, |
3461 | geo_ch->center_freq, | |
3462 | il_is_channel_a_band(ch) ? "5.2" : "2.4", | |
3463 | geo_ch-> | |
3464 | flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid", | |
3465 | geo_ch->flags); | |
be663ab6 WYG |
3466 | } |
3467 | ||
46bc8d4b SG |
3468 | il->tx_power_device_lmt = max_tx_power; |
3469 | il->tx_power_user_lmt = max_tx_power; | |
3470 | il->tx_power_next = max_tx_power; | |
332704a5 | 3471 | |
232913b5 SG |
3472 | if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 && |
3473 | (il->cfg->sku & IL_SKU_A)) { | |
9406f797 | 3474 | IL_INFO("Incorrectly detected BG card as ABG. " |
be663ab6 | 3475 | "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n", |
e7392364 | 3476 | il->pci_dev->device, il->pci_dev->subsystem_device); |
46bc8d4b | 3477 | il->cfg->sku &= ~IL_SKU_A; |
be663ab6 WYG |
3478 | } |
3479 | ||
9406f797 | 3480 | IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
e7392364 SG |
3481 | il->bands[IEEE80211_BAND_2GHZ].n_channels, |
3482 | il->bands[IEEE80211_BAND_5GHZ].n_channels); | |
be663ab6 | 3483 | |
a6766ccd | 3484 | set_bit(S_GEO_CONFIGURED, &il->status); |
be663ab6 WYG |
3485 | |
3486 | return 0; | |
3487 | } | |
e2ebc833 | 3488 | EXPORT_SYMBOL(il_init_geos); |
be663ab6 WYG |
3489 | |
3490 | /* | |
e2ebc833 | 3491 | * il_free_geos - undo allocations in il_init_geos |
be663ab6 | 3492 | */ |
e7392364 SG |
3493 | void |
3494 | il_free_geos(struct il_priv *il) | |
be663ab6 | 3495 | { |
46bc8d4b SG |
3496 | kfree(il->ieee_channels); |
3497 | kfree(il->ieee_rates); | |
a6766ccd | 3498 | clear_bit(S_GEO_CONFIGURED, &il->status); |
be663ab6 | 3499 | } |
e2ebc833 | 3500 | EXPORT_SYMBOL(il_free_geos); |
be663ab6 | 3501 | |
e7392364 SG |
3502 | static bool |
3503 | il_is_channel_extension(struct il_priv *il, enum ieee80211_band band, | |
3504 | u16 channel, u8 extension_chan_offset) | |
be663ab6 | 3505 | { |
e2ebc833 | 3506 | const struct il_channel_info *ch_info; |
be663ab6 | 3507 | |
46bc8d4b | 3508 | ch_info = il_get_channel_info(il, band, channel); |
e2ebc833 | 3509 | if (!il_is_channel_valid(ch_info)) |
be663ab6 WYG |
3510 | return false; |
3511 | ||
3512 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) | |
e7392364 SG |
3513 | return !(ch_info-> |
3514 | ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS); | |
be663ab6 | 3515 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
e7392364 SG |
3516 | return !(ch_info-> |
3517 | ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS); | |
be663ab6 WYG |
3518 | |
3519 | return false; | |
3520 | } | |
3521 | ||
e7392364 | 3522 | bool |
83007196 | 3523 | il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap) |
be663ab6 | 3524 | { |
1c03c462 | 3525 | if (!il->ht.enabled || !il->ht.is_40mhz) |
be663ab6 WYG |
3526 | return false; |
3527 | ||
3528 | /* | |
3529 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
3530 | * the bit will not set if it is pure 40MHz case | |
3531 | */ | |
3532 | if (ht_cap && !ht_cap->ht_supported) | |
3533 | return false; | |
3534 | ||
d3175167 | 3535 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
46bc8d4b | 3536 | if (il->disable_ht40) |
be663ab6 WYG |
3537 | return false; |
3538 | #endif | |
3539 | ||
46bc8d4b | 3540 | return il_is_channel_extension(il, il->band, |
c8b03958 | 3541 | le16_to_cpu(il->staging.channel), |
1c03c462 | 3542 | il->ht.extension_chan_offset); |
be663ab6 | 3543 | } |
e2ebc833 | 3544 | EXPORT_SYMBOL(il_is_ht40_tx_allowed); |
be663ab6 | 3545 | |
e7392364 SG |
3546 | static u16 |
3547 | il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) | |
be663ab6 WYG |
3548 | { |
3549 | u16 new_val; | |
3550 | u16 beacon_factor; | |
3551 | ||
3552 | /* | |
3553 | * If mac80211 hasn't given us a beacon interval, program | |
3554 | * the default into the device. | |
3555 | */ | |
3556 | if (!beacon_val) | |
3557 | return DEFAULT_BEACON_INTERVAL; | |
3558 | ||
3559 | /* | |
3560 | * If the beacon interval we obtained from the peer | |
3561 | * is too large, we'll have to wake up more often | |
3562 | * (and in IBSS case, we'll beacon too much) | |
3563 | * | |
3564 | * For example, if max_beacon_val is 4096, and the | |
3565 | * requested beacon interval is 7000, we'll have to | |
3566 | * use 3500 to be able to wake up on the beacons. | |
3567 | * | |
3568 | * This could badly influence beacon detection stats. | |
3569 | */ | |
3570 | ||
3571 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
3572 | new_val = beacon_val / beacon_factor; | |
3573 | ||
3574 | if (!new_val) | |
3575 | new_val = max_beacon_val; | |
3576 | ||
3577 | return new_val; | |
3578 | } | |
3579 | ||
3580 | int | |
83007196 | 3581 | il_send_rxon_timing(struct il_priv *il) |
be663ab6 WYG |
3582 | { |
3583 | u64 tsf; | |
3584 | s32 interval_tm, rem; | |
3585 | struct ieee80211_conf *conf = NULL; | |
3586 | u16 beacon_int; | |
83007196 | 3587 | struct ieee80211_vif *vif = il->vif; |
be663ab6 | 3588 | |
6278ddab | 3589 | conf = &il->hw->conf; |
be663ab6 | 3590 | |
46bc8d4b | 3591 | lockdep_assert_held(&il->mutex); |
be663ab6 | 3592 | |
c8b03958 | 3593 | memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd)); |
be663ab6 | 3594 | |
c8b03958 SG |
3595 | il->timing.timestamp = cpu_to_le64(il->timestamp); |
3596 | il->timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
be663ab6 WYG |
3597 | |
3598 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; | |
3599 | ||
3600 | /* | |
6ce1dc45 | 3601 | * TODO: For IBSS we need to get atim_win from mac80211, |
e7392364 | 3602 | * for now just always use 0 |
be663ab6 | 3603 | */ |
c8b03958 | 3604 | il->timing.atim_win = 0; |
be663ab6 | 3605 | |
e7392364 SG |
3606 | beacon_int = |
3607 | il_adjust_beacon_interval(beacon_int, | |
3608 | il->hw_params.max_beacon_itrvl * | |
3609 | TIME_UNIT); | |
c8b03958 | 3610 | il->timing.beacon_interval = cpu_to_le16(beacon_int); |
be663ab6 | 3611 | |
e7392364 | 3612 | tsf = il->timestamp; /* tsf is modifed by do_div: copy it */ |
be663ab6 WYG |
3613 | interval_tm = beacon_int * TIME_UNIT; |
3614 | rem = do_div(tsf, interval_tm); | |
c8b03958 | 3615 | il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
be663ab6 | 3616 | |
c8b03958 | 3617 | il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1; |
be663ab6 | 3618 | |
e7392364 | 3619 | D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n", |
c8b03958 SG |
3620 | le16_to_cpu(il->timing.beacon_interval), |
3621 | le32_to_cpu(il->timing.beacon_init_val), | |
3622 | le16_to_cpu(il->timing.atim_win)); | |
be663ab6 | 3623 | |
63d0f0c5 | 3624 | return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing), |
c8b03958 | 3625 | &il->timing); |
be663ab6 | 3626 | } |
e2ebc833 | 3627 | EXPORT_SYMBOL(il_send_rxon_timing); |
be663ab6 WYG |
3628 | |
3629 | void | |
83007196 | 3630 | il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt) |
be663ab6 | 3631 | { |
c8b03958 | 3632 | struct il_rxon_cmd *rxon = &il->staging; |
be663ab6 WYG |
3633 | |
3634 | if (hw_decrypt) | |
3635 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
3636 | else | |
3637 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
3638 | ||
3639 | } | |
e2ebc833 | 3640 | EXPORT_SYMBOL(il_set_rxon_hwcrypto); |
be663ab6 WYG |
3641 | |
3642 | /* validate RXON structure is valid */ | |
3643 | int | |
83007196 | 3644 | il_check_rxon_cmd(struct il_priv *il) |
be663ab6 | 3645 | { |
c8b03958 | 3646 | struct il_rxon_cmd *rxon = &il->staging; |
be663ab6 WYG |
3647 | bool error = false; |
3648 | ||
3649 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
3650 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { | |
9406f797 | 3651 | IL_WARN("check 2.4G: wrong narrow\n"); |
be663ab6 WYG |
3652 | error = true; |
3653 | } | |
3654 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
9406f797 | 3655 | IL_WARN("check 2.4G: wrong radar\n"); |
be663ab6 WYG |
3656 | error = true; |
3657 | } | |
3658 | } else { | |
3659 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { | |
9406f797 | 3660 | IL_WARN("check 5.2G: not short slot!\n"); |
be663ab6 WYG |
3661 | error = true; |
3662 | } | |
3663 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
9406f797 | 3664 | IL_WARN("check 5.2G: CCK!\n"); |
be663ab6 WYG |
3665 | error = true; |
3666 | } | |
3667 | } | |
3668 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
9406f797 | 3669 | IL_WARN("mac/bssid mcast!\n"); |
be663ab6 WYG |
3670 | error = true; |
3671 | } | |
3672 | ||
3673 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
2eb05816 SG |
3674 | if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 && |
3675 | (rxon->cck_basic_rates & RATE_1M_MASK) == 0) { | |
9406f797 | 3676 | IL_WARN("neither 1 nor 6 are basic\n"); |
be663ab6 WYG |
3677 | error = true; |
3678 | } | |
3679 | ||
3680 | if (le16_to_cpu(rxon->assoc_id) > 2007) { | |
9406f797 | 3681 | IL_WARN("aid > 2007\n"); |
be663ab6 WYG |
3682 | error = true; |
3683 | } | |
3684 | ||
e7392364 SG |
3685 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) == |
3686 | (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
9406f797 | 3687 | IL_WARN("CCK and short slot\n"); |
be663ab6 WYG |
3688 | error = true; |
3689 | } | |
3690 | ||
e7392364 SG |
3691 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) == |
3692 | (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
9406f797 | 3693 | IL_WARN("CCK and auto detect"); |
be663ab6 WYG |
3694 | error = true; |
3695 | } | |
3696 | ||
e7392364 SG |
3697 | if ((rxon-> |
3698 | flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) == | |
3699 | RXON_FLG_TGG_PROTECT_MSK) { | |
9406f797 | 3700 | IL_WARN("TGg but no auto-detect\n"); |
be663ab6 WYG |
3701 | error = true; |
3702 | } | |
3703 | ||
3704 | if (error) | |
e7392364 | 3705 | IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel)); |
be663ab6 WYG |
3706 | |
3707 | if (error) { | |
9406f797 | 3708 | IL_ERR("Invalid RXON\n"); |
be663ab6 WYG |
3709 | return -EINVAL; |
3710 | } | |
3711 | return 0; | |
3712 | } | |
e2ebc833 | 3713 | EXPORT_SYMBOL(il_check_rxon_cmd); |
be663ab6 WYG |
3714 | |
3715 | /** | |
e2ebc833 | 3716 | * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
46bc8d4b | 3717 | * @il: staging_rxon is compared to active_rxon |
be663ab6 WYG |
3718 | * |
3719 | * If the RXON structure is changing enough to require a new tune, | |
3720 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
3721 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
3722 | */ | |
e7392364 | 3723 | int |
83007196 | 3724 | il_full_rxon_required(struct il_priv *il) |
be663ab6 | 3725 | { |
c8b03958 SG |
3726 | const struct il_rxon_cmd *staging = &il->staging; |
3727 | const struct il_rxon_cmd *active = &il->active; | |
be663ab6 WYG |
3728 | |
3729 | #define CHK(cond) \ | |
3730 | if ((cond)) { \ | |
58de00a4 | 3731 | D_INFO("need full RXON - " #cond "\n"); \ |
be663ab6 WYG |
3732 | return 1; \ |
3733 | } | |
3734 | ||
3735 | #define CHK_NEQ(c1, c2) \ | |
3736 | if ((c1) != (c2)) { \ | |
58de00a4 | 3737 | D_INFO("need full RXON - " \ |
be663ab6 WYG |
3738 | #c1 " != " #c2 " - %d != %d\n", \ |
3739 | (c1), (c2)); \ | |
3740 | return 1; \ | |
3741 | } | |
3742 | ||
3743 | /* These items are only settable from the full RXON command */ | |
c8b03958 | 3744 | CHK(!il_is_associated(il)); |
be663ab6 WYG |
3745 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); |
3746 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
e7392364 SG |
3747 | CHK(compare_ether_addr |
3748 | (staging->wlap_bssid_addr, active->wlap_bssid_addr)); | |
be663ab6 WYG |
3749 | CHK_NEQ(staging->dev_type, active->dev_type); |
3750 | CHK_NEQ(staging->channel, active->channel); | |
3751 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
3752 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
3753 | active->ofdm_ht_single_stream_basic_rates); | |
3754 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
3755 | active->ofdm_ht_dual_stream_basic_rates); | |
3756 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
3757 | ||
3758 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
3759 | * be updated with the RXON_ASSOC command -- however only some | |
3760 | * flag transitions are allowed using RXON_ASSOC */ | |
3761 | ||
3762 | /* Check if we are not switching bands */ | |
3763 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, | |
3764 | active->flags & RXON_FLG_BAND_24G_MSK); | |
3765 | ||
3766 | /* Check if we are switching association toggle */ | |
3767 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, | |
3768 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
3769 | ||
3770 | #undef CHK | |
3771 | #undef CHK_NEQ | |
3772 | ||
3773 | return 0; | |
3774 | } | |
e2ebc833 | 3775 | EXPORT_SYMBOL(il_full_rxon_required); |
be663ab6 | 3776 | |
e7392364 | 3777 | u8 |
83007196 | 3778 | il_get_lowest_plcp(struct il_priv *il) |
be663ab6 WYG |
3779 | { |
3780 | /* | |
3781 | * Assign the lowest rate -- should really get this from | |
3782 | * the beacon skb from mac80211. | |
3783 | */ | |
c8b03958 | 3784 | if (il->staging.flags & RXON_FLG_BAND_24G_MSK) |
2eb05816 | 3785 | return RATE_1M_PLCP; |
be663ab6 | 3786 | else |
2eb05816 | 3787 | return RATE_6M_PLCP; |
be663ab6 | 3788 | } |
e2ebc833 | 3789 | EXPORT_SYMBOL(il_get_lowest_plcp); |
be663ab6 | 3790 | |
e7392364 | 3791 | static void |
83007196 | 3792 | _il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf) |
be663ab6 | 3793 | { |
c8b03958 | 3794 | struct il_rxon_cmd *rxon = &il->staging; |
be663ab6 | 3795 | |
1c03c462 | 3796 | if (!il->ht.enabled) { |
e7392364 SG |
3797 | rxon->flags &= |
3798 | ~(RXON_FLG_CHANNEL_MODE_MSK | | |
3799 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK | |
3800 | | RXON_FLG_HT_PROT_MSK); | |
be663ab6 WYG |
3801 | return; |
3802 | } | |
3803 | ||
e7392364 | 3804 | rxon->flags |= |
1c03c462 | 3805 | cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); |
be663ab6 WYG |
3806 | |
3807 | /* Set up channel bandwidth: | |
3808 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ | |
3809 | /* clear the HT channel mode before set the mode */ | |
e7392364 SG |
3810 | rxon->flags &= |
3811 | ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
83007196 | 3812 | if (il_is_ht40_tx_allowed(il, NULL)) { |
be663ab6 | 3813 | /* pure ht40 */ |
1c03c462 | 3814 | if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
be663ab6 WYG |
3815 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
3816 | /* Note: control channel is opposite of extension channel */ | |
1c03c462 | 3817 | switch (il->ht.extension_chan_offset) { |
be663ab6 WYG |
3818 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
3819 | rxon->flags &= | |
e7392364 | 3820 | ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
be663ab6 WYG |
3821 | break; |
3822 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
e7392364 | 3823 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
be663ab6 WYG |
3824 | break; |
3825 | } | |
3826 | } else { | |
3827 | /* Note: control channel is opposite of extension channel */ | |
1c03c462 | 3828 | switch (il->ht.extension_chan_offset) { |
be663ab6 WYG |
3829 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
3830 | rxon->flags &= | |
e7392364 | 3831 | ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); |
be663ab6 WYG |
3832 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; |
3833 | break; | |
3834 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
e7392364 | 3835 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
be663ab6 WYG |
3836 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; |
3837 | break; | |
3838 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
3839 | default: | |
3840 | /* channel location only valid if in Mixed mode */ | |
e7392364 | 3841 | IL_ERR("invalid extension channel offset\n"); |
be663ab6 WYG |
3842 | break; |
3843 | } | |
3844 | } | |
3845 | } else { | |
3846 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
3847 | } | |
3848 | ||
c39ae9fd SG |
3849 | if (il->ops->hcmd->set_rxon_chain) |
3850 | il->ops->hcmd->set_rxon_chain(il); | |
be663ab6 | 3851 | |
58de00a4 | 3852 | D_ASSOC("rxon flags 0x%X operation mode :0x%X " |
e7392364 | 3853 | "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags), |
1c03c462 | 3854 | il->ht.protection, il->ht.extension_chan_offset); |
be663ab6 WYG |
3855 | } |
3856 | ||
e7392364 SG |
3857 | void |
3858 | il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf) | |
be663ab6 | 3859 | { |
83007196 | 3860 | _il_set_rxon_ht(il, ht_conf); |
be663ab6 | 3861 | } |
e2ebc833 | 3862 | EXPORT_SYMBOL(il_set_rxon_ht); |
be663ab6 WYG |
3863 | |
3864 | /* Return valid, unused, channel for a passive scan to reset the RF */ | |
e7392364 SG |
3865 | u8 |
3866 | il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band) | |
be663ab6 | 3867 | { |
e2ebc833 | 3868 | const struct il_channel_info *ch_info; |
be663ab6 WYG |
3869 | int i; |
3870 | u8 channel = 0; | |
3871 | u8 min, max; | |
be663ab6 WYG |
3872 | |
3873 | if (band == IEEE80211_BAND_5GHZ) { | |
3874 | min = 14; | |
46bc8d4b | 3875 | max = il->channel_count; |
be663ab6 WYG |
3876 | } else { |
3877 | min = 0; | |
3878 | max = 14; | |
3879 | } | |
3880 | ||
3881 | for (i = min; i < max; i++) { | |
17d6e557 | 3882 | channel = il->channel_info[i].channel; |
c8b03958 | 3883 | if (channel == le16_to_cpu(il->staging.channel)) |
be663ab6 WYG |
3884 | continue; |
3885 | ||
46bc8d4b | 3886 | ch_info = il_get_channel_info(il, band, channel); |
e2ebc833 | 3887 | if (il_is_channel_valid(ch_info)) |
be663ab6 WYG |
3888 | break; |
3889 | } | |
3890 | ||
3891 | return channel; | |
3892 | } | |
e2ebc833 | 3893 | EXPORT_SYMBOL(il_get_single_channel_number); |
be663ab6 WYG |
3894 | |
3895 | /** | |
e2ebc833 | 3896 | * il_set_rxon_channel - Set the band and channel values in staging RXON |
be663ab6 WYG |
3897 | * @ch: requested channel as a pointer to struct ieee80211_channel |
3898 | ||
3899 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
3900 | * in the staging RXON flag structure based on the ch->band | |
3901 | */ | |
3902 | int | |
83007196 | 3903 | il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch) |
be663ab6 WYG |
3904 | { |
3905 | enum ieee80211_band band = ch->band; | |
3906 | u16 channel = ch->hw_value; | |
3907 | ||
c8b03958 | 3908 | if (le16_to_cpu(il->staging.channel) == channel && il->band == band) |
be663ab6 WYG |
3909 | return 0; |
3910 | ||
c8b03958 | 3911 | il->staging.channel = cpu_to_le16(channel); |
be663ab6 | 3912 | if (band == IEEE80211_BAND_5GHZ) |
c8b03958 | 3913 | il->staging.flags &= ~RXON_FLG_BAND_24G_MSK; |
be663ab6 | 3914 | else |
c8b03958 | 3915 | il->staging.flags |= RXON_FLG_BAND_24G_MSK; |
be663ab6 | 3916 | |
46bc8d4b | 3917 | il->band = band; |
be663ab6 | 3918 | |
58de00a4 | 3919 | D_INFO("Staging channel set to %d [%d]\n", channel, band); |
be663ab6 WYG |
3920 | |
3921 | return 0; | |
3922 | } | |
e2ebc833 | 3923 | EXPORT_SYMBOL(il_set_rxon_channel); |
be663ab6 | 3924 | |
e7392364 | 3925 | void |
83007196 SG |
3926 | il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band, |
3927 | struct ieee80211_vif *vif) | |
be663ab6 WYG |
3928 | { |
3929 | if (band == IEEE80211_BAND_5GHZ) { | |
c8b03958 | 3930 | il->staging.flags &= |
e7392364 SG |
3931 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
3932 | RXON_FLG_CCK_MSK); | |
c8b03958 | 3933 | il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
be663ab6 | 3934 | } else { |
e2ebc833 | 3935 | /* Copied from il_post_associate() */ |
be663ab6 | 3936 | if (vif && vif->bss_conf.use_short_slot) |
c8b03958 | 3937 | il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
be663ab6 | 3938 | else |
c8b03958 | 3939 | il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
be663ab6 | 3940 | |
c8b03958 SG |
3941 | il->staging.flags |= RXON_FLG_BAND_24G_MSK; |
3942 | il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
3943 | il->staging.flags &= ~RXON_FLG_CCK_MSK; | |
be663ab6 WYG |
3944 | } |
3945 | } | |
e2ebc833 | 3946 | EXPORT_SYMBOL(il_set_flags_for_band); |
be663ab6 WYG |
3947 | |
3948 | /* | |
3949 | * initialize rxon structure with default values from eeprom | |
3950 | */ | |
e7392364 | 3951 | void |
83007196 | 3952 | il_connection_init_rx_config(struct il_priv *il) |
be663ab6 | 3953 | { |
e2ebc833 | 3954 | const struct il_channel_info *ch_info; |
be663ab6 | 3955 | |
c8b03958 | 3956 | memset(&il->staging, 0, sizeof(il->staging)); |
be663ab6 | 3957 | |
83007196 | 3958 | if (!il->vif) { |
0f8b90f5 | 3959 | il->staging.dev_type = RXON_DEV_TYPE_ESS; |
83007196 SG |
3960 | } else if (il->vif->type == NL80211_IFTYPE_STATION) { |
3961 | il->staging.dev_type = RXON_DEV_TYPE_ESS; | |
3962 | il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
3963 | } else if (il->vif->type == NL80211_IFTYPE_ADHOC) { | |
3964 | il->staging.dev_type = RXON_DEV_TYPE_IBSS; | |
3965 | il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
3966 | il->staging.filter_flags = | |
3967 | RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK; | |
3968 | } else { | |
3969 | IL_ERR("Unsupported interface type %d\n", il->vif->type); | |
3970 | return; | |
3971 | } | |
be663ab6 WYG |
3972 | |
3973 | #if 0 | |
3974 | /* TODO: Figure out when short_preamble would be set and cache from | |
3975 | * that */ | |
46bc8d4b | 3976 | if (!hw_to_local(il->hw)->short_preamble) |
c8b03958 | 3977 | il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
be663ab6 | 3978 | else |
c8b03958 | 3979 | il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
be663ab6 WYG |
3980 | #endif |
3981 | ||
e7392364 | 3982 | ch_info = |
c8b03958 | 3983 | il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel)); |
be663ab6 WYG |
3984 | |
3985 | if (!ch_info) | |
46bc8d4b | 3986 | ch_info = &il->channel_info[0]; |
be663ab6 | 3987 | |
c8b03958 | 3988 | il->staging.channel = cpu_to_le16(ch_info->channel); |
46bc8d4b | 3989 | il->band = ch_info->band; |
be663ab6 | 3990 | |
83007196 | 3991 | il_set_flags_for_band(il, il->band, il->vif); |
be663ab6 | 3992 | |
c8b03958 | 3993 | il->staging.ofdm_basic_rates = |
e2ebc833 | 3994 | (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF; |
c8b03958 | 3995 | il->staging.cck_basic_rates = |
e2ebc833 | 3996 | (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF; |
be663ab6 WYG |
3997 | |
3998 | /* clear both MIX and PURE40 mode flag */ | |
c8b03958 | 3999 | il->staging.flags &= |
e7392364 | 4000 | ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40); |
83007196 SG |
4001 | if (il->vif) |
4002 | memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN); | |
be663ab6 | 4003 | |
c8b03958 SG |
4004 | il->staging.ofdm_ht_single_stream_basic_rates = 0xff; |
4005 | il->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
be663ab6 | 4006 | } |
e2ebc833 | 4007 | EXPORT_SYMBOL(il_connection_init_rx_config); |
be663ab6 | 4008 | |
e7392364 SG |
4009 | void |
4010 | il_set_rate(struct il_priv *il) | |
be663ab6 WYG |
4011 | { |
4012 | const struct ieee80211_supported_band *hw = NULL; | |
4013 | struct ieee80211_rate *rate; | |
be663ab6 WYG |
4014 | int i; |
4015 | ||
46bc8d4b | 4016 | hw = il_get_hw_mode(il, il->band); |
be663ab6 | 4017 | if (!hw) { |
9406f797 | 4018 | IL_ERR("Failed to set rate: unable to get hw mode\n"); |
be663ab6 WYG |
4019 | return; |
4020 | } | |
4021 | ||
46bc8d4b | 4022 | il->active_rate = 0; |
be663ab6 WYG |
4023 | |
4024 | for (i = 0; i < hw->n_bitrates; i++) { | |
4025 | rate = &(hw->bitrates[i]); | |
2eb05816 | 4026 | if (rate->hw_value < RATE_COUNT_LEGACY) |
46bc8d4b | 4027 | il->active_rate |= (1 << rate->hw_value); |
be663ab6 WYG |
4028 | } |
4029 | ||
58de00a4 | 4030 | D_RATE("Set active_rate = %0x\n", il->active_rate); |
be663ab6 | 4031 | |
c8b03958 | 4032 | il->staging.cck_basic_rates = |
e7392364 | 4033 | (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF; |
be663ab6 | 4034 | |
c8b03958 | 4035 | il->staging.ofdm_basic_rates = |
e7392364 | 4036 | (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF; |
be663ab6 | 4037 | } |
e2ebc833 | 4038 | EXPORT_SYMBOL(il_set_rate); |
be663ab6 | 4039 | |
e7392364 SG |
4040 | void |
4041 | il_chswitch_done(struct il_priv *il, bool is_success) | |
be663ab6 | 4042 | { |
a6766ccd | 4043 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
4044 | return; |
4045 | ||
a6766ccd | 4046 | if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) |
83007196 | 4047 | ieee80211_chswitch_done(il->vif, is_success); |
be663ab6 | 4048 | } |
e2ebc833 | 4049 | EXPORT_SYMBOL(il_chswitch_done); |
be663ab6 | 4050 | |
e7392364 SG |
4051 | void |
4052 | il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4053 | { |
dcae1c64 | 4054 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 4055 | struct il_csa_notification *csa = &(pkt->u.csa_notif); |
c8b03958 | 4056 | struct il_rxon_cmd *rxon = (void *)&il->active; |
be663ab6 | 4057 | |
a6766ccd | 4058 | if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) |
51e65257 SG |
4059 | return; |
4060 | ||
46bc8d4b | 4061 | if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) { |
51e65257 | 4062 | rxon->channel = csa->channel; |
c8b03958 | 4063 | il->staging.channel = csa->channel; |
e7392364 | 4064 | D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel)); |
46bc8d4b | 4065 | il_chswitch_done(il, true); |
51e65257 | 4066 | } else { |
9406f797 | 4067 | IL_ERR("CSA notif (fail) : channel %d\n", |
e7392364 | 4068 | le16_to_cpu(csa->channel)); |
46bc8d4b | 4069 | il_chswitch_done(il, false); |
be663ab6 WYG |
4070 | } |
4071 | } | |
d2dfb33e | 4072 | EXPORT_SYMBOL(il_hdl_csa); |
be663ab6 | 4073 | |
d3175167 | 4074 | #ifdef CONFIG_IWLEGACY_DEBUG |
e7392364 | 4075 | void |
83007196 | 4076 | il_print_rx_config_cmd(struct il_priv *il) |
be663ab6 | 4077 | { |
c8b03958 | 4078 | struct il_rxon_cmd *rxon = &il->staging; |
be663ab6 | 4079 | |
58de00a4 | 4080 | D_RADIO("RX CONFIG:\n"); |
46bc8d4b | 4081 | il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e7392364 | 4082 | D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
58de00a4 | 4083 | D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); |
e7392364 | 4084 | D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags)); |
58de00a4 | 4085 | D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); |
e7392364 SG |
4086 | D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates); |
4087 | D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
58de00a4 SG |
4088 | D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr); |
4089 | D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
e7392364 | 4090 | D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
be663ab6 | 4091 | } |
e2ebc833 | 4092 | EXPORT_SYMBOL(il_print_rx_config_cmd); |
be663ab6 WYG |
4093 | #endif |
4094 | /** | |
e2ebc833 | 4095 | * il_irq_handle_error - called for HW or SW error interrupt from card |
be663ab6 | 4096 | */ |
e7392364 SG |
4097 | void |
4098 | il_irq_handle_error(struct il_priv *il) | |
be663ab6 | 4099 | { |
e2ebc833 | 4100 | /* Set the FW error flag -- cleared on il_down */ |
a6766ccd | 4101 | set_bit(S_FW_ERROR, &il->status); |
be663ab6 WYG |
4102 | |
4103 | /* Cancel currently queued command. */ | |
a6766ccd | 4104 | clear_bit(S_HCMD_ACTIVE, &il->status); |
be663ab6 | 4105 | |
e7392364 | 4106 | IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version); |
be663ab6 | 4107 | |
c39ae9fd SG |
4108 | il->ops->lib->dump_nic_error_log(il); |
4109 | if (il->ops->lib->dump_fh) | |
4110 | il->ops->lib->dump_fh(il, NULL, false); | |
d3175167 | 4111 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 4112 | if (il_get_debug_level(il) & IL_DL_FW_ERRORS) |
83007196 | 4113 | il_print_rx_config_cmd(il); |
be663ab6 WYG |
4114 | #endif |
4115 | ||
46bc8d4b | 4116 | wake_up(&il->wait_command_queue); |
be663ab6 WYG |
4117 | |
4118 | /* Keep the restart process from trying to send host | |
4119 | * commands by clearing the INIT status bit */ | |
a6766ccd | 4120 | clear_bit(S_READY, &il->status); |
be663ab6 | 4121 | |
a6766ccd | 4122 | if (!test_bit(S_EXIT_PENDING, &il->status)) { |
58de00a4 | 4123 | IL_DBG(IL_DL_FW_ERRORS, |
e7392364 | 4124 | "Restarting adapter due to uCode error.\n"); |
be663ab6 | 4125 | |
46bc8d4b SG |
4126 | if (il->cfg->mod_params->restart_fw) |
4127 | queue_work(il->workqueue, &il->restart); | |
be663ab6 WYG |
4128 | } |
4129 | } | |
e2ebc833 | 4130 | EXPORT_SYMBOL(il_irq_handle_error); |
be663ab6 | 4131 | |
e7392364 SG |
4132 | static int |
4133 | il_apm_stop_master(struct il_priv *il) | |
be663ab6 WYG |
4134 | { |
4135 | int ret = 0; | |
4136 | ||
4137 | /* stop device's busmaster DMA activity */ | |
46bc8d4b | 4138 | il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
be663ab6 | 4139 | |
e7392364 SG |
4140 | ret = |
4141 | _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
4142 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
be663ab6 | 4143 | if (ret) |
9406f797 | 4144 | IL_WARN("Master Disable Timed Out, 100 usec\n"); |
be663ab6 | 4145 | |
58de00a4 | 4146 | D_INFO("stop master\n"); |
be663ab6 WYG |
4147 | |
4148 | return ret; | |
4149 | } | |
4150 | ||
e7392364 SG |
4151 | void |
4152 | il_apm_stop(struct il_priv *il) | |
be663ab6 | 4153 | { |
58de00a4 | 4154 | D_INFO("Stop card, put in low power state\n"); |
be663ab6 WYG |
4155 | |
4156 | /* Stop device's DMA activity */ | |
46bc8d4b | 4157 | il_apm_stop_master(il); |
be663ab6 WYG |
4158 | |
4159 | /* Reset the entire device */ | |
46bc8d4b | 4160 | il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
be663ab6 WYG |
4161 | |
4162 | udelay(10); | |
4163 | ||
4164 | /* | |
4165 | * Clear "initialization complete" bit to move adapter from | |
4166 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
4167 | */ | |
e7392364 | 4168 | il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
be663ab6 | 4169 | } |
e7392364 | 4170 | EXPORT_SYMBOL(il_apm_stop); |
be663ab6 WYG |
4171 | |
4172 | /* | |
4173 | * Start up NIC's basic functionality after it has been reset | |
e2ebc833 | 4174 | * (e.g. after platform boot, or shutdown via il_apm_stop()) |
be663ab6 WYG |
4175 | * NOTE: This does not load uCode nor start the embedded processor |
4176 | */ | |
e7392364 SG |
4177 | int |
4178 | il_apm_init(struct il_priv *il) | |
be663ab6 WYG |
4179 | { |
4180 | int ret = 0; | |
4181 | u16 lctl; | |
4182 | ||
58de00a4 | 4183 | D_INFO("Init card's basic functions\n"); |
be663ab6 WYG |
4184 | |
4185 | /* | |
4186 | * Use "set_bit" below rather than "write", to preserve any hardware | |
4187 | * bits already set by default after reset. | |
4188 | */ | |
4189 | ||
4190 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
46bc8d4b | 4191 | il_set_bit(il, CSR_GIO_CHICKEN_BITS, |
e7392364 | 4192 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
be663ab6 WYG |
4193 | |
4194 | /* | |
4195 | * Disable L0s without affecting L1; | |
4196 | * don't wait for ICH L0s (ICH bug W/A) | |
4197 | */ | |
46bc8d4b | 4198 | il_set_bit(il, CSR_GIO_CHICKEN_BITS, |
e7392364 | 4199 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
be663ab6 WYG |
4200 | |
4201 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
e7392364 | 4202 | il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
be663ab6 WYG |
4203 | |
4204 | /* | |
4205 | * Enable HAP INTA (interrupt from management bus) to | |
4206 | * wake device's PCI Express link L1a -> L0s | |
25985edc | 4207 | * NOTE: This is no-op for 3945 (non-existent bit) |
be663ab6 | 4208 | */ |
46bc8d4b | 4209 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
e7392364 | 4210 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
be663ab6 WYG |
4211 | |
4212 | /* | |
4213 | * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition. | |
4214 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
4215 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
4216 | * costs negligible amount of power savings. | |
4217 | * If not (unlikely), enable L0S, so there is at least some | |
4218 | * power savings, even without L1. | |
4219 | */ | |
89ef1ed2 | 4220 | if (il->cfg->set_l0s) { |
46bc8d4b | 4221 | lctl = il_pcie_link_ctl(il); |
be663ab6 | 4222 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == |
e7392364 | 4223 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { |
be663ab6 | 4224 | /* L1-ASPM enabled; disable(!) L0S */ |
46bc8d4b | 4225 | il_set_bit(il, CSR_GIO_REG, |
e7392364 | 4226 | CSR_GIO_REG_VAL_L0S_ENABLED); |
58de00a4 | 4227 | D_POWER("L1 Enabled; Disabling L0S\n"); |
be663ab6 WYG |
4228 | } else { |
4229 | /* L1-ASPM disabled; enable(!) L0S */ | |
46bc8d4b | 4230 | il_clear_bit(il, CSR_GIO_REG, |
e7392364 | 4231 | CSR_GIO_REG_VAL_L0S_ENABLED); |
58de00a4 | 4232 | D_POWER("L1 Disabled; Enabling L0S\n"); |
be663ab6 WYG |
4233 | } |
4234 | } | |
4235 | ||
4236 | /* Configure analog phase-lock-loop before activating to D0A */ | |
89ef1ed2 | 4237 | if (il->cfg->pll_cfg_val) |
46bc8d4b | 4238 | il_set_bit(il, CSR_ANA_PLL_CFG, |
89ef1ed2 | 4239 | il->cfg->pll_cfg_val); |
be663ab6 WYG |
4240 | |
4241 | /* | |
4242 | * Set "initialization complete" bit to move adapter from | |
4243 | * D0U* --> D0A* (powered-up active) state. | |
4244 | */ | |
46bc8d4b | 4245 | il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
be663ab6 WYG |
4246 | |
4247 | /* | |
4248 | * Wait for clock stabilization; once stabilized, access to | |
db54eb57 | 4249 | * device-internal resources is supported, e.g. il_wr_prph() |
be663ab6 WYG |
4250 | * and accesses to uCode SRAM. |
4251 | */ | |
e7392364 SG |
4252 | ret = |
4253 | _il_poll_bit(il, CSR_GP_CNTRL, | |
4254 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
4255 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
be663ab6 | 4256 | if (ret < 0) { |
58de00a4 | 4257 | D_INFO("Failed to init the card\n"); |
be663ab6 WYG |
4258 | goto out; |
4259 | } | |
4260 | ||
4261 | /* | |
4262 | * Enable DMA and BSM (if used) clocks, wait for them to stabilize. | |
4263 | * BSM (Boostrap State Machine) is only in 3945 and 4965. | |
4264 | * | |
4265 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
4266 | * do not disable clocks. This preserves any hardware bits already | |
4267 | * set by default in "CLK_CTRL_REG" after reset. | |
4268 | */ | |
89ef1ed2 | 4269 | if (il->cfg->use_bsm) |
db54eb57 | 4270 | il_wr_prph(il, APMG_CLK_EN_REG, |
e7392364 | 4271 | APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT); |
be663ab6 | 4272 | else |
e7392364 | 4273 | il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
be663ab6 WYG |
4274 | udelay(20); |
4275 | ||
4276 | /* Disable L1-Active */ | |
46bc8d4b | 4277 | il_set_bits_prph(il, APMG_PCIDEV_STT_REG, |
e7392364 | 4278 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
be663ab6 WYG |
4279 | |
4280 | out: | |
4281 | return ret; | |
4282 | } | |
e7392364 | 4283 | EXPORT_SYMBOL(il_apm_init); |
be663ab6 | 4284 | |
e7392364 SG |
4285 | int |
4286 | il_set_tx_power(struct il_priv *il, s8 tx_power, bool force) | |
be663ab6 WYG |
4287 | { |
4288 | int ret; | |
4289 | s8 prev_tx_power; | |
43f12d47 | 4290 | bool defer; |
be663ab6 | 4291 | |
46bc8d4b | 4292 | lockdep_assert_held(&il->mutex); |
be663ab6 | 4293 | |
46bc8d4b | 4294 | if (il->tx_power_user_lmt == tx_power && !force) |
be663ab6 WYG |
4295 | return 0; |
4296 | ||
c39ae9fd | 4297 | if (!il->ops->lib->send_tx_power) |
be663ab6 WYG |
4298 | return -EOPNOTSUPP; |
4299 | ||
332704a5 SG |
4300 | /* 0 dBm mean 1 milliwatt */ |
4301 | if (tx_power < 0) { | |
e7392364 | 4302 | IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power); |
be663ab6 WYG |
4303 | return -EINVAL; |
4304 | } | |
4305 | ||
46bc8d4b | 4306 | if (tx_power > il->tx_power_device_lmt) { |
e7392364 SG |
4307 | IL_WARN("Requested user TXPOWER %d above upper limit %d.\n", |
4308 | tx_power, il->tx_power_device_lmt); | |
be663ab6 WYG |
4309 | return -EINVAL; |
4310 | } | |
4311 | ||
46bc8d4b | 4312 | if (!il_is_ready_rf(il)) |
be663ab6 WYG |
4313 | return -EIO; |
4314 | ||
43f12d47 SG |
4315 | /* scan complete and commit_rxon use tx_power_next value, |
4316 | * it always need to be updated for newest request */ | |
46bc8d4b | 4317 | il->tx_power_next = tx_power; |
43f12d47 SG |
4318 | |
4319 | /* do not set tx power when scanning or channel changing */ | |
a6766ccd | 4320 | defer = test_bit(S_SCANNING, &il->status) || |
c8b03958 | 4321 | memcmp(&il->active, &il->staging, sizeof(il->staging)); |
43f12d47 | 4322 | if (defer && !force) { |
58de00a4 | 4323 | D_INFO("Deferring tx power set\n"); |
be663ab6 WYG |
4324 | return 0; |
4325 | } | |
4326 | ||
46bc8d4b SG |
4327 | prev_tx_power = il->tx_power_user_lmt; |
4328 | il->tx_power_user_lmt = tx_power; | |
be663ab6 | 4329 | |
c39ae9fd | 4330 | ret = il->ops->lib->send_tx_power(il); |
be663ab6 WYG |
4331 | |
4332 | /* if fail to set tx_power, restore the orig. tx power */ | |
4333 | if (ret) { | |
46bc8d4b SG |
4334 | il->tx_power_user_lmt = prev_tx_power; |
4335 | il->tx_power_next = prev_tx_power; | |
be663ab6 WYG |
4336 | } |
4337 | return ret; | |
4338 | } | |
e2ebc833 | 4339 | EXPORT_SYMBOL(il_set_tx_power); |
be663ab6 | 4340 | |
e7392364 SG |
4341 | void |
4342 | il_send_bt_config(struct il_priv *il) | |
be663ab6 | 4343 | { |
e2ebc833 | 4344 | struct il_bt_cmd bt_cmd = { |
be663ab6 WYG |
4345 | .lead_time = BT_LEAD_TIME_DEF, |
4346 | .max_kill = BT_MAX_KILL_DEF, | |
4347 | .kill_ack_mask = 0, | |
4348 | .kill_cts_mask = 0, | |
4349 | }; | |
4350 | ||
4351 | if (!bt_coex_active) | |
4352 | bt_cmd.flags = BT_COEX_DISABLE; | |
4353 | else | |
4354 | bt_cmd.flags = BT_COEX_ENABLE; | |
4355 | ||
58de00a4 | 4356 | D_INFO("BT coex %s\n", |
e7392364 | 4357 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); |
be663ab6 | 4358 | |
e7392364 | 4359 | if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd)) |
9406f797 | 4360 | IL_ERR("failed to send BT Coex Config\n"); |
be663ab6 | 4361 | } |
e2ebc833 | 4362 | EXPORT_SYMBOL(il_send_bt_config); |
be663ab6 | 4363 | |
e7392364 SG |
4364 | int |
4365 | il_send_stats_request(struct il_priv *il, u8 flags, bool clear) | |
be663ab6 | 4366 | { |
ebf0d90d | 4367 | struct il_stats_cmd stats_cmd = { |
e7392364 | 4368 | .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0, |
be663ab6 WYG |
4369 | }; |
4370 | ||
4371 | if (flags & CMD_ASYNC) | |
e7392364 SG |
4372 | return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd), |
4373 | &stats_cmd, NULL); | |
be663ab6 | 4374 | else |
e7392364 SG |
4375 | return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd), |
4376 | &stats_cmd); | |
be663ab6 | 4377 | } |
ebf0d90d | 4378 | EXPORT_SYMBOL(il_send_stats_request); |
be663ab6 | 4379 | |
e7392364 SG |
4380 | void |
4381 | il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4382 | { |
d3175167 | 4383 | #ifdef CONFIG_IWLEGACY_DEBUG |
dcae1c64 | 4384 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 4385 | struct il_sleep_notification *sleep = &(pkt->u.sleep_notif); |
58de00a4 | 4386 | D_RX("sleep mode: %d, src: %d\n", |
1722f8e1 | 4387 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); |
be663ab6 WYG |
4388 | #endif |
4389 | } | |
d2dfb33e | 4390 | EXPORT_SYMBOL(il_hdl_pm_sleep); |
be663ab6 | 4391 | |
e7392364 SG |
4392 | void |
4393 | il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4394 | { |
dcae1c64 | 4395 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e94a4099 | 4396 | u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK; |
e7392364 SG |
4397 | D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len, |
4398 | il_get_cmd_string(pkt->hdr.cmd)); | |
46bc8d4b | 4399 | il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len); |
be663ab6 | 4400 | } |
d2dfb33e | 4401 | EXPORT_SYMBOL(il_hdl_pm_debug_stats); |
be663ab6 | 4402 | |
e7392364 SG |
4403 | void |
4404 | il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4405 | { |
dcae1c64 | 4406 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
be663ab6 | 4407 | |
9406f797 | 4408 | IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) " |
e7392364 SG |
4409 | "seq 0x%04X ser 0x%08X\n", |
4410 | le32_to_cpu(pkt->u.err_resp.error_type), | |
4411 | il_get_cmd_string(pkt->u.err_resp.cmd_id), | |
4412 | pkt->u.err_resp.cmd_id, | |
4413 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
4414 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
be663ab6 | 4415 | } |
6e9848b4 | 4416 | EXPORT_SYMBOL(il_hdl_error); |
be663ab6 | 4417 | |
e7392364 SG |
4418 | void |
4419 | il_clear_isr_stats(struct il_priv *il) | |
be663ab6 | 4420 | { |
46bc8d4b | 4421 | memset(&il->isr_stats, 0, sizeof(il->isr_stats)); |
be663ab6 WYG |
4422 | } |
4423 | ||
e7392364 SG |
4424 | int |
4425 | il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, | |
4426 | const struct ieee80211_tx_queue_params *params) | |
be663ab6 | 4427 | { |
46bc8d4b | 4428 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
4429 | unsigned long flags; |
4430 | int q; | |
4431 | ||
58de00a4 | 4432 | D_MAC80211("enter\n"); |
be663ab6 | 4433 | |
46bc8d4b | 4434 | if (!il_is_ready_rf(il)) { |
58de00a4 | 4435 | D_MAC80211("leave - RF not ready\n"); |
be663ab6 WYG |
4436 | return -EIO; |
4437 | } | |
4438 | ||
4439 | if (queue >= AC_NUM) { | |
58de00a4 | 4440 | D_MAC80211("leave - queue >= AC_NUM %d\n", queue); |
be663ab6 WYG |
4441 | return 0; |
4442 | } | |
4443 | ||
4444 | q = AC_NUM - 1 - queue; | |
4445 | ||
46bc8d4b | 4446 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 | 4447 | |
8d44f2bd | 4448 | il->qos_data.def_qos_parm.ac[q].cw_min = |
e7392364 | 4449 | cpu_to_le16(params->cw_min); |
8d44f2bd | 4450 | il->qos_data.def_qos_parm.ac[q].cw_max = |
e7392364 | 4451 | cpu_to_le16(params->cw_max); |
8d44f2bd SG |
4452 | il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; |
4453 | il->qos_data.def_qos_parm.ac[q].edca_txop = | |
e7392364 | 4454 | cpu_to_le16((params->txop * 32)); |
be663ab6 | 4455 | |
8d44f2bd | 4456 | il->qos_data.def_qos_parm.ac[q].reserved1 = 0; |
be663ab6 | 4457 | |
46bc8d4b | 4458 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 4459 | |
58de00a4 | 4460 | D_MAC80211("leave\n"); |
be663ab6 WYG |
4461 | return 0; |
4462 | } | |
e2ebc833 | 4463 | EXPORT_SYMBOL(il_mac_conf_tx); |
be663ab6 | 4464 | |
e7392364 SG |
4465 | int |
4466 | il_mac_tx_last_beacon(struct ieee80211_hw *hw) | |
be663ab6 | 4467 | { |
46bc8d4b | 4468 | struct il_priv *il = hw->priv; |
be663ab6 | 4469 | |
46bc8d4b | 4470 | return il->ibss_manager == IL_IBSS_MANAGER; |
be663ab6 | 4471 | } |
e2ebc833 | 4472 | EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon); |
be663ab6 WYG |
4473 | |
4474 | static int | |
83007196 | 4475 | il_set_mode(struct il_priv *il) |
be663ab6 | 4476 | { |
83007196 | 4477 | il_connection_init_rx_config(il); |
be663ab6 | 4478 | |
c39ae9fd SG |
4479 | if (il->ops->hcmd->set_rxon_chain) |
4480 | il->ops->hcmd->set_rxon_chain(il); | |
be663ab6 | 4481 | |
83007196 | 4482 | return il_commit_rxon(il); |
be663ab6 WYG |
4483 | } |
4484 | ||
be663ab6 | 4485 | int |
e2ebc833 | 4486 | il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
be663ab6 | 4487 | { |
46bc8d4b | 4488 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
4489 | int err; |
4490 | ||
e7392364 | 4491 | D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr); |
be663ab6 | 4492 | |
46bc8d4b | 4493 | mutex_lock(&il->mutex); |
be663ab6 | 4494 | |
46bc8d4b | 4495 | if (!il_is_ready_rf(il)) { |
9406f797 | 4496 | IL_WARN("Try to add interface when device not ready\n"); |
be663ab6 WYG |
4497 | err = -EINVAL; |
4498 | goto out; | |
4499 | } | |
4500 | ||
83007196 | 4501 | if (il->vif) { |
be663ab6 WYG |
4502 | err = -EOPNOTSUPP; |
4503 | goto out; | |
4504 | } | |
4505 | ||
83007196 | 4506 | il->vif = vif; |
20c47eba | 4507 | il->iw_mode = vif->type; |
be663ab6 | 4508 | |
83007196 | 4509 | err = il_set_mode(il); |
17d6e557 | 4510 | if (err) { |
83007196 | 4511 | il->vif = NULL; |
17d6e557 SG |
4512 | il->iw_mode = NL80211_IFTYPE_STATION; |
4513 | } | |
be663ab6 | 4514 | |
e7392364 | 4515 | out: |
46bc8d4b | 4516 | mutex_unlock(&il->mutex); |
be663ab6 | 4517 | |
58de00a4 | 4518 | D_MAC80211("leave\n"); |
be663ab6 WYG |
4519 | return err; |
4520 | } | |
e2ebc833 | 4521 | EXPORT_SYMBOL(il_mac_add_interface); |
be663ab6 | 4522 | |
e7392364 SG |
4523 | static void |
4524 | il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif, | |
4525 | bool mode_change) | |
be663ab6 | 4526 | { |
46bc8d4b | 4527 | lockdep_assert_held(&il->mutex); |
be663ab6 | 4528 | |
46bc8d4b SG |
4529 | if (il->scan_vif == vif) { |
4530 | il_scan_cancel_timeout(il, 200); | |
4531 | il_force_scan_end(il); | |
be663ab6 WYG |
4532 | } |
4533 | ||
dee9a09e | 4534 | if (!mode_change) |
83007196 | 4535 | il_set_mode(il); |
dee9a09e | 4536 | |
be663ab6 WYG |
4537 | } |
4538 | ||
e7392364 SG |
4539 | void |
4540 | il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
be663ab6 | 4541 | { |
46bc8d4b | 4542 | struct il_priv *il = hw->priv; |
be663ab6 | 4543 | |
58de00a4 | 4544 | D_MAC80211("enter\n"); |
be663ab6 | 4545 | |
46bc8d4b | 4546 | mutex_lock(&il->mutex); |
be663ab6 | 4547 | |
83007196 SG |
4548 | WARN_ON(il->vif != vif); |
4549 | il->vif = NULL; | |
be663ab6 | 4550 | |
46bc8d4b | 4551 | il_teardown_interface(il, vif, false); |
be663ab6 | 4552 | |
46bc8d4b SG |
4553 | memset(il->bssid, 0, ETH_ALEN); |
4554 | mutex_unlock(&il->mutex); | |
be663ab6 | 4555 | |
58de00a4 | 4556 | D_MAC80211("leave\n"); |
be663ab6 WYG |
4557 | |
4558 | } | |
e2ebc833 | 4559 | EXPORT_SYMBOL(il_mac_remove_interface); |
be663ab6 | 4560 | |
e7392364 SG |
4561 | int |
4562 | il_alloc_txq_mem(struct il_priv *il) | |
be663ab6 | 4563 | { |
46bc8d4b | 4564 | if (!il->txq) |
e7392364 SG |
4565 | il->txq = |
4566 | kzalloc(sizeof(struct il_tx_queue) * | |
89ef1ed2 | 4567 | il->cfg->num_of_queues, GFP_KERNEL); |
46bc8d4b | 4568 | if (!il->txq) { |
9406f797 | 4569 | IL_ERR("Not enough memory for txq\n"); |
be663ab6 WYG |
4570 | return -ENOMEM; |
4571 | } | |
4572 | return 0; | |
4573 | } | |
e2ebc833 | 4574 | EXPORT_SYMBOL(il_alloc_txq_mem); |
be663ab6 | 4575 | |
e7392364 SG |
4576 | void |
4577 | il_txq_mem(struct il_priv *il) | |
be663ab6 | 4578 | { |
46bc8d4b SG |
4579 | kfree(il->txq); |
4580 | il->txq = NULL; | |
be663ab6 | 4581 | } |
e2ebc833 | 4582 | EXPORT_SYMBOL(il_txq_mem); |
be663ab6 | 4583 | |
d3175167 | 4584 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
be663ab6 | 4585 | |
e2ebc833 | 4586 | #define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES) |
be663ab6 | 4587 | |
e7392364 SG |
4588 | void |
4589 | il_reset_traffic_log(struct il_priv *il) | |
be663ab6 | 4590 | { |
46bc8d4b SG |
4591 | il->tx_traffic_idx = 0; |
4592 | il->rx_traffic_idx = 0; | |
4593 | if (il->tx_traffic) | |
4594 | memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE); | |
4595 | if (il->rx_traffic) | |
4596 | memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE); | |
be663ab6 WYG |
4597 | } |
4598 | ||
e7392364 SG |
4599 | int |
4600 | il_alloc_traffic_mem(struct il_priv *il) | |
be663ab6 | 4601 | { |
e2ebc833 | 4602 | u32 traffic_size = IL_TRAFFIC_DUMP_SIZE; |
be663ab6 | 4603 | |
d2ddf621 | 4604 | if (il_debug_level & IL_DL_TX) { |
46bc8d4b | 4605 | if (!il->tx_traffic) { |
e7392364 | 4606 | il->tx_traffic = kzalloc(traffic_size, GFP_KERNEL); |
46bc8d4b | 4607 | if (!il->tx_traffic) |
be663ab6 WYG |
4608 | return -ENOMEM; |
4609 | } | |
4610 | } | |
d2ddf621 | 4611 | if (il_debug_level & IL_DL_RX) { |
46bc8d4b | 4612 | if (!il->rx_traffic) { |
e7392364 | 4613 | il->rx_traffic = kzalloc(traffic_size, GFP_KERNEL); |
46bc8d4b | 4614 | if (!il->rx_traffic) |
be663ab6 WYG |
4615 | return -ENOMEM; |
4616 | } | |
4617 | } | |
46bc8d4b | 4618 | il_reset_traffic_log(il); |
be663ab6 WYG |
4619 | return 0; |
4620 | } | |
e2ebc833 | 4621 | EXPORT_SYMBOL(il_alloc_traffic_mem); |
be663ab6 | 4622 | |
e7392364 SG |
4623 | void |
4624 | il_free_traffic_mem(struct il_priv *il) | |
be663ab6 | 4625 | { |
46bc8d4b SG |
4626 | kfree(il->tx_traffic); |
4627 | il->tx_traffic = NULL; | |
be663ab6 | 4628 | |
46bc8d4b SG |
4629 | kfree(il->rx_traffic); |
4630 | il->rx_traffic = NULL; | |
be663ab6 | 4631 | } |
e2ebc833 | 4632 | EXPORT_SYMBOL(il_free_traffic_mem); |
be663ab6 | 4633 | |
e7392364 SG |
4634 | void |
4635 | il_dbg_log_tx_data_frame(struct il_priv *il, u16 length, | |
4636 | struct ieee80211_hdr *header) | |
be663ab6 WYG |
4637 | { |
4638 | __le16 fc; | |
4639 | u16 len; | |
4640 | ||
d2ddf621 | 4641 | if (likely(!(il_debug_level & IL_DL_TX))) |
be663ab6 WYG |
4642 | return; |
4643 | ||
46bc8d4b | 4644 | if (!il->tx_traffic) |
be663ab6 WYG |
4645 | return; |
4646 | ||
4647 | fc = header->frame_control; | |
4648 | if (ieee80211_is_data(fc)) { | |
e7392364 SG |
4649 | len = |
4650 | (length > | |
4651 | IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length; | |
46bc8d4b | 4652 | memcpy((il->tx_traffic + |
e7392364 SG |
4653 | (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header, |
4654 | len); | |
46bc8d4b | 4655 | il->tx_traffic_idx = |
e7392364 | 4656 | (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES; |
be663ab6 WYG |
4657 | } |
4658 | } | |
e2ebc833 | 4659 | EXPORT_SYMBOL(il_dbg_log_tx_data_frame); |
be663ab6 | 4660 | |
e7392364 SG |
4661 | void |
4662 | il_dbg_log_rx_data_frame(struct il_priv *il, u16 length, | |
4663 | struct ieee80211_hdr *header) | |
be663ab6 WYG |
4664 | { |
4665 | __le16 fc; | |
4666 | u16 len; | |
4667 | ||
d2ddf621 | 4668 | if (likely(!(il_debug_level & IL_DL_RX))) |
be663ab6 WYG |
4669 | return; |
4670 | ||
46bc8d4b | 4671 | if (!il->rx_traffic) |
be663ab6 WYG |
4672 | return; |
4673 | ||
4674 | fc = header->frame_control; | |
4675 | if (ieee80211_is_data(fc)) { | |
e7392364 SG |
4676 | len = |
4677 | (length > | |
4678 | IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length; | |
46bc8d4b | 4679 | memcpy((il->rx_traffic + |
e7392364 SG |
4680 | (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header, |
4681 | len); | |
46bc8d4b | 4682 | il->rx_traffic_idx = |
e7392364 | 4683 | (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES; |
be663ab6 WYG |
4684 | } |
4685 | } | |
e2ebc833 | 4686 | EXPORT_SYMBOL(il_dbg_log_rx_data_frame); |
be663ab6 | 4687 | |
e7392364 SG |
4688 | const char * |
4689 | il_get_mgmt_string(int cmd) | |
be663ab6 WYG |
4690 | { |
4691 | switch (cmd) { | |
e2ebc833 SG |
4692 | IL_CMD(MANAGEMENT_ASSOC_REQ); |
4693 | IL_CMD(MANAGEMENT_ASSOC_RESP); | |
4694 | IL_CMD(MANAGEMENT_REASSOC_REQ); | |
4695 | IL_CMD(MANAGEMENT_REASSOC_RESP); | |
4696 | IL_CMD(MANAGEMENT_PROBE_REQ); | |
4697 | IL_CMD(MANAGEMENT_PROBE_RESP); | |
4698 | IL_CMD(MANAGEMENT_BEACON); | |
4699 | IL_CMD(MANAGEMENT_ATIM); | |
4700 | IL_CMD(MANAGEMENT_DISASSOC); | |
4701 | IL_CMD(MANAGEMENT_AUTH); | |
4702 | IL_CMD(MANAGEMENT_DEAUTH); | |
4703 | IL_CMD(MANAGEMENT_ACTION); | |
be663ab6 WYG |
4704 | default: |
4705 | return "UNKNOWN"; | |
4706 | ||
4707 | } | |
4708 | } | |
4709 | ||
e7392364 SG |
4710 | const char * |
4711 | il_get_ctrl_string(int cmd) | |
be663ab6 WYG |
4712 | { |
4713 | switch (cmd) { | |
e2ebc833 SG |
4714 | IL_CMD(CONTROL_BACK_REQ); |
4715 | IL_CMD(CONTROL_BACK); | |
4716 | IL_CMD(CONTROL_PSPOLL); | |
4717 | IL_CMD(CONTROL_RTS); | |
4718 | IL_CMD(CONTROL_CTS); | |
4719 | IL_CMD(CONTROL_ACK); | |
4720 | IL_CMD(CONTROL_CFEND); | |
4721 | IL_CMD(CONTROL_CFENDACK); | |
be663ab6 WYG |
4722 | default: |
4723 | return "UNKNOWN"; | |
4724 | ||
4725 | } | |
4726 | } | |
4727 | ||
e7392364 SG |
4728 | void |
4729 | il_clear_traffic_stats(struct il_priv *il) | |
be663ab6 | 4730 | { |
46bc8d4b SG |
4731 | memset(&il->tx_stats, 0, sizeof(struct traffic_stats)); |
4732 | memset(&il->rx_stats, 0, sizeof(struct traffic_stats)); | |
be663ab6 WYG |
4733 | } |
4734 | ||
4735 | /* | |
d3175167 | 4736 | * if CONFIG_IWLEGACY_DEBUGFS defined, |
e2ebc833 | 4737 | * il_update_stats function will |
be663ab6 | 4738 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass |
ebf0d90d | 4739 | * Use debugFs to display the rx/rx_stats |
d3175167 | 4740 | * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL |
be663ab6 | 4741 | * information will be recorded, but DATA pkt still will be recorded |
e2ebc833 | 4742 | * for the reason of il_led.c need to control the led blinking based on |
be663ab6 WYG |
4743 | * number of tx and rx data. |
4744 | * | |
4745 | */ | |
4746 | void | |
46bc8d4b | 4747 | il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len) |
be663ab6 | 4748 | { |
e7392364 | 4749 | struct traffic_stats *stats; |
be663ab6 WYG |
4750 | |
4751 | if (is_tx) | |
46bc8d4b | 4752 | stats = &il->tx_stats; |
be663ab6 | 4753 | else |
46bc8d4b | 4754 | stats = &il->rx_stats; |
be663ab6 WYG |
4755 | |
4756 | if (ieee80211_is_mgmt(fc)) { | |
4757 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
4758 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
4759 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
4760 | break; | |
4761 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
4762 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
4763 | break; | |
4764 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
4765 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
4766 | break; | |
4767 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
4768 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
4769 | break; | |
4770 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
4771 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
4772 | break; | |
4773 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
4774 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
4775 | break; | |
4776 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
4777 | stats->mgmt[MANAGEMENT_BEACON]++; | |
4778 | break; | |
4779 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
4780 | stats->mgmt[MANAGEMENT_ATIM]++; | |
4781 | break; | |
4782 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
4783 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
4784 | break; | |
4785 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
4786 | stats->mgmt[MANAGEMENT_AUTH]++; | |
4787 | break; | |
4788 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
4789 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
4790 | break; | |
4791 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
4792 | stats->mgmt[MANAGEMENT_ACTION]++; | |
4793 | break; | |
4794 | } | |
4795 | } else if (ieee80211_is_ctl(fc)) { | |
4796 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
4797 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
4798 | stats->ctrl[CONTROL_BACK_REQ]++; | |
4799 | break; | |
4800 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
4801 | stats->ctrl[CONTROL_BACK]++; | |
4802 | break; | |
4803 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
4804 | stats->ctrl[CONTROL_PSPOLL]++; | |
4805 | break; | |
4806 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
4807 | stats->ctrl[CONTROL_RTS]++; | |
4808 | break; | |
4809 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
4810 | stats->ctrl[CONTROL_CTS]++; | |
4811 | break; | |
4812 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
4813 | stats->ctrl[CONTROL_ACK]++; | |
4814 | break; | |
4815 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
4816 | stats->ctrl[CONTROL_CFEND]++; | |
4817 | break; | |
4818 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
4819 | stats->ctrl[CONTROL_CFENDACK]++; | |
4820 | break; | |
4821 | } | |
4822 | } else { | |
4823 | /* data */ | |
4824 | stats->data_cnt++; | |
4825 | stats->data_bytes += len; | |
4826 | } | |
4827 | } | |
e2ebc833 | 4828 | EXPORT_SYMBOL(il_update_stats); |
be663ab6 WYG |
4829 | #endif |
4830 | ||
e7392364 SG |
4831 | int |
4832 | il_force_reset(struct il_priv *il, bool external) | |
be663ab6 | 4833 | { |
e2ebc833 | 4834 | struct il_force_reset *force_reset; |
be663ab6 | 4835 | |
a6766ccd | 4836 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
4837 | return -EINVAL; |
4838 | ||
46bc8d4b | 4839 | force_reset = &il->force_reset; |
be663ab6 WYG |
4840 | force_reset->reset_request_count++; |
4841 | if (!external) { | |
4842 | if (force_reset->last_force_reset_jiffies && | |
4843 | time_after(force_reset->last_force_reset_jiffies + | |
e7392364 | 4844 | force_reset->reset_duration, jiffies)) { |
58de00a4 | 4845 | D_INFO("force reset rejected\n"); |
be663ab6 WYG |
4846 | force_reset->reset_reject_count++; |
4847 | return -EAGAIN; | |
4848 | } | |
4849 | } | |
4850 | force_reset->reset_success_count++; | |
4851 | force_reset->last_force_reset_jiffies = jiffies; | |
dd6d2a8a SG |
4852 | |
4853 | /* | |
4854 | * if the request is from external(ex: debugfs), | |
4855 | * then always perform the request in regardless the module | |
4856 | * parameter setting | |
4857 | * if the request is from internal (uCode error or driver | |
4858 | * detect failure), then fw_restart module parameter | |
4859 | * need to be check before performing firmware reload | |
4860 | */ | |
4861 | ||
46bc8d4b | 4862 | if (!external && !il->cfg->mod_params->restart_fw) { |
58de00a4 | 4863 | D_INFO("Cancel firmware reload based on " |
e7392364 | 4864 | "module parameter setting\n"); |
dd6d2a8a | 4865 | return 0; |
be663ab6 | 4866 | } |
dd6d2a8a | 4867 | |
9406f797 | 4868 | IL_ERR("On demand firmware reload\n"); |
dd6d2a8a | 4869 | |
e2ebc833 | 4870 | /* Set the FW error flag -- cleared on il_down */ |
a6766ccd | 4871 | set_bit(S_FW_ERROR, &il->status); |
46bc8d4b | 4872 | wake_up(&il->wait_command_queue); |
dd6d2a8a SG |
4873 | /* |
4874 | * Keep the restart process from trying to send host | |
4875 | * commands by clearing the INIT status bit | |
4876 | */ | |
a6766ccd | 4877 | clear_bit(S_READY, &il->status); |
46bc8d4b | 4878 | queue_work(il->workqueue, &il->restart); |
dd6d2a8a | 4879 | |
be663ab6 WYG |
4880 | return 0; |
4881 | } | |
4882 | ||
4883 | int | |
e7392364 | 4884 | il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
be663ab6 WYG |
4885 | enum nl80211_iftype newtype, bool newp2p) |
4886 | { | |
46bc8d4b | 4887 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
4888 | int err; |
4889 | ||
8c9c48d5 SG |
4890 | if (newp2p) |
4891 | return -EOPNOTSUPP; | |
be663ab6 | 4892 | |
46bc8d4b | 4893 | mutex_lock(&il->mutex); |
be663ab6 | 4894 | |
83007196 | 4895 | if (!il->vif || !il_is_ready_rf(il)) { |
ffd8c746 JB |
4896 | /* |
4897 | * Huh? But wait ... this can maybe happen when | |
4898 | * we're in the middle of a firmware restart! | |
4899 | */ | |
4900 | err = -EBUSY; | |
4901 | goto out; | |
4902 | } | |
4903 | ||
be663ab6 | 4904 | /* success */ |
46bc8d4b | 4905 | il_teardown_interface(il, vif, true); |
be663ab6 | 4906 | vif->type = newtype; |
8c9c48d5 | 4907 | vif->p2p = false; |
83007196 | 4908 | err = il_set_mode(il); |
be663ab6 WYG |
4909 | WARN_ON(err); |
4910 | /* | |
4911 | * We've switched internally, but submitting to the | |
4912 | * device may have failed for some reason. Mask this | |
4913 | * error, because otherwise mac80211 will not switch | |
4914 | * (and set the interface type back) and we'll be | |
4915 | * out of sync with it. | |
4916 | */ | |
4917 | err = 0; | |
4918 | ||
e7392364 | 4919 | out: |
46bc8d4b | 4920 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
4921 | return err; |
4922 | } | |
e2ebc833 | 4923 | EXPORT_SYMBOL(il_mac_change_interface); |
be663ab6 WYG |
4924 | |
4925 | /* | |
4926 | * On every watchdog tick we check (latest) time stamp. If it does not | |
4927 | * change during timeout period and queue is not empty we reset firmware. | |
4928 | */ | |
e7392364 SG |
4929 | static int |
4930 | il_check_stuck_queue(struct il_priv *il, int cnt) | |
be663ab6 | 4931 | { |
46bc8d4b | 4932 | struct il_tx_queue *txq = &il->txq[cnt]; |
e2ebc833 | 4933 | struct il_queue *q = &txq->q; |
be663ab6 WYG |
4934 | unsigned long timeout; |
4935 | int ret; | |
4936 | ||
4937 | if (q->read_ptr == q->write_ptr) { | |
4938 | txq->time_stamp = jiffies; | |
4939 | return 0; | |
4940 | } | |
4941 | ||
e7392364 SG |
4942 | timeout = |
4943 | txq->time_stamp + | |
89ef1ed2 | 4944 | msecs_to_jiffies(il->cfg->wd_timeout); |
be663ab6 WYG |
4945 | |
4946 | if (time_after(jiffies, timeout)) { | |
e7392364 | 4947 | IL_ERR("Queue %d stuck for %u ms.\n", q->id, |
89ef1ed2 | 4948 | il->cfg->wd_timeout); |
46bc8d4b | 4949 | ret = il_force_reset(il, false); |
be663ab6 WYG |
4950 | return (ret == -EAGAIN) ? 0 : 1; |
4951 | } | |
4952 | ||
4953 | return 0; | |
4954 | } | |
4955 | ||
4956 | /* | |
4957 | * Making watchdog tick be a quarter of timeout assure we will | |
4958 | * discover the queue hung between timeout and 1.25*timeout | |
4959 | */ | |
e2ebc833 | 4960 | #define IL_WD_TICK(timeout) ((timeout) / 4) |
be663ab6 WYG |
4961 | |
4962 | /* | |
4963 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
4964 | * we reset the firmware. If everything is fine just rearm the timer. | |
4965 | */ | |
e7392364 SG |
4966 | void |
4967 | il_bg_watchdog(unsigned long data) | |
be663ab6 | 4968 | { |
46bc8d4b | 4969 | struct il_priv *il = (struct il_priv *)data; |
be663ab6 WYG |
4970 | int cnt; |
4971 | unsigned long timeout; | |
4972 | ||
a6766ccd | 4973 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
4974 | return; |
4975 | ||
89ef1ed2 | 4976 | timeout = il->cfg->wd_timeout; |
be663ab6 WYG |
4977 | if (timeout == 0) |
4978 | return; | |
4979 | ||
4980 | /* monitor and check for stuck cmd queue */ | |
46bc8d4b | 4981 | if (il_check_stuck_queue(il, il->cmd_queue)) |
be663ab6 WYG |
4982 | return; |
4983 | ||
4984 | /* monitor and check for other stuck queues */ | |
46bc8d4b SG |
4985 | if (il_is_any_associated(il)) { |
4986 | for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) { | |
be663ab6 | 4987 | /* skip as we already checked the command queue */ |
46bc8d4b | 4988 | if (cnt == il->cmd_queue) |
be663ab6 | 4989 | continue; |
46bc8d4b | 4990 | if (il_check_stuck_queue(il, cnt)) |
be663ab6 WYG |
4991 | return; |
4992 | } | |
4993 | } | |
4994 | ||
e7392364 SG |
4995 | mod_timer(&il->watchdog, |
4996 | jiffies + msecs_to_jiffies(IL_WD_TICK(timeout))); | |
be663ab6 | 4997 | } |
e2ebc833 | 4998 | EXPORT_SYMBOL(il_bg_watchdog); |
be663ab6 | 4999 | |
e7392364 SG |
5000 | void |
5001 | il_setup_watchdog(struct il_priv *il) | |
be663ab6 | 5002 | { |
89ef1ed2 | 5003 | unsigned int timeout = il->cfg->wd_timeout; |
be663ab6 WYG |
5004 | |
5005 | if (timeout) | |
46bc8d4b | 5006 | mod_timer(&il->watchdog, |
e2ebc833 | 5007 | jiffies + msecs_to_jiffies(IL_WD_TICK(timeout))); |
be663ab6 | 5008 | else |
46bc8d4b | 5009 | del_timer(&il->watchdog); |
be663ab6 | 5010 | } |
e2ebc833 | 5011 | EXPORT_SYMBOL(il_setup_watchdog); |
be663ab6 WYG |
5012 | |
5013 | /* | |
5014 | * extended beacon time format | |
5015 | * time in usec will be changed into a 32-bit value in extended:internal format | |
5016 | * the extended part is the beacon counts | |
5017 | * the internal part is the time in usec within one beacon interval | |
5018 | */ | |
5019 | u32 | |
e7392364 | 5020 | il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval) |
be663ab6 WYG |
5021 | { |
5022 | u32 quot; | |
5023 | u32 rem; | |
5024 | u32 interval = beacon_interval * TIME_UNIT; | |
5025 | ||
5026 | if (!interval || !usec) | |
5027 | return 0; | |
5028 | ||
e7392364 SG |
5029 | quot = |
5030 | (usec / | |
5031 | interval) & (il_beacon_time_mask_high(il, | |
5032 | il->hw_params. | |
5033 | beacon_time_tsf_bits) >> il-> | |
5034 | hw_params.beacon_time_tsf_bits); | |
5035 | rem = | |
5036 | (usec % interval) & il_beacon_time_mask_low(il, | |
5037 | il->hw_params. | |
5038 | beacon_time_tsf_bits); | |
be663ab6 | 5039 | |
46bc8d4b | 5040 | return (quot << il->hw_params.beacon_time_tsf_bits) + rem; |
be663ab6 | 5041 | } |
e2ebc833 | 5042 | EXPORT_SYMBOL(il_usecs_to_beacons); |
be663ab6 WYG |
5043 | |
5044 | /* base is usually what we get from ucode with each received frame, | |
5045 | * the same as HW timer counter counting down | |
5046 | */ | |
e7392364 | 5047 | __le32 |
1722f8e1 | 5048 | il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, |
e7392364 | 5049 | u32 beacon_interval) |
be663ab6 | 5050 | { |
46bc8d4b | 5051 | u32 base_low = base & il_beacon_time_mask_low(il, |
e7392364 SG |
5052 | il->hw_params. |
5053 | beacon_time_tsf_bits); | |
46bc8d4b | 5054 | u32 addon_low = addon & il_beacon_time_mask_low(il, |
e7392364 SG |
5055 | il->hw_params. |
5056 | beacon_time_tsf_bits); | |
be663ab6 | 5057 | u32 interval = beacon_interval * TIME_UNIT; |
46bc8d4b | 5058 | u32 res = (base & il_beacon_time_mask_high(il, |
e7392364 SG |
5059 | il->hw_params. |
5060 | beacon_time_tsf_bits)) + | |
5061 | (addon & il_beacon_time_mask_high(il, | |
5062 | il->hw_params. | |
5063 | beacon_time_tsf_bits)); | |
be663ab6 WYG |
5064 | |
5065 | if (base_low > addon_low) | |
5066 | res += base_low - addon_low; | |
5067 | else if (base_low < addon_low) { | |
5068 | res += interval + base_low - addon_low; | |
46bc8d4b | 5069 | res += (1 << il->hw_params.beacon_time_tsf_bits); |
be663ab6 | 5070 | } else |
46bc8d4b | 5071 | res += (1 << il->hw_params.beacon_time_tsf_bits); |
be663ab6 WYG |
5072 | |
5073 | return cpu_to_le32(res); | |
5074 | } | |
e2ebc833 | 5075 | EXPORT_SYMBOL(il_add_beacon_time); |
be663ab6 WYG |
5076 | |
5077 | #ifdef CONFIG_PM | |
5078 | ||
e7392364 SG |
5079 | int |
5080 | il_pci_suspend(struct device *device) | |
be663ab6 WYG |
5081 | { |
5082 | struct pci_dev *pdev = to_pci_dev(device); | |
46bc8d4b | 5083 | struct il_priv *il = pci_get_drvdata(pdev); |
be663ab6 WYG |
5084 | |
5085 | /* | |
5086 | * This function is called when system goes into suspend state | |
e2ebc833 SG |
5087 | * mac80211 will call il_mac_stop() from the mac80211 suspend function |
5088 | * first but since il_mac_stop() has no knowledge of who the caller is, | |
be663ab6 WYG |
5089 | * it will not call apm_ops.stop() to stop the DMA operation. |
5090 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
5091 | */ | |
46bc8d4b | 5092 | il_apm_stop(il); |
be663ab6 WYG |
5093 | |
5094 | return 0; | |
5095 | } | |
e2ebc833 | 5096 | EXPORT_SYMBOL(il_pci_suspend); |
be663ab6 | 5097 | |
e7392364 SG |
5098 | int |
5099 | il_pci_resume(struct device *device) | |
be663ab6 WYG |
5100 | { |
5101 | struct pci_dev *pdev = to_pci_dev(device); | |
46bc8d4b | 5102 | struct il_priv *il = pci_get_drvdata(pdev); |
be663ab6 WYG |
5103 | bool hw_rfkill = false; |
5104 | ||
5105 | /* | |
5106 | * We disable the RETRY_TIMEOUT register (0x41) to keep | |
5107 | * PCI Tx retries from interfering with C3 CPU state. | |
5108 | */ | |
5109 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
5110 | ||
46bc8d4b | 5111 | il_enable_interrupts(il); |
be663ab6 | 5112 | |
e7392364 | 5113 | if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
be663ab6 WYG |
5114 | hw_rfkill = true; |
5115 | ||
5116 | if (hw_rfkill) | |
a6766ccd | 5117 | set_bit(S_RF_KILL_HW, &il->status); |
be663ab6 | 5118 | else |
a6766ccd | 5119 | clear_bit(S_RF_KILL_HW, &il->status); |
be663ab6 | 5120 | |
46bc8d4b | 5121 | wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill); |
be663ab6 WYG |
5122 | |
5123 | return 0; | |
5124 | } | |
e2ebc833 | 5125 | EXPORT_SYMBOL(il_pci_resume); |
be663ab6 | 5126 | |
e2ebc833 SG |
5127 | const struct dev_pm_ops il_pm_ops = { |
5128 | .suspend = il_pci_suspend, | |
5129 | .resume = il_pci_resume, | |
5130 | .freeze = il_pci_suspend, | |
5131 | .thaw = il_pci_resume, | |
5132 | .poweroff = il_pci_suspend, | |
5133 | .restore = il_pci_resume, | |
be663ab6 | 5134 | }; |
e2ebc833 | 5135 | EXPORT_SYMBOL(il_pm_ops); |
be663ab6 WYG |
5136 | |
5137 | #endif /* CONFIG_PM */ | |
5138 | ||
5139 | static void | |
83007196 | 5140 | il_update_qos(struct il_priv *il) |
be663ab6 | 5141 | { |
a6766ccd | 5142 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
5143 | return; |
5144 | ||
8d44f2bd | 5145 | il->qos_data.def_qos_parm.qos_flags = 0; |
be663ab6 | 5146 | |
8d44f2bd SG |
5147 | if (il->qos_data.qos_active) |
5148 | il->qos_data.def_qos_parm.qos_flags |= | |
e7392364 | 5149 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; |
be663ab6 | 5150 | |
1c03c462 | 5151 | if (il->ht.enabled) |
8d44f2bd | 5152 | il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; |
be663ab6 | 5153 | |
58de00a4 | 5154 | D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n", |
8d44f2bd | 5155 | il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags); |
be663ab6 | 5156 | |
b96ed60c | 5157 | il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd), |
8d44f2bd | 5158 | &il->qos_data.def_qos_parm, NULL); |
be663ab6 WYG |
5159 | } |
5160 | ||
5161 | /** | |
e2ebc833 | 5162 | * il_mac_config - mac80211 config callback |
be663ab6 | 5163 | */ |
e7392364 SG |
5164 | int |
5165 | il_mac_config(struct ieee80211_hw *hw, u32 changed) | |
be663ab6 | 5166 | { |
46bc8d4b | 5167 | struct il_priv *il = hw->priv; |
e2ebc833 | 5168 | const struct il_channel_info *ch_info; |
be663ab6 WYG |
5169 | struct ieee80211_conf *conf = &hw->conf; |
5170 | struct ieee80211_channel *channel = conf->channel; | |
46bc8d4b | 5171 | struct il_ht_config *ht_conf = &il->current_ht_config; |
be663ab6 WYG |
5172 | unsigned long flags = 0; |
5173 | int ret = 0; | |
5174 | u16 ch; | |
5175 | int scan_active = 0; | |
7c2cde2e | 5176 | bool ht_changed = false; |
be663ab6 | 5177 | |
c39ae9fd | 5178 | if (WARN_ON(!il->ops->legacy)) |
be663ab6 WYG |
5179 | return -EOPNOTSUPP; |
5180 | ||
46bc8d4b | 5181 | mutex_lock(&il->mutex); |
be663ab6 | 5182 | |
e7392364 SG |
5183 | D_MAC80211("enter to channel %d changed 0x%X\n", channel->hw_value, |
5184 | changed); | |
be663ab6 | 5185 | |
a6766ccd | 5186 | if (unlikely(test_bit(S_SCANNING, &il->status))) { |
be663ab6 | 5187 | scan_active = 1; |
58de00a4 | 5188 | D_MAC80211("scan active\n"); |
be663ab6 WYG |
5189 | } |
5190 | ||
e7392364 SG |
5191 | if (changed & |
5192 | (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) { | |
be663ab6 | 5193 | /* mac80211 uses static for non-HT which is what we want */ |
46bc8d4b | 5194 | il->current_ht_config.smps = conf->smps_mode; |
be663ab6 WYG |
5195 | |
5196 | /* | |
5197 | * Recalculate chain counts. | |
5198 | * | |
5199 | * If monitor mode is enabled then mac80211 will | |
5200 | * set up the SM PS mode to OFF if an HT channel is | |
5201 | * configured. | |
5202 | */ | |
c39ae9fd SG |
5203 | if (il->ops->hcmd->set_rxon_chain) |
5204 | il->ops->hcmd->set_rxon_chain(il); | |
be663ab6 WYG |
5205 | } |
5206 | ||
5207 | /* during scanning mac80211 will delay channel setting until | |
5208 | * scan finish with changed = 0 | |
5209 | */ | |
5210 | if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { | |
17d6e557 | 5211 | |
be663ab6 WYG |
5212 | if (scan_active) |
5213 | goto set_ch_out; | |
5214 | ||
5215 | ch = channel->hw_value; | |
46bc8d4b | 5216 | ch_info = il_get_channel_info(il, channel->band, ch); |
e2ebc833 | 5217 | if (!il_is_channel_valid(ch_info)) { |
58de00a4 | 5218 | D_MAC80211("leave - invalid channel\n"); |
be663ab6 WYG |
5219 | ret = -EINVAL; |
5220 | goto set_ch_out; | |
5221 | } | |
5222 | ||
46bc8d4b | 5223 | if (il->iw_mode == NL80211_IFTYPE_ADHOC && |
e2ebc833 | 5224 | !il_is_channel_ibss(ch_info)) { |
58de00a4 | 5225 | D_MAC80211("leave - not IBSS channel\n"); |
eb85de3f SG |
5226 | ret = -EINVAL; |
5227 | goto set_ch_out; | |
5228 | } | |
5229 | ||
46bc8d4b | 5230 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 | 5231 | |
17d6e557 | 5232 | /* Configure HT40 channels */ |
1c03c462 SG |
5233 | if (il->ht.enabled != conf_is_ht(conf)) { |
5234 | il->ht.enabled = conf_is_ht(conf); | |
17d6e557 SG |
5235 | ht_changed = true; |
5236 | } | |
1c03c462 | 5237 | if (il->ht.enabled) { |
17d6e557 | 5238 | if (conf_is_ht40_minus(conf)) { |
1c03c462 | 5239 | il->ht.extension_chan_offset = |
e7392364 | 5240 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
1c03c462 | 5241 | il->ht.is_40mhz = true; |
17d6e557 | 5242 | } else if (conf_is_ht40_plus(conf)) { |
1c03c462 | 5243 | il->ht.extension_chan_offset = |
e7392364 | 5244 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
1c03c462 | 5245 | il->ht.is_40mhz = true; |
17d6e557 | 5246 | } else { |
1c03c462 | 5247 | il->ht.extension_chan_offset = |
e7392364 | 5248 | IEEE80211_HT_PARAM_CHA_SEC_NONE; |
1c03c462 | 5249 | il->ht.is_40mhz = false; |
17d6e557 SG |
5250 | } |
5251 | } else | |
1c03c462 | 5252 | il->ht.is_40mhz = false; |
be663ab6 | 5253 | |
17d6e557 SG |
5254 | /* |
5255 | * Default to no protection. Protection mode will | |
5256 | * later be set from BSS config in il_ht_conf | |
5257 | */ | |
1c03c462 | 5258 | il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE; |
be663ab6 | 5259 | |
17d6e557 SG |
5260 | /* if we are switching from ht to 2.4 clear flags |
5261 | * from any ht related info since 2.4 does not | |
5262 | * support ht */ | |
c8b03958 SG |
5263 | if ((le16_to_cpu(il->staging.channel) != ch)) |
5264 | il->staging.flags = 0; | |
be663ab6 | 5265 | |
83007196 | 5266 | il_set_rxon_channel(il, channel); |
17d6e557 | 5267 | il_set_rxon_ht(il, ht_conf); |
be663ab6 | 5268 | |
83007196 | 5269 | il_set_flags_for_band(il, channel->band, il->vif); |
be663ab6 | 5270 | |
46bc8d4b | 5271 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 5272 | |
c39ae9fd SG |
5273 | if (il->ops->legacy->update_bcast_stations) |
5274 | ret = il->ops->legacy->update_bcast_stations(il); | |
be663ab6 | 5275 | |
e7392364 | 5276 | set_ch_out: |
be663ab6 WYG |
5277 | /* The list of supported rates and rate mask can be different |
5278 | * for each band; since the band may have changed, reset | |
5279 | * the rate mask to what mac80211 lists */ | |
46bc8d4b | 5280 | il_set_rate(il); |
be663ab6 WYG |
5281 | } |
5282 | ||
e7392364 | 5283 | if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) { |
46bc8d4b | 5284 | ret = il_power_update_mode(il, false); |
be663ab6 | 5285 | if (ret) |
58de00a4 | 5286 | D_MAC80211("Error setting sleep level\n"); |
be663ab6 WYG |
5287 | } |
5288 | ||
5289 | if (changed & IEEE80211_CONF_CHANGE_POWER) { | |
e7392364 SG |
5290 | D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt, |
5291 | conf->power_level); | |
be663ab6 | 5292 | |
46bc8d4b | 5293 | il_set_tx_power(il, conf->power_level, false); |
be663ab6 WYG |
5294 | } |
5295 | ||
46bc8d4b | 5296 | if (!il_is_ready(il)) { |
58de00a4 | 5297 | D_MAC80211("leave - not ready\n"); |
be663ab6 WYG |
5298 | goto out; |
5299 | } | |
5300 | ||
5301 | if (scan_active) | |
5302 | goto out; | |
5303 | ||
c8b03958 | 5304 | if (memcmp(&il->active, &il->staging, sizeof(il->staging))) |
83007196 | 5305 | il_commit_rxon(il); |
17d6e557 SG |
5306 | else |
5307 | D_INFO("Not re-sending same RXON configuration.\n"); | |
5308 | if (ht_changed) | |
83007196 | 5309 | il_update_qos(il); |
be663ab6 WYG |
5310 | |
5311 | out: | |
58de00a4 | 5312 | D_MAC80211("leave\n"); |
46bc8d4b | 5313 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5314 | return ret; |
5315 | } | |
e2ebc833 | 5316 | EXPORT_SYMBOL(il_mac_config); |
be663ab6 | 5317 | |
e7392364 SG |
5318 | void |
5319 | il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
be663ab6 | 5320 | { |
46bc8d4b | 5321 | struct il_priv *il = hw->priv; |
be663ab6 | 5322 | unsigned long flags; |
be663ab6 | 5323 | |
c39ae9fd | 5324 | if (WARN_ON(!il->ops->legacy)) |
be663ab6 WYG |
5325 | return; |
5326 | ||
46bc8d4b | 5327 | mutex_lock(&il->mutex); |
58de00a4 | 5328 | D_MAC80211("enter\n"); |
be663ab6 | 5329 | |
46bc8d4b SG |
5330 | spin_lock_irqsave(&il->lock, flags); |
5331 | memset(&il->current_ht_config, 0, sizeof(struct il_ht_config)); | |
5332 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 | 5333 | |
46bc8d4b | 5334 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
5335 | |
5336 | /* new association get rid of ibss beacon skb */ | |
46bc8d4b SG |
5337 | if (il->beacon_skb) |
5338 | dev_kfree_skb(il->beacon_skb); | |
be663ab6 | 5339 | |
46bc8d4b | 5340 | il->beacon_skb = NULL; |
be663ab6 | 5341 | |
46bc8d4b | 5342 | il->timestamp = 0; |
be663ab6 | 5343 | |
46bc8d4b | 5344 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 5345 | |
46bc8d4b SG |
5346 | il_scan_cancel_timeout(il, 100); |
5347 | if (!il_is_ready_rf(il)) { | |
58de00a4 | 5348 | D_MAC80211("leave - not ready\n"); |
46bc8d4b | 5349 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5350 | return; |
5351 | } | |
5352 | ||
5353 | /* we are restarting association process | |
5354 | * clear RXON_FILTER_ASSOC_MSK bit | |
5355 | */ | |
c8b03958 | 5356 | il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
83007196 | 5357 | il_commit_rxon(il); |
be663ab6 | 5358 | |
46bc8d4b | 5359 | il_set_rate(il); |
be663ab6 | 5360 | |
46bc8d4b | 5361 | mutex_unlock(&il->mutex); |
be663ab6 | 5362 | |
58de00a4 | 5363 | D_MAC80211("leave\n"); |
be663ab6 | 5364 | } |
e2ebc833 | 5365 | EXPORT_SYMBOL(il_mac_reset_tsf); |
be663ab6 | 5366 | |
e7392364 SG |
5367 | static void |
5368 | il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif) | |
be663ab6 | 5369 | { |
46bc8d4b | 5370 | struct il_ht_config *ht_conf = &il->current_ht_config; |
be663ab6 WYG |
5371 | struct ieee80211_sta *sta; |
5372 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
be663ab6 | 5373 | |
58de00a4 | 5374 | D_ASSOC("enter:\n"); |
be663ab6 | 5375 | |
1c03c462 | 5376 | if (!il->ht.enabled) |
be663ab6 WYG |
5377 | return; |
5378 | ||
1c03c462 | 5379 | il->ht.protection = |
e7392364 | 5380 | bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION; |
1c03c462 | 5381 | il->ht.non_gf_sta_present = |
e7392364 SG |
5382 | !!(bss_conf-> |
5383 | ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); | |
be663ab6 WYG |
5384 | |
5385 | ht_conf->single_chain_sufficient = false; | |
5386 | ||
5387 | switch (vif->type) { | |
5388 | case NL80211_IFTYPE_STATION: | |
5389 | rcu_read_lock(); | |
5390 | sta = ieee80211_find_sta(vif, bss_conf->bssid); | |
5391 | if (sta) { | |
5392 | struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap; | |
5393 | int maxstreams; | |
5394 | ||
e7392364 SG |
5395 | maxstreams = |
5396 | (ht_cap->mcs. | |
5397 | tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK) | |
5398 | >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; | |
be663ab6 WYG |
5399 | maxstreams += 1; |
5400 | ||
232913b5 SG |
5401 | if (ht_cap->mcs.rx_mask[1] == 0 && |
5402 | ht_cap->mcs.rx_mask[2] == 0) | |
be663ab6 WYG |
5403 | ht_conf->single_chain_sufficient = true; |
5404 | if (maxstreams <= 1) | |
5405 | ht_conf->single_chain_sufficient = true; | |
5406 | } else { | |
5407 | /* | |
5408 | * If at all, this can only happen through a race | |
5409 | * when the AP disconnects us while we're still | |
5410 | * setting up the connection, in that case mac80211 | |
5411 | * will soon tell us about that. | |
5412 | */ | |
5413 | ht_conf->single_chain_sufficient = true; | |
5414 | } | |
5415 | rcu_read_unlock(); | |
5416 | break; | |
5417 | case NL80211_IFTYPE_ADHOC: | |
5418 | ht_conf->single_chain_sufficient = true; | |
5419 | break; | |
5420 | default: | |
5421 | break; | |
5422 | } | |
5423 | ||
58de00a4 | 5424 | D_ASSOC("leave\n"); |
be663ab6 WYG |
5425 | } |
5426 | ||
e7392364 SG |
5427 | static inline void |
5428 | il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif) | |
be663ab6 | 5429 | { |
be663ab6 WYG |
5430 | /* |
5431 | * inform the ucode that there is no longer an | |
5432 | * association and that no more packets should be | |
5433 | * sent | |
5434 | */ | |
c8b03958 SG |
5435 | il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
5436 | il->staging.assoc_id = 0; | |
83007196 | 5437 | il_commit_rxon(il); |
be663ab6 WYG |
5438 | } |
5439 | ||
e7392364 SG |
5440 | static void |
5441 | il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
be663ab6 | 5442 | { |
46bc8d4b | 5443 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
5444 | unsigned long flags; |
5445 | __le64 timestamp; | |
5446 | struct sk_buff *skb = ieee80211_beacon_get(hw, vif); | |
5447 | ||
5448 | if (!skb) | |
5449 | return; | |
5450 | ||
58de00a4 | 5451 | D_MAC80211("enter\n"); |
be663ab6 | 5452 | |
46bc8d4b | 5453 | lockdep_assert_held(&il->mutex); |
be663ab6 | 5454 | |
83007196 SG |
5455 | if (!il->beacon_enabled) { |
5456 | IL_ERR("update beacon with no beaconing enabled\n"); | |
be663ab6 WYG |
5457 | dev_kfree_skb(skb); |
5458 | return; | |
5459 | } | |
5460 | ||
46bc8d4b | 5461 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 | 5462 | |
46bc8d4b SG |
5463 | if (il->beacon_skb) |
5464 | dev_kfree_skb(il->beacon_skb); | |
be663ab6 | 5465 | |
46bc8d4b | 5466 | il->beacon_skb = skb; |
be663ab6 WYG |
5467 | |
5468 | timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; | |
46bc8d4b | 5469 | il->timestamp = le64_to_cpu(timestamp); |
be663ab6 | 5470 | |
58de00a4 | 5471 | D_MAC80211("leave\n"); |
46bc8d4b | 5472 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 5473 | |
46bc8d4b | 5474 | if (!il_is_ready_rf(il)) { |
58de00a4 | 5475 | D_MAC80211("leave - RF not ready\n"); |
be663ab6 WYG |
5476 | return; |
5477 | } | |
5478 | ||
c39ae9fd | 5479 | il->ops->legacy->post_associate(il); |
be663ab6 WYG |
5480 | } |
5481 | ||
e7392364 SG |
5482 | void |
5483 | il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
5484 | struct ieee80211_bss_conf *bss_conf, u32 changes) | |
be663ab6 | 5485 | { |
46bc8d4b | 5486 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
5487 | int ret; |
5488 | ||
c39ae9fd | 5489 | if (WARN_ON(!il->ops->legacy)) |
be663ab6 WYG |
5490 | return; |
5491 | ||
58de00a4 | 5492 | D_MAC80211("changes = 0x%X\n", changes); |
be663ab6 | 5493 | |
46bc8d4b | 5494 | mutex_lock(&il->mutex); |
be663ab6 | 5495 | |
46bc8d4b SG |
5496 | if (!il_is_alive(il)) { |
5497 | mutex_unlock(&il->mutex); | |
28a6e577 SG |
5498 | return; |
5499 | } | |
5500 | ||
be663ab6 WYG |
5501 | if (changes & BSS_CHANGED_QOS) { |
5502 | unsigned long flags; | |
5503 | ||
46bc8d4b | 5504 | spin_lock_irqsave(&il->lock, flags); |
8d44f2bd | 5505 | il->qos_data.qos_active = bss_conf->qos; |
83007196 | 5506 | il_update_qos(il); |
46bc8d4b | 5507 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
5508 | } |
5509 | ||
5510 | if (changes & BSS_CHANGED_BEACON_ENABLED) { | |
83007196 | 5511 | /* FIXME: can we remove beacon_enabled ? */ |
be663ab6 | 5512 | if (vif->bss_conf.enable_beacon) |
83007196 | 5513 | il->beacon_enabled = true; |
be663ab6 | 5514 | else |
83007196 | 5515 | il->beacon_enabled = false; |
be663ab6 WYG |
5516 | } |
5517 | ||
5518 | if (changes & BSS_CHANGED_BSSID) { | |
58de00a4 | 5519 | D_MAC80211("BSSID %pM\n", bss_conf->bssid); |
be663ab6 WYG |
5520 | |
5521 | /* | |
5522 | * If there is currently a HW scan going on in the | |
5523 | * background then we need to cancel it else the RXON | |
5524 | * below/in post_associate will fail. | |
5525 | */ | |
46bc8d4b | 5526 | if (il_scan_cancel_timeout(il, 100)) { |
e7392364 SG |
5527 | IL_WARN("Aborted scan still in progress after 100ms\n"); |
5528 | D_MAC80211("leaving - scan abort failed.\n"); | |
46bc8d4b | 5529 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5530 | return; |
5531 | } | |
5532 | ||
5533 | /* mac80211 only sets assoc when in STATION mode */ | |
5534 | if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) { | |
c8b03958 | 5535 | memcpy(il->staging.bssid_addr, bss_conf->bssid, |
e7392364 | 5536 | ETH_ALEN); |
be663ab6 WYG |
5537 | |
5538 | /* currently needed in a few places */ | |
46bc8d4b | 5539 | memcpy(il->bssid, bss_conf->bssid, ETH_ALEN); |
be663ab6 | 5540 | } else { |
c8b03958 | 5541 | il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
be663ab6 WYG |
5542 | } |
5543 | ||
5544 | } | |
5545 | ||
5546 | /* | |
5547 | * This needs to be after setting the BSSID in case | |
5548 | * mac80211 decides to do both changes at once because | |
5549 | * it will invoke post_associate. | |
5550 | */ | |
232913b5 | 5551 | if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON)) |
e2ebc833 | 5552 | il_beacon_update(hw, vif); |
be663ab6 WYG |
5553 | |
5554 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { | |
e7392364 | 5555 | D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble); |
be663ab6 | 5556 | if (bss_conf->use_short_preamble) |
c8b03958 | 5557 | il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
be663ab6 | 5558 | else |
c8b03958 | 5559 | il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
be663ab6 WYG |
5560 | } |
5561 | ||
5562 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { | |
e7392364 | 5563 | D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); |
232913b5 | 5564 | if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ) |
c8b03958 | 5565 | il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK; |
be663ab6 | 5566 | else |
c8b03958 | 5567 | il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK; |
be663ab6 | 5568 | if (bss_conf->use_cts_prot) |
c8b03958 | 5569 | il->staging.flags |= RXON_FLG_SELF_CTS_EN; |
be663ab6 | 5570 | else |
c8b03958 | 5571 | il->staging.flags &= ~RXON_FLG_SELF_CTS_EN; |
be663ab6 WYG |
5572 | } |
5573 | ||
5574 | if (changes & BSS_CHANGED_BASIC_RATES) { | |
5575 | /* XXX use this information | |
5576 | * | |
e2ebc833 | 5577 | * To do that, remove code from il_set_rate() and put something |
be663ab6 WYG |
5578 | * like this here: |
5579 | * | |
e7392364 | 5580 | if (A-band) |
c8b03958 | 5581 | il->staging.ofdm_basic_rates = |
e7392364 SG |
5582 | bss_conf->basic_rates; |
5583 | else | |
c8b03958 | 5584 | il->staging.ofdm_basic_rates = |
e7392364 | 5585 | bss_conf->basic_rates >> 4; |
c8b03958 | 5586 | il->staging.cck_basic_rates = |
e7392364 | 5587 | bss_conf->basic_rates & 0xF; |
be663ab6 WYG |
5588 | */ |
5589 | } | |
5590 | ||
5591 | if (changes & BSS_CHANGED_HT) { | |
46bc8d4b | 5592 | il_ht_conf(il, vif); |
be663ab6 | 5593 | |
c39ae9fd SG |
5594 | if (il->ops->hcmd->set_rxon_chain) |
5595 | il->ops->hcmd->set_rxon_chain(il); | |
be663ab6 WYG |
5596 | } |
5597 | ||
5598 | if (changes & BSS_CHANGED_ASSOC) { | |
58de00a4 | 5599 | D_MAC80211("ASSOC %d\n", bss_conf->assoc); |
be663ab6 | 5600 | if (bss_conf->assoc) { |
46bc8d4b | 5601 | il->timestamp = bss_conf->timestamp; |
be663ab6 | 5602 | |
46bc8d4b | 5603 | if (!il_is_rfkill(il)) |
c39ae9fd | 5604 | il->ops->legacy->post_associate(il); |
be663ab6 | 5605 | } else |
46bc8d4b | 5606 | il_set_no_assoc(il, vif); |
be663ab6 WYG |
5607 | } |
5608 | ||
c8b03958 | 5609 | if (changes && il_is_associated(il) && bss_conf->aid) { |
e7392364 | 5610 | D_MAC80211("Changes (%#x) while associated\n", changes); |
83007196 | 5611 | ret = il_send_rxon_assoc(il); |
be663ab6 WYG |
5612 | if (!ret) { |
5613 | /* Sync active_rxon with latest change. */ | |
c8b03958 | 5614 | memcpy((void *)&il->active, &il->staging, |
e7392364 | 5615 | sizeof(struct il_rxon_cmd)); |
be663ab6 WYG |
5616 | } |
5617 | } | |
5618 | ||
5619 | if (changes & BSS_CHANGED_BEACON_ENABLED) { | |
5620 | if (vif->bss_conf.enable_beacon) { | |
c8b03958 | 5621 | memcpy(il->staging.bssid_addr, bss_conf->bssid, |
e7392364 | 5622 | ETH_ALEN); |
46bc8d4b | 5623 | memcpy(il->bssid, bss_conf->bssid, ETH_ALEN); |
c39ae9fd | 5624 | il->ops->legacy->config_ap(il); |
be663ab6 | 5625 | } else |
46bc8d4b | 5626 | il_set_no_assoc(il, vif); |
be663ab6 WYG |
5627 | } |
5628 | ||
5629 | if (changes & BSS_CHANGED_IBSS) { | |
e7392364 | 5630 | ret = |
c39ae9fd SG |
5631 | il->ops->legacy->manage_ibss_station(il, vif, |
5632 | bss_conf->ibss_joined); | |
be663ab6 | 5633 | if (ret) |
9406f797 | 5634 | IL_ERR("failed to %s IBSS station %pM\n", |
e7392364 SG |
5635 | bss_conf->ibss_joined ? "add" : "remove", |
5636 | bss_conf->bssid); | |
be663ab6 WYG |
5637 | } |
5638 | ||
46bc8d4b | 5639 | mutex_unlock(&il->mutex); |
be663ab6 | 5640 | |
58de00a4 | 5641 | D_MAC80211("leave\n"); |
be663ab6 | 5642 | } |
e2ebc833 | 5643 | EXPORT_SYMBOL(il_mac_bss_info_changed); |
be663ab6 | 5644 | |
e7392364 SG |
5645 | irqreturn_t |
5646 | il_isr(int irq, void *data) | |
be663ab6 | 5647 | { |
46bc8d4b | 5648 | struct il_priv *il = data; |
be663ab6 WYG |
5649 | u32 inta, inta_mask; |
5650 | u32 inta_fh; | |
5651 | unsigned long flags; | |
46bc8d4b | 5652 | if (!il) |
be663ab6 WYG |
5653 | return IRQ_NONE; |
5654 | ||
46bc8d4b | 5655 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
5656 | |
5657 | /* Disable (but don't clear!) interrupts here to avoid | |
5658 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
5659 | * If we have something to service, the tasklet will re-enable ints. | |
5660 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
e7392364 | 5661 | inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */ |
841b2cca | 5662 | _il_wr(il, CSR_INT_MASK, 0x00000000); |
be663ab6 WYG |
5663 | |
5664 | /* Discover which interrupts are active/pending */ | |
841b2cca SG |
5665 | inta = _il_rd(il, CSR_INT); |
5666 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); | |
be663ab6 WYG |
5667 | |
5668 | /* Ignore interrupt if there's nothing in NIC to service. | |
5669 | * This may be due to IRQ shared with another device, | |
5670 | * or due to sporadic interrupts thrown from our NIC. */ | |
5671 | if (!inta && !inta_fh) { | |
e7392364 | 5672 | D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); |
be663ab6 WYG |
5673 | goto none; |
5674 | } | |
5675 | ||
232913b5 | 5676 | if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) { |
be663ab6 WYG |
5677 | /* Hardware disappeared. It might have already raised |
5678 | * an interrupt */ | |
9406f797 | 5679 | IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta); |
be663ab6 WYG |
5680 | goto unplugged; |
5681 | } | |
5682 | ||
e7392364 SG |
5683 | D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask, |
5684 | inta_fh); | |
be663ab6 WYG |
5685 | |
5686 | inta &= ~CSR_INT_BIT_SCD; | |
5687 | ||
e2ebc833 | 5688 | /* il_irq_tasklet() will service interrupts and re-enable them */ |
be663ab6 | 5689 | if (likely(inta || inta_fh)) |
46bc8d4b | 5690 | tasklet_schedule(&il->irq_tasklet); |
be663ab6 WYG |
5691 | |
5692 | unplugged: | |
46bc8d4b | 5693 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
5694 | return IRQ_HANDLED; |
5695 | ||
5696 | none: | |
5697 | /* re-enable interrupts here since we don't have anything to service. */ | |
93fd74e3 | 5698 | /* only Re-enable if disabled by irq */ |
a6766ccd | 5699 | if (test_bit(S_INT_ENABLED, &il->status)) |
46bc8d4b SG |
5700 | il_enable_interrupts(il); |
5701 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 WYG |
5702 | return IRQ_NONE; |
5703 | } | |
e2ebc833 | 5704 | EXPORT_SYMBOL(il_isr); |
be663ab6 WYG |
5705 | |
5706 | /* | |
e2ebc833 | 5707 | * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this |
be663ab6 WYG |
5708 | * function. |
5709 | */ | |
e7392364 SG |
5710 | void |
5711 | il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info, | |
1722f8e1 | 5712 | __le16 fc, __le32 *tx_flags) |
be663ab6 WYG |
5713 | { |
5714 | if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
5715 | *tx_flags |= TX_CMD_FLG_RTS_MSK; | |
5716 | *tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
5717 | *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
5718 | ||
5719 | if (!ieee80211_is_mgmt(fc)) | |
5720 | return; | |
5721 | ||
5722 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
5723 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
5724 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
5725 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
5726 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
5727 | *tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
5728 | *tx_flags |= TX_CMD_FLG_CTS_MSK; | |
5729 | break; | |
5730 | } | |
e7392364 SG |
5731 | } else if (info->control.rates[0]. |
5732 | flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
be663ab6 WYG |
5733 | *tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
5734 | *tx_flags |= TX_CMD_FLG_CTS_MSK; | |
5735 | *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
5736 | } | |
5737 | } | |
e2ebc833 | 5738 | EXPORT_SYMBOL(il_tx_cmd_protection); |