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iwlegacy: merge il_lib_ops into il_ops
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.h
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
e94a4099 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
be663ab6 4 *
e94a4099
SG		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
be663ab6
WYG		 7 * published by the Free Software Foundation.
8 *
e94a4099
SG		 9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
be663ab6 13 *
e94a4099
SG		 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
be663ab6 17 *
e94a4099
SG		 18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
be663ab6
WYG		 20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
e94a4099
SG		 25 *****************************************************************************/
26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
e7392364 30#include <linux/pci.h> /* for struct pci_device_id */
e94a4099
SG		 31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
17d4eca6 34#include <linux/io.h>
47ef694d 35#include <net/mac80211.h>
e94a4099
SG		 36#include <net/ieee80211_radiotap.h>
37
99412002 38#include "commands.h"
e94a4099 39#include "csr.h"
e8c39d4e 40#include "prph.h"
e94a4099
SG		 41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
f02579e3
SG		 46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
e94a4099
SG		 50#define RX_QUEUE_SIZE 256
51#define RX_QUEUE_MASK 255
52#define RX_QUEUE_SIZE_LOG 8
53
54/*
55 * RX related structures and functions
56 */
57#define RX_FREE_BUFFERS 64
58#define RX_LOW_WATERMARK 8
59
60#define U32_PAD(n) ((4-(n))&0x3)
61
62/* CT-KILL constants */
e7392364 63#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
e94a4099
SG		 64
65/* Default noise level to report when noise measurement is not available.
66 * This may be because we're:
67 * 1) Not associated (4965, no beacon stats being sent to driver)
68 * 2) Scanning (noise measurement does not apply to associated channel)
69 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
70 * Use default noise value of -127 ... this is below the range of measurable
71 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
72 * Also, -127 works better than 0 when averaging frames with/without
73 * noise info (e.g. averaging might be done in app); measured dBm values are
74 * always negative ... using a negative value as the default keeps all
75 * averages within an s8's (used in some apps) range of negative values. */
76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
77
78/*
79 * RTS threshold here is total size [2347] minus 4 FCS bytes
80 * Per spec:
81 * a value of 0 means RTS on all data/management packets
82 * a value > max MSDU size means no RTS
83 * else RTS for data/management frames where MPDU is larger
84 * than RTS value.
85 */
86#define DEFAULT_RTS_THRESHOLD 2347U
87#define MIN_RTS_THRESHOLD 0U
88#define MAX_RTS_THRESHOLD 2347U
89#define MAX_MSDU_SIZE 2304U
90#define MAX_MPDU_SIZE 2346U
91#define DEFAULT_BEACON_INTERVAL 100U
92#define DEFAULT_SHORT_RETRY_LIMIT 7U
93#define DEFAULT_LONG_RETRY_LIMIT 4U
94
95struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99};
100
101#define rxb_addr(r) page_address(r->page)
102
103/* defined below */
104struct il_device_cmd;
105
106struct il_cmd_meta {
107 /* only for SYNC commands, iff the reply skb is wanted */
108 struct il_host_cmd *source;
109 /*
110 * only for ASYNC commands
111 * (which is somewhat stupid -- look at common.c for instance
112 * which duplicates a bunch of code because the callback isn't
113 * invoked for SYNC commands, if it were and its result passed
114 * through it would be simpler...)
115 */
1722f8e1
SG		 116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
e94a4099
SG		 118
119 /* The CMD_SIZE_HUGE flag bit indicates that the command
120 * structure is stored at the end of the shared queue memory. */
121 u32 flags;
122
e7392364
SG		 123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
e94a4099
SG		 125};
126
127/*
128 * Generic queue structure
129 *
130 * Contains common data for Rx and Tx queues
131 */
132struct il_queue {
e7392364
SG		 133 int n_bd; /* number of BDs in this queue */
134 int write_ptr; /* 1-st empty entry (idx) host_w */
135 int read_ptr; /* last used entry (idx) host_r */
e94a4099 136 /* use for monitoring and recovering the stuck queue */
e7392364
SG		 137 dma_addr_t dma_addr; /* physical addr for BD's */
138 int n_win; /* safe queue win */
e94a4099 139 u32 id;
e7392364
SG		 140 int low_mark; /* low watermark, resume queue if free
141 * space more than this */
142 int high_mark; /* high watermark, stop queue if free
143 * space less than this */
e94a4099
SG		 144};
145
e94a4099
SG		 146/**
147 * struct il_tx_queue - Tx Queue for DMA
148 * @q: generic Rx/Tx queue descriptor
149 * @bd: base of circular buffer of TFDs
150 * @cmd: array of command/TX buffer pointers
151 * @meta: array of meta data for each command/tx buffer
152 * @dma_addr_cmd: physical address of cmd/tx buffer array
00ea99e1 153 * @skbs: array of per-TFD socket buffer pointers
e94a4099
SG		 154 * @time_stamp: time (in jiffies) of last read_ptr change
155 * @need_update: indicates need to update read/write idx
156 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
157 *
158 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
159 * descriptors) and required locking structures.
160 */
161#define TFD_TX_CMD_SLOTS 256
162#define TFD_CMD_SLOTS 32
163
164struct il_tx_queue {
165 struct il_queue q;
166 void *tfds;
167 struct il_device_cmd **cmd;
168 struct il_cmd_meta *meta;
00ea99e1 169 struct sk_buff **skbs;
e94a4099
SG		 170 unsigned long time_stamp;
171 u8 need_update;
172 u8 sched_retry;
173 u8 active;
174 u8 swq_id;
175};
176
47ef694d
SG		 177/*
178 * EEPROM access time values:
179 *
180 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
181 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
182 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
183 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
184 */
e7392364 185#define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
47ef694d 186
e7392364
SG		 187#define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
188#define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
47ef694d
SG		 189
190/*
191 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
192 *
193 * IBSS and/or AP operation is allowed *only* on those channels with
194 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
195 * RADAR detection is not supported by the 4965 driver, but is a
196 * requirement for establishing a new network for legal operation on channels
197 * requiring RADAR detection or restricting ACTIVE scanning.
198 *
199 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
200 * It only indicates that 20 MHz channel use is supported; HT40 channel
201 * usage is indicated by a separate set of regulatory flags for each
202 * HT40 channel pair.
203 *
204 * NOTE: Using a channel inappropriately will result in a uCode error!
205 */
206#define IL_NUM_TX_CALIB_GROUPS 5
207enum {
208 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
e7392364 209 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
47ef694d
SG		 210 /* Bit 2 Reserved */
211 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
212 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
e7392364 213 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
47ef694d
SG		 214 /* Bit 6 Reserved (was Narrow Channel) */
215 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
216};
217
218/* SKU Capabilities */
219/* 3945 only */
220#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
221#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
222
223/* *regulatory* channel data format in eeprom, one for each channel.
224 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
225struct il_eeprom_channel {
226 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
227 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
228} __packed;
229
230/* 3945 Specific */
231#define EEPROM_3945_EEPROM_VERSION (0x2f)
232
233/* 4965 has two radio transmitters (and 3 radio receivers) */
234#define EEPROM_TX_POWER_TX_CHAINS (2)
235
236/* 4965 has room for up to 8 sets of txpower calibration data */
237#define EEPROM_TX_POWER_BANDS (8)
238
239/* 4965 factory calibration measures txpower gain settings for
240 * each of 3 target output levels */
241#define EEPROM_TX_POWER_MEASUREMENTS (3)
242
243/* 4965 Specific */
244/* 4965 driver does not work with txpower calibration version < 5 */
245#define EEPROM_4965_TX_POWER_VERSION (5)
246#define EEPROM_4965_EEPROM_VERSION (0x2f)
e7392364
SG		 247#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
248#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
249#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
250#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
47ef694d
SG		 251
252/* 2.4 GHz */
253extern const u8 il_eeprom_band_1[14];
254
255/*
256 * factory calibration data for one txpower level, on one channel,
257 * measured on one of the 2 tx chains (radio transmitter and associated
258 * antenna). EEPROM contains:
259 *
260 * 1) Temperature (degrees Celsius) of device when measurement was made.
261 *
262 * 2) Gain table idx used to achieve the target measurement power.
263 * This refers to the "well-known" gain tables (see 4965.h).
264 *
265 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
266 *
267 * 4) RF power amplifier detector level measurement (not used).
268 */
269struct il_eeprom_calib_measure {
270 u8 temperature; /* Device temperature (Celsius) */
271 u8 gain_idx; /* Index into gain table */
272 u8 actual_pow; /* Measured RF output power, half-dBm */
273 s8 pa_det; /* Power amp detector level (not used) */
274} __packed;
275
47ef694d
SG		 276/*
277 * measurement set for one channel. EEPROM contains:
278 *
279 * 1) Channel number measured
280 *
281 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
282 * (a.k.a. "tx chains") (6 measurements altogether)
283 */
284struct il_eeprom_calib_ch_info {
285 u8 ch_num;
286 struct il_eeprom_calib_measure
e7392364
SG		 287 measurements[EEPROM_TX_POWER_TX_CHAINS]
288 [EEPROM_TX_POWER_MEASUREMENTS];
47ef694d
SG		 289} __packed;
290
291/*
292 * txpower subband info.
293 *
294 * For each frequency subband, EEPROM contains the following:
295 *
296 * 1) First and last channels within range of the subband. "0" values
297 * indicate that this sample set is not being used.
298 *
299 * 2) Sample measurement sets for 2 channels close to the range endpoints.
300 */
301struct il_eeprom_calib_subband_info {
e7392364
SG		 302 u8 ch_from; /* channel number of lowest channel in subband */
303 u8 ch_to; /* channel number of highest channel in subband */
47ef694d
SG		 304 struct il_eeprom_calib_ch_info ch1;
305 struct il_eeprom_calib_ch_info ch2;
306} __packed;
307
47ef694d
SG		 308/*
309 * txpower calibration info. EEPROM contains:
310 *
311 * 1) Factory-measured saturation power levels (maximum levels at which
312 * tx power amplifier can output a signal without too much distortion).
313 * There is one level for 2.4 GHz band and one for 5 GHz band. These
314 * values apply to all channels within each of the bands.
315 *
316 * 2) Factory-measured power supply voltage level. This is assumed to be
317 * constant (i.e. same value applies to all channels/bands) while the
318 * factory measurements are being made.
319 *
320 * 3) Up to 8 sets of factory-measured txpower calibration values.
321 * These are for different frequency ranges, since txpower gain
322 * characteristics of the analog radio circuitry vary with frequency.
323 *
324 * Not all sets need to be filled with data;
325 * struct il_eeprom_calib_subband_info contains range of channels
326 * (0 if unused) for each set of data.
327 */
328struct il_eeprom_calib_info {
329 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
330 u8 saturation_power52; /* half-dBm */
331 __le16 voltage; /* signed */
e7392364 332 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
47ef694d
SG		 333} __packed;
334
47ef694d
SG		 335/* General */
336#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
337#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
338#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
339#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
340#define EEPROM_VERSION (2*0x44) /* 2 bytes */
341#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
342#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
343#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
344#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
345#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
346
347/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
e7392364
SG		 348#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
349#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
350#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
351#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
352#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
353#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
47ef694d
SG		 354
355#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
356#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
357
358/*
359 * Per-channel regulatory data.
360 *
361 * Each channel that *might* be supported by iwl has a fixed location
362 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
363 * txpower (MSB).
364 *
365 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
366 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
367 *
368 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
369 */
e7392364 370#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
47ef694d
SG		 371#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
372#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
373
374/*
375 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
376 * 5.0 GHz channels 7, 8, 11, 12, 16
377 * (4915-5080MHz) (none of these is ever supported)
378 */
379#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
380#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
381
382/*
383 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
384 * (5170-5320MHz)
385 */
386#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
387#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
388
389/*
390 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
391 * (5500-5700MHz)
392 */
393#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
394#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
395
396/*
397 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
398 * (5725-5825MHz)
399 */
400#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
401#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
402
403/*
404 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
405 *
406 * The channel listed is the center of the lower 20 MHz half of the channel.
407 * The overall center frequency is actually 2 channels (10 MHz) above that,
408 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
409 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
410 * and the overall HT40 channel width centers on channel 3.
411 *
412 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
413 * control channel to which to tune. RXON also specifies whether the
414 * control channel is the upper or lower half of a HT40 channel.
415 *
416 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
417 */
418#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
419
420/*
421 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
422 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
423 */
424#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
425
426#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
427
47ef694d
SG		 428int il_eeprom_init(struct il_priv *il);
429void il_eeprom_free(struct il_priv *il);
e7392364 430const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
47ef694d
SG		 431u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
432int il_init_channel_map(struct il_priv *il);
433void il_free_channel_map(struct il_priv *il);
e7392364
SG		 434const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
435 enum ieee80211_band band,
436 u16 channel);
47ef694d 437
e94a4099
SG		 438#define IL_NUM_SCAN_RATES (2)
439
440struct il4965_channel_tgd_info {
441 u8 type;
442 s8 max_power;
443};
444
445struct il4965_channel_tgh_info {
446 s64 last_radar_time;
447};
448
449#define IL4965_MAX_RATE (33)
450
451struct il3945_clip_group {
452 /* maximum power level to prevent clipping for each rate, derived by
453 * us from this band's saturation power in EEPROM */
454 const s8 clip_powers[IL_MAX_RATES];
455};
456
457/* current Tx power values to use, one for each rate for each channel.
458 * requested power is limited by:
459 * -- regulatory EEPROM limits for this channel
460 * -- hardware capabilities (clip-powers)
461 * -- spectrum management
462 * -- user preference (e.g. iwconfig)
463 * when requested power is set, base power idx must also be set. */
464struct il3945_channel_power_info {
465 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
466 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
467 s8 base_power_idx; /* gain idx for power at factory temp. */
468 s8 requested_power; /* power (dBm) requested for this chnl/rate */
469};
470
471/* current scan Tx power values to use, one for each scan rate for each
472 * channel. */
473struct il3945_scan_power_info {
474 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
475 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
476 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
477};
478
479/*
480 * One for each channel, holds all channel setup data
481 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
482 * with one another!
483 */
484struct il_channel_info {
485 struct il4965_channel_tgd_info tgd;
486 struct il4965_channel_tgh_info tgh;
487 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
488 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
489 * HT40 channel */
490
e7392364
SG		 491 u8 channel; /* channel number */
492 u8 flags; /* flags copied from EEPROM */
493 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
494 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
495 s8 min_power; /* always 0 */
496 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
e94a4099 497
e7392364
SG		 498 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
499 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
e94a4099
SG		 500 enum ieee80211_band band;
501
502 /* HT40 channel info */
503 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
504 u8 ht40_flags; /* flags copied from EEPROM */
e7392364 505 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
e94a4099
SG		 506
507 /* Radio/DSP gain settings for each "normal" data Tx rate.
508 * These include, in addition to RF and DSP gain, a few fields for
509 * remembering/modifying gain settings (idxes). */
510 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
511
512 /* Radio/DSP gain settings for each scan rate, for directed scans. */
513 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
514};
515
516#define IL_TX_FIFO_BK 0 /* shared */
517#define IL_TX_FIFO_BE 1
518#define IL_TX_FIFO_VI 2 /* shared */
519#define IL_TX_FIFO_VO 3
520#define IL_TX_FIFO_UNUSED -1
521
522/* Minimum number of queues. MAX_NUM is defined in hw specific files.
523 * Set the minimum to accommodate the 4 standard TX queues, 1 command
524 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
525#define IL_MIN_NUM_QUEUES 10
526
527#define IL_DEFAULT_CMD_QUEUE_NUM 4
528
529#define IEEE80211_DATA_LEN 2304
530#define IEEE80211_4ADDR_LEN 30
531#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
532#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
533
534struct il_frame {
535 union {
536 struct ieee80211_hdr frame;
537 struct il_tx_beacon_cmd beacon;
538 u8 raw[IEEE80211_FRAME_LEN];
539 u8 cmd[360];
540 } u;
541 struct list_head list;
542};
543
544#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
545#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
546#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
547
548enum {
549 CMD_SYNC = 0,
550 CMD_SIZE_NORMAL = 0,
551 CMD_NO_SKB = 0,
552 CMD_SIZE_HUGE = (1 << 0),
553 CMD_ASYNC = (1 << 1),
554 CMD_WANT_SKB = (1 << 2),
555 CMD_MAPPED = (1 << 3),
556};
557
558#define DEF_CMD_PAYLOAD_SIZE 320
559
560/**
561 * struct il_device_cmd
562 *
563 * For allocation of the command and tx queues, this establishes the overall
564 * size of the largest command we send to uCode, except for a scan command
565 * (which is relatively huge; space is allocated separately).
566 */
567struct il_device_cmd {
568 struct il_cmd_header hdr; /* uCode API */
569 union {
570 u32 flags;
571 u8 val8;
572 u16 val16;
573 u32 val32;
574 struct il_tx_cmd tx;
575 u8 payload[DEF_CMD_PAYLOAD_SIZE];
576 } __packed cmd;
577} __packed;
578
579#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
580
e94a4099
SG		 581struct il_host_cmd {
582 const void *data;
583 unsigned long reply_page;
1722f8e1
SG		 584 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
585 struct il_rx_pkt *pkt);
e94a4099
SG		 586 u32 flags;
587 u16 len;
588 u8 id;
589};
590
591#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
592#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
593#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
594
595/**
596 * struct il_rx_queue - Rx queue
597 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
598 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
599 * @read: Shared idx to newest available Rx buffer
600 * @write: Shared idx to oldest written Rx packet
601 * @free_count: Number of pre-allocated buffers in rx_free
602 * @rx_free: list of free SKBs for use
603 * @rx_used: List of Rx buffers with no SKB
604 * @need_update: flag to indicate we need to update read/write idx
605 * @rb_stts: driver's pointer to receive buffer status
606 * @rb_stts_dma: bus address of receive buffer status
607 *
608 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
609 */
610struct il_rx_queue {
611 __le32 *bd;
612 dma_addr_t bd_dma;
613 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
614 struct il_rx_buf *queue[RX_QUEUE_SIZE];
615 u32 read;
616 u32 write;
617 u32 free_count;
618 u32 write_actual;
619 struct list_head rx_free;
620 struct list_head rx_used;
621 int need_update;
622 struct il_rb_status *rb_stts;
623 dma_addr_t rb_stts_dma;
624 spinlock_t lock;
625};
626
627#define IL_SUPPORTED_RATES_IE_LEN 8
628
629#define MAX_TID_COUNT 9
630
631#define IL_INVALID_RATE 0xFF
632#define IL_INVALID_VALUE -1
633
634/**
635 * struct il_ht_agg -- aggregation status while waiting for block-ack
636 * @txq_id: Tx queue used for Tx attempt
637 * @frame_count: # frames attempted by Tx command
638 * @wait_for_ba: Expect block-ack before next Tx reply
639 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
640 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
641 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
642 * @rate_n_flags: Rate at which Tx was attempted
643 *
644 * If C_TX indicates that aggregation was attempted, driver must wait
645 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
646 * until block ack arrives.
647 */
648struct il_ht_agg {
649 u16 txq_id;
650 u16 frame_count;
651 u16 wait_for_ba;
652 u16 start_idx;
653 u64 bitmap;
654 u32 rate_n_flags;
655#define IL_AGG_OFF 0
656#define IL_AGG_ON 1
657#define IL_EMPTYING_HW_QUEUE_ADDBA 2
658#define IL_EMPTYING_HW_QUEUE_DELBA 3
659 u8 state;
660};
661
e94a4099 662struct il_tid_data {
e7392364 663 u16 seq_number; /* 4965 only */
e94a4099
SG		 664 u16 tfds_in_queue;
665 struct il_ht_agg agg;
666};
667
668struct il_hw_key {
669 u32 cipher;
670 int keylen;
671 u8 keyidx;
672 u8 key[32];
673};
674
675union il_ht_rate_supp {
676 u16 rates;
677 struct {
678 u8 siso_rate;
679 u8 mimo_rate;
680 };
681};
682
683#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
684#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
685#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
686#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
687#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
688#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
689#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
690
691/*
692 * Maximal MPDU density for TX aggregation
693 * 4 - 2us density
694 * 5 - 4us density
695 * 6 - 8us density
696 * 7 - 16us density
697 */
698#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
699#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
700#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
701#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
702#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
703#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
704#define CFG_HT_MPDU_DENSITY_MIN (0x1)
705
706struct il_ht_config {
707 bool single_chain_sufficient;
e7392364 708 enum ieee80211_smps_mode smps; /* current smps mode */
e94a4099
SG		 709};
710
711/* QoS structures */
712struct il_qos_info {
713 int qos_active;
714 struct il_qosparam_cmd def_qos_parm;
715};
716
717/*
718 * Structure should be accessed with sta_lock held. When station addition
719 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
720 * the commands (il_addsta_cmd and il_link_quality_cmd) without
721 * sta_lock held.
722 */
723struct il_station_entry {
724 struct il_addsta_cmd sta;
725 struct il_tid_data tid[MAX_TID_COUNT];
6aa0c254 726 u8 used;
e94a4099
SG		 727 struct il_hw_key keyinfo;
728 struct il_link_quality_cmd *lq;
729};
730
731struct il_station_priv_common {
e94a4099
SG		 732 u8 sta_id;
733};
734
e94a4099
SG		 735/**
736 * struct il_vif_priv - driver's ilate per-interface information
737 *
738 * When mac80211 allocates a virtual interface, it can allocate
739 * space for us to put data into.
740 */
741struct il_vif_priv {
e94a4099
SG		 742 u8 ibss_bssid_sta_id;
743};
744
745/* one for each uCode image (inst/data, boot/init/runtime) */
746struct fw_desc {
747 void *v_addr; /* access by driver */
748 dma_addr_t p_addr; /* access by card's busmaster DMA */
749 u32 len; /* bytes */
750};
751
752/* uCode file layout */
753struct il_ucode_header {
e7392364 754 __le32 ver; /* major/minor/API/serial */
e94a4099
SG		 755 struct {
756 __le32 inst_size; /* bytes of runtime code */
757 __le32 data_size; /* bytes of runtime data */
758 __le32 init_size; /* bytes of init code */
759 __le32 init_data_size; /* bytes of init data */
760 __le32 boot_size; /* bytes of bootstrap code */
e7392364 761 u8 data[0]; /* in same order as sizes */
e94a4099
SG		 762 } v1;
763};
764
765struct il4965_ibss_seq {
766 u8 mac[ETH_ALEN];
767 u16 seq_num;
768 u16 frag_num;
769 unsigned long packet_time;
770 struct list_head list;
771};
772
773struct il_sensitivity_ranges {
774 u16 min_nrg_cck;
775 u16 max_nrg_cck;
776
777 u16 nrg_th_cck;
778 u16 nrg_th_ofdm;
779
780 u16 auto_corr_min_ofdm;
781 u16 auto_corr_min_ofdm_mrc;
782 u16 auto_corr_min_ofdm_x1;
783 u16 auto_corr_min_ofdm_mrc_x1;
784
785 u16 auto_corr_max_ofdm;
786 u16 auto_corr_max_ofdm_mrc;
787 u16 auto_corr_max_ofdm_x1;
788 u16 auto_corr_max_ofdm_mrc_x1;
789
790 u16 auto_corr_max_cck;
791 u16 auto_corr_max_cck_mrc;
792 u16 auto_corr_min_cck;
793 u16 auto_corr_min_cck_mrc;
794
795 u16 barker_corr_th_min;
796 u16 barker_corr_th_min_mrc;
797 u16 nrg_th_cca;
798};
799
e94a4099
SG		 800#define KELVIN_TO_CELSIUS(x) ((x)-273)
801#define CELSIUS_TO_KELVIN(x) ((x)+273)
802
e94a4099
SG		 803/**
804 * struct il_hw_params
b16db50a 805 * @bcast_id: f/w broadcast station ID
e94a4099
SG		 806 * @max_txq_num: Max # Tx queues supported
807 * @dma_chnl_num: Number of Tx DMA/FIFO channels
808 * @scd_bc_tbls_size: size of scheduler byte count tables
809 * @tfd_size: TFD size
810 * @tx/rx_chains_num: Number of TX/RX chains
811 * @valid_tx/rx_ant: usable antennas
812 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
813 * @max_rxq_log: Log-base-2 of max_rxq_size
814 * @rx_page_order: Rx buffer page order
815 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
816 * @max_stations:
817 * @ht40_channel: is 40MHz width possible in band 2.4
818 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
819 * @sw_crypto: 0 for hw, 1 for sw
820 * @max_xxx_size: for ucode uses
821 * @ct_kill_threshold: temperature threshold
822 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
823 * @struct il_sensitivity_ranges: range of sensitivity values
824 */
825struct il_hw_params {
b16db50a 826 u8 bcast_id;
e94a4099
SG		 827 u8 max_txq_num;
828 u8 dma_chnl_num;
829 u16 scd_bc_tbls_size;
830 u32 tfd_size;
e7392364
SG		 831 u8 tx_chains_num;
832 u8 rx_chains_num;
833 u8 valid_tx_ant;
834 u8 valid_rx_ant;
e94a4099
SG		 835 u16 max_rxq_size;
836 u16 max_rxq_log;
837 u32 rx_page_order;
838 u32 rx_wrt_ptr_reg;
e7392364
SG		 839 u8 max_stations;
840 u8 ht40_channel;
841 u8 max_beacon_itrvl; /* in 1024 ms */
e94a4099
SG		 842 u32 max_inst_size;
843 u32 max_data_size;
844 u32 max_bsm_size;
e7392364 845 u32 ct_kill_threshold; /* value in hw-dependent units */
e94a4099
SG		 846 u16 beacon_time_tsf_bits;
847 const struct il_sensitivity_ranges *sens;
848};
849
e94a4099
SG		 850/******************************************************************************
851 *
852 * Functions implemented in core module which are forward declared here
853 * for use by iwl-[4-5].c
854 *
855 * NOTE: The implementation of these functions are not hardware specific
856 * which is why they are in the core module files.
857 *
858 * Naming convention --
859 * il_ <-- Is part of iwlwifi
860 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
861 * il4965_bg_ <-- Called from work queue context
862 * il4965_mac_ <-- mac80211 callback
863 *
864 ****************************************************************************/
865extern void il4965_update_chain_flags(struct il_priv *il);
866extern const u8 il_bcast_addr[ETH_ALEN];
867extern int il_queue_space(const struct il_queue *q);
e7392364
SG		 868static inline int
869il_queue_used(const struct il_queue *q, int i)
e94a4099 870{
e7392364
SG		 871 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
872 i < q->write_ptr) : !(i <
873 q->read_ptr
874 && i >=
875 q->
876 write_ptr);
e94a4099
SG		 877}
878
e7392364
SG		 879static inline u8
880il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
e94a4099
SG		 881{
882 /*
883 * This is for init calibration result and scan command which
884 * required buffer > TFD_MAX_PAYLOAD_SIZE,
885 * the big buffer at end of command array
886 */
887 if (is_huge)
888 return q->n_win; /* must be power of 2 */
889
890 /* Otherwise, use normal size buffers */
891 return idx & (q->n_win - 1);
892}
893
e94a4099
SG		 894struct il_dma_ptr {
895 dma_addr_t dma;
896 void *addr;
897 size_t size;
898};
899
900#define IL_OPERATION_MODE_AUTO 0
901#define IL_OPERATION_MODE_HT_ONLY 1
902#define IL_OPERATION_MODE_MIXED 2
903#define IL_OPERATION_MODE_20MHZ 3
904
905#define IL_TX_CRC_SIZE 4
906#define IL_TX_DELIMITER_SIZE 4
907
908#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
909
910/* Sensitivity and chain noise calibration */
911#define INITIALIZATION_VALUE 0xFFFF
912#define IL4965_CAL_NUM_BEACONS 20
913#define IL_CAL_NUM_BEACONS 16
914#define MAXIMUM_ALLOWED_PATHLOSS 15
915
916#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
917
918#define MAX_FA_OFDM 50
919#define MIN_FA_OFDM 5
920#define MAX_FA_CCK 50
921#define MIN_FA_CCK 5
922
923#define AUTO_CORR_STEP_OFDM 1
924
925#define AUTO_CORR_STEP_CCK 3
926#define AUTO_CORR_MAX_TH_CCK 160
927
928#define NRG_DIFF 2
929#define NRG_STEP_CCK 2
930#define NRG_MARGIN 8
931#define MAX_NUMBER_CCK_NO_FA 100
932
933#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
934
935#define CHAIN_A 0
936#define CHAIN_B 1
937#define CHAIN_C 2
938#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
939#define ALL_BAND_FILTER 0xFF00
940#define IN_BAND_FILTER 0xFF
941#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
942
943#define NRG_NUM_PREV_STAT_L 20
944#define NUM_RX_CHAINS 3
945
946enum il4965_false_alarm_state {
947 IL_FA_TOO_MANY = 0,
948 IL_FA_TOO_FEW = 1,
949 IL_FA_GOOD_RANGE = 2,
950};
951
952enum il4965_chain_noise_state {
e7392364 953 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
e94a4099
SG		 954 IL_CHAIN_NOISE_ACCUMULATE,
955 IL_CHAIN_NOISE_CALIBRATED,
956 IL_CHAIN_NOISE_DONE,
957};
958
959enum il4965_calib_enabled_state {
e7392364 960 IL_CALIB_DISABLED = 0, /* must be 0 */
e94a4099
SG		 961 IL_CALIB_ENABLED = 1,
962};
963
964/*
965 * enum il_calib
966 * defines the order in which results of initial calibrations
967 * should be sent to the runtime uCode
968 */
969enum il_calib {
970 IL_CALIB_MAX,
971};
972
973/* Opaque calibration results */
974struct il_calib_result {
975 void *buf;
976 size_t buf_len;
977};
978
979enum ucode_type {
980 UCODE_NONE = 0,
981 UCODE_INIT,
982 UCODE_RT
983};
984
985/* Sensitivity calib data */
986struct il_sensitivity_data {
987 u32 auto_corr_ofdm;
988 u32 auto_corr_ofdm_mrc;
989 u32 auto_corr_ofdm_x1;
990 u32 auto_corr_ofdm_mrc_x1;
991 u32 auto_corr_cck;
992 u32 auto_corr_cck_mrc;
993
994 u32 last_bad_plcp_cnt_ofdm;
995 u32 last_fa_cnt_ofdm;
996 u32 last_bad_plcp_cnt_cck;
997 u32 last_fa_cnt_cck;
998
999 u32 nrg_curr_state;
1000 u32 nrg_prev_state;
1001 u32 nrg_value[10];
e7392364 1002 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
e94a4099
SG		 1003 u32 nrg_silence_ref;
1004 u32 nrg_energy_idx;
1005 u32 nrg_silence_idx;
1006 u32 nrg_th_cck;
1007 s32 nrg_auto_corr_silence_diff;
1008 u32 num_in_cck_no_fa;
1009 u32 nrg_th_ofdm;
1010
1011 u16 barker_corr_th_min;
1012 u16 barker_corr_th_min_mrc;
1013 u16 nrg_th_cca;
1014};
1015
1016/* Chain noise (differential Rx gain) calib data */
1017struct il_chain_noise_data {
1018 u32 active_chains;
1019 u32 chain_noise_a;
1020 u32 chain_noise_b;
1021 u32 chain_noise_c;
1022 u32 chain_signal_a;
1023 u32 chain_signal_b;
1024 u32 chain_signal_c;
1025 u16 beacon_count;
1026 u8 disconn_array[NUM_RX_CHAINS];
1027 u8 delta_gain_code[NUM_RX_CHAINS];
1028 u8 radio_write;
1029 u8 state;
1030};
1031
e7392364 1032#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
e94a4099
SG		 1033#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1034
1035#define IL_TRAFFIC_ENTRIES (256)
1036#define IL_TRAFFIC_ENTRY_SIZE (64)
1037
1038enum {
1039 MEASUREMENT_READY = (1 << 0),
1040 MEASUREMENT_ACTIVE = (1 << 1),
1041};
1042
1043/* interrupt stats */
1044struct isr_stats {
1045 u32 hw;
1046 u32 sw;
1047 u32 err_code;
1048 u32 sch;
1049 u32 alive;
1050 u32 rfkill;
1051 u32 ctkill;
1052 u32 wakeup;
1053 u32 rx;
1054 u32 handlers[IL_CN_MAX];
1055 u32 tx;
1056 u32 unhandled;
1057};
1058
1059/* management stats */
1060enum il_mgmt_stats {
1061 MANAGEMENT_ASSOC_REQ = 0,
1062 MANAGEMENT_ASSOC_RESP,
1063 MANAGEMENT_REASSOC_REQ,
1064 MANAGEMENT_REASSOC_RESP,
1065 MANAGEMENT_PROBE_REQ,
1066 MANAGEMENT_PROBE_RESP,
1067 MANAGEMENT_BEACON,
1068 MANAGEMENT_ATIM,
1069 MANAGEMENT_DISASSOC,
1070 MANAGEMENT_AUTH,
1071 MANAGEMENT_DEAUTH,
1072 MANAGEMENT_ACTION,
1073 MANAGEMENT_MAX,
1074};
1075/* control stats */
1076enum il_ctrl_stats {
e7392364 1077 CONTROL_BACK_REQ = 0,
e94a4099
SG		 1078 CONTROL_BACK,
1079 CONTROL_PSPOLL,
1080 CONTROL_RTS,
1081 CONTROL_CTS,
1082 CONTROL_ACK,
1083 CONTROL_CFEND,
1084 CONTROL_CFENDACK,
1085 CONTROL_MAX,
1086};
1087
1088struct traffic_stats {
1089#ifdef CONFIG_IWLEGACY_DEBUGFS
1090 u32 mgmt[MANAGEMENT_MAX];
1091 u32 ctrl[CONTROL_MAX];
1092 u32 data_cnt;
1093 u64 data_bytes;
1094#endif
1095};
1096
1097/*
1098 * host interrupt timeout value
1099 * used with setting interrupt coalescing timer
1100 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1101 *
1102 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1103 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1104 */
1105#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1106#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1107#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1108#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1109#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1110#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1111
1112#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1113
1114/* TX queue watchdog timeouts in mSecs */
1115#define IL_DEF_WD_TIMEOUT (2000)
1116#define IL_LONG_WD_TIMEOUT (10000)
1117#define IL_MAX_WD_TIMEOUT (120000)
1118
1119struct il_force_reset {
1120 int reset_request_count;
1121 int reset_success_count;
1122 int reset_reject_count;
1123 unsigned long reset_duration;
1124 unsigned long last_force_reset_jiffies;
1125};
1126
1127/* extend beacon time format bit shifting */
1128/*
1129 * for _3945 devices
1130 * bits 31:24 - extended
1131 * bits 23:0 - interval
1132 */
1133#define IL3945_EXT_BEACON_TIME_POS 24
1134/*
1135 * for _4965 devices
1136 * bits 31:22 - extended
1137 * bits 21:0 - interval
1138 */
1139#define IL4965_EXT_BEACON_TIME_POS 22
1140
1141struct il_rxon_context {
1142 struct ieee80211_vif *vif;
e94a4099
SG		 1143};
1144
99412002
SG		 1145struct il_power_mgr {
1146 struct il_powertable_cmd sleep_cmd;
1147 struct il_powertable_cmd sleep_cmd_next;
1148 int debug_sleep_level_override;
1149 bool pci_pm;
1150};
1151
e94a4099 1152struct il_priv {
e94a4099
SG		 1153 struct ieee80211_hw *hw;
1154 struct ieee80211_channel *ieee_channels;
1155 struct ieee80211_rate *ieee_rates;
93b7654e 1156
e94a4099 1157 struct il_cfg *cfg;
c39ae9fd 1158 const struct il_ops *ops;
93b7654e
SG		 1159#ifdef CONFIG_IWLEGACY_DEBUGFS
1160 const struct il_debugfs_ops *debugfs_ops;
1161#endif
e94a4099
SG		 1162
1163 /* temporary frame storage list */
1164 struct list_head free_frames;
1165 int frames_count;
1166
1167 enum ieee80211_band band;
1168 int alloc_rxb_page;
1169
1722f8e1
SG		 1170 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1171 struct il_rx_buf *rxb);
e94a4099
SG		 1172
1173 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1174
1175 /* spectrum measurement report caching */
1176 struct il_spectrum_notification measure_report;
1177 u8 measurement_status;
1178
1179 /* ucode beacon time */
1180 u32 ucode_beacon_time;
1181 int missed_beacon_threshold;
1182
1183 /* track IBSS manager (last beacon) status */
1184 u32 ibss_manager;
1185
1186 /* force reset */
1187 struct il_force_reset force_reset;
1188
1189 /* we allocate array of il_channel_info for NIC's valid channels.
1190 * Access via channel # using indirect idx array */
1191 struct il_channel_info *channel_info; /* channel info array */
1192 u8 channel_count; /* # of channels */
1193
1194 /* thermal calibration */
1195 s32 temperature; /* degrees Kelvin */
1196 s32 last_temperature;
1197
1198 /* init calibration results */
1199 struct il_calib_result calib_results[IL_CALIB_MAX];
1200
1201 /* Scan related variables */
1202 unsigned long scan_start;
1203 unsigned long scan_start_tsf;
1204 void *scan_cmd;
1205 enum ieee80211_band scan_band;
1206 struct cfg80211_scan_request *scan_request;
1207 struct ieee80211_vif *scan_vif;
1208 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1209 u8 mgmt_tx_ant;
1210
1211 /* spinlock */
1212 spinlock_t lock; /* protect general shared data */
1213 spinlock_t hcmd_lock; /* protect hcmd */
1214 spinlock_t reg_lock; /* protect hw register access */
1215 struct mutex mutex;
1216
1217 /* basic pci-network driver stuff */
1218 struct pci_dev *pci_dev;
1219
1220 /* pci hardware address support */
1221 void __iomem *hw_base;
e7392364
SG		 1222 u32 hw_rev;
1223 u32 hw_wa_rev;
1224 u8 rev_id;
e94a4099
SG		 1225
1226 /* command queue number */
1227 u8 cmd_queue;
1228
1229 /* max number of station keys */
1230 u8 sta_key_max_num;
1231
1232 /* EEPROM MAC addresses */
1233 struct mac_address addresses[1];
1234
1235 /* uCode images, save to reload in case of failure */
e7392364
SG		 1236 int fw_idx; /* firmware we're trying to load */
1237 u32 ucode_ver; /* version of ucode, copy of
1238 il_ucode.ver */
e94a4099
SG		 1239 struct fw_desc ucode_code; /* runtime inst */
1240 struct fw_desc ucode_data; /* runtime data original */
1241 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1242 struct fw_desc ucode_init; /* initialization inst */
1243 struct fw_desc ucode_init_data; /* initialization data */
1244 struct fw_desc ucode_boot; /* bootstrap inst */
1245 enum ucode_type ucode_type;
1246 u8 ucode_write_complete; /* the image write is complete */
1247 char firmware_name[25];
1248
83007196 1249 struct ieee80211_vif *vif;
e94a4099 1250
8d44f2bd
SG		 1251 struct il_qos_info qos_data;
1252
1c03c462
SG		 1253 struct {
1254 bool enabled;
1255 bool is_40mhz;
1256 bool non_gf_sta_present;
1257 u8 protection;
1258 u8 extension_chan_offset;
1259 } ht;
1260
c8b03958
SG		 1261 /*
1262 * We declare this const so it can only be
1263 * changed via explicit cast within the
1264 * routines that actually update the physical
1265 * hardware.
1266 */
1267 const struct il_rxon_cmd active;
1268 struct il_rxon_cmd staging;
1269
1270 struct il_rxon_time_cmd timing;
1271
e94a4099
SG		 1272 __le16 switch_channel;
1273
1274 /* 1st responses from initialize and runtime uCode images.
1275 * _4965's initialize alive response contains some calibration data. */
1276 struct il_init_alive_resp card_alive_init;
1277 struct il_alive_resp card_alive;
1278
1279 u16 active_rate;
1280
1281 u8 start_calib;
1282 struct il_sensitivity_data sensitivity_data;
1283 struct il_chain_noise_data chain_noise_data;
1284 __le16 sensitivity_tbl[HD_TBL_SIZE];
1285
1286 struct il_ht_config current_ht_config;
1287
1288 /* Rate scaling data */
1289 u8 retry_rate;
1290
1291 wait_queue_head_t wait_command_queue;
1292
1293 int activity_timer_active;
1294
1295 /* Rx and Tx DMA processing queues */
1296 struct il_rx_queue rxq;
1297 struct il_tx_queue *txq;
1298 unsigned long txq_ctx_active_msk;
e7392364
SG		 1299 struct il_dma_ptr kw; /* keep warm address */
1300 struct il_dma_ptr scd_bc_tbls;
e94a4099
SG		 1301
1302 u32 scd_base_addr; /* scheduler sram base address */
1303
1304 unsigned long status;
1305
1306 /* counts mgmt, ctl, and data packets */
1307 struct traffic_stats tx_stats;
1308 struct traffic_stats rx_stats;
1309
1310 /* counts interrupts */
1311 struct isr_stats isr_stats;
1312
1313 struct il_power_mgr power_data;
1314
1315 /* context information */
e7392364 1316 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
e94a4099
SG		 1317
1318 /* station table variables */
1319
1320 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1321 spinlock_t sta_lock;
1322 int num_stations;
1323 struct il_station_entry stations[IL_STATION_COUNT];
1324 unsigned long ucode_key_table;
1325
1326 /* queue refcounts */
1327#define IL_MAX_HW_QUEUES 32
1328 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1329 /* for each AC */
1330 atomic_t queue_stop_count[4];
1331
1332 /* Indication if ieee80211_ops->open has been called */
1333 u8 is_open;
1334
1335 u8 mac80211_registered;
1336
1337 /* eeprom -- this is in the card's little endian byte order */
1338 u8 *eeprom;
1339 struct il_eeprom_calib_info *calib_info;
1340
1341 enum nl80211_iftype iw_mode;
1342
1343 /* Last Rx'd beacon timestamp */
1344 u64 timestamp;
1345
1346 union {
1347#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1348 struct {
1349 void *shared_virt;
1350 dma_addr_t shared_phys;
1351
1352 struct delayed_work thermal_periodic;
1353 struct delayed_work rfkill_poll;
1354
1355 struct il3945_notif_stats stats;
1356#ifdef CONFIG_IWLEGACY_DEBUGFS
1357 struct il3945_notif_stats accum_stats;
1358 struct il3945_notif_stats delta_stats;
1359 struct il3945_notif_stats max_delta;
1360#endif
1361
1362 u32 sta_supp_rates;
1363 int last_rx_rssi; /* From Rx packet stats */
1364
1365 /* Rx'd packet timing information */
1366 u32 last_beacon_time;
1367 u64 last_tsf;
1368
1369 /*
1370 * each calibration channel group in the
1371 * EEPROM has a derived clip setting for
1372 * each rate.
1373 */
1374 const struct il3945_clip_group clip_groups[5];
1375
1376 } _3945;
1377#endif
1378#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1379 struct {
1380 struct il_rx_phy_res last_phy_res;
1381 bool last_phy_res_valid;
1382
1383 struct completion firmware_loading_complete;
1384
1385 /*
1386 * chain noise reset and gain commands are the
1387 * two extra calibration commands follows the standard
1388 * phy calibration commands
1389 */
1390 u8 phy_calib_chain_noise_reset_cmd;
1391 u8 phy_calib_chain_noise_gain_cmd;
1392
d735f921
SG		 1393 u8 key_mapping_keys;
1394 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1395
e94a4099
SG		 1396 struct il_notif_stats stats;
1397#ifdef CONFIG_IWLEGACY_DEBUGFS
1398 struct il_notif_stats accum_stats;
1399 struct il_notif_stats delta_stats;
1400 struct il_notif_stats max_delta;
1401#endif
1402
1403 } _4965;
1404#endif
1405 };
1406
1407 struct il_hw_params hw_params;
1408
1409 u32 inta_mask;
1410
1411 struct workqueue_struct *workqueue;
1412
1413 struct work_struct restart;
1414 struct work_struct scan_completed;
1415 struct work_struct rx_replenish;
1416 struct work_struct abort_scan;
1417
83007196 1418 bool beacon_enabled;
e94a4099
SG		 1419 struct sk_buff *beacon_skb;
1420
1421 struct work_struct tx_flush;
1422
1423 struct tasklet_struct irq_tasklet;
1424
1425 struct delayed_work init_alive_start;
1426 struct delayed_work alive_start;
1427 struct delayed_work scan_check;
1428
1429 /* TX Power */
1430 s8 tx_power_user_lmt;
1431 s8 tx_power_device_lmt;
1432 s8 tx_power_next;
1433
e94a4099
SG		 1434#ifdef CONFIG_IWLEGACY_DEBUG
1435 /* debugging info */
e7392364
SG		 1436 u32 debug_level; /* per device debugging will override global
1437 il_debug_level if set */
1438#endif /* CONFIG_IWLEGACY_DEBUG */
e94a4099
SG		 1439#ifdef CONFIG_IWLEGACY_DEBUGFS
1440 /* debugfs */
1441 u16 tx_traffic_idx;
1442 u16 rx_traffic_idx;
1443 u8 *tx_traffic;
1444 u8 *rx_traffic;
1445 struct dentry *debugfs_dir;
1446 u32 dbgfs_sram_offset, dbgfs_sram_len;
1447 bool disable_ht40;
e7392364 1448#endif /* CONFIG_IWLEGACY_DEBUGFS */
e94a4099
SG		 1449
1450 struct work_struct txpower_work;
1451 u32 disable_sens_cal;
1452 u32 disable_chain_noise_cal;
1453 u32 disable_tx_power_cal;
1454 struct work_struct run_time_calib_work;
1455 struct timer_list stats_periodic;
1456 struct timer_list watchdog;
1457 bool hw_ready;
1458
1459 struct led_classdev led;
1460 unsigned long blink_on, blink_off;
1461 bool led_registered;
e7392364 1462}; /*il_priv */
e94a4099 1463
e7392364
SG		 1464static inline void
1465il_txq_ctx_activate(struct il_priv *il, int txq_id)
e94a4099
SG		 1466{
1467 set_bit(txq_id, &il->txq_ctx_active_msk);
1468}
1469
e7392364
SG		 1470static inline void
1471il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
e94a4099
SG		 1472{
1473 clear_bit(txq_id, &il->txq_ctx_active_msk);
1474}
1475
e7392364
SG		 1476static inline int
1477il_is_associated(struct il_priv *il)
e94a4099 1478{
c8b03958 1479 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
e94a4099
SG		 1480}
1481
e7392364
SG		 1482static inline int
1483il_is_any_associated(struct il_priv *il)
e94a4099
SG		 1484{
1485 return il_is_associated(il);
1486}
1487
e7392364
SG		 1488static inline int
1489il_is_channel_valid(const struct il_channel_info *ch_info)
e94a4099
SG		 1490{
1491 if (ch_info == NULL)
1492 return 0;
1493 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1494}
1495
e7392364
SG		 1496static inline int
1497il_is_channel_radar(const struct il_channel_info *ch_info)
e94a4099
SG		 1498{
1499 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1500}
1501
e7392364
SG		 1502static inline u8
1503il_is_channel_a_band(const struct il_channel_info *ch_info)
e94a4099
SG		 1504{
1505 return ch_info->band == IEEE80211_BAND_5GHZ;
1506}
1507
1508static inline int
1509il_is_channel_passive(const struct il_channel_info *ch)
1510{
1511 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1512}
1513
1514static inline int
1515il_is_channel_ibss(const struct il_channel_info *ch)
1516{
1517 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1518}
be663ab6 1519
e94a4099
SG		 1520static inline void
1521__il_free_pages(struct il_priv *il, struct page *page)
1522{
1523 __free_pages(page, il->hw_params.rx_page_order);
1524 il->alloc_rxb_page--;
1525}
1526
e7392364
SG		 1527static inline void
1528il_free_pages(struct il_priv *il, unsigned long page)
e94a4099
SG		 1529{
1530 free_pages(page, il->hw_params.rx_page_order);
1531 il->alloc_rxb_page--;
1532}
be663ab6
WYG		 1533
1534#define IWLWIFI_VERSION "in-tree:"
1535#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1536#define DRV_AUTHOR "<ilw@linux.intel.com>"
1537
e2ebc833 1538#define IL_PCI_DEVICE(dev, subdev, cfg) \
be663ab6
WYG		 1539 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1540 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1541 .driver_data = (kernel_ulong_t)&(cfg)
1542
1543#define TIME_UNIT 1024
1544
e2ebc833
SG		 1545#define IL_SKU_G 0x1
1546#define IL_SKU_A 0x2
1547#define IL_SKU_N 0x8
be663ab6 1548
e2ebc833 1549#define IL_CMD(x) case x: return #x
be663ab6 1550
e94a4099 1551/* Size of one Rx buffer in host DRAM */
e7392364 1552#define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
e94a4099
SG		 1553#define IL_RX_BUF_SIZE_4K (4 * 1024)
1554#define IL_RX_BUF_SIZE_8K (8 * 1024)
1555
e2ebc833 1556struct il_hcmd_ops {
83007196
SG		 1557 int (*rxon_assoc) (struct il_priv *il);
1558 int (*commit_rxon) (struct il_priv *il);
1559 void (*set_rxon_chain) (struct il_priv *il);
be663ab6
WYG		 1560};
1561
e2ebc833 1562struct il_hcmd_utils_ops {
e7392364 1563 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1722f8e1
SG		 1564 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1565 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1566 void (*post_scan) (struct il_priv *il);
be663ab6
WYG		 1567};
1568
9b5e2f46 1569#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1570struct il_debugfs_ops {
1722f8e1
SG		 1571 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1572 size_t count, loff_t *ppos);
1573 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1574 size_t count, loff_t *ppos);
1575 ssize_t(*general_stats_read) (struct file *file,
1576 char __user *user_buf, size_t count,
1577 loff_t *ppos);
be663ab6 1578};
9b5e2f46 1579#endif
be663ab6 1580
1600b875
SG		 1581struct il_led_ops {
1582 int (*cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1583};
1584
1585struct il_legacy_ops {
1586 void (*post_associate) (struct il_priv *il);
1587 void (*config_ap) (struct il_priv *il);
1588 /* station management */
1589 int (*update_bcast_stations) (struct il_priv *il);
1590 int (*manage_ibss_station) (struct il_priv *il,
1591 struct ieee80211_vif *vif, bool add);
1592};
1593
1594struct il_ops {
be663ab6 1595 /* Handling TX */
1722f8e1
SG		 1596 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1597 struct il_tx_queue *txq,
e7392364 1598 u16 byte_cnt);
1722f8e1
SG		 1599 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1600 struct il_tx_queue *txq, dma_addr_t addr,
e7392364 1601 u16 len, u8 reset, u8 pad);
1722f8e1
SG		 1602 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1603 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
be663ab6 1604 /* alive notification after init uCode load */
1722f8e1 1605 void (*init_alive_start) (struct il_priv *il);
be663ab6 1606 /* check validity of rtc data address */
e7392364 1607 int (*is_valid_rtc_data_addr) (u32 addr);
be663ab6 1608 /* 1st ucode load */
1722f8e1 1609 int (*load_ucode) (struct il_priv *il);
1ba2f121 1610
1722f8e1
SG		 1611 void (*dump_nic_error_log) (struct il_priv *il);
1612 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1613 int (*set_channel_switch) (struct il_priv *il,
1614 struct ieee80211_channel_switch *ch_switch);
be663ab6 1615 /* power management */
f03ee2a8 1616 int (*apm_init) (struct il_priv *il);
be663ab6 1617
f03ee2a8 1618 /* tx power */
1722f8e1
SG		 1619 int (*send_tx_power) (struct il_priv *il);
1620 void (*update_chain_flags) (struct il_priv *il);
be663ab6 1621
47ef694d 1622 /* eeprom operations */
a89268e8
SG		 1623 int (*eeprom_acquire_semaphore) (struct il_priv *il);
1624 void (*eeprom_release_semaphore) (struct il_priv *il);
be663ab6 1625
e2ebc833
SG		 1626 const struct il_hcmd_ops *hcmd;
1627 const struct il_hcmd_utils_ops *utils;
1628 const struct il_led_ops *led;
1629 const struct il_nic_ops *nic;
1630 const struct il_legacy_ops *legacy;
be663ab6
WYG		 1631};
1632
e2ebc833 1633struct il_mod_params {
be663ab6
WYG		 1634 int sw_crypto; /* def: 0 = using hardware encryption */
1635 int disable_hw_scan; /* def: 0 = use h/w scan */
1636 int num_of_queues; /* def: HW dependent */
1637 int disable_11n; /* def: 0 = 11n capabilities enabled */
1638 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
e7392364 1639 int antenna; /* def: 0 = both antennas (use diversity) */
be663ab6
WYG		 1640 int restart_fw; /* def: 1 = restart firmware */
1641};
1642
1643/*
1644 * @led_compensation: compensate on the led on/off time per HW according
1645 * to the deviation to achieve the desired led frequency.
47ef694d 1646 * The detail algorithm is described in common.c
be663ab6 1647 * @chain_noise_num_beacons: number of beacons used to compute chain noise
be663ab6
WYG		 1648 * @wd_timeout: TX queues watchdog timeout
1649 * @temperature_kelvin: temperature report by uCode in kelvin
be663ab6
WYG		 1650 * @ucode_tracing: support ucode continuous tracing
1651 * @sensitivity_calib_by_driver: driver has the capability to perform
1652 * sensitivity calibration operation
1653 * @chain_noise_calib_by_driver: driver has the capability to perform
1654 * chain noise calibration operation
1655 */
e2ebc833 1656struct il_base_params {
be663ab6
WYG		 1657};
1658
47ef694d
SG		 1659#define IL_LED_SOLID 11
1660#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1661
1662#define IL_LED_ACTIVITY (0<<1)
1663#define IL_LED_LINK (1<<1)
1664
1665/*
1666 * LED mode
1667 * IL_LED_DEFAULT: use device default
1668 * IL_LED_RF_STATE: turn LED on/off based on RF state
1669 * LED ON = RF ON
1670 * LED OFF = RF OFF
1671 * IL_LED_BLINK: adjust led blink rate based on blink table
1672 */
1673enum il_led_mode {
1674 IL_LED_DEFAULT,
1675 IL_LED_RF_STATE,
1676 IL_LED_BLINK,
1677};
1678
1679void il_leds_init(struct il_priv *il);
1680void il_leds_exit(struct il_priv *il);
1681
be663ab6 1682/**
e2ebc833 1683 * struct il_cfg
be663ab6
WYG		 1684 * @fw_name_pre: Firmware filename prefix. The api version and extension
1685 * (.ucode) will be added to filename before loading from disk. The
1686 * filename is constructed as fw_name_pre<api>.ucode.
1687 * @ucode_api_max: Highest version of uCode API supported by driver.
1688 * @ucode_api_min: Lowest version of uCode API supported by driver.
1689 * @scan_antennas: available antenna for scan operation
1690 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1691 *
1692 * We enable the driver to be backward compatible wrt API version. The
1693 * driver specifies which APIs it supports (with @ucode_api_max being the
1694 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1695 * it has a supported API version. The firmware's API version will be
e2ebc833 1696 * stored in @il_priv, enabling the driver to make runtime changes based
be663ab6
WYG		 1697 * on firmware version used.
1698 *
1699 * For example,
46bc8d4b 1700 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
be663ab6
WYG		 1701 * Driver interacts with Firmware API version >= 2.
1702 * } else {
1703 * Driver interacts with Firmware API version 1.
1704 * }
1705 *
1706 * The ideal usage of this infrastructure is to treat a new ucode API
1707 * release as a new hardware revision. That is, through utilizing the
e2ebc833 1708 * il_hcmd_utils_ops etc. we accommodate different command structures
be663ab6
WYG		 1709 * and flows between hardware versions as well as their API
1710 * versions.
1711 *
1712 */
e2ebc833 1713struct il_cfg {
be663ab6
WYG		 1714 /* params specific to an individual device within a device family */
1715 const char *name;
1716 const char *fw_name_pre;
1717 const unsigned int ucode_api_max;
1718 const unsigned int ucode_api_min;
e7392364
SG		 1719 u8 valid_tx_ant;
1720 u8 valid_rx_ant;
be663ab6 1721 unsigned int sku;
e7392364
SG		 1722 u16 eeprom_ver;
1723 u16 eeprom_calib_ver;
be663ab6 1724 /* module based parameters which can be set from modprobe cmd */
e2ebc833 1725 const struct il_mod_params *mod_params;
be663ab6 1726 /* params not likely to change within a device family */
e2ebc833 1727 struct il_base_params *base_params;
be663ab6
WYG		 1728 /* params likely to change within a device family */
1729 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
e2ebc833 1730 enum il_led_mode led_mode;
89ef1ed2
SG		 1731
1732 int eeprom_size;
1733 int num_of_queues; /* def: HW dependent */
1734 int num_of_ampdu_queues; /* def: HW dependent */
1735 /* for il_apm_init() */
1736 u32 pll_cfg_val;
1737 bool set_l0s;
1738 bool use_bsm;
1739
1740 u16 led_compensation;
1741 int chain_noise_num_beacons;
1742 unsigned int wd_timeout;
1743 bool temperature_kelvin;
1744 const bool ucode_tracing;
1745 const bool sensitivity_calib_by_driver;
1746 const bool chain_noise_calib_by_driver;
93a984a4
SG		 1747
1748 const u32 regulatory_bands[7];
be663ab6
WYG		 1749};
1750
1751/***************************
1752 * L i b *
1753 ***************************/
1754
e7392364
SG		 1755int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1756 u16 queue, const struct ieee80211_tx_queue_params *params);
e2ebc833 1757int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
e7392364 1758
83007196
SG		 1759void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1760int il_check_rxon_cmd(struct il_priv *il);
1761int il_full_rxon_required(struct il_priv *il);
1762int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1763void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
1764 struct ieee80211_vif *vif);
e7392364
SG		 1765u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1766void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
83007196 1767bool il_is_ht40_tx_allowed(struct il_priv *il,
e7392364 1768 struct ieee80211_sta_ht_cap *ht_cap);
83007196 1769void il_connection_init_rx_config(struct il_priv *il);
46bc8d4b 1770void il_set_rate(struct il_priv *il);
e7392364
SG		 1771int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1772 u32 decrypt_res, struct ieee80211_rx_status *stats);
46bc8d4b 1773void il_irq_handle_error(struct il_priv *il);
e7392364 1774int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
e2ebc833 1775void il_mac_remove_interface(struct ieee80211_hw *hw,
e7392364
SG		 1776 struct ieee80211_vif *vif);
1777int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1778 enum nl80211_iftype newtype, bool newp2p);
46bc8d4b
SG		 1779int il_alloc_txq_mem(struct il_priv *il);
1780void il_txq_mem(struct il_priv *il);
be663ab6 1781
d3175167 1782#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b
SG		 1783int il_alloc_traffic_mem(struct il_priv *il);
1784void il_free_traffic_mem(struct il_priv *il);
1785void il_reset_traffic_log(struct il_priv *il);
e7392364
SG		 1786void il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1787 struct ieee80211_hdr *header);
1788void il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1789 struct ieee80211_hdr *header);
e2ebc833
SG		 1790const char *il_get_mgmt_string(int cmd);
1791const char *il_get_ctrl_string(int cmd);
46bc8d4b 1792void il_clear_traffic_stats(struct il_priv *il);
e7392364 1793void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
be663ab6 1794#else
e7392364
SG		 1795static inline int
1796il_alloc_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1797{
1798 return 0;
1799}
e7392364
SG		 1800
1801static inline void
1802il_free_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1803{
1804}
e7392364
SG		 1805
1806static inline void
1807il_reset_traffic_log(struct il_priv *il)
be663ab6
WYG		 1808{
1809}
e7392364
SG		 1810
1811static inline void
1812il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1813 struct ieee80211_hdr *header)
be663ab6
WYG		 1814{
1815}
e7392364
SG		 1816
1817static inline void
1818il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1819 struct ieee80211_hdr *header)
be663ab6
WYG		 1820{
1821}
e7392364
SG		 1822
1823static inline void
1824il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6
WYG		 1825{
1826}
1827#endif
1828/*****************************************************
1829 * RX handlers.
1830 * **************************************************/
e7392364
SG		 1831void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1832void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1833void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1834
1835/*****************************************************
1836* RX
1837******************************************************/
46bc8d4b
SG		 1838void il_cmd_queue_unmap(struct il_priv *il);
1839void il_cmd_queue_free(struct il_priv *il);
1840int il_rx_queue_alloc(struct il_priv *il);
e7392364 1841void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
e2ebc833 1842int il_rx_queue_space(const struct il_rx_queue *q);
e7392364 1843void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6 1844/* Handlers */
e7392364
SG		 1845void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1846void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
46bc8d4b 1847void il_chswitch_done(struct il_priv *il, bool is_success);
d2dfb33e 1848void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1849
1850/* TX helpers */
1851
1852/*****************************************************
1853* TX
1854******************************************************/
e7392364
SG		 1855void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1856int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
1857 u32 txq_id);
1858void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
1859 int slots_num, u32 txq_id);
46bc8d4b
SG		 1860void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1861void il_tx_queue_free(struct il_priv *il, int txq_id);
1862void il_setup_watchdog(struct il_priv *il);
be663ab6
WYG		 1863/*****************************************************
1864 * TX power
1865 ****************************************************/
46bc8d4b 1866int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
be663ab6
WYG		 1867
1868/*******************************************************************************
1869 * Rate
1870 ******************************************************************************/
1871
83007196 1872u8 il_get_lowest_plcp(struct il_priv *il);
be663ab6
WYG		 1873
1874/*******************************************************************************
1875 * Scanning
1876 ******************************************************************************/
46bc8d4b
SG		 1877void il_init_scan_params(struct il_priv *il);
1878int il_scan_cancel(struct il_priv *il);
1879int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1880void il_force_scan_end(struct il_priv *il);
e7392364
SG		 1881int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1882 struct cfg80211_scan_request *req);
46bc8d4b
SG		 1883void il_internal_short_hw_scan(struct il_priv *il);
1884int il_force_reset(struct il_priv *il, bool external);
e7392364 1885u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1886 const u8 *ta, const u8 *ie, int ie_len, int left);
46bc8d4b 1887void il_setup_rx_scan_handlers(struct il_priv *il);
e7392364
SG		 1888u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1889 u8 n_probes);
1890u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1891 struct ieee80211_vif *vif);
46bc8d4b
SG		 1892void il_setup_scan_deferred_work(struct il_priv *il);
1893void il_cancel_scan_deferred_work(struct il_priv *il);
be663ab6
WYG		 1894
1895/* For faster active scanning, scan will move to the next channel if fewer than
1896 * PLCP_QUIET_THRESH packets are heard on this channel within
1897 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
1898 * time if it's a quiet channel (nothing responded to our probe, and there's
1899 * no other traffic).
1900 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
e7392364
SG		 1901#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
1902#define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
be663ab6 1903
e2ebc833 1904#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
be663ab6
WYG		 1905
1906/*****************************************************
1907 * S e n d i n g H o s t C o m m a n d s *
1908 *****************************************************/
1909
e2ebc833 1910const char *il_get_cmd_string(u8 cmd);
e7392364 1911int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
46bc8d4b 1912int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
e7392364
SG		 1913int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1914 const void *data);
1915int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 1916 void (*callback) (struct il_priv *il,
1917 struct il_device_cmd *cmd,
1918 struct il_rx_pkt *pkt));
be663ab6 1919
46bc8d4b 1920int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
be663ab6 1921
be663ab6
WYG		 1922/*****************************************************
1923 * PCI *
1924 *****************************************************/
1925
e7392364
SG		 1926static inline u16
1927il_pcie_link_ctl(struct il_priv *il)
be663ab6
WYG		 1928{
1929 int pos;
1930 u16 pci_lnk_ctl;
46bc8d4b
SG		 1931 pos = pci_pcie_cap(il->pci_dev);
1932 pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
be663ab6
WYG		 1933 return pci_lnk_ctl;
1934}
1935
e2ebc833 1936void il_bg_watchdog(unsigned long data);
e7392364
SG		 1937u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1938__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1939 u32 beacon_interval);
be663ab6
WYG		 1940
1941#ifdef CONFIG_PM
e2ebc833
SG		 1942int il_pci_suspend(struct device *device);
1943int il_pci_resume(struct device *device);
1944extern const struct dev_pm_ops il_pm_ops;
be663ab6 1945
e2ebc833 1946#define IL_LEGACY_PM_OPS (&il_pm_ops)
be663ab6
WYG		 1947
1948#else /* !CONFIG_PM */
1949
e2ebc833 1950#define IL_LEGACY_PM_OPS NULL
be663ab6
WYG		 1951
1952#endif /* !CONFIG_PM */
1953
1954/*****************************************************
1955* Error Handling Debugging
1956******************************************************/
46bc8d4b 1957void il4965_dump_nic_error_log(struct il_priv *il);
d3175167 1958#ifdef CONFIG_IWLEGACY_DEBUG
83007196 1959void il_print_rx_config_cmd(struct il_priv *il);
be663ab6 1960#else
e7392364 1961static inline void
83007196 1962il_print_rx_config_cmd(struct il_priv *il)
be663ab6
WYG		 1963{
1964}
1965#endif
1966
46bc8d4b 1967void il_clear_isr_stats(struct il_priv *il);
be663ab6
WYG		 1968
1969/*****************************************************
1970* GEOS
1971******************************************************/
46bc8d4b
SG		 1972int il_init_geos(struct il_priv *il);
1973void il_free_geos(struct il_priv *il);
be663ab6
WYG		 1974
1975/*************** DRIVER STATUS FUNCTIONS *****/
1976
a6766ccd
SG		 1977#define S_HCMD_ACTIVE 0 /* host command in progress */
1978/* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
1979#define S_INT_ENABLED 2
1980#define S_RF_KILL_HW 3
1981#define S_CT_KILL 4
1982#define S_INIT 5
1983#define S_ALIVE 6
1984#define S_READY 7
1985#define S_TEMPERATURE 8
1986#define S_GEO_CONFIGURED 9
1987#define S_EXIT_PENDING 10
db7746f7 1988#define S_STATS 12
a6766ccd
SG		 1989#define S_SCANNING 13
1990#define S_SCAN_ABORTING 14
1991#define S_SCAN_HW 15
1992#define S_POWER_PMI 16
1993#define S_FW_ERROR 17
1994#define S_CHANNEL_SWITCH_PENDING 18
be663ab6 1995
e7392364
SG		 1996static inline int
1997il_is_ready(struct il_priv *il)
be663ab6
WYG		 1998{
1999 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
2000 * set but EXIT_PENDING is not */
a6766ccd 2001 return test_bit(S_READY, &il->status) &&
e7392364
SG		 2002 test_bit(S_GEO_CONFIGURED, &il->status) &&
2003 !test_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 2004}
2005
e7392364
SG		 2006static inline int
2007il_is_alive(struct il_priv *il)
be663ab6 2008{
a6766ccd 2009 return test_bit(S_ALIVE, &il->status);
be663ab6
WYG		 2010}
2011
e7392364
SG		 2012static inline int
2013il_is_init(struct il_priv *il)
be663ab6 2014{
a6766ccd 2015 return test_bit(S_INIT, &il->status);
be663ab6
WYG		 2016}
2017
e7392364
SG		 2018static inline int
2019il_is_rfkill_hw(struct il_priv *il)
be663ab6 2020{
a6766ccd 2021 return test_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 2022}
2023
e7392364
SG		 2024static inline int
2025il_is_rfkill(struct il_priv *il)
be663ab6 2026{
46bc8d4b 2027 return il_is_rfkill_hw(il);
be663ab6
WYG		 2028}
2029
e7392364
SG		 2030static inline int
2031il_is_ctkill(struct il_priv *il)
be663ab6 2032{
a6766ccd 2033 return test_bit(S_CT_KILL, &il->status);
be663ab6
WYG		 2034}
2035
e7392364
SG		 2036static inline int
2037il_is_ready_rf(struct il_priv *il)
be663ab6
WYG		 2038{
2039
46bc8d4b 2040 if (il_is_rfkill(il))
be663ab6
WYG		 2041 return 0;
2042
46bc8d4b 2043 return il_is_ready(il);
be663ab6
WYG		 2044}
2045
46bc8d4b 2046extern void il_send_bt_config(struct il_priv *il);
e7392364 2047extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
46bc8d4b
SG		 2048void il_apm_stop(struct il_priv *il);
2049int il_apm_init(struct il_priv *il);
be663ab6 2050
83007196
SG		 2051int il_send_rxon_timing(struct il_priv *il);
2052
e7392364 2053static inline int
83007196 2054il_send_rxon_assoc(struct il_priv *il)
be663ab6 2055{
c39ae9fd 2056 return il->ops->hcmd->rxon_assoc(il);
be663ab6 2057}
e7392364
SG		 2058
2059static inline int
83007196 2060il_commit_rxon(struct il_priv *il)
be663ab6 2061{
c39ae9fd 2062 return il->ops->hcmd->commit_rxon(il);
be663ab6 2063}
e7392364
SG		 2064
2065static inline const struct ieee80211_supported_band *
2066il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
be663ab6 2067{
46bc8d4b 2068 return il->hw->wiphy->bands[band];
be663ab6
WYG		 2069}
2070
be663ab6 2071/* mac80211 handlers */
e2ebc833 2072int il_mac_config(struct ieee80211_hw *hw, u32 changed);
e7392364
SG		 2073void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
2074void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2075 struct ieee80211_bss_conf *bss_conf, u32 changes);
2076void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 2077 __le16 fc, __le32 *tx_flags);
be663ab6 2078
e2ebc833 2079irqreturn_t il_isr(int irq, void *data);
be663ab6 2080
17d4eca6
SG		 2081extern void il_set_bit(struct il_priv *p, u32 r, u32 m);
2082extern void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1e0f32a4 2083extern bool _il_grab_nic_access(struct il_priv *il);
17d4eca6
SG		 2084extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
2085extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
2086extern u32 il_rd_prph(struct il_priv *il, u32 reg);
2087extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
2088extern u32 il_read_targ_mem(struct il_priv *il, u32 addr);
2089extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
e94a4099 2090
e7392364
SG		 2091static inline void
2092_il_write8(struct il_priv *il, u32 ofs, u8 val)
e94a4099 2093{
a5f16137 2094 writeb(val, il->hw_base + ofs);
e94a4099
SG		 2095}
2096#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2097
e7392364
SG		 2098static inline void
2099_il_wr(struct il_priv *il, u32 ofs, u32 val)
e94a4099 2100{
a5f16137 2101 writel(val, il->hw_base + ofs);
e94a4099
SG		 2102}
2103
e7392364
SG		 2104static inline u32
2105_il_rd(struct il_priv *il, u32 ofs)
e94a4099 2106{
a5f16137 2107 return readl(il->hw_base + ofs);
e94a4099
SG		 2108}
2109
e94a4099
SG		 2110static inline void
2111_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2112{
2113 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2114}
2115
e7392364 2116static inline void
17d4eca6 2117_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
e94a4099 2118{
17d4eca6 2119 _il_wr(il, reg, _il_rd(il, reg) | mask);
e94a4099
SG		 2120}
2121
e7392364
SG		 2122static inline void
2123_il_release_nic_access(struct il_priv *il)
e94a4099 2124{
e7392364 2125 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4e5ea208
SG		 2126 /*
2127 * In above we are reading CSR_GP_CNTRL register, what will flush any
2128 * previous writes, but still want write, which clear MAC_ACCESS_REQ
2129 * bit, be performed on PCI bus before any other writes scheduled on
2130 * different CPUs (after we drop reg_lock).
2131 */
2132 mmiowb();
e94a4099
SG		 2133}
2134
e7392364
SG		 2135static inline u32
2136il_rd(struct il_priv *il, u32 reg)
e94a4099
SG		 2137{
2138 u32 value;
2139 unsigned long reg_flags;
2140
2141 spin_lock_irqsave(&il->reg_lock, reg_flags);
2142 _il_grab_nic_access(il);
2143 value = _il_rd(il, reg);
2144 _il_release_nic_access(il);
2145 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2146 return value;
e94a4099
SG		 2147}
2148
2149static inline void
2150il_wr(struct il_priv *il, u32 reg, u32 value)
2151{
2152 unsigned long reg_flags;
2153
2154 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 2155 if (likely(_il_grab_nic_access(il))) {
e94a4099
SG		 2156 _il_wr(il, reg, value);
2157 _il_release_nic_access(il);
2158 }
2159 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2160}
2161
e7392364
SG		 2162static inline u32
2163_il_rd_prph(struct il_priv *il, u32 reg)
e94a4099
SG		 2164{
2165 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
e94a4099
SG		 2166 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2167}
2168
e7392364
SG		 2169static inline void
2170_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
e94a4099 2171{
e7392364 2172 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
e94a4099
SG		 2173 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2174}
2175
e94a4099
SG		 2176static inline void
2177il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2178{
2179 unsigned long reg_flags;
2180
2181 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4
SG		 2182 if (likely(_il_grab_nic_access(il))) {
2183 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2184 _il_release_nic_access(il);
2185 }
e94a4099
SG		 2186 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2187}
2188
e7392364
SG		 2189static inline void
2190il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
e94a4099
SG		 2191{
2192 unsigned long reg_flags;
2193
2194 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4
SG		 2195 if (likely(_il_grab_nic_access(il))) {
2196 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2197 _il_release_nic_access(il);
2198 }
e94a4099
SG		 2199 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2200}
2201
e7392364
SG		 2202static inline void
2203il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
e94a4099
SG		 2204{
2205 unsigned long reg_flags;
2206 u32 val;
2207
2208 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4
SG		 2209 if (likely(_il_grab_nic_access(il))) {
2210 val = _il_rd_prph(il, reg);
2211 _il_wr_prph(il, reg, (val & ~mask));
2212 _il_release_nic_access(il);
2213 }
e94a4099
SG		 2214 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2215}
2216
e94a4099
SG		 2217#define HW_KEY_DYNAMIC 0
2218#define HW_KEY_DEFAULT 1
2219
e7392364
SG		 2220#define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2221#define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2222#define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2223 being activated */
2224#define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2225 (this is for the IBSS BSSID stations) */
2226#define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
e94a4099 2227
83007196
SG		 2228void il_restore_stations(struct il_priv *il);
2229void il_clear_ucode_stations(struct il_priv *il);
e94a4099
SG		 2230void il_dealloc_bcast_stations(struct il_priv *il);
2231int il_get_free_ucode_key_idx(struct il_priv *il);
e7392364 2232int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
83007196 2233int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
1722f8e1 2234 struct ieee80211_sta *sta, u8 *sta_id_r);
e7392364
SG		 2235int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2236int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2237 struct ieee80211_sta *sta);
2238
83007196
SG		 2239u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2240 struct ieee80211_sta *sta);
e7392364 2241
83007196
SG		 2242int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2243 u8 flags, bool init);
e94a4099
SG		 2244
2245/**
2246 * il_clear_driver_stations - clear knowledge of all stations from driver
2247 * @il: iwl il struct
2248 *
2249 * This is called during il_down() to make sure that in the case
2250 * we're coming there from a hardware restart mac80211 will be
2251 * able to reconfigure stations -- if we're getting there in the
2252 * normal down flow then the stations will already be cleared.
2253 */
e7392364
SG		 2254static inline void
2255il_clear_driver_stations(struct il_priv *il)
e94a4099
SG		 2256{
2257 unsigned long flags;
e94a4099
SG		 2258
2259 spin_lock_irqsave(&il->sta_lock, flags);
2260 memset(il->stations, 0, sizeof(il->stations));
2261 il->num_stations = 0;
e94a4099 2262 il->ucode_key_table = 0;
e94a4099
SG		 2263 spin_unlock_irqrestore(&il->sta_lock, flags);
2264}
2265
e7392364
SG		 2266static inline int
2267il_sta_id(struct ieee80211_sta *sta)
e94a4099
SG		 2268{
2269 if (WARN_ON(!sta))
2270 return IL_INVALID_STATION;
2271
2272 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2273}
2274
2275/**
2276 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2277 * @il: iwl il
2278 * @context: the current context
2279 * @sta: mac80211 station
2280 *
2281 * In certain circumstances mac80211 passes a station pointer
2282 * that may be %NULL, for example during TX or key setup. In
2283 * that case, we need to use the broadcast station, so this
2284 * inline wraps that pattern.
2285 */
e7392364 2286static inline int
83007196 2287il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
e94a4099
SG		 2288{
2289 int sta_id;
2290
2291 if (!sta)
b16db50a 2292 return il->hw_params.bcast_id;
e94a4099
SG		 2293
2294 sta_id = il_sta_id(sta);
2295
2296 /*
2297 * mac80211 should not be passing a partially
2298 * initialised station!
2299 */
2300 WARN_ON(sta_id == IL_INVALID_STATION);
2301
2302 return sta_id;
2303}
2304
2305/**
2306 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2307 * @idx -- current idx
2308 * @n_bd -- total number of entries in queue (must be power of 2)
2309 */
e7392364
SG		 2310static inline int
2311il_queue_inc_wrap(int idx, int n_bd)
e94a4099
SG		 2312{
2313 return ++idx & (n_bd - 1);
2314}
2315
2316/**
2317 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2318 * @idx -- current idx
2319 * @n_bd -- total number of entries in queue (must be power of 2)
2320 */
e7392364
SG		 2321static inline int
2322il_queue_dec_wrap(int idx, int n_bd)
e94a4099
SG		 2323{
2324 return --idx & (n_bd - 1);
2325}
2326
2327/* TODO: Move fw_desc functions to iwl-pci.ko */
e7392364
SG		 2328static inline void
2329il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2330{
2331 if (desc->v_addr)
e7392364
SG		 2332 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2333 desc->p_addr);
e94a4099
SG		 2334 desc->v_addr = NULL;
2335 desc->len = 0;
2336}
2337
e7392364
SG		 2338static inline int
2339il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2340{
2341 if (!desc->len) {
2342 desc->v_addr = NULL;
2343 return -EINVAL;
2344 }
2345
e7392364
SG		 2346 desc->v_addr =
2347 dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2348 GFP_KERNEL);
e94a4099
SG		 2349 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2350}
2351
2352/*
2353 * we have 8 bits used like this:
2354 *
2355 * 7 6 5 4 3 2 1 0
2356 * | | | | | | | |
2357 * | | | | | | +-+-------- AC queue (0-3)
2358 * | | | | | |
2359 * | +-+-+-+-+------------ HW queue ID
2360 * |
2361 * +---------------------- unused
2362 */
2363static inline void
2364il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2365{
e7392364
SG		 2366 BUG_ON(ac > 3); /* only have 2 bits */
2367 BUG_ON(hwq > 31); /* only use 5 bits */
e94a4099
SG		 2368
2369 txq->swq_id = (hwq << 2) | ac;
2370}
2371
e7392364
SG		 2372static inline void
2373il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2374{
2375 u8 queue = txq->swq_id;
2376 u8 ac = queue & 3;
2377 u8 hwq = (queue >> 2) & 0x1f;
2378
2379 if (test_and_clear_bit(hwq, il->queue_stopped))
2380 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2381 ieee80211_wake_queue(il->hw, ac);
2382}
2383
e7392364
SG		 2384static inline void
2385il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2386{
2387 u8 queue = txq->swq_id;
2388 u8 ac = queue & 3;
2389 u8 hwq = (queue >> 2) & 0x1f;
2390
2391 if (!test_and_set_bit(hwq, il->queue_stopped))
2392 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2393 ieee80211_stop_queue(il->hw, ac);
2394}
2395
2396#ifdef ieee80211_stop_queue
2397#undef ieee80211_stop_queue
2398#endif
2399
2400#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2401
2402#ifdef ieee80211_wake_queue
2403#undef ieee80211_wake_queue
2404#endif
2405
2406#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2407
e7392364
SG		 2408static inline void
2409il_disable_interrupts(struct il_priv *il)
e94a4099
SG		 2410{
2411 clear_bit(S_INT_ENABLED, &il->status);
2412
2413 /* disable interrupts from uCode/NIC to host */
2414 _il_wr(il, CSR_INT_MASK, 0x00000000);
2415
2416 /* acknowledge/clear/reset any interrupts still pending
2417 * from uCode or flow handler (Rx/Tx DMA) */
2418 _il_wr(il, CSR_INT, 0xffffffff);
2419 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
e94a4099
SG		 2420}
2421
e7392364
SG		 2422static inline void
2423il_enable_rfkill_int(struct il_priv *il)
e94a4099 2424{
e94a4099
SG		 2425 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2426}
2427
e7392364
SG		 2428static inline void
2429il_enable_interrupts(struct il_priv *il)
e94a4099 2430{
e94a4099
SG		 2431 set_bit(S_INT_ENABLED, &il->status);
2432 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2433}
2434
2435/**
2436 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2437 * @il -- pointer to il_priv data structure
2438 * @tsf_bits -- number of bits need to shift for masking)
2439 */
e7392364
SG		 2440static inline u32
2441il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2442{
2443 return (1 << tsf_bits) - 1;
2444}
2445
2446/**
2447 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2448 * @il -- pointer to il_priv data structure
2449 * @tsf_bits -- number of bits need to shift for masking)
2450 */
e7392364
SG		 2451static inline u32
2452il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2453{
2454 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2455}
2456
2457/**
2458 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2459 *
2460 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2461 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2462 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2463 * in which the last frame was written to
2464 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2465 * which was transferred
2466 */
2467struct il_rb_status {
2468 __le16 closed_rb_num;
2469 __le16 closed_fr_num;
2470 __le16 finished_rb_num;
2471 __le16 finished_fr_nam;
e7392364 2472 __le32 __unused; /* 3945 only */
e94a4099
SG		 2473} __packed;
2474
e94a4099
SG		 2475#define TFD_QUEUE_SIZE_MAX (256)
2476#define TFD_QUEUE_SIZE_BC_DUP (64)
2477#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2478#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2479#define IL_NUM_OF_TBS 20
2480
e7392364
SG		 2481static inline u8
2482il_get_dma_hi_addr(dma_addr_t addr)
e94a4099
SG		 2483{
2484 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2485}
e7392364 2486
e94a4099
SG		 2487/**
2488 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2489 *
2490 * This structure contains dma address and length of transmission address
2491 *
1722f8e1
SG		 2492 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2493 * unaligned on 16 bit boundary
2494 * @hi_n_len: 0-3 [35:32] portion of dma
2495 * 4-15 length of the tx buffer
e94a4099
SG		 2496 */
2497struct il_tfd_tb {
2498 __le32 lo;
2499 __le16 hi_n_len;
2500} __packed;
2501
2502/**
2503 * struct il_tfd
2504 *
2505 * Transmit Frame Descriptor (TFD)
2506 *
2507 * @ __reserved1[3] reserved
2508 * @ num_tbs 0-4 number of active tbs
2509 * 5 reserved
2510 * 6-7 padding (not used)
2511 * @ tbs[20] transmit frame buffer descriptors
1722f8e1 2512 * @ __pad padding
e94a4099
SG		 2513 *
2514 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2515 * Both driver and device share these circular buffers, each of which must be
2516 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2517 *
2518 * Driver must indicate the physical address of the base of each
9a95b370 2519 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
e94a4099
SG		 2520 *
2521 * Each TFD contains pointer/size information for up to 20 data buffers
2522 * in host DRAM. These buffers collectively contain the (one) frame described
2523 * by the TFD. Each buffer must be a single contiguous block of memory within
2524 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2525 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2526 * Tx frame, up to 8 KBytes in size.
2527 *
2528 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2529 */
2530struct il_tfd {
2531 u8 __reserved1[3];
2532 u8 num_tbs;
2533 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2534 __le32 __pad;
2535} __packed;
2536/* PCI registers */
2537#define PCI_CFG_RETRY_TIMEOUT 0x041
2538
2539/* PCI register values */
2540#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2541#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2542
3fbbf9a8 2543struct il_rate_info {
e7392364
SG		 2544 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2545 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2546 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2547 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2548 u8 prev_ieee; /* previous rate in IEEE speeds */
2549 u8 next_ieee; /* next rate in IEEE speeds */
2550 u8 prev_rs; /* previous rate used in rs algo */
2551 u8 next_rs; /* next rate used in rs algo */
2552 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2553 u8 next_rs_tgg; /* next rate used in TGG rs algo */
3fbbf9a8
SG		 2554};
2555
2556struct il3945_rate_info {
2557 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2558 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2559 u8 prev_ieee; /* previous rate in IEEE speeds */
2560 u8 next_ieee; /* next rate in IEEE speeds */
2561 u8 prev_rs; /* previous rate used in rs algo */
2562 u8 next_rs; /* next rate used in rs algo */
2563 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2564 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2565 u8 table_rs_idx; /* idx in rate scale table cmd */
2566 u8 prev_table_rs; /* prev in rate table cmd */
2567};
2568
3fbbf9a8
SG		 2569/*
2570 * These serve as idxes into
2571 * struct il_rate_info il_rates[RATE_COUNT];
2572 */
2573enum {
2574 RATE_1M_IDX = 0,
2575 RATE_2M_IDX,
2576 RATE_5M_IDX,
2577 RATE_11M_IDX,
2578 RATE_6M_IDX,
2579 RATE_9M_IDX,
2580 RATE_12M_IDX,
2581 RATE_18M_IDX,
2582 RATE_24M_IDX,
2583 RATE_36M_IDX,
2584 RATE_48M_IDX,
2585 RATE_54M_IDX,
2586 RATE_60M_IDX,
2587 RATE_COUNT,
2588 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2589 RATE_COUNT_3945 = RATE_COUNT - 1,
2590 RATE_INVM_IDX = RATE_COUNT,
2591 RATE_INVALID = RATE_COUNT,
2592};
2593
2594enum {
2595 RATE_6M_IDX_TBL = 0,
2596 RATE_9M_IDX_TBL,
2597 RATE_12M_IDX_TBL,
2598 RATE_18M_IDX_TBL,
2599 RATE_24M_IDX_TBL,
2600 RATE_36M_IDX_TBL,
2601 RATE_48M_IDX_TBL,
2602 RATE_54M_IDX_TBL,
2603 RATE_1M_IDX_TBL,
2604 RATE_2M_IDX_TBL,
2605 RATE_5M_IDX_TBL,
2606 RATE_11M_IDX_TBL,
2607 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2608};
2609
2610enum {
2611 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2612 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2613 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2614 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2615 IL_LAST_CCK_RATE = RATE_11M_IDX,
2616};
2617
2618/* #define vs. enum to keep from defaulting to 'large integer' */
2619#define RATE_6M_MASK (1 << RATE_6M_IDX)
2620#define RATE_9M_MASK (1 << RATE_9M_IDX)
2621#define RATE_12M_MASK (1 << RATE_12M_IDX)
2622#define RATE_18M_MASK (1 << RATE_18M_IDX)
2623#define RATE_24M_MASK (1 << RATE_24M_IDX)
2624#define RATE_36M_MASK (1 << RATE_36M_IDX)
2625#define RATE_48M_MASK (1 << RATE_48M_IDX)
2626#define RATE_54M_MASK (1 << RATE_54M_IDX)
2627#define RATE_60M_MASK (1 << RATE_60M_IDX)
2628#define RATE_1M_MASK (1 << RATE_1M_IDX)
2629#define RATE_2M_MASK (1 << RATE_2M_IDX)
2630#define RATE_5M_MASK (1 << RATE_5M_IDX)
2631#define RATE_11M_MASK (1 << RATE_11M_IDX)
2632
2633/* uCode API values for legacy bit rates, both OFDM and CCK */
2634enum {
e7392364
SG		 2635 RATE_6M_PLCP = 13,
2636 RATE_9M_PLCP = 15,
3fbbf9a8
SG		 2637 RATE_12M_PLCP = 5,
2638 RATE_18M_PLCP = 7,
2639 RATE_24M_PLCP = 9,
2640 RATE_36M_PLCP = 11,
2641 RATE_48M_PLCP = 1,
2642 RATE_54M_PLCP = 3,
e7392364
SG		 2643 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */
2644 RATE_1M_PLCP = 10,
2645 RATE_2M_PLCP = 20,
2646 RATE_5M_PLCP = 55,
3fbbf9a8 2647 RATE_11M_PLCP = 110,
e7392364 2648 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
3fbbf9a8
SG		 2649};
2650
2651/* uCode API values for OFDM high-throughput (HT) bit rates */
2652enum {
2653 RATE_SISO_6M_PLCP = 0,
2654 RATE_SISO_12M_PLCP = 1,
2655 RATE_SISO_18M_PLCP = 2,
2656 RATE_SISO_24M_PLCP = 3,
2657 RATE_SISO_36M_PLCP = 4,
2658 RATE_SISO_48M_PLCP = 5,
2659 RATE_SISO_54M_PLCP = 6,
2660 RATE_SISO_60M_PLCP = 7,
e7392364 2661 RATE_MIMO2_6M_PLCP = 0x8,
3fbbf9a8
SG		 2662 RATE_MIMO2_12M_PLCP = 0x9,
2663 RATE_MIMO2_18M_PLCP = 0xa,
2664 RATE_MIMO2_24M_PLCP = 0xb,
2665 RATE_MIMO2_36M_PLCP = 0xc,
2666 RATE_MIMO2_48M_PLCP = 0xd,
2667 RATE_MIMO2_54M_PLCP = 0xe,
2668 RATE_MIMO2_60M_PLCP = 0xf,
2669 RATE_SISO_INVM_PLCP,
2670 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2671};
2672
2673/* MAC header values for bit rates */
2674enum {
e7392364
SG		 2675 RATE_6M_IEEE = 12,
2676 RATE_9M_IEEE = 18,
3fbbf9a8
SG		 2677 RATE_12M_IEEE = 24,
2678 RATE_18M_IEEE = 36,
2679 RATE_24M_IEEE = 48,
2680 RATE_36M_IEEE = 72,
2681 RATE_48M_IEEE = 96,
2682 RATE_54M_IEEE = 108,
2683 RATE_60M_IEEE = 120,
e7392364
SG		 2684 RATE_1M_IEEE = 2,
2685 RATE_2M_IEEE = 4,
2686 RATE_5M_IEEE = 11,
3fbbf9a8
SG		 2687 RATE_11M_IEEE = 22,
2688};
2689
2690#define IL_CCK_BASIC_RATES_MASK \
2691 (RATE_1M_MASK | \
2692 RATE_2M_MASK)
2693
2694#define IL_CCK_RATES_MASK \
2695 (IL_CCK_BASIC_RATES_MASK | \
2696 RATE_5M_MASK | \
2697 RATE_11M_MASK)
2698
2699#define IL_OFDM_BASIC_RATES_MASK \
2700 (RATE_6M_MASK | \
2701 RATE_12M_MASK | \
2702 RATE_24M_MASK)
2703
2704#define IL_OFDM_RATES_MASK \
2705 (IL_OFDM_BASIC_RATES_MASK | \
2706 RATE_9M_MASK | \
2707 RATE_18M_MASK | \
2708 RATE_36M_MASK | \
2709 RATE_48M_MASK | \
2710 RATE_54M_MASK)
2711
2712#define IL_BASIC_RATES_MASK \
2713 (IL_OFDM_BASIC_RATES_MASK | \
2714 IL_CCK_BASIC_RATES_MASK)
2715
2716#define RATES_MASK ((1 << RATE_COUNT) - 1)
2717#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2718
2719#define IL_INVALID_VALUE -1
2720
2721#define IL_MIN_RSSI_VAL -100
2722#define IL_MAX_RSSI_VAL 0
2723
2724/* These values specify how many Tx frame attempts before
2725 * searching for a new modulation mode */
2726#define IL_LEGACY_FAILURE_LIMIT 160
2727#define IL_LEGACY_SUCCESS_LIMIT 480
2728#define IL_LEGACY_TBL_COUNT 160
2729
2730#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2731#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2732#define IL_NONE_LEGACY_TBL_COUNT 1500
2733
2734/* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2735#define IL_RS_GOOD_RATIO 12800 /* 100% */
2736#define RATE_SCALE_SWITCH 10880 /* 85% */
2737#define RATE_HIGH_TH 10880 /* 85% */
2738#define RATE_INCREASE_TH 6400 /* 50% */
2739#define RATE_DECREASE_TH 1920 /* 15% */
2740
2741/* possible actions when in legacy mode */
2742#define IL_LEGACY_SWITCH_ANTENNA1 0
2743#define IL_LEGACY_SWITCH_ANTENNA2 1
2744#define IL_LEGACY_SWITCH_SISO 2
2745#define IL_LEGACY_SWITCH_MIMO2_AB 3
2746#define IL_LEGACY_SWITCH_MIMO2_AC 4
2747#define IL_LEGACY_SWITCH_MIMO2_BC 5
2748
2749/* possible actions when in siso mode */
2750#define IL_SISO_SWITCH_ANTENNA1 0
2751#define IL_SISO_SWITCH_ANTENNA2 1
2752#define IL_SISO_SWITCH_MIMO2_AB 2
2753#define IL_SISO_SWITCH_MIMO2_AC 3
2754#define IL_SISO_SWITCH_MIMO2_BC 4
2755#define IL_SISO_SWITCH_GI 5
2756
2757/* possible actions when in mimo mode */
2758#define IL_MIMO2_SWITCH_ANTENNA1 0
2759#define IL_MIMO2_SWITCH_ANTENNA2 1
2760#define IL_MIMO2_SWITCH_SISO_A 2
2761#define IL_MIMO2_SWITCH_SISO_B 3
2762#define IL_MIMO2_SWITCH_SISO_C 4
2763#define IL_MIMO2_SWITCH_GI 5
2764
2765#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2766
2767#define IL_ACTION_LIMIT 3 /* # possible actions */
2768
2769#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
2770
2771/* load per tid defines for A-MPDU activation */
2772#define IL_AGG_TPT_THREHOLD 0
2773#define IL_AGG_LOAD_THRESHOLD 10
2774#define IL_AGG_ALL_TID 0xff
2775#define TID_QUEUE_CELL_SPACING 50 /*mS */
2776#define TID_QUEUE_MAX_SIZE 20
2777#define TID_ROUND_VALUE 5 /* mS */
2778#define TID_MAX_LOAD_COUNT 8
2779
2780#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2781#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2782
2783extern const struct il_rate_info il_rates[RATE_COUNT];
2784
2785enum il_table_type {
2786 LQ_NONE,
e7392364 2787 LQ_G, /* legacy types */
3fbbf9a8 2788 LQ_A,
e7392364 2789 LQ_SISO, /* high-throughput types */
3fbbf9a8
SG		 2790 LQ_MIMO2,
2791 LQ_MAX,
2792};
2793
2794#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2795#define is_siso(tbl) ((tbl) == LQ_SISO)
2796#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2797#define is_mimo(tbl) (is_mimo2(tbl))
2798#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2799#define is_a_band(tbl) ((tbl) == LQ_A)
2800#define is_g_and(tbl) ((tbl) == LQ_G)
2801
2802#define ANT_NONE 0x0
2803#define ANT_A BIT(0)
2804#define ANT_B BIT(1)
2805#define ANT_AB (ANT_A | ANT_B)
2806#define ANT_C BIT(2)
2807#define ANT_AC (ANT_A | ANT_C)
2808#define ANT_BC (ANT_B | ANT_C)
2809#define ANT_ABC (ANT_AB | ANT_C)
2810
2811#define IL_MAX_MCS_DISPLAY_SIZE 12
2812
2813struct il_rate_mcs_info {
e7392364
SG		 2814 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2815 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
3fbbf9a8
SG		 2816};
2817
2818/**
2819 * struct il_rate_scale_data -- tx success history for one rate
2820 */
2821struct il_rate_scale_data {
2822 u64 data; /* bitmap of successful frames */
2823 s32 success_counter; /* number of frames successful */
2824 s32 success_ratio; /* per-cent * 128 */
2825 s32 counter; /* number of frames attempted */
2826 s32 average_tpt; /* success ratio * expected throughput */
2827 unsigned long stamp;
2828};
2829
2830/**
2831 * struct il_scale_tbl_info -- tx params and success history for all rates
2832 *
2833 * There are two of these in struct il_lq_sta,
2834 * one for "active", and one for "search".
2835 */
2836struct il_scale_tbl_info {
2837 enum il_table_type lq_type;
2838 u8 ant_type;
e7392364
SG		 2839 u8 is_SGI; /* 1 = short guard interval */
2840 u8 is_ht40; /* 1 = 40 MHz channel width */
2841 u8 is_dup; /* 1 = duplicated data streams */
2842 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2843 u8 max_search; /* maximun number of tables we can search */
3fbbf9a8 2844 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
e7392364
SG		 2845 u32 current_rate; /* rate_n_flags, uCode API format */
2846 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
3fbbf9a8
SG		 2847};
2848
2849struct il_traffic_load {
2850 unsigned long time_stamp; /* age of the oldest stats */
e7392364 2851 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
3fbbf9a8 2852 * slice */
e7392364
SG		 2853 u32 total; /* total num of packets during the
2854 * last TID_MAX_TIME_DIFF */
2855 u8 queue_count; /* number of queues that has
2856 * been used since the last cleanup */
2857 u8 head; /* start of the circular buffer */
3fbbf9a8
SG		 2858};
2859
2860/**
2861 * struct il_lq_sta -- driver's rate scaling ilate structure
2862 *
2863 * Pointer to this gets passed back and forth between driver and mac80211.
2864 */
2865struct il_lq_sta {
2866 u8 active_tbl; /* idx of active table, range 0-1 */
2867 u8 enable_counter; /* indicates HT mode */
2868 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
2869 u8 search_better_tbl; /* 1: currently trying alternate mode */
2870 s32 last_tpt;
2871
2872 /* The following determine when to search for a new mode */
2873 u32 table_count_limit;
2874 u32 max_failure_limit; /* # failed frames before new search */
2875 u32 max_success_limit; /* # successful frames before new search */
2876 u32 table_count;
2877 u32 total_failed; /* total failed frames, any/all rates */
2878 u32 total_success; /* total successful frames, any/all rates */
2879 u64 flush_timer; /* time staying in mode before new search */
2880
2881 u8 action_counter; /* # mode-switch actions tried */
2882 u8 is_green;
2883 u8 is_dup;
2884 enum ieee80211_band band;
2885
2886 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2887 u32 supp_rates;
2888 u16 active_legacy_rate;
2889 u16 active_siso_rate;
2890 u16 active_mimo2_rate;
e7392364 2891 s8 max_rate_idx; /* Max rate set by user */
3fbbf9a8
SG		 2892 u8 missed_rate_counter;
2893
2894 struct il_link_quality_cmd lq;
e7392364 2895 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
3fbbf9a8
SG		 2896 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2897 u8 tx_agg_tid_en;
2898#ifdef CONFIG_MAC80211_DEBUGFS
2899 struct dentry *rs_sta_dbgfs_scale_table_file;
2900 struct dentry *rs_sta_dbgfs_stats_table_file;
2901 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2902 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2903 u32 dbg_fixed_rate;
2904#endif
2905 struct il_priv *drv;
2906
2907 /* used to be in sta_info */
2908 int last_txrate_idx;
2909 /* last tx rate_n_flags */
2910 u32 last_rate_n_flags;
2911 /* packets destined for this STA are aggregated */
2912 u8 is_agg;
2913};
2914
2915/*
2916 * il_station_priv: Driver's ilate station information
2917 *
2918 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2919 * in the structure for use by driver. This structure is places in that
2920 * space.
2921 *
2922 * The common struct MUST be first because it is shared between
2923 * 3945 and 4965!
2924 */
2925struct il_station_priv {
2926 struct il_station_priv_common common;
2927 struct il_lq_sta lq_sta;
2928 atomic_t pending_frames;
2929 bool client;
2930 bool asleep;
2931};
2932
e7392364
SG		 2933static inline u8
2934il4965_num_of_ant(u8 m)
3fbbf9a8
SG		 2935{
2936 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2937}
2938
e7392364
SG		 2939static inline u8
2940il4965_first_antenna(u8 mask)
3fbbf9a8
SG		 2941{
2942 if (mask & ANT_A)
2943 return ANT_A;
2944 if (mask & ANT_B)
2945 return ANT_B;
2946 return ANT_C;
2947}
2948
3fbbf9a8
SG		 2949/**
2950 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
2951 *
2952 * The specific throughput table used is based on the type of network
2953 * the associated with, including A, B, G, and G w/ TGG protection
2954 */
2955extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2956
2957/* Initialize station's rate scaling information after adding station */
e7392364
SG		 2958extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2959 u8 sta_id);
2960extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2961 u8 sta_id);
3fbbf9a8
SG		 2962
2963/**
2964 * il_rate_control_register - Register the rate control algorithm callbacks
2965 *
2966 * Since the rate control algorithm is hardware specific, there is no need
2967 * or reason to place it as a stand alone module. The driver can call
2968 * il_rate_control_register in order to register the rate control callbacks
2969 * with the mac80211 subsystem. This should be performed prior to calling
2970 * ieee80211_register_hw
2971 *
2972 */
2973extern int il4965_rate_control_register(void);
2974extern int il3945_rate_control_register(void);
2975
2976/**
2977 * il_rate_control_unregister - Unregister the rate control callbacks
2978 *
2979 * This should be called after calling ieee80211_unregister_hw, but before
2980 * the driver is unloaded.
2981 */
2982extern void il4965_rate_control_unregister(void);
2983extern void il3945_rate_control_unregister(void);
2984
99412002
SG		 2985extern int il_power_update_mode(struct il_priv *il, bool force);
2986extern void il_power_initialize(struct il_priv *il);
47ef694d 2987
f02579e3
SG		 2988extern u32 il_debug_level;
2989
2990#ifdef CONFIG_IWLEGACY_DEBUG
2991/*
2992 * il_get_debug_level: Return active debug level for device
2993 *
2994 * Using sysfs it is possible to set per device debug level. This debug
2995 * level will be used if set, otherwise the global debug level which can be
2996 * set via module parameter is used.
2997 */
e7392364
SG		 2998static inline u32
2999il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3000{
3001 if (il->debug_level)
3002 return il->debug_level;
3003 else
3004 return il_debug_level;
3005}
3006#else
e7392364
SG		 3007static inline u32
3008il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3009{
3010 return il_debug_level;
3011}
3012#endif
3013
3014#define il_print_hex_error(il, p, len) \
3015do { \
3016 print_hex_dump(KERN_ERR, "iwl data: ", \
3017 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3018} while (0)
3019
3020#ifdef CONFIG_IWLEGACY_DEBUG
3021#define IL_DBG(level, fmt, args...) \
3022do { \
3023 if (il_get_debug_level(il) & level) \
3024 dev_printk(KERN_ERR, &il->hw->wiphy->dev, \
3025 "%c %s " fmt, in_interrupt() ? 'I' : 'U', \
3026 __func__ , ## args); \
3027} while (0)
3028
1722f8e1 3029#define il_print_hex_dump(il, level, p, len) \
f02579e3
SG		 3030do { \
3031 if (il_get_debug_level(il) & level) \
3032 print_hex_dump(KERN_DEBUG, "iwl data: ", \
3033 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3034} while (0)
3035
3036#else
3037#define IL_DBG(level, fmt, args...)
e7392364
SG		 3038static inline void
3039il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
3040{
3041}
3042#endif /* CONFIG_IWLEGACY_DEBUG */
f02579e3
SG		 3043
3044#ifdef CONFIG_IWLEGACY_DEBUGFS
3045int il_dbgfs_register(struct il_priv *il, const char *name);
3046void il_dbgfs_unregister(struct il_priv *il);
3047#else
3048static inline int
3049il_dbgfs_register(struct il_priv *il, const char *name)
3050{
3051 return 0;
3052}
e7392364
SG		 3053
3054static inline void
3055il_dbgfs_unregister(struct il_priv *il)
f02579e3
SG		 3056{
3057}
e7392364 3058#endif /* CONFIG_IWLEGACY_DEBUGFS */
f02579e3
SG		 3059
3060/*
3061 * To use the debug system:
3062 *
3063 * If you are defining a new debug classification, simply add it to the #define
3064 * list here in the form of
3065 *
3066 * #define IL_DL_xxxx VALUE
3067 *
3068 * where xxxx should be the name of the classification (for example, WEP).
3069 *
3070 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
3071 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
3072 * to send output to that classification.
3073 *
3074 * The active debug levels can be accessed via files
3075 *
1722f8e1 3076 * /sys/module/iwl4965/parameters/debug
f02579e3 3077 * /sys/module/iwl3945/parameters/debug
1722f8e1 3078 * /sys/class/net/wlan0/device/debug_level
f02579e3
SG		 3079 *
3080 * when CONFIG_IWLEGACY_DEBUG=y.
3081 */
3082
3083/* 0x0000000F - 0x00000001 */
3084#define IL_DL_INFO (1 << 0)
3085#define IL_DL_MAC80211 (1 << 1)
3086#define IL_DL_HCMD (1 << 2)
3087#define IL_DL_STATE (1 << 3)
3088/* 0x000000F0 - 0x00000010 */
3089#define IL_DL_MACDUMP (1 << 4)
3090#define IL_DL_HCMD_DUMP (1 << 5)
3091#define IL_DL_EEPROM (1 << 6)
3092#define IL_DL_RADIO (1 << 7)
3093/* 0x00000F00 - 0x00000100 */
3094#define IL_DL_POWER (1 << 8)
3095#define IL_DL_TEMP (1 << 9)
3096#define IL_DL_NOTIF (1 << 10)
3097#define IL_DL_SCAN (1 << 11)
3098/* 0x0000F000 - 0x00001000 */
3099#define IL_DL_ASSOC (1 << 12)
3100#define IL_DL_DROP (1 << 13)
3101#define IL_DL_TXPOWER (1 << 14)
3102#define IL_DL_AP (1 << 15)
3103/* 0x000F0000 - 0x00010000 */
3104#define IL_DL_FW (1 << 16)
3105#define IL_DL_RF_KILL (1 << 17)
3106#define IL_DL_FW_ERRORS (1 << 18)
3107#define IL_DL_LED (1 << 19)
3108/* 0x00F00000 - 0x00100000 */
3109#define IL_DL_RATE (1 << 20)
3110#define IL_DL_CALIB (1 << 21)
3111#define IL_DL_WEP (1 << 22)
3112#define IL_DL_TX (1 << 23)
3113/* 0x0F000000 - 0x01000000 */
3114#define IL_DL_RX (1 << 24)
3115#define IL_DL_ISR (1 << 25)
3116#define IL_DL_HT (1 << 26)
3117/* 0xF0000000 - 0x10000000 */
3118#define IL_DL_11H (1 << 28)
3119#define IL_DL_STATS (1 << 29)
3120#define IL_DL_TX_REPLY (1 << 30)
3121#define IL_DL_QOS (1 << 31)
3122
3123#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3124#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3125#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3126#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3127#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3128#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3129#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3130#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3131#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3132#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3133#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3134#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3135#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3136#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3137#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3138#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3139#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3140#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3141#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3142#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3143#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3144#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3145#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3146#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3147#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3148#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3149#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3150#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3151#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3152
e2ebc833 3153#endif /* __il_core_h__ */
Linux kernel - Deliverables
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