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iwlegacy: remove il_setup_interface()
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.h
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
e94a4099 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
be663ab6 4 *
e94a4099
SG		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
be663ab6
WYG		 7 * published by the Free Software Foundation.
8 *
e94a4099
SG		 9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
be663ab6 13 *
e94a4099
SG		 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
be663ab6 17 *
e94a4099
SG		 18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
be663ab6
WYG		 20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
e94a4099
SG		 25 *****************************************************************************/
26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
e7392364 30#include <linux/pci.h> /* for struct pci_device_id */
e94a4099
SG		 31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
17d4eca6 34#include <linux/io.h>
47ef694d 35#include <net/mac80211.h>
e94a4099
SG		 36#include <net/ieee80211_radiotap.h>
37
99412002 38#include "commands.h"
e94a4099 39#include "csr.h"
e8c39d4e 40#include "prph.h"
e94a4099
SG		 41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
f02579e3
SG		 46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
e94a4099
SG		 50#define RX_QUEUE_SIZE 256
51#define RX_QUEUE_MASK 255
52#define RX_QUEUE_SIZE_LOG 8
53
54/*
55 * RX related structures and functions
56 */
57#define RX_FREE_BUFFERS 64
58#define RX_LOW_WATERMARK 8
59
60#define U32_PAD(n) ((4-(n))&0x3)
61
62/* CT-KILL constants */
e7392364 63#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
e94a4099
SG		 64
65/* Default noise level to report when noise measurement is not available.
66 * This may be because we're:
67 * 1) Not associated (4965, no beacon stats being sent to driver)
68 * 2) Scanning (noise measurement does not apply to associated channel)
69 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
70 * Use default noise value of -127 ... this is below the range of measurable
71 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
72 * Also, -127 works better than 0 when averaging frames with/without
73 * noise info (e.g. averaging might be done in app); measured dBm values are
74 * always negative ... using a negative value as the default keeps all
75 * averages within an s8's (used in some apps) range of negative values. */
76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
77
78/*
79 * RTS threshold here is total size [2347] minus 4 FCS bytes
80 * Per spec:
81 * a value of 0 means RTS on all data/management packets
82 * a value > max MSDU size means no RTS
83 * else RTS for data/management frames where MPDU is larger
84 * than RTS value.
85 */
86#define DEFAULT_RTS_THRESHOLD 2347U
87#define MIN_RTS_THRESHOLD 0U
88#define MAX_RTS_THRESHOLD 2347U
89#define MAX_MSDU_SIZE 2304U
90#define MAX_MPDU_SIZE 2346U
91#define DEFAULT_BEACON_INTERVAL 100U
92#define DEFAULT_SHORT_RETRY_LIMIT 7U
93#define DEFAULT_LONG_RETRY_LIMIT 4U
94
95struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99};
100
101#define rxb_addr(r) page_address(r->page)
102
103/* defined below */
104struct il_device_cmd;
105
106struct il_cmd_meta {
107 /* only for SYNC commands, iff the reply skb is wanted */
108 struct il_host_cmd *source;
109 /*
110 * only for ASYNC commands
111 * (which is somewhat stupid -- look at common.c for instance
112 * which duplicates a bunch of code because the callback isn't
113 * invoked for SYNC commands, if it were and its result passed
114 * through it would be simpler...)
115 */
1722f8e1
SG		 116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
e94a4099
SG		 118
119 /* The CMD_SIZE_HUGE flag bit indicates that the command
120 * structure is stored at the end of the shared queue memory. */
121 u32 flags;
122
e7392364
SG		 123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
e94a4099
SG		 125};
126
127/*
128 * Generic queue structure
129 *
130 * Contains common data for Rx and Tx queues
131 */
132struct il_queue {
e7392364
SG		 133 int n_bd; /* number of BDs in this queue */
134 int write_ptr; /* 1-st empty entry (idx) host_w */
135 int read_ptr; /* last used entry (idx) host_r */
e94a4099 136 /* use for monitoring and recovering the stuck queue */
e7392364
SG		 137 dma_addr_t dma_addr; /* physical addr for BD's */
138 int n_win; /* safe queue win */
e94a4099 139 u32 id;
e7392364
SG		 140 int low_mark; /* low watermark, resume queue if free
141 * space more than this */
142 int high_mark; /* high watermark, stop queue if free
143 * space less than this */
e94a4099
SG		 144};
145
146/* One for each TFD */
147struct il_tx_info {
148 struct sk_buff *skb;
149 struct il_rxon_context *ctx;
150};
151
152/**
153 * struct il_tx_queue - Tx Queue for DMA
154 * @q: generic Rx/Tx queue descriptor
155 * @bd: base of circular buffer of TFDs
156 * @cmd: array of command/TX buffer pointers
157 * @meta: array of meta data for each command/tx buffer
158 * @dma_addr_cmd: physical address of cmd/tx buffer array
159 * @txb: array of per-TFD driver data
160 * @time_stamp: time (in jiffies) of last read_ptr change
161 * @need_update: indicates need to update read/write idx
162 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
163 *
164 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
165 * descriptors) and required locking structures.
166 */
167#define TFD_TX_CMD_SLOTS 256
168#define TFD_CMD_SLOTS 32
169
170struct il_tx_queue {
171 struct il_queue q;
172 void *tfds;
173 struct il_device_cmd **cmd;
174 struct il_cmd_meta *meta;
175 struct il_tx_info *txb;
176 unsigned long time_stamp;
177 u8 need_update;
178 u8 sched_retry;
179 u8 active;
180 u8 swq_id;
181};
182
47ef694d
SG		 183/*
184 * EEPROM access time values:
185 *
186 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
187 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
188 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
189 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
190 */
e7392364 191#define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
47ef694d 192
e7392364
SG		 193#define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
194#define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
47ef694d
SG		 195
196/*
197 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
198 *
199 * IBSS and/or AP operation is allowed *only* on those channels with
200 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
201 * RADAR detection is not supported by the 4965 driver, but is a
202 * requirement for establishing a new network for legal operation on channels
203 * requiring RADAR detection or restricting ACTIVE scanning.
204 *
205 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
206 * It only indicates that 20 MHz channel use is supported; HT40 channel
207 * usage is indicated by a separate set of regulatory flags for each
208 * HT40 channel pair.
209 *
210 * NOTE: Using a channel inappropriately will result in a uCode error!
211 */
212#define IL_NUM_TX_CALIB_GROUPS 5
213enum {
214 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
e7392364 215 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
47ef694d
SG		 216 /* Bit 2 Reserved */
217 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
218 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
e7392364 219 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
47ef694d
SG		 220 /* Bit 6 Reserved (was Narrow Channel) */
221 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
222};
223
224/* SKU Capabilities */
225/* 3945 only */
226#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
227#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
228
229/* *regulatory* channel data format in eeprom, one for each channel.
230 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
231struct il_eeprom_channel {
232 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
233 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
234} __packed;
235
236/* 3945 Specific */
237#define EEPROM_3945_EEPROM_VERSION (0x2f)
238
239/* 4965 has two radio transmitters (and 3 radio receivers) */
240#define EEPROM_TX_POWER_TX_CHAINS (2)
241
242/* 4965 has room for up to 8 sets of txpower calibration data */
243#define EEPROM_TX_POWER_BANDS (8)
244
245/* 4965 factory calibration measures txpower gain settings for
246 * each of 3 target output levels */
247#define EEPROM_TX_POWER_MEASUREMENTS (3)
248
249/* 4965 Specific */
250/* 4965 driver does not work with txpower calibration version < 5 */
251#define EEPROM_4965_TX_POWER_VERSION (5)
252#define EEPROM_4965_EEPROM_VERSION (0x2f)
e7392364
SG		 253#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
254#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
255#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
256#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
47ef694d
SG		 257
258/* 2.4 GHz */
259extern const u8 il_eeprom_band_1[14];
260
261/*
262 * factory calibration data for one txpower level, on one channel,
263 * measured on one of the 2 tx chains (radio transmitter and associated
264 * antenna). EEPROM contains:
265 *
266 * 1) Temperature (degrees Celsius) of device when measurement was made.
267 *
268 * 2) Gain table idx used to achieve the target measurement power.
269 * This refers to the "well-known" gain tables (see 4965.h).
270 *
271 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
272 *
273 * 4) RF power amplifier detector level measurement (not used).
274 */
275struct il_eeprom_calib_measure {
276 u8 temperature; /* Device temperature (Celsius) */
277 u8 gain_idx; /* Index into gain table */
278 u8 actual_pow; /* Measured RF output power, half-dBm */
279 s8 pa_det; /* Power amp detector level (not used) */
280} __packed;
281
47ef694d
SG		 282/*
283 * measurement set for one channel. EEPROM contains:
284 *
285 * 1) Channel number measured
286 *
287 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
288 * (a.k.a. "tx chains") (6 measurements altogether)
289 */
290struct il_eeprom_calib_ch_info {
291 u8 ch_num;
292 struct il_eeprom_calib_measure
e7392364
SG		 293 measurements[EEPROM_TX_POWER_TX_CHAINS]
294 [EEPROM_TX_POWER_MEASUREMENTS];
47ef694d
SG		 295} __packed;
296
297/*
298 * txpower subband info.
299 *
300 * For each frequency subband, EEPROM contains the following:
301 *
302 * 1) First and last channels within range of the subband. "0" values
303 * indicate that this sample set is not being used.
304 *
305 * 2) Sample measurement sets for 2 channels close to the range endpoints.
306 */
307struct il_eeprom_calib_subband_info {
e7392364
SG		 308 u8 ch_from; /* channel number of lowest channel in subband */
309 u8 ch_to; /* channel number of highest channel in subband */
47ef694d
SG		 310 struct il_eeprom_calib_ch_info ch1;
311 struct il_eeprom_calib_ch_info ch2;
312} __packed;
313
47ef694d
SG		 314/*
315 * txpower calibration info. EEPROM contains:
316 *
317 * 1) Factory-measured saturation power levels (maximum levels at which
318 * tx power amplifier can output a signal without too much distortion).
319 * There is one level for 2.4 GHz band and one for 5 GHz band. These
320 * values apply to all channels within each of the bands.
321 *
322 * 2) Factory-measured power supply voltage level. This is assumed to be
323 * constant (i.e. same value applies to all channels/bands) while the
324 * factory measurements are being made.
325 *
326 * 3) Up to 8 sets of factory-measured txpower calibration values.
327 * These are for different frequency ranges, since txpower gain
328 * characteristics of the analog radio circuitry vary with frequency.
329 *
330 * Not all sets need to be filled with data;
331 * struct il_eeprom_calib_subband_info contains range of channels
332 * (0 if unused) for each set of data.
333 */
334struct il_eeprom_calib_info {
335 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
336 u8 saturation_power52; /* half-dBm */
337 __le16 voltage; /* signed */
e7392364 338 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
47ef694d
SG		 339} __packed;
340
47ef694d
SG		 341/* General */
342#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
343#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
344#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
345#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
346#define EEPROM_VERSION (2*0x44) /* 2 bytes */
347#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
348#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
349#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
350#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
351#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
352
353/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
e7392364
SG		 354#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
355#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
356#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
357#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
358#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
359#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
47ef694d
SG		 360
361#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
362#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
363
364/*
365 * Per-channel regulatory data.
366 *
367 * Each channel that *might* be supported by iwl has a fixed location
368 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
369 * txpower (MSB).
370 *
371 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
372 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
373 *
374 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
375 */
e7392364 376#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
47ef694d
SG		 377#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
378#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
379
380/*
381 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
382 * 5.0 GHz channels 7, 8, 11, 12, 16
383 * (4915-5080MHz) (none of these is ever supported)
384 */
385#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
386#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
387
388/*
389 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
390 * (5170-5320MHz)
391 */
392#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
393#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
394
395/*
396 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
397 * (5500-5700MHz)
398 */
399#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
400#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
401
402/*
403 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
404 * (5725-5825MHz)
405 */
406#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
407#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
408
409/*
410 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
411 *
412 * The channel listed is the center of the lower 20 MHz half of the channel.
413 * The overall center frequency is actually 2 channels (10 MHz) above that,
414 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
415 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
416 * and the overall HT40 channel width centers on channel 3.
417 *
418 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
419 * control channel to which to tune. RXON also specifies whether the
420 * control channel is the upper or lower half of a HT40 channel.
421 *
422 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
423 */
424#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
425
426/*
427 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
428 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
429 */
430#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
431
432#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
433
434struct il_eeprom_ops {
435 const u32 regulatory_bands[7];
1722f8e1
SG		 436 int (*acquire_semaphore) (struct il_priv *il);
437 void (*release_semaphore) (struct il_priv *il);
47ef694d
SG		 438};
439
47ef694d
SG		 440int il_eeprom_init(struct il_priv *il);
441void il_eeprom_free(struct il_priv *il);
e7392364 442const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
47ef694d
SG		 443u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
444int il_init_channel_map(struct il_priv *il);
445void il_free_channel_map(struct il_priv *il);
e7392364
SG		 446const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
447 enum ieee80211_band band,
448 u16 channel);
47ef694d 449
e94a4099
SG		 450#define IL_NUM_SCAN_RATES (2)
451
452struct il4965_channel_tgd_info {
453 u8 type;
454 s8 max_power;
455};
456
457struct il4965_channel_tgh_info {
458 s64 last_radar_time;
459};
460
461#define IL4965_MAX_RATE (33)
462
463struct il3945_clip_group {
464 /* maximum power level to prevent clipping for each rate, derived by
465 * us from this band's saturation power in EEPROM */
466 const s8 clip_powers[IL_MAX_RATES];
467};
468
469/* current Tx power values to use, one for each rate for each channel.
470 * requested power is limited by:
471 * -- regulatory EEPROM limits for this channel
472 * -- hardware capabilities (clip-powers)
473 * -- spectrum management
474 * -- user preference (e.g. iwconfig)
475 * when requested power is set, base power idx must also be set. */
476struct il3945_channel_power_info {
477 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
478 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
479 s8 base_power_idx; /* gain idx for power at factory temp. */
480 s8 requested_power; /* power (dBm) requested for this chnl/rate */
481};
482
483/* current scan Tx power values to use, one for each scan rate for each
484 * channel. */
485struct il3945_scan_power_info {
486 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
487 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
488 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
489};
490
491/*
492 * One for each channel, holds all channel setup data
493 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
494 * with one another!
495 */
496struct il_channel_info {
497 struct il4965_channel_tgd_info tgd;
498 struct il4965_channel_tgh_info tgh;
499 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
500 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
501 * HT40 channel */
502
e7392364
SG		 503 u8 channel; /* channel number */
504 u8 flags; /* flags copied from EEPROM */
505 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
506 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
507 s8 min_power; /* always 0 */
508 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
e94a4099 509
e7392364
SG		 510 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
511 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
e94a4099
SG		 512 enum ieee80211_band band;
513
514 /* HT40 channel info */
515 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
516 u8 ht40_flags; /* flags copied from EEPROM */
e7392364 517 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
e94a4099
SG		 518
519 /* Radio/DSP gain settings for each "normal" data Tx rate.
520 * These include, in addition to RF and DSP gain, a few fields for
521 * remembering/modifying gain settings (idxes). */
522 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
523
524 /* Radio/DSP gain settings for each scan rate, for directed scans. */
525 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
526};
527
528#define IL_TX_FIFO_BK 0 /* shared */
529#define IL_TX_FIFO_BE 1
530#define IL_TX_FIFO_VI 2 /* shared */
531#define IL_TX_FIFO_VO 3
532#define IL_TX_FIFO_UNUSED -1
533
534/* Minimum number of queues. MAX_NUM is defined in hw specific files.
535 * Set the minimum to accommodate the 4 standard TX queues, 1 command
536 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
537#define IL_MIN_NUM_QUEUES 10
538
539#define IL_DEFAULT_CMD_QUEUE_NUM 4
540
541#define IEEE80211_DATA_LEN 2304
542#define IEEE80211_4ADDR_LEN 30
543#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
544#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
545
546struct il_frame {
547 union {
548 struct ieee80211_hdr frame;
549 struct il_tx_beacon_cmd beacon;
550 u8 raw[IEEE80211_FRAME_LEN];
551 u8 cmd[360];
552 } u;
553 struct list_head list;
554};
555
556#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
557#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
558#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
559
560enum {
561 CMD_SYNC = 0,
562 CMD_SIZE_NORMAL = 0,
563 CMD_NO_SKB = 0,
564 CMD_SIZE_HUGE = (1 << 0),
565 CMD_ASYNC = (1 << 1),
566 CMD_WANT_SKB = (1 << 2),
567 CMD_MAPPED = (1 << 3),
568};
569
570#define DEF_CMD_PAYLOAD_SIZE 320
571
572/**
573 * struct il_device_cmd
574 *
575 * For allocation of the command and tx queues, this establishes the overall
576 * size of the largest command we send to uCode, except for a scan command
577 * (which is relatively huge; space is allocated separately).
578 */
579struct il_device_cmd {
580 struct il_cmd_header hdr; /* uCode API */
581 union {
582 u32 flags;
583 u8 val8;
584 u16 val16;
585 u32 val32;
586 struct il_tx_cmd tx;
587 u8 payload[DEF_CMD_PAYLOAD_SIZE];
588 } __packed cmd;
589} __packed;
590
591#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
592
e94a4099
SG		 593struct il_host_cmd {
594 const void *data;
595 unsigned long reply_page;
1722f8e1
SG		 596 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
597 struct il_rx_pkt *pkt);
e94a4099
SG		 598 u32 flags;
599 u16 len;
600 u8 id;
601};
602
603#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
604#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
605#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
606
607/**
608 * struct il_rx_queue - Rx queue
609 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
610 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
611 * @read: Shared idx to newest available Rx buffer
612 * @write: Shared idx to oldest written Rx packet
613 * @free_count: Number of pre-allocated buffers in rx_free
614 * @rx_free: list of free SKBs for use
615 * @rx_used: List of Rx buffers with no SKB
616 * @need_update: flag to indicate we need to update read/write idx
617 * @rb_stts: driver's pointer to receive buffer status
618 * @rb_stts_dma: bus address of receive buffer status
619 *
620 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
621 */
622struct il_rx_queue {
623 __le32 *bd;
624 dma_addr_t bd_dma;
625 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
626 struct il_rx_buf *queue[RX_QUEUE_SIZE];
627 u32 read;
628 u32 write;
629 u32 free_count;
630 u32 write_actual;
631 struct list_head rx_free;
632 struct list_head rx_used;
633 int need_update;
634 struct il_rb_status *rb_stts;
635 dma_addr_t rb_stts_dma;
636 spinlock_t lock;
637};
638
639#define IL_SUPPORTED_RATES_IE_LEN 8
640
641#define MAX_TID_COUNT 9
642
643#define IL_INVALID_RATE 0xFF
644#define IL_INVALID_VALUE -1
645
646/**
647 * struct il_ht_agg -- aggregation status while waiting for block-ack
648 * @txq_id: Tx queue used for Tx attempt
649 * @frame_count: # frames attempted by Tx command
650 * @wait_for_ba: Expect block-ack before next Tx reply
651 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
652 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
653 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
654 * @rate_n_flags: Rate at which Tx was attempted
655 *
656 * If C_TX indicates that aggregation was attempted, driver must wait
657 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
658 * until block ack arrives.
659 */
660struct il_ht_agg {
661 u16 txq_id;
662 u16 frame_count;
663 u16 wait_for_ba;
664 u16 start_idx;
665 u64 bitmap;
666 u32 rate_n_flags;
667#define IL_AGG_OFF 0
668#define IL_AGG_ON 1
669#define IL_EMPTYING_HW_QUEUE_ADDBA 2
670#define IL_EMPTYING_HW_QUEUE_DELBA 3
671 u8 state;
672};
673
e94a4099 674struct il_tid_data {
e7392364 675 u16 seq_number; /* 4965 only */
e94a4099
SG		 676 u16 tfds_in_queue;
677 struct il_ht_agg agg;
678};
679
680struct il_hw_key {
681 u32 cipher;
682 int keylen;
683 u8 keyidx;
684 u8 key[32];
685};
686
687union il_ht_rate_supp {
688 u16 rates;
689 struct {
690 u8 siso_rate;
691 u8 mimo_rate;
692 };
693};
694
695#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
696#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
697#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
698#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
699#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
700#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
701#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
702
703/*
704 * Maximal MPDU density for TX aggregation
705 * 4 - 2us density
706 * 5 - 4us density
707 * 6 - 8us density
708 * 7 - 16us density
709 */
710#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
711#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
712#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
713#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
714#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
715#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
716#define CFG_HT_MPDU_DENSITY_MIN (0x1)
717
718struct il_ht_config {
719 bool single_chain_sufficient;
e7392364 720 enum ieee80211_smps_mode smps; /* current smps mode */
e94a4099
SG		 721};
722
723/* QoS structures */
724struct il_qos_info {
725 int qos_active;
726 struct il_qosparam_cmd def_qos_parm;
727};
728
729/*
730 * Structure should be accessed with sta_lock held. When station addition
731 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
732 * the commands (il_addsta_cmd and il_link_quality_cmd) without
733 * sta_lock held.
734 */
735struct il_station_entry {
736 struct il_addsta_cmd sta;
737 struct il_tid_data tid[MAX_TID_COUNT];
6aa0c254 738 u8 used;
e94a4099
SG		 739 struct il_hw_key keyinfo;
740 struct il_link_quality_cmd *lq;
741};
742
743struct il_station_priv_common {
744 struct il_rxon_context *ctx;
745 u8 sta_id;
746};
747
e94a4099
SG		 748/**
749 * struct il_vif_priv - driver's ilate per-interface information
750 *
751 * When mac80211 allocates a virtual interface, it can allocate
752 * space for us to put data into.
753 */
754struct il_vif_priv {
755 struct il_rxon_context *ctx;
756 u8 ibss_bssid_sta_id;
757};
758
759/* one for each uCode image (inst/data, boot/init/runtime) */
760struct fw_desc {
761 void *v_addr; /* access by driver */
762 dma_addr_t p_addr; /* access by card's busmaster DMA */
763 u32 len; /* bytes */
764};
765
766/* uCode file layout */
767struct il_ucode_header {
e7392364 768 __le32 ver; /* major/minor/API/serial */
e94a4099
SG		 769 struct {
770 __le32 inst_size; /* bytes of runtime code */
771 __le32 data_size; /* bytes of runtime data */
772 __le32 init_size; /* bytes of init code */
773 __le32 init_data_size; /* bytes of init data */
774 __le32 boot_size; /* bytes of bootstrap code */
e7392364 775 u8 data[0]; /* in same order as sizes */
e94a4099
SG		 776 } v1;
777};
778
779struct il4965_ibss_seq {
780 u8 mac[ETH_ALEN];
781 u16 seq_num;
782 u16 frag_num;
783 unsigned long packet_time;
784 struct list_head list;
785};
786
787struct il_sensitivity_ranges {
788 u16 min_nrg_cck;
789 u16 max_nrg_cck;
790
791 u16 nrg_th_cck;
792 u16 nrg_th_ofdm;
793
794 u16 auto_corr_min_ofdm;
795 u16 auto_corr_min_ofdm_mrc;
796 u16 auto_corr_min_ofdm_x1;
797 u16 auto_corr_min_ofdm_mrc_x1;
798
799 u16 auto_corr_max_ofdm;
800 u16 auto_corr_max_ofdm_mrc;
801 u16 auto_corr_max_ofdm_x1;
802 u16 auto_corr_max_ofdm_mrc_x1;
803
804 u16 auto_corr_max_cck;
805 u16 auto_corr_max_cck_mrc;
806 u16 auto_corr_min_cck;
807 u16 auto_corr_min_cck_mrc;
808
809 u16 barker_corr_th_min;
810 u16 barker_corr_th_min_mrc;
811 u16 nrg_th_cca;
812};
813
e94a4099
SG		 814#define KELVIN_TO_CELSIUS(x) ((x)-273)
815#define CELSIUS_TO_KELVIN(x) ((x)+273)
816
e94a4099
SG		 817/**
818 * struct il_hw_params
b16db50a 819 * @bcast_id: f/w broadcast station ID
e94a4099
SG		 820 * @max_txq_num: Max # Tx queues supported
821 * @dma_chnl_num: Number of Tx DMA/FIFO channels
822 * @scd_bc_tbls_size: size of scheduler byte count tables
823 * @tfd_size: TFD size
824 * @tx/rx_chains_num: Number of TX/RX chains
825 * @valid_tx/rx_ant: usable antennas
826 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
827 * @max_rxq_log: Log-base-2 of max_rxq_size
828 * @rx_page_order: Rx buffer page order
829 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
830 * @max_stations:
831 * @ht40_channel: is 40MHz width possible in band 2.4
832 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
833 * @sw_crypto: 0 for hw, 1 for sw
834 * @max_xxx_size: for ucode uses
835 * @ct_kill_threshold: temperature threshold
836 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
837 * @struct il_sensitivity_ranges: range of sensitivity values
838 */
839struct il_hw_params {
b16db50a 840 u8 bcast_id;
e94a4099
SG		 841 u8 max_txq_num;
842 u8 dma_chnl_num;
843 u16 scd_bc_tbls_size;
844 u32 tfd_size;
e7392364
SG		 845 u8 tx_chains_num;
846 u8 rx_chains_num;
847 u8 valid_tx_ant;
848 u8 valid_rx_ant;
e94a4099
SG		 849 u16 max_rxq_size;
850 u16 max_rxq_log;
851 u32 rx_page_order;
852 u32 rx_wrt_ptr_reg;
e7392364
SG		 853 u8 max_stations;
854 u8 ht40_channel;
855 u8 max_beacon_itrvl; /* in 1024 ms */
e94a4099
SG		 856 u32 max_inst_size;
857 u32 max_data_size;
858 u32 max_bsm_size;
e7392364 859 u32 ct_kill_threshold; /* value in hw-dependent units */
e94a4099
SG		 860 u16 beacon_time_tsf_bits;
861 const struct il_sensitivity_ranges *sens;
862};
863
e94a4099
SG		 864/******************************************************************************
865 *
866 * Functions implemented in core module which are forward declared here
867 * for use by iwl-[4-5].c
868 *
869 * NOTE: The implementation of these functions are not hardware specific
870 * which is why they are in the core module files.
871 *
872 * Naming convention --
873 * il_ <-- Is part of iwlwifi
874 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
875 * il4965_bg_ <-- Called from work queue context
876 * il4965_mac_ <-- mac80211 callback
877 *
878 ****************************************************************************/
879extern void il4965_update_chain_flags(struct il_priv *il);
880extern const u8 il_bcast_addr[ETH_ALEN];
881extern int il_queue_space(const struct il_queue *q);
e7392364
SG		 882static inline int
883il_queue_used(const struct il_queue *q, int i)
e94a4099 884{
e7392364
SG		 885 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
886 i < q->write_ptr) : !(i <
887 q->read_ptr
888 && i >=
889 q->
890 write_ptr);
e94a4099
SG		 891}
892
e7392364
SG		 893static inline u8
894il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
e94a4099
SG		 895{
896 /*
897 * This is for init calibration result and scan command which
898 * required buffer > TFD_MAX_PAYLOAD_SIZE,
899 * the big buffer at end of command array
900 */
901 if (is_huge)
902 return q->n_win; /* must be power of 2 */
903
904 /* Otherwise, use normal size buffers */
905 return idx & (q->n_win - 1);
906}
907
e94a4099
SG		 908struct il_dma_ptr {
909 dma_addr_t dma;
910 void *addr;
911 size_t size;
912};
913
914#define IL_OPERATION_MODE_AUTO 0
915#define IL_OPERATION_MODE_HT_ONLY 1
916#define IL_OPERATION_MODE_MIXED 2
917#define IL_OPERATION_MODE_20MHZ 3
918
919#define IL_TX_CRC_SIZE 4
920#define IL_TX_DELIMITER_SIZE 4
921
922#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
923
924/* Sensitivity and chain noise calibration */
925#define INITIALIZATION_VALUE 0xFFFF
926#define IL4965_CAL_NUM_BEACONS 20
927#define IL_CAL_NUM_BEACONS 16
928#define MAXIMUM_ALLOWED_PATHLOSS 15
929
930#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
931
932#define MAX_FA_OFDM 50
933#define MIN_FA_OFDM 5
934#define MAX_FA_CCK 50
935#define MIN_FA_CCK 5
936
937#define AUTO_CORR_STEP_OFDM 1
938
939#define AUTO_CORR_STEP_CCK 3
940#define AUTO_CORR_MAX_TH_CCK 160
941
942#define NRG_DIFF 2
943#define NRG_STEP_CCK 2
944#define NRG_MARGIN 8
945#define MAX_NUMBER_CCK_NO_FA 100
946
947#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
948
949#define CHAIN_A 0
950#define CHAIN_B 1
951#define CHAIN_C 2
952#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
953#define ALL_BAND_FILTER 0xFF00
954#define IN_BAND_FILTER 0xFF
955#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
956
957#define NRG_NUM_PREV_STAT_L 20
958#define NUM_RX_CHAINS 3
959
960enum il4965_false_alarm_state {
961 IL_FA_TOO_MANY = 0,
962 IL_FA_TOO_FEW = 1,
963 IL_FA_GOOD_RANGE = 2,
964};
965
966enum il4965_chain_noise_state {
e7392364 967 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
e94a4099
SG		 968 IL_CHAIN_NOISE_ACCUMULATE,
969 IL_CHAIN_NOISE_CALIBRATED,
970 IL_CHAIN_NOISE_DONE,
971};
972
973enum il4965_calib_enabled_state {
e7392364 974 IL_CALIB_DISABLED = 0, /* must be 0 */
e94a4099
SG		 975 IL_CALIB_ENABLED = 1,
976};
977
978/*
979 * enum il_calib
980 * defines the order in which results of initial calibrations
981 * should be sent to the runtime uCode
982 */
983enum il_calib {
984 IL_CALIB_MAX,
985};
986
987/* Opaque calibration results */
988struct il_calib_result {
989 void *buf;
990 size_t buf_len;
991};
992
993enum ucode_type {
994 UCODE_NONE = 0,
995 UCODE_INIT,
996 UCODE_RT
997};
998
999/* Sensitivity calib data */
1000struct il_sensitivity_data {
1001 u32 auto_corr_ofdm;
1002 u32 auto_corr_ofdm_mrc;
1003 u32 auto_corr_ofdm_x1;
1004 u32 auto_corr_ofdm_mrc_x1;
1005 u32 auto_corr_cck;
1006 u32 auto_corr_cck_mrc;
1007
1008 u32 last_bad_plcp_cnt_ofdm;
1009 u32 last_fa_cnt_ofdm;
1010 u32 last_bad_plcp_cnt_cck;
1011 u32 last_fa_cnt_cck;
1012
1013 u32 nrg_curr_state;
1014 u32 nrg_prev_state;
1015 u32 nrg_value[10];
e7392364 1016 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
e94a4099
SG		 1017 u32 nrg_silence_ref;
1018 u32 nrg_energy_idx;
1019 u32 nrg_silence_idx;
1020 u32 nrg_th_cck;
1021 s32 nrg_auto_corr_silence_diff;
1022 u32 num_in_cck_no_fa;
1023 u32 nrg_th_ofdm;
1024
1025 u16 barker_corr_th_min;
1026 u16 barker_corr_th_min_mrc;
1027 u16 nrg_th_cca;
1028};
1029
1030/* Chain noise (differential Rx gain) calib data */
1031struct il_chain_noise_data {
1032 u32 active_chains;
1033 u32 chain_noise_a;
1034 u32 chain_noise_b;
1035 u32 chain_noise_c;
1036 u32 chain_signal_a;
1037 u32 chain_signal_b;
1038 u32 chain_signal_c;
1039 u16 beacon_count;
1040 u8 disconn_array[NUM_RX_CHAINS];
1041 u8 delta_gain_code[NUM_RX_CHAINS];
1042 u8 radio_write;
1043 u8 state;
1044};
1045
e7392364 1046#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
e94a4099
SG		 1047#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1048
1049#define IL_TRAFFIC_ENTRIES (256)
1050#define IL_TRAFFIC_ENTRY_SIZE (64)
1051
1052enum {
1053 MEASUREMENT_READY = (1 << 0),
1054 MEASUREMENT_ACTIVE = (1 << 1),
1055};
1056
1057/* interrupt stats */
1058struct isr_stats {
1059 u32 hw;
1060 u32 sw;
1061 u32 err_code;
1062 u32 sch;
1063 u32 alive;
1064 u32 rfkill;
1065 u32 ctkill;
1066 u32 wakeup;
1067 u32 rx;
1068 u32 handlers[IL_CN_MAX];
1069 u32 tx;
1070 u32 unhandled;
1071};
1072
1073/* management stats */
1074enum il_mgmt_stats {
1075 MANAGEMENT_ASSOC_REQ = 0,
1076 MANAGEMENT_ASSOC_RESP,
1077 MANAGEMENT_REASSOC_REQ,
1078 MANAGEMENT_REASSOC_RESP,
1079 MANAGEMENT_PROBE_REQ,
1080 MANAGEMENT_PROBE_RESP,
1081 MANAGEMENT_BEACON,
1082 MANAGEMENT_ATIM,
1083 MANAGEMENT_DISASSOC,
1084 MANAGEMENT_AUTH,
1085 MANAGEMENT_DEAUTH,
1086 MANAGEMENT_ACTION,
1087 MANAGEMENT_MAX,
1088};
1089/* control stats */
1090enum il_ctrl_stats {
e7392364 1091 CONTROL_BACK_REQ = 0,
e94a4099
SG		 1092 CONTROL_BACK,
1093 CONTROL_PSPOLL,
1094 CONTROL_RTS,
1095 CONTROL_CTS,
1096 CONTROL_ACK,
1097 CONTROL_CFEND,
1098 CONTROL_CFENDACK,
1099 CONTROL_MAX,
1100};
1101
1102struct traffic_stats {
1103#ifdef CONFIG_IWLEGACY_DEBUGFS
1104 u32 mgmt[MANAGEMENT_MAX];
1105 u32 ctrl[CONTROL_MAX];
1106 u32 data_cnt;
1107 u64 data_bytes;
1108#endif
1109};
1110
1111/*
1112 * host interrupt timeout value
1113 * used with setting interrupt coalescing timer
1114 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1115 *
1116 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1117 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1118 */
1119#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1120#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1121#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1122#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1123#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1124#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1125
1126#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1127
1128/* TX queue watchdog timeouts in mSecs */
1129#define IL_DEF_WD_TIMEOUT (2000)
1130#define IL_LONG_WD_TIMEOUT (10000)
1131#define IL_MAX_WD_TIMEOUT (120000)
1132
1133struct il_force_reset {
1134 int reset_request_count;
1135 int reset_success_count;
1136 int reset_reject_count;
1137 unsigned long reset_duration;
1138 unsigned long last_force_reset_jiffies;
1139};
1140
1141/* extend beacon time format bit shifting */
1142/*
1143 * for _3945 devices
1144 * bits 31:24 - extended
1145 * bits 23:0 - interval
1146 */
1147#define IL3945_EXT_BEACON_TIME_POS 24
1148/*
1149 * for _4965 devices
1150 * bits 31:22 - extended
1151 * bits 21:0 - interval
1152 */
1153#define IL4965_EXT_BEACON_TIME_POS 22
1154
1155struct il_rxon_context {
1156 struct ieee80211_vif *vif;
e94a4099
SG		 1157};
1158
99412002
SG		 1159struct il_power_mgr {
1160 struct il_powertable_cmd sleep_cmd;
1161 struct il_powertable_cmd sleep_cmd_next;
1162 int debug_sleep_level_override;
1163 bool pci_pm;
1164};
1165
e94a4099
SG		 1166struct il_priv {
1167
1168 /* ieee device used by generic ieee processing code */
1169 struct ieee80211_hw *hw;
1170 struct ieee80211_channel *ieee_channels;
1171 struct ieee80211_rate *ieee_rates;
1172 struct il_cfg *cfg;
1173
1174 /* temporary frame storage list */
1175 struct list_head free_frames;
1176 int frames_count;
1177
1178 enum ieee80211_band band;
1179 int alloc_rxb_page;
1180
1722f8e1
SG		 1181 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1182 struct il_rx_buf *rxb);
e94a4099
SG		 1183
1184 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1185
1186 /* spectrum measurement report caching */
1187 struct il_spectrum_notification measure_report;
1188 u8 measurement_status;
1189
1190 /* ucode beacon time */
1191 u32 ucode_beacon_time;
1192 int missed_beacon_threshold;
1193
1194 /* track IBSS manager (last beacon) status */
1195 u32 ibss_manager;
1196
1197 /* force reset */
1198 struct il_force_reset force_reset;
1199
1200 /* we allocate array of il_channel_info for NIC's valid channels.
1201 * Access via channel # using indirect idx array */
1202 struct il_channel_info *channel_info; /* channel info array */
1203 u8 channel_count; /* # of channels */
1204
1205 /* thermal calibration */
1206 s32 temperature; /* degrees Kelvin */
1207 s32 last_temperature;
1208
1209 /* init calibration results */
1210 struct il_calib_result calib_results[IL_CALIB_MAX];
1211
1212 /* Scan related variables */
1213 unsigned long scan_start;
1214 unsigned long scan_start_tsf;
1215 void *scan_cmd;
1216 enum ieee80211_band scan_band;
1217 struct cfg80211_scan_request *scan_request;
1218 struct ieee80211_vif *scan_vif;
1219 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1220 u8 mgmt_tx_ant;
1221
1222 /* spinlock */
1223 spinlock_t lock; /* protect general shared data */
1224 spinlock_t hcmd_lock; /* protect hcmd */
1225 spinlock_t reg_lock; /* protect hw register access */
1226 struct mutex mutex;
1227
1228 /* basic pci-network driver stuff */
1229 struct pci_dev *pci_dev;
1230
1231 /* pci hardware address support */
1232 void __iomem *hw_base;
e7392364
SG		 1233 u32 hw_rev;
1234 u32 hw_wa_rev;
1235 u8 rev_id;
e94a4099
SG		 1236
1237 /* command queue number */
1238 u8 cmd_queue;
1239
1240 /* max number of station keys */
1241 u8 sta_key_max_num;
1242
1243 /* EEPROM MAC addresses */
1244 struct mac_address addresses[1];
1245
1246 /* uCode images, save to reload in case of failure */
e7392364
SG		 1247 int fw_idx; /* firmware we're trying to load */
1248 u32 ucode_ver; /* version of ucode, copy of
1249 il_ucode.ver */
e94a4099
SG		 1250 struct fw_desc ucode_code; /* runtime inst */
1251 struct fw_desc ucode_data; /* runtime data original */
1252 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1253 struct fw_desc ucode_init; /* initialization inst */
1254 struct fw_desc ucode_init_data; /* initialization data */
1255 struct fw_desc ucode_boot; /* bootstrap inst */
1256 enum ucode_type ucode_type;
1257 u8 ucode_write_complete; /* the image write is complete */
1258 char firmware_name[25];
1259
1260 struct il_rxon_context ctx;
1261
8d44f2bd
SG		 1262 struct il_qos_info qos_data;
1263
1c03c462
SG		 1264 struct {
1265 bool enabled;
1266 bool is_40mhz;
1267 bool non_gf_sta_present;
1268 u8 protection;
1269 u8 extension_chan_offset;
1270 } ht;
1271
c8b03958
SG		 1272 /*
1273 * We declare this const so it can only be
1274 * changed via explicit cast within the
1275 * routines that actually update the physical
1276 * hardware.
1277 */
1278 const struct il_rxon_cmd active;
1279 struct il_rxon_cmd staging;
1280
1281 struct il_rxon_time_cmd timing;
1282
e94a4099
SG		 1283 __le16 switch_channel;
1284
1285 /* 1st responses from initialize and runtime uCode images.
1286 * _4965's initialize alive response contains some calibration data. */
1287 struct il_init_alive_resp card_alive_init;
1288 struct il_alive_resp card_alive;
1289
1290 u16 active_rate;
1291
1292 u8 start_calib;
1293 struct il_sensitivity_data sensitivity_data;
1294 struct il_chain_noise_data chain_noise_data;
1295 __le16 sensitivity_tbl[HD_TBL_SIZE];
1296
1297 struct il_ht_config current_ht_config;
1298
1299 /* Rate scaling data */
1300 u8 retry_rate;
1301
1302 wait_queue_head_t wait_command_queue;
1303
1304 int activity_timer_active;
1305
1306 /* Rx and Tx DMA processing queues */
1307 struct il_rx_queue rxq;
1308 struct il_tx_queue *txq;
1309 unsigned long txq_ctx_active_msk;
e7392364
SG		 1310 struct il_dma_ptr kw; /* keep warm address */
1311 struct il_dma_ptr scd_bc_tbls;
e94a4099
SG		 1312
1313 u32 scd_base_addr; /* scheduler sram base address */
1314
1315 unsigned long status;
1316
1317 /* counts mgmt, ctl, and data packets */
1318 struct traffic_stats tx_stats;
1319 struct traffic_stats rx_stats;
1320
1321 /* counts interrupts */
1322 struct isr_stats isr_stats;
1323
1324 struct il_power_mgr power_data;
1325
1326 /* context information */
e7392364 1327 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
e94a4099
SG		 1328
1329 /* station table variables */
1330
1331 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1332 spinlock_t sta_lock;
1333 int num_stations;
1334 struct il_station_entry stations[IL_STATION_COUNT];
1335 unsigned long ucode_key_table;
1336
1337 /* queue refcounts */
1338#define IL_MAX_HW_QUEUES 32
1339 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1340 /* for each AC */
1341 atomic_t queue_stop_count[4];
1342
1343 /* Indication if ieee80211_ops->open has been called */
1344 u8 is_open;
1345
1346 u8 mac80211_registered;
1347
1348 /* eeprom -- this is in the card's little endian byte order */
1349 u8 *eeprom;
1350 struct il_eeprom_calib_info *calib_info;
1351
1352 enum nl80211_iftype iw_mode;
1353
1354 /* Last Rx'd beacon timestamp */
1355 u64 timestamp;
1356
1357 union {
1358#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1359 struct {
1360 void *shared_virt;
1361 dma_addr_t shared_phys;
1362
1363 struct delayed_work thermal_periodic;
1364 struct delayed_work rfkill_poll;
1365
1366 struct il3945_notif_stats stats;
1367#ifdef CONFIG_IWLEGACY_DEBUGFS
1368 struct il3945_notif_stats accum_stats;
1369 struct il3945_notif_stats delta_stats;
1370 struct il3945_notif_stats max_delta;
1371#endif
1372
1373 u32 sta_supp_rates;
1374 int last_rx_rssi; /* From Rx packet stats */
1375
1376 /* Rx'd packet timing information */
1377 u32 last_beacon_time;
1378 u64 last_tsf;
1379
1380 /*
1381 * each calibration channel group in the
1382 * EEPROM has a derived clip setting for
1383 * each rate.
1384 */
1385 const struct il3945_clip_group clip_groups[5];
1386
1387 } _3945;
1388#endif
1389#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1390 struct {
1391 struct il_rx_phy_res last_phy_res;
1392 bool last_phy_res_valid;
1393
1394 struct completion firmware_loading_complete;
1395
1396 /*
1397 * chain noise reset and gain commands are the
1398 * two extra calibration commands follows the standard
1399 * phy calibration commands
1400 */
1401 u8 phy_calib_chain_noise_reset_cmd;
1402 u8 phy_calib_chain_noise_gain_cmd;
1403
d735f921
SG		 1404 u8 key_mapping_keys;
1405 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1406
e94a4099
SG		 1407 struct il_notif_stats stats;
1408#ifdef CONFIG_IWLEGACY_DEBUGFS
1409 struct il_notif_stats accum_stats;
1410 struct il_notif_stats delta_stats;
1411 struct il_notif_stats max_delta;
1412#endif
1413
1414 } _4965;
1415#endif
1416 };
1417
1418 struct il_hw_params hw_params;
1419
1420 u32 inta_mask;
1421
1422 struct workqueue_struct *workqueue;
1423
1424 struct work_struct restart;
1425 struct work_struct scan_completed;
1426 struct work_struct rx_replenish;
1427 struct work_struct abort_scan;
1428
1429 struct il_rxon_context *beacon_ctx;
1430 struct sk_buff *beacon_skb;
1431
1432 struct work_struct tx_flush;
1433
1434 struct tasklet_struct irq_tasklet;
1435
1436 struct delayed_work init_alive_start;
1437 struct delayed_work alive_start;
1438 struct delayed_work scan_check;
1439
1440 /* TX Power */
1441 s8 tx_power_user_lmt;
1442 s8 tx_power_device_lmt;
1443 s8 tx_power_next;
1444
e94a4099
SG		 1445#ifdef CONFIG_IWLEGACY_DEBUG
1446 /* debugging info */
e7392364
SG		 1447 u32 debug_level; /* per device debugging will override global
1448 il_debug_level if set */
1449#endif /* CONFIG_IWLEGACY_DEBUG */
e94a4099
SG		 1450#ifdef CONFIG_IWLEGACY_DEBUGFS
1451 /* debugfs */
1452 u16 tx_traffic_idx;
1453 u16 rx_traffic_idx;
1454 u8 *tx_traffic;
1455 u8 *rx_traffic;
1456 struct dentry *debugfs_dir;
1457 u32 dbgfs_sram_offset, dbgfs_sram_len;
1458 bool disable_ht40;
e7392364 1459#endif /* CONFIG_IWLEGACY_DEBUGFS */
e94a4099
SG		 1460
1461 struct work_struct txpower_work;
1462 u32 disable_sens_cal;
1463 u32 disable_chain_noise_cal;
1464 u32 disable_tx_power_cal;
1465 struct work_struct run_time_calib_work;
1466 struct timer_list stats_periodic;
1467 struct timer_list watchdog;
1468 bool hw_ready;
1469
1470 struct led_classdev led;
1471 unsigned long blink_on, blink_off;
1472 bool led_registered;
e7392364 1473}; /*il_priv */
e94a4099 1474
e7392364
SG		 1475static inline void
1476il_txq_ctx_activate(struct il_priv *il, int txq_id)
e94a4099
SG		 1477{
1478 set_bit(txq_id, &il->txq_ctx_active_msk);
1479}
1480
e7392364
SG		 1481static inline void
1482il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
e94a4099
SG		 1483{
1484 clear_bit(txq_id, &il->txq_ctx_active_msk);
1485}
1486
e94a4099 1487static inline struct ieee80211_hdr *
e7392364 1488il_tx_queue_get_hdr(struct il_priv *il, int txq_id, int idx)
e94a4099
SG		 1489{
1490 if (il->txq[txq_id].txb[idx].skb)
e7392364
SG		 1491 return (struct ieee80211_hdr *)il->txq[txq_id].txb[idx].skb->
1492 data;
e94a4099
SG		 1493 return NULL;
1494}
1495
1496static inline struct il_rxon_context *
1497il_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1498{
1499 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1500
1501 return vif_priv->ctx;
1502}
1503
1504#define for_each_context(il, _ctx) \
1505 for (_ctx = &il->ctx; _ctx == &il->ctx; _ctx++)
1506
e7392364
SG		 1507static inline int
1508il_is_associated(struct il_priv *il)
e94a4099 1509{
c8b03958 1510 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
e94a4099
SG		 1511}
1512
e7392364
SG		 1513static inline int
1514il_is_any_associated(struct il_priv *il)
e94a4099
SG		 1515{
1516 return il_is_associated(il);
1517}
1518
e7392364
SG		 1519static inline int
1520il_is_channel_valid(const struct il_channel_info *ch_info)
e94a4099
SG		 1521{
1522 if (ch_info == NULL)
1523 return 0;
1524 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1525}
1526
e7392364
SG		 1527static inline int
1528il_is_channel_radar(const struct il_channel_info *ch_info)
e94a4099
SG		 1529{
1530 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1531}
1532
e7392364
SG		 1533static inline u8
1534il_is_channel_a_band(const struct il_channel_info *ch_info)
e94a4099
SG		 1535{
1536 return ch_info->band == IEEE80211_BAND_5GHZ;
1537}
1538
1539static inline int
1540il_is_channel_passive(const struct il_channel_info *ch)
1541{
1542 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1543}
1544
1545static inline int
1546il_is_channel_ibss(const struct il_channel_info *ch)
1547{
1548 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1549}
be663ab6 1550
e94a4099
SG		 1551static inline void
1552__il_free_pages(struct il_priv *il, struct page *page)
1553{
1554 __free_pages(page, il->hw_params.rx_page_order);
1555 il->alloc_rxb_page--;
1556}
1557
e7392364
SG		 1558static inline void
1559il_free_pages(struct il_priv *il, unsigned long page)
e94a4099
SG		 1560{
1561 free_pages(page, il->hw_params.rx_page_order);
1562 il->alloc_rxb_page--;
1563}
be663ab6
WYG		 1564
1565#define IWLWIFI_VERSION "in-tree:"
1566#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1567#define DRV_AUTHOR "<ilw@linux.intel.com>"
1568
e2ebc833 1569#define IL_PCI_DEVICE(dev, subdev, cfg) \
be663ab6
WYG		 1570 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1571 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1572 .driver_data = (kernel_ulong_t)&(cfg)
1573
1574#define TIME_UNIT 1024
1575
e2ebc833
SG		 1576#define IL_SKU_G 0x1
1577#define IL_SKU_A 0x2
1578#define IL_SKU_N 0x8
be663ab6 1579
e2ebc833 1580#define IL_CMD(x) case x: return #x
be663ab6 1581
e94a4099 1582/* Size of one Rx buffer in host DRAM */
e7392364 1583#define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
e94a4099
SG		 1584#define IL_RX_BUF_SIZE_4K (4 * 1024)
1585#define IL_RX_BUF_SIZE_8K (8 * 1024)
1586
e2ebc833 1587struct il_hcmd_ops {
1722f8e1
SG		 1588 int (*rxon_assoc) (struct il_priv *il, struct il_rxon_context *ctx);
1589 int (*commit_rxon) (struct il_priv *il, struct il_rxon_context *ctx);
1590 void (*set_rxon_chain) (struct il_priv *il,
1591 struct il_rxon_context *ctx);
be663ab6
WYG		 1592};
1593
e2ebc833 1594struct il_hcmd_utils_ops {
e7392364 1595 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1722f8e1
SG		 1596 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1597 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1598 void (*post_scan) (struct il_priv *il);
be663ab6
WYG		 1599};
1600
e2ebc833 1601struct il_apm_ops {
1722f8e1
SG		 1602 int (*init) (struct il_priv *il);
1603 void (*config) (struct il_priv *il);
be663ab6
WYG		 1604};
1605
9b5e2f46 1606#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1607struct il_debugfs_ops {
1722f8e1
SG		 1608 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1609 size_t count, loff_t *ppos);
1610 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1611 size_t count, loff_t *ppos);
1612 ssize_t(*general_stats_read) (struct file *file,
1613 char __user *user_buf, size_t count,
1614 loff_t *ppos);
be663ab6 1615};
9b5e2f46 1616#endif
be663ab6 1617
e2ebc833 1618struct il_temp_ops {
1722f8e1 1619 void (*temperature) (struct il_priv *il);
be663ab6
WYG		 1620};
1621
e2ebc833 1622struct il_lib_ops {
be663ab6 1623 /* set hw dependent parameters */
1722f8e1 1624 int (*set_hw_params) (struct il_priv *il);
be663ab6 1625 /* Handling TX */
1722f8e1
SG		 1626 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1627 struct il_tx_queue *txq,
e7392364 1628 u16 byte_cnt);
1722f8e1
SG		 1629 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1630 struct il_tx_queue *txq, dma_addr_t addr,
e7392364 1631 u16 len, u8 reset, u8 pad);
1722f8e1
SG		 1632 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1633 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
be663ab6 1634 /* setup Rx handler */
1722f8e1 1635 void (*handler_setup) (struct il_priv *il);
be663ab6 1636 /* alive notification after init uCode load */
1722f8e1 1637 void (*init_alive_start) (struct il_priv *il);
be663ab6 1638 /* check validity of rtc data address */
e7392364 1639 int (*is_valid_rtc_data_addr) (u32 addr);
be663ab6 1640 /* 1st ucode load */
1722f8e1 1641 int (*load_ucode) (struct il_priv *il);
1ba2f121 1642
1722f8e1
SG		 1643 void (*dump_nic_error_log) (struct il_priv *il);
1644 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1645 int (*set_channel_switch) (struct il_priv *il,
1646 struct ieee80211_channel_switch *ch_switch);
be663ab6 1647 /* power management */
e2ebc833 1648 struct il_apm_ops apm_ops;
be663ab6
WYG		 1649
1650 /* power */
1722f8e1
SG		 1651 int (*send_tx_power) (struct il_priv *il);
1652 void (*update_chain_flags) (struct il_priv *il);
be663ab6 1653
47ef694d 1654 /* eeprom operations */
e2ebc833 1655 struct il_eeprom_ops eeprom_ops;
be663ab6
WYG		 1656
1657 /* temperature */
e2ebc833 1658 struct il_temp_ops temp_ops;
be663ab6 1659
9b5e2f46 1660#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1661 struct il_debugfs_ops debugfs_ops;
9b5e2f46 1662#endif
be663ab6
WYG		 1663
1664};
1665
e2ebc833 1666struct il_led_ops {
1722f8e1 1667 int (*cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
be663ab6
WYG		 1668};
1669
e2ebc833 1670struct il_legacy_ops {
1722f8e1
SG		 1671 void (*post_associate) (struct il_priv *il);
1672 void (*config_ap) (struct il_priv *il);
be663ab6 1673 /* station management */
1722f8e1
SG		 1674 int (*update_bcast_stations) (struct il_priv *il);
1675 int (*manage_ibss_station) (struct il_priv *il,
1676 struct ieee80211_vif *vif, bool add);
be663ab6
WYG		 1677};
1678
e2ebc833
SG		 1679struct il_ops {
1680 const struct il_lib_ops *lib;
1681 const struct il_hcmd_ops *hcmd;
1682 const struct il_hcmd_utils_ops *utils;
1683 const struct il_led_ops *led;
1684 const struct il_nic_ops *nic;
1685 const struct il_legacy_ops *legacy;
be663ab6
WYG		 1686 const struct ieee80211_ops *ieee80211_ops;
1687};
1688
e2ebc833 1689struct il_mod_params {
be663ab6
WYG		 1690 int sw_crypto; /* def: 0 = using hardware encryption */
1691 int disable_hw_scan; /* def: 0 = use h/w scan */
1692 int num_of_queues; /* def: HW dependent */
1693 int disable_11n; /* def: 0 = 11n capabilities enabled */
1694 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
e7392364 1695 int antenna; /* def: 0 = both antennas (use diversity) */
be663ab6
WYG		 1696 int restart_fw; /* def: 1 = restart firmware */
1697};
1698
1699/*
1700 * @led_compensation: compensate on the led on/off time per HW according
1701 * to the deviation to achieve the desired led frequency.
47ef694d 1702 * The detail algorithm is described in common.c
be663ab6 1703 * @chain_noise_num_beacons: number of beacons used to compute chain noise
be663ab6
WYG		 1704 * @wd_timeout: TX queues watchdog timeout
1705 * @temperature_kelvin: temperature report by uCode in kelvin
be663ab6
WYG		 1706 * @ucode_tracing: support ucode continuous tracing
1707 * @sensitivity_calib_by_driver: driver has the capability to perform
1708 * sensitivity calibration operation
1709 * @chain_noise_calib_by_driver: driver has the capability to perform
1710 * chain noise calibration operation
1711 */
e2ebc833 1712struct il_base_params {
be663ab6
WYG		 1713 int eeprom_size;
1714 int num_of_queues; /* def: HW dependent */
e7392364 1715 int num_of_ampdu_queues; /* def: HW dependent */
e2ebc833 1716 /* for il_apm_init() */
be663ab6
WYG		 1717 u32 pll_cfg_val;
1718 bool set_l0s;
1719 bool use_bsm;
1720
1721 u16 led_compensation;
1722 int chain_noise_num_beacons;
be663ab6
WYG		 1723 unsigned int wd_timeout;
1724 bool temperature_kelvin;
be663ab6
WYG		 1725 const bool ucode_tracing;
1726 const bool sensitivity_calib_by_driver;
1727 const bool chain_noise_calib_by_driver;
1728};
1729
47ef694d
SG		 1730#define IL_LED_SOLID 11
1731#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1732
1733#define IL_LED_ACTIVITY (0<<1)
1734#define IL_LED_LINK (1<<1)
1735
1736/*
1737 * LED mode
1738 * IL_LED_DEFAULT: use device default
1739 * IL_LED_RF_STATE: turn LED on/off based on RF state
1740 * LED ON = RF ON
1741 * LED OFF = RF OFF
1742 * IL_LED_BLINK: adjust led blink rate based on blink table
1743 */
1744enum il_led_mode {
1745 IL_LED_DEFAULT,
1746 IL_LED_RF_STATE,
1747 IL_LED_BLINK,
1748};
1749
1750void il_leds_init(struct il_priv *il);
1751void il_leds_exit(struct il_priv *il);
1752
be663ab6 1753/**
e2ebc833 1754 * struct il_cfg
be663ab6
WYG		 1755 * @fw_name_pre: Firmware filename prefix. The api version and extension
1756 * (.ucode) will be added to filename before loading from disk. The
1757 * filename is constructed as fw_name_pre<api>.ucode.
1758 * @ucode_api_max: Highest version of uCode API supported by driver.
1759 * @ucode_api_min: Lowest version of uCode API supported by driver.
1760 * @scan_antennas: available antenna for scan operation
1761 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1762 *
1763 * We enable the driver to be backward compatible wrt API version. The
1764 * driver specifies which APIs it supports (with @ucode_api_max being the
1765 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1766 * it has a supported API version. The firmware's API version will be
e2ebc833 1767 * stored in @il_priv, enabling the driver to make runtime changes based
be663ab6
WYG		 1768 * on firmware version used.
1769 *
1770 * For example,
46bc8d4b 1771 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
be663ab6
WYG		 1772 * Driver interacts with Firmware API version >= 2.
1773 * } else {
1774 * Driver interacts with Firmware API version 1.
1775 * }
1776 *
1777 * The ideal usage of this infrastructure is to treat a new ucode API
1778 * release as a new hardware revision. That is, through utilizing the
e2ebc833 1779 * il_hcmd_utils_ops etc. we accommodate different command structures
be663ab6
WYG		 1780 * and flows between hardware versions as well as their API
1781 * versions.
1782 *
1783 */
e2ebc833 1784struct il_cfg {
be663ab6
WYG		 1785 /* params specific to an individual device within a device family */
1786 const char *name;
1787 const char *fw_name_pre;
1788 const unsigned int ucode_api_max;
1789 const unsigned int ucode_api_min;
e7392364
SG		 1790 u8 valid_tx_ant;
1791 u8 valid_rx_ant;
be663ab6 1792 unsigned int sku;
e7392364
SG		 1793 u16 eeprom_ver;
1794 u16 eeprom_calib_ver;
e2ebc833 1795 const struct il_ops *ops;
be663ab6 1796 /* module based parameters which can be set from modprobe cmd */
e2ebc833 1797 const struct il_mod_params *mod_params;
be663ab6 1798 /* params not likely to change within a device family */
e2ebc833 1799 struct il_base_params *base_params;
be663ab6
WYG		 1800 /* params likely to change within a device family */
1801 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
e2ebc833 1802 enum il_led_mode led_mode;
be663ab6
WYG		 1803};
1804
1805/***************************
1806 * L i b *
1807 ***************************/
1808
e2ebc833 1809struct ieee80211_hw *il_alloc_all(struct il_cfg *cfg);
e7392364
SG		 1810int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1811 u16 queue, const struct ieee80211_tx_queue_params *params);
e2ebc833 1812int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
e7392364
SG		 1813
1814void il_set_rxon_hwcrypto(struct il_priv *il, struct il_rxon_context *ctx,
1815 int hw_decrypt);
1816int il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx);
1817int il_full_rxon_required(struct il_priv *il, struct il_rxon_context *ctx);
1818int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
e2ebc833 1819 struct il_rxon_context *ctx);
e7392364
SG		 1820void il_set_flags_for_band(struct il_priv *il, struct il_rxon_context *ctx,
1821 enum ieee80211_band band, struct ieee80211_vif *vif);
1822u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1823void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1824bool il_is_ht40_tx_allowed(struct il_priv *il, struct il_rxon_context *ctx,
1825 struct ieee80211_sta_ht_cap *ht_cap);
46bc8d4b 1826void il_connection_init_rx_config(struct il_priv *il,
e7392364 1827 struct il_rxon_context *ctx);
46bc8d4b 1828void il_set_rate(struct il_priv *il);
e7392364
SG		 1829int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1830 u32 decrypt_res, struct ieee80211_rx_status *stats);
46bc8d4b 1831void il_irq_handle_error(struct il_priv *il);
e7392364 1832int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
e2ebc833 1833void il_mac_remove_interface(struct ieee80211_hw *hw,
e7392364
SG		 1834 struct ieee80211_vif *vif);
1835int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1836 enum nl80211_iftype newtype, bool newp2p);
46bc8d4b
SG		 1837int il_alloc_txq_mem(struct il_priv *il);
1838void il_txq_mem(struct il_priv *il);
be663ab6 1839
d3175167 1840#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b
SG		 1841int il_alloc_traffic_mem(struct il_priv *il);
1842void il_free_traffic_mem(struct il_priv *il);
1843void il_reset_traffic_log(struct il_priv *il);
e7392364
SG		 1844void il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1845 struct ieee80211_hdr *header);
1846void il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1847 struct ieee80211_hdr *header);
e2ebc833
SG		 1848const char *il_get_mgmt_string(int cmd);
1849const char *il_get_ctrl_string(int cmd);
46bc8d4b 1850void il_clear_traffic_stats(struct il_priv *il);
e7392364 1851void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
be663ab6 1852#else
e7392364
SG		 1853static inline int
1854il_alloc_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1855{
1856 return 0;
1857}
e7392364
SG		 1858
1859static inline void
1860il_free_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1861{
1862}
e7392364
SG		 1863
1864static inline void
1865il_reset_traffic_log(struct il_priv *il)
be663ab6
WYG		 1866{
1867}
e7392364
SG		 1868
1869static inline void
1870il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1871 struct ieee80211_hdr *header)
be663ab6
WYG		 1872{
1873}
e7392364
SG		 1874
1875static inline void
1876il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1877 struct ieee80211_hdr *header)
be663ab6
WYG		 1878{
1879}
e7392364
SG		 1880
1881static inline void
1882il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6
WYG		 1883{
1884}
1885#endif
1886/*****************************************************
1887 * RX handlers.
1888 * **************************************************/
e7392364
SG		 1889void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1890void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1891void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1892
1893/*****************************************************
1894* RX
1895******************************************************/
46bc8d4b
SG		 1896void il_cmd_queue_unmap(struct il_priv *il);
1897void il_cmd_queue_free(struct il_priv *il);
1898int il_rx_queue_alloc(struct il_priv *il);
e7392364 1899void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
e2ebc833 1900int il_rx_queue_space(const struct il_rx_queue *q);
e7392364 1901void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6 1902/* Handlers */
e7392364
SG		 1903void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1904void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
46bc8d4b 1905void il_chswitch_done(struct il_priv *il, bool is_success);
d2dfb33e 1906void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1907
1908/* TX helpers */
1909
1910/*****************************************************
1911* TX
1912******************************************************/
e7392364
SG		 1913void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1914int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
1915 u32 txq_id);
1916void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
1917 int slots_num, u32 txq_id);
46bc8d4b
SG		 1918void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1919void il_tx_queue_free(struct il_priv *il, int txq_id);
1920void il_setup_watchdog(struct il_priv *il);
be663ab6
WYG		 1921/*****************************************************
1922 * TX power
1923 ****************************************************/
46bc8d4b 1924int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
be663ab6
WYG		 1925
1926/*******************************************************************************
1927 * Rate
1928 ******************************************************************************/
1929
e7392364 1930u8 il_get_lowest_plcp(struct il_priv *il, struct il_rxon_context *ctx);
be663ab6
WYG		 1931
1932/*******************************************************************************
1933 * Scanning
1934 ******************************************************************************/
46bc8d4b
SG		 1935void il_init_scan_params(struct il_priv *il);
1936int il_scan_cancel(struct il_priv *il);
1937int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1938void il_force_scan_end(struct il_priv *il);
e7392364
SG		 1939int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1940 struct cfg80211_scan_request *req);
46bc8d4b
SG		 1941void il_internal_short_hw_scan(struct il_priv *il);
1942int il_force_reset(struct il_priv *il, bool external);
e7392364 1943u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1944 const u8 *ta, const u8 *ie, int ie_len, int left);
46bc8d4b 1945void il_setup_rx_scan_handlers(struct il_priv *il);
e7392364
SG		 1946u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1947 u8 n_probes);
1948u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1949 struct ieee80211_vif *vif);
46bc8d4b
SG		 1950void il_setup_scan_deferred_work(struct il_priv *il);
1951void il_cancel_scan_deferred_work(struct il_priv *il);
be663ab6
WYG		 1952
1953/* For faster active scanning, scan will move to the next channel if fewer than
1954 * PLCP_QUIET_THRESH packets are heard on this channel within
1955 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
1956 * time if it's a quiet channel (nothing responded to our probe, and there's
1957 * no other traffic).
1958 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
e7392364
SG		 1959#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
1960#define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
be663ab6 1961
e2ebc833 1962#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
be663ab6
WYG		 1963
1964/*****************************************************
1965 * S e n d i n g H o s t C o m m a n d s *
1966 *****************************************************/
1967
e2ebc833 1968const char *il_get_cmd_string(u8 cmd);
e7392364 1969int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
46bc8d4b 1970int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
e7392364
SG		 1971int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1972 const void *data);
1973int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 1974 void (*callback) (struct il_priv *il,
1975 struct il_device_cmd *cmd,
1976 struct il_rx_pkt *pkt));
be663ab6 1977
46bc8d4b 1978int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
be663ab6 1979
be663ab6
WYG		 1980/*****************************************************
1981 * PCI *
1982 *****************************************************/
1983
e7392364
SG		 1984static inline u16
1985il_pcie_link_ctl(struct il_priv *il)
be663ab6
WYG		 1986{
1987 int pos;
1988 u16 pci_lnk_ctl;
46bc8d4b
SG		 1989 pos = pci_pcie_cap(il->pci_dev);
1990 pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
be663ab6
WYG		 1991 return pci_lnk_ctl;
1992}
1993
e2ebc833 1994void il_bg_watchdog(unsigned long data);
e7392364
SG		 1995u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1996__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1997 u32 beacon_interval);
be663ab6
WYG		 1998
1999#ifdef CONFIG_PM
e2ebc833
SG		 2000int il_pci_suspend(struct device *device);
2001int il_pci_resume(struct device *device);
2002extern const struct dev_pm_ops il_pm_ops;
be663ab6 2003
e2ebc833 2004#define IL_LEGACY_PM_OPS (&il_pm_ops)
be663ab6
WYG		 2005
2006#else /* !CONFIG_PM */
2007
e2ebc833 2008#define IL_LEGACY_PM_OPS NULL
be663ab6
WYG		 2009
2010#endif /* !CONFIG_PM */
2011
2012/*****************************************************
2013* Error Handling Debugging
2014******************************************************/
46bc8d4b 2015void il4965_dump_nic_error_log(struct il_priv *il);
d3175167 2016#ifdef CONFIG_IWLEGACY_DEBUG
e7392364 2017void il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx);
be663ab6 2018#else
e7392364
SG		 2019static inline void
2020il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG		 2021{
2022}
2023#endif
2024
46bc8d4b 2025void il_clear_isr_stats(struct il_priv *il);
be663ab6
WYG		 2026
2027/*****************************************************
2028* GEOS
2029******************************************************/
46bc8d4b
SG		 2030int il_init_geos(struct il_priv *il);
2031void il_free_geos(struct il_priv *il);
be663ab6
WYG		 2032
2033/*************** DRIVER STATUS FUNCTIONS *****/
2034
a6766ccd
SG		 2035#define S_HCMD_ACTIVE 0 /* host command in progress */
2036/* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
2037#define S_INT_ENABLED 2
2038#define S_RF_KILL_HW 3
2039#define S_CT_KILL 4
2040#define S_INIT 5
2041#define S_ALIVE 6
2042#define S_READY 7
2043#define S_TEMPERATURE 8
2044#define S_GEO_CONFIGURED 9
2045#define S_EXIT_PENDING 10
db7746f7 2046#define S_STATS 12
a6766ccd
SG		 2047#define S_SCANNING 13
2048#define S_SCAN_ABORTING 14
2049#define S_SCAN_HW 15
2050#define S_POWER_PMI 16
2051#define S_FW_ERROR 17
2052#define S_CHANNEL_SWITCH_PENDING 18
be663ab6 2053
e7392364
SG		 2054static inline int
2055il_is_ready(struct il_priv *il)
be663ab6
WYG		 2056{
2057 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
2058 * set but EXIT_PENDING is not */
a6766ccd 2059 return test_bit(S_READY, &il->status) &&
e7392364
SG		 2060 test_bit(S_GEO_CONFIGURED, &il->status) &&
2061 !test_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 2062}
2063
e7392364
SG		 2064static inline int
2065il_is_alive(struct il_priv *il)
be663ab6 2066{
a6766ccd 2067 return test_bit(S_ALIVE, &il->status);
be663ab6
WYG		 2068}
2069
e7392364
SG		 2070static inline int
2071il_is_init(struct il_priv *il)
be663ab6 2072{
a6766ccd 2073 return test_bit(S_INIT, &il->status);
be663ab6
WYG		 2074}
2075
e7392364
SG		 2076static inline int
2077il_is_rfkill_hw(struct il_priv *il)
be663ab6 2078{
a6766ccd 2079 return test_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 2080}
2081
e7392364
SG		 2082static inline int
2083il_is_rfkill(struct il_priv *il)
be663ab6 2084{
46bc8d4b 2085 return il_is_rfkill_hw(il);
be663ab6
WYG		 2086}
2087
e7392364
SG		 2088static inline int
2089il_is_ctkill(struct il_priv *il)
be663ab6 2090{
a6766ccd 2091 return test_bit(S_CT_KILL, &il->status);
be663ab6
WYG		 2092}
2093
e7392364
SG		 2094static inline int
2095il_is_ready_rf(struct il_priv *il)
be663ab6
WYG		 2096{
2097
46bc8d4b 2098 if (il_is_rfkill(il))
be663ab6
WYG		 2099 return 0;
2100
46bc8d4b 2101 return il_is_ready(il);
be663ab6
WYG		 2102}
2103
46bc8d4b 2104extern void il_send_bt_config(struct il_priv *il);
e7392364 2105extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
46bc8d4b
SG		 2106void il_apm_stop(struct il_priv *il);
2107int il_apm_init(struct il_priv *il);
be663ab6 2108
e7392364
SG		 2109int il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx);
2110static inline int
2111il_send_rxon_assoc(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 2112{
46bc8d4b 2113 return il->cfg->ops->hcmd->rxon_assoc(il, ctx);
be663ab6 2114}
e7392364
SG		 2115
2116static inline int
2117il_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 2118{
46bc8d4b 2119 return il->cfg->ops->hcmd->commit_rxon(il, ctx);
be663ab6 2120}
e7392364
SG		 2121
2122static inline const struct ieee80211_supported_band *
2123il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
be663ab6 2124{
46bc8d4b 2125 return il->hw->wiphy->bands[band];
be663ab6
WYG		 2126}
2127
be663ab6 2128/* mac80211 handlers */
e2ebc833 2129int il_mac_config(struct ieee80211_hw *hw, u32 changed);
e7392364
SG		 2130void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
2131void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2132 struct ieee80211_bss_conf *bss_conf, u32 changes);
2133void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 2134 __le16 fc, __le32 *tx_flags);
be663ab6 2135
e2ebc833 2136irqreturn_t il_isr(int irq, void *data);
be663ab6 2137
17d4eca6
SG		 2138extern void il_set_bit(struct il_priv *p, u32 r, u32 m);
2139extern void il_clear_bit(struct il_priv *p, u32 r, u32 m);
2140extern int _il_grab_nic_access(struct il_priv *il);
2141extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
2142extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
2143extern u32 il_rd_prph(struct il_priv *il, u32 reg);
2144extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
2145extern u32 il_read_targ_mem(struct il_priv *il, u32 addr);
2146extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
e94a4099 2147
e7392364
SG		 2148static inline void
2149_il_write8(struct il_priv *il, u32 ofs, u8 val)
e94a4099
SG		 2150{
2151 iowrite8(val, il->hw_base + ofs);
2152}
2153#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2154
e7392364
SG		 2155static inline void
2156_il_wr(struct il_priv *il, u32 ofs, u32 val)
e94a4099
SG		 2157{
2158 iowrite32(val, il->hw_base + ofs);
2159}
2160
e7392364
SG		 2161static inline u32
2162_il_rd(struct il_priv *il, u32 ofs)
e94a4099
SG		 2163{
2164 return ioread32(il->hw_base + ofs);
2165}
2166
e94a4099
SG		 2167static inline void
2168_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2169{
2170 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2171}
2172
e7392364 2173static inline void
17d4eca6 2174_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
e94a4099 2175{
17d4eca6 2176 _il_wr(il, reg, _il_rd(il, reg) | mask);
e94a4099
SG		 2177}
2178
e7392364
SG		 2179static inline void
2180_il_release_nic_access(struct il_priv *il)
e94a4099 2181{
e7392364 2182 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
e94a4099
SG		 2183}
2184
e7392364
SG		 2185static inline u32
2186il_rd(struct il_priv *il, u32 reg)
e94a4099
SG		 2187{
2188 u32 value;
2189 unsigned long reg_flags;
2190
2191 spin_lock_irqsave(&il->reg_lock, reg_flags);
2192 _il_grab_nic_access(il);
2193 value = _il_rd(il, reg);
2194 _il_release_nic_access(il);
2195 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2196 return value;
e94a4099
SG		 2197}
2198
2199static inline void
2200il_wr(struct il_priv *il, u32 reg, u32 value)
2201{
2202 unsigned long reg_flags;
2203
2204 spin_lock_irqsave(&il->reg_lock, reg_flags);
2205 if (!_il_grab_nic_access(il)) {
2206 _il_wr(il, reg, value);
2207 _il_release_nic_access(il);
2208 }
2209 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2210}
2211
e7392364
SG		 2212static inline u32
2213_il_rd_prph(struct il_priv *il, u32 reg)
e94a4099
SG		 2214{
2215 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2216 rmb();
2217 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2218}
2219
e7392364
SG		 2220static inline void
2221_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
e94a4099 2222{
e7392364 2223 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
e94a4099
SG		 2224 wmb();
2225 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2226}
2227
e94a4099
SG		 2228static inline void
2229il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2230{
2231 unsigned long reg_flags;
2232
2233 spin_lock_irqsave(&il->reg_lock, reg_flags);
2234 _il_grab_nic_access(il);
17d4eca6 2235 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
e94a4099
SG		 2236 _il_release_nic_access(il);
2237 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2238}
2239
e7392364
SG		 2240static inline void
2241il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
e94a4099
SG		 2242{
2243 unsigned long reg_flags;
2244
2245 spin_lock_irqsave(&il->reg_lock, reg_flags);
2246 _il_grab_nic_access(il);
17d4eca6 2247 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
e94a4099
SG		 2248 _il_release_nic_access(il);
2249 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2250}
2251
e7392364
SG		 2252static inline void
2253il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
e94a4099
SG		 2254{
2255 unsigned long reg_flags;
2256 u32 val;
2257
2258 spin_lock_irqsave(&il->reg_lock, reg_flags);
2259 _il_grab_nic_access(il);
2260 val = _il_rd_prph(il, reg);
2261 _il_wr_prph(il, reg, (val & ~mask));
2262 _il_release_nic_access(il);
2263 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2264}
2265
e94a4099
SG		 2266#define HW_KEY_DYNAMIC 0
2267#define HW_KEY_DEFAULT 1
2268
e7392364
SG		 2269#define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2270#define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2271#define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2272 being activated */
2273#define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2274 (this is for the IBSS BSSID stations) */
2275#define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
e94a4099 2276
e7392364
SG		 2277void il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx);
2278void il_clear_ucode_stations(struct il_priv *il, struct il_rxon_context *ctx);
e94a4099
SG		 2279void il_dealloc_bcast_stations(struct il_priv *il);
2280int il_get_free_ucode_key_idx(struct il_priv *il);
e7392364
SG		 2281int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2282int il_add_station_common(struct il_priv *il, struct il_rxon_context *ctx,
1722f8e1
SG		 2283 const u8 *addr, bool is_ap,
2284 struct ieee80211_sta *sta, u8 *sta_id_r);
e7392364
SG		 2285int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2286int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2287 struct ieee80211_sta *sta);
2288
2289u8 il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
1722f8e1 2290 const u8 *addr, bool is_ap, struct ieee80211_sta *sta);
e7392364
SG		 2291
2292int il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
2293 struct il_link_quality_cmd *lq, u8 flags, bool init);
e94a4099
SG		 2294
2295/**
2296 * il_clear_driver_stations - clear knowledge of all stations from driver
2297 * @il: iwl il struct
2298 *
2299 * This is called during il_down() to make sure that in the case
2300 * we're coming there from a hardware restart mac80211 will be
2301 * able to reconfigure stations -- if we're getting there in the
2302 * normal down flow then the stations will already be cleared.
2303 */
e7392364
SG		 2304static inline void
2305il_clear_driver_stations(struct il_priv *il)
e94a4099
SG		 2306{
2307 unsigned long flags;
e94a4099
SG		 2308
2309 spin_lock_irqsave(&il->sta_lock, flags);
2310 memset(il->stations, 0, sizeof(il->stations));
2311 il->num_stations = 0;
e94a4099 2312 il->ucode_key_table = 0;
e94a4099
SG		 2313 spin_unlock_irqrestore(&il->sta_lock, flags);
2314}
2315
e7392364
SG		 2316static inline int
2317il_sta_id(struct ieee80211_sta *sta)
e94a4099
SG		 2318{
2319 if (WARN_ON(!sta))
2320 return IL_INVALID_STATION;
2321
2322 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2323}
2324
2325/**
2326 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2327 * @il: iwl il
2328 * @context: the current context
2329 * @sta: mac80211 station
2330 *
2331 * In certain circumstances mac80211 passes a station pointer
2332 * that may be %NULL, for example during TX or key setup. In
2333 * that case, we need to use the broadcast station, so this
2334 * inline wraps that pattern.
2335 */
e7392364
SG		 2336static inline int
2337il_sta_id_or_broadcast(struct il_priv *il, struct il_rxon_context *context,
2338 struct ieee80211_sta *sta)
e94a4099
SG		 2339{
2340 int sta_id;
2341
2342 if (!sta)
b16db50a 2343 return il->hw_params.bcast_id;
e94a4099
SG		 2344
2345 sta_id = il_sta_id(sta);
2346
2347 /*
2348 * mac80211 should not be passing a partially
2349 * initialised station!
2350 */
2351 WARN_ON(sta_id == IL_INVALID_STATION);
2352
2353 return sta_id;
2354}
2355
2356/**
2357 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2358 * @idx -- current idx
2359 * @n_bd -- total number of entries in queue (must be power of 2)
2360 */
e7392364
SG		 2361static inline int
2362il_queue_inc_wrap(int idx, int n_bd)
e94a4099
SG		 2363{
2364 return ++idx & (n_bd - 1);
2365}
2366
2367/**
2368 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2369 * @idx -- current idx
2370 * @n_bd -- total number of entries in queue (must be power of 2)
2371 */
e7392364
SG		 2372static inline int
2373il_queue_dec_wrap(int idx, int n_bd)
e94a4099
SG		 2374{
2375 return --idx & (n_bd - 1);
2376}
2377
2378/* TODO: Move fw_desc functions to iwl-pci.ko */
e7392364
SG		 2379static inline void
2380il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2381{
2382 if (desc->v_addr)
e7392364
SG		 2383 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2384 desc->p_addr);
e94a4099
SG		 2385 desc->v_addr = NULL;
2386 desc->len = 0;
2387}
2388
e7392364
SG		 2389static inline int
2390il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2391{
2392 if (!desc->len) {
2393 desc->v_addr = NULL;
2394 return -EINVAL;
2395 }
2396
e7392364
SG		 2397 desc->v_addr =
2398 dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2399 GFP_KERNEL);
e94a4099
SG		 2400 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2401}
2402
2403/*
2404 * we have 8 bits used like this:
2405 *
2406 * 7 6 5 4 3 2 1 0
2407 * | | | | | | | |
2408 * | | | | | | +-+-------- AC queue (0-3)
2409 * | | | | | |
2410 * | +-+-+-+-+------------ HW queue ID
2411 * |
2412 * +---------------------- unused
2413 */
2414static inline void
2415il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2416{
e7392364
SG		 2417 BUG_ON(ac > 3); /* only have 2 bits */
2418 BUG_ON(hwq > 31); /* only use 5 bits */
e94a4099
SG		 2419
2420 txq->swq_id = (hwq << 2) | ac;
2421}
2422
e7392364
SG		 2423static inline void
2424il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2425{
2426 u8 queue = txq->swq_id;
2427 u8 ac = queue & 3;
2428 u8 hwq = (queue >> 2) & 0x1f;
2429
2430 if (test_and_clear_bit(hwq, il->queue_stopped))
2431 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2432 ieee80211_wake_queue(il->hw, ac);
2433}
2434
e7392364
SG		 2435static inline void
2436il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2437{
2438 u8 queue = txq->swq_id;
2439 u8 ac = queue & 3;
2440 u8 hwq = (queue >> 2) & 0x1f;
2441
2442 if (!test_and_set_bit(hwq, il->queue_stopped))
2443 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2444 ieee80211_stop_queue(il->hw, ac);
2445}
2446
2447#ifdef ieee80211_stop_queue
2448#undef ieee80211_stop_queue
2449#endif
2450
2451#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2452
2453#ifdef ieee80211_wake_queue
2454#undef ieee80211_wake_queue
2455#endif
2456
2457#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2458
e7392364
SG		 2459static inline void
2460il_disable_interrupts(struct il_priv *il)
e94a4099
SG		 2461{
2462 clear_bit(S_INT_ENABLED, &il->status);
2463
2464 /* disable interrupts from uCode/NIC to host */
2465 _il_wr(il, CSR_INT_MASK, 0x00000000);
2466
2467 /* acknowledge/clear/reset any interrupts still pending
2468 * from uCode or flow handler (Rx/Tx DMA) */
2469 _il_wr(il, CSR_INT, 0xffffffff);
2470 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
e94a4099
SG		 2471}
2472
e7392364
SG		 2473static inline void
2474il_enable_rfkill_int(struct il_priv *il)
e94a4099 2475{
e94a4099
SG		 2476 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2477}
2478
e7392364
SG		 2479static inline void
2480il_enable_interrupts(struct il_priv *il)
e94a4099 2481{
e94a4099
SG		 2482 set_bit(S_INT_ENABLED, &il->status);
2483 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2484}
2485
2486/**
2487 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2488 * @il -- pointer to il_priv data structure
2489 * @tsf_bits -- number of bits need to shift for masking)
2490 */
e7392364
SG		 2491static inline u32
2492il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2493{
2494 return (1 << tsf_bits) - 1;
2495}
2496
2497/**
2498 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2499 * @il -- pointer to il_priv data structure
2500 * @tsf_bits -- number of bits need to shift for masking)
2501 */
e7392364
SG		 2502static inline u32
2503il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2504{
2505 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2506}
2507
2508/**
2509 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2510 *
2511 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2512 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2513 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2514 * in which the last frame was written to
2515 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2516 * which was transferred
2517 */
2518struct il_rb_status {
2519 __le16 closed_rb_num;
2520 __le16 closed_fr_num;
2521 __le16 finished_rb_num;
2522 __le16 finished_fr_nam;
e7392364 2523 __le32 __unused; /* 3945 only */
e94a4099
SG		 2524} __packed;
2525
e94a4099
SG		 2526#define TFD_QUEUE_SIZE_MAX (256)
2527#define TFD_QUEUE_SIZE_BC_DUP (64)
2528#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2529#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2530#define IL_NUM_OF_TBS 20
2531
e7392364
SG		 2532static inline u8
2533il_get_dma_hi_addr(dma_addr_t addr)
e94a4099
SG		 2534{
2535 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2536}
e7392364 2537
e94a4099
SG		 2538/**
2539 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2540 *
2541 * This structure contains dma address and length of transmission address
2542 *
1722f8e1
SG		 2543 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2544 * unaligned on 16 bit boundary
2545 * @hi_n_len: 0-3 [35:32] portion of dma
2546 * 4-15 length of the tx buffer
e94a4099
SG		 2547 */
2548struct il_tfd_tb {
2549 __le32 lo;
2550 __le16 hi_n_len;
2551} __packed;
2552
2553/**
2554 * struct il_tfd
2555 *
2556 * Transmit Frame Descriptor (TFD)
2557 *
2558 * @ __reserved1[3] reserved
2559 * @ num_tbs 0-4 number of active tbs
2560 * 5 reserved
2561 * 6-7 padding (not used)
2562 * @ tbs[20] transmit frame buffer descriptors
1722f8e1 2563 * @ __pad padding
e94a4099
SG		 2564 *
2565 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2566 * Both driver and device share these circular buffers, each of which must be
2567 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2568 *
2569 * Driver must indicate the physical address of the base of each
9a95b370 2570 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
e94a4099
SG		 2571 *
2572 * Each TFD contains pointer/size information for up to 20 data buffers
2573 * in host DRAM. These buffers collectively contain the (one) frame described
2574 * by the TFD. Each buffer must be a single contiguous block of memory within
2575 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2576 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2577 * Tx frame, up to 8 KBytes in size.
2578 *
2579 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2580 */
2581struct il_tfd {
2582 u8 __reserved1[3];
2583 u8 num_tbs;
2584 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2585 __le32 __pad;
2586} __packed;
2587/* PCI registers */
2588#define PCI_CFG_RETRY_TIMEOUT 0x041
2589
2590/* PCI register values */
2591#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2592#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2593
3fbbf9a8 2594struct il_rate_info {
e7392364
SG		 2595 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2596 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2597 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2598 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2599 u8 prev_ieee; /* previous rate in IEEE speeds */
2600 u8 next_ieee; /* next rate in IEEE speeds */
2601 u8 prev_rs; /* previous rate used in rs algo */
2602 u8 next_rs; /* next rate used in rs algo */
2603 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2604 u8 next_rs_tgg; /* next rate used in TGG rs algo */
3fbbf9a8
SG		 2605};
2606
2607struct il3945_rate_info {
2608 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2609 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2610 u8 prev_ieee; /* previous rate in IEEE speeds */
2611 u8 next_ieee; /* next rate in IEEE speeds */
2612 u8 prev_rs; /* previous rate used in rs algo */
2613 u8 next_rs; /* next rate used in rs algo */
2614 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2615 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2616 u8 table_rs_idx; /* idx in rate scale table cmd */
2617 u8 prev_table_rs; /* prev in rate table cmd */
2618};
2619
3fbbf9a8
SG		 2620/*
2621 * These serve as idxes into
2622 * struct il_rate_info il_rates[RATE_COUNT];
2623 */
2624enum {
2625 RATE_1M_IDX = 0,
2626 RATE_2M_IDX,
2627 RATE_5M_IDX,
2628 RATE_11M_IDX,
2629 RATE_6M_IDX,
2630 RATE_9M_IDX,
2631 RATE_12M_IDX,
2632 RATE_18M_IDX,
2633 RATE_24M_IDX,
2634 RATE_36M_IDX,
2635 RATE_48M_IDX,
2636 RATE_54M_IDX,
2637 RATE_60M_IDX,
2638 RATE_COUNT,
2639 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2640 RATE_COUNT_3945 = RATE_COUNT - 1,
2641 RATE_INVM_IDX = RATE_COUNT,
2642 RATE_INVALID = RATE_COUNT,
2643};
2644
2645enum {
2646 RATE_6M_IDX_TBL = 0,
2647 RATE_9M_IDX_TBL,
2648 RATE_12M_IDX_TBL,
2649 RATE_18M_IDX_TBL,
2650 RATE_24M_IDX_TBL,
2651 RATE_36M_IDX_TBL,
2652 RATE_48M_IDX_TBL,
2653 RATE_54M_IDX_TBL,
2654 RATE_1M_IDX_TBL,
2655 RATE_2M_IDX_TBL,
2656 RATE_5M_IDX_TBL,
2657 RATE_11M_IDX_TBL,
2658 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2659};
2660
2661enum {
2662 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2663 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2664 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2665 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2666 IL_LAST_CCK_RATE = RATE_11M_IDX,
2667};
2668
2669/* #define vs. enum to keep from defaulting to 'large integer' */
2670#define RATE_6M_MASK (1 << RATE_6M_IDX)
2671#define RATE_9M_MASK (1 << RATE_9M_IDX)
2672#define RATE_12M_MASK (1 << RATE_12M_IDX)
2673#define RATE_18M_MASK (1 << RATE_18M_IDX)
2674#define RATE_24M_MASK (1 << RATE_24M_IDX)
2675#define RATE_36M_MASK (1 << RATE_36M_IDX)
2676#define RATE_48M_MASK (1 << RATE_48M_IDX)
2677#define RATE_54M_MASK (1 << RATE_54M_IDX)
2678#define RATE_60M_MASK (1 << RATE_60M_IDX)
2679#define RATE_1M_MASK (1 << RATE_1M_IDX)
2680#define RATE_2M_MASK (1 << RATE_2M_IDX)
2681#define RATE_5M_MASK (1 << RATE_5M_IDX)
2682#define RATE_11M_MASK (1 << RATE_11M_IDX)
2683
2684/* uCode API values for legacy bit rates, both OFDM and CCK */
2685enum {
e7392364
SG		 2686 RATE_6M_PLCP = 13,
2687 RATE_9M_PLCP = 15,
3fbbf9a8
SG		 2688 RATE_12M_PLCP = 5,
2689 RATE_18M_PLCP = 7,
2690 RATE_24M_PLCP = 9,
2691 RATE_36M_PLCP = 11,
2692 RATE_48M_PLCP = 1,
2693 RATE_54M_PLCP = 3,
e7392364
SG		 2694 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */
2695 RATE_1M_PLCP = 10,
2696 RATE_2M_PLCP = 20,
2697 RATE_5M_PLCP = 55,
3fbbf9a8 2698 RATE_11M_PLCP = 110,
e7392364 2699 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
3fbbf9a8
SG		 2700};
2701
2702/* uCode API values for OFDM high-throughput (HT) bit rates */
2703enum {
2704 RATE_SISO_6M_PLCP = 0,
2705 RATE_SISO_12M_PLCP = 1,
2706 RATE_SISO_18M_PLCP = 2,
2707 RATE_SISO_24M_PLCP = 3,
2708 RATE_SISO_36M_PLCP = 4,
2709 RATE_SISO_48M_PLCP = 5,
2710 RATE_SISO_54M_PLCP = 6,
2711 RATE_SISO_60M_PLCP = 7,
e7392364 2712 RATE_MIMO2_6M_PLCP = 0x8,
3fbbf9a8
SG		 2713 RATE_MIMO2_12M_PLCP = 0x9,
2714 RATE_MIMO2_18M_PLCP = 0xa,
2715 RATE_MIMO2_24M_PLCP = 0xb,
2716 RATE_MIMO2_36M_PLCP = 0xc,
2717 RATE_MIMO2_48M_PLCP = 0xd,
2718 RATE_MIMO2_54M_PLCP = 0xe,
2719 RATE_MIMO2_60M_PLCP = 0xf,
2720 RATE_SISO_INVM_PLCP,
2721 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2722};
2723
2724/* MAC header values for bit rates */
2725enum {
e7392364
SG		 2726 RATE_6M_IEEE = 12,
2727 RATE_9M_IEEE = 18,
3fbbf9a8
SG		 2728 RATE_12M_IEEE = 24,
2729 RATE_18M_IEEE = 36,
2730 RATE_24M_IEEE = 48,
2731 RATE_36M_IEEE = 72,
2732 RATE_48M_IEEE = 96,
2733 RATE_54M_IEEE = 108,
2734 RATE_60M_IEEE = 120,
e7392364
SG		 2735 RATE_1M_IEEE = 2,
2736 RATE_2M_IEEE = 4,
2737 RATE_5M_IEEE = 11,
3fbbf9a8
SG		 2738 RATE_11M_IEEE = 22,
2739};
2740
2741#define IL_CCK_BASIC_RATES_MASK \
2742 (RATE_1M_MASK | \
2743 RATE_2M_MASK)
2744
2745#define IL_CCK_RATES_MASK \
2746 (IL_CCK_BASIC_RATES_MASK | \
2747 RATE_5M_MASK | \
2748 RATE_11M_MASK)
2749
2750#define IL_OFDM_BASIC_RATES_MASK \
2751 (RATE_6M_MASK | \
2752 RATE_12M_MASK | \
2753 RATE_24M_MASK)
2754
2755#define IL_OFDM_RATES_MASK \
2756 (IL_OFDM_BASIC_RATES_MASK | \
2757 RATE_9M_MASK | \
2758 RATE_18M_MASK | \
2759 RATE_36M_MASK | \
2760 RATE_48M_MASK | \
2761 RATE_54M_MASK)
2762
2763#define IL_BASIC_RATES_MASK \
2764 (IL_OFDM_BASIC_RATES_MASK | \
2765 IL_CCK_BASIC_RATES_MASK)
2766
2767#define RATES_MASK ((1 << RATE_COUNT) - 1)
2768#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2769
2770#define IL_INVALID_VALUE -1
2771
2772#define IL_MIN_RSSI_VAL -100
2773#define IL_MAX_RSSI_VAL 0
2774
2775/* These values specify how many Tx frame attempts before
2776 * searching for a new modulation mode */
2777#define IL_LEGACY_FAILURE_LIMIT 160
2778#define IL_LEGACY_SUCCESS_LIMIT 480
2779#define IL_LEGACY_TBL_COUNT 160
2780
2781#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2782#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2783#define IL_NONE_LEGACY_TBL_COUNT 1500
2784
2785/* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2786#define IL_RS_GOOD_RATIO 12800 /* 100% */
2787#define RATE_SCALE_SWITCH 10880 /* 85% */
2788#define RATE_HIGH_TH 10880 /* 85% */
2789#define RATE_INCREASE_TH 6400 /* 50% */
2790#define RATE_DECREASE_TH 1920 /* 15% */
2791
2792/* possible actions when in legacy mode */
2793#define IL_LEGACY_SWITCH_ANTENNA1 0
2794#define IL_LEGACY_SWITCH_ANTENNA2 1
2795#define IL_LEGACY_SWITCH_SISO 2
2796#define IL_LEGACY_SWITCH_MIMO2_AB 3
2797#define IL_LEGACY_SWITCH_MIMO2_AC 4
2798#define IL_LEGACY_SWITCH_MIMO2_BC 5
2799
2800/* possible actions when in siso mode */
2801#define IL_SISO_SWITCH_ANTENNA1 0
2802#define IL_SISO_SWITCH_ANTENNA2 1
2803#define IL_SISO_SWITCH_MIMO2_AB 2
2804#define IL_SISO_SWITCH_MIMO2_AC 3
2805#define IL_SISO_SWITCH_MIMO2_BC 4
2806#define IL_SISO_SWITCH_GI 5
2807
2808/* possible actions when in mimo mode */
2809#define IL_MIMO2_SWITCH_ANTENNA1 0
2810#define IL_MIMO2_SWITCH_ANTENNA2 1
2811#define IL_MIMO2_SWITCH_SISO_A 2
2812#define IL_MIMO2_SWITCH_SISO_B 3
2813#define IL_MIMO2_SWITCH_SISO_C 4
2814#define IL_MIMO2_SWITCH_GI 5
2815
2816#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2817
2818#define IL_ACTION_LIMIT 3 /* # possible actions */
2819
2820#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
2821
2822/* load per tid defines for A-MPDU activation */
2823#define IL_AGG_TPT_THREHOLD 0
2824#define IL_AGG_LOAD_THRESHOLD 10
2825#define IL_AGG_ALL_TID 0xff
2826#define TID_QUEUE_CELL_SPACING 50 /*mS */
2827#define TID_QUEUE_MAX_SIZE 20
2828#define TID_ROUND_VALUE 5 /* mS */
2829#define TID_MAX_LOAD_COUNT 8
2830
2831#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2832#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2833
2834extern const struct il_rate_info il_rates[RATE_COUNT];
2835
2836enum il_table_type {
2837 LQ_NONE,
e7392364 2838 LQ_G, /* legacy types */
3fbbf9a8 2839 LQ_A,
e7392364 2840 LQ_SISO, /* high-throughput types */
3fbbf9a8
SG		 2841 LQ_MIMO2,
2842 LQ_MAX,
2843};
2844
2845#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2846#define is_siso(tbl) ((tbl) == LQ_SISO)
2847#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2848#define is_mimo(tbl) (is_mimo2(tbl))
2849#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2850#define is_a_band(tbl) ((tbl) == LQ_A)
2851#define is_g_and(tbl) ((tbl) == LQ_G)
2852
2853#define ANT_NONE 0x0
2854#define ANT_A BIT(0)
2855#define ANT_B BIT(1)
2856#define ANT_AB (ANT_A | ANT_B)
2857#define ANT_C BIT(2)
2858#define ANT_AC (ANT_A | ANT_C)
2859#define ANT_BC (ANT_B | ANT_C)
2860#define ANT_ABC (ANT_AB | ANT_C)
2861
2862#define IL_MAX_MCS_DISPLAY_SIZE 12
2863
2864struct il_rate_mcs_info {
e7392364
SG		 2865 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2866 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
3fbbf9a8
SG		 2867};
2868
2869/**
2870 * struct il_rate_scale_data -- tx success history for one rate
2871 */
2872struct il_rate_scale_data {
2873 u64 data; /* bitmap of successful frames */
2874 s32 success_counter; /* number of frames successful */
2875 s32 success_ratio; /* per-cent * 128 */
2876 s32 counter; /* number of frames attempted */
2877 s32 average_tpt; /* success ratio * expected throughput */
2878 unsigned long stamp;
2879};
2880
2881/**
2882 * struct il_scale_tbl_info -- tx params and success history for all rates
2883 *
2884 * There are two of these in struct il_lq_sta,
2885 * one for "active", and one for "search".
2886 */
2887struct il_scale_tbl_info {
2888 enum il_table_type lq_type;
2889 u8 ant_type;
e7392364
SG		 2890 u8 is_SGI; /* 1 = short guard interval */
2891 u8 is_ht40; /* 1 = 40 MHz channel width */
2892 u8 is_dup; /* 1 = duplicated data streams */
2893 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2894 u8 max_search; /* maximun number of tables we can search */
3fbbf9a8 2895 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
e7392364
SG		 2896 u32 current_rate; /* rate_n_flags, uCode API format */
2897 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
3fbbf9a8
SG		 2898};
2899
2900struct il_traffic_load {
2901 unsigned long time_stamp; /* age of the oldest stats */
e7392364 2902 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
3fbbf9a8 2903 * slice */
e7392364
SG		 2904 u32 total; /* total num of packets during the
2905 * last TID_MAX_TIME_DIFF */
2906 u8 queue_count; /* number of queues that has
2907 * been used since the last cleanup */
2908 u8 head; /* start of the circular buffer */
3fbbf9a8
SG		 2909};
2910
2911/**
2912 * struct il_lq_sta -- driver's rate scaling ilate structure
2913 *
2914 * Pointer to this gets passed back and forth between driver and mac80211.
2915 */
2916struct il_lq_sta {
2917 u8 active_tbl; /* idx of active table, range 0-1 */
2918 u8 enable_counter; /* indicates HT mode */
2919 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
2920 u8 search_better_tbl; /* 1: currently trying alternate mode */
2921 s32 last_tpt;
2922
2923 /* The following determine when to search for a new mode */
2924 u32 table_count_limit;
2925 u32 max_failure_limit; /* # failed frames before new search */
2926 u32 max_success_limit; /* # successful frames before new search */
2927 u32 table_count;
2928 u32 total_failed; /* total failed frames, any/all rates */
2929 u32 total_success; /* total successful frames, any/all rates */
2930 u64 flush_timer; /* time staying in mode before new search */
2931
2932 u8 action_counter; /* # mode-switch actions tried */
2933 u8 is_green;
2934 u8 is_dup;
2935 enum ieee80211_band band;
2936
2937 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2938 u32 supp_rates;
2939 u16 active_legacy_rate;
2940 u16 active_siso_rate;
2941 u16 active_mimo2_rate;
e7392364 2942 s8 max_rate_idx; /* Max rate set by user */
3fbbf9a8
SG		 2943 u8 missed_rate_counter;
2944
2945 struct il_link_quality_cmd lq;
e7392364 2946 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
3fbbf9a8
SG		 2947 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2948 u8 tx_agg_tid_en;
2949#ifdef CONFIG_MAC80211_DEBUGFS
2950 struct dentry *rs_sta_dbgfs_scale_table_file;
2951 struct dentry *rs_sta_dbgfs_stats_table_file;
2952 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2953 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2954 u32 dbg_fixed_rate;
2955#endif
2956 struct il_priv *drv;
2957
2958 /* used to be in sta_info */
2959 int last_txrate_idx;
2960 /* last tx rate_n_flags */
2961 u32 last_rate_n_flags;
2962 /* packets destined for this STA are aggregated */
2963 u8 is_agg;
2964};
2965
2966/*
2967 * il_station_priv: Driver's ilate station information
2968 *
2969 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2970 * in the structure for use by driver. This structure is places in that
2971 * space.
2972 *
2973 * The common struct MUST be first because it is shared between
2974 * 3945 and 4965!
2975 */
2976struct il_station_priv {
2977 struct il_station_priv_common common;
2978 struct il_lq_sta lq_sta;
2979 atomic_t pending_frames;
2980 bool client;
2981 bool asleep;
2982};
2983
e7392364
SG		 2984static inline u8
2985il4965_num_of_ant(u8 m)
3fbbf9a8
SG		 2986{
2987 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2988}
2989
e7392364
SG		 2990static inline u8
2991il4965_first_antenna(u8 mask)
3fbbf9a8
SG		 2992{
2993 if (mask & ANT_A)
2994 return ANT_A;
2995 if (mask & ANT_B)
2996 return ANT_B;
2997 return ANT_C;
2998}
2999
3fbbf9a8
SG		 3000/**
3001 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
3002 *
3003 * The specific throughput table used is based on the type of network
3004 * the associated with, including A, B, G, and G w/ TGG protection
3005 */
3006extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
3007
3008/* Initialize station's rate scaling information after adding station */
e7392364
SG		 3009extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
3010 u8 sta_id);
3011extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
3012 u8 sta_id);
3fbbf9a8
SG		 3013
3014/**
3015 * il_rate_control_register - Register the rate control algorithm callbacks
3016 *
3017 * Since the rate control algorithm is hardware specific, there is no need
3018 * or reason to place it as a stand alone module. The driver can call
3019 * il_rate_control_register in order to register the rate control callbacks
3020 * with the mac80211 subsystem. This should be performed prior to calling
3021 * ieee80211_register_hw
3022 *
3023 */
3024extern int il4965_rate_control_register(void);
3025extern int il3945_rate_control_register(void);
3026
3027/**
3028 * il_rate_control_unregister - Unregister the rate control callbacks
3029 *
3030 * This should be called after calling ieee80211_unregister_hw, but before
3031 * the driver is unloaded.
3032 */
3033extern void il4965_rate_control_unregister(void);
3034extern void il3945_rate_control_unregister(void);
3035
99412002
SG		 3036extern int il_power_update_mode(struct il_priv *il, bool force);
3037extern void il_power_initialize(struct il_priv *il);
47ef694d 3038
f02579e3
SG		 3039extern u32 il_debug_level;
3040
3041#ifdef CONFIG_IWLEGACY_DEBUG
3042/*
3043 * il_get_debug_level: Return active debug level for device
3044 *
3045 * Using sysfs it is possible to set per device debug level. This debug
3046 * level will be used if set, otherwise the global debug level which can be
3047 * set via module parameter is used.
3048 */
e7392364
SG		 3049static inline u32
3050il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3051{
3052 if (il->debug_level)
3053 return il->debug_level;
3054 else
3055 return il_debug_level;
3056}
3057#else
e7392364
SG		 3058static inline u32
3059il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3060{
3061 return il_debug_level;
3062}
3063#endif
3064
3065#define il_print_hex_error(il, p, len) \
3066do { \
3067 print_hex_dump(KERN_ERR, "iwl data: ", \
3068 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3069} while (0)
3070
3071#ifdef CONFIG_IWLEGACY_DEBUG
3072#define IL_DBG(level, fmt, args...) \
3073do { \
3074 if (il_get_debug_level(il) & level) \
3075 dev_printk(KERN_ERR, &il->hw->wiphy->dev, \
3076 "%c %s " fmt, in_interrupt() ? 'I' : 'U', \
3077 __func__ , ## args); \
3078} while (0)
3079
1722f8e1 3080#define il_print_hex_dump(il, level, p, len) \
f02579e3
SG		 3081do { \
3082 if (il_get_debug_level(il) & level) \
3083 print_hex_dump(KERN_DEBUG, "iwl data: ", \
3084 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3085} while (0)
3086
3087#else
3088#define IL_DBG(level, fmt, args...)
e7392364
SG		 3089static inline void
3090il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
3091{
3092}
3093#endif /* CONFIG_IWLEGACY_DEBUG */
f02579e3
SG		 3094
3095#ifdef CONFIG_IWLEGACY_DEBUGFS
3096int il_dbgfs_register(struct il_priv *il, const char *name);
3097void il_dbgfs_unregister(struct il_priv *il);
3098#else
3099static inline int
3100il_dbgfs_register(struct il_priv *il, const char *name)
3101{
3102 return 0;
3103}
e7392364
SG		 3104
3105static inline void
3106il_dbgfs_unregister(struct il_priv *il)
f02579e3
SG		 3107{
3108}
e7392364 3109#endif /* CONFIG_IWLEGACY_DEBUGFS */
f02579e3
SG		 3110
3111/*
3112 * To use the debug system:
3113 *
3114 * If you are defining a new debug classification, simply add it to the #define
3115 * list here in the form of
3116 *
3117 * #define IL_DL_xxxx VALUE
3118 *
3119 * where xxxx should be the name of the classification (for example, WEP).
3120 *
3121 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
3122 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
3123 * to send output to that classification.
3124 *
3125 * The active debug levels can be accessed via files
3126 *
1722f8e1 3127 * /sys/module/iwl4965/parameters/debug
f02579e3 3128 * /sys/module/iwl3945/parameters/debug
1722f8e1 3129 * /sys/class/net/wlan0/device/debug_level
f02579e3
SG		 3130 *
3131 * when CONFIG_IWLEGACY_DEBUG=y.
3132 */
3133
3134/* 0x0000000F - 0x00000001 */
3135#define IL_DL_INFO (1 << 0)
3136#define IL_DL_MAC80211 (1 << 1)
3137#define IL_DL_HCMD (1 << 2)
3138#define IL_DL_STATE (1 << 3)
3139/* 0x000000F0 - 0x00000010 */
3140#define IL_DL_MACDUMP (1 << 4)
3141#define IL_DL_HCMD_DUMP (1 << 5)
3142#define IL_DL_EEPROM (1 << 6)
3143#define IL_DL_RADIO (1 << 7)
3144/* 0x00000F00 - 0x00000100 */
3145#define IL_DL_POWER (1 << 8)
3146#define IL_DL_TEMP (1 << 9)
3147#define IL_DL_NOTIF (1 << 10)
3148#define IL_DL_SCAN (1 << 11)
3149/* 0x0000F000 - 0x00001000 */
3150#define IL_DL_ASSOC (1 << 12)
3151#define IL_DL_DROP (1 << 13)
3152#define IL_DL_TXPOWER (1 << 14)
3153#define IL_DL_AP (1 << 15)
3154/* 0x000F0000 - 0x00010000 */
3155#define IL_DL_FW (1 << 16)
3156#define IL_DL_RF_KILL (1 << 17)
3157#define IL_DL_FW_ERRORS (1 << 18)
3158#define IL_DL_LED (1 << 19)
3159/* 0x00F00000 - 0x00100000 */
3160#define IL_DL_RATE (1 << 20)
3161#define IL_DL_CALIB (1 << 21)
3162#define IL_DL_WEP (1 << 22)
3163#define IL_DL_TX (1 << 23)
3164/* 0x0F000000 - 0x01000000 */
3165#define IL_DL_RX (1 << 24)
3166#define IL_DL_ISR (1 << 25)
3167#define IL_DL_HT (1 << 26)
3168/* 0xF0000000 - 0x10000000 */
3169#define IL_DL_11H (1 << 28)
3170#define IL_DL_STATS (1 << 29)
3171#define IL_DL_TX_REPLY (1 << 30)
3172#define IL_DL_QOS (1 << 31)
3173
3174#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3175#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3176#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3177#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3178#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3179#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3180#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3181#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3182#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3183#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3184#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3185#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3186#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3187#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3188#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3189#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3190#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3191#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3192#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3193#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3194#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3195#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3196#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3197#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3198#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3199#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3200#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3201#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3202#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3203
e2ebc833 3204#endif /* __il_core_h__ */
Linux kernel - Deliverables
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