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iwlegacy: remove temp_ops
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.h
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
e94a4099 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
be663ab6 4 *
e94a4099
SG		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
be663ab6
WYG		 7 * published by the Free Software Foundation.
8 *
e94a4099
SG		 9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
be663ab6 13 *
e94a4099
SG		 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
be663ab6 17 *
e94a4099
SG		 18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
be663ab6
WYG		 20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
e94a4099
SG		 25 *****************************************************************************/
26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
e7392364 30#include <linux/pci.h> /* for struct pci_device_id */
e94a4099
SG		 31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
17d4eca6 34#include <linux/io.h>
47ef694d 35#include <net/mac80211.h>
e94a4099
SG		 36#include <net/ieee80211_radiotap.h>
37
99412002 38#include "commands.h"
e94a4099 39#include "csr.h"
e8c39d4e 40#include "prph.h"
e94a4099
SG		 41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
f02579e3
SG		 46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
e94a4099
SG		 50#define RX_QUEUE_SIZE 256
51#define RX_QUEUE_MASK 255
52#define RX_QUEUE_SIZE_LOG 8
53
54/*
55 * RX related structures and functions
56 */
57#define RX_FREE_BUFFERS 64
58#define RX_LOW_WATERMARK 8
59
60#define U32_PAD(n) ((4-(n))&0x3)
61
62/* CT-KILL constants */
e7392364 63#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
e94a4099
SG		 64
65/* Default noise level to report when noise measurement is not available.
66 * This may be because we're:
67 * 1) Not associated (4965, no beacon stats being sent to driver)
68 * 2) Scanning (noise measurement does not apply to associated channel)
69 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
70 * Use default noise value of -127 ... this is below the range of measurable
71 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
72 * Also, -127 works better than 0 when averaging frames with/without
73 * noise info (e.g. averaging might be done in app); measured dBm values are
74 * always negative ... using a negative value as the default keeps all
75 * averages within an s8's (used in some apps) range of negative values. */
76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
77
78/*
79 * RTS threshold here is total size [2347] minus 4 FCS bytes
80 * Per spec:
81 * a value of 0 means RTS on all data/management packets
82 * a value > max MSDU size means no RTS
83 * else RTS for data/management frames where MPDU is larger
84 * than RTS value.
85 */
86#define DEFAULT_RTS_THRESHOLD 2347U
87#define MIN_RTS_THRESHOLD 0U
88#define MAX_RTS_THRESHOLD 2347U
89#define MAX_MSDU_SIZE 2304U
90#define MAX_MPDU_SIZE 2346U
91#define DEFAULT_BEACON_INTERVAL 100U
92#define DEFAULT_SHORT_RETRY_LIMIT 7U
93#define DEFAULT_LONG_RETRY_LIMIT 4U
94
95struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99};
100
101#define rxb_addr(r) page_address(r->page)
102
103/* defined below */
104struct il_device_cmd;
105
106struct il_cmd_meta {
107 /* only for SYNC commands, iff the reply skb is wanted */
108 struct il_host_cmd *source;
109 /*
110 * only for ASYNC commands
111 * (which is somewhat stupid -- look at common.c for instance
112 * which duplicates a bunch of code because the callback isn't
113 * invoked for SYNC commands, if it were and its result passed
114 * through it would be simpler...)
115 */
1722f8e1
SG		 116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
e94a4099
SG		 118
119 /* The CMD_SIZE_HUGE flag bit indicates that the command
120 * structure is stored at the end of the shared queue memory. */
121 u32 flags;
122
e7392364
SG		 123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
e94a4099
SG		 125};
126
127/*
128 * Generic queue structure
129 *
130 * Contains common data for Rx and Tx queues
131 */
132struct il_queue {
e7392364
SG		 133 int n_bd; /* number of BDs in this queue */
134 int write_ptr; /* 1-st empty entry (idx) host_w */
135 int read_ptr; /* last used entry (idx) host_r */
e94a4099 136 /* use for monitoring and recovering the stuck queue */
e7392364
SG		 137 dma_addr_t dma_addr; /* physical addr for BD's */
138 int n_win; /* safe queue win */
e94a4099 139 u32 id;
e7392364
SG		 140 int low_mark; /* low watermark, resume queue if free
141 * space more than this */
142 int high_mark; /* high watermark, stop queue if free
143 * space less than this */
e94a4099
SG		 144};
145
e94a4099
SG		 146/**
147 * struct il_tx_queue - Tx Queue for DMA
148 * @q: generic Rx/Tx queue descriptor
149 * @bd: base of circular buffer of TFDs
150 * @cmd: array of command/TX buffer pointers
151 * @meta: array of meta data for each command/tx buffer
152 * @dma_addr_cmd: physical address of cmd/tx buffer array
00ea99e1 153 * @skbs: array of per-TFD socket buffer pointers
e94a4099
SG		 154 * @time_stamp: time (in jiffies) of last read_ptr change
155 * @need_update: indicates need to update read/write idx
156 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
157 *
158 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
159 * descriptors) and required locking structures.
160 */
161#define TFD_TX_CMD_SLOTS 256
162#define TFD_CMD_SLOTS 32
163
164struct il_tx_queue {
165 struct il_queue q;
166 void *tfds;
167 struct il_device_cmd **cmd;
168 struct il_cmd_meta *meta;
00ea99e1 169 struct sk_buff **skbs;
e94a4099
SG		 170 unsigned long time_stamp;
171 u8 need_update;
172 u8 sched_retry;
173 u8 active;
174 u8 swq_id;
175};
176
47ef694d
SG		 177/*
178 * EEPROM access time values:
179 *
180 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
181 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
182 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
183 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
184 */
e7392364 185#define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
47ef694d 186
e7392364
SG		 187#define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
188#define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
47ef694d
SG		 189
190/*
191 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
192 *
193 * IBSS and/or AP operation is allowed *only* on those channels with
194 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
195 * RADAR detection is not supported by the 4965 driver, but is a
196 * requirement for establishing a new network for legal operation on channels
197 * requiring RADAR detection or restricting ACTIVE scanning.
198 *
199 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
200 * It only indicates that 20 MHz channel use is supported; HT40 channel
201 * usage is indicated by a separate set of regulatory flags for each
202 * HT40 channel pair.
203 *
204 * NOTE: Using a channel inappropriately will result in a uCode error!
205 */
206#define IL_NUM_TX_CALIB_GROUPS 5
207enum {
208 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
e7392364 209 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
47ef694d
SG		 210 /* Bit 2 Reserved */
211 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
212 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
e7392364 213 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
47ef694d
SG		 214 /* Bit 6 Reserved (was Narrow Channel) */
215 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
216};
217
218/* SKU Capabilities */
219/* 3945 only */
220#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
221#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
222
223/* *regulatory* channel data format in eeprom, one for each channel.
224 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
225struct il_eeprom_channel {
226 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
227 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
228} __packed;
229
230/* 3945 Specific */
231#define EEPROM_3945_EEPROM_VERSION (0x2f)
232
233/* 4965 has two radio transmitters (and 3 radio receivers) */
234#define EEPROM_TX_POWER_TX_CHAINS (2)
235
236/* 4965 has room for up to 8 sets of txpower calibration data */
237#define EEPROM_TX_POWER_BANDS (8)
238
239/* 4965 factory calibration measures txpower gain settings for
240 * each of 3 target output levels */
241#define EEPROM_TX_POWER_MEASUREMENTS (3)
242
243/* 4965 Specific */
244/* 4965 driver does not work with txpower calibration version < 5 */
245#define EEPROM_4965_TX_POWER_VERSION (5)
246#define EEPROM_4965_EEPROM_VERSION (0x2f)
e7392364
SG		 247#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
248#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
249#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
250#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
47ef694d
SG		 251
252/* 2.4 GHz */
253extern const u8 il_eeprom_band_1[14];
254
255/*
256 * factory calibration data for one txpower level, on one channel,
257 * measured on one of the 2 tx chains (radio transmitter and associated
258 * antenna). EEPROM contains:
259 *
260 * 1) Temperature (degrees Celsius) of device when measurement was made.
261 *
262 * 2) Gain table idx used to achieve the target measurement power.
263 * This refers to the "well-known" gain tables (see 4965.h).
264 *
265 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
266 *
267 * 4) RF power amplifier detector level measurement (not used).
268 */
269struct il_eeprom_calib_measure {
270 u8 temperature; /* Device temperature (Celsius) */
271 u8 gain_idx; /* Index into gain table */
272 u8 actual_pow; /* Measured RF output power, half-dBm */
273 s8 pa_det; /* Power amp detector level (not used) */
274} __packed;
275
47ef694d
SG		 276/*
277 * measurement set for one channel. EEPROM contains:
278 *
279 * 1) Channel number measured
280 *
281 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
282 * (a.k.a. "tx chains") (6 measurements altogether)
283 */
284struct il_eeprom_calib_ch_info {
285 u8 ch_num;
286 struct il_eeprom_calib_measure
e7392364
SG		 287 measurements[EEPROM_TX_POWER_TX_CHAINS]
288 [EEPROM_TX_POWER_MEASUREMENTS];
47ef694d
SG		 289} __packed;
290
291/*
292 * txpower subband info.
293 *
294 * For each frequency subband, EEPROM contains the following:
295 *
296 * 1) First and last channels within range of the subband. "0" values
297 * indicate that this sample set is not being used.
298 *
299 * 2) Sample measurement sets for 2 channels close to the range endpoints.
300 */
301struct il_eeprom_calib_subband_info {
e7392364
SG		 302 u8 ch_from; /* channel number of lowest channel in subband */
303 u8 ch_to; /* channel number of highest channel in subband */
47ef694d
SG		 304 struct il_eeprom_calib_ch_info ch1;
305 struct il_eeprom_calib_ch_info ch2;
306} __packed;
307
47ef694d
SG		 308/*
309 * txpower calibration info. EEPROM contains:
310 *
311 * 1) Factory-measured saturation power levels (maximum levels at which
312 * tx power amplifier can output a signal without too much distortion).
313 * There is one level for 2.4 GHz band and one for 5 GHz band. These
314 * values apply to all channels within each of the bands.
315 *
316 * 2) Factory-measured power supply voltage level. This is assumed to be
317 * constant (i.e. same value applies to all channels/bands) while the
318 * factory measurements are being made.
319 *
320 * 3) Up to 8 sets of factory-measured txpower calibration values.
321 * These are for different frequency ranges, since txpower gain
322 * characteristics of the analog radio circuitry vary with frequency.
323 *
324 * Not all sets need to be filled with data;
325 * struct il_eeprom_calib_subband_info contains range of channels
326 * (0 if unused) for each set of data.
327 */
328struct il_eeprom_calib_info {
329 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
330 u8 saturation_power52; /* half-dBm */
331 __le16 voltage; /* signed */
e7392364 332 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
47ef694d
SG		 333} __packed;
334
47ef694d
SG		 335/* General */
336#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
337#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
338#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
339#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
340#define EEPROM_VERSION (2*0x44) /* 2 bytes */
341#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
342#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
343#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
344#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
345#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
346
347/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
e7392364
SG		 348#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
349#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
350#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
351#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
352#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
353#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
47ef694d
SG		 354
355#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
356#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
357
358/*
359 * Per-channel regulatory data.
360 *
361 * Each channel that *might* be supported by iwl has a fixed location
362 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
363 * txpower (MSB).
364 *
365 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
366 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
367 *
368 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
369 */
e7392364 370#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
47ef694d
SG		 371#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
372#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
373
374/*
375 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
376 * 5.0 GHz channels 7, 8, 11, 12, 16
377 * (4915-5080MHz) (none of these is ever supported)
378 */
379#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
380#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
381
382/*
383 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
384 * (5170-5320MHz)
385 */
386#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
387#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
388
389/*
390 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
391 * (5500-5700MHz)
392 */
393#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
394#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
395
396/*
397 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
398 * (5725-5825MHz)
399 */
400#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
401#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
402
403/*
404 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
405 *
406 * The channel listed is the center of the lower 20 MHz half of the channel.
407 * The overall center frequency is actually 2 channels (10 MHz) above that,
408 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
409 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
410 * and the overall HT40 channel width centers on channel 3.
411 *
412 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
413 * control channel to which to tune. RXON also specifies whether the
414 * control channel is the upper or lower half of a HT40 channel.
415 *
416 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
417 */
418#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
419
420/*
421 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
422 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
423 */
424#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
425
426#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
427
428struct il_eeprom_ops {
1722f8e1
SG		 429 int (*acquire_semaphore) (struct il_priv *il);
430 void (*release_semaphore) (struct il_priv *il);
47ef694d
SG		 431};
432
47ef694d
SG		 433int il_eeprom_init(struct il_priv *il);
434void il_eeprom_free(struct il_priv *il);
e7392364 435const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
47ef694d
SG		 436u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
437int il_init_channel_map(struct il_priv *il);
438void il_free_channel_map(struct il_priv *il);
e7392364
SG		 439const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
440 enum ieee80211_band band,
441 u16 channel);
47ef694d 442
e94a4099
SG		 443#define IL_NUM_SCAN_RATES (2)
444
445struct il4965_channel_tgd_info {
446 u8 type;
447 s8 max_power;
448};
449
450struct il4965_channel_tgh_info {
451 s64 last_radar_time;
452};
453
454#define IL4965_MAX_RATE (33)
455
456struct il3945_clip_group {
457 /* maximum power level to prevent clipping for each rate, derived by
458 * us from this band's saturation power in EEPROM */
459 const s8 clip_powers[IL_MAX_RATES];
460};
461
462/* current Tx power values to use, one for each rate for each channel.
463 * requested power is limited by:
464 * -- regulatory EEPROM limits for this channel
465 * -- hardware capabilities (clip-powers)
466 * -- spectrum management
467 * -- user preference (e.g. iwconfig)
468 * when requested power is set, base power idx must also be set. */
469struct il3945_channel_power_info {
470 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
471 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
472 s8 base_power_idx; /* gain idx for power at factory temp. */
473 s8 requested_power; /* power (dBm) requested for this chnl/rate */
474};
475
476/* current scan Tx power values to use, one for each scan rate for each
477 * channel. */
478struct il3945_scan_power_info {
479 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
480 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
481 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
482};
483
484/*
485 * One for each channel, holds all channel setup data
486 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
487 * with one another!
488 */
489struct il_channel_info {
490 struct il4965_channel_tgd_info tgd;
491 struct il4965_channel_tgh_info tgh;
492 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
493 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
494 * HT40 channel */
495
e7392364
SG		 496 u8 channel; /* channel number */
497 u8 flags; /* flags copied from EEPROM */
498 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
499 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
500 s8 min_power; /* always 0 */
501 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
e94a4099 502
e7392364
SG		 503 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
504 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
e94a4099
SG		 505 enum ieee80211_band band;
506
507 /* HT40 channel info */
508 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
509 u8 ht40_flags; /* flags copied from EEPROM */
e7392364 510 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
e94a4099
SG		 511
512 /* Radio/DSP gain settings for each "normal" data Tx rate.
513 * These include, in addition to RF and DSP gain, a few fields for
514 * remembering/modifying gain settings (idxes). */
515 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
516
517 /* Radio/DSP gain settings for each scan rate, for directed scans. */
518 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
519};
520
521#define IL_TX_FIFO_BK 0 /* shared */
522#define IL_TX_FIFO_BE 1
523#define IL_TX_FIFO_VI 2 /* shared */
524#define IL_TX_FIFO_VO 3
525#define IL_TX_FIFO_UNUSED -1
526
527/* Minimum number of queues. MAX_NUM is defined in hw specific files.
528 * Set the minimum to accommodate the 4 standard TX queues, 1 command
529 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
530#define IL_MIN_NUM_QUEUES 10
531
532#define IL_DEFAULT_CMD_QUEUE_NUM 4
533
534#define IEEE80211_DATA_LEN 2304
535#define IEEE80211_4ADDR_LEN 30
536#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
537#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
538
539struct il_frame {
540 union {
541 struct ieee80211_hdr frame;
542 struct il_tx_beacon_cmd beacon;
543 u8 raw[IEEE80211_FRAME_LEN];
544 u8 cmd[360];
545 } u;
546 struct list_head list;
547};
548
549#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
550#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
551#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
552
553enum {
554 CMD_SYNC = 0,
555 CMD_SIZE_NORMAL = 0,
556 CMD_NO_SKB = 0,
557 CMD_SIZE_HUGE = (1 << 0),
558 CMD_ASYNC = (1 << 1),
559 CMD_WANT_SKB = (1 << 2),
560 CMD_MAPPED = (1 << 3),
561};
562
563#define DEF_CMD_PAYLOAD_SIZE 320
564
565/**
566 * struct il_device_cmd
567 *
568 * For allocation of the command and tx queues, this establishes the overall
569 * size of the largest command we send to uCode, except for a scan command
570 * (which is relatively huge; space is allocated separately).
571 */
572struct il_device_cmd {
573 struct il_cmd_header hdr; /* uCode API */
574 union {
575 u32 flags;
576 u8 val8;
577 u16 val16;
578 u32 val32;
579 struct il_tx_cmd tx;
580 u8 payload[DEF_CMD_PAYLOAD_SIZE];
581 } __packed cmd;
582} __packed;
583
584#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
585
e94a4099
SG		 586struct il_host_cmd {
587 const void *data;
588 unsigned long reply_page;
1722f8e1
SG		 589 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
590 struct il_rx_pkt *pkt);
e94a4099
SG		 591 u32 flags;
592 u16 len;
593 u8 id;
594};
595
596#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
597#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
598#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
599
600/**
601 * struct il_rx_queue - Rx queue
602 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
603 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
604 * @read: Shared idx to newest available Rx buffer
605 * @write: Shared idx to oldest written Rx packet
606 * @free_count: Number of pre-allocated buffers in rx_free
607 * @rx_free: list of free SKBs for use
608 * @rx_used: List of Rx buffers with no SKB
609 * @need_update: flag to indicate we need to update read/write idx
610 * @rb_stts: driver's pointer to receive buffer status
611 * @rb_stts_dma: bus address of receive buffer status
612 *
613 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
614 */
615struct il_rx_queue {
616 __le32 *bd;
617 dma_addr_t bd_dma;
618 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
619 struct il_rx_buf *queue[RX_QUEUE_SIZE];
620 u32 read;
621 u32 write;
622 u32 free_count;
623 u32 write_actual;
624 struct list_head rx_free;
625 struct list_head rx_used;
626 int need_update;
627 struct il_rb_status *rb_stts;
628 dma_addr_t rb_stts_dma;
629 spinlock_t lock;
630};
631
632#define IL_SUPPORTED_RATES_IE_LEN 8
633
634#define MAX_TID_COUNT 9
635
636#define IL_INVALID_RATE 0xFF
637#define IL_INVALID_VALUE -1
638
639/**
640 * struct il_ht_agg -- aggregation status while waiting for block-ack
641 * @txq_id: Tx queue used for Tx attempt
642 * @frame_count: # frames attempted by Tx command
643 * @wait_for_ba: Expect block-ack before next Tx reply
644 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
645 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
646 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
647 * @rate_n_flags: Rate at which Tx was attempted
648 *
649 * If C_TX indicates that aggregation was attempted, driver must wait
650 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
651 * until block ack arrives.
652 */
653struct il_ht_agg {
654 u16 txq_id;
655 u16 frame_count;
656 u16 wait_for_ba;
657 u16 start_idx;
658 u64 bitmap;
659 u32 rate_n_flags;
660#define IL_AGG_OFF 0
661#define IL_AGG_ON 1
662#define IL_EMPTYING_HW_QUEUE_ADDBA 2
663#define IL_EMPTYING_HW_QUEUE_DELBA 3
664 u8 state;
665};
666
e94a4099 667struct il_tid_data {
e7392364 668 u16 seq_number; /* 4965 only */
e94a4099
SG		 669 u16 tfds_in_queue;
670 struct il_ht_agg agg;
671};
672
673struct il_hw_key {
674 u32 cipher;
675 int keylen;
676 u8 keyidx;
677 u8 key[32];
678};
679
680union il_ht_rate_supp {
681 u16 rates;
682 struct {
683 u8 siso_rate;
684 u8 mimo_rate;
685 };
686};
687
688#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
689#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
690#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
691#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
692#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
693#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
694#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
695
696/*
697 * Maximal MPDU density for TX aggregation
698 * 4 - 2us density
699 * 5 - 4us density
700 * 6 - 8us density
701 * 7 - 16us density
702 */
703#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
704#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
705#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
706#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
707#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
708#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
709#define CFG_HT_MPDU_DENSITY_MIN (0x1)
710
711struct il_ht_config {
712 bool single_chain_sufficient;
e7392364 713 enum ieee80211_smps_mode smps; /* current smps mode */
e94a4099
SG		 714};
715
716/* QoS structures */
717struct il_qos_info {
718 int qos_active;
719 struct il_qosparam_cmd def_qos_parm;
720};
721
722/*
723 * Structure should be accessed with sta_lock held. When station addition
724 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
725 * the commands (il_addsta_cmd and il_link_quality_cmd) without
726 * sta_lock held.
727 */
728struct il_station_entry {
729 struct il_addsta_cmd sta;
730 struct il_tid_data tid[MAX_TID_COUNT];
6aa0c254 731 u8 used;
e94a4099
SG		 732 struct il_hw_key keyinfo;
733 struct il_link_quality_cmd *lq;
734};
735
736struct il_station_priv_common {
e94a4099
SG		 737 u8 sta_id;
738};
739
e94a4099
SG		 740/**
741 * struct il_vif_priv - driver's ilate per-interface information
742 *
743 * When mac80211 allocates a virtual interface, it can allocate
744 * space for us to put data into.
745 */
746struct il_vif_priv {
e94a4099
SG		 747 u8 ibss_bssid_sta_id;
748};
749
750/* one for each uCode image (inst/data, boot/init/runtime) */
751struct fw_desc {
752 void *v_addr; /* access by driver */
753 dma_addr_t p_addr; /* access by card's busmaster DMA */
754 u32 len; /* bytes */
755};
756
757/* uCode file layout */
758struct il_ucode_header {
e7392364 759 __le32 ver; /* major/minor/API/serial */
e94a4099
SG		 760 struct {
761 __le32 inst_size; /* bytes of runtime code */
762 __le32 data_size; /* bytes of runtime data */
763 __le32 init_size; /* bytes of init code */
764 __le32 init_data_size; /* bytes of init data */
765 __le32 boot_size; /* bytes of bootstrap code */
e7392364 766 u8 data[0]; /* in same order as sizes */
e94a4099
SG		 767 } v1;
768};
769
770struct il4965_ibss_seq {
771 u8 mac[ETH_ALEN];
772 u16 seq_num;
773 u16 frag_num;
774 unsigned long packet_time;
775 struct list_head list;
776};
777
778struct il_sensitivity_ranges {
779 u16 min_nrg_cck;
780 u16 max_nrg_cck;
781
782 u16 nrg_th_cck;
783 u16 nrg_th_ofdm;
784
785 u16 auto_corr_min_ofdm;
786 u16 auto_corr_min_ofdm_mrc;
787 u16 auto_corr_min_ofdm_x1;
788 u16 auto_corr_min_ofdm_mrc_x1;
789
790 u16 auto_corr_max_ofdm;
791 u16 auto_corr_max_ofdm_mrc;
792 u16 auto_corr_max_ofdm_x1;
793 u16 auto_corr_max_ofdm_mrc_x1;
794
795 u16 auto_corr_max_cck;
796 u16 auto_corr_max_cck_mrc;
797 u16 auto_corr_min_cck;
798 u16 auto_corr_min_cck_mrc;
799
800 u16 barker_corr_th_min;
801 u16 barker_corr_th_min_mrc;
802 u16 nrg_th_cca;
803};
804
e94a4099
SG		 805#define KELVIN_TO_CELSIUS(x) ((x)-273)
806#define CELSIUS_TO_KELVIN(x) ((x)+273)
807
e94a4099
SG		 808/**
809 * struct il_hw_params
b16db50a 810 * @bcast_id: f/w broadcast station ID
e94a4099
SG		 811 * @max_txq_num: Max # Tx queues supported
812 * @dma_chnl_num: Number of Tx DMA/FIFO channels
813 * @scd_bc_tbls_size: size of scheduler byte count tables
814 * @tfd_size: TFD size
815 * @tx/rx_chains_num: Number of TX/RX chains
816 * @valid_tx/rx_ant: usable antennas
817 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
818 * @max_rxq_log: Log-base-2 of max_rxq_size
819 * @rx_page_order: Rx buffer page order
820 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
821 * @max_stations:
822 * @ht40_channel: is 40MHz width possible in band 2.4
823 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
824 * @sw_crypto: 0 for hw, 1 for sw
825 * @max_xxx_size: for ucode uses
826 * @ct_kill_threshold: temperature threshold
827 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
828 * @struct il_sensitivity_ranges: range of sensitivity values
829 */
830struct il_hw_params {
b16db50a 831 u8 bcast_id;
e94a4099
SG		 832 u8 max_txq_num;
833 u8 dma_chnl_num;
834 u16 scd_bc_tbls_size;
835 u32 tfd_size;
e7392364
SG		 836 u8 tx_chains_num;
837 u8 rx_chains_num;
838 u8 valid_tx_ant;
839 u8 valid_rx_ant;
e94a4099
SG		 840 u16 max_rxq_size;
841 u16 max_rxq_log;
842 u32 rx_page_order;
843 u32 rx_wrt_ptr_reg;
e7392364
SG		 844 u8 max_stations;
845 u8 ht40_channel;
846 u8 max_beacon_itrvl; /* in 1024 ms */
e94a4099
SG		 847 u32 max_inst_size;
848 u32 max_data_size;
849 u32 max_bsm_size;
e7392364 850 u32 ct_kill_threshold; /* value in hw-dependent units */
e94a4099
SG		 851 u16 beacon_time_tsf_bits;
852 const struct il_sensitivity_ranges *sens;
853};
854
e94a4099
SG		 855/******************************************************************************
856 *
857 * Functions implemented in core module which are forward declared here
858 * for use by iwl-[4-5].c
859 *
860 * NOTE: The implementation of these functions are not hardware specific
861 * which is why they are in the core module files.
862 *
863 * Naming convention --
864 * il_ <-- Is part of iwlwifi
865 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
866 * il4965_bg_ <-- Called from work queue context
867 * il4965_mac_ <-- mac80211 callback
868 *
869 ****************************************************************************/
870extern void il4965_update_chain_flags(struct il_priv *il);
871extern const u8 il_bcast_addr[ETH_ALEN];
872extern int il_queue_space(const struct il_queue *q);
e7392364
SG		 873static inline int
874il_queue_used(const struct il_queue *q, int i)
e94a4099 875{
e7392364
SG		 876 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
877 i < q->write_ptr) : !(i <
878 q->read_ptr
879 && i >=
880 q->
881 write_ptr);
e94a4099
SG		 882}
883
e7392364
SG		 884static inline u8
885il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
e94a4099
SG		 886{
887 /*
888 * This is for init calibration result and scan command which
889 * required buffer > TFD_MAX_PAYLOAD_SIZE,
890 * the big buffer at end of command array
891 */
892 if (is_huge)
893 return q->n_win; /* must be power of 2 */
894
895 /* Otherwise, use normal size buffers */
896 return idx & (q->n_win - 1);
897}
898
e94a4099
SG		 899struct il_dma_ptr {
900 dma_addr_t dma;
901 void *addr;
902 size_t size;
903};
904
905#define IL_OPERATION_MODE_AUTO 0
906#define IL_OPERATION_MODE_HT_ONLY 1
907#define IL_OPERATION_MODE_MIXED 2
908#define IL_OPERATION_MODE_20MHZ 3
909
910#define IL_TX_CRC_SIZE 4
911#define IL_TX_DELIMITER_SIZE 4
912
913#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
914
915/* Sensitivity and chain noise calibration */
916#define INITIALIZATION_VALUE 0xFFFF
917#define IL4965_CAL_NUM_BEACONS 20
918#define IL_CAL_NUM_BEACONS 16
919#define MAXIMUM_ALLOWED_PATHLOSS 15
920
921#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
922
923#define MAX_FA_OFDM 50
924#define MIN_FA_OFDM 5
925#define MAX_FA_CCK 50
926#define MIN_FA_CCK 5
927
928#define AUTO_CORR_STEP_OFDM 1
929
930#define AUTO_CORR_STEP_CCK 3
931#define AUTO_CORR_MAX_TH_CCK 160
932
933#define NRG_DIFF 2
934#define NRG_STEP_CCK 2
935#define NRG_MARGIN 8
936#define MAX_NUMBER_CCK_NO_FA 100
937
938#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
939
940#define CHAIN_A 0
941#define CHAIN_B 1
942#define CHAIN_C 2
943#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
944#define ALL_BAND_FILTER 0xFF00
945#define IN_BAND_FILTER 0xFF
946#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
947
948#define NRG_NUM_PREV_STAT_L 20
949#define NUM_RX_CHAINS 3
950
951enum il4965_false_alarm_state {
952 IL_FA_TOO_MANY = 0,
953 IL_FA_TOO_FEW = 1,
954 IL_FA_GOOD_RANGE = 2,
955};
956
957enum il4965_chain_noise_state {
e7392364 958 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
e94a4099
SG		 959 IL_CHAIN_NOISE_ACCUMULATE,
960 IL_CHAIN_NOISE_CALIBRATED,
961 IL_CHAIN_NOISE_DONE,
962};
963
964enum il4965_calib_enabled_state {
e7392364 965 IL_CALIB_DISABLED = 0, /* must be 0 */
e94a4099
SG		 966 IL_CALIB_ENABLED = 1,
967};
968
969/*
970 * enum il_calib
971 * defines the order in which results of initial calibrations
972 * should be sent to the runtime uCode
973 */
974enum il_calib {
975 IL_CALIB_MAX,
976};
977
978/* Opaque calibration results */
979struct il_calib_result {
980 void *buf;
981 size_t buf_len;
982};
983
984enum ucode_type {
985 UCODE_NONE = 0,
986 UCODE_INIT,
987 UCODE_RT
988};
989
990/* Sensitivity calib data */
991struct il_sensitivity_data {
992 u32 auto_corr_ofdm;
993 u32 auto_corr_ofdm_mrc;
994 u32 auto_corr_ofdm_x1;
995 u32 auto_corr_ofdm_mrc_x1;
996 u32 auto_corr_cck;
997 u32 auto_corr_cck_mrc;
998
999 u32 last_bad_plcp_cnt_ofdm;
1000 u32 last_fa_cnt_ofdm;
1001 u32 last_bad_plcp_cnt_cck;
1002 u32 last_fa_cnt_cck;
1003
1004 u32 nrg_curr_state;
1005 u32 nrg_prev_state;
1006 u32 nrg_value[10];
e7392364 1007 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
e94a4099
SG		 1008 u32 nrg_silence_ref;
1009 u32 nrg_energy_idx;
1010 u32 nrg_silence_idx;
1011 u32 nrg_th_cck;
1012 s32 nrg_auto_corr_silence_diff;
1013 u32 num_in_cck_no_fa;
1014 u32 nrg_th_ofdm;
1015
1016 u16 barker_corr_th_min;
1017 u16 barker_corr_th_min_mrc;
1018 u16 nrg_th_cca;
1019};
1020
1021/* Chain noise (differential Rx gain) calib data */
1022struct il_chain_noise_data {
1023 u32 active_chains;
1024 u32 chain_noise_a;
1025 u32 chain_noise_b;
1026 u32 chain_noise_c;
1027 u32 chain_signal_a;
1028 u32 chain_signal_b;
1029 u32 chain_signal_c;
1030 u16 beacon_count;
1031 u8 disconn_array[NUM_RX_CHAINS];
1032 u8 delta_gain_code[NUM_RX_CHAINS];
1033 u8 radio_write;
1034 u8 state;
1035};
1036
e7392364 1037#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
e94a4099
SG		 1038#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1039
1040#define IL_TRAFFIC_ENTRIES (256)
1041#define IL_TRAFFIC_ENTRY_SIZE (64)
1042
1043enum {
1044 MEASUREMENT_READY = (1 << 0),
1045 MEASUREMENT_ACTIVE = (1 << 1),
1046};
1047
1048/* interrupt stats */
1049struct isr_stats {
1050 u32 hw;
1051 u32 sw;
1052 u32 err_code;
1053 u32 sch;
1054 u32 alive;
1055 u32 rfkill;
1056 u32 ctkill;
1057 u32 wakeup;
1058 u32 rx;
1059 u32 handlers[IL_CN_MAX];
1060 u32 tx;
1061 u32 unhandled;
1062};
1063
1064/* management stats */
1065enum il_mgmt_stats {
1066 MANAGEMENT_ASSOC_REQ = 0,
1067 MANAGEMENT_ASSOC_RESP,
1068 MANAGEMENT_REASSOC_REQ,
1069 MANAGEMENT_REASSOC_RESP,
1070 MANAGEMENT_PROBE_REQ,
1071 MANAGEMENT_PROBE_RESP,
1072 MANAGEMENT_BEACON,
1073 MANAGEMENT_ATIM,
1074 MANAGEMENT_DISASSOC,
1075 MANAGEMENT_AUTH,
1076 MANAGEMENT_DEAUTH,
1077 MANAGEMENT_ACTION,
1078 MANAGEMENT_MAX,
1079};
1080/* control stats */
1081enum il_ctrl_stats {
e7392364 1082 CONTROL_BACK_REQ = 0,
e94a4099
SG		 1083 CONTROL_BACK,
1084 CONTROL_PSPOLL,
1085 CONTROL_RTS,
1086 CONTROL_CTS,
1087 CONTROL_ACK,
1088 CONTROL_CFEND,
1089 CONTROL_CFENDACK,
1090 CONTROL_MAX,
1091};
1092
1093struct traffic_stats {
1094#ifdef CONFIG_IWLEGACY_DEBUGFS
1095 u32 mgmt[MANAGEMENT_MAX];
1096 u32 ctrl[CONTROL_MAX];
1097 u32 data_cnt;
1098 u64 data_bytes;
1099#endif
1100};
1101
1102/*
1103 * host interrupt timeout value
1104 * used with setting interrupt coalescing timer
1105 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1106 *
1107 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1108 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1109 */
1110#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1111#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1112#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1113#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1114#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1115#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1116
1117#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1118
1119/* TX queue watchdog timeouts in mSecs */
1120#define IL_DEF_WD_TIMEOUT (2000)
1121#define IL_LONG_WD_TIMEOUT (10000)
1122#define IL_MAX_WD_TIMEOUT (120000)
1123
1124struct il_force_reset {
1125 int reset_request_count;
1126 int reset_success_count;
1127 int reset_reject_count;
1128 unsigned long reset_duration;
1129 unsigned long last_force_reset_jiffies;
1130};
1131
1132/* extend beacon time format bit shifting */
1133/*
1134 * for _3945 devices
1135 * bits 31:24 - extended
1136 * bits 23:0 - interval
1137 */
1138#define IL3945_EXT_BEACON_TIME_POS 24
1139/*
1140 * for _4965 devices
1141 * bits 31:22 - extended
1142 * bits 21:0 - interval
1143 */
1144#define IL4965_EXT_BEACON_TIME_POS 22
1145
1146struct il_rxon_context {
1147 struct ieee80211_vif *vif;
e94a4099
SG		 1148};
1149
99412002
SG		 1150struct il_power_mgr {
1151 struct il_powertable_cmd sleep_cmd;
1152 struct il_powertable_cmd sleep_cmd_next;
1153 int debug_sleep_level_override;
1154 bool pci_pm;
1155};
1156
e94a4099 1157struct il_priv {
e94a4099
SG		 1158 struct ieee80211_hw *hw;
1159 struct ieee80211_channel *ieee_channels;
1160 struct ieee80211_rate *ieee_rates;
93b7654e 1161
e94a4099 1162 struct il_cfg *cfg;
c39ae9fd 1163 const struct il_ops *ops;
93b7654e
SG		 1164#ifdef CONFIG_IWLEGACY_DEBUGFS
1165 const struct il_debugfs_ops *debugfs_ops;
1166#endif
e94a4099
SG		 1167
1168 /* temporary frame storage list */
1169 struct list_head free_frames;
1170 int frames_count;
1171
1172 enum ieee80211_band band;
1173 int alloc_rxb_page;
1174
1722f8e1
SG		 1175 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1176 struct il_rx_buf *rxb);
e94a4099
SG		 1177
1178 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1179
1180 /* spectrum measurement report caching */
1181 struct il_spectrum_notification measure_report;
1182 u8 measurement_status;
1183
1184 /* ucode beacon time */
1185 u32 ucode_beacon_time;
1186 int missed_beacon_threshold;
1187
1188 /* track IBSS manager (last beacon) status */
1189 u32 ibss_manager;
1190
1191 /* force reset */
1192 struct il_force_reset force_reset;
1193
1194 /* we allocate array of il_channel_info for NIC's valid channels.
1195 * Access via channel # using indirect idx array */
1196 struct il_channel_info *channel_info; /* channel info array */
1197 u8 channel_count; /* # of channels */
1198
1199 /* thermal calibration */
1200 s32 temperature; /* degrees Kelvin */
1201 s32 last_temperature;
1202
1203 /* init calibration results */
1204 struct il_calib_result calib_results[IL_CALIB_MAX];
1205
1206 /* Scan related variables */
1207 unsigned long scan_start;
1208 unsigned long scan_start_tsf;
1209 void *scan_cmd;
1210 enum ieee80211_band scan_band;
1211 struct cfg80211_scan_request *scan_request;
1212 struct ieee80211_vif *scan_vif;
1213 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1214 u8 mgmt_tx_ant;
1215
1216 /* spinlock */
1217 spinlock_t lock; /* protect general shared data */
1218 spinlock_t hcmd_lock; /* protect hcmd */
1219 spinlock_t reg_lock; /* protect hw register access */
1220 struct mutex mutex;
1221
1222 /* basic pci-network driver stuff */
1223 struct pci_dev *pci_dev;
1224
1225 /* pci hardware address support */
1226 void __iomem *hw_base;
e7392364
SG		 1227 u32 hw_rev;
1228 u32 hw_wa_rev;
1229 u8 rev_id;
e94a4099
SG		 1230
1231 /* command queue number */
1232 u8 cmd_queue;
1233
1234 /* max number of station keys */
1235 u8 sta_key_max_num;
1236
1237 /* EEPROM MAC addresses */
1238 struct mac_address addresses[1];
1239
1240 /* uCode images, save to reload in case of failure */
e7392364
SG		 1241 int fw_idx; /* firmware we're trying to load */
1242 u32 ucode_ver; /* version of ucode, copy of
1243 il_ucode.ver */
e94a4099
SG		 1244 struct fw_desc ucode_code; /* runtime inst */
1245 struct fw_desc ucode_data; /* runtime data original */
1246 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1247 struct fw_desc ucode_init; /* initialization inst */
1248 struct fw_desc ucode_init_data; /* initialization data */
1249 struct fw_desc ucode_boot; /* bootstrap inst */
1250 enum ucode_type ucode_type;
1251 u8 ucode_write_complete; /* the image write is complete */
1252 char firmware_name[25];
1253
83007196 1254 struct ieee80211_vif *vif;
e94a4099 1255
8d44f2bd
SG		 1256 struct il_qos_info qos_data;
1257
1c03c462
SG		 1258 struct {
1259 bool enabled;
1260 bool is_40mhz;
1261 bool non_gf_sta_present;
1262 u8 protection;
1263 u8 extension_chan_offset;
1264 } ht;
1265
c8b03958
SG		 1266 /*
1267 * We declare this const so it can only be
1268 * changed via explicit cast within the
1269 * routines that actually update the physical
1270 * hardware.
1271 */
1272 const struct il_rxon_cmd active;
1273 struct il_rxon_cmd staging;
1274
1275 struct il_rxon_time_cmd timing;
1276
e94a4099
SG		 1277 __le16 switch_channel;
1278
1279 /* 1st responses from initialize and runtime uCode images.
1280 * _4965's initialize alive response contains some calibration data. */
1281 struct il_init_alive_resp card_alive_init;
1282 struct il_alive_resp card_alive;
1283
1284 u16 active_rate;
1285
1286 u8 start_calib;
1287 struct il_sensitivity_data sensitivity_data;
1288 struct il_chain_noise_data chain_noise_data;
1289 __le16 sensitivity_tbl[HD_TBL_SIZE];
1290
1291 struct il_ht_config current_ht_config;
1292
1293 /* Rate scaling data */
1294 u8 retry_rate;
1295
1296 wait_queue_head_t wait_command_queue;
1297
1298 int activity_timer_active;
1299
1300 /* Rx and Tx DMA processing queues */
1301 struct il_rx_queue rxq;
1302 struct il_tx_queue *txq;
1303 unsigned long txq_ctx_active_msk;
e7392364
SG		 1304 struct il_dma_ptr kw; /* keep warm address */
1305 struct il_dma_ptr scd_bc_tbls;
e94a4099
SG		 1306
1307 u32 scd_base_addr; /* scheduler sram base address */
1308
1309 unsigned long status;
1310
1311 /* counts mgmt, ctl, and data packets */
1312 struct traffic_stats tx_stats;
1313 struct traffic_stats rx_stats;
1314
1315 /* counts interrupts */
1316 struct isr_stats isr_stats;
1317
1318 struct il_power_mgr power_data;
1319
1320 /* context information */
e7392364 1321 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
e94a4099
SG		 1322
1323 /* station table variables */
1324
1325 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1326 spinlock_t sta_lock;
1327 int num_stations;
1328 struct il_station_entry stations[IL_STATION_COUNT];
1329 unsigned long ucode_key_table;
1330
1331 /* queue refcounts */
1332#define IL_MAX_HW_QUEUES 32
1333 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1334 /* for each AC */
1335 atomic_t queue_stop_count[4];
1336
1337 /* Indication if ieee80211_ops->open has been called */
1338 u8 is_open;
1339
1340 u8 mac80211_registered;
1341
1342 /* eeprom -- this is in the card's little endian byte order */
1343 u8 *eeprom;
1344 struct il_eeprom_calib_info *calib_info;
1345
1346 enum nl80211_iftype iw_mode;
1347
1348 /* Last Rx'd beacon timestamp */
1349 u64 timestamp;
1350
1351 union {
1352#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1353 struct {
1354 void *shared_virt;
1355 dma_addr_t shared_phys;
1356
1357 struct delayed_work thermal_periodic;
1358 struct delayed_work rfkill_poll;
1359
1360 struct il3945_notif_stats stats;
1361#ifdef CONFIG_IWLEGACY_DEBUGFS
1362 struct il3945_notif_stats accum_stats;
1363 struct il3945_notif_stats delta_stats;
1364 struct il3945_notif_stats max_delta;
1365#endif
1366
1367 u32 sta_supp_rates;
1368 int last_rx_rssi; /* From Rx packet stats */
1369
1370 /* Rx'd packet timing information */
1371 u32 last_beacon_time;
1372 u64 last_tsf;
1373
1374 /*
1375 * each calibration channel group in the
1376 * EEPROM has a derived clip setting for
1377 * each rate.
1378 */
1379 const struct il3945_clip_group clip_groups[5];
1380
1381 } _3945;
1382#endif
1383#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1384 struct {
1385 struct il_rx_phy_res last_phy_res;
1386 bool last_phy_res_valid;
1387
1388 struct completion firmware_loading_complete;
1389
1390 /*
1391 * chain noise reset and gain commands are the
1392 * two extra calibration commands follows the standard
1393 * phy calibration commands
1394 */
1395 u8 phy_calib_chain_noise_reset_cmd;
1396 u8 phy_calib_chain_noise_gain_cmd;
1397
d735f921
SG		 1398 u8 key_mapping_keys;
1399 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1400
e94a4099
SG		 1401 struct il_notif_stats stats;
1402#ifdef CONFIG_IWLEGACY_DEBUGFS
1403 struct il_notif_stats accum_stats;
1404 struct il_notif_stats delta_stats;
1405 struct il_notif_stats max_delta;
1406#endif
1407
1408 } _4965;
1409#endif
1410 };
1411
1412 struct il_hw_params hw_params;
1413
1414 u32 inta_mask;
1415
1416 struct workqueue_struct *workqueue;
1417
1418 struct work_struct restart;
1419 struct work_struct scan_completed;
1420 struct work_struct rx_replenish;
1421 struct work_struct abort_scan;
1422
83007196 1423 bool beacon_enabled;
e94a4099
SG		 1424 struct sk_buff *beacon_skb;
1425
1426 struct work_struct tx_flush;
1427
1428 struct tasklet_struct irq_tasklet;
1429
1430 struct delayed_work init_alive_start;
1431 struct delayed_work alive_start;
1432 struct delayed_work scan_check;
1433
1434 /* TX Power */
1435 s8 tx_power_user_lmt;
1436 s8 tx_power_device_lmt;
1437 s8 tx_power_next;
1438
e94a4099
SG		 1439#ifdef CONFIG_IWLEGACY_DEBUG
1440 /* debugging info */
e7392364
SG		 1441 u32 debug_level; /* per device debugging will override global
1442 il_debug_level if set */
1443#endif /* CONFIG_IWLEGACY_DEBUG */
e94a4099
SG		 1444#ifdef CONFIG_IWLEGACY_DEBUGFS
1445 /* debugfs */
1446 u16 tx_traffic_idx;
1447 u16 rx_traffic_idx;
1448 u8 *tx_traffic;
1449 u8 *rx_traffic;
1450 struct dentry *debugfs_dir;
1451 u32 dbgfs_sram_offset, dbgfs_sram_len;
1452 bool disable_ht40;
e7392364 1453#endif /* CONFIG_IWLEGACY_DEBUGFS */
e94a4099
SG		 1454
1455 struct work_struct txpower_work;
1456 u32 disable_sens_cal;
1457 u32 disable_chain_noise_cal;
1458 u32 disable_tx_power_cal;
1459 struct work_struct run_time_calib_work;
1460 struct timer_list stats_periodic;
1461 struct timer_list watchdog;
1462 bool hw_ready;
1463
1464 struct led_classdev led;
1465 unsigned long blink_on, blink_off;
1466 bool led_registered;
e7392364 1467}; /*il_priv */
e94a4099 1468
e7392364
SG		 1469static inline void
1470il_txq_ctx_activate(struct il_priv *il, int txq_id)
e94a4099
SG		 1471{
1472 set_bit(txq_id, &il->txq_ctx_active_msk);
1473}
1474
e7392364
SG		 1475static inline void
1476il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
e94a4099
SG		 1477{
1478 clear_bit(txq_id, &il->txq_ctx_active_msk);
1479}
1480
e7392364
SG		 1481static inline int
1482il_is_associated(struct il_priv *il)
e94a4099 1483{
c8b03958 1484 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
e94a4099
SG		 1485}
1486
e7392364
SG		 1487static inline int
1488il_is_any_associated(struct il_priv *il)
e94a4099
SG		 1489{
1490 return il_is_associated(il);
1491}
1492
e7392364
SG		 1493static inline int
1494il_is_channel_valid(const struct il_channel_info *ch_info)
e94a4099
SG		 1495{
1496 if (ch_info == NULL)
1497 return 0;
1498 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1499}
1500
e7392364
SG		 1501static inline int
1502il_is_channel_radar(const struct il_channel_info *ch_info)
e94a4099
SG		 1503{
1504 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1505}
1506
e7392364
SG		 1507static inline u8
1508il_is_channel_a_band(const struct il_channel_info *ch_info)
e94a4099
SG		 1509{
1510 return ch_info->band == IEEE80211_BAND_5GHZ;
1511}
1512
1513static inline int
1514il_is_channel_passive(const struct il_channel_info *ch)
1515{
1516 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1517}
1518
1519static inline int
1520il_is_channel_ibss(const struct il_channel_info *ch)
1521{
1522 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1523}
be663ab6 1524
e94a4099
SG		 1525static inline void
1526__il_free_pages(struct il_priv *il, struct page *page)
1527{
1528 __free_pages(page, il->hw_params.rx_page_order);
1529 il->alloc_rxb_page--;
1530}
1531
e7392364
SG		 1532static inline void
1533il_free_pages(struct il_priv *il, unsigned long page)
e94a4099
SG		 1534{
1535 free_pages(page, il->hw_params.rx_page_order);
1536 il->alloc_rxb_page--;
1537}
be663ab6
WYG		 1538
1539#define IWLWIFI_VERSION "in-tree:"
1540#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1541#define DRV_AUTHOR "<ilw@linux.intel.com>"
1542
e2ebc833 1543#define IL_PCI_DEVICE(dev, subdev, cfg) \
be663ab6
WYG		 1544 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1545 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1546 .driver_data = (kernel_ulong_t)&(cfg)
1547
1548#define TIME_UNIT 1024
1549
e2ebc833
SG		 1550#define IL_SKU_G 0x1
1551#define IL_SKU_A 0x2
1552#define IL_SKU_N 0x8
be663ab6 1553
e2ebc833 1554#define IL_CMD(x) case x: return #x
be663ab6 1555
e94a4099 1556/* Size of one Rx buffer in host DRAM */
e7392364 1557#define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
e94a4099
SG		 1558#define IL_RX_BUF_SIZE_4K (4 * 1024)
1559#define IL_RX_BUF_SIZE_8K (8 * 1024)
1560
e2ebc833 1561struct il_hcmd_ops {
83007196
SG		 1562 int (*rxon_assoc) (struct il_priv *il);
1563 int (*commit_rxon) (struct il_priv *il);
1564 void (*set_rxon_chain) (struct il_priv *il);
be663ab6
WYG		 1565};
1566
e2ebc833 1567struct il_hcmd_utils_ops {
e7392364 1568 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1722f8e1
SG		 1569 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1570 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1571 void (*post_scan) (struct il_priv *il);
be663ab6
WYG		 1572};
1573
e2ebc833 1574struct il_apm_ops {
1722f8e1
SG		 1575 int (*init) (struct il_priv *il);
1576 void (*config) (struct il_priv *il);
be663ab6
WYG		 1577};
1578
9b5e2f46 1579#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1580struct il_debugfs_ops {
1722f8e1
SG		 1581 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1582 size_t count, loff_t *ppos);
1583 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1584 size_t count, loff_t *ppos);
1585 ssize_t(*general_stats_read) (struct file *file,
1586 char __user *user_buf, size_t count,
1587 loff_t *ppos);
be663ab6 1588};
9b5e2f46 1589#endif
be663ab6 1590
e2ebc833 1591struct il_lib_ops {
be663ab6 1592 /* Handling TX */
1722f8e1
SG		 1593 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1594 struct il_tx_queue *txq,
e7392364 1595 u16 byte_cnt);
1722f8e1
SG		 1596 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1597 struct il_tx_queue *txq, dma_addr_t addr,
e7392364 1598 u16 len, u8 reset, u8 pad);
1722f8e1
SG		 1599 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1600 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
be663ab6 1601 /* alive notification after init uCode load */
1722f8e1 1602 void (*init_alive_start) (struct il_priv *il);
be663ab6 1603 /* check validity of rtc data address */
e7392364 1604 int (*is_valid_rtc_data_addr) (u32 addr);
be663ab6 1605 /* 1st ucode load */
1722f8e1 1606 int (*load_ucode) (struct il_priv *il);
1ba2f121 1607
1722f8e1
SG		 1608 void (*dump_nic_error_log) (struct il_priv *il);
1609 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1610 int (*set_channel_switch) (struct il_priv *il,
1611 struct ieee80211_channel_switch *ch_switch);
be663ab6 1612 /* power management */
e2ebc833 1613 struct il_apm_ops apm_ops;
be663ab6
WYG		 1614
1615 /* power */
1722f8e1
SG		 1616 int (*send_tx_power) (struct il_priv *il);
1617 void (*update_chain_flags) (struct il_priv *il);
be663ab6 1618
47ef694d 1619 /* eeprom operations */
e2ebc833 1620 struct il_eeprom_ops eeprom_ops;
be663ab6
WYG		 1621};
1622
e2ebc833 1623struct il_led_ops {
1722f8e1 1624 int (*cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
be663ab6
WYG		 1625};
1626
e2ebc833 1627struct il_legacy_ops {
1722f8e1
SG		 1628 void (*post_associate) (struct il_priv *il);
1629 void (*config_ap) (struct il_priv *il);
be663ab6 1630 /* station management */
1722f8e1
SG		 1631 int (*update_bcast_stations) (struct il_priv *il);
1632 int (*manage_ibss_station) (struct il_priv *il,
1633 struct ieee80211_vif *vif, bool add);
be663ab6
WYG		 1634};
1635
e2ebc833
SG		 1636struct il_ops {
1637 const struct il_lib_ops *lib;
1638 const struct il_hcmd_ops *hcmd;
1639 const struct il_hcmd_utils_ops *utils;
1640 const struct il_led_ops *led;
1641 const struct il_nic_ops *nic;
1642 const struct il_legacy_ops *legacy;
be663ab6
WYG		 1643};
1644
e2ebc833 1645struct il_mod_params {
be663ab6
WYG		 1646 int sw_crypto; /* def: 0 = using hardware encryption */
1647 int disable_hw_scan; /* def: 0 = use h/w scan */
1648 int num_of_queues; /* def: HW dependent */
1649 int disable_11n; /* def: 0 = 11n capabilities enabled */
1650 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
e7392364 1651 int antenna; /* def: 0 = both antennas (use diversity) */
be663ab6
WYG		 1652 int restart_fw; /* def: 1 = restart firmware */
1653};
1654
1655/*
1656 * @led_compensation: compensate on the led on/off time per HW according
1657 * to the deviation to achieve the desired led frequency.
47ef694d 1658 * The detail algorithm is described in common.c
be663ab6 1659 * @chain_noise_num_beacons: number of beacons used to compute chain noise
be663ab6
WYG		 1660 * @wd_timeout: TX queues watchdog timeout
1661 * @temperature_kelvin: temperature report by uCode in kelvin
be663ab6
WYG		 1662 * @ucode_tracing: support ucode continuous tracing
1663 * @sensitivity_calib_by_driver: driver has the capability to perform
1664 * sensitivity calibration operation
1665 * @chain_noise_calib_by_driver: driver has the capability to perform
1666 * chain noise calibration operation
1667 */
e2ebc833 1668struct il_base_params {
be663ab6
WYG		 1669};
1670
47ef694d
SG		 1671#define IL_LED_SOLID 11
1672#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1673
1674#define IL_LED_ACTIVITY (0<<1)
1675#define IL_LED_LINK (1<<1)
1676
1677/*
1678 * LED mode
1679 * IL_LED_DEFAULT: use device default
1680 * IL_LED_RF_STATE: turn LED on/off based on RF state
1681 * LED ON = RF ON
1682 * LED OFF = RF OFF
1683 * IL_LED_BLINK: adjust led blink rate based on blink table
1684 */
1685enum il_led_mode {
1686 IL_LED_DEFAULT,
1687 IL_LED_RF_STATE,
1688 IL_LED_BLINK,
1689};
1690
1691void il_leds_init(struct il_priv *il);
1692void il_leds_exit(struct il_priv *il);
1693
be663ab6 1694/**
e2ebc833 1695 * struct il_cfg
be663ab6
WYG		 1696 * @fw_name_pre: Firmware filename prefix. The api version and extension
1697 * (.ucode) will be added to filename before loading from disk. The
1698 * filename is constructed as fw_name_pre<api>.ucode.
1699 * @ucode_api_max: Highest version of uCode API supported by driver.
1700 * @ucode_api_min: Lowest version of uCode API supported by driver.
1701 * @scan_antennas: available antenna for scan operation
1702 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1703 *
1704 * We enable the driver to be backward compatible wrt API version. The
1705 * driver specifies which APIs it supports (with @ucode_api_max being the
1706 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1707 * it has a supported API version. The firmware's API version will be
e2ebc833 1708 * stored in @il_priv, enabling the driver to make runtime changes based
be663ab6
WYG		 1709 * on firmware version used.
1710 *
1711 * For example,
46bc8d4b 1712 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
be663ab6
WYG		 1713 * Driver interacts with Firmware API version >= 2.
1714 * } else {
1715 * Driver interacts with Firmware API version 1.
1716 * }
1717 *
1718 * The ideal usage of this infrastructure is to treat a new ucode API
1719 * release as a new hardware revision. That is, through utilizing the
e2ebc833 1720 * il_hcmd_utils_ops etc. we accommodate different command structures
be663ab6
WYG		 1721 * and flows between hardware versions as well as their API
1722 * versions.
1723 *
1724 */
e2ebc833 1725struct il_cfg {
be663ab6
WYG		 1726 /* params specific to an individual device within a device family */
1727 const char *name;
1728 const char *fw_name_pre;
1729 const unsigned int ucode_api_max;
1730 const unsigned int ucode_api_min;
e7392364
SG		 1731 u8 valid_tx_ant;
1732 u8 valid_rx_ant;
be663ab6 1733 unsigned int sku;
e7392364
SG		 1734 u16 eeprom_ver;
1735 u16 eeprom_calib_ver;
be663ab6 1736 /* module based parameters which can be set from modprobe cmd */
e2ebc833 1737 const struct il_mod_params *mod_params;
be663ab6 1738 /* params not likely to change within a device family */
e2ebc833 1739 struct il_base_params *base_params;
be663ab6
WYG		 1740 /* params likely to change within a device family */
1741 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
e2ebc833 1742 enum il_led_mode led_mode;
89ef1ed2
SG		 1743
1744 int eeprom_size;
1745 int num_of_queues; /* def: HW dependent */
1746 int num_of_ampdu_queues; /* def: HW dependent */
1747 /* for il_apm_init() */
1748 u32 pll_cfg_val;
1749 bool set_l0s;
1750 bool use_bsm;
1751
1752 u16 led_compensation;
1753 int chain_noise_num_beacons;
1754 unsigned int wd_timeout;
1755 bool temperature_kelvin;
1756 const bool ucode_tracing;
1757 const bool sensitivity_calib_by_driver;
1758 const bool chain_noise_calib_by_driver;
93a984a4
SG		 1759
1760 const u32 regulatory_bands[7];
be663ab6
WYG		 1761};
1762
1763/***************************
1764 * L i b *
1765 ***************************/
1766
e7392364
SG		 1767int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1768 u16 queue, const struct ieee80211_tx_queue_params *params);
e2ebc833 1769int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
e7392364 1770
83007196
SG		 1771void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1772int il_check_rxon_cmd(struct il_priv *il);
1773int il_full_rxon_required(struct il_priv *il);
1774int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1775void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
1776 struct ieee80211_vif *vif);
e7392364
SG		 1777u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1778void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
83007196 1779bool il_is_ht40_tx_allowed(struct il_priv *il,
e7392364 1780 struct ieee80211_sta_ht_cap *ht_cap);
83007196 1781void il_connection_init_rx_config(struct il_priv *il);
46bc8d4b 1782void il_set_rate(struct il_priv *il);
e7392364
SG		 1783int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1784 u32 decrypt_res, struct ieee80211_rx_status *stats);
46bc8d4b 1785void il_irq_handle_error(struct il_priv *il);
e7392364 1786int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
e2ebc833 1787void il_mac_remove_interface(struct ieee80211_hw *hw,
e7392364
SG		 1788 struct ieee80211_vif *vif);
1789int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1790 enum nl80211_iftype newtype, bool newp2p);
46bc8d4b
SG		 1791int il_alloc_txq_mem(struct il_priv *il);
1792void il_txq_mem(struct il_priv *il);
be663ab6 1793
d3175167 1794#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b
SG		 1795int il_alloc_traffic_mem(struct il_priv *il);
1796void il_free_traffic_mem(struct il_priv *il);
1797void il_reset_traffic_log(struct il_priv *il);
e7392364
SG		 1798void il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1799 struct ieee80211_hdr *header);
1800void il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1801 struct ieee80211_hdr *header);
e2ebc833
SG		 1802const char *il_get_mgmt_string(int cmd);
1803const char *il_get_ctrl_string(int cmd);
46bc8d4b 1804void il_clear_traffic_stats(struct il_priv *il);
e7392364 1805void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
be663ab6 1806#else
e7392364
SG		 1807static inline int
1808il_alloc_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1809{
1810 return 0;
1811}
e7392364
SG		 1812
1813static inline void
1814il_free_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1815{
1816}
e7392364
SG		 1817
1818static inline void
1819il_reset_traffic_log(struct il_priv *il)
be663ab6
WYG		 1820{
1821}
e7392364
SG		 1822
1823static inline void
1824il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1825 struct ieee80211_hdr *header)
be663ab6
WYG		 1826{
1827}
e7392364
SG		 1828
1829static inline void
1830il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1831 struct ieee80211_hdr *header)
be663ab6
WYG		 1832{
1833}
e7392364
SG		 1834
1835static inline void
1836il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6
WYG		 1837{
1838}
1839#endif
1840/*****************************************************
1841 * RX handlers.
1842 * **************************************************/
e7392364
SG		 1843void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1844void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1845void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1846
1847/*****************************************************
1848* RX
1849******************************************************/
46bc8d4b
SG		 1850void il_cmd_queue_unmap(struct il_priv *il);
1851void il_cmd_queue_free(struct il_priv *il);
1852int il_rx_queue_alloc(struct il_priv *il);
e7392364 1853void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
e2ebc833 1854int il_rx_queue_space(const struct il_rx_queue *q);
e7392364 1855void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6 1856/* Handlers */
e7392364
SG		 1857void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1858void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
46bc8d4b 1859void il_chswitch_done(struct il_priv *il, bool is_success);
d2dfb33e 1860void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1861
1862/* TX helpers */
1863
1864/*****************************************************
1865* TX
1866******************************************************/
e7392364
SG		 1867void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1868int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
1869 u32 txq_id);
1870void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
1871 int slots_num, u32 txq_id);
46bc8d4b
SG		 1872void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1873void il_tx_queue_free(struct il_priv *il, int txq_id);
1874void il_setup_watchdog(struct il_priv *il);
be663ab6
WYG		 1875/*****************************************************
1876 * TX power
1877 ****************************************************/
46bc8d4b 1878int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
be663ab6
WYG		 1879
1880/*******************************************************************************
1881 * Rate
1882 ******************************************************************************/
1883
83007196 1884u8 il_get_lowest_plcp(struct il_priv *il);
be663ab6
WYG		 1885
1886/*******************************************************************************
1887 * Scanning
1888 ******************************************************************************/
46bc8d4b
SG		 1889void il_init_scan_params(struct il_priv *il);
1890int il_scan_cancel(struct il_priv *il);
1891int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1892void il_force_scan_end(struct il_priv *il);
e7392364
SG		 1893int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1894 struct cfg80211_scan_request *req);
46bc8d4b
SG		 1895void il_internal_short_hw_scan(struct il_priv *il);
1896int il_force_reset(struct il_priv *il, bool external);
e7392364 1897u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1898 const u8 *ta, const u8 *ie, int ie_len, int left);
46bc8d4b 1899void il_setup_rx_scan_handlers(struct il_priv *il);
e7392364
SG		 1900u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1901 u8 n_probes);
1902u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1903 struct ieee80211_vif *vif);
46bc8d4b
SG		 1904void il_setup_scan_deferred_work(struct il_priv *il);
1905void il_cancel_scan_deferred_work(struct il_priv *il);
be663ab6
WYG		 1906
1907/* For faster active scanning, scan will move to the next channel if fewer than
1908 * PLCP_QUIET_THRESH packets are heard on this channel within
1909 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
1910 * time if it's a quiet channel (nothing responded to our probe, and there's
1911 * no other traffic).
1912 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
e7392364
SG		 1913#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
1914#define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
be663ab6 1915
e2ebc833 1916#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
be663ab6
WYG		 1917
1918/*****************************************************
1919 * S e n d i n g H o s t C o m m a n d s *
1920 *****************************************************/
1921
e2ebc833 1922const char *il_get_cmd_string(u8 cmd);
e7392364 1923int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
46bc8d4b 1924int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
e7392364
SG		 1925int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1926 const void *data);
1927int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 1928 void (*callback) (struct il_priv *il,
1929 struct il_device_cmd *cmd,
1930 struct il_rx_pkt *pkt));
be663ab6 1931
46bc8d4b 1932int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
be663ab6 1933
be663ab6
WYG		 1934/*****************************************************
1935 * PCI *
1936 *****************************************************/
1937
e7392364
SG		 1938static inline u16
1939il_pcie_link_ctl(struct il_priv *il)
be663ab6
WYG		 1940{
1941 int pos;
1942 u16 pci_lnk_ctl;
46bc8d4b
SG		 1943 pos = pci_pcie_cap(il->pci_dev);
1944 pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
be663ab6
WYG		 1945 return pci_lnk_ctl;
1946}
1947
e2ebc833 1948void il_bg_watchdog(unsigned long data);
e7392364
SG		 1949u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1950__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1951 u32 beacon_interval);
be663ab6
WYG		 1952
1953#ifdef CONFIG_PM
e2ebc833
SG		 1954int il_pci_suspend(struct device *device);
1955int il_pci_resume(struct device *device);
1956extern const struct dev_pm_ops il_pm_ops;
be663ab6 1957
e2ebc833 1958#define IL_LEGACY_PM_OPS (&il_pm_ops)
be663ab6
WYG		 1959
1960#else /* !CONFIG_PM */
1961
e2ebc833 1962#define IL_LEGACY_PM_OPS NULL
be663ab6
WYG		 1963
1964#endif /* !CONFIG_PM */
1965
1966/*****************************************************
1967* Error Handling Debugging
1968******************************************************/
46bc8d4b 1969void il4965_dump_nic_error_log(struct il_priv *il);
d3175167 1970#ifdef CONFIG_IWLEGACY_DEBUG
83007196 1971void il_print_rx_config_cmd(struct il_priv *il);
be663ab6 1972#else
e7392364 1973static inline void
83007196 1974il_print_rx_config_cmd(struct il_priv *il)
be663ab6
WYG		 1975{
1976}
1977#endif
1978
46bc8d4b 1979void il_clear_isr_stats(struct il_priv *il);
be663ab6
WYG		 1980
1981/*****************************************************
1982* GEOS
1983******************************************************/
46bc8d4b
SG		 1984int il_init_geos(struct il_priv *il);
1985void il_free_geos(struct il_priv *il);
be663ab6
WYG		 1986
1987/*************** DRIVER STATUS FUNCTIONS *****/
1988
a6766ccd
SG		 1989#define S_HCMD_ACTIVE 0 /* host command in progress */
1990/* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
1991#define S_INT_ENABLED 2
1992#define S_RF_KILL_HW 3
1993#define S_CT_KILL 4
1994#define S_INIT 5
1995#define S_ALIVE 6
1996#define S_READY 7
1997#define S_TEMPERATURE 8
1998#define S_GEO_CONFIGURED 9
1999#define S_EXIT_PENDING 10
db7746f7 2000#define S_STATS 12
a6766ccd
SG		 2001#define S_SCANNING 13
2002#define S_SCAN_ABORTING 14
2003#define S_SCAN_HW 15
2004#define S_POWER_PMI 16
2005#define S_FW_ERROR 17
2006#define S_CHANNEL_SWITCH_PENDING 18
be663ab6 2007
e7392364
SG		 2008static inline int
2009il_is_ready(struct il_priv *il)
be663ab6
WYG		 2010{
2011 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
2012 * set but EXIT_PENDING is not */
a6766ccd 2013 return test_bit(S_READY, &il->status) &&
e7392364
SG		 2014 test_bit(S_GEO_CONFIGURED, &il->status) &&
2015 !test_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 2016}
2017
e7392364
SG		 2018static inline int
2019il_is_alive(struct il_priv *il)
be663ab6 2020{
a6766ccd 2021 return test_bit(S_ALIVE, &il->status);
be663ab6
WYG		 2022}
2023
e7392364
SG		 2024static inline int
2025il_is_init(struct il_priv *il)
be663ab6 2026{
a6766ccd 2027 return test_bit(S_INIT, &il->status);
be663ab6
WYG		 2028}
2029
e7392364
SG		 2030static inline int
2031il_is_rfkill_hw(struct il_priv *il)
be663ab6 2032{
a6766ccd 2033 return test_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 2034}
2035
e7392364
SG		 2036static inline int
2037il_is_rfkill(struct il_priv *il)
be663ab6 2038{
46bc8d4b 2039 return il_is_rfkill_hw(il);
be663ab6
WYG		 2040}
2041
e7392364
SG		 2042static inline int
2043il_is_ctkill(struct il_priv *il)
be663ab6 2044{
a6766ccd 2045 return test_bit(S_CT_KILL, &il->status);
be663ab6
WYG		 2046}
2047
e7392364
SG		 2048static inline int
2049il_is_ready_rf(struct il_priv *il)
be663ab6
WYG		 2050{
2051
46bc8d4b 2052 if (il_is_rfkill(il))
be663ab6
WYG		 2053 return 0;
2054
46bc8d4b 2055 return il_is_ready(il);
be663ab6
WYG		 2056}
2057
46bc8d4b 2058extern void il_send_bt_config(struct il_priv *il);
e7392364 2059extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
46bc8d4b
SG		 2060void il_apm_stop(struct il_priv *il);
2061int il_apm_init(struct il_priv *il);
be663ab6 2062
83007196
SG		 2063int il_send_rxon_timing(struct il_priv *il);
2064
e7392364 2065static inline int
83007196 2066il_send_rxon_assoc(struct il_priv *il)
be663ab6 2067{
c39ae9fd 2068 return il->ops->hcmd->rxon_assoc(il);
be663ab6 2069}
e7392364
SG		 2070
2071static inline int
83007196 2072il_commit_rxon(struct il_priv *il)
be663ab6 2073{
c39ae9fd 2074 return il->ops->hcmd->commit_rxon(il);
be663ab6 2075}
e7392364
SG		 2076
2077static inline const struct ieee80211_supported_band *
2078il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
be663ab6 2079{
46bc8d4b 2080 return il->hw->wiphy->bands[band];
be663ab6
WYG		 2081}
2082
be663ab6 2083/* mac80211 handlers */
e2ebc833 2084int il_mac_config(struct ieee80211_hw *hw, u32 changed);
e7392364
SG		 2085void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
2086void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2087 struct ieee80211_bss_conf *bss_conf, u32 changes);
2088void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 2089 __le16 fc, __le32 *tx_flags);
be663ab6 2090
e2ebc833 2091irqreturn_t il_isr(int irq, void *data);
be663ab6 2092
17d4eca6
SG		 2093extern void il_set_bit(struct il_priv *p, u32 r, u32 m);
2094extern void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1e0f32a4 2095extern bool _il_grab_nic_access(struct il_priv *il);
17d4eca6
SG		 2096extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
2097extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
2098extern u32 il_rd_prph(struct il_priv *il, u32 reg);
2099extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
2100extern u32 il_read_targ_mem(struct il_priv *il, u32 addr);
2101extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
e94a4099 2102
e7392364
SG		 2103static inline void
2104_il_write8(struct il_priv *il, u32 ofs, u8 val)
e94a4099 2105{
a5f16137 2106 writeb(val, il->hw_base + ofs);
e94a4099
SG		 2107}
2108#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2109
e7392364
SG		 2110static inline void
2111_il_wr(struct il_priv *il, u32 ofs, u32 val)
e94a4099 2112{
a5f16137 2113 writel(val, il->hw_base + ofs);
e94a4099
SG		 2114}
2115
e7392364
SG		 2116static inline u32
2117_il_rd(struct il_priv *il, u32 ofs)
e94a4099 2118{
a5f16137 2119 return readl(il->hw_base + ofs);
e94a4099
SG		 2120}
2121
e94a4099
SG		 2122static inline void
2123_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2124{
2125 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2126}
2127
e7392364 2128static inline void
17d4eca6 2129_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
e94a4099 2130{
17d4eca6 2131 _il_wr(il, reg, _il_rd(il, reg) | mask);
e94a4099
SG		 2132}
2133
e7392364
SG		 2134static inline void
2135_il_release_nic_access(struct il_priv *il)
e94a4099 2136{
e7392364 2137 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4e5ea208
SG		 2138 /*
2139 * In above we are reading CSR_GP_CNTRL register, what will flush any
2140 * previous writes, but still want write, which clear MAC_ACCESS_REQ
2141 * bit, be performed on PCI bus before any other writes scheduled on
2142 * different CPUs (after we drop reg_lock).
2143 */
2144 mmiowb();
e94a4099
SG		 2145}
2146
e7392364
SG		 2147static inline u32
2148il_rd(struct il_priv *il, u32 reg)
e94a4099
SG		 2149{
2150 u32 value;
2151 unsigned long reg_flags;
2152
2153 spin_lock_irqsave(&il->reg_lock, reg_flags);
2154 _il_grab_nic_access(il);
2155 value = _il_rd(il, reg);
2156 _il_release_nic_access(il);
2157 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2158 return value;
e94a4099
SG		 2159}
2160
2161static inline void
2162il_wr(struct il_priv *il, u32 reg, u32 value)
2163{
2164 unsigned long reg_flags;
2165
2166 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 2167 if (likely(_il_grab_nic_access(il))) {
e94a4099
SG		 2168 _il_wr(il, reg, value);
2169 _il_release_nic_access(il);
2170 }
2171 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2172}
2173
e7392364
SG		 2174static inline u32
2175_il_rd_prph(struct il_priv *il, u32 reg)
e94a4099
SG		 2176{
2177 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
e94a4099
SG		 2178 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2179}
2180
e7392364
SG		 2181static inline void
2182_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
e94a4099 2183{
e7392364 2184 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
e94a4099
SG		 2185 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2186}
2187
e94a4099
SG		 2188static inline void
2189il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2190{
2191 unsigned long reg_flags;
2192
2193 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4
SG		 2194 if (likely(_il_grab_nic_access(il))) {
2195 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2196 _il_release_nic_access(il);
2197 }
e94a4099
SG		 2198 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2199}
2200
e7392364
SG		 2201static inline void
2202il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
e94a4099
SG		 2203{
2204 unsigned long reg_flags;
2205
2206 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4
SG		 2207 if (likely(_il_grab_nic_access(il))) {
2208 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2209 _il_release_nic_access(il);
2210 }
e94a4099
SG		 2211 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2212}
2213
e7392364
SG		 2214static inline void
2215il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
e94a4099
SG		 2216{
2217 unsigned long reg_flags;
2218 u32 val;
2219
2220 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4
SG		 2221 if (likely(_il_grab_nic_access(il))) {
2222 val = _il_rd_prph(il, reg);
2223 _il_wr_prph(il, reg, (val & ~mask));
2224 _il_release_nic_access(il);
2225 }
e94a4099
SG		 2226 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2227}
2228
e94a4099
SG		 2229#define HW_KEY_DYNAMIC 0
2230#define HW_KEY_DEFAULT 1
2231
e7392364
SG		 2232#define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2233#define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2234#define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2235 being activated */
2236#define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2237 (this is for the IBSS BSSID stations) */
2238#define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
e94a4099 2239
83007196
SG		 2240void il_restore_stations(struct il_priv *il);
2241void il_clear_ucode_stations(struct il_priv *il);
e94a4099
SG		 2242void il_dealloc_bcast_stations(struct il_priv *il);
2243int il_get_free_ucode_key_idx(struct il_priv *il);
e7392364 2244int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
83007196 2245int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
1722f8e1 2246 struct ieee80211_sta *sta, u8 *sta_id_r);
e7392364
SG		 2247int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2248int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2249 struct ieee80211_sta *sta);
2250
83007196
SG		 2251u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2252 struct ieee80211_sta *sta);
e7392364 2253
83007196
SG		 2254int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2255 u8 flags, bool init);
e94a4099
SG		 2256
2257/**
2258 * il_clear_driver_stations - clear knowledge of all stations from driver
2259 * @il: iwl il struct
2260 *
2261 * This is called during il_down() to make sure that in the case
2262 * we're coming there from a hardware restart mac80211 will be
2263 * able to reconfigure stations -- if we're getting there in the
2264 * normal down flow then the stations will already be cleared.
2265 */
e7392364
SG		 2266static inline void
2267il_clear_driver_stations(struct il_priv *il)
e94a4099
SG		 2268{
2269 unsigned long flags;
e94a4099
SG		 2270
2271 spin_lock_irqsave(&il->sta_lock, flags);
2272 memset(il->stations, 0, sizeof(il->stations));
2273 il->num_stations = 0;
e94a4099 2274 il->ucode_key_table = 0;
e94a4099
SG		 2275 spin_unlock_irqrestore(&il->sta_lock, flags);
2276}
2277
e7392364
SG		 2278static inline int
2279il_sta_id(struct ieee80211_sta *sta)
e94a4099
SG		 2280{
2281 if (WARN_ON(!sta))
2282 return IL_INVALID_STATION;
2283
2284 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2285}
2286
2287/**
2288 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2289 * @il: iwl il
2290 * @context: the current context
2291 * @sta: mac80211 station
2292 *
2293 * In certain circumstances mac80211 passes a station pointer
2294 * that may be %NULL, for example during TX or key setup. In
2295 * that case, we need to use the broadcast station, so this
2296 * inline wraps that pattern.
2297 */
e7392364 2298static inline int
83007196 2299il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
e94a4099
SG		 2300{
2301 int sta_id;
2302
2303 if (!sta)
b16db50a 2304 return il->hw_params.bcast_id;
e94a4099
SG		 2305
2306 sta_id = il_sta_id(sta);
2307
2308 /*
2309 * mac80211 should not be passing a partially
2310 * initialised station!
2311 */
2312 WARN_ON(sta_id == IL_INVALID_STATION);
2313
2314 return sta_id;
2315}
2316
2317/**
2318 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2319 * @idx -- current idx
2320 * @n_bd -- total number of entries in queue (must be power of 2)
2321 */
e7392364
SG		 2322static inline int
2323il_queue_inc_wrap(int idx, int n_bd)
e94a4099
SG		 2324{
2325 return ++idx & (n_bd - 1);
2326}
2327
2328/**
2329 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2330 * @idx -- current idx
2331 * @n_bd -- total number of entries in queue (must be power of 2)
2332 */
e7392364
SG		 2333static inline int
2334il_queue_dec_wrap(int idx, int n_bd)
e94a4099
SG		 2335{
2336 return --idx & (n_bd - 1);
2337}
2338
2339/* TODO: Move fw_desc functions to iwl-pci.ko */
e7392364
SG		 2340static inline void
2341il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2342{
2343 if (desc->v_addr)
e7392364
SG		 2344 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2345 desc->p_addr);
e94a4099
SG		 2346 desc->v_addr = NULL;
2347 desc->len = 0;
2348}
2349
e7392364
SG		 2350static inline int
2351il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2352{
2353 if (!desc->len) {
2354 desc->v_addr = NULL;
2355 return -EINVAL;
2356 }
2357
e7392364
SG		 2358 desc->v_addr =
2359 dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2360 GFP_KERNEL);
e94a4099
SG		 2361 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2362}
2363
2364/*
2365 * we have 8 bits used like this:
2366 *
2367 * 7 6 5 4 3 2 1 0
2368 * | | | | | | | |
2369 * | | | | | | +-+-------- AC queue (0-3)
2370 * | | | | | |
2371 * | +-+-+-+-+------------ HW queue ID
2372 * |
2373 * +---------------------- unused
2374 */
2375static inline void
2376il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2377{
e7392364
SG		 2378 BUG_ON(ac > 3); /* only have 2 bits */
2379 BUG_ON(hwq > 31); /* only use 5 bits */
e94a4099
SG		 2380
2381 txq->swq_id = (hwq << 2) | ac;
2382}
2383
e7392364
SG		 2384static inline void
2385il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2386{
2387 u8 queue = txq->swq_id;
2388 u8 ac = queue & 3;
2389 u8 hwq = (queue >> 2) & 0x1f;
2390
2391 if (test_and_clear_bit(hwq, il->queue_stopped))
2392 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2393 ieee80211_wake_queue(il->hw, ac);
2394}
2395
e7392364
SG		 2396static inline void
2397il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2398{
2399 u8 queue = txq->swq_id;
2400 u8 ac = queue & 3;
2401 u8 hwq = (queue >> 2) & 0x1f;
2402
2403 if (!test_and_set_bit(hwq, il->queue_stopped))
2404 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2405 ieee80211_stop_queue(il->hw, ac);
2406}
2407
2408#ifdef ieee80211_stop_queue
2409#undef ieee80211_stop_queue
2410#endif
2411
2412#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2413
2414#ifdef ieee80211_wake_queue
2415#undef ieee80211_wake_queue
2416#endif
2417
2418#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2419
e7392364
SG		 2420static inline void
2421il_disable_interrupts(struct il_priv *il)
e94a4099
SG		 2422{
2423 clear_bit(S_INT_ENABLED, &il->status);
2424
2425 /* disable interrupts from uCode/NIC to host */
2426 _il_wr(il, CSR_INT_MASK, 0x00000000);
2427
2428 /* acknowledge/clear/reset any interrupts still pending
2429 * from uCode or flow handler (Rx/Tx DMA) */
2430 _il_wr(il, CSR_INT, 0xffffffff);
2431 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
e94a4099
SG		 2432}
2433
e7392364
SG		 2434static inline void
2435il_enable_rfkill_int(struct il_priv *il)
e94a4099 2436{
e94a4099
SG		 2437 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2438}
2439
e7392364
SG		 2440static inline void
2441il_enable_interrupts(struct il_priv *il)
e94a4099 2442{
e94a4099
SG		 2443 set_bit(S_INT_ENABLED, &il->status);
2444 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2445}
2446
2447/**
2448 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2449 * @il -- pointer to il_priv data structure
2450 * @tsf_bits -- number of bits need to shift for masking)
2451 */
e7392364
SG		 2452static inline u32
2453il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2454{
2455 return (1 << tsf_bits) - 1;
2456}
2457
2458/**
2459 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2460 * @il -- pointer to il_priv data structure
2461 * @tsf_bits -- number of bits need to shift for masking)
2462 */
e7392364
SG		 2463static inline u32
2464il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2465{
2466 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2467}
2468
2469/**
2470 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2471 *
2472 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2473 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2474 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2475 * in which the last frame was written to
2476 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2477 * which was transferred
2478 */
2479struct il_rb_status {
2480 __le16 closed_rb_num;
2481 __le16 closed_fr_num;
2482 __le16 finished_rb_num;
2483 __le16 finished_fr_nam;
e7392364 2484 __le32 __unused; /* 3945 only */
e94a4099
SG		 2485} __packed;
2486
e94a4099
SG		 2487#define TFD_QUEUE_SIZE_MAX (256)
2488#define TFD_QUEUE_SIZE_BC_DUP (64)
2489#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2490#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2491#define IL_NUM_OF_TBS 20
2492
e7392364
SG		 2493static inline u8
2494il_get_dma_hi_addr(dma_addr_t addr)
e94a4099
SG		 2495{
2496 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2497}
e7392364 2498
e94a4099
SG		 2499/**
2500 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2501 *
2502 * This structure contains dma address and length of transmission address
2503 *
1722f8e1
SG		 2504 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2505 * unaligned on 16 bit boundary
2506 * @hi_n_len: 0-3 [35:32] portion of dma
2507 * 4-15 length of the tx buffer
e94a4099
SG		 2508 */
2509struct il_tfd_tb {
2510 __le32 lo;
2511 __le16 hi_n_len;
2512} __packed;
2513
2514/**
2515 * struct il_tfd
2516 *
2517 * Transmit Frame Descriptor (TFD)
2518 *
2519 * @ __reserved1[3] reserved
2520 * @ num_tbs 0-4 number of active tbs
2521 * 5 reserved
2522 * 6-7 padding (not used)
2523 * @ tbs[20] transmit frame buffer descriptors
1722f8e1 2524 * @ __pad padding
e94a4099
SG		 2525 *
2526 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2527 * Both driver and device share these circular buffers, each of which must be
2528 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2529 *
2530 * Driver must indicate the physical address of the base of each
9a95b370 2531 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
e94a4099
SG		 2532 *
2533 * Each TFD contains pointer/size information for up to 20 data buffers
2534 * in host DRAM. These buffers collectively contain the (one) frame described
2535 * by the TFD. Each buffer must be a single contiguous block of memory within
2536 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2537 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2538 * Tx frame, up to 8 KBytes in size.
2539 *
2540 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2541 */
2542struct il_tfd {
2543 u8 __reserved1[3];
2544 u8 num_tbs;
2545 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2546 __le32 __pad;
2547} __packed;
2548/* PCI registers */
2549#define PCI_CFG_RETRY_TIMEOUT 0x041
2550
2551/* PCI register values */
2552#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2553#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2554
3fbbf9a8 2555struct il_rate_info {
e7392364
SG		 2556 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2557 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2558 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2559 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2560 u8 prev_ieee; /* previous rate in IEEE speeds */
2561 u8 next_ieee; /* next rate in IEEE speeds */
2562 u8 prev_rs; /* previous rate used in rs algo */
2563 u8 next_rs; /* next rate used in rs algo */
2564 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2565 u8 next_rs_tgg; /* next rate used in TGG rs algo */
3fbbf9a8
SG		 2566};
2567
2568struct il3945_rate_info {
2569 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2570 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2571 u8 prev_ieee; /* previous rate in IEEE speeds */
2572 u8 next_ieee; /* next rate in IEEE speeds */
2573 u8 prev_rs; /* previous rate used in rs algo */
2574 u8 next_rs; /* next rate used in rs algo */
2575 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2576 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2577 u8 table_rs_idx; /* idx in rate scale table cmd */
2578 u8 prev_table_rs; /* prev in rate table cmd */
2579};
2580
3fbbf9a8
SG		 2581/*
2582 * These serve as idxes into
2583 * struct il_rate_info il_rates[RATE_COUNT];
2584 */
2585enum {
2586 RATE_1M_IDX = 0,
2587 RATE_2M_IDX,
2588 RATE_5M_IDX,
2589 RATE_11M_IDX,
2590 RATE_6M_IDX,
2591 RATE_9M_IDX,
2592 RATE_12M_IDX,
2593 RATE_18M_IDX,
2594 RATE_24M_IDX,
2595 RATE_36M_IDX,
2596 RATE_48M_IDX,
2597 RATE_54M_IDX,
2598 RATE_60M_IDX,
2599 RATE_COUNT,
2600 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2601 RATE_COUNT_3945 = RATE_COUNT - 1,
2602 RATE_INVM_IDX = RATE_COUNT,
2603 RATE_INVALID = RATE_COUNT,
2604};
2605
2606enum {
2607 RATE_6M_IDX_TBL = 0,
2608 RATE_9M_IDX_TBL,
2609 RATE_12M_IDX_TBL,
2610 RATE_18M_IDX_TBL,
2611 RATE_24M_IDX_TBL,
2612 RATE_36M_IDX_TBL,
2613 RATE_48M_IDX_TBL,
2614 RATE_54M_IDX_TBL,
2615 RATE_1M_IDX_TBL,
2616 RATE_2M_IDX_TBL,
2617 RATE_5M_IDX_TBL,
2618 RATE_11M_IDX_TBL,
2619 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2620};
2621
2622enum {
2623 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2624 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2625 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2626 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2627 IL_LAST_CCK_RATE = RATE_11M_IDX,
2628};
2629
2630/* #define vs. enum to keep from defaulting to 'large integer' */
2631#define RATE_6M_MASK (1 << RATE_6M_IDX)
2632#define RATE_9M_MASK (1 << RATE_9M_IDX)
2633#define RATE_12M_MASK (1 << RATE_12M_IDX)
2634#define RATE_18M_MASK (1 << RATE_18M_IDX)
2635#define RATE_24M_MASK (1 << RATE_24M_IDX)
2636#define RATE_36M_MASK (1 << RATE_36M_IDX)
2637#define RATE_48M_MASK (1 << RATE_48M_IDX)
2638#define RATE_54M_MASK (1 << RATE_54M_IDX)
2639#define RATE_60M_MASK (1 << RATE_60M_IDX)
2640#define RATE_1M_MASK (1 << RATE_1M_IDX)
2641#define RATE_2M_MASK (1 << RATE_2M_IDX)
2642#define RATE_5M_MASK (1 << RATE_5M_IDX)
2643#define RATE_11M_MASK (1 << RATE_11M_IDX)
2644
2645/* uCode API values for legacy bit rates, both OFDM and CCK */
2646enum {
e7392364
SG		 2647 RATE_6M_PLCP = 13,
2648 RATE_9M_PLCP = 15,
3fbbf9a8
SG		 2649 RATE_12M_PLCP = 5,
2650 RATE_18M_PLCP = 7,
2651 RATE_24M_PLCP = 9,
2652 RATE_36M_PLCP = 11,
2653 RATE_48M_PLCP = 1,
2654 RATE_54M_PLCP = 3,
e7392364
SG		 2655 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */
2656 RATE_1M_PLCP = 10,
2657 RATE_2M_PLCP = 20,
2658 RATE_5M_PLCP = 55,
3fbbf9a8 2659 RATE_11M_PLCP = 110,
e7392364 2660 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
3fbbf9a8
SG		 2661};
2662
2663/* uCode API values for OFDM high-throughput (HT) bit rates */
2664enum {
2665 RATE_SISO_6M_PLCP = 0,
2666 RATE_SISO_12M_PLCP = 1,
2667 RATE_SISO_18M_PLCP = 2,
2668 RATE_SISO_24M_PLCP = 3,
2669 RATE_SISO_36M_PLCP = 4,
2670 RATE_SISO_48M_PLCP = 5,
2671 RATE_SISO_54M_PLCP = 6,
2672 RATE_SISO_60M_PLCP = 7,
e7392364 2673 RATE_MIMO2_6M_PLCP = 0x8,
3fbbf9a8
SG		 2674 RATE_MIMO2_12M_PLCP = 0x9,
2675 RATE_MIMO2_18M_PLCP = 0xa,
2676 RATE_MIMO2_24M_PLCP = 0xb,
2677 RATE_MIMO2_36M_PLCP = 0xc,
2678 RATE_MIMO2_48M_PLCP = 0xd,
2679 RATE_MIMO2_54M_PLCP = 0xe,
2680 RATE_MIMO2_60M_PLCP = 0xf,
2681 RATE_SISO_INVM_PLCP,
2682 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2683};
2684
2685/* MAC header values for bit rates */
2686enum {
e7392364
SG		 2687 RATE_6M_IEEE = 12,
2688 RATE_9M_IEEE = 18,
3fbbf9a8
SG		 2689 RATE_12M_IEEE = 24,
2690 RATE_18M_IEEE = 36,
2691 RATE_24M_IEEE = 48,
2692 RATE_36M_IEEE = 72,
2693 RATE_48M_IEEE = 96,
2694 RATE_54M_IEEE = 108,
2695 RATE_60M_IEEE = 120,
e7392364
SG		 2696 RATE_1M_IEEE = 2,
2697 RATE_2M_IEEE = 4,
2698 RATE_5M_IEEE = 11,
3fbbf9a8
SG		 2699 RATE_11M_IEEE = 22,
2700};
2701
2702#define IL_CCK_BASIC_RATES_MASK \
2703 (RATE_1M_MASK | \
2704 RATE_2M_MASK)
2705
2706#define IL_CCK_RATES_MASK \
2707 (IL_CCK_BASIC_RATES_MASK | \
2708 RATE_5M_MASK | \
2709 RATE_11M_MASK)
2710
2711#define IL_OFDM_BASIC_RATES_MASK \
2712 (RATE_6M_MASK | \
2713 RATE_12M_MASK | \
2714 RATE_24M_MASK)
2715
2716#define IL_OFDM_RATES_MASK \
2717 (IL_OFDM_BASIC_RATES_MASK | \
2718 RATE_9M_MASK | \
2719 RATE_18M_MASK | \
2720 RATE_36M_MASK | \
2721 RATE_48M_MASK | \
2722 RATE_54M_MASK)
2723
2724#define IL_BASIC_RATES_MASK \
2725 (IL_OFDM_BASIC_RATES_MASK | \
2726 IL_CCK_BASIC_RATES_MASK)
2727
2728#define RATES_MASK ((1 << RATE_COUNT) - 1)
2729#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2730
2731#define IL_INVALID_VALUE -1
2732
2733#define IL_MIN_RSSI_VAL -100
2734#define IL_MAX_RSSI_VAL 0
2735
2736/* These values specify how many Tx frame attempts before
2737 * searching for a new modulation mode */
2738#define IL_LEGACY_FAILURE_LIMIT 160
2739#define IL_LEGACY_SUCCESS_LIMIT 480
2740#define IL_LEGACY_TBL_COUNT 160
2741
2742#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2743#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2744#define IL_NONE_LEGACY_TBL_COUNT 1500
2745
2746/* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2747#define IL_RS_GOOD_RATIO 12800 /* 100% */
2748#define RATE_SCALE_SWITCH 10880 /* 85% */
2749#define RATE_HIGH_TH 10880 /* 85% */
2750#define RATE_INCREASE_TH 6400 /* 50% */
2751#define RATE_DECREASE_TH 1920 /* 15% */
2752
2753/* possible actions when in legacy mode */
2754#define IL_LEGACY_SWITCH_ANTENNA1 0
2755#define IL_LEGACY_SWITCH_ANTENNA2 1
2756#define IL_LEGACY_SWITCH_SISO 2
2757#define IL_LEGACY_SWITCH_MIMO2_AB 3
2758#define IL_LEGACY_SWITCH_MIMO2_AC 4
2759#define IL_LEGACY_SWITCH_MIMO2_BC 5
2760
2761/* possible actions when in siso mode */
2762#define IL_SISO_SWITCH_ANTENNA1 0
2763#define IL_SISO_SWITCH_ANTENNA2 1
2764#define IL_SISO_SWITCH_MIMO2_AB 2
2765#define IL_SISO_SWITCH_MIMO2_AC 3
2766#define IL_SISO_SWITCH_MIMO2_BC 4
2767#define IL_SISO_SWITCH_GI 5
2768
2769/* possible actions when in mimo mode */
2770#define IL_MIMO2_SWITCH_ANTENNA1 0
2771#define IL_MIMO2_SWITCH_ANTENNA2 1
2772#define IL_MIMO2_SWITCH_SISO_A 2
2773#define IL_MIMO2_SWITCH_SISO_B 3
2774#define IL_MIMO2_SWITCH_SISO_C 4
2775#define IL_MIMO2_SWITCH_GI 5
2776
2777#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2778
2779#define IL_ACTION_LIMIT 3 /* # possible actions */
2780
2781#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
2782
2783/* load per tid defines for A-MPDU activation */
2784#define IL_AGG_TPT_THREHOLD 0
2785#define IL_AGG_LOAD_THRESHOLD 10
2786#define IL_AGG_ALL_TID 0xff
2787#define TID_QUEUE_CELL_SPACING 50 /*mS */
2788#define TID_QUEUE_MAX_SIZE 20
2789#define TID_ROUND_VALUE 5 /* mS */
2790#define TID_MAX_LOAD_COUNT 8
2791
2792#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2793#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2794
2795extern const struct il_rate_info il_rates[RATE_COUNT];
2796
2797enum il_table_type {
2798 LQ_NONE,
e7392364 2799 LQ_G, /* legacy types */
3fbbf9a8 2800 LQ_A,
e7392364 2801 LQ_SISO, /* high-throughput types */
3fbbf9a8
SG		 2802 LQ_MIMO2,
2803 LQ_MAX,
2804};
2805
2806#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2807#define is_siso(tbl) ((tbl) == LQ_SISO)
2808#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2809#define is_mimo(tbl) (is_mimo2(tbl))
2810#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2811#define is_a_band(tbl) ((tbl) == LQ_A)
2812#define is_g_and(tbl) ((tbl) == LQ_G)
2813
2814#define ANT_NONE 0x0
2815#define ANT_A BIT(0)
2816#define ANT_B BIT(1)
2817#define ANT_AB (ANT_A | ANT_B)
2818#define ANT_C BIT(2)
2819#define ANT_AC (ANT_A | ANT_C)
2820#define ANT_BC (ANT_B | ANT_C)
2821#define ANT_ABC (ANT_AB | ANT_C)
2822
2823#define IL_MAX_MCS_DISPLAY_SIZE 12
2824
2825struct il_rate_mcs_info {
e7392364
SG		 2826 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2827 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
3fbbf9a8
SG		 2828};
2829
2830/**
2831 * struct il_rate_scale_data -- tx success history for one rate
2832 */
2833struct il_rate_scale_data {
2834 u64 data; /* bitmap of successful frames */
2835 s32 success_counter; /* number of frames successful */
2836 s32 success_ratio; /* per-cent * 128 */
2837 s32 counter; /* number of frames attempted */
2838 s32 average_tpt; /* success ratio * expected throughput */
2839 unsigned long stamp;
2840};
2841
2842/**
2843 * struct il_scale_tbl_info -- tx params and success history for all rates
2844 *
2845 * There are two of these in struct il_lq_sta,
2846 * one for "active", and one for "search".
2847 */
2848struct il_scale_tbl_info {
2849 enum il_table_type lq_type;
2850 u8 ant_type;
e7392364
SG		 2851 u8 is_SGI; /* 1 = short guard interval */
2852 u8 is_ht40; /* 1 = 40 MHz channel width */
2853 u8 is_dup; /* 1 = duplicated data streams */
2854 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2855 u8 max_search; /* maximun number of tables we can search */
3fbbf9a8 2856 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
e7392364
SG		 2857 u32 current_rate; /* rate_n_flags, uCode API format */
2858 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
3fbbf9a8
SG		 2859};
2860
2861struct il_traffic_load {
2862 unsigned long time_stamp; /* age of the oldest stats */
e7392364 2863 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
3fbbf9a8 2864 * slice */
e7392364
SG		 2865 u32 total; /* total num of packets during the
2866 * last TID_MAX_TIME_DIFF */
2867 u8 queue_count; /* number of queues that has
2868 * been used since the last cleanup */
2869 u8 head; /* start of the circular buffer */
3fbbf9a8
SG		 2870};
2871
2872/**
2873 * struct il_lq_sta -- driver's rate scaling ilate structure
2874 *
2875 * Pointer to this gets passed back and forth between driver and mac80211.
2876 */
2877struct il_lq_sta {
2878 u8 active_tbl; /* idx of active table, range 0-1 */
2879 u8 enable_counter; /* indicates HT mode */
2880 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
2881 u8 search_better_tbl; /* 1: currently trying alternate mode */
2882 s32 last_tpt;
2883
2884 /* The following determine when to search for a new mode */
2885 u32 table_count_limit;
2886 u32 max_failure_limit; /* # failed frames before new search */
2887 u32 max_success_limit; /* # successful frames before new search */
2888 u32 table_count;
2889 u32 total_failed; /* total failed frames, any/all rates */
2890 u32 total_success; /* total successful frames, any/all rates */
2891 u64 flush_timer; /* time staying in mode before new search */
2892
2893 u8 action_counter; /* # mode-switch actions tried */
2894 u8 is_green;
2895 u8 is_dup;
2896 enum ieee80211_band band;
2897
2898 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2899 u32 supp_rates;
2900 u16 active_legacy_rate;
2901 u16 active_siso_rate;
2902 u16 active_mimo2_rate;
e7392364 2903 s8 max_rate_idx; /* Max rate set by user */
3fbbf9a8
SG		 2904 u8 missed_rate_counter;
2905
2906 struct il_link_quality_cmd lq;
e7392364 2907 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
3fbbf9a8
SG		 2908 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2909 u8 tx_agg_tid_en;
2910#ifdef CONFIG_MAC80211_DEBUGFS
2911 struct dentry *rs_sta_dbgfs_scale_table_file;
2912 struct dentry *rs_sta_dbgfs_stats_table_file;
2913 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2914 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2915 u32 dbg_fixed_rate;
2916#endif
2917 struct il_priv *drv;
2918
2919 /* used to be in sta_info */
2920 int last_txrate_idx;
2921 /* last tx rate_n_flags */
2922 u32 last_rate_n_flags;
2923 /* packets destined for this STA are aggregated */
2924 u8 is_agg;
2925};
2926
2927/*
2928 * il_station_priv: Driver's ilate station information
2929 *
2930 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2931 * in the structure for use by driver. This structure is places in that
2932 * space.
2933 *
2934 * The common struct MUST be first because it is shared between
2935 * 3945 and 4965!
2936 */
2937struct il_station_priv {
2938 struct il_station_priv_common common;
2939 struct il_lq_sta lq_sta;
2940 atomic_t pending_frames;
2941 bool client;
2942 bool asleep;
2943};
2944
e7392364
SG		 2945static inline u8
2946il4965_num_of_ant(u8 m)
3fbbf9a8
SG		 2947{
2948 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2949}
2950
e7392364
SG		 2951static inline u8
2952il4965_first_antenna(u8 mask)
3fbbf9a8
SG		 2953{
2954 if (mask & ANT_A)
2955 return ANT_A;
2956 if (mask & ANT_B)
2957 return ANT_B;
2958 return ANT_C;
2959}
2960
3fbbf9a8
SG		 2961/**
2962 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
2963 *
2964 * The specific throughput table used is based on the type of network
2965 * the associated with, including A, B, G, and G w/ TGG protection
2966 */
2967extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2968
2969/* Initialize station's rate scaling information after adding station */
e7392364
SG		 2970extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2971 u8 sta_id);
2972extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2973 u8 sta_id);
3fbbf9a8
SG		 2974
2975/**
2976 * il_rate_control_register - Register the rate control algorithm callbacks
2977 *
2978 * Since the rate control algorithm is hardware specific, there is no need
2979 * or reason to place it as a stand alone module. The driver can call
2980 * il_rate_control_register in order to register the rate control callbacks
2981 * with the mac80211 subsystem. This should be performed prior to calling
2982 * ieee80211_register_hw
2983 *
2984 */
2985extern int il4965_rate_control_register(void);
2986extern int il3945_rate_control_register(void);
2987
2988/**
2989 * il_rate_control_unregister - Unregister the rate control callbacks
2990 *
2991 * This should be called after calling ieee80211_unregister_hw, but before
2992 * the driver is unloaded.
2993 */
2994extern void il4965_rate_control_unregister(void);
2995extern void il3945_rate_control_unregister(void);
2996
99412002
SG		 2997extern int il_power_update_mode(struct il_priv *il, bool force);
2998extern void il_power_initialize(struct il_priv *il);
47ef694d 2999
f02579e3
SG		 3000extern u32 il_debug_level;
3001
3002#ifdef CONFIG_IWLEGACY_DEBUG
3003/*
3004 * il_get_debug_level: Return active debug level for device
3005 *
3006 * Using sysfs it is possible to set per device debug level. This debug
3007 * level will be used if set, otherwise the global debug level which can be
3008 * set via module parameter is used.
3009 */
e7392364
SG		 3010static inline u32
3011il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3012{
3013 if (il->debug_level)
3014 return il->debug_level;
3015 else
3016 return il_debug_level;
3017}
3018#else
e7392364
SG		 3019static inline u32
3020il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3021{
3022 return il_debug_level;
3023}
3024#endif
3025
3026#define il_print_hex_error(il, p, len) \
3027do { \
3028 print_hex_dump(KERN_ERR, "iwl data: ", \
3029 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3030} while (0)
3031
3032#ifdef CONFIG_IWLEGACY_DEBUG
3033#define IL_DBG(level, fmt, args...) \
3034do { \
3035 if (il_get_debug_level(il) & level) \
3036 dev_printk(KERN_ERR, &il->hw->wiphy->dev, \
3037 "%c %s " fmt, in_interrupt() ? 'I' : 'U', \
3038 __func__ , ## args); \
3039} while (0)
3040
1722f8e1 3041#define il_print_hex_dump(il, level, p, len) \
f02579e3
SG		 3042do { \
3043 if (il_get_debug_level(il) & level) \
3044 print_hex_dump(KERN_DEBUG, "iwl data: ", \
3045 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3046} while (0)
3047
3048#else
3049#define IL_DBG(level, fmt, args...)
e7392364
SG		 3050static inline void
3051il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
3052{
3053}
3054#endif /* CONFIG_IWLEGACY_DEBUG */
f02579e3
SG		 3055
3056#ifdef CONFIG_IWLEGACY_DEBUGFS
3057int il_dbgfs_register(struct il_priv *il, const char *name);
3058void il_dbgfs_unregister(struct il_priv *il);
3059#else
3060static inline int
3061il_dbgfs_register(struct il_priv *il, const char *name)
3062{
3063 return 0;
3064}
e7392364
SG		 3065
3066static inline void
3067il_dbgfs_unregister(struct il_priv *il)
f02579e3
SG		 3068{
3069}
e7392364 3070#endif /* CONFIG_IWLEGACY_DEBUGFS */
f02579e3
SG		 3071
3072/*
3073 * To use the debug system:
3074 *
3075 * If you are defining a new debug classification, simply add it to the #define
3076 * list here in the form of
3077 *
3078 * #define IL_DL_xxxx VALUE
3079 *
3080 * where xxxx should be the name of the classification (for example, WEP).
3081 *
3082 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
3083 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
3084 * to send output to that classification.
3085 *
3086 * The active debug levels can be accessed via files
3087 *
1722f8e1 3088 * /sys/module/iwl4965/parameters/debug
f02579e3 3089 * /sys/module/iwl3945/parameters/debug
1722f8e1 3090 * /sys/class/net/wlan0/device/debug_level
f02579e3
SG		 3091 *
3092 * when CONFIG_IWLEGACY_DEBUG=y.
3093 */
3094
3095/* 0x0000000F - 0x00000001 */
3096#define IL_DL_INFO (1 << 0)
3097#define IL_DL_MAC80211 (1 << 1)
3098#define IL_DL_HCMD (1 << 2)
3099#define IL_DL_STATE (1 << 3)
3100/* 0x000000F0 - 0x00000010 */
3101#define IL_DL_MACDUMP (1 << 4)
3102#define IL_DL_HCMD_DUMP (1 << 5)
3103#define IL_DL_EEPROM (1 << 6)
3104#define IL_DL_RADIO (1 << 7)
3105/* 0x00000F00 - 0x00000100 */
3106#define IL_DL_POWER (1 << 8)
3107#define IL_DL_TEMP (1 << 9)
3108#define IL_DL_NOTIF (1 << 10)
3109#define IL_DL_SCAN (1 << 11)
3110/* 0x0000F000 - 0x00001000 */
3111#define IL_DL_ASSOC (1 << 12)
3112#define IL_DL_DROP (1 << 13)
3113#define IL_DL_TXPOWER (1 << 14)
3114#define IL_DL_AP (1 << 15)
3115/* 0x000F0000 - 0x00010000 */
3116#define IL_DL_FW (1 << 16)
3117#define IL_DL_RF_KILL (1 << 17)
3118#define IL_DL_FW_ERRORS (1 << 18)
3119#define IL_DL_LED (1 << 19)
3120/* 0x00F00000 - 0x00100000 */
3121#define IL_DL_RATE (1 << 20)
3122#define IL_DL_CALIB (1 << 21)
3123#define IL_DL_WEP (1 << 22)
3124#define IL_DL_TX (1 << 23)
3125/* 0x0F000000 - 0x01000000 */
3126#define IL_DL_RX (1 << 24)
3127#define IL_DL_ISR (1 << 25)
3128#define IL_DL_HT (1 << 26)
3129/* 0xF0000000 - 0x10000000 */
3130#define IL_DL_11H (1 << 28)
3131#define IL_DL_STATS (1 << 29)
3132#define IL_DL_TX_REPLY (1 << 30)
3133#define IL_DL_QOS (1 << 31)
3134
3135#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3136#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3137#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3138#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3139#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3140#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3141#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3142#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3143#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3144#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3145#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3146#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3147#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3148#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3149#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3150#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3151#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3152#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3153#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3154#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3155#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3156#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3157#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3158#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3159#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3160#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3161#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3162#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3163#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3164
e2ebc833 3165#endif /* __il_core_h__ */
Linux kernel - Deliverables
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