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iwlegacy: use FH39_ prefix in 3945 code
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.h
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
e94a4099 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
be663ab6 4 *
e94a4099
SG		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
be663ab6
WYG		 7 * published by the Free Software Foundation.
8 *
e94a4099
SG		 9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
be663ab6 13 *
e94a4099
SG		 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
be663ab6 17 *
e94a4099
SG		 18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
be663ab6
WYG		 20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
e94a4099
SG		 25 *****************************************************************************/
26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
30#include <linux/pci.h> /* for struct pci_device_id */
31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
47ef694d 34#include <net/mac80211.h>
e94a4099
SG		 35#include <net/ieee80211_radiotap.h>
36
99412002 37#include "commands.h"
e94a4099 38#include "csr.h"
e8c39d4e 39#include "prph.h"
e94a4099 40#include "iwl-debug.h"
e94a4099
SG		 41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
46#define RX_QUEUE_SIZE 256
47#define RX_QUEUE_MASK 255
48#define RX_QUEUE_SIZE_LOG 8
49
50/*
51 * RX related structures and functions
52 */
53#define RX_FREE_BUFFERS 64
54#define RX_LOW_WATERMARK 8
55
56#define U32_PAD(n) ((4-(n))&0x3)
57
58/* CT-KILL constants */
59#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
60
61/* Default noise level to report when noise measurement is not available.
62 * This may be because we're:
63 * 1) Not associated (4965, no beacon stats being sent to driver)
64 * 2) Scanning (noise measurement does not apply to associated channel)
65 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
66 * Use default noise value of -127 ... this is below the range of measurable
67 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
68 * Also, -127 works better than 0 when averaging frames with/without
69 * noise info (e.g. averaging might be done in app); measured dBm values are
70 * always negative ... using a negative value as the default keeps all
71 * averages within an s8's (used in some apps) range of negative values. */
72#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
73
74/*
75 * RTS threshold here is total size [2347] minus 4 FCS bytes
76 * Per spec:
77 * a value of 0 means RTS on all data/management packets
78 * a value > max MSDU size means no RTS
79 * else RTS for data/management frames where MPDU is larger
80 * than RTS value.
81 */
82#define DEFAULT_RTS_THRESHOLD 2347U
83#define MIN_RTS_THRESHOLD 0U
84#define MAX_RTS_THRESHOLD 2347U
85#define MAX_MSDU_SIZE 2304U
86#define MAX_MPDU_SIZE 2346U
87#define DEFAULT_BEACON_INTERVAL 100U
88#define DEFAULT_SHORT_RETRY_LIMIT 7U
89#define DEFAULT_LONG_RETRY_LIMIT 4U
90
91struct il_rx_buf {
92 dma_addr_t page_dma;
93 struct page *page;
94 struct list_head list;
95};
96
97#define rxb_addr(r) page_address(r->page)
98
99/* defined below */
100struct il_device_cmd;
101
102struct il_cmd_meta {
103 /* only for SYNC commands, iff the reply skb is wanted */
104 struct il_host_cmd *source;
105 /*
106 * only for ASYNC commands
107 * (which is somewhat stupid -- look at common.c for instance
108 * which duplicates a bunch of code because the callback isn't
109 * invoked for SYNC commands, if it were and its result passed
110 * through it would be simpler...)
111 */
112 void (*callback)(struct il_priv *il,
113 struct il_device_cmd *cmd,
114 struct il_rx_pkt *pkt);
115
116 /* The CMD_SIZE_HUGE flag bit indicates that the command
117 * structure is stored at the end of the shared queue memory. */
118 u32 flags;
119
120 DEFINE_DMA_UNMAP_ADDR(mapping);
121 DEFINE_DMA_UNMAP_LEN(len);
122};
123
124/*
125 * Generic queue structure
126 *
127 * Contains common data for Rx and Tx queues
128 */
129struct il_queue {
130 int n_bd; /* number of BDs in this queue */
131 int write_ptr; /* 1-st empty entry (idx) host_w*/
132 int read_ptr; /* last used entry (idx) host_r*/
133 /* use for monitoring and recovering the stuck queue */
134 dma_addr_t dma_addr; /* physical addr for BD's */
135 int n_win; /* safe queue win */
136 u32 id;
137 int low_mark; /* low watermark, resume queue if free
138 * space more than this */
139 int high_mark; /* high watermark, stop queue if free
140 * space less than this */
141};
142
143/* One for each TFD */
144struct il_tx_info {
145 struct sk_buff *skb;
146 struct il_rxon_context *ctx;
147};
148
149/**
150 * struct il_tx_queue - Tx Queue for DMA
151 * @q: generic Rx/Tx queue descriptor
152 * @bd: base of circular buffer of TFDs
153 * @cmd: array of command/TX buffer pointers
154 * @meta: array of meta data for each command/tx buffer
155 * @dma_addr_cmd: physical address of cmd/tx buffer array
156 * @txb: array of per-TFD driver data
157 * @time_stamp: time (in jiffies) of last read_ptr change
158 * @need_update: indicates need to update read/write idx
159 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
160 *
161 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
162 * descriptors) and required locking structures.
163 */
164#define TFD_TX_CMD_SLOTS 256
165#define TFD_CMD_SLOTS 32
166
167struct il_tx_queue {
168 struct il_queue q;
169 void *tfds;
170 struct il_device_cmd **cmd;
171 struct il_cmd_meta *meta;
172 struct il_tx_info *txb;
173 unsigned long time_stamp;
174 u8 need_update;
175 u8 sched_retry;
176 u8 active;
177 u8 swq_id;
178};
179
47ef694d
SG		 180/*
181 * EEPROM access time values:
182 *
183 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
184 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
185 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
186 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
187 */
188#define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
189
190#define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
191#define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
192
193
194/*
195 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
196 *
197 * IBSS and/or AP operation is allowed *only* on those channels with
198 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
199 * RADAR detection is not supported by the 4965 driver, but is a
200 * requirement for establishing a new network for legal operation on channels
201 * requiring RADAR detection or restricting ACTIVE scanning.
202 *
203 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
204 * It only indicates that 20 MHz channel use is supported; HT40 channel
205 * usage is indicated by a separate set of regulatory flags for each
206 * HT40 channel pair.
207 *
208 * NOTE: Using a channel inappropriately will result in a uCode error!
209 */
210#define IL_NUM_TX_CALIB_GROUPS 5
211enum {
212 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
213 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
214 /* Bit 2 Reserved */
215 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
216 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
217 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
218 /* Bit 6 Reserved (was Narrow Channel) */
219 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
220};
221
222/* SKU Capabilities */
223/* 3945 only */
224#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
225#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
226
227/* *regulatory* channel data format in eeprom, one for each channel.
228 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
229struct il_eeprom_channel {
230 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
231 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
232} __packed;
233
234/* 3945 Specific */
235#define EEPROM_3945_EEPROM_VERSION (0x2f)
236
237/* 4965 has two radio transmitters (and 3 radio receivers) */
238#define EEPROM_TX_POWER_TX_CHAINS (2)
239
240/* 4965 has room for up to 8 sets of txpower calibration data */
241#define EEPROM_TX_POWER_BANDS (8)
242
243/* 4965 factory calibration measures txpower gain settings for
244 * each of 3 target output levels */
245#define EEPROM_TX_POWER_MEASUREMENTS (3)
246
247/* 4965 Specific */
248/* 4965 driver does not work with txpower calibration version < 5 */
249#define EEPROM_4965_TX_POWER_VERSION (5)
250#define EEPROM_4965_EEPROM_VERSION (0x2f)
251#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
252#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
253#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
254#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
255
256/* 2.4 GHz */
257extern const u8 il_eeprom_band_1[14];
258
259/*
260 * factory calibration data for one txpower level, on one channel,
261 * measured on one of the 2 tx chains (radio transmitter and associated
262 * antenna). EEPROM contains:
263 *
264 * 1) Temperature (degrees Celsius) of device when measurement was made.
265 *
266 * 2) Gain table idx used to achieve the target measurement power.
267 * This refers to the "well-known" gain tables (see 4965.h).
268 *
269 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
270 *
271 * 4) RF power amplifier detector level measurement (not used).
272 */
273struct il_eeprom_calib_measure {
274 u8 temperature; /* Device temperature (Celsius) */
275 u8 gain_idx; /* Index into gain table */
276 u8 actual_pow; /* Measured RF output power, half-dBm */
277 s8 pa_det; /* Power amp detector level (not used) */
278} __packed;
279
280
281/*
282 * measurement set for one channel. EEPROM contains:
283 *
284 * 1) Channel number measured
285 *
286 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
287 * (a.k.a. "tx chains") (6 measurements altogether)
288 */
289struct il_eeprom_calib_ch_info {
290 u8 ch_num;
291 struct il_eeprom_calib_measure
292 measurements[EEPROM_TX_POWER_TX_CHAINS]
293 [EEPROM_TX_POWER_MEASUREMENTS];
294} __packed;
295
296/*
297 * txpower subband info.
298 *
299 * For each frequency subband, EEPROM contains the following:
300 *
301 * 1) First and last channels within range of the subband. "0" values
302 * indicate that this sample set is not being used.
303 *
304 * 2) Sample measurement sets for 2 channels close to the range endpoints.
305 */
306struct il_eeprom_calib_subband_info {
307 u8 ch_from; /* channel number of lowest channel in subband */
308 u8 ch_to; /* channel number of highest channel in subband */
309 struct il_eeprom_calib_ch_info ch1;
310 struct il_eeprom_calib_ch_info ch2;
311} __packed;
312
313
314/*
315 * txpower calibration info. EEPROM contains:
316 *
317 * 1) Factory-measured saturation power levels (maximum levels at which
318 * tx power amplifier can output a signal without too much distortion).
319 * There is one level for 2.4 GHz band and one for 5 GHz band. These
320 * values apply to all channels within each of the bands.
321 *
322 * 2) Factory-measured power supply voltage level. This is assumed to be
323 * constant (i.e. same value applies to all channels/bands) while the
324 * factory measurements are being made.
325 *
326 * 3) Up to 8 sets of factory-measured txpower calibration values.
327 * These are for different frequency ranges, since txpower gain
328 * characteristics of the analog radio circuitry vary with frequency.
329 *
330 * Not all sets need to be filled with data;
331 * struct il_eeprom_calib_subband_info contains range of channels
332 * (0 if unused) for each set of data.
333 */
334struct il_eeprom_calib_info {
335 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
336 u8 saturation_power52; /* half-dBm */
337 __le16 voltage; /* signed */
338 struct il_eeprom_calib_subband_info
339 band_info[EEPROM_TX_POWER_BANDS];
340} __packed;
341
342
343/* General */
344#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
345#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
346#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
347#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
348#define EEPROM_VERSION (2*0x44) /* 2 bytes */
349#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
350#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
351#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
352#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
353#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
354
355/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
356#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
357#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
358#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
359#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
360#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
361#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
362
363#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
364#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
365
366/*
367 * Per-channel regulatory data.
368 *
369 * Each channel that *might* be supported by iwl has a fixed location
370 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
371 * txpower (MSB).
372 *
373 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
374 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
375 *
376 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
377 */
378#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
379#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
380#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
381
382/*
383 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
384 * 5.0 GHz channels 7, 8, 11, 12, 16
385 * (4915-5080MHz) (none of these is ever supported)
386 */
387#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
388#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
389
390/*
391 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
392 * (5170-5320MHz)
393 */
394#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
395#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
396
397/*
398 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
399 * (5500-5700MHz)
400 */
401#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
402#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
403
404/*
405 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
406 * (5725-5825MHz)
407 */
408#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
409#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
410
411/*
412 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
413 *
414 * The channel listed is the center of the lower 20 MHz half of the channel.
415 * The overall center frequency is actually 2 channels (10 MHz) above that,
416 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
417 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
418 * and the overall HT40 channel width centers on channel 3.
419 *
420 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
421 * control channel to which to tune. RXON also specifies whether the
422 * control channel is the upper or lower half of a HT40 channel.
423 *
424 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
425 */
426#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
427
428/*
429 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
430 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
431 */
432#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
433
434#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
435
436struct il_eeprom_ops {
437 const u32 regulatory_bands[7];
438 int (*acquire_semaphore) (struct il_priv *il);
439 void (*release_semaphore) (struct il_priv *il);
440};
441
442
443int il_eeprom_init(struct il_priv *il);
444void il_eeprom_free(struct il_priv *il);
445const u8 *il_eeprom_query_addr(const struct il_priv *il,
446 size_t offset);
447u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
448int il_init_channel_map(struct il_priv *il);
449void il_free_channel_map(struct il_priv *il);
450const struct il_channel_info *il_get_channel_info(
451 const struct il_priv *il,
452 enum ieee80211_band band, u16 channel);
453
454
e94a4099
SG		 455#define IL_NUM_SCAN_RATES (2)
456
457struct il4965_channel_tgd_info {
458 u8 type;
459 s8 max_power;
460};
461
462struct il4965_channel_tgh_info {
463 s64 last_radar_time;
464};
465
466#define IL4965_MAX_RATE (33)
467
468struct il3945_clip_group {
469 /* maximum power level to prevent clipping for each rate, derived by
470 * us from this band's saturation power in EEPROM */
471 const s8 clip_powers[IL_MAX_RATES];
472};
473
474/* current Tx power values to use, one for each rate for each channel.
475 * requested power is limited by:
476 * -- regulatory EEPROM limits for this channel
477 * -- hardware capabilities (clip-powers)
478 * -- spectrum management
479 * -- user preference (e.g. iwconfig)
480 * when requested power is set, base power idx must also be set. */
481struct il3945_channel_power_info {
482 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
483 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
484 s8 base_power_idx; /* gain idx for power at factory temp. */
485 s8 requested_power; /* power (dBm) requested for this chnl/rate */
486};
487
488/* current scan Tx power values to use, one for each scan rate for each
489 * channel. */
490struct il3945_scan_power_info {
491 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
492 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
493 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
494};
495
496/*
497 * One for each channel, holds all channel setup data
498 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
499 * with one another!
500 */
501struct il_channel_info {
502 struct il4965_channel_tgd_info tgd;
503 struct il4965_channel_tgh_info tgh;
504 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
505 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
506 * HT40 channel */
507
508 u8 channel; /* channel number */
509 u8 flags; /* flags copied from EEPROM */
510 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
511 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
512 s8 min_power; /* always 0 */
513 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
514
515 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
516 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
517 enum ieee80211_band band;
518
519 /* HT40 channel info */
520 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
521 u8 ht40_flags; /* flags copied from EEPROM */
522 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
523
524 /* Radio/DSP gain settings for each "normal" data Tx rate.
525 * These include, in addition to RF and DSP gain, a few fields for
526 * remembering/modifying gain settings (idxes). */
527 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
528
529 /* Radio/DSP gain settings for each scan rate, for directed scans. */
530 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
531};
532
533#define IL_TX_FIFO_BK 0 /* shared */
534#define IL_TX_FIFO_BE 1
535#define IL_TX_FIFO_VI 2 /* shared */
536#define IL_TX_FIFO_VO 3
537#define IL_TX_FIFO_UNUSED -1
538
539/* Minimum number of queues. MAX_NUM is defined in hw specific files.
540 * Set the minimum to accommodate the 4 standard TX queues, 1 command
541 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
542#define IL_MIN_NUM_QUEUES 10
543
544#define IL_DEFAULT_CMD_QUEUE_NUM 4
545
546#define IEEE80211_DATA_LEN 2304
547#define IEEE80211_4ADDR_LEN 30
548#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
549#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
550
551struct il_frame {
552 union {
553 struct ieee80211_hdr frame;
554 struct il_tx_beacon_cmd beacon;
555 u8 raw[IEEE80211_FRAME_LEN];
556 u8 cmd[360];
557 } u;
558 struct list_head list;
559};
560
561#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
562#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
563#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
564
565enum {
566 CMD_SYNC = 0,
567 CMD_SIZE_NORMAL = 0,
568 CMD_NO_SKB = 0,
569 CMD_SIZE_HUGE = (1 << 0),
570 CMD_ASYNC = (1 << 1),
571 CMD_WANT_SKB = (1 << 2),
572 CMD_MAPPED = (1 << 3),
573};
574
575#define DEF_CMD_PAYLOAD_SIZE 320
576
577/**
578 * struct il_device_cmd
579 *
580 * For allocation of the command and tx queues, this establishes the overall
581 * size of the largest command we send to uCode, except for a scan command
582 * (which is relatively huge; space is allocated separately).
583 */
584struct il_device_cmd {
585 struct il_cmd_header hdr; /* uCode API */
586 union {
587 u32 flags;
588 u8 val8;
589 u16 val16;
590 u32 val32;
591 struct il_tx_cmd tx;
592 u8 payload[DEF_CMD_PAYLOAD_SIZE];
593 } __packed cmd;
594} __packed;
595
596#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
597
598
599struct il_host_cmd {
600 const void *data;
601 unsigned long reply_page;
602 void (*callback)(struct il_priv *il,
603 struct il_device_cmd *cmd,
604 struct il_rx_pkt *pkt);
605 u32 flags;
606 u16 len;
607 u8 id;
608};
609
610#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
611#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
612#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
613
614/**
615 * struct il_rx_queue - Rx queue
616 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
617 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
618 * @read: Shared idx to newest available Rx buffer
619 * @write: Shared idx to oldest written Rx packet
620 * @free_count: Number of pre-allocated buffers in rx_free
621 * @rx_free: list of free SKBs for use
622 * @rx_used: List of Rx buffers with no SKB
623 * @need_update: flag to indicate we need to update read/write idx
624 * @rb_stts: driver's pointer to receive buffer status
625 * @rb_stts_dma: bus address of receive buffer status
626 *
627 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
628 */
629struct il_rx_queue {
630 __le32 *bd;
631 dma_addr_t bd_dma;
632 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
633 struct il_rx_buf *queue[RX_QUEUE_SIZE];
634 u32 read;
635 u32 write;
636 u32 free_count;
637 u32 write_actual;
638 struct list_head rx_free;
639 struct list_head rx_used;
640 int need_update;
641 struct il_rb_status *rb_stts;
642 dma_addr_t rb_stts_dma;
643 spinlock_t lock;
644};
645
646#define IL_SUPPORTED_RATES_IE_LEN 8
647
648#define MAX_TID_COUNT 9
649
650#define IL_INVALID_RATE 0xFF
651#define IL_INVALID_VALUE -1
652
653/**
654 * struct il_ht_agg -- aggregation status while waiting for block-ack
655 * @txq_id: Tx queue used for Tx attempt
656 * @frame_count: # frames attempted by Tx command
657 * @wait_for_ba: Expect block-ack before next Tx reply
658 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
659 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
660 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
661 * @rate_n_flags: Rate at which Tx was attempted
662 *
663 * If C_TX indicates that aggregation was attempted, driver must wait
664 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
665 * until block ack arrives.
666 */
667struct il_ht_agg {
668 u16 txq_id;
669 u16 frame_count;
670 u16 wait_for_ba;
671 u16 start_idx;
672 u64 bitmap;
673 u32 rate_n_flags;
674#define IL_AGG_OFF 0
675#define IL_AGG_ON 1
676#define IL_EMPTYING_HW_QUEUE_ADDBA 2
677#define IL_EMPTYING_HW_QUEUE_DELBA 3
678 u8 state;
679};
680
681
682struct il_tid_data {
683 u16 seq_number; /* 4965 only */
684 u16 tfds_in_queue;
685 struct il_ht_agg agg;
686};
687
688struct il_hw_key {
689 u32 cipher;
690 int keylen;
691 u8 keyidx;
692 u8 key[32];
693};
694
695union il_ht_rate_supp {
696 u16 rates;
697 struct {
698 u8 siso_rate;
699 u8 mimo_rate;
700 };
701};
702
703#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
704#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
705#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
706#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
707#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
708#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
709#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
710
711/*
712 * Maximal MPDU density for TX aggregation
713 * 4 - 2us density
714 * 5 - 4us density
715 * 6 - 8us density
716 * 7 - 16us density
717 */
718#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
719#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
720#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
721#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
722#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
723#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
724#define CFG_HT_MPDU_DENSITY_MIN (0x1)
725
726struct il_ht_config {
727 bool single_chain_sufficient;
728 enum ieee80211_smps_mode smps; /* current smps mode */
729};
730
731/* QoS structures */
732struct il_qos_info {
733 int qos_active;
734 struct il_qosparam_cmd def_qos_parm;
735};
736
737/*
738 * Structure should be accessed with sta_lock held. When station addition
739 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
740 * the commands (il_addsta_cmd and il_link_quality_cmd) without
741 * sta_lock held.
742 */
743struct il_station_entry {
744 struct il_addsta_cmd sta;
745 struct il_tid_data tid[MAX_TID_COUNT];
746 u8 used, ctxid;
747 struct il_hw_key keyinfo;
748 struct il_link_quality_cmd *lq;
749};
750
751struct il_station_priv_common {
752 struct il_rxon_context *ctx;
753 u8 sta_id;
754};
755
e94a4099
SG		 756/**
757 * struct il_vif_priv - driver's ilate per-interface information
758 *
759 * When mac80211 allocates a virtual interface, it can allocate
760 * space for us to put data into.
761 */
762struct il_vif_priv {
763 struct il_rxon_context *ctx;
764 u8 ibss_bssid_sta_id;
765};
766
767/* one for each uCode image (inst/data, boot/init/runtime) */
768struct fw_desc {
769 void *v_addr; /* access by driver */
770 dma_addr_t p_addr; /* access by card's busmaster DMA */
771 u32 len; /* bytes */
772};
773
774/* uCode file layout */
775struct il_ucode_header {
776 __le32 ver; /* major/minor/API/serial */
777 struct {
778 __le32 inst_size; /* bytes of runtime code */
779 __le32 data_size; /* bytes of runtime data */
780 __le32 init_size; /* bytes of init code */
781 __le32 init_data_size; /* bytes of init data */
782 __le32 boot_size; /* bytes of bootstrap code */
783 u8 data[0]; /* in same order as sizes */
784 } v1;
785};
786
787struct il4965_ibss_seq {
788 u8 mac[ETH_ALEN];
789 u16 seq_num;
790 u16 frag_num;
791 unsigned long packet_time;
792 struct list_head list;
793};
794
795struct il_sensitivity_ranges {
796 u16 min_nrg_cck;
797 u16 max_nrg_cck;
798
799 u16 nrg_th_cck;
800 u16 nrg_th_ofdm;
801
802 u16 auto_corr_min_ofdm;
803 u16 auto_corr_min_ofdm_mrc;
804 u16 auto_corr_min_ofdm_x1;
805 u16 auto_corr_min_ofdm_mrc_x1;
806
807 u16 auto_corr_max_ofdm;
808 u16 auto_corr_max_ofdm_mrc;
809 u16 auto_corr_max_ofdm_x1;
810 u16 auto_corr_max_ofdm_mrc_x1;
811
812 u16 auto_corr_max_cck;
813 u16 auto_corr_max_cck_mrc;
814 u16 auto_corr_min_cck;
815 u16 auto_corr_min_cck_mrc;
816
817 u16 barker_corr_th_min;
818 u16 barker_corr_th_min_mrc;
819 u16 nrg_th_cca;
820};
821
822
823#define KELVIN_TO_CELSIUS(x) ((x)-273)
824#define CELSIUS_TO_KELVIN(x) ((x)+273)
825
826
827/**
828 * struct il_hw_params
829 * @max_txq_num: Max # Tx queues supported
830 * @dma_chnl_num: Number of Tx DMA/FIFO channels
831 * @scd_bc_tbls_size: size of scheduler byte count tables
832 * @tfd_size: TFD size
833 * @tx/rx_chains_num: Number of TX/RX chains
834 * @valid_tx/rx_ant: usable antennas
835 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
836 * @max_rxq_log: Log-base-2 of max_rxq_size
837 * @rx_page_order: Rx buffer page order
838 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
839 * @max_stations:
840 * @ht40_channel: is 40MHz width possible in band 2.4
841 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
842 * @sw_crypto: 0 for hw, 1 for sw
843 * @max_xxx_size: for ucode uses
844 * @ct_kill_threshold: temperature threshold
845 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
846 * @struct il_sensitivity_ranges: range of sensitivity values
847 */
848struct il_hw_params {
849 u8 max_txq_num;
850 u8 dma_chnl_num;
851 u16 scd_bc_tbls_size;
852 u32 tfd_size;
853 u8 tx_chains_num;
854 u8 rx_chains_num;
855 u8 valid_tx_ant;
856 u8 valid_rx_ant;
857 u16 max_rxq_size;
858 u16 max_rxq_log;
859 u32 rx_page_order;
860 u32 rx_wrt_ptr_reg;
861 u8 max_stations;
862 u8 ht40_channel;
863 u8 max_beacon_itrvl; /* in 1024 ms */
864 u32 max_inst_size;
865 u32 max_data_size;
866 u32 max_bsm_size;
867 u32 ct_kill_threshold; /* value in hw-dependent units */
868 u16 beacon_time_tsf_bits;
869 const struct il_sensitivity_ranges *sens;
870};
871
872
873/******************************************************************************
874 *
875 * Functions implemented in core module which are forward declared here
876 * for use by iwl-[4-5].c
877 *
878 * NOTE: The implementation of these functions are not hardware specific
879 * which is why they are in the core module files.
880 *
881 * Naming convention --
882 * il_ <-- Is part of iwlwifi
883 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
884 * il4965_bg_ <-- Called from work queue context
885 * il4965_mac_ <-- mac80211 callback
886 *
887 ****************************************************************************/
888extern void il4965_update_chain_flags(struct il_priv *il);
889extern const u8 il_bcast_addr[ETH_ALEN];
890extern int il_queue_space(const struct il_queue *q);
891static inline int il_queue_used(const struct il_queue *q, int i)
892{
893 return q->write_ptr >= q->read_ptr ?
894 (i >= q->read_ptr && i < q->write_ptr) :
895 !(i < q->read_ptr && i >= q->write_ptr);
896}
897
898
899static inline u8 il_get_cmd_idx(struct il_queue *q, u32 idx,
900 int is_huge)
901{
902 /*
903 * This is for init calibration result and scan command which
904 * required buffer > TFD_MAX_PAYLOAD_SIZE,
905 * the big buffer at end of command array
906 */
907 if (is_huge)
908 return q->n_win; /* must be power of 2 */
909
910 /* Otherwise, use normal size buffers */
911 return idx & (q->n_win - 1);
912}
913
914
915struct il_dma_ptr {
916 dma_addr_t dma;
917 void *addr;
918 size_t size;
919};
920
921#define IL_OPERATION_MODE_AUTO 0
922#define IL_OPERATION_MODE_HT_ONLY 1
923#define IL_OPERATION_MODE_MIXED 2
924#define IL_OPERATION_MODE_20MHZ 3
925
926#define IL_TX_CRC_SIZE 4
927#define IL_TX_DELIMITER_SIZE 4
928
929#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
930
931/* Sensitivity and chain noise calibration */
932#define INITIALIZATION_VALUE 0xFFFF
933#define IL4965_CAL_NUM_BEACONS 20
934#define IL_CAL_NUM_BEACONS 16
935#define MAXIMUM_ALLOWED_PATHLOSS 15
936
937#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
938
939#define MAX_FA_OFDM 50
940#define MIN_FA_OFDM 5
941#define MAX_FA_CCK 50
942#define MIN_FA_CCK 5
943
944#define AUTO_CORR_STEP_OFDM 1
945
946#define AUTO_CORR_STEP_CCK 3
947#define AUTO_CORR_MAX_TH_CCK 160
948
949#define NRG_DIFF 2
950#define NRG_STEP_CCK 2
951#define NRG_MARGIN 8
952#define MAX_NUMBER_CCK_NO_FA 100
953
954#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
955
956#define CHAIN_A 0
957#define CHAIN_B 1
958#define CHAIN_C 2
959#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
960#define ALL_BAND_FILTER 0xFF00
961#define IN_BAND_FILTER 0xFF
962#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
963
964#define NRG_NUM_PREV_STAT_L 20
965#define NUM_RX_CHAINS 3
966
967enum il4965_false_alarm_state {
968 IL_FA_TOO_MANY = 0,
969 IL_FA_TOO_FEW = 1,
970 IL_FA_GOOD_RANGE = 2,
971};
972
973enum il4965_chain_noise_state {
974 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
975 IL_CHAIN_NOISE_ACCUMULATE,
976 IL_CHAIN_NOISE_CALIBRATED,
977 IL_CHAIN_NOISE_DONE,
978};
979
980enum il4965_calib_enabled_state {
981 IL_CALIB_DISABLED = 0, /* must be 0 */
982 IL_CALIB_ENABLED = 1,
983};
984
985/*
986 * enum il_calib
987 * defines the order in which results of initial calibrations
988 * should be sent to the runtime uCode
989 */
990enum il_calib {
991 IL_CALIB_MAX,
992};
993
994/* Opaque calibration results */
995struct il_calib_result {
996 void *buf;
997 size_t buf_len;
998};
999
1000enum ucode_type {
1001 UCODE_NONE = 0,
1002 UCODE_INIT,
1003 UCODE_RT
1004};
1005
1006/* Sensitivity calib data */
1007struct il_sensitivity_data {
1008 u32 auto_corr_ofdm;
1009 u32 auto_corr_ofdm_mrc;
1010 u32 auto_corr_ofdm_x1;
1011 u32 auto_corr_ofdm_mrc_x1;
1012 u32 auto_corr_cck;
1013 u32 auto_corr_cck_mrc;
1014
1015 u32 last_bad_plcp_cnt_ofdm;
1016 u32 last_fa_cnt_ofdm;
1017 u32 last_bad_plcp_cnt_cck;
1018 u32 last_fa_cnt_cck;
1019
1020 u32 nrg_curr_state;
1021 u32 nrg_prev_state;
1022 u32 nrg_value[10];
1023 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
1024 u32 nrg_silence_ref;
1025 u32 nrg_energy_idx;
1026 u32 nrg_silence_idx;
1027 u32 nrg_th_cck;
1028 s32 nrg_auto_corr_silence_diff;
1029 u32 num_in_cck_no_fa;
1030 u32 nrg_th_ofdm;
1031
1032 u16 barker_corr_th_min;
1033 u16 barker_corr_th_min_mrc;
1034 u16 nrg_th_cca;
1035};
1036
1037/* Chain noise (differential Rx gain) calib data */
1038struct il_chain_noise_data {
1039 u32 active_chains;
1040 u32 chain_noise_a;
1041 u32 chain_noise_b;
1042 u32 chain_noise_c;
1043 u32 chain_signal_a;
1044 u32 chain_signal_b;
1045 u32 chain_signal_c;
1046 u16 beacon_count;
1047 u8 disconn_array[NUM_RX_CHAINS];
1048 u8 delta_gain_code[NUM_RX_CHAINS];
1049 u8 radio_write;
1050 u8 state;
1051};
1052
1053#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
1054#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1055
1056#define IL_TRAFFIC_ENTRIES (256)
1057#define IL_TRAFFIC_ENTRY_SIZE (64)
1058
1059enum {
1060 MEASUREMENT_READY = (1 << 0),
1061 MEASUREMENT_ACTIVE = (1 << 1),
1062};
1063
1064/* interrupt stats */
1065struct isr_stats {
1066 u32 hw;
1067 u32 sw;
1068 u32 err_code;
1069 u32 sch;
1070 u32 alive;
1071 u32 rfkill;
1072 u32 ctkill;
1073 u32 wakeup;
1074 u32 rx;
1075 u32 handlers[IL_CN_MAX];
1076 u32 tx;
1077 u32 unhandled;
1078};
1079
1080/* management stats */
1081enum il_mgmt_stats {
1082 MANAGEMENT_ASSOC_REQ = 0,
1083 MANAGEMENT_ASSOC_RESP,
1084 MANAGEMENT_REASSOC_REQ,
1085 MANAGEMENT_REASSOC_RESP,
1086 MANAGEMENT_PROBE_REQ,
1087 MANAGEMENT_PROBE_RESP,
1088 MANAGEMENT_BEACON,
1089 MANAGEMENT_ATIM,
1090 MANAGEMENT_DISASSOC,
1091 MANAGEMENT_AUTH,
1092 MANAGEMENT_DEAUTH,
1093 MANAGEMENT_ACTION,
1094 MANAGEMENT_MAX,
1095};
1096/* control stats */
1097enum il_ctrl_stats {
1098 CONTROL_BACK_REQ = 0,
1099 CONTROL_BACK,
1100 CONTROL_PSPOLL,
1101 CONTROL_RTS,
1102 CONTROL_CTS,
1103 CONTROL_ACK,
1104 CONTROL_CFEND,
1105 CONTROL_CFENDACK,
1106 CONTROL_MAX,
1107};
1108
1109struct traffic_stats {
1110#ifdef CONFIG_IWLEGACY_DEBUGFS
1111 u32 mgmt[MANAGEMENT_MAX];
1112 u32 ctrl[CONTROL_MAX];
1113 u32 data_cnt;
1114 u64 data_bytes;
1115#endif
1116};
1117
1118/*
1119 * host interrupt timeout value
1120 * used with setting interrupt coalescing timer
1121 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1122 *
1123 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1124 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1125 */
1126#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1127#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1128#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1129#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1130#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1131#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1132
1133#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1134
1135/* TX queue watchdog timeouts in mSecs */
1136#define IL_DEF_WD_TIMEOUT (2000)
1137#define IL_LONG_WD_TIMEOUT (10000)
1138#define IL_MAX_WD_TIMEOUT (120000)
1139
1140struct il_force_reset {
1141 int reset_request_count;
1142 int reset_success_count;
1143 int reset_reject_count;
1144 unsigned long reset_duration;
1145 unsigned long last_force_reset_jiffies;
1146};
1147
1148/* extend beacon time format bit shifting */
1149/*
1150 * for _3945 devices
1151 * bits 31:24 - extended
1152 * bits 23:0 - interval
1153 */
1154#define IL3945_EXT_BEACON_TIME_POS 24
1155/*
1156 * for _4965 devices
1157 * bits 31:22 - extended
1158 * bits 21:0 - interval
1159 */
1160#define IL4965_EXT_BEACON_TIME_POS 22
1161
1162struct il_rxon_context {
1163 struct ieee80211_vif *vif;
1164
1165 const u8 *ac_to_fifo;
1166 const u8 *ac_to_queue;
1167 u8 mcast_queue;
1168
1169 /*
1170 * We could use the vif to indicate active, but we
1171 * also need it to be active during disabling when
1172 * we already removed the vif for type setting.
1173 */
1174 bool always_active, is_active;
1175
1176 bool ht_need_multiple_chains;
1177
1178 int ctxid;
1179
1180 u32 interface_modes, exclusive_interface_modes;
1181 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1182
1183 /*
1184 * We declare this const so it can only be
1185 * changed via explicit cast within the
1186 * routines that actually update the physical
1187 * hardware.
1188 */
1189 const struct il_rxon_cmd active;
1190 struct il_rxon_cmd staging;
1191
1192 struct il_rxon_time_cmd timing;
1193
1194 struct il_qos_info qos_data;
1195
1196 u8 bcast_sta_id, ap_sta_id;
1197
1198 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
1199 u8 qos_cmd;
1200 u8 wep_key_cmd;
1201
1202 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1203 u8 key_mapping_keys;
1204
1205 __le32 station_flags;
1206
1207 struct {
1208 bool non_gf_sta_present;
1209 u8 protection;
1210 bool enabled, is_40mhz;
1211 u8 extension_chan_offset;
1212 } ht;
1213};
1214
99412002
SG		 1215struct il_power_mgr {
1216 struct il_powertable_cmd sleep_cmd;
1217 struct il_powertable_cmd sleep_cmd_next;
1218 int debug_sleep_level_override;
1219 bool pci_pm;
1220};
1221
e94a4099
SG		 1222struct il_priv {
1223
1224 /* ieee device used by generic ieee processing code */
1225 struct ieee80211_hw *hw;
1226 struct ieee80211_channel *ieee_channels;
1227 struct ieee80211_rate *ieee_rates;
1228 struct il_cfg *cfg;
1229
1230 /* temporary frame storage list */
1231 struct list_head free_frames;
1232 int frames_count;
1233
1234 enum ieee80211_band band;
1235 int alloc_rxb_page;
1236
1237 void (*handlers[IL_CN_MAX])(struct il_priv *il,
1238 struct il_rx_buf *rxb);
1239
1240 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1241
1242 /* spectrum measurement report caching */
1243 struct il_spectrum_notification measure_report;
1244 u8 measurement_status;
1245
1246 /* ucode beacon time */
1247 u32 ucode_beacon_time;
1248 int missed_beacon_threshold;
1249
1250 /* track IBSS manager (last beacon) status */
1251 u32 ibss_manager;
1252
1253 /* force reset */
1254 struct il_force_reset force_reset;
1255
1256 /* we allocate array of il_channel_info for NIC's valid channels.
1257 * Access via channel # using indirect idx array */
1258 struct il_channel_info *channel_info; /* channel info array */
1259 u8 channel_count; /* # of channels */
1260
1261 /* thermal calibration */
1262 s32 temperature; /* degrees Kelvin */
1263 s32 last_temperature;
1264
1265 /* init calibration results */
1266 struct il_calib_result calib_results[IL_CALIB_MAX];
1267
1268 /* Scan related variables */
1269 unsigned long scan_start;
1270 unsigned long scan_start_tsf;
1271 void *scan_cmd;
1272 enum ieee80211_band scan_band;
1273 struct cfg80211_scan_request *scan_request;
1274 struct ieee80211_vif *scan_vif;
1275 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1276 u8 mgmt_tx_ant;
1277
1278 /* spinlock */
1279 spinlock_t lock; /* protect general shared data */
1280 spinlock_t hcmd_lock; /* protect hcmd */
1281 spinlock_t reg_lock; /* protect hw register access */
1282 struct mutex mutex;
1283
1284 /* basic pci-network driver stuff */
1285 struct pci_dev *pci_dev;
1286
1287 /* pci hardware address support */
1288 void __iomem *hw_base;
1289 u32 hw_rev;
1290 u32 hw_wa_rev;
1291 u8 rev_id;
1292
1293 /* command queue number */
1294 u8 cmd_queue;
1295
1296 /* max number of station keys */
1297 u8 sta_key_max_num;
1298
1299 /* EEPROM MAC addresses */
1300 struct mac_address addresses[1];
1301
1302 /* uCode images, save to reload in case of failure */
1303 int fw_idx; /* firmware we're trying to load */
1304 u32 ucode_ver; /* version of ucode, copy of
1305 il_ucode.ver */
1306 struct fw_desc ucode_code; /* runtime inst */
1307 struct fw_desc ucode_data; /* runtime data original */
1308 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1309 struct fw_desc ucode_init; /* initialization inst */
1310 struct fw_desc ucode_init_data; /* initialization data */
1311 struct fw_desc ucode_boot; /* bootstrap inst */
1312 enum ucode_type ucode_type;
1313 u8 ucode_write_complete; /* the image write is complete */
1314 char firmware_name[25];
1315
1316 struct il_rxon_context ctx;
1317
1318 __le16 switch_channel;
1319
1320 /* 1st responses from initialize and runtime uCode images.
1321 * _4965's initialize alive response contains some calibration data. */
1322 struct il_init_alive_resp card_alive_init;
1323 struct il_alive_resp card_alive;
1324
1325 u16 active_rate;
1326
1327 u8 start_calib;
1328 struct il_sensitivity_data sensitivity_data;
1329 struct il_chain_noise_data chain_noise_data;
1330 __le16 sensitivity_tbl[HD_TBL_SIZE];
1331
1332 struct il_ht_config current_ht_config;
1333
1334 /* Rate scaling data */
1335 u8 retry_rate;
1336
1337 wait_queue_head_t wait_command_queue;
1338
1339 int activity_timer_active;
1340
1341 /* Rx and Tx DMA processing queues */
1342 struct il_rx_queue rxq;
1343 struct il_tx_queue *txq;
1344 unsigned long txq_ctx_active_msk;
1345 struct il_dma_ptr kw; /* keep warm address */
1346 struct il_dma_ptr scd_bc_tbls;
1347
1348 u32 scd_base_addr; /* scheduler sram base address */
1349
1350 unsigned long status;
1351
1352 /* counts mgmt, ctl, and data packets */
1353 struct traffic_stats tx_stats;
1354 struct traffic_stats rx_stats;
1355
1356 /* counts interrupts */
1357 struct isr_stats isr_stats;
1358
1359 struct il_power_mgr power_data;
1360
1361 /* context information */
1362 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
1363
1364 /* station table variables */
1365
1366 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1367 spinlock_t sta_lock;
1368 int num_stations;
1369 struct il_station_entry stations[IL_STATION_COUNT];
1370 unsigned long ucode_key_table;
1371
1372 /* queue refcounts */
1373#define IL_MAX_HW_QUEUES 32
1374 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1375 /* for each AC */
1376 atomic_t queue_stop_count[4];
1377
1378 /* Indication if ieee80211_ops->open has been called */
1379 u8 is_open;
1380
1381 u8 mac80211_registered;
1382
1383 /* eeprom -- this is in the card's little endian byte order */
1384 u8 *eeprom;
1385 struct il_eeprom_calib_info *calib_info;
1386
1387 enum nl80211_iftype iw_mode;
1388
1389 /* Last Rx'd beacon timestamp */
1390 u64 timestamp;
1391
1392 union {
1393#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1394 struct {
1395 void *shared_virt;
1396 dma_addr_t shared_phys;
1397
1398 struct delayed_work thermal_periodic;
1399 struct delayed_work rfkill_poll;
1400
1401 struct il3945_notif_stats stats;
1402#ifdef CONFIG_IWLEGACY_DEBUGFS
1403 struct il3945_notif_stats accum_stats;
1404 struct il3945_notif_stats delta_stats;
1405 struct il3945_notif_stats max_delta;
1406#endif
1407
1408 u32 sta_supp_rates;
1409 int last_rx_rssi; /* From Rx packet stats */
1410
1411 /* Rx'd packet timing information */
1412 u32 last_beacon_time;
1413 u64 last_tsf;
1414
1415 /*
1416 * each calibration channel group in the
1417 * EEPROM has a derived clip setting for
1418 * each rate.
1419 */
1420 const struct il3945_clip_group clip_groups[5];
1421
1422 } _3945;
1423#endif
1424#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1425 struct {
1426 struct il_rx_phy_res last_phy_res;
1427 bool last_phy_res_valid;
1428
1429 struct completion firmware_loading_complete;
1430
1431 /*
1432 * chain noise reset and gain commands are the
1433 * two extra calibration commands follows the standard
1434 * phy calibration commands
1435 */
1436 u8 phy_calib_chain_noise_reset_cmd;
1437 u8 phy_calib_chain_noise_gain_cmd;
1438
1439 struct il_notif_stats stats;
1440#ifdef CONFIG_IWLEGACY_DEBUGFS
1441 struct il_notif_stats accum_stats;
1442 struct il_notif_stats delta_stats;
1443 struct il_notif_stats max_delta;
1444#endif
1445
1446 } _4965;
1447#endif
1448 };
1449
1450 struct il_hw_params hw_params;
1451
1452 u32 inta_mask;
1453
1454 struct workqueue_struct *workqueue;
1455
1456 struct work_struct restart;
1457 struct work_struct scan_completed;
1458 struct work_struct rx_replenish;
1459 struct work_struct abort_scan;
1460
1461 struct il_rxon_context *beacon_ctx;
1462 struct sk_buff *beacon_skb;
1463
1464 struct work_struct tx_flush;
1465
1466 struct tasklet_struct irq_tasklet;
1467
1468 struct delayed_work init_alive_start;
1469 struct delayed_work alive_start;
1470 struct delayed_work scan_check;
1471
1472 /* TX Power */
1473 s8 tx_power_user_lmt;
1474 s8 tx_power_device_lmt;
1475 s8 tx_power_next;
1476
1477
1478#ifdef CONFIG_IWLEGACY_DEBUG
1479 /* debugging info */
1480 u32 debug_level; /* per device debugging will override global
1481 il_debug_level if set */
1482#endif /* CONFIG_IWLEGACY_DEBUG */
1483#ifdef CONFIG_IWLEGACY_DEBUGFS
1484 /* debugfs */
1485 u16 tx_traffic_idx;
1486 u16 rx_traffic_idx;
1487 u8 *tx_traffic;
1488 u8 *rx_traffic;
1489 struct dentry *debugfs_dir;
1490 u32 dbgfs_sram_offset, dbgfs_sram_len;
1491 bool disable_ht40;
1492#endif /* CONFIG_IWLEGACY_DEBUGFS */
1493
1494 struct work_struct txpower_work;
1495 u32 disable_sens_cal;
1496 u32 disable_chain_noise_cal;
1497 u32 disable_tx_power_cal;
1498 struct work_struct run_time_calib_work;
1499 struct timer_list stats_periodic;
1500 struct timer_list watchdog;
1501 bool hw_ready;
1502
1503 struct led_classdev led;
1504 unsigned long blink_on, blink_off;
1505 bool led_registered;
1506}; /*il_priv */
1507
1508static inline void il_txq_ctx_activate(struct il_priv *il, int txq_id)
1509{
1510 set_bit(txq_id, &il->txq_ctx_active_msk);
1511}
1512
1513static inline void il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1514{
1515 clear_bit(txq_id, &il->txq_ctx_active_msk);
1516}
1517
1518#ifdef CONFIG_IWLEGACY_DEBUG
1519/*
1520 * il_get_debug_level: Return active debug level for device
1521 *
1522 * Using sysfs it is possible to set per device debug level. This debug
1523 * level will be used if set, otherwise the global debug level which can be
1524 * set via module parameter is used.
1525 */
1526static inline u32 il_get_debug_level(struct il_priv *il)
1527{
1528 if (il->debug_level)
1529 return il->debug_level;
1530 else
1531 return il_debug_level;
1532}
1533#else
1534static inline u32 il_get_debug_level(struct il_priv *il)
1535{
1536 return il_debug_level;
1537}
1538#endif
be663ab6 1539
be663ab6 1540
e94a4099
SG		 1541static inline struct ieee80211_hdr *
1542il_tx_queue_get_hdr(struct il_priv *il,
1543 int txq_id, int idx)
1544{
1545 if (il->txq[txq_id].txb[idx].skb)
1546 return (struct ieee80211_hdr *)il->txq[txq_id].
1547 txb[idx].skb->data;
1548 return NULL;
1549}
1550
1551static inline struct il_rxon_context *
1552il_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1553{
1554 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1555
1556 return vif_priv->ctx;
1557}
1558
1559#define for_each_context(il, _ctx) \
1560 for (_ctx = &il->ctx; _ctx == &il->ctx; _ctx++)
1561
1562static inline int il_is_associated(struct il_priv *il)
1563{
1564 return (il->ctx.active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1565}
1566
1567static inline int il_is_any_associated(struct il_priv *il)
1568{
1569 return il_is_associated(il);
1570}
1571
1572static inline int il_is_associated_ctx(struct il_rxon_context *ctx)
1573{
1574 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1575}
1576
1577static inline int il_is_channel_valid(const struct il_channel_info *ch_info)
1578{
1579 if (ch_info == NULL)
1580 return 0;
1581 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1582}
1583
1584static inline int il_is_channel_radar(const struct il_channel_info *ch_info)
1585{
1586 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1587}
1588
1589static inline u8 il_is_channel_a_band(const struct il_channel_info *ch_info)
1590{
1591 return ch_info->band == IEEE80211_BAND_5GHZ;
1592}
1593
1594static inline int
1595il_is_channel_passive(const struct il_channel_info *ch)
1596{
1597 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1598}
1599
1600static inline int
1601il_is_channel_ibss(const struct il_channel_info *ch)
1602{
1603 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1604}
be663ab6 1605
47ef694d 1606
e94a4099
SG		 1607static inline void
1608__il_free_pages(struct il_priv *il, struct page *page)
1609{
1610 __free_pages(page, il->hw_params.rx_page_order);
1611 il->alloc_rxb_page--;
1612}
1613
1614static inline void il_free_pages(struct il_priv *il, unsigned long page)
1615{
1616 free_pages(page, il->hw_params.rx_page_order);
1617 il->alloc_rxb_page--;
1618}
be663ab6
WYG		 1619
1620#define IWLWIFI_VERSION "in-tree:"
1621#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1622#define DRV_AUTHOR "<ilw@linux.intel.com>"
1623
e2ebc833 1624#define IL_PCI_DEVICE(dev, subdev, cfg) \
be663ab6
WYG		 1625 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1626 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1627 .driver_data = (kernel_ulong_t)&(cfg)
1628
1629#define TIME_UNIT 1024
1630
e2ebc833
SG		 1631#define IL_SKU_G 0x1
1632#define IL_SKU_A 0x2
1633#define IL_SKU_N 0x8
be663ab6 1634
e2ebc833 1635#define IL_CMD(x) case x: return #x
be663ab6 1636
e94a4099
SG		 1637/* Size of one Rx buffer in host DRAM */
1638#define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
1639#define IL_RX_BUF_SIZE_4K (4 * 1024)
1640#define IL_RX_BUF_SIZE_8K (8 * 1024)
1641
e2ebc833 1642struct il_hcmd_ops {
46bc8d4b
SG		 1643 int (*rxon_assoc)(struct il_priv *il, struct il_rxon_context *ctx);
1644 int (*commit_rxon)(struct il_priv *il, struct il_rxon_context *ctx);
1645 void (*set_rxon_chain)(struct il_priv *il,
e2ebc833 1646 struct il_rxon_context *ctx);
be663ab6
WYG		 1647};
1648
e2ebc833 1649struct il_hcmd_utils_ops {
be663ab6 1650 u16 (*get_hcmd_size)(u8 cmd_id, u16 len);
e2ebc833 1651 u16 (*build_addsta_hcmd)(const struct il_addsta_cmd *cmd,
be663ab6 1652 u8 *data);
46bc8d4b
SG		 1653 int (*request_scan)(struct il_priv *il, struct ieee80211_vif *vif);
1654 void (*post_scan)(struct il_priv *il);
be663ab6
WYG		 1655};
1656
e2ebc833 1657struct il_apm_ops {
46bc8d4b
SG		 1658 int (*init)(struct il_priv *il);
1659 void (*config)(struct il_priv *il);
be663ab6
WYG		 1660};
1661
e2ebc833 1662struct il_debugfs_ops {
be663ab6
WYG		 1663 ssize_t (*rx_stats_read)(struct file *file, char __user *user_buf,
1664 size_t count, loff_t *ppos);
1665 ssize_t (*tx_stats_read)(struct file *file, char __user *user_buf,
1666 size_t count, loff_t *ppos);
1667 ssize_t (*general_stats_read)(struct file *file, char __user *user_buf,
1668 size_t count, loff_t *ppos);
1669};
1670
e2ebc833 1671struct il_temp_ops {
46bc8d4b 1672 void (*temperature)(struct il_priv *il);
be663ab6
WYG		 1673};
1674
e2ebc833 1675struct il_lib_ops {
be663ab6 1676 /* set hw dependent parameters */
46bc8d4b 1677 int (*set_hw_params)(struct il_priv *il);
be663ab6 1678 /* Handling TX */
46bc8d4b 1679 void (*txq_update_byte_cnt_tbl)(struct il_priv *il,
e2ebc833 1680 struct il_tx_queue *txq,
be663ab6 1681 u16 byte_cnt);
46bc8d4b 1682 int (*txq_attach_buf_to_tfd)(struct il_priv *il,
e2ebc833 1683 struct il_tx_queue *txq,
be663ab6
WYG		 1684 dma_addr_t addr,
1685 u16 len, u8 reset, u8 pad);
46bc8d4b 1686 void (*txq_free_tfd)(struct il_priv *il,
e2ebc833 1687 struct il_tx_queue *txq);
46bc8d4b 1688 int (*txq_init)(struct il_priv *il,
e2ebc833 1689 struct il_tx_queue *txq);
be663ab6 1690 /* setup Rx handler */
d0c72347 1691 void (*handler_setup)(struct il_priv *il);
be663ab6 1692 /* alive notification after init uCode load */
46bc8d4b 1693 void (*init_alive_start)(struct il_priv *il);
be663ab6
WYG		 1694 /* check validity of rtc data address */
1695 int (*is_valid_rtc_data_addr)(u32 addr);
1696 /* 1st ucode load */
46bc8d4b 1697 int (*load_ucode)(struct il_priv *il);
1ba2f121 1698
46bc8d4b
SG		 1699 void (*dump_nic_error_log)(struct il_priv *il);
1700 int (*dump_fh)(struct il_priv *il, char **buf, bool display);
1701 int (*set_channel_switch)(struct il_priv *il,
be663ab6
WYG		 1702 struct ieee80211_channel_switch *ch_switch);
1703 /* power management */
e2ebc833 1704 struct il_apm_ops apm_ops;
be663ab6
WYG		 1705
1706 /* power */
46bc8d4b
SG		 1707 int (*send_tx_power) (struct il_priv *il);
1708 void (*update_chain_flags)(struct il_priv *il);
be663ab6 1709
47ef694d 1710 /* eeprom operations */
e2ebc833 1711 struct il_eeprom_ops eeprom_ops;
be663ab6
WYG		 1712
1713 /* temperature */
e2ebc833 1714 struct il_temp_ops temp_ops;
be663ab6 1715
e2ebc833 1716 struct il_debugfs_ops debugfs_ops;
be663ab6
WYG		 1717
1718};
1719
e2ebc833 1720struct il_led_ops {
46bc8d4b 1721 int (*cmd)(struct il_priv *il, struct il_led_cmd *led_cmd);
be663ab6
WYG		 1722};
1723
e2ebc833 1724struct il_legacy_ops {
46bc8d4b
SG		 1725 void (*post_associate)(struct il_priv *il);
1726 void (*config_ap)(struct il_priv *il);
be663ab6 1727 /* station management */
46bc8d4b
SG		 1728 int (*update_bcast_stations)(struct il_priv *il);
1729 int (*manage_ibss_station)(struct il_priv *il,
be663ab6
WYG		 1730 struct ieee80211_vif *vif, bool add);
1731};
1732
e2ebc833
SG		 1733struct il_ops {
1734 const struct il_lib_ops *lib;
1735 const struct il_hcmd_ops *hcmd;
1736 const struct il_hcmd_utils_ops *utils;
1737 const struct il_led_ops *led;
1738 const struct il_nic_ops *nic;
1739 const struct il_legacy_ops *legacy;
be663ab6
WYG		 1740 const struct ieee80211_ops *ieee80211_ops;
1741};
1742
e2ebc833 1743struct il_mod_params {
be663ab6
WYG		 1744 int sw_crypto; /* def: 0 = using hardware encryption */
1745 int disable_hw_scan; /* def: 0 = use h/w scan */
1746 int num_of_queues; /* def: HW dependent */
1747 int disable_11n; /* def: 0 = 11n capabilities enabled */
1748 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
1749 int antenna; /* def: 0 = both antennas (use diversity) */
1750 int restart_fw; /* def: 1 = restart firmware */
1751};
1752
1753/*
1754 * @led_compensation: compensate on the led on/off time per HW according
1755 * to the deviation to achieve the desired led frequency.
47ef694d 1756 * The detail algorithm is described in common.c
be663ab6 1757 * @chain_noise_num_beacons: number of beacons used to compute chain noise
be663ab6
WYG		 1758 * @wd_timeout: TX queues watchdog timeout
1759 * @temperature_kelvin: temperature report by uCode in kelvin
be663ab6
WYG		 1760 * @ucode_tracing: support ucode continuous tracing
1761 * @sensitivity_calib_by_driver: driver has the capability to perform
1762 * sensitivity calibration operation
1763 * @chain_noise_calib_by_driver: driver has the capability to perform
1764 * chain noise calibration operation
1765 */
e2ebc833 1766struct il_base_params {
be663ab6
WYG		 1767 int eeprom_size;
1768 int num_of_queues; /* def: HW dependent */
1769 int num_of_ampdu_queues;/* def: HW dependent */
e2ebc833 1770 /* for il_apm_init() */
be663ab6
WYG		 1771 u32 pll_cfg_val;
1772 bool set_l0s;
1773 bool use_bsm;
1774
1775 u16 led_compensation;
1776 int chain_noise_num_beacons;
be663ab6
WYG		 1777 unsigned int wd_timeout;
1778 bool temperature_kelvin;
be663ab6
WYG		 1779 const bool ucode_tracing;
1780 const bool sensitivity_calib_by_driver;
1781 const bool chain_noise_calib_by_driver;
1782};
1783
47ef694d
SG		 1784#define IL_LED_SOLID 11
1785#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1786
1787#define IL_LED_ACTIVITY (0<<1)
1788#define IL_LED_LINK (1<<1)
1789
1790/*
1791 * LED mode
1792 * IL_LED_DEFAULT: use device default
1793 * IL_LED_RF_STATE: turn LED on/off based on RF state
1794 * LED ON = RF ON
1795 * LED OFF = RF OFF
1796 * IL_LED_BLINK: adjust led blink rate based on blink table
1797 */
1798enum il_led_mode {
1799 IL_LED_DEFAULT,
1800 IL_LED_RF_STATE,
1801 IL_LED_BLINK,
1802};
1803
1804void il_leds_init(struct il_priv *il);
1805void il_leds_exit(struct il_priv *il);
1806
be663ab6 1807/**
e2ebc833 1808 * struct il_cfg
be663ab6
WYG		 1809 * @fw_name_pre: Firmware filename prefix. The api version and extension
1810 * (.ucode) will be added to filename before loading from disk. The
1811 * filename is constructed as fw_name_pre<api>.ucode.
1812 * @ucode_api_max: Highest version of uCode API supported by driver.
1813 * @ucode_api_min: Lowest version of uCode API supported by driver.
1814 * @scan_antennas: available antenna for scan operation
1815 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1816 *
1817 * We enable the driver to be backward compatible wrt API version. The
1818 * driver specifies which APIs it supports (with @ucode_api_max being the
1819 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1820 * it has a supported API version. The firmware's API version will be
e2ebc833 1821 * stored in @il_priv, enabling the driver to make runtime changes based
be663ab6
WYG		 1822 * on firmware version used.
1823 *
1824 * For example,
46bc8d4b 1825 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
be663ab6
WYG		 1826 * Driver interacts with Firmware API version >= 2.
1827 * } else {
1828 * Driver interacts with Firmware API version 1.
1829 * }
1830 *
1831 * The ideal usage of this infrastructure is to treat a new ucode API
1832 * release as a new hardware revision. That is, through utilizing the
e2ebc833 1833 * il_hcmd_utils_ops etc. we accommodate different command structures
be663ab6
WYG		 1834 * and flows between hardware versions as well as their API
1835 * versions.
1836 *
1837 */
e2ebc833 1838struct il_cfg {
be663ab6
WYG		 1839 /* params specific to an individual device within a device family */
1840 const char *name;
1841 const char *fw_name_pre;
1842 const unsigned int ucode_api_max;
1843 const unsigned int ucode_api_min;
1844 u8 valid_tx_ant;
1845 u8 valid_rx_ant;
1846 unsigned int sku;
1847 u16 eeprom_ver;
1848 u16 eeprom_calib_ver;
e2ebc833 1849 const struct il_ops *ops;
be663ab6 1850 /* module based parameters which can be set from modprobe cmd */
e2ebc833 1851 const struct il_mod_params *mod_params;
be663ab6 1852 /* params not likely to change within a device family */
e2ebc833 1853 struct il_base_params *base_params;
be663ab6
WYG		 1854 /* params likely to change within a device family */
1855 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
e2ebc833 1856 enum il_led_mode led_mode;
be663ab6
WYG		 1857};
1858
1859/***************************
1860 * L i b *
1861 ***************************/
1862
e2ebc833
SG		 1863struct ieee80211_hw *il_alloc_all(struct il_cfg *cfg);
1864int il_mac_conf_tx(struct ieee80211_hw *hw,
8a3a3c85 1865 struct ieee80211_vif *vif, u16 queue,
be663ab6 1866 const struct ieee80211_tx_queue_params *params);
e2ebc833 1867int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
46bc8d4b 1868void il_set_rxon_hwcrypto(struct il_priv *il,
e2ebc833 1869 struct il_rxon_context *ctx,
be663ab6 1870 int hw_decrypt);
46bc8d4b 1871int il_check_rxon_cmd(struct il_priv *il,
e2ebc833 1872 struct il_rxon_context *ctx);
46bc8d4b 1873int il_full_rxon_required(struct il_priv *il,
e2ebc833 1874 struct il_rxon_context *ctx);
46bc8d4b 1875int il_set_rxon_channel(struct il_priv *il,
be663ab6 1876 struct ieee80211_channel *ch,
e2ebc833 1877 struct il_rxon_context *ctx);
46bc8d4b 1878void il_set_flags_for_band(struct il_priv *il,
e2ebc833 1879 struct il_rxon_context *ctx,
be663ab6
WYG		 1880 enum ieee80211_band band,
1881 struct ieee80211_vif *vif);
46bc8d4b 1882u8 il_get_single_channel_number(struct il_priv *il,
be663ab6 1883 enum ieee80211_band band);
46bc8d4b 1884void il_set_rxon_ht(struct il_priv *il,
e2ebc833 1885 struct il_ht_config *ht_conf);
46bc8d4b 1886bool il_is_ht40_tx_allowed(struct il_priv *il,
e2ebc833 1887 struct il_rxon_context *ctx,
be663ab6 1888 struct ieee80211_sta_ht_cap *ht_cap);
46bc8d4b 1889void il_connection_init_rx_config(struct il_priv *il,
e2ebc833 1890 struct il_rxon_context *ctx);
46bc8d4b
SG		 1891void il_set_rate(struct il_priv *il);
1892int il_set_decrypted_flag(struct il_priv *il,
be663ab6
WYG		 1893 struct ieee80211_hdr *hdr,
1894 u32 decrypt_res,
1895 struct ieee80211_rx_status *stats);
46bc8d4b 1896void il_irq_handle_error(struct il_priv *il);
e2ebc833 1897int il_mac_add_interface(struct ieee80211_hw *hw,
be663ab6 1898 struct ieee80211_vif *vif);
e2ebc833 1899void il_mac_remove_interface(struct ieee80211_hw *hw,
be663ab6 1900 struct ieee80211_vif *vif);
e2ebc833 1901int il_mac_change_interface(struct ieee80211_hw *hw,
be663ab6
WYG		 1902 struct ieee80211_vif *vif,
1903 enum nl80211_iftype newtype, bool newp2p);
46bc8d4b
SG		 1904int il_alloc_txq_mem(struct il_priv *il);
1905void il_txq_mem(struct il_priv *il);
be663ab6 1906
d3175167 1907#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b
SG		 1908int il_alloc_traffic_mem(struct il_priv *il);
1909void il_free_traffic_mem(struct il_priv *il);
1910void il_reset_traffic_log(struct il_priv *il);
1911void il_dbg_log_tx_data_frame(struct il_priv *il,
be663ab6 1912 u16 length, struct ieee80211_hdr *header);
46bc8d4b 1913void il_dbg_log_rx_data_frame(struct il_priv *il,
be663ab6 1914 u16 length, struct ieee80211_hdr *header);
e2ebc833
SG		 1915const char *il_get_mgmt_string(int cmd);
1916const char *il_get_ctrl_string(int cmd);
46bc8d4b
SG		 1917void il_clear_traffic_stats(struct il_priv *il);
1918void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc,
be663ab6
WYG		 1919 u16 len);
1920#else
46bc8d4b 1921static inline int il_alloc_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1922{
1923 return 0;
1924}
46bc8d4b 1925static inline void il_free_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1926{
1927}
46bc8d4b 1928static inline void il_reset_traffic_log(struct il_priv *il)
be663ab6
WYG		 1929{
1930}
46bc8d4b 1931static inline void il_dbg_log_tx_data_frame(struct il_priv *il,
be663ab6
WYG		 1932 u16 length, struct ieee80211_hdr *header)
1933{
1934}
46bc8d4b 1935static inline void il_dbg_log_rx_data_frame(struct il_priv *il,
be663ab6
WYG		 1936 u16 length, struct ieee80211_hdr *header)
1937{
1938}
46bc8d4b 1939static inline void il_update_stats(struct il_priv *il, bool is_tx,
be663ab6
WYG		 1940 __le16 fc, u16 len)
1941{
1942}
1943#endif
1944/*****************************************************
1945 * RX handlers.
1946 * **************************************************/
d2dfb33e 1947void il_hdl_pm_sleep(struct il_priv *il,
b73bb5f1 1948 struct il_rx_buf *rxb);
d2dfb33e 1949void il_hdl_pm_debug_stats(struct il_priv *il,
b73bb5f1 1950 struct il_rx_buf *rxb);
6e9848b4 1951void il_hdl_error(struct il_priv *il,
b73bb5f1 1952 struct il_rx_buf *rxb);
be663ab6
WYG		 1953
1954/*****************************************************
1955* RX
1956******************************************************/
46bc8d4b
SG		 1957void il_cmd_queue_unmap(struct il_priv *il);
1958void il_cmd_queue_free(struct il_priv *il);
1959int il_rx_queue_alloc(struct il_priv *il);
1960void il_rx_queue_update_write_ptr(struct il_priv *il,
e2ebc833
SG		 1961 struct il_rx_queue *q);
1962int il_rx_queue_space(const struct il_rx_queue *q);
46bc8d4b 1963void il_tx_cmd_complete(struct il_priv *il,
b73bb5f1 1964 struct il_rx_buf *rxb);
be663ab6 1965/* Handlers */
d2dfb33e 1966void il_hdl_spectrum_measurement(struct il_priv *il,
b73bb5f1 1967 struct il_rx_buf *rxb);
ebf0d90d 1968void il_recover_from_stats(struct il_priv *il,
dcae1c64 1969 struct il_rx_pkt *pkt);
46bc8d4b 1970void il_chswitch_done(struct il_priv *il, bool is_success);
d2dfb33e 1971void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1972
1973/* TX helpers */
1974
1975/*****************************************************
1976* TX
1977******************************************************/
46bc8d4b 1978void il_txq_update_write_ptr(struct il_priv *il,
e2ebc833 1979 struct il_tx_queue *txq);
46bc8d4b 1980int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq,
be663ab6 1981 int slots_num, u32 txq_id);
46bc8d4b 1982void il_tx_queue_reset(struct il_priv *il,
e2ebc833 1983 struct il_tx_queue *txq,
be663ab6 1984 int slots_num, u32 txq_id);
46bc8d4b
SG		 1985void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1986void il_tx_queue_free(struct il_priv *il, int txq_id);
1987void il_setup_watchdog(struct il_priv *il);
be663ab6
WYG		 1988/*****************************************************
1989 * TX power
1990 ****************************************************/
46bc8d4b 1991int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
be663ab6
WYG		 1992
1993/*******************************************************************************
1994 * Rate
1995 ******************************************************************************/
1996
46bc8d4b 1997u8 il_get_lowest_plcp(struct il_priv *il,
e2ebc833 1998 struct il_rxon_context *ctx);
be663ab6
WYG		 1999
2000/*******************************************************************************
2001 * Scanning
2002 ******************************************************************************/
46bc8d4b
SG		 2003void il_init_scan_params(struct il_priv *il);
2004int il_scan_cancel(struct il_priv *il);
2005int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
2006void il_force_scan_end(struct il_priv *il);
e2ebc833 2007int il_mac_hw_scan(struct ieee80211_hw *hw,
be663ab6
WYG		 2008 struct ieee80211_vif *vif,
2009 struct cfg80211_scan_request *req);
46bc8d4b
SG		 2010void il_internal_short_hw_scan(struct il_priv *il);
2011int il_force_reset(struct il_priv *il, bool external);
2012u16 il_fill_probe_req(struct il_priv *il,
be663ab6
WYG		 2013 struct ieee80211_mgmt *frame,
2014 const u8 *ta, const u8 *ie, int ie_len, int left);
46bc8d4b
SG		 2015void il_setup_rx_scan_handlers(struct il_priv *il);
2016u16 il_get_active_dwell_time(struct il_priv *il,
be663ab6
WYG		 2017 enum ieee80211_band band,
2018 u8 n_probes);
46bc8d4b 2019u16 il_get_passive_dwell_time(struct il_priv *il,
be663ab6
WYG		 2020 enum ieee80211_band band,
2021 struct ieee80211_vif *vif);
46bc8d4b
SG		 2022void il_setup_scan_deferred_work(struct il_priv *il);
2023void il_cancel_scan_deferred_work(struct il_priv *il);
be663ab6
WYG		 2024
2025/* For faster active scanning, scan will move to the next channel if fewer than
2026 * PLCP_QUIET_THRESH packets are heard on this channel within
2027 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
2028 * time if it's a quiet channel (nothing responded to our probe, and there's
2029 * no other traffic).
2030 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
e2ebc833
SG		 2031#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
2032#define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
be663ab6 2033
e2ebc833 2034#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
be663ab6
WYG		 2035
2036/*****************************************************
2037 * S e n d i n g H o s t C o m m a n d s *
2038 *****************************************************/
2039
e2ebc833 2040const char *il_get_cmd_string(u8 cmd);
46bc8d4b 2041int __must_check il_send_cmd_sync(struct il_priv *il,
e2ebc833 2042 struct il_host_cmd *cmd);
46bc8d4b
SG		 2043int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
2044int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id,
be663ab6 2045 u16 len, const void *data);
46bc8d4b 2046int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len,
be663ab6 2047 const void *data,
46bc8d4b 2048 void (*callback)(struct il_priv *il,
e2ebc833 2049 struct il_device_cmd *cmd,
dcae1c64 2050 struct il_rx_pkt *pkt));
be663ab6 2051
46bc8d4b 2052int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
be663ab6
WYG		 2053
2054
2055/*****************************************************
2056 * PCI *
2057 *****************************************************/
2058
46bc8d4b 2059static inline u16 il_pcie_link_ctl(struct il_priv *il)
be663ab6
WYG		 2060{
2061 int pos;
2062 u16 pci_lnk_ctl;
46bc8d4b
SG		 2063 pos = pci_pcie_cap(il->pci_dev);
2064 pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
be663ab6
WYG		 2065 return pci_lnk_ctl;
2066}
2067
e2ebc833 2068void il_bg_watchdog(unsigned long data);
46bc8d4b 2069u32 il_usecs_to_beacons(struct il_priv *il,
be663ab6 2070 u32 usec, u32 beacon_interval);
46bc8d4b 2071__le32 il_add_beacon_time(struct il_priv *il, u32 base,
be663ab6
WYG		 2072 u32 addon, u32 beacon_interval);
2073
2074#ifdef CONFIG_PM
e2ebc833
SG		 2075int il_pci_suspend(struct device *device);
2076int il_pci_resume(struct device *device);
2077extern const struct dev_pm_ops il_pm_ops;
be663ab6 2078
e2ebc833 2079#define IL_LEGACY_PM_OPS (&il_pm_ops)
be663ab6
WYG		 2080
2081#else /* !CONFIG_PM */
2082
e2ebc833 2083#define IL_LEGACY_PM_OPS NULL
be663ab6
WYG		 2084
2085#endif /* !CONFIG_PM */
2086
2087/*****************************************************
2088* Error Handling Debugging
2089******************************************************/
46bc8d4b 2090void il4965_dump_nic_error_log(struct il_priv *il);
d3175167 2091#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 2092void il_print_rx_config_cmd(struct il_priv *il,
e2ebc833 2093 struct il_rxon_context *ctx);
be663ab6 2094#else
46bc8d4b 2095static inline void il_print_rx_config_cmd(struct il_priv *il,
e2ebc833 2096 struct il_rxon_context *ctx)
be663ab6
WYG		 2097{
2098}
2099#endif
2100
46bc8d4b 2101void il_clear_isr_stats(struct il_priv *il);
be663ab6
WYG		 2102
2103/*****************************************************
2104* GEOS
2105******************************************************/
46bc8d4b
SG		 2106int il_init_geos(struct il_priv *il);
2107void il_free_geos(struct il_priv *il);
be663ab6
WYG		 2108
2109/*************** DRIVER STATUS FUNCTIONS *****/
2110
a6766ccd
SG		 2111#define S_HCMD_ACTIVE 0 /* host command in progress */
2112/* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
2113#define S_INT_ENABLED 2
2114#define S_RF_KILL_HW 3
2115#define S_CT_KILL 4
2116#define S_INIT 5
2117#define S_ALIVE 6
2118#define S_READY 7
2119#define S_TEMPERATURE 8
2120#define S_GEO_CONFIGURED 9
2121#define S_EXIT_PENDING 10
db7746f7 2122#define S_STATS 12
a6766ccd
SG		 2123#define S_SCANNING 13
2124#define S_SCAN_ABORTING 14
2125#define S_SCAN_HW 15
2126#define S_POWER_PMI 16
2127#define S_FW_ERROR 17
2128#define S_CHANNEL_SWITCH_PENDING 18
be663ab6 2129
46bc8d4b 2130static inline int il_is_ready(struct il_priv *il)
be663ab6
WYG		 2131{
2132 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
2133 * set but EXIT_PENDING is not */
a6766ccd
SG		 2134 return test_bit(S_READY, &il->status) &&
2135 test_bit(S_GEO_CONFIGURED, &il->status) &&
2136 !test_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 2137}
2138
46bc8d4b 2139static inline int il_is_alive(struct il_priv *il)
be663ab6 2140{
a6766ccd 2141 return test_bit(S_ALIVE, &il->status);
be663ab6
WYG		 2142}
2143
46bc8d4b 2144static inline int il_is_init(struct il_priv *il)
be663ab6 2145{
a6766ccd 2146 return test_bit(S_INIT, &il->status);
be663ab6
WYG		 2147}
2148
46bc8d4b 2149static inline int il_is_rfkill_hw(struct il_priv *il)
be663ab6 2150{
a6766ccd 2151 return test_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 2152}
2153
46bc8d4b 2154static inline int il_is_rfkill(struct il_priv *il)
be663ab6 2155{
46bc8d4b 2156 return il_is_rfkill_hw(il);
be663ab6
WYG		 2157}
2158
46bc8d4b 2159static inline int il_is_ctkill(struct il_priv *il)
be663ab6 2160{
a6766ccd 2161 return test_bit(S_CT_KILL, &il->status);
be663ab6
WYG		 2162}
2163
46bc8d4b 2164static inline int il_is_ready_rf(struct il_priv *il)
be663ab6
WYG		 2165{
2166
46bc8d4b 2167 if (il_is_rfkill(il))
be663ab6
WYG		 2168 return 0;
2169
46bc8d4b 2170 return il_is_ready(il);
be663ab6
WYG		 2171}
2172
46bc8d4b 2173extern void il_send_bt_config(struct il_priv *il);
ebf0d90d 2174extern int il_send_stats_request(struct il_priv *il,
be663ab6 2175 u8 flags, bool clear);
46bc8d4b
SG		 2176void il_apm_stop(struct il_priv *il);
2177int il_apm_init(struct il_priv *il);
be663ab6 2178
46bc8d4b 2179int il_send_rxon_timing(struct il_priv *il,
e2ebc833 2180 struct il_rxon_context *ctx);
46bc8d4b 2181static inline int il_send_rxon_assoc(struct il_priv *il,
e2ebc833 2182 struct il_rxon_context *ctx)
be663ab6 2183{
46bc8d4b 2184 return il->cfg->ops->hcmd->rxon_assoc(il, ctx);
be663ab6 2185}
46bc8d4b 2186static inline int il_commit_rxon(struct il_priv *il,
e2ebc833 2187 struct il_rxon_context *ctx)
be663ab6 2188{
46bc8d4b 2189 return il->cfg->ops->hcmd->commit_rxon(il, ctx);
be663ab6 2190}
e2ebc833 2191static inline const struct ieee80211_supported_band *il_get_hw_mode(
46bc8d4b 2192 struct il_priv *il, enum ieee80211_band band)
be663ab6 2193{
46bc8d4b 2194 return il->hw->wiphy->bands[band];
be663ab6
WYG		 2195}
2196
be663ab6 2197/* mac80211 handlers */
e2ebc833
SG		 2198int il_mac_config(struct ieee80211_hw *hw, u32 changed);
2199void il_mac_reset_tsf(struct ieee80211_hw *hw,
37a41b4a 2200 struct ieee80211_vif *vif);
e2ebc833 2201void il_mac_bss_info_changed(struct ieee80211_hw *hw,
be663ab6
WYG		 2202 struct ieee80211_vif *vif,
2203 struct ieee80211_bss_conf *bss_conf,
2204 u32 changes);
46bc8d4b 2205void il_tx_cmd_protection(struct il_priv *il,
be663ab6
WYG		 2206 struct ieee80211_tx_info *info,
2207 __le16 fc, __le32 *tx_flags);
2208
e2ebc833 2209irqreturn_t il_isr(int irq, void *data);
be663ab6 2210
e94a4099
SG		 2211
2212#include <linux/io.h>
2213
2214static inline void _il_write8(struct il_priv *il, u32 ofs, u8 val)
2215{
2216 iowrite8(val, il->hw_base + ofs);
2217}
2218#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2219
2220static inline void _il_wr(struct il_priv *il, u32 ofs, u32 val)
2221{
2222 iowrite32(val, il->hw_base + ofs);
2223}
2224
2225static inline u32 _il_rd(struct il_priv *il, u32 ofs)
2226{
2227 return ioread32(il->hw_base + ofs);
2228}
2229
2230#define IL_POLL_INTERVAL 10 /* microseconds */
2231static inline int
2232_il_poll_bit(struct il_priv *il, u32 addr,
2233 u32 bits, u32 mask, int timeout)
2234{
2235 int t = 0;
2236
2237 do {
2238 if ((_il_rd(il, addr) & mask) == (bits & mask))
2239 return t;
2240 udelay(IL_POLL_INTERVAL);
2241 t += IL_POLL_INTERVAL;
2242 } while (t < timeout);
2243
2244 return -ETIMEDOUT;
2245}
2246
2247static inline void _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2248{
2249 _il_wr(il, reg, _il_rd(il, reg) | mask);
2250}
2251
2252static inline void il_set_bit(struct il_priv *p, u32 r, u32 m)
2253{
2254 unsigned long reg_flags;
2255
2256 spin_lock_irqsave(&p->reg_lock, reg_flags);
2257 _il_set_bit(p, r, m);
2258 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
2259}
2260
2261static inline void
2262_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2263{
2264 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2265}
2266
2267static inline void il_clear_bit(struct il_priv *p, u32 r, u32 m)
2268{
2269 unsigned long reg_flags;
2270
2271 spin_lock_irqsave(&p->reg_lock, reg_flags);
2272 _il_clear_bit(p, r, m);
2273 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
2274}
2275
2276static inline int _il_grab_nic_access(struct il_priv *il)
2277{
2278 int ret;
2279 u32 val;
2280
2281 /* this bit wakes up the NIC */
2282 _il_set_bit(il, CSR_GP_CNTRL,
2283 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2284
2285 /*
2286 * These bits say the device is running, and should keep running for
2287 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2288 * but they do not indicate that embedded SRAM is restored yet;
2289 * 3945 and 4965 have volatile SRAM, and must save/restore contents
2290 * to/from host DRAM when sleeping/waking for power-saving.
2291 * Each direction takes approximately 1/4 millisecond; with this
2292 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2293 * series of register accesses are expected (e.g. reading Event Log),
2294 * to keep device from sleeping.
2295 *
2296 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2297 * SRAM is okay/restored. We don't check that here because this call
2298 * is just for hardware register access; but GP1 MAC_SLEEP check is a
2299 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
2300 *
2301 */
2302 ret = _il_poll_bit(il, CSR_GP_CNTRL,
2303 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2304 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2305 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2306 if (ret < 0) {
2307 val = _il_rd(il, CSR_GP_CNTRL);
2308 IL_ERR(
2309 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
2310 _il_wr(il, CSR_RESET,
2311 CSR_RESET_REG_FLAG_FORCE_NMI);
2312 return -EIO;
2313 }
2314
2315 return 0;
2316}
2317
2318static inline void _il_release_nic_access(struct il_priv *il)
2319{
2320 _il_clear_bit(il, CSR_GP_CNTRL,
2321 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2322}
2323
2324static inline u32 il_rd(struct il_priv *il, u32 reg)
2325{
2326 u32 value;
2327 unsigned long reg_flags;
2328
2329 spin_lock_irqsave(&il->reg_lock, reg_flags);
2330 _il_grab_nic_access(il);
2331 value = _il_rd(il, reg);
2332 _il_release_nic_access(il);
2333 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2334 return value;
2335
2336}
2337
2338static inline void
2339il_wr(struct il_priv *il, u32 reg, u32 value)
2340{
2341 unsigned long reg_flags;
2342
2343 spin_lock_irqsave(&il->reg_lock, reg_flags);
2344 if (!_il_grab_nic_access(il)) {
2345 _il_wr(il, reg, value);
2346 _il_release_nic_access(il);
2347 }
2348 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2349}
2350
2351static inline void il_write_reg_buf(struct il_priv *il,
2352 u32 reg, u32 len, u32 *values)
2353{
2354 u32 count = sizeof(u32);
2355
2356 if (il != NULL && values != NULL) {
2357 for (; 0 < len; len -= count, reg += count, values++)
2358 il_wr(il, reg, *values);
2359 }
2360}
2361
2362static inline int il_poll_bit(struct il_priv *il, u32 addr,
2363 u32 mask, int timeout)
2364{
2365 int t = 0;
2366
2367 do {
2368 if ((il_rd(il, addr) & mask) == mask)
2369 return t;
2370 udelay(IL_POLL_INTERVAL);
2371 t += IL_POLL_INTERVAL;
2372 } while (t < timeout);
2373
2374 return -ETIMEDOUT;
2375}
2376
2377static inline u32 _il_rd_prph(struct il_priv *il, u32 reg)
2378{
2379 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2380 rmb();
2381 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2382}
2383
2384static inline u32 il_rd_prph(struct il_priv *il, u32 reg)
2385{
2386 unsigned long reg_flags;
2387 u32 val;
2388
2389 spin_lock_irqsave(&il->reg_lock, reg_flags);
2390 _il_grab_nic_access(il);
2391 val = _il_rd_prph(il, reg);
2392 _il_release_nic_access(il);
2393 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2394 return val;
2395}
2396
2397static inline void _il_wr_prph(struct il_priv *il,
2398 u32 addr, u32 val)
2399{
2400 _il_wr(il, HBUS_TARG_PRPH_WADDR,
2401 ((addr & 0x0000FFFF) | (3 << 24)));
2402 wmb();
2403 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2404}
2405
2406static inline void
2407il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2408{
2409 unsigned long reg_flags;
2410
2411 spin_lock_irqsave(&il->reg_lock, reg_flags);
2412 if (!_il_grab_nic_access(il)) {
2413 _il_wr_prph(il, addr, val);
2414 _il_release_nic_access(il);
2415 }
2416 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2417}
2418
2419#define _il_set_bits_prph(il, reg, mask) \
2420_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask))
2421
2422static inline void
2423il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2424{
2425 unsigned long reg_flags;
2426
2427 spin_lock_irqsave(&il->reg_lock, reg_flags);
2428 _il_grab_nic_access(il);
2429 _il_set_bits_prph(il, reg, mask);
2430 _il_release_nic_access(il);
2431 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2432}
2433
2434#define _il_set_bits_mask_prph(il, reg, bits, mask) \
2435_il_wr_prph(il, reg, \
2436 ((_il_rd_prph(il, reg) & mask) | bits))
2437
2438static inline void il_set_bits_mask_prph(struct il_priv *il, u32 reg,
2439 u32 bits, u32 mask)
2440{
2441 unsigned long reg_flags;
2442
2443 spin_lock_irqsave(&il->reg_lock, reg_flags);
2444 _il_grab_nic_access(il);
2445 _il_set_bits_mask_prph(il, reg, bits, mask);
2446 _il_release_nic_access(il);
2447 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2448}
2449
2450static inline void il_clear_bits_prph(struct il_priv
2451 *il, u32 reg, u32 mask)
2452{
2453 unsigned long reg_flags;
2454 u32 val;
2455
2456 spin_lock_irqsave(&il->reg_lock, reg_flags);
2457 _il_grab_nic_access(il);
2458 val = _il_rd_prph(il, reg);
2459 _il_wr_prph(il, reg, (val & ~mask));
2460 _il_release_nic_access(il);
2461 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2462}
2463
2464static inline u32 il_read_targ_mem(struct il_priv *il, u32 addr)
2465{
2466 unsigned long reg_flags;
2467 u32 value;
2468
2469 spin_lock_irqsave(&il->reg_lock, reg_flags);
2470 _il_grab_nic_access(il);
2471
2472 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
2473 rmb();
2474 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
2475
2476 _il_release_nic_access(il);
2477 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2478 return value;
2479}
2480
2481static inline void
2482il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
2483{
2484 unsigned long reg_flags;
2485
2486 spin_lock_irqsave(&il->reg_lock, reg_flags);
2487 if (!_il_grab_nic_access(il)) {
2488 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
2489 wmb();
2490 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
2491 _il_release_nic_access(il);
2492 }
2493 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2494}
2495
2496static inline void
2497il_write_targ_mem_buf(struct il_priv *il, u32 addr,
2498 u32 len, u32 *values)
2499{
2500 unsigned long reg_flags;
2501
2502 spin_lock_irqsave(&il->reg_lock, reg_flags);
2503 if (!_il_grab_nic_access(il)) {
2504 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
2505 wmb();
2506 for (; 0 < len; len -= sizeof(u32), values++)
2507 _il_wr(il,
2508 HBUS_TARG_MEM_WDAT, *values);
2509
2510 _il_release_nic_access(il);
2511 }
2512 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2513}
2514
2515#define HW_KEY_DYNAMIC 0
2516#define HW_KEY_DEFAULT 1
2517
2518#define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2519#define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2520#define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2521 being activated */
2522#define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2523 (this is for the IBSS BSSID stations) */
2524#define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
2525
2526
2527void il_restore_stations(struct il_priv *il,
2528 struct il_rxon_context *ctx);
2529void il_clear_ucode_stations(struct il_priv *il,
2530 struct il_rxon_context *ctx);
2531void il_dealloc_bcast_stations(struct il_priv *il);
2532int il_get_free_ucode_key_idx(struct il_priv *il);
2533int il_send_add_sta(struct il_priv *il,
2534 struct il_addsta_cmd *sta, u8 flags);
2535int il_add_station_common(struct il_priv *il,
2536 struct il_rxon_context *ctx,
2537 const u8 *addr, bool is_ap,
2538 struct ieee80211_sta *sta, u8 *sta_id_r);
2539int il_remove_station(struct il_priv *il,
2540 const u8 sta_id,
2541 const u8 *addr);
2542int il_mac_sta_remove(struct ieee80211_hw *hw,
2543 struct ieee80211_vif *vif,
2544 struct ieee80211_sta *sta);
2545
2546u8 il_prep_station(struct il_priv *il,
2547 struct il_rxon_context *ctx,
2548 const u8 *addr, bool is_ap,
2549 struct ieee80211_sta *sta);
2550
2551int il_send_lq_cmd(struct il_priv *il,
2552 struct il_rxon_context *ctx,
2553 struct il_link_quality_cmd *lq,
2554 u8 flags, bool init);
2555
2556/**
2557 * il_clear_driver_stations - clear knowledge of all stations from driver
2558 * @il: iwl il struct
2559 *
2560 * This is called during il_down() to make sure that in the case
2561 * we're coming there from a hardware restart mac80211 will be
2562 * able to reconfigure stations -- if we're getting there in the
2563 * normal down flow then the stations will already be cleared.
2564 */
2565static inline void il_clear_driver_stations(struct il_priv *il)
2566{
2567 unsigned long flags;
2568 struct il_rxon_context *ctx = &il->ctx;
2569
2570 spin_lock_irqsave(&il->sta_lock, flags);
2571 memset(il->stations, 0, sizeof(il->stations));
2572 il->num_stations = 0;
2573
2574 il->ucode_key_table = 0;
2575
2576 /*
2577 * Remove all key information that is not stored as part
2578 * of station information since mac80211 may not have had
2579 * a chance to remove all the keys. When device is
2580 * reconfigured by mac80211 after an error all keys will
2581 * be reconfigured.
2582 */
2583 memset(ctx->wep_keys, 0, sizeof(ctx->wep_keys));
2584 ctx->key_mapping_keys = 0;
2585
2586 spin_unlock_irqrestore(&il->sta_lock, flags);
2587}
2588
2589static inline int il_sta_id(struct ieee80211_sta *sta)
2590{
2591 if (WARN_ON(!sta))
2592 return IL_INVALID_STATION;
2593
2594 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2595}
2596
2597/**
2598 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2599 * @il: iwl il
2600 * @context: the current context
2601 * @sta: mac80211 station
2602 *
2603 * In certain circumstances mac80211 passes a station pointer
2604 * that may be %NULL, for example during TX or key setup. In
2605 * that case, we need to use the broadcast station, so this
2606 * inline wraps that pattern.
2607 */
2608static inline int il_sta_id_or_broadcast(struct il_priv *il,
2609 struct il_rxon_context *context,
2610 struct ieee80211_sta *sta)
2611{
2612 int sta_id;
2613
2614 if (!sta)
2615 return context->bcast_sta_id;
2616
2617 sta_id = il_sta_id(sta);
2618
2619 /*
2620 * mac80211 should not be passing a partially
2621 * initialised station!
2622 */
2623 WARN_ON(sta_id == IL_INVALID_STATION);
2624
2625 return sta_id;
2626}
2627
2628/**
2629 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2630 * @idx -- current idx
2631 * @n_bd -- total number of entries in queue (must be power of 2)
2632 */
2633static inline int il_queue_inc_wrap(int idx, int n_bd)
2634{
2635 return ++idx & (n_bd - 1);
2636}
2637
2638/**
2639 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2640 * @idx -- current idx
2641 * @n_bd -- total number of entries in queue (must be power of 2)
2642 */
2643static inline int il_queue_dec_wrap(int idx, int n_bd)
2644{
2645 return --idx & (n_bd - 1);
2646}
2647
2648/* TODO: Move fw_desc functions to iwl-pci.ko */
2649static inline void il_free_fw_desc(struct pci_dev *pci_dev,
2650 struct fw_desc *desc)
2651{
2652 if (desc->v_addr)
2653 dma_free_coherent(&pci_dev->dev, desc->len,
2654 desc->v_addr, desc->p_addr);
2655 desc->v_addr = NULL;
2656 desc->len = 0;
2657}
2658
2659static inline int il_alloc_fw_desc(struct pci_dev *pci_dev,
2660 struct fw_desc *desc)
2661{
2662 if (!desc->len) {
2663 desc->v_addr = NULL;
2664 return -EINVAL;
2665 }
2666
2667 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2668 &desc->p_addr, GFP_KERNEL);
2669 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2670}
2671
2672/*
2673 * we have 8 bits used like this:
2674 *
2675 * 7 6 5 4 3 2 1 0
2676 * | | | | | | | |
2677 * | | | | | | +-+-------- AC queue (0-3)
2678 * | | | | | |
2679 * | +-+-+-+-+------------ HW queue ID
2680 * |
2681 * +---------------------- unused
2682 */
2683static inline void
2684il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2685{
2686 BUG_ON(ac > 3); /* only have 2 bits */
2687 BUG_ON(hwq > 31); /* only use 5 bits */
2688
2689 txq->swq_id = (hwq << 2) | ac;
2690}
2691
2692static inline void il_wake_queue(struct il_priv *il,
2693 struct il_tx_queue *txq)
2694{
2695 u8 queue = txq->swq_id;
2696 u8 ac = queue & 3;
2697 u8 hwq = (queue >> 2) & 0x1f;
2698
2699 if (test_and_clear_bit(hwq, il->queue_stopped))
2700 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2701 ieee80211_wake_queue(il->hw, ac);
2702}
2703
2704static inline void il_stop_queue(struct il_priv *il,
2705 struct il_tx_queue *txq)
2706{
2707 u8 queue = txq->swq_id;
2708 u8 ac = queue & 3;
2709 u8 hwq = (queue >> 2) & 0x1f;
2710
2711 if (!test_and_set_bit(hwq, il->queue_stopped))
2712 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2713 ieee80211_stop_queue(il->hw, ac);
2714}
2715
2716#ifdef ieee80211_stop_queue
2717#undef ieee80211_stop_queue
2718#endif
2719
2720#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2721
2722#ifdef ieee80211_wake_queue
2723#undef ieee80211_wake_queue
2724#endif
2725
2726#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2727
2728static inline void il_disable_interrupts(struct il_priv *il)
2729{
2730 clear_bit(S_INT_ENABLED, &il->status);
2731
2732 /* disable interrupts from uCode/NIC to host */
2733 _il_wr(il, CSR_INT_MASK, 0x00000000);
2734
2735 /* acknowledge/clear/reset any interrupts still pending
2736 * from uCode or flow handler (Rx/Tx DMA) */
2737 _il_wr(il, CSR_INT, 0xffffffff);
2738 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2739 D_ISR("Disabled interrupts\n");
2740}
2741
2742static inline void il_enable_rfkill_int(struct il_priv *il)
2743{
2744 D_ISR("Enabling rfkill interrupt\n");
2745 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2746}
2747
2748static inline void il_enable_interrupts(struct il_priv *il)
2749{
2750 D_ISR("Enabling interrupts\n");
2751 set_bit(S_INT_ENABLED, &il->status);
2752 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2753}
2754
2755/**
2756 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2757 * @il -- pointer to il_priv data structure
2758 * @tsf_bits -- number of bits need to shift for masking)
2759 */
2760static inline u32 il_beacon_time_mask_low(struct il_priv *il,
2761 u16 tsf_bits)
2762{
2763 return (1 << tsf_bits) - 1;
2764}
2765
2766/**
2767 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2768 * @il -- pointer to il_priv data structure
2769 * @tsf_bits -- number of bits need to shift for masking)
2770 */
2771static inline u32 il_beacon_time_mask_high(struct il_priv *il,
2772 u16 tsf_bits)
2773{
2774 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2775}
2776
2777/**
2778 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2779 *
2780 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2781 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2782 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2783 * in which the last frame was written to
2784 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2785 * which was transferred
2786 */
2787struct il_rb_status {
2788 __le16 closed_rb_num;
2789 __le16 closed_fr_num;
2790 __le16 finished_rb_num;
2791 __le16 finished_fr_nam;
2792 __le32 __unused; /* 3945 only */
2793} __packed;
2794
2795
2796#define TFD_QUEUE_SIZE_MAX (256)
2797#define TFD_QUEUE_SIZE_BC_DUP (64)
2798#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2799#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2800#define IL_NUM_OF_TBS 20
2801
2802static inline u8 il_get_dma_hi_addr(dma_addr_t addr)
2803{
2804 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2805}
2806/**
2807 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2808 *
2809 * This structure contains dma address and length of transmission address
2810 *
2811 * @lo: low [31:0] portion of the dma address of TX buffer
2812 * every even is unaligned on 16 bit boundary
2813 * @hi_n_len 0-3 [35:32] portion of dma
2814 * 4-15 length of the tx buffer
2815 */
2816struct il_tfd_tb {
2817 __le32 lo;
2818 __le16 hi_n_len;
2819} __packed;
2820
2821/**
2822 * struct il_tfd
2823 *
2824 * Transmit Frame Descriptor (TFD)
2825 *
2826 * @ __reserved1[3] reserved
2827 * @ num_tbs 0-4 number of active tbs
2828 * 5 reserved
2829 * 6-7 padding (not used)
2830 * @ tbs[20] transmit frame buffer descriptors
2831 * @ __pad padding
2832 *
2833 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2834 * Both driver and device share these circular buffers, each of which must be
2835 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2836 *
2837 * Driver must indicate the physical address of the base of each
2838 * circular buffer via the FH_MEM_CBBC_QUEUE registers.
2839 *
2840 * Each TFD contains pointer/size information for up to 20 data buffers
2841 * in host DRAM. These buffers collectively contain the (one) frame described
2842 * by the TFD. Each buffer must be a single contiguous block of memory within
2843 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2844 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2845 * Tx frame, up to 8 KBytes in size.
2846 *
2847 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2848 */
2849struct il_tfd {
2850 u8 __reserved1[3];
2851 u8 num_tbs;
2852 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2853 __le32 __pad;
2854} __packed;
2855/* PCI registers */
2856#define PCI_CFG_RETRY_TIMEOUT 0x041
2857
2858/* PCI register values */
2859#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2860#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2861
3fbbf9a8
SG		 2862struct il_rate_info {
2863 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2864 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2865 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2866 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2867 u8 prev_ieee; /* previous rate in IEEE speeds */
2868 u8 next_ieee; /* next rate in IEEE speeds */
2869 u8 prev_rs; /* previous rate used in rs algo */
2870 u8 next_rs; /* next rate used in rs algo */
2871 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2872 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2873};
2874
2875struct il3945_rate_info {
2876 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2877 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2878 u8 prev_ieee; /* previous rate in IEEE speeds */
2879 u8 next_ieee; /* next rate in IEEE speeds */
2880 u8 prev_rs; /* previous rate used in rs algo */
2881 u8 next_rs; /* next rate used in rs algo */
2882 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2883 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2884 u8 table_rs_idx; /* idx in rate scale table cmd */
2885 u8 prev_table_rs; /* prev in rate table cmd */
2886};
2887
2888
2889/*
2890 * These serve as idxes into
2891 * struct il_rate_info il_rates[RATE_COUNT];
2892 */
2893enum {
2894 RATE_1M_IDX = 0,
2895 RATE_2M_IDX,
2896 RATE_5M_IDX,
2897 RATE_11M_IDX,
2898 RATE_6M_IDX,
2899 RATE_9M_IDX,
2900 RATE_12M_IDX,
2901 RATE_18M_IDX,
2902 RATE_24M_IDX,
2903 RATE_36M_IDX,
2904 RATE_48M_IDX,
2905 RATE_54M_IDX,
2906 RATE_60M_IDX,
2907 RATE_COUNT,
2908 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2909 RATE_COUNT_3945 = RATE_COUNT - 1,
2910 RATE_INVM_IDX = RATE_COUNT,
2911 RATE_INVALID = RATE_COUNT,
2912};
2913
2914enum {
2915 RATE_6M_IDX_TBL = 0,
2916 RATE_9M_IDX_TBL,
2917 RATE_12M_IDX_TBL,
2918 RATE_18M_IDX_TBL,
2919 RATE_24M_IDX_TBL,
2920 RATE_36M_IDX_TBL,
2921 RATE_48M_IDX_TBL,
2922 RATE_54M_IDX_TBL,
2923 RATE_1M_IDX_TBL,
2924 RATE_2M_IDX_TBL,
2925 RATE_5M_IDX_TBL,
2926 RATE_11M_IDX_TBL,
2927 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2928};
2929
2930enum {
2931 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2932 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2933 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2934 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2935 IL_LAST_CCK_RATE = RATE_11M_IDX,
2936};
2937
2938/* #define vs. enum to keep from defaulting to 'large integer' */
2939#define RATE_6M_MASK (1 << RATE_6M_IDX)
2940#define RATE_9M_MASK (1 << RATE_9M_IDX)
2941#define RATE_12M_MASK (1 << RATE_12M_IDX)
2942#define RATE_18M_MASK (1 << RATE_18M_IDX)
2943#define RATE_24M_MASK (1 << RATE_24M_IDX)
2944#define RATE_36M_MASK (1 << RATE_36M_IDX)
2945#define RATE_48M_MASK (1 << RATE_48M_IDX)
2946#define RATE_54M_MASK (1 << RATE_54M_IDX)
2947#define RATE_60M_MASK (1 << RATE_60M_IDX)
2948#define RATE_1M_MASK (1 << RATE_1M_IDX)
2949#define RATE_2M_MASK (1 << RATE_2M_IDX)
2950#define RATE_5M_MASK (1 << RATE_5M_IDX)
2951#define RATE_11M_MASK (1 << RATE_11M_IDX)
2952
2953/* uCode API values for legacy bit rates, both OFDM and CCK */
2954enum {
2955 RATE_6M_PLCP = 13,
2956 RATE_9M_PLCP = 15,
2957 RATE_12M_PLCP = 5,
2958 RATE_18M_PLCP = 7,
2959 RATE_24M_PLCP = 9,
2960 RATE_36M_PLCP = 11,
2961 RATE_48M_PLCP = 1,
2962 RATE_54M_PLCP = 3,
2963 RATE_60M_PLCP = 3,/*FIXME:RS:should be removed*/
2964 RATE_1M_PLCP = 10,
2965 RATE_2M_PLCP = 20,
2966 RATE_5M_PLCP = 55,
2967 RATE_11M_PLCP = 110,
2968 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0,*/
2969};
2970
2971/* uCode API values for OFDM high-throughput (HT) bit rates */
2972enum {
2973 RATE_SISO_6M_PLCP = 0,
2974 RATE_SISO_12M_PLCP = 1,
2975 RATE_SISO_18M_PLCP = 2,
2976 RATE_SISO_24M_PLCP = 3,
2977 RATE_SISO_36M_PLCP = 4,
2978 RATE_SISO_48M_PLCP = 5,
2979 RATE_SISO_54M_PLCP = 6,
2980 RATE_SISO_60M_PLCP = 7,
2981 RATE_MIMO2_6M_PLCP = 0x8,
2982 RATE_MIMO2_12M_PLCP = 0x9,
2983 RATE_MIMO2_18M_PLCP = 0xa,
2984 RATE_MIMO2_24M_PLCP = 0xb,
2985 RATE_MIMO2_36M_PLCP = 0xc,
2986 RATE_MIMO2_48M_PLCP = 0xd,
2987 RATE_MIMO2_54M_PLCP = 0xe,
2988 RATE_MIMO2_60M_PLCP = 0xf,
2989 RATE_SISO_INVM_PLCP,
2990 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2991};
2992
2993/* MAC header values for bit rates */
2994enum {
2995 RATE_6M_IEEE = 12,
2996 RATE_9M_IEEE = 18,
2997 RATE_12M_IEEE = 24,
2998 RATE_18M_IEEE = 36,
2999 RATE_24M_IEEE = 48,
3000 RATE_36M_IEEE = 72,
3001 RATE_48M_IEEE = 96,
3002 RATE_54M_IEEE = 108,
3003 RATE_60M_IEEE = 120,
3004 RATE_1M_IEEE = 2,
3005 RATE_2M_IEEE = 4,
3006 RATE_5M_IEEE = 11,
3007 RATE_11M_IEEE = 22,
3008};
3009
3010#define IL_CCK_BASIC_RATES_MASK \
3011 (RATE_1M_MASK | \
3012 RATE_2M_MASK)
3013
3014#define IL_CCK_RATES_MASK \
3015 (IL_CCK_BASIC_RATES_MASK | \
3016 RATE_5M_MASK | \
3017 RATE_11M_MASK)
3018
3019#define IL_OFDM_BASIC_RATES_MASK \
3020 (RATE_6M_MASK | \
3021 RATE_12M_MASK | \
3022 RATE_24M_MASK)
3023
3024#define IL_OFDM_RATES_MASK \
3025 (IL_OFDM_BASIC_RATES_MASK | \
3026 RATE_9M_MASK | \
3027 RATE_18M_MASK | \
3028 RATE_36M_MASK | \
3029 RATE_48M_MASK | \
3030 RATE_54M_MASK)
3031
3032#define IL_BASIC_RATES_MASK \
3033 (IL_OFDM_BASIC_RATES_MASK | \
3034 IL_CCK_BASIC_RATES_MASK)
3035
3036#define RATES_MASK ((1 << RATE_COUNT) - 1)
3037#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
3038
3039#define IL_INVALID_VALUE -1
3040
3041#define IL_MIN_RSSI_VAL -100
3042#define IL_MAX_RSSI_VAL 0
3043
3044/* These values specify how many Tx frame attempts before
3045 * searching for a new modulation mode */
3046#define IL_LEGACY_FAILURE_LIMIT 160
3047#define IL_LEGACY_SUCCESS_LIMIT 480
3048#define IL_LEGACY_TBL_COUNT 160
3049
3050#define IL_NONE_LEGACY_FAILURE_LIMIT 400
3051#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
3052#define IL_NONE_LEGACY_TBL_COUNT 1500
3053
3054/* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
3055#define IL_RS_GOOD_RATIO 12800 /* 100% */
3056#define RATE_SCALE_SWITCH 10880 /* 85% */
3057#define RATE_HIGH_TH 10880 /* 85% */
3058#define RATE_INCREASE_TH 6400 /* 50% */
3059#define RATE_DECREASE_TH 1920 /* 15% */
3060
3061/* possible actions when in legacy mode */
3062#define IL_LEGACY_SWITCH_ANTENNA1 0
3063#define IL_LEGACY_SWITCH_ANTENNA2 1
3064#define IL_LEGACY_SWITCH_SISO 2
3065#define IL_LEGACY_SWITCH_MIMO2_AB 3
3066#define IL_LEGACY_SWITCH_MIMO2_AC 4
3067#define IL_LEGACY_SWITCH_MIMO2_BC 5
3068
3069/* possible actions when in siso mode */
3070#define IL_SISO_SWITCH_ANTENNA1 0
3071#define IL_SISO_SWITCH_ANTENNA2 1
3072#define IL_SISO_SWITCH_MIMO2_AB 2
3073#define IL_SISO_SWITCH_MIMO2_AC 3
3074#define IL_SISO_SWITCH_MIMO2_BC 4
3075#define IL_SISO_SWITCH_GI 5
3076
3077/* possible actions when in mimo mode */
3078#define IL_MIMO2_SWITCH_ANTENNA1 0
3079#define IL_MIMO2_SWITCH_ANTENNA2 1
3080#define IL_MIMO2_SWITCH_SISO_A 2
3081#define IL_MIMO2_SWITCH_SISO_B 3
3082#define IL_MIMO2_SWITCH_SISO_C 4
3083#define IL_MIMO2_SWITCH_GI 5
3084
3085#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
3086
3087#define IL_ACTION_LIMIT 3 /* # possible actions */
3088
3089#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
3090
3091/* load per tid defines for A-MPDU activation */
3092#define IL_AGG_TPT_THREHOLD 0
3093#define IL_AGG_LOAD_THRESHOLD 10
3094#define IL_AGG_ALL_TID 0xff
3095#define TID_QUEUE_CELL_SPACING 50 /*mS */
3096#define TID_QUEUE_MAX_SIZE 20
3097#define TID_ROUND_VALUE 5 /* mS */
3098#define TID_MAX_LOAD_COUNT 8
3099
3100#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
3101#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
3102
3103extern const struct il_rate_info il_rates[RATE_COUNT];
3104
3105enum il_table_type {
3106 LQ_NONE,
3107 LQ_G, /* legacy types */
3108 LQ_A,
3109 LQ_SISO, /* high-throughput types */
3110 LQ_MIMO2,
3111 LQ_MAX,
3112};
3113
3114#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
3115#define is_siso(tbl) ((tbl) == LQ_SISO)
3116#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
3117#define is_mimo(tbl) (is_mimo2(tbl))
3118#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
3119#define is_a_band(tbl) ((tbl) == LQ_A)
3120#define is_g_and(tbl) ((tbl) == LQ_G)
3121
3122#define ANT_NONE 0x0
3123#define ANT_A BIT(0)
3124#define ANT_B BIT(1)
3125#define ANT_AB (ANT_A | ANT_B)
3126#define ANT_C BIT(2)
3127#define ANT_AC (ANT_A | ANT_C)
3128#define ANT_BC (ANT_B | ANT_C)
3129#define ANT_ABC (ANT_AB | ANT_C)
3130
3131#define IL_MAX_MCS_DISPLAY_SIZE 12
3132
3133struct il_rate_mcs_info {
3134 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
3135 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
3136};
3137
3138/**
3139 * struct il_rate_scale_data -- tx success history for one rate
3140 */
3141struct il_rate_scale_data {
3142 u64 data; /* bitmap of successful frames */
3143 s32 success_counter; /* number of frames successful */
3144 s32 success_ratio; /* per-cent * 128 */
3145 s32 counter; /* number of frames attempted */
3146 s32 average_tpt; /* success ratio * expected throughput */
3147 unsigned long stamp;
3148};
3149
3150/**
3151 * struct il_scale_tbl_info -- tx params and success history for all rates
3152 *
3153 * There are two of these in struct il_lq_sta,
3154 * one for "active", and one for "search".
3155 */
3156struct il_scale_tbl_info {
3157 enum il_table_type lq_type;
3158 u8 ant_type;
3159 u8 is_SGI; /* 1 = short guard interval */
3160 u8 is_ht40; /* 1 = 40 MHz channel width */
3161 u8 is_dup; /* 1 = duplicated data streams */
3162 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
3163 u8 max_search; /* maximun number of tables we can search */
3164 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
3165 u32 current_rate; /* rate_n_flags, uCode API format */
3166 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
3167};
3168
3169struct il_traffic_load {
3170 unsigned long time_stamp; /* age of the oldest stats */
3171 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
3172 * slice */
3173 u32 total; /* total num of packets during the
3174 * last TID_MAX_TIME_DIFF */
3175 u8 queue_count; /* number of queues that has
3176 * been used since the last cleanup */
3177 u8 head; /* start of the circular buffer */
3178};
3179
3180/**
3181 * struct il_lq_sta -- driver's rate scaling ilate structure
3182 *
3183 * Pointer to this gets passed back and forth between driver and mac80211.
3184 */
3185struct il_lq_sta {
3186 u8 active_tbl; /* idx of active table, range 0-1 */
3187 u8 enable_counter; /* indicates HT mode */
3188 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
3189 u8 search_better_tbl; /* 1: currently trying alternate mode */
3190 s32 last_tpt;
3191
3192 /* The following determine when to search for a new mode */
3193 u32 table_count_limit;
3194 u32 max_failure_limit; /* # failed frames before new search */
3195 u32 max_success_limit; /* # successful frames before new search */
3196 u32 table_count;
3197 u32 total_failed; /* total failed frames, any/all rates */
3198 u32 total_success; /* total successful frames, any/all rates */
3199 u64 flush_timer; /* time staying in mode before new search */
3200
3201 u8 action_counter; /* # mode-switch actions tried */
3202 u8 is_green;
3203 u8 is_dup;
3204 enum ieee80211_band band;
3205
3206 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
3207 u32 supp_rates;
3208 u16 active_legacy_rate;
3209 u16 active_siso_rate;
3210 u16 active_mimo2_rate;
3211 s8 max_rate_idx; /* Max rate set by user */
3212 u8 missed_rate_counter;
3213
3214 struct il_link_quality_cmd lq;
3215 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
3216 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
3217 u8 tx_agg_tid_en;
3218#ifdef CONFIG_MAC80211_DEBUGFS
3219 struct dentry *rs_sta_dbgfs_scale_table_file;
3220 struct dentry *rs_sta_dbgfs_stats_table_file;
3221 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
3222 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
3223 u32 dbg_fixed_rate;
3224#endif
3225 struct il_priv *drv;
3226
3227 /* used to be in sta_info */
3228 int last_txrate_idx;
3229 /* last tx rate_n_flags */
3230 u32 last_rate_n_flags;
3231 /* packets destined for this STA are aggregated */
3232 u8 is_agg;
3233};
3234
3235/*
3236 * il_station_priv: Driver's ilate station information
3237 *
3238 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
3239 * in the structure for use by driver. This structure is places in that
3240 * space.
3241 *
3242 * The common struct MUST be first because it is shared between
3243 * 3945 and 4965!
3244 */
3245struct il_station_priv {
3246 struct il_station_priv_common common;
3247 struct il_lq_sta lq_sta;
3248 atomic_t pending_frames;
3249 bool client;
3250 bool asleep;
3251};
3252
3253static inline u8 il4965_num_of_ant(u8 m)
3254{
3255 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
3256}
3257
3258static inline u8 il4965_first_antenna(u8 mask)
3259{
3260 if (mask & ANT_A)
3261 return ANT_A;
3262 if (mask & ANT_B)
3263 return ANT_B;
3264 return ANT_C;
3265}
3266
3267
3268/**
3269 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
3270 *
3271 * The specific throughput table used is based on the type of network
3272 * the associated with, including A, B, G, and G w/ TGG protection
3273 */
3274extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
3275
3276/* Initialize station's rate scaling information after adding station */
3277extern void il4965_rs_rate_init(struct il_priv *il,
3278 struct ieee80211_sta *sta, u8 sta_id);
3279extern void il3945_rs_rate_init(struct il_priv *il,
3280 struct ieee80211_sta *sta, u8 sta_id);
3281
3282/**
3283 * il_rate_control_register - Register the rate control algorithm callbacks
3284 *
3285 * Since the rate control algorithm is hardware specific, there is no need
3286 * or reason to place it as a stand alone module. The driver can call
3287 * il_rate_control_register in order to register the rate control callbacks
3288 * with the mac80211 subsystem. This should be performed prior to calling
3289 * ieee80211_register_hw
3290 *
3291 */
3292extern int il4965_rate_control_register(void);
3293extern int il3945_rate_control_register(void);
3294
3295/**
3296 * il_rate_control_unregister - Unregister the rate control callbacks
3297 *
3298 * This should be called after calling ieee80211_unregister_hw, but before
3299 * the driver is unloaded.
3300 */
3301extern void il4965_rate_control_unregister(void);
3302extern void il3945_rate_control_unregister(void);
3303
99412002
SG		 3304extern int il_power_update_mode(struct il_priv *il, bool force);
3305extern void il_power_initialize(struct il_priv *il);
47ef694d 3306
e2ebc833 3307#endif /* __il_core_h__ */
Linux kernel - Deliverables
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