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be663ab6 WYG |
1 | /****************************************************************************** |
2 | * | |
e94a4099 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
be663ab6 | 4 | * |
e94a4099 SG |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of version 2 of the GNU General Public License as | |
be663ab6 WYG |
7 | * published by the Free Software Foundation. |
8 | * | |
e94a4099 SG |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
be663ab6 | 13 | * |
e94a4099 SG |
14 | * You should have received a copy of the GNU General Public License along with |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
be663ab6 | 17 | * |
e94a4099 SG |
18 | * The full GNU General Public License is included in this distribution in the |
19 | * file called LICENSE. | |
be663ab6 WYG |
20 | * |
21 | * Contact Information: | |
22 | * Intel Linux Wireless <ilw@linux.intel.com> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
e94a4099 SG |
25 | *****************************************************************************/ |
26 | #ifndef __il_core_h__ | |
27 | #define __il_core_h__ | |
28 | ||
29 | #include <linux/interrupt.h> | |
e7392364 | 30 | #include <linux/pci.h> /* for struct pci_device_id */ |
e94a4099 SG |
31 | #include <linux/kernel.h> |
32 | #include <linux/leds.h> | |
33 | #include <linux/wait.h> | |
17d4eca6 | 34 | #include <linux/io.h> |
47ef694d | 35 | #include <net/mac80211.h> |
e94a4099 SG |
36 | #include <net/ieee80211_radiotap.h> |
37 | ||
99412002 | 38 | #include "commands.h" |
e94a4099 | 39 | #include "csr.h" |
e8c39d4e | 40 | #include "prph.h" |
e94a4099 SG |
41 | |
42 | struct il_host_cmd; | |
43 | struct il_cmd; | |
44 | struct il_tx_queue; | |
45 | ||
f02579e3 SG |
46 | #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a) |
47 | #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a) | |
48 | #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a) | |
49 | ||
e94a4099 SG |
50 | #define RX_QUEUE_SIZE 256 |
51 | #define RX_QUEUE_MASK 255 | |
52 | #define RX_QUEUE_SIZE_LOG 8 | |
53 | ||
54 | /* | |
55 | * RX related structures and functions | |
56 | */ | |
57 | #define RX_FREE_BUFFERS 64 | |
58 | #define RX_LOW_WATERMARK 8 | |
59 | ||
60 | #define U32_PAD(n) ((4-(n))&0x3) | |
61 | ||
62 | /* CT-KILL constants */ | |
e7392364 | 63 | #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ |
e94a4099 SG |
64 | |
65 | /* Default noise level to report when noise measurement is not available. | |
66 | * This may be because we're: | |
67 | * 1) Not associated (4965, no beacon stats being sent to driver) | |
68 | * 2) Scanning (noise measurement does not apply to associated channel) | |
69 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
70 | * Use default noise value of -127 ... this is below the range of measurable | |
71 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
72 | * Also, -127 works better than 0 when averaging frames with/without | |
73 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
74 | * always negative ... using a negative value as the default keeps all | |
75 | * averages within an s8's (used in some apps) range of negative values. */ | |
76 | #define IL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
77 | ||
78 | /* | |
79 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
80 | * Per spec: | |
81 | * a value of 0 means RTS on all data/management packets | |
82 | * a value > max MSDU size means no RTS | |
83 | * else RTS for data/management frames where MPDU is larger | |
84 | * than RTS value. | |
85 | */ | |
86 | #define DEFAULT_RTS_THRESHOLD 2347U | |
87 | #define MIN_RTS_THRESHOLD 0U | |
88 | #define MAX_RTS_THRESHOLD 2347U | |
89 | #define MAX_MSDU_SIZE 2304U | |
90 | #define MAX_MPDU_SIZE 2346U | |
91 | #define DEFAULT_BEACON_INTERVAL 100U | |
92 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
93 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
94 | ||
95 | struct il_rx_buf { | |
96 | dma_addr_t page_dma; | |
97 | struct page *page; | |
98 | struct list_head list; | |
99 | }; | |
100 | ||
101 | #define rxb_addr(r) page_address(r->page) | |
102 | ||
103 | /* defined below */ | |
104 | struct il_device_cmd; | |
105 | ||
106 | struct il_cmd_meta { | |
107 | /* only for SYNC commands, iff the reply skb is wanted */ | |
108 | struct il_host_cmd *source; | |
109 | /* | |
110 | * only for ASYNC commands | |
111 | * (which is somewhat stupid -- look at common.c for instance | |
112 | * which duplicates a bunch of code because the callback isn't | |
113 | * invoked for SYNC commands, if it were and its result passed | |
114 | * through it would be simpler...) | |
115 | */ | |
1722f8e1 SG |
116 | void (*callback) (struct il_priv *il, struct il_device_cmd *cmd, |
117 | struct il_rx_pkt *pkt); | |
e94a4099 SG |
118 | |
119 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
120 | * structure is stored at the end of the shared queue memory. */ | |
121 | u32 flags; | |
122 | ||
e7392364 SG |
123 | DEFINE_DMA_UNMAP_ADDR(mapping); |
124 | DEFINE_DMA_UNMAP_LEN(len); | |
e94a4099 SG |
125 | }; |
126 | ||
127 | /* | |
128 | * Generic queue structure | |
129 | * | |
130 | * Contains common data for Rx and Tx queues | |
131 | */ | |
132 | struct il_queue { | |
e7392364 SG |
133 | int n_bd; /* number of BDs in this queue */ |
134 | int write_ptr; /* 1-st empty entry (idx) host_w */ | |
135 | int read_ptr; /* last used entry (idx) host_r */ | |
e94a4099 | 136 | /* use for monitoring and recovering the stuck queue */ |
e7392364 SG |
137 | dma_addr_t dma_addr; /* physical addr for BD's */ |
138 | int n_win; /* safe queue win */ | |
e94a4099 | 139 | u32 id; |
e7392364 SG |
140 | int low_mark; /* low watermark, resume queue if free |
141 | * space more than this */ | |
142 | int high_mark; /* high watermark, stop queue if free | |
143 | * space less than this */ | |
e94a4099 SG |
144 | }; |
145 | ||
e94a4099 SG |
146 | /** |
147 | * struct il_tx_queue - Tx Queue for DMA | |
148 | * @q: generic Rx/Tx queue descriptor | |
149 | * @bd: base of circular buffer of TFDs | |
150 | * @cmd: array of command/TX buffer pointers | |
151 | * @meta: array of meta data for each command/tx buffer | |
152 | * @dma_addr_cmd: physical address of cmd/tx buffer array | |
00ea99e1 | 153 | * @skbs: array of per-TFD socket buffer pointers |
e94a4099 SG |
154 | * @time_stamp: time (in jiffies) of last read_ptr change |
155 | * @need_update: indicates need to update read/write idx | |
156 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
157 | * | |
158 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame | |
159 | * descriptors) and required locking structures. | |
160 | */ | |
161 | #define TFD_TX_CMD_SLOTS 256 | |
162 | #define TFD_CMD_SLOTS 32 | |
163 | ||
164 | struct il_tx_queue { | |
165 | struct il_queue q; | |
166 | void *tfds; | |
167 | struct il_device_cmd **cmd; | |
168 | struct il_cmd_meta *meta; | |
00ea99e1 | 169 | struct sk_buff **skbs; |
e94a4099 SG |
170 | unsigned long time_stamp; |
171 | u8 need_update; | |
172 | u8 sched_retry; | |
173 | u8 active; | |
174 | u8 swq_id; | |
175 | }; | |
176 | ||
47ef694d SG |
177 | /* |
178 | * EEPROM access time values: | |
179 | * | |
180 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. | |
181 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). | |
182 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. | |
183 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. | |
184 | */ | |
e7392364 | 185 | #define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ |
47ef694d | 186 | |
e7392364 SG |
187 | #define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ |
188 | #define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
47ef694d SG |
189 | |
190 | /* | |
191 | * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags. | |
192 | * | |
193 | * IBSS and/or AP operation is allowed *only* on those channels with | |
194 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because | |
195 | * RADAR detection is not supported by the 4965 driver, but is a | |
196 | * requirement for establishing a new network for legal operation on channels | |
197 | * requiring RADAR detection or restricting ACTIVE scanning. | |
198 | * | |
199 | * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels. | |
200 | * It only indicates that 20 MHz channel use is supported; HT40 channel | |
201 | * usage is indicated by a separate set of regulatory flags for each | |
202 | * HT40 channel pair. | |
203 | * | |
204 | * NOTE: Using a channel inappropriately will result in a uCode error! | |
205 | */ | |
206 | #define IL_NUM_TX_CALIB_GROUPS 5 | |
207 | enum { | |
208 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ | |
e7392364 | 209 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ |
47ef694d SG |
210 | /* Bit 2 Reserved */ |
211 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ | |
212 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ | |
e7392364 | 213 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ |
47ef694d SG |
214 | /* Bit 6 Reserved (was Narrow Channel) */ |
215 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ | |
216 | }; | |
217 | ||
218 | /* SKU Capabilities */ | |
219 | /* 3945 only */ | |
220 | #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) | |
221 | #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) | |
222 | ||
223 | /* *regulatory* channel data format in eeprom, one for each channel. | |
224 | * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */ | |
225 | struct il_eeprom_channel { | |
226 | u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ | |
227 | s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ | |
228 | } __packed; | |
229 | ||
230 | /* 3945 Specific */ | |
231 | #define EEPROM_3945_EEPROM_VERSION (0x2f) | |
232 | ||
233 | /* 4965 has two radio transmitters (and 3 radio receivers) */ | |
234 | #define EEPROM_TX_POWER_TX_CHAINS (2) | |
235 | ||
236 | /* 4965 has room for up to 8 sets of txpower calibration data */ | |
237 | #define EEPROM_TX_POWER_BANDS (8) | |
238 | ||
239 | /* 4965 factory calibration measures txpower gain settings for | |
240 | * each of 3 target output levels */ | |
241 | #define EEPROM_TX_POWER_MEASUREMENTS (3) | |
242 | ||
243 | /* 4965 Specific */ | |
244 | /* 4965 driver does not work with txpower calibration version < 5 */ | |
245 | #define EEPROM_4965_TX_POWER_VERSION (5) | |
246 | #define EEPROM_4965_EEPROM_VERSION (0x2f) | |
e7392364 SG |
247 | #define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */ |
248 | #define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */ | |
249 | #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */ | |
250 | #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */ | |
47ef694d SG |
251 | |
252 | /* 2.4 GHz */ | |
253 | extern const u8 il_eeprom_band_1[14]; | |
254 | ||
255 | /* | |
256 | * factory calibration data for one txpower level, on one channel, | |
257 | * measured on one of the 2 tx chains (radio transmitter and associated | |
258 | * antenna). EEPROM contains: | |
259 | * | |
260 | * 1) Temperature (degrees Celsius) of device when measurement was made. | |
261 | * | |
262 | * 2) Gain table idx used to achieve the target measurement power. | |
263 | * This refers to the "well-known" gain tables (see 4965.h). | |
264 | * | |
265 | * 3) Actual measured output power, in half-dBm ("34" = 17 dBm). | |
266 | * | |
267 | * 4) RF power amplifier detector level measurement (not used). | |
268 | */ | |
269 | struct il_eeprom_calib_measure { | |
270 | u8 temperature; /* Device temperature (Celsius) */ | |
271 | u8 gain_idx; /* Index into gain table */ | |
272 | u8 actual_pow; /* Measured RF output power, half-dBm */ | |
273 | s8 pa_det; /* Power amp detector level (not used) */ | |
274 | } __packed; | |
275 | ||
47ef694d SG |
276 | /* |
277 | * measurement set for one channel. EEPROM contains: | |
278 | * | |
279 | * 1) Channel number measured | |
280 | * | |
281 | * 2) Measurements for each of 3 power levels for each of 2 radio transmitters | |
282 | * (a.k.a. "tx chains") (6 measurements altogether) | |
283 | */ | |
284 | struct il_eeprom_calib_ch_info { | |
285 | u8 ch_num; | |
286 | struct il_eeprom_calib_measure | |
e7392364 SG |
287 | measurements[EEPROM_TX_POWER_TX_CHAINS] |
288 | [EEPROM_TX_POWER_MEASUREMENTS]; | |
47ef694d SG |
289 | } __packed; |
290 | ||
291 | /* | |
292 | * txpower subband info. | |
293 | * | |
294 | * For each frequency subband, EEPROM contains the following: | |
295 | * | |
296 | * 1) First and last channels within range of the subband. "0" values | |
297 | * indicate that this sample set is not being used. | |
298 | * | |
299 | * 2) Sample measurement sets for 2 channels close to the range endpoints. | |
300 | */ | |
301 | struct il_eeprom_calib_subband_info { | |
e7392364 SG |
302 | u8 ch_from; /* channel number of lowest channel in subband */ |
303 | u8 ch_to; /* channel number of highest channel in subband */ | |
47ef694d SG |
304 | struct il_eeprom_calib_ch_info ch1; |
305 | struct il_eeprom_calib_ch_info ch2; | |
306 | } __packed; | |
307 | ||
47ef694d SG |
308 | /* |
309 | * txpower calibration info. EEPROM contains: | |
310 | * | |
311 | * 1) Factory-measured saturation power levels (maximum levels at which | |
312 | * tx power amplifier can output a signal without too much distortion). | |
313 | * There is one level for 2.4 GHz band and one for 5 GHz band. These | |
314 | * values apply to all channels within each of the bands. | |
315 | * | |
316 | * 2) Factory-measured power supply voltage level. This is assumed to be | |
317 | * constant (i.e. same value applies to all channels/bands) while the | |
318 | * factory measurements are being made. | |
319 | * | |
320 | * 3) Up to 8 sets of factory-measured txpower calibration values. | |
321 | * These are for different frequency ranges, since txpower gain | |
322 | * characteristics of the analog radio circuitry vary with frequency. | |
323 | * | |
324 | * Not all sets need to be filled with data; | |
325 | * struct il_eeprom_calib_subband_info contains range of channels | |
326 | * (0 if unused) for each set of data. | |
327 | */ | |
328 | struct il_eeprom_calib_info { | |
329 | u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */ | |
330 | u8 saturation_power52; /* half-dBm */ | |
331 | __le16 voltage; /* signed */ | |
e7392364 | 332 | struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS]; |
47ef694d SG |
333 | } __packed; |
334 | ||
47ef694d SG |
335 | /* General */ |
336 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ | |
337 | #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ | |
338 | #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ | |
339 | #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ | |
340 | #define EEPROM_VERSION (2*0x44) /* 2 bytes */ | |
341 | #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ | |
342 | #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ | |
343 | #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ | |
344 | #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ | |
345 | #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ | |
346 | ||
347 | /* The following masks are to be applied on EEPROM_RADIO_CONFIG */ | |
e7392364 SG |
348 | #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ |
349 | #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ | |
350 | #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ | |
351 | #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ | |
352 | #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ | |
353 | #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ | |
47ef694d SG |
354 | |
355 | #define EEPROM_3945_RF_CFG_TYPE_MAX 0x0 | |
356 | #define EEPROM_4965_RF_CFG_TYPE_MAX 0x1 | |
357 | ||
358 | /* | |
359 | * Per-channel regulatory data. | |
360 | * | |
361 | * Each channel that *might* be supported by iwl has a fixed location | |
362 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory | |
363 | * txpower (MSB). | |
364 | * | |
365 | * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz) | |
366 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. | |
367 | * | |
368 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
369 | */ | |
e7392364 | 370 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ |
47ef694d SG |
371 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ |
372 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ | |
373 | ||
374 | /* | |
375 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | |
376 | * 5.0 GHz channels 7, 8, 11, 12, 16 | |
377 | * (4915-5080MHz) (none of these is ever supported) | |
378 | */ | |
379 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ | |
380 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ | |
381 | ||
382 | /* | |
383 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
384 | * (5170-5320MHz) | |
385 | */ | |
386 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ | |
387 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ | |
388 | ||
389 | /* | |
390 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
391 | * (5500-5700MHz) | |
392 | */ | |
393 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ | |
394 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ | |
395 | ||
396 | /* | |
397 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | |
398 | * (5725-5825MHz) | |
399 | */ | |
400 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ | |
401 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ | |
402 | ||
403 | /* | |
404 | * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11) | |
405 | * | |
406 | * The channel listed is the center of the lower 20 MHz half of the channel. | |
407 | * The overall center frequency is actually 2 channels (10 MHz) above that, | |
408 | * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away | |
409 | * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5, | |
410 | * and the overall HT40 channel width centers on channel 3. | |
411 | * | |
412 | * NOTE: The RXON command uses 20 MHz channel numbers to specify the | |
413 | * control channel to which to tune. RXON also specifies whether the | |
414 | * control channel is the upper or lower half of a HT40 channel. | |
415 | * | |
416 | * NOTE: 4965 does not support HT40 channels on 2.4 GHz. | |
417 | */ | |
418 | #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */ | |
419 | ||
420 | /* | |
421 | * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64), | |
422 | * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161) | |
423 | */ | |
424 | #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */ | |
425 | ||
426 | #define EEPROM_REGULATORY_BAND_NO_HT40 (0) | |
427 | ||
47ef694d SG |
428 | int il_eeprom_init(struct il_priv *il); |
429 | void il_eeprom_free(struct il_priv *il); | |
e7392364 | 430 | const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset); |
47ef694d SG |
431 | u16 il_eeprom_query16(const struct il_priv *il, size_t offset); |
432 | int il_init_channel_map(struct il_priv *il); | |
433 | void il_free_channel_map(struct il_priv *il); | |
e7392364 SG |
434 | const struct il_channel_info *il_get_channel_info(const struct il_priv *il, |
435 | enum ieee80211_band band, | |
436 | u16 channel); | |
47ef694d | 437 | |
e94a4099 SG |
438 | #define IL_NUM_SCAN_RATES (2) |
439 | ||
440 | struct il4965_channel_tgd_info { | |
441 | u8 type; | |
442 | s8 max_power; | |
443 | }; | |
444 | ||
445 | struct il4965_channel_tgh_info { | |
446 | s64 last_radar_time; | |
447 | }; | |
448 | ||
449 | #define IL4965_MAX_RATE (33) | |
450 | ||
451 | struct il3945_clip_group { | |
452 | /* maximum power level to prevent clipping for each rate, derived by | |
453 | * us from this band's saturation power in EEPROM */ | |
454 | const s8 clip_powers[IL_MAX_RATES]; | |
455 | }; | |
456 | ||
457 | /* current Tx power values to use, one for each rate for each channel. | |
458 | * requested power is limited by: | |
459 | * -- regulatory EEPROM limits for this channel | |
460 | * -- hardware capabilities (clip-powers) | |
461 | * -- spectrum management | |
462 | * -- user preference (e.g. iwconfig) | |
463 | * when requested power is set, base power idx must also be set. */ | |
464 | struct il3945_channel_power_info { | |
465 | struct il3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
466 | s8 power_table_idx; /* actual (compenst'd) idx into gain table */ | |
467 | s8 base_power_idx; /* gain idx for power at factory temp. */ | |
468 | s8 requested_power; /* power (dBm) requested for this chnl/rate */ | |
469 | }; | |
470 | ||
471 | /* current scan Tx power values to use, one for each scan rate for each | |
472 | * channel. */ | |
473 | struct il3945_scan_power_info { | |
474 | struct il3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
475 | s8 power_table_idx; /* actual (compenst'd) idx into gain table */ | |
476 | s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ | |
477 | }; | |
478 | ||
479 | /* | |
480 | * One for each channel, holds all channel setup data | |
481 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
482 | * with one another! | |
483 | */ | |
484 | struct il_channel_info { | |
485 | struct il4965_channel_tgd_info tgd; | |
486 | struct il4965_channel_tgh_info tgh; | |
487 | struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */ | |
488 | struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for | |
489 | * HT40 channel */ | |
490 | ||
e7392364 SG |
491 | u8 channel; /* channel number */ |
492 | u8 flags; /* flags copied from EEPROM */ | |
493 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
494 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ | |
495 | s8 min_power; /* always 0 */ | |
496 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
e94a4099 | 497 | |
e7392364 SG |
498 | u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */ |
499 | u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */ | |
e94a4099 SG |
500 | enum ieee80211_band band; |
501 | ||
502 | /* HT40 channel info */ | |
503 | s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
504 | u8 ht40_flags; /* flags copied from EEPROM */ | |
e7392364 | 505 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ |
e94a4099 SG |
506 | |
507 | /* Radio/DSP gain settings for each "normal" data Tx rate. | |
508 | * These include, in addition to RF and DSP gain, a few fields for | |
509 | * remembering/modifying gain settings (idxes). */ | |
510 | struct il3945_channel_power_info power_info[IL4965_MAX_RATE]; | |
511 | ||
512 | /* Radio/DSP gain settings for each scan rate, for directed scans. */ | |
513 | struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES]; | |
514 | }; | |
515 | ||
516 | #define IL_TX_FIFO_BK 0 /* shared */ | |
517 | #define IL_TX_FIFO_BE 1 | |
518 | #define IL_TX_FIFO_VI 2 /* shared */ | |
519 | #define IL_TX_FIFO_VO 3 | |
520 | #define IL_TX_FIFO_UNUSED -1 | |
521 | ||
522 | /* Minimum number of queues. MAX_NUM is defined in hw specific files. | |
523 | * Set the minimum to accommodate the 4 standard TX queues, 1 command | |
524 | * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ | |
525 | #define IL_MIN_NUM_QUEUES 10 | |
526 | ||
527 | #define IL_DEFAULT_CMD_QUEUE_NUM 4 | |
528 | ||
529 | #define IEEE80211_DATA_LEN 2304 | |
530 | #define IEEE80211_4ADDR_LEN 30 | |
531 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
532 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
533 | ||
534 | struct il_frame { | |
535 | union { | |
536 | struct ieee80211_hdr frame; | |
537 | struct il_tx_beacon_cmd beacon; | |
538 | u8 raw[IEEE80211_FRAME_LEN]; | |
539 | u8 cmd[360]; | |
540 | } u; | |
541 | struct list_head list; | |
542 | }; | |
543 | ||
544 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) | |
545 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
546 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
547 | ||
548 | enum { | |
549 | CMD_SYNC = 0, | |
550 | CMD_SIZE_NORMAL = 0, | |
551 | CMD_NO_SKB = 0, | |
552 | CMD_SIZE_HUGE = (1 << 0), | |
553 | CMD_ASYNC = (1 << 1), | |
554 | CMD_WANT_SKB = (1 << 2), | |
555 | CMD_MAPPED = (1 << 3), | |
556 | }; | |
557 | ||
558 | #define DEF_CMD_PAYLOAD_SIZE 320 | |
559 | ||
560 | /** | |
561 | * struct il_device_cmd | |
562 | * | |
563 | * For allocation of the command and tx queues, this establishes the overall | |
564 | * size of the largest command we send to uCode, except for a scan command | |
565 | * (which is relatively huge; space is allocated separately). | |
566 | */ | |
567 | struct il_device_cmd { | |
568 | struct il_cmd_header hdr; /* uCode API */ | |
569 | union { | |
570 | u32 flags; | |
571 | u8 val8; | |
572 | u16 val16; | |
573 | u32 val32; | |
574 | struct il_tx_cmd tx; | |
575 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | |
576 | } __packed cmd; | |
577 | } __packed; | |
578 | ||
579 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd)) | |
580 | ||
e94a4099 SG |
581 | struct il_host_cmd { |
582 | const void *data; | |
583 | unsigned long reply_page; | |
1722f8e1 SG |
584 | void (*callback) (struct il_priv *il, struct il_device_cmd *cmd, |
585 | struct il_rx_pkt *pkt); | |
e94a4099 SG |
586 | u32 flags; |
587 | u16 len; | |
588 | u8 id; | |
589 | }; | |
590 | ||
591 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 | |
592 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
593 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
594 | ||
595 | /** | |
596 | * struct il_rx_queue - Rx queue | |
597 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) | |
598 | * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) | |
599 | * @read: Shared idx to newest available Rx buffer | |
600 | * @write: Shared idx to oldest written Rx packet | |
601 | * @free_count: Number of pre-allocated buffers in rx_free | |
602 | * @rx_free: list of free SKBs for use | |
603 | * @rx_used: List of Rx buffers with no SKB | |
604 | * @need_update: flag to indicate we need to update read/write idx | |
605 | * @rb_stts: driver's pointer to receive buffer status | |
606 | * @rb_stts_dma: bus address of receive buffer status | |
607 | * | |
608 | * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs | |
609 | */ | |
610 | struct il_rx_queue { | |
611 | __le32 *bd; | |
612 | dma_addr_t bd_dma; | |
613 | struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; | |
614 | struct il_rx_buf *queue[RX_QUEUE_SIZE]; | |
615 | u32 read; | |
616 | u32 write; | |
617 | u32 free_count; | |
618 | u32 write_actual; | |
619 | struct list_head rx_free; | |
620 | struct list_head rx_used; | |
621 | int need_update; | |
622 | struct il_rb_status *rb_stts; | |
623 | dma_addr_t rb_stts_dma; | |
624 | spinlock_t lock; | |
625 | }; | |
626 | ||
627 | #define IL_SUPPORTED_RATES_IE_LEN 8 | |
628 | ||
629 | #define MAX_TID_COUNT 9 | |
630 | ||
631 | #define IL_INVALID_RATE 0xFF | |
632 | #define IL_INVALID_VALUE -1 | |
633 | ||
634 | /** | |
635 | * struct il_ht_agg -- aggregation status while waiting for block-ack | |
636 | * @txq_id: Tx queue used for Tx attempt | |
637 | * @frame_count: # frames attempted by Tx command | |
638 | * @wait_for_ba: Expect block-ack before next Tx reply | |
639 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win | |
640 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win | |
641 | * @bitmap1: High order, one bit for each frame pending ACK in Tx win | |
642 | * @rate_n_flags: Rate at which Tx was attempted | |
643 | * | |
644 | * If C_TX indicates that aggregation was attempted, driver must wait | |
645 | * for block ack (N_COMPRESSED_BA). This struct stores tx reply info | |
646 | * until block ack arrives. | |
647 | */ | |
648 | struct il_ht_agg { | |
649 | u16 txq_id; | |
650 | u16 frame_count; | |
651 | u16 wait_for_ba; | |
652 | u16 start_idx; | |
653 | u64 bitmap; | |
654 | u32 rate_n_flags; | |
655 | #define IL_AGG_OFF 0 | |
656 | #define IL_AGG_ON 1 | |
657 | #define IL_EMPTYING_HW_QUEUE_ADDBA 2 | |
658 | #define IL_EMPTYING_HW_QUEUE_DELBA 3 | |
659 | u8 state; | |
660 | }; | |
661 | ||
e94a4099 | 662 | struct il_tid_data { |
e7392364 | 663 | u16 seq_number; /* 4965 only */ |
e94a4099 SG |
664 | u16 tfds_in_queue; |
665 | struct il_ht_agg agg; | |
666 | }; | |
667 | ||
668 | struct il_hw_key { | |
669 | u32 cipher; | |
670 | int keylen; | |
671 | u8 keyidx; | |
672 | u8 key[32]; | |
673 | }; | |
674 | ||
675 | union il_ht_rate_supp { | |
676 | u16 rates; | |
677 | struct { | |
678 | u8 siso_rate; | |
679 | u8 mimo_rate; | |
680 | }; | |
681 | }; | |
682 | ||
683 | #define CFG_HT_RX_AMPDU_FACTOR_8K (0x0) | |
684 | #define CFG_HT_RX_AMPDU_FACTOR_16K (0x1) | |
685 | #define CFG_HT_RX_AMPDU_FACTOR_32K (0x2) | |
686 | #define CFG_HT_RX_AMPDU_FACTOR_64K (0x3) | |
687 | #define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K | |
688 | #define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K | |
689 | #define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K | |
690 | ||
691 | /* | |
692 | * Maximal MPDU density for TX aggregation | |
693 | * 4 - 2us density | |
694 | * 5 - 4us density | |
695 | * 6 - 8us density | |
696 | * 7 - 16us density | |
697 | */ | |
698 | #define CFG_HT_MPDU_DENSITY_2USEC (0x4) | |
699 | #define CFG_HT_MPDU_DENSITY_4USEC (0x5) | |
700 | #define CFG_HT_MPDU_DENSITY_8USEC (0x6) | |
701 | #define CFG_HT_MPDU_DENSITY_16USEC (0x7) | |
702 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC | |
703 | #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC | |
704 | #define CFG_HT_MPDU_DENSITY_MIN (0x1) | |
705 | ||
706 | struct il_ht_config { | |
707 | bool single_chain_sufficient; | |
e7392364 | 708 | enum ieee80211_smps_mode smps; /* current smps mode */ |
e94a4099 SG |
709 | }; |
710 | ||
711 | /* QoS structures */ | |
712 | struct il_qos_info { | |
713 | int qos_active; | |
714 | struct il_qosparam_cmd def_qos_parm; | |
715 | }; | |
716 | ||
717 | /* | |
718 | * Structure should be accessed with sta_lock held. When station addition | |
719 | * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only | |
720 | * the commands (il_addsta_cmd and il_link_quality_cmd) without | |
721 | * sta_lock held. | |
722 | */ | |
723 | struct il_station_entry { | |
724 | struct il_addsta_cmd sta; | |
725 | struct il_tid_data tid[MAX_TID_COUNT]; | |
6aa0c254 | 726 | u8 used; |
e94a4099 SG |
727 | struct il_hw_key keyinfo; |
728 | struct il_link_quality_cmd *lq; | |
729 | }; | |
730 | ||
731 | struct il_station_priv_common { | |
e94a4099 SG |
732 | u8 sta_id; |
733 | }; | |
734 | ||
e94a4099 SG |
735 | /** |
736 | * struct il_vif_priv - driver's ilate per-interface information | |
737 | * | |
738 | * When mac80211 allocates a virtual interface, it can allocate | |
739 | * space for us to put data into. | |
740 | */ | |
741 | struct il_vif_priv { | |
e94a4099 SG |
742 | u8 ibss_bssid_sta_id; |
743 | }; | |
744 | ||
745 | /* one for each uCode image (inst/data, boot/init/runtime) */ | |
746 | struct fw_desc { | |
747 | void *v_addr; /* access by driver */ | |
748 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
749 | u32 len; /* bytes */ | |
750 | }; | |
751 | ||
752 | /* uCode file layout */ | |
753 | struct il_ucode_header { | |
e7392364 | 754 | __le32 ver; /* major/minor/API/serial */ |
e94a4099 SG |
755 | struct { |
756 | __le32 inst_size; /* bytes of runtime code */ | |
757 | __le32 data_size; /* bytes of runtime data */ | |
758 | __le32 init_size; /* bytes of init code */ | |
759 | __le32 init_data_size; /* bytes of init data */ | |
760 | __le32 boot_size; /* bytes of bootstrap code */ | |
e7392364 | 761 | u8 data[0]; /* in same order as sizes */ |
e94a4099 SG |
762 | } v1; |
763 | }; | |
764 | ||
765 | struct il4965_ibss_seq { | |
766 | u8 mac[ETH_ALEN]; | |
767 | u16 seq_num; | |
768 | u16 frag_num; | |
769 | unsigned long packet_time; | |
770 | struct list_head list; | |
771 | }; | |
772 | ||
773 | struct il_sensitivity_ranges { | |
774 | u16 min_nrg_cck; | |
775 | u16 max_nrg_cck; | |
776 | ||
777 | u16 nrg_th_cck; | |
778 | u16 nrg_th_ofdm; | |
779 | ||
780 | u16 auto_corr_min_ofdm; | |
781 | u16 auto_corr_min_ofdm_mrc; | |
782 | u16 auto_corr_min_ofdm_x1; | |
783 | u16 auto_corr_min_ofdm_mrc_x1; | |
784 | ||
785 | u16 auto_corr_max_ofdm; | |
786 | u16 auto_corr_max_ofdm_mrc; | |
787 | u16 auto_corr_max_ofdm_x1; | |
788 | u16 auto_corr_max_ofdm_mrc_x1; | |
789 | ||
790 | u16 auto_corr_max_cck; | |
791 | u16 auto_corr_max_cck_mrc; | |
792 | u16 auto_corr_min_cck; | |
793 | u16 auto_corr_min_cck_mrc; | |
794 | ||
795 | u16 barker_corr_th_min; | |
796 | u16 barker_corr_th_min_mrc; | |
797 | u16 nrg_th_cca; | |
798 | }; | |
799 | ||
e94a4099 SG |
800 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
801 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
802 | ||
e94a4099 SG |
803 | /** |
804 | * struct il_hw_params | |
b16db50a | 805 | * @bcast_id: f/w broadcast station ID |
e94a4099 SG |
806 | * @max_txq_num: Max # Tx queues supported |
807 | * @dma_chnl_num: Number of Tx DMA/FIFO channels | |
808 | * @scd_bc_tbls_size: size of scheduler byte count tables | |
809 | * @tfd_size: TFD size | |
810 | * @tx/rx_chains_num: Number of TX/RX chains | |
811 | * @valid_tx/rx_ant: usable antennas | |
812 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) | |
813 | * @max_rxq_log: Log-base-2 of max_rxq_size | |
814 | * @rx_page_order: Rx buffer page order | |
815 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR | |
816 | * @max_stations: | |
817 | * @ht40_channel: is 40MHz width possible in band 2.4 | |
818 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) | |
819 | * @sw_crypto: 0 for hw, 1 for sw | |
820 | * @max_xxx_size: for ucode uses | |
821 | * @ct_kill_threshold: temperature threshold | |
822 | * @beacon_time_tsf_bits: number of valid tsf bits for beacon time | |
823 | * @struct il_sensitivity_ranges: range of sensitivity values | |
824 | */ | |
825 | struct il_hw_params { | |
b16db50a | 826 | u8 bcast_id; |
e94a4099 SG |
827 | u8 max_txq_num; |
828 | u8 dma_chnl_num; | |
829 | u16 scd_bc_tbls_size; | |
830 | u32 tfd_size; | |
e7392364 SG |
831 | u8 tx_chains_num; |
832 | u8 rx_chains_num; | |
833 | u8 valid_tx_ant; | |
834 | u8 valid_rx_ant; | |
e94a4099 SG |
835 | u16 max_rxq_size; |
836 | u16 max_rxq_log; | |
837 | u32 rx_page_order; | |
838 | u32 rx_wrt_ptr_reg; | |
e7392364 SG |
839 | u8 max_stations; |
840 | u8 ht40_channel; | |
841 | u8 max_beacon_itrvl; /* in 1024 ms */ | |
e94a4099 SG |
842 | u32 max_inst_size; |
843 | u32 max_data_size; | |
844 | u32 max_bsm_size; | |
e7392364 | 845 | u32 ct_kill_threshold; /* value in hw-dependent units */ |
e94a4099 SG |
846 | u16 beacon_time_tsf_bits; |
847 | const struct il_sensitivity_ranges *sens; | |
848 | }; | |
849 | ||
e94a4099 SG |
850 | /****************************************************************************** |
851 | * | |
852 | * Functions implemented in core module which are forward declared here | |
853 | * for use by iwl-[4-5].c | |
854 | * | |
855 | * NOTE: The implementation of these functions are not hardware specific | |
856 | * which is why they are in the core module files. | |
857 | * | |
858 | * Naming convention -- | |
859 | * il_ <-- Is part of iwlwifi | |
860 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) | |
861 | * il4965_bg_ <-- Called from work queue context | |
862 | * il4965_mac_ <-- mac80211 callback | |
863 | * | |
864 | ****************************************************************************/ | |
865 | extern void il4965_update_chain_flags(struct il_priv *il); | |
866 | extern const u8 il_bcast_addr[ETH_ALEN]; | |
867 | extern int il_queue_space(const struct il_queue *q); | |
e7392364 SG |
868 | static inline int |
869 | il_queue_used(const struct il_queue *q, int i) | |
e94a4099 | 870 | { |
e7392364 SG |
871 | return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr && |
872 | i < q->write_ptr) : !(i < | |
873 | q->read_ptr | |
874 | && i >= | |
875 | q-> | |
876 | write_ptr); | |
e94a4099 SG |
877 | } |
878 | ||
e7392364 SG |
879 | static inline u8 |
880 | il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge) | |
e94a4099 SG |
881 | { |
882 | /* | |
883 | * This is for init calibration result and scan command which | |
884 | * required buffer > TFD_MAX_PAYLOAD_SIZE, | |
885 | * the big buffer at end of command array | |
886 | */ | |
887 | if (is_huge) | |
888 | return q->n_win; /* must be power of 2 */ | |
889 | ||
890 | /* Otherwise, use normal size buffers */ | |
891 | return idx & (q->n_win - 1); | |
892 | } | |
893 | ||
e94a4099 SG |
894 | struct il_dma_ptr { |
895 | dma_addr_t dma; | |
896 | void *addr; | |
897 | size_t size; | |
898 | }; | |
899 | ||
900 | #define IL_OPERATION_MODE_AUTO 0 | |
901 | #define IL_OPERATION_MODE_HT_ONLY 1 | |
902 | #define IL_OPERATION_MODE_MIXED 2 | |
903 | #define IL_OPERATION_MODE_20MHZ 3 | |
904 | ||
905 | #define IL_TX_CRC_SIZE 4 | |
906 | #define IL_TX_DELIMITER_SIZE 4 | |
907 | ||
908 | #define TX_POWER_IL_ILLEGAL_VOLTAGE -10000 | |
909 | ||
910 | /* Sensitivity and chain noise calibration */ | |
911 | #define INITIALIZATION_VALUE 0xFFFF | |
912 | #define IL4965_CAL_NUM_BEACONS 20 | |
913 | #define IL_CAL_NUM_BEACONS 16 | |
914 | #define MAXIMUM_ALLOWED_PATHLOSS 15 | |
915 | ||
916 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 | |
917 | ||
918 | #define MAX_FA_OFDM 50 | |
919 | #define MIN_FA_OFDM 5 | |
920 | #define MAX_FA_CCK 50 | |
921 | #define MIN_FA_CCK 5 | |
922 | ||
923 | #define AUTO_CORR_STEP_OFDM 1 | |
924 | ||
925 | #define AUTO_CORR_STEP_CCK 3 | |
926 | #define AUTO_CORR_MAX_TH_CCK 160 | |
927 | ||
928 | #define NRG_DIFF 2 | |
929 | #define NRG_STEP_CCK 2 | |
930 | #define NRG_MARGIN 8 | |
931 | #define MAX_NUMBER_CCK_NO_FA 100 | |
932 | ||
933 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
934 | ||
935 | #define CHAIN_A 0 | |
936 | #define CHAIN_B 1 | |
937 | #define CHAIN_C 2 | |
938 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
939 | #define ALL_BAND_FILTER 0xFF00 | |
940 | #define IN_BAND_FILTER 0xFF | |
941 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
942 | ||
943 | #define NRG_NUM_PREV_STAT_L 20 | |
944 | #define NUM_RX_CHAINS 3 | |
945 | ||
946 | enum il4965_false_alarm_state { | |
947 | IL_FA_TOO_MANY = 0, | |
948 | IL_FA_TOO_FEW = 1, | |
949 | IL_FA_GOOD_RANGE = 2, | |
950 | }; | |
951 | ||
952 | enum il4965_chain_noise_state { | |
e7392364 | 953 | IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
e94a4099 SG |
954 | IL_CHAIN_NOISE_ACCUMULATE, |
955 | IL_CHAIN_NOISE_CALIBRATED, | |
956 | IL_CHAIN_NOISE_DONE, | |
957 | }; | |
958 | ||
959 | enum il4965_calib_enabled_state { | |
e7392364 | 960 | IL_CALIB_DISABLED = 0, /* must be 0 */ |
e94a4099 SG |
961 | IL_CALIB_ENABLED = 1, |
962 | }; | |
963 | ||
964 | /* | |
965 | * enum il_calib | |
966 | * defines the order in which results of initial calibrations | |
967 | * should be sent to the runtime uCode | |
968 | */ | |
969 | enum il_calib { | |
970 | IL_CALIB_MAX, | |
971 | }; | |
972 | ||
973 | /* Opaque calibration results */ | |
974 | struct il_calib_result { | |
975 | void *buf; | |
976 | size_t buf_len; | |
977 | }; | |
978 | ||
979 | enum ucode_type { | |
980 | UCODE_NONE = 0, | |
981 | UCODE_INIT, | |
982 | UCODE_RT | |
983 | }; | |
984 | ||
985 | /* Sensitivity calib data */ | |
986 | struct il_sensitivity_data { | |
987 | u32 auto_corr_ofdm; | |
988 | u32 auto_corr_ofdm_mrc; | |
989 | u32 auto_corr_ofdm_x1; | |
990 | u32 auto_corr_ofdm_mrc_x1; | |
991 | u32 auto_corr_cck; | |
992 | u32 auto_corr_cck_mrc; | |
993 | ||
994 | u32 last_bad_plcp_cnt_ofdm; | |
995 | u32 last_fa_cnt_ofdm; | |
996 | u32 last_bad_plcp_cnt_cck; | |
997 | u32 last_fa_cnt_cck; | |
998 | ||
999 | u32 nrg_curr_state; | |
1000 | u32 nrg_prev_state; | |
1001 | u32 nrg_value[10]; | |
e7392364 | 1002 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; |
e94a4099 SG |
1003 | u32 nrg_silence_ref; |
1004 | u32 nrg_energy_idx; | |
1005 | u32 nrg_silence_idx; | |
1006 | u32 nrg_th_cck; | |
1007 | s32 nrg_auto_corr_silence_diff; | |
1008 | u32 num_in_cck_no_fa; | |
1009 | u32 nrg_th_ofdm; | |
1010 | ||
1011 | u16 barker_corr_th_min; | |
1012 | u16 barker_corr_th_min_mrc; | |
1013 | u16 nrg_th_cca; | |
1014 | }; | |
1015 | ||
1016 | /* Chain noise (differential Rx gain) calib data */ | |
1017 | struct il_chain_noise_data { | |
1018 | u32 active_chains; | |
1019 | u32 chain_noise_a; | |
1020 | u32 chain_noise_b; | |
1021 | u32 chain_noise_c; | |
1022 | u32 chain_signal_a; | |
1023 | u32 chain_signal_b; | |
1024 | u32 chain_signal_c; | |
1025 | u16 beacon_count; | |
1026 | u8 disconn_array[NUM_RX_CHAINS]; | |
1027 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
1028 | u8 radio_write; | |
1029 | u8 state; | |
1030 | }; | |
1031 | ||
e7392364 | 1032 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
e94a4099 SG |
1033 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ |
1034 | ||
1035 | #define IL_TRAFFIC_ENTRIES (256) | |
1036 | #define IL_TRAFFIC_ENTRY_SIZE (64) | |
1037 | ||
1038 | enum { | |
1039 | MEASUREMENT_READY = (1 << 0), | |
1040 | MEASUREMENT_ACTIVE = (1 << 1), | |
1041 | }; | |
1042 | ||
1043 | /* interrupt stats */ | |
1044 | struct isr_stats { | |
1045 | u32 hw; | |
1046 | u32 sw; | |
1047 | u32 err_code; | |
1048 | u32 sch; | |
1049 | u32 alive; | |
1050 | u32 rfkill; | |
1051 | u32 ctkill; | |
1052 | u32 wakeup; | |
1053 | u32 rx; | |
1054 | u32 handlers[IL_CN_MAX]; | |
1055 | u32 tx; | |
1056 | u32 unhandled; | |
1057 | }; | |
1058 | ||
1059 | /* management stats */ | |
1060 | enum il_mgmt_stats { | |
1061 | MANAGEMENT_ASSOC_REQ = 0, | |
1062 | MANAGEMENT_ASSOC_RESP, | |
1063 | MANAGEMENT_REASSOC_REQ, | |
1064 | MANAGEMENT_REASSOC_RESP, | |
1065 | MANAGEMENT_PROBE_REQ, | |
1066 | MANAGEMENT_PROBE_RESP, | |
1067 | MANAGEMENT_BEACON, | |
1068 | MANAGEMENT_ATIM, | |
1069 | MANAGEMENT_DISASSOC, | |
1070 | MANAGEMENT_AUTH, | |
1071 | MANAGEMENT_DEAUTH, | |
1072 | MANAGEMENT_ACTION, | |
1073 | MANAGEMENT_MAX, | |
1074 | }; | |
1075 | /* control stats */ | |
1076 | enum il_ctrl_stats { | |
e7392364 | 1077 | CONTROL_BACK_REQ = 0, |
e94a4099 SG |
1078 | CONTROL_BACK, |
1079 | CONTROL_PSPOLL, | |
1080 | CONTROL_RTS, | |
1081 | CONTROL_CTS, | |
1082 | CONTROL_ACK, | |
1083 | CONTROL_CFEND, | |
1084 | CONTROL_CFENDACK, | |
1085 | CONTROL_MAX, | |
1086 | }; | |
1087 | ||
1088 | struct traffic_stats { | |
1089 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
1090 | u32 mgmt[MANAGEMENT_MAX]; | |
1091 | u32 ctrl[CONTROL_MAX]; | |
1092 | u32 data_cnt; | |
1093 | u64 data_bytes; | |
1094 | #endif | |
1095 | }; | |
1096 | ||
1097 | /* | |
1098 | * host interrupt timeout value | |
1099 | * used with setting interrupt coalescing timer | |
1100 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
1101 | * | |
1102 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
1103 | * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs | |
1104 | */ | |
1105 | #define IL_HOST_INT_TIMEOUT_MAX (0xFF) | |
1106 | #define IL_HOST_INT_TIMEOUT_DEF (0x40) | |
1107 | #define IL_HOST_INT_TIMEOUT_MIN (0x0) | |
1108 | #define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) | |
1109 | #define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) | |
1110 | #define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) | |
1111 | ||
1112 | #define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5) | |
1113 | ||
1114 | /* TX queue watchdog timeouts in mSecs */ | |
1115 | #define IL_DEF_WD_TIMEOUT (2000) | |
1116 | #define IL_LONG_WD_TIMEOUT (10000) | |
1117 | #define IL_MAX_WD_TIMEOUT (120000) | |
1118 | ||
1119 | struct il_force_reset { | |
1120 | int reset_request_count; | |
1121 | int reset_success_count; | |
1122 | int reset_reject_count; | |
1123 | unsigned long reset_duration; | |
1124 | unsigned long last_force_reset_jiffies; | |
1125 | }; | |
1126 | ||
1127 | /* extend beacon time format bit shifting */ | |
1128 | /* | |
1129 | * for _3945 devices | |
1130 | * bits 31:24 - extended | |
1131 | * bits 23:0 - interval | |
1132 | */ | |
1133 | #define IL3945_EXT_BEACON_TIME_POS 24 | |
1134 | /* | |
1135 | * for _4965 devices | |
1136 | * bits 31:22 - extended | |
1137 | * bits 21:0 - interval | |
1138 | */ | |
1139 | #define IL4965_EXT_BEACON_TIME_POS 22 | |
1140 | ||
1141 | struct il_rxon_context { | |
1142 | struct ieee80211_vif *vif; | |
e94a4099 SG |
1143 | }; |
1144 | ||
99412002 SG |
1145 | struct il_power_mgr { |
1146 | struct il_powertable_cmd sleep_cmd; | |
1147 | struct il_powertable_cmd sleep_cmd_next; | |
1148 | int debug_sleep_level_override; | |
1149 | bool pci_pm; | |
1150 | }; | |
1151 | ||
e94a4099 | 1152 | struct il_priv { |
e94a4099 SG |
1153 | struct ieee80211_hw *hw; |
1154 | struct ieee80211_channel *ieee_channels; | |
1155 | struct ieee80211_rate *ieee_rates; | |
93b7654e | 1156 | |
e94a4099 | 1157 | struct il_cfg *cfg; |
c39ae9fd | 1158 | const struct il_ops *ops; |
93b7654e SG |
1159 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
1160 | const struct il_debugfs_ops *debugfs_ops; | |
1161 | #endif | |
e94a4099 SG |
1162 | |
1163 | /* temporary frame storage list */ | |
1164 | struct list_head free_frames; | |
1165 | int frames_count; | |
1166 | ||
1167 | enum ieee80211_band band; | |
1168 | int alloc_rxb_page; | |
1169 | ||
1722f8e1 SG |
1170 | void (*handlers[IL_CN_MAX]) (struct il_priv *il, |
1171 | struct il_rx_buf *rxb); | |
e94a4099 SG |
1172 | |
1173 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; | |
1174 | ||
1175 | /* spectrum measurement report caching */ | |
1176 | struct il_spectrum_notification measure_report; | |
1177 | u8 measurement_status; | |
1178 | ||
1179 | /* ucode beacon time */ | |
1180 | u32 ucode_beacon_time; | |
1181 | int missed_beacon_threshold; | |
1182 | ||
1183 | /* track IBSS manager (last beacon) status */ | |
1184 | u32 ibss_manager; | |
1185 | ||
1186 | /* force reset */ | |
1187 | struct il_force_reset force_reset; | |
1188 | ||
1189 | /* we allocate array of il_channel_info for NIC's valid channels. | |
1190 | * Access via channel # using indirect idx array */ | |
1191 | struct il_channel_info *channel_info; /* channel info array */ | |
1192 | u8 channel_count; /* # of channels */ | |
1193 | ||
1194 | /* thermal calibration */ | |
1195 | s32 temperature; /* degrees Kelvin */ | |
1196 | s32 last_temperature; | |
1197 | ||
1198 | /* init calibration results */ | |
1199 | struct il_calib_result calib_results[IL_CALIB_MAX]; | |
1200 | ||
1201 | /* Scan related variables */ | |
1202 | unsigned long scan_start; | |
1203 | unsigned long scan_start_tsf; | |
1204 | void *scan_cmd; | |
1205 | enum ieee80211_band scan_band; | |
1206 | struct cfg80211_scan_request *scan_request; | |
1207 | struct ieee80211_vif *scan_vif; | |
1208 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; | |
1209 | u8 mgmt_tx_ant; | |
1210 | ||
1211 | /* spinlock */ | |
1212 | spinlock_t lock; /* protect general shared data */ | |
1213 | spinlock_t hcmd_lock; /* protect hcmd */ | |
1214 | spinlock_t reg_lock; /* protect hw register access */ | |
1215 | struct mutex mutex; | |
1216 | ||
1217 | /* basic pci-network driver stuff */ | |
1218 | struct pci_dev *pci_dev; | |
1219 | ||
1220 | /* pci hardware address support */ | |
1221 | void __iomem *hw_base; | |
e7392364 SG |
1222 | u32 hw_rev; |
1223 | u32 hw_wa_rev; | |
1224 | u8 rev_id; | |
e94a4099 SG |
1225 | |
1226 | /* command queue number */ | |
1227 | u8 cmd_queue; | |
1228 | ||
1229 | /* max number of station keys */ | |
1230 | u8 sta_key_max_num; | |
1231 | ||
1232 | /* EEPROM MAC addresses */ | |
1233 | struct mac_address addresses[1]; | |
1234 | ||
1235 | /* uCode images, save to reload in case of failure */ | |
e7392364 SG |
1236 | int fw_idx; /* firmware we're trying to load */ |
1237 | u32 ucode_ver; /* version of ucode, copy of | |
1238 | il_ucode.ver */ | |
e94a4099 SG |
1239 | struct fw_desc ucode_code; /* runtime inst */ |
1240 | struct fw_desc ucode_data; /* runtime data original */ | |
1241 | struct fw_desc ucode_data_backup; /* runtime data save/restore */ | |
1242 | struct fw_desc ucode_init; /* initialization inst */ | |
1243 | struct fw_desc ucode_init_data; /* initialization data */ | |
1244 | struct fw_desc ucode_boot; /* bootstrap inst */ | |
1245 | enum ucode_type ucode_type; | |
1246 | u8 ucode_write_complete; /* the image write is complete */ | |
1247 | char firmware_name[25]; | |
1248 | ||
83007196 | 1249 | struct ieee80211_vif *vif; |
e94a4099 | 1250 | |
8d44f2bd SG |
1251 | struct il_qos_info qos_data; |
1252 | ||
1c03c462 SG |
1253 | struct { |
1254 | bool enabled; | |
1255 | bool is_40mhz; | |
1256 | bool non_gf_sta_present; | |
1257 | u8 protection; | |
1258 | u8 extension_chan_offset; | |
1259 | } ht; | |
1260 | ||
c8b03958 SG |
1261 | /* |
1262 | * We declare this const so it can only be | |
1263 | * changed via explicit cast within the | |
1264 | * routines that actually update the physical | |
1265 | * hardware. | |
1266 | */ | |
1267 | const struct il_rxon_cmd active; | |
1268 | struct il_rxon_cmd staging; | |
1269 | ||
1270 | struct il_rxon_time_cmd timing; | |
1271 | ||
e94a4099 SG |
1272 | __le16 switch_channel; |
1273 | ||
1274 | /* 1st responses from initialize and runtime uCode images. | |
1275 | * _4965's initialize alive response contains some calibration data. */ | |
1276 | struct il_init_alive_resp card_alive_init; | |
1277 | struct il_alive_resp card_alive; | |
1278 | ||
1279 | u16 active_rate; | |
1280 | ||
1281 | u8 start_calib; | |
1282 | struct il_sensitivity_data sensitivity_data; | |
1283 | struct il_chain_noise_data chain_noise_data; | |
1284 | __le16 sensitivity_tbl[HD_TBL_SIZE]; | |
1285 | ||
1286 | struct il_ht_config current_ht_config; | |
1287 | ||
1288 | /* Rate scaling data */ | |
1289 | u8 retry_rate; | |
1290 | ||
1291 | wait_queue_head_t wait_command_queue; | |
1292 | ||
1293 | int activity_timer_active; | |
1294 | ||
1295 | /* Rx and Tx DMA processing queues */ | |
1296 | struct il_rx_queue rxq; | |
1297 | struct il_tx_queue *txq; | |
1298 | unsigned long txq_ctx_active_msk; | |
e7392364 SG |
1299 | struct il_dma_ptr kw; /* keep warm address */ |
1300 | struct il_dma_ptr scd_bc_tbls; | |
e94a4099 SG |
1301 | |
1302 | u32 scd_base_addr; /* scheduler sram base address */ | |
1303 | ||
1304 | unsigned long status; | |
1305 | ||
1306 | /* counts mgmt, ctl, and data packets */ | |
1307 | struct traffic_stats tx_stats; | |
1308 | struct traffic_stats rx_stats; | |
1309 | ||
1310 | /* counts interrupts */ | |
1311 | struct isr_stats isr_stats; | |
1312 | ||
1313 | struct il_power_mgr power_data; | |
1314 | ||
1315 | /* context information */ | |
e7392364 | 1316 | u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */ |
e94a4099 SG |
1317 | |
1318 | /* station table variables */ | |
1319 | ||
1320 | /* Note: if lock and sta_lock are needed, lock must be acquired first */ | |
1321 | spinlock_t sta_lock; | |
1322 | int num_stations; | |
1323 | struct il_station_entry stations[IL_STATION_COUNT]; | |
1324 | unsigned long ucode_key_table; | |
1325 | ||
1326 | /* queue refcounts */ | |
1327 | #define IL_MAX_HW_QUEUES 32 | |
1328 | unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)]; | |
1329 | /* for each AC */ | |
1330 | atomic_t queue_stop_count[4]; | |
1331 | ||
1332 | /* Indication if ieee80211_ops->open has been called */ | |
1333 | u8 is_open; | |
1334 | ||
1335 | u8 mac80211_registered; | |
1336 | ||
1337 | /* eeprom -- this is in the card's little endian byte order */ | |
1338 | u8 *eeprom; | |
1339 | struct il_eeprom_calib_info *calib_info; | |
1340 | ||
1341 | enum nl80211_iftype iw_mode; | |
1342 | ||
1343 | /* Last Rx'd beacon timestamp */ | |
1344 | u64 timestamp; | |
1345 | ||
1346 | union { | |
1347 | #if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE) | |
1348 | struct { | |
1349 | void *shared_virt; | |
1350 | dma_addr_t shared_phys; | |
1351 | ||
1352 | struct delayed_work thermal_periodic; | |
1353 | struct delayed_work rfkill_poll; | |
1354 | ||
1355 | struct il3945_notif_stats stats; | |
1356 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
1357 | struct il3945_notif_stats accum_stats; | |
1358 | struct il3945_notif_stats delta_stats; | |
1359 | struct il3945_notif_stats max_delta; | |
1360 | #endif | |
1361 | ||
1362 | u32 sta_supp_rates; | |
1363 | int last_rx_rssi; /* From Rx packet stats */ | |
1364 | ||
1365 | /* Rx'd packet timing information */ | |
1366 | u32 last_beacon_time; | |
1367 | u64 last_tsf; | |
1368 | ||
1369 | /* | |
1370 | * each calibration channel group in the | |
1371 | * EEPROM has a derived clip setting for | |
1372 | * each rate. | |
1373 | */ | |
1374 | const struct il3945_clip_group clip_groups[5]; | |
1375 | ||
1376 | } _3945; | |
1377 | #endif | |
1378 | #if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE) | |
1379 | struct { | |
1380 | struct il_rx_phy_res last_phy_res; | |
1381 | bool last_phy_res_valid; | |
1382 | ||
1383 | struct completion firmware_loading_complete; | |
1384 | ||
1385 | /* | |
1386 | * chain noise reset and gain commands are the | |
1387 | * two extra calibration commands follows the standard | |
1388 | * phy calibration commands | |
1389 | */ | |
1390 | u8 phy_calib_chain_noise_reset_cmd; | |
1391 | u8 phy_calib_chain_noise_gain_cmd; | |
1392 | ||
d735f921 SG |
1393 | u8 key_mapping_keys; |
1394 | struct il_wep_key wep_keys[WEP_KEYS_MAX]; | |
1395 | ||
e94a4099 SG |
1396 | struct il_notif_stats stats; |
1397 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
1398 | struct il_notif_stats accum_stats; | |
1399 | struct il_notif_stats delta_stats; | |
1400 | struct il_notif_stats max_delta; | |
1401 | #endif | |
1402 | ||
1403 | } _4965; | |
1404 | #endif | |
1405 | }; | |
1406 | ||
1407 | struct il_hw_params hw_params; | |
1408 | ||
1409 | u32 inta_mask; | |
1410 | ||
1411 | struct workqueue_struct *workqueue; | |
1412 | ||
1413 | struct work_struct restart; | |
1414 | struct work_struct scan_completed; | |
1415 | struct work_struct rx_replenish; | |
1416 | struct work_struct abort_scan; | |
1417 | ||
83007196 | 1418 | bool beacon_enabled; |
e94a4099 SG |
1419 | struct sk_buff *beacon_skb; |
1420 | ||
1421 | struct work_struct tx_flush; | |
1422 | ||
1423 | struct tasklet_struct irq_tasklet; | |
1424 | ||
1425 | struct delayed_work init_alive_start; | |
1426 | struct delayed_work alive_start; | |
1427 | struct delayed_work scan_check; | |
1428 | ||
1429 | /* TX Power */ | |
1430 | s8 tx_power_user_lmt; | |
1431 | s8 tx_power_device_lmt; | |
1432 | s8 tx_power_next; | |
1433 | ||
e94a4099 SG |
1434 | #ifdef CONFIG_IWLEGACY_DEBUG |
1435 | /* debugging info */ | |
e7392364 SG |
1436 | u32 debug_level; /* per device debugging will override global |
1437 | il_debug_level if set */ | |
1438 | #endif /* CONFIG_IWLEGACY_DEBUG */ | |
e94a4099 SG |
1439 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
1440 | /* debugfs */ | |
1441 | u16 tx_traffic_idx; | |
1442 | u16 rx_traffic_idx; | |
1443 | u8 *tx_traffic; | |
1444 | u8 *rx_traffic; | |
1445 | struct dentry *debugfs_dir; | |
1446 | u32 dbgfs_sram_offset, dbgfs_sram_len; | |
1447 | bool disable_ht40; | |
e7392364 | 1448 | #endif /* CONFIG_IWLEGACY_DEBUGFS */ |
e94a4099 SG |
1449 | |
1450 | struct work_struct txpower_work; | |
1451 | u32 disable_sens_cal; | |
1452 | u32 disable_chain_noise_cal; | |
1453 | u32 disable_tx_power_cal; | |
1454 | struct work_struct run_time_calib_work; | |
1455 | struct timer_list stats_periodic; | |
1456 | struct timer_list watchdog; | |
1457 | bool hw_ready; | |
1458 | ||
1459 | struct led_classdev led; | |
1460 | unsigned long blink_on, blink_off; | |
1461 | bool led_registered; | |
e7392364 | 1462 | }; /*il_priv */ |
e94a4099 | 1463 | |
e7392364 SG |
1464 | static inline void |
1465 | il_txq_ctx_activate(struct il_priv *il, int txq_id) | |
e94a4099 SG |
1466 | { |
1467 | set_bit(txq_id, &il->txq_ctx_active_msk); | |
1468 | } | |
1469 | ||
e7392364 SG |
1470 | static inline void |
1471 | il_txq_ctx_deactivate(struct il_priv *il, int txq_id) | |
e94a4099 SG |
1472 | { |
1473 | clear_bit(txq_id, &il->txq_ctx_active_msk); | |
1474 | } | |
1475 | ||
e7392364 SG |
1476 | static inline int |
1477 | il_is_associated(struct il_priv *il) | |
e94a4099 | 1478 | { |
c8b03958 | 1479 | return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; |
e94a4099 SG |
1480 | } |
1481 | ||
e7392364 SG |
1482 | static inline int |
1483 | il_is_any_associated(struct il_priv *il) | |
e94a4099 SG |
1484 | { |
1485 | return il_is_associated(il); | |
1486 | } | |
1487 | ||
e7392364 SG |
1488 | static inline int |
1489 | il_is_channel_valid(const struct il_channel_info *ch_info) | |
e94a4099 SG |
1490 | { |
1491 | if (ch_info == NULL) | |
1492 | return 0; | |
1493 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1494 | } | |
1495 | ||
e7392364 SG |
1496 | static inline int |
1497 | il_is_channel_radar(const struct il_channel_info *ch_info) | |
e94a4099 SG |
1498 | { |
1499 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1500 | } | |
1501 | ||
e7392364 SG |
1502 | static inline u8 |
1503 | il_is_channel_a_band(const struct il_channel_info *ch_info) | |
e94a4099 SG |
1504 | { |
1505 | return ch_info->band == IEEE80211_BAND_5GHZ; | |
1506 | } | |
1507 | ||
1508 | static inline int | |
1509 | il_is_channel_passive(const struct il_channel_info *ch) | |
1510 | { | |
1511 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1512 | } | |
1513 | ||
1514 | static inline int | |
1515 | il_is_channel_ibss(const struct il_channel_info *ch) | |
1516 | { | |
1517 | return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0; | |
1518 | } | |
be663ab6 | 1519 | |
e94a4099 SG |
1520 | static inline void |
1521 | __il_free_pages(struct il_priv *il, struct page *page) | |
1522 | { | |
1523 | __free_pages(page, il->hw_params.rx_page_order); | |
1524 | il->alloc_rxb_page--; | |
1525 | } | |
1526 | ||
e7392364 SG |
1527 | static inline void |
1528 | il_free_pages(struct il_priv *il, unsigned long page) | |
e94a4099 SG |
1529 | { |
1530 | free_pages(page, il->hw_params.rx_page_order); | |
1531 | il->alloc_rxb_page--; | |
1532 | } | |
be663ab6 WYG |
1533 | |
1534 | #define IWLWIFI_VERSION "in-tree:" | |
1535 | #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation" | |
1536 | #define DRV_AUTHOR "<ilw@linux.intel.com>" | |
1537 | ||
e2ebc833 | 1538 | #define IL_PCI_DEVICE(dev, subdev, cfg) \ |
be663ab6 WYG |
1539 | .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ |
1540 | .subvendor = PCI_ANY_ID, .subdevice = (subdev), \ | |
1541 | .driver_data = (kernel_ulong_t)&(cfg) | |
1542 | ||
1543 | #define TIME_UNIT 1024 | |
1544 | ||
e2ebc833 SG |
1545 | #define IL_SKU_G 0x1 |
1546 | #define IL_SKU_A 0x2 | |
1547 | #define IL_SKU_N 0x8 | |
be663ab6 | 1548 | |
e2ebc833 | 1549 | #define IL_CMD(x) case x: return #x |
be663ab6 | 1550 | |
e94a4099 | 1551 | /* Size of one Rx buffer in host DRAM */ |
e7392364 | 1552 | #define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */ |
e94a4099 SG |
1553 | #define IL_RX_BUF_SIZE_4K (4 * 1024) |
1554 | #define IL_RX_BUF_SIZE_8K (8 * 1024) | |
1555 | ||
9b5e2f46 | 1556 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
e2ebc833 | 1557 | struct il_debugfs_ops { |
1722f8e1 SG |
1558 | ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf, |
1559 | size_t count, loff_t *ppos); | |
1560 | ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf, | |
1561 | size_t count, loff_t *ppos); | |
1562 | ssize_t(*general_stats_read) (struct file *file, | |
1563 | char __user *user_buf, size_t count, | |
1564 | loff_t *ppos); | |
be663ab6 | 1565 | }; |
9b5e2f46 | 1566 | #endif |
be663ab6 | 1567 | |
1600b875 | 1568 | struct il_ops { |
be663ab6 | 1569 | /* Handling TX */ |
1722f8e1 SG |
1570 | void (*txq_update_byte_cnt_tbl) (struct il_priv *il, |
1571 | struct il_tx_queue *txq, | |
e7392364 | 1572 | u16 byte_cnt); |
1722f8e1 SG |
1573 | int (*txq_attach_buf_to_tfd) (struct il_priv *il, |
1574 | struct il_tx_queue *txq, dma_addr_t addr, | |
e7392364 | 1575 | u16 len, u8 reset, u8 pad); |
1722f8e1 SG |
1576 | void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq); |
1577 | int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq); | |
be663ab6 | 1578 | /* alive notification after init uCode load */ |
1722f8e1 | 1579 | void (*init_alive_start) (struct il_priv *il); |
be663ab6 | 1580 | /* check validity of rtc data address */ |
e7392364 | 1581 | int (*is_valid_rtc_data_addr) (u32 addr); |
be663ab6 | 1582 | /* 1st ucode load */ |
1722f8e1 | 1583 | int (*load_ucode) (struct il_priv *il); |
1ba2f121 | 1584 | |
1722f8e1 SG |
1585 | void (*dump_nic_error_log) (struct il_priv *il); |
1586 | int (*dump_fh) (struct il_priv *il, char **buf, bool display); | |
1587 | int (*set_channel_switch) (struct il_priv *il, | |
1588 | struct ieee80211_channel_switch *ch_switch); | |
be663ab6 | 1589 | /* power management */ |
f03ee2a8 | 1590 | int (*apm_init) (struct il_priv *il); |
be663ab6 | 1591 | |
f03ee2a8 | 1592 | /* tx power */ |
1722f8e1 SG |
1593 | int (*send_tx_power) (struct il_priv *il); |
1594 | void (*update_chain_flags) (struct il_priv *il); | |
be663ab6 | 1595 | |
47ef694d | 1596 | /* eeprom operations */ |
a89268e8 SG |
1597 | int (*eeprom_acquire_semaphore) (struct il_priv *il); |
1598 | void (*eeprom_release_semaphore) (struct il_priv *il); | |
be663ab6 | 1599 | |
c9363551 SG |
1600 | int (*rxon_assoc) (struct il_priv *il); |
1601 | int (*commit_rxon) (struct il_priv *il); | |
1602 | void (*set_rxon_chain) (struct il_priv *il); | |
1603 | ||
1604 | u16(*get_hcmd_size) (u8 cmd_id, u16 len); | |
1605 | u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data); | |
1606 | ||
1607 | int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif); | |
1608 | void (*post_scan) (struct il_priv *il); | |
1609 | void (*post_associate) (struct il_priv *il); | |
1610 | void (*config_ap) (struct il_priv *il); | |
1611 | /* station management */ | |
1612 | int (*update_bcast_stations) (struct il_priv *il); | |
1613 | int (*manage_ibss_station) (struct il_priv *il, | |
1614 | struct ieee80211_vif *vif, bool add); | |
1615 | ||
1616 | int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd); | |
be663ab6 WYG |
1617 | }; |
1618 | ||
e2ebc833 | 1619 | struct il_mod_params { |
be663ab6 WYG |
1620 | int sw_crypto; /* def: 0 = using hardware encryption */ |
1621 | int disable_hw_scan; /* def: 0 = use h/w scan */ | |
1622 | int num_of_queues; /* def: HW dependent */ | |
1623 | int disable_11n; /* def: 0 = 11n capabilities enabled */ | |
1624 | int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */ | |
e7392364 | 1625 | int antenna; /* def: 0 = both antennas (use diversity) */ |
be663ab6 WYG |
1626 | int restart_fw; /* def: 1 = restart firmware */ |
1627 | }; | |
1628 | ||
47ef694d SG |
1629 | #define IL_LED_SOLID 11 |
1630 | #define IL_DEF_LED_INTRVL cpu_to_le32(1000) | |
1631 | ||
1632 | #define IL_LED_ACTIVITY (0<<1) | |
1633 | #define IL_LED_LINK (1<<1) | |
1634 | ||
1635 | /* | |
1636 | * LED mode | |
1637 | * IL_LED_DEFAULT: use device default | |
1638 | * IL_LED_RF_STATE: turn LED on/off based on RF state | |
1639 | * LED ON = RF ON | |
1640 | * LED OFF = RF OFF | |
1641 | * IL_LED_BLINK: adjust led blink rate based on blink table | |
1642 | */ | |
1643 | enum il_led_mode { | |
1644 | IL_LED_DEFAULT, | |
1645 | IL_LED_RF_STATE, | |
1646 | IL_LED_BLINK, | |
1647 | }; | |
1648 | ||
1649 | void il_leds_init(struct il_priv *il); | |
1650 | void il_leds_exit(struct il_priv *il); | |
1651 | ||
be663ab6 | 1652 | /** |
e2ebc833 | 1653 | * struct il_cfg |
be663ab6 WYG |
1654 | * @fw_name_pre: Firmware filename prefix. The api version and extension |
1655 | * (.ucode) will be added to filename before loading from disk. The | |
1656 | * filename is constructed as fw_name_pre<api>.ucode. | |
1657 | * @ucode_api_max: Highest version of uCode API supported by driver. | |
1658 | * @ucode_api_min: Lowest version of uCode API supported by driver. | |
1659 | * @scan_antennas: available antenna for scan operation | |
1660 | * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off) | |
1661 | * | |
1662 | * We enable the driver to be backward compatible wrt API version. The | |
1663 | * driver specifies which APIs it supports (with @ucode_api_max being the | |
1664 | * highest and @ucode_api_min the lowest). Firmware will only be loaded if | |
1665 | * it has a supported API version. The firmware's API version will be | |
e2ebc833 | 1666 | * stored in @il_priv, enabling the driver to make runtime changes based |
be663ab6 WYG |
1667 | * on firmware version used. |
1668 | * | |
1669 | * For example, | |
46bc8d4b | 1670 | * if (IL_UCODE_API(il->ucode_ver) >= 2) { |
be663ab6 WYG |
1671 | * Driver interacts with Firmware API version >= 2. |
1672 | * } else { | |
1673 | * Driver interacts with Firmware API version 1. | |
1674 | * } | |
1675 | * | |
1676 | * The ideal usage of this infrastructure is to treat a new ucode API | |
1677 | * release as a new hardware revision. That is, through utilizing the | |
e2ebc833 | 1678 | * il_hcmd_utils_ops etc. we accommodate different command structures |
be663ab6 WYG |
1679 | * and flows between hardware versions as well as their API |
1680 | * versions. | |
1681 | * | |
1682 | */ | |
e2ebc833 | 1683 | struct il_cfg { |
be663ab6 WYG |
1684 | /* params specific to an individual device within a device family */ |
1685 | const char *name; | |
1686 | const char *fw_name_pre; | |
1687 | const unsigned int ucode_api_max; | |
1688 | const unsigned int ucode_api_min; | |
e7392364 SG |
1689 | u8 valid_tx_ant; |
1690 | u8 valid_rx_ant; | |
be663ab6 | 1691 | unsigned int sku; |
e7392364 SG |
1692 | u16 eeprom_ver; |
1693 | u16 eeprom_calib_ver; | |
be663ab6 | 1694 | /* module based parameters which can be set from modprobe cmd */ |
e2ebc833 | 1695 | const struct il_mod_params *mod_params; |
be663ab6 | 1696 | /* params not likely to change within a device family */ |
e2ebc833 | 1697 | struct il_base_params *base_params; |
be663ab6 WYG |
1698 | /* params likely to change within a device family */ |
1699 | u8 scan_rx_antennas[IEEE80211_NUM_BANDS]; | |
e2ebc833 | 1700 | enum il_led_mode led_mode; |
89ef1ed2 SG |
1701 | |
1702 | int eeprom_size; | |
1703 | int num_of_queues; /* def: HW dependent */ | |
1704 | int num_of_ampdu_queues; /* def: HW dependent */ | |
1705 | /* for il_apm_init() */ | |
1706 | u32 pll_cfg_val; | |
1707 | bool set_l0s; | |
1708 | bool use_bsm; | |
1709 | ||
1710 | u16 led_compensation; | |
1711 | int chain_noise_num_beacons; | |
1712 | unsigned int wd_timeout; | |
1713 | bool temperature_kelvin; | |
1714 | const bool ucode_tracing; | |
1715 | const bool sensitivity_calib_by_driver; | |
1716 | const bool chain_noise_calib_by_driver; | |
93a984a4 SG |
1717 | |
1718 | const u32 regulatory_bands[7]; | |
be663ab6 WYG |
1719 | }; |
1720 | ||
1721 | /*************************** | |
1722 | * L i b * | |
1723 | ***************************/ | |
1724 | ||
e7392364 SG |
1725 | int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1726 | u16 queue, const struct ieee80211_tx_queue_params *params); | |
e2ebc833 | 1727 | int il_mac_tx_last_beacon(struct ieee80211_hw *hw); |
e7392364 | 1728 | |
83007196 SG |
1729 | void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt); |
1730 | int il_check_rxon_cmd(struct il_priv *il); | |
1731 | int il_full_rxon_required(struct il_priv *il); | |
1732 | int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch); | |
1733 | void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band, | |
1734 | struct ieee80211_vif *vif); | |
e7392364 SG |
1735 | u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band); |
1736 | void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf); | |
83007196 | 1737 | bool il_is_ht40_tx_allowed(struct il_priv *il, |
e7392364 | 1738 | struct ieee80211_sta_ht_cap *ht_cap); |
83007196 | 1739 | void il_connection_init_rx_config(struct il_priv *il); |
46bc8d4b | 1740 | void il_set_rate(struct il_priv *il); |
e7392364 SG |
1741 | int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr, |
1742 | u32 decrypt_res, struct ieee80211_rx_status *stats); | |
46bc8d4b | 1743 | void il_irq_handle_error(struct il_priv *il); |
e7392364 | 1744 | int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif); |
e2ebc833 | 1745 | void il_mac_remove_interface(struct ieee80211_hw *hw, |
e7392364 SG |
1746 | struct ieee80211_vif *vif); |
1747 | int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
1748 | enum nl80211_iftype newtype, bool newp2p); | |
46bc8d4b | 1749 | int il_alloc_txq_mem(struct il_priv *il); |
6668e4eb | 1750 | void il_free_txq_mem(struct il_priv *il); |
be663ab6 | 1751 | |
d3175167 | 1752 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
288f9954 | 1753 | extern void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len); |
be663ab6 | 1754 | #else |
e7392364 SG |
1755 | static inline void |
1756 | il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len) | |
be663ab6 WYG |
1757 | { |
1758 | } | |
1759 | #endif | |
288f9954 | 1760 | |
be663ab6 | 1761 | /***************************************************** |
288f9954 SG |
1762 | * Handlers |
1763 | ***************************************************/ | |
e7392364 SG |
1764 | void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb); |
1765 | void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb); | |
1766 | void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb); | |
288f9954 | 1767 | void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb); |
be663ab6 WYG |
1768 | |
1769 | /***************************************************** | |
1770 | * RX | |
1771 | ******************************************************/ | |
46bc8d4b SG |
1772 | void il_cmd_queue_unmap(struct il_priv *il); |
1773 | void il_cmd_queue_free(struct il_priv *il); | |
1774 | int il_rx_queue_alloc(struct il_priv *il); | |
e7392364 | 1775 | void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q); |
e2ebc833 | 1776 | int il_rx_queue_space(const struct il_rx_queue *q); |
e7392364 | 1777 | void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb); |
288f9954 | 1778 | |
e7392364 SG |
1779 | void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb); |
1780 | void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt); | |
46bc8d4b | 1781 | void il_chswitch_done(struct il_priv *il, bool is_success); |
be663ab6 WYG |
1782 | |
1783 | /***************************************************** | |
1784 | * TX | |
1785 | ******************************************************/ | |
d87c771f SG |
1786 | extern void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq); |
1787 | extern int il_tx_queue_init(struct il_priv *il, u32 txq_id); | |
1788 | extern void il_tx_queue_reset(struct il_priv *il, u32 txq_id); | |
1789 | extern void il_tx_queue_unmap(struct il_priv *il, int txq_id); | |
1790 | extern void il_tx_queue_free(struct il_priv *il, int txq_id); | |
1791 | extern void il_setup_watchdog(struct il_priv *il); | |
be663ab6 WYG |
1792 | /***************************************************** |
1793 | * TX power | |
1794 | ****************************************************/ | |
46bc8d4b | 1795 | int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force); |
be663ab6 WYG |
1796 | |
1797 | /******************************************************************************* | |
1798 | * Rate | |
1799 | ******************************************************************************/ | |
1800 | ||
83007196 | 1801 | u8 il_get_lowest_plcp(struct il_priv *il); |
be663ab6 WYG |
1802 | |
1803 | /******************************************************************************* | |
1804 | * Scanning | |
1805 | ******************************************************************************/ | |
46bc8d4b SG |
1806 | void il_init_scan_params(struct il_priv *il); |
1807 | int il_scan_cancel(struct il_priv *il); | |
1808 | int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms); | |
1809 | void il_force_scan_end(struct il_priv *il); | |
e7392364 SG |
1810 | int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1811 | struct cfg80211_scan_request *req); | |
46bc8d4b SG |
1812 | void il_internal_short_hw_scan(struct il_priv *il); |
1813 | int il_force_reset(struct il_priv *il, bool external); | |
e7392364 | 1814 | u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame, |
1722f8e1 | 1815 | const u8 *ta, const u8 *ie, int ie_len, int left); |
46bc8d4b | 1816 | void il_setup_rx_scan_handlers(struct il_priv *il); |
e7392364 SG |
1817 | u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band, |
1818 | u8 n_probes); | |
1819 | u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band, | |
1820 | struct ieee80211_vif *vif); | |
46bc8d4b SG |
1821 | void il_setup_scan_deferred_work(struct il_priv *il); |
1822 | void il_cancel_scan_deferred_work(struct il_priv *il); | |
be663ab6 WYG |
1823 | |
1824 | /* For faster active scanning, scan will move to the next channel if fewer than | |
1825 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
1826 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
1827 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
1828 | * no other traffic). | |
1829 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
e7392364 SG |
1830 | #define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */ |
1831 | #define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */ | |
be663ab6 | 1832 | |
e2ebc833 | 1833 | #define IL_SCAN_CHECK_WATCHDOG (HZ * 7) |
be663ab6 WYG |
1834 | |
1835 | /***************************************************** | |
1836 | * S e n d i n g H o s t C o m m a n d s * | |
1837 | *****************************************************/ | |
1838 | ||
e2ebc833 | 1839 | const char *il_get_cmd_string(u8 cmd); |
e7392364 | 1840 | int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd); |
46bc8d4b | 1841 | int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd); |
e7392364 SG |
1842 | int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, |
1843 | const void *data); | |
1844 | int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data, | |
1722f8e1 SG |
1845 | void (*callback) (struct il_priv *il, |
1846 | struct il_device_cmd *cmd, | |
1847 | struct il_rx_pkt *pkt)); | |
be663ab6 | 1848 | |
46bc8d4b | 1849 | int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd); |
be663ab6 | 1850 | |
be663ab6 WYG |
1851 | /***************************************************** |
1852 | * PCI * | |
1853 | *****************************************************/ | |
1854 | ||
e7392364 SG |
1855 | static inline u16 |
1856 | il_pcie_link_ctl(struct il_priv *il) | |
be663ab6 WYG |
1857 | { |
1858 | int pos; | |
1859 | u16 pci_lnk_ctl; | |
46bc8d4b SG |
1860 | pos = pci_pcie_cap(il->pci_dev); |
1861 | pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl); | |
be663ab6 WYG |
1862 | return pci_lnk_ctl; |
1863 | } | |
1864 | ||
e2ebc833 | 1865 | void il_bg_watchdog(unsigned long data); |
e7392364 SG |
1866 | u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval); |
1867 | __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, | |
1868 | u32 beacon_interval); | |
be663ab6 WYG |
1869 | |
1870 | #ifdef CONFIG_PM | |
e2ebc833 SG |
1871 | int il_pci_suspend(struct device *device); |
1872 | int il_pci_resume(struct device *device); | |
1873 | extern const struct dev_pm_ops il_pm_ops; | |
be663ab6 | 1874 | |
e2ebc833 | 1875 | #define IL_LEGACY_PM_OPS (&il_pm_ops) |
be663ab6 WYG |
1876 | |
1877 | #else /* !CONFIG_PM */ | |
1878 | ||
e2ebc833 | 1879 | #define IL_LEGACY_PM_OPS NULL |
be663ab6 WYG |
1880 | |
1881 | #endif /* !CONFIG_PM */ | |
1882 | ||
1883 | /***************************************************** | |
1884 | * Error Handling Debugging | |
1885 | ******************************************************/ | |
46bc8d4b | 1886 | void il4965_dump_nic_error_log(struct il_priv *il); |
d3175167 | 1887 | #ifdef CONFIG_IWLEGACY_DEBUG |
83007196 | 1888 | void il_print_rx_config_cmd(struct il_priv *il); |
be663ab6 | 1889 | #else |
e7392364 | 1890 | static inline void |
83007196 | 1891 | il_print_rx_config_cmd(struct il_priv *il) |
be663ab6 WYG |
1892 | { |
1893 | } | |
1894 | #endif | |
1895 | ||
46bc8d4b | 1896 | void il_clear_isr_stats(struct il_priv *il); |
be663ab6 WYG |
1897 | |
1898 | /***************************************************** | |
1899 | * GEOS | |
1900 | ******************************************************/ | |
46bc8d4b SG |
1901 | int il_init_geos(struct il_priv *il); |
1902 | void il_free_geos(struct il_priv *il); | |
be663ab6 WYG |
1903 | |
1904 | /*************** DRIVER STATUS FUNCTIONS *****/ | |
1905 | ||
a6766ccd SG |
1906 | #define S_HCMD_ACTIVE 0 /* host command in progress */ |
1907 | /* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */ | |
1908 | #define S_INT_ENABLED 2 | |
bc269a8e | 1909 | #define S_RFKILL 3 |
a6766ccd SG |
1910 | #define S_CT_KILL 4 |
1911 | #define S_INIT 5 | |
1912 | #define S_ALIVE 6 | |
1913 | #define S_READY 7 | |
1914 | #define S_TEMPERATURE 8 | |
1915 | #define S_GEO_CONFIGURED 9 | |
1916 | #define S_EXIT_PENDING 10 | |
db7746f7 | 1917 | #define S_STATS 12 |
a6766ccd SG |
1918 | #define S_SCANNING 13 |
1919 | #define S_SCAN_ABORTING 14 | |
1920 | #define S_SCAN_HW 15 | |
1921 | #define S_POWER_PMI 16 | |
1922 | #define S_FW_ERROR 17 | |
1923 | #define S_CHANNEL_SWITCH_PENDING 18 | |
be663ab6 | 1924 | |
e7392364 SG |
1925 | static inline int |
1926 | il_is_ready(struct il_priv *il) | |
be663ab6 WYG |
1927 | { |
1928 | /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are | |
1929 | * set but EXIT_PENDING is not */ | |
a6766ccd | 1930 | return test_bit(S_READY, &il->status) && |
e7392364 SG |
1931 | test_bit(S_GEO_CONFIGURED, &il->status) && |
1932 | !test_bit(S_EXIT_PENDING, &il->status); | |
be663ab6 WYG |
1933 | } |
1934 | ||
e7392364 SG |
1935 | static inline int |
1936 | il_is_alive(struct il_priv *il) | |
be663ab6 | 1937 | { |
a6766ccd | 1938 | return test_bit(S_ALIVE, &il->status); |
be663ab6 WYG |
1939 | } |
1940 | ||
e7392364 SG |
1941 | static inline int |
1942 | il_is_init(struct il_priv *il) | |
be663ab6 | 1943 | { |
a6766ccd | 1944 | return test_bit(S_INIT, &il->status); |
be663ab6 WYG |
1945 | } |
1946 | ||
e7392364 SG |
1947 | static inline int |
1948 | il_is_rfkill_hw(struct il_priv *il) | |
be663ab6 | 1949 | { |
bc269a8e | 1950 | return test_bit(S_RFKILL, &il->status); |
be663ab6 WYG |
1951 | } |
1952 | ||
e7392364 SG |
1953 | static inline int |
1954 | il_is_rfkill(struct il_priv *il) | |
be663ab6 | 1955 | { |
46bc8d4b | 1956 | return il_is_rfkill_hw(il); |
be663ab6 WYG |
1957 | } |
1958 | ||
e7392364 SG |
1959 | static inline int |
1960 | il_is_ctkill(struct il_priv *il) | |
be663ab6 | 1961 | { |
a6766ccd | 1962 | return test_bit(S_CT_KILL, &il->status); |
be663ab6 WYG |
1963 | } |
1964 | ||
e7392364 SG |
1965 | static inline int |
1966 | il_is_ready_rf(struct il_priv *il) | |
be663ab6 WYG |
1967 | { |
1968 | ||
46bc8d4b | 1969 | if (il_is_rfkill(il)) |
be663ab6 WYG |
1970 | return 0; |
1971 | ||
46bc8d4b | 1972 | return il_is_ready(il); |
be663ab6 WYG |
1973 | } |
1974 | ||
46bc8d4b | 1975 | extern void il_send_bt_config(struct il_priv *il); |
e7392364 | 1976 | extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear); |
775ed8ab SG |
1977 | extern void il_apm_stop(struct il_priv *il); |
1978 | extern void _il_apm_stop(struct il_priv *il); | |
1979 | ||
46bc8d4b | 1980 | int il_apm_init(struct il_priv *il); |
be663ab6 | 1981 | |
83007196 SG |
1982 | int il_send_rxon_timing(struct il_priv *il); |
1983 | ||
e7392364 | 1984 | static inline int |
83007196 | 1985 | il_send_rxon_assoc(struct il_priv *il) |
be663ab6 | 1986 | { |
c9363551 | 1987 | return il->ops->rxon_assoc(il); |
be663ab6 | 1988 | } |
e7392364 SG |
1989 | |
1990 | static inline int | |
83007196 | 1991 | il_commit_rxon(struct il_priv *il) |
be663ab6 | 1992 | { |
c9363551 | 1993 | return il->ops->commit_rxon(il); |
be663ab6 | 1994 | } |
e7392364 SG |
1995 | |
1996 | static inline const struct ieee80211_supported_band * | |
1997 | il_get_hw_mode(struct il_priv *il, enum ieee80211_band band) | |
be663ab6 | 1998 | { |
46bc8d4b | 1999 | return il->hw->wiphy->bands[band]; |
be663ab6 WYG |
2000 | } |
2001 | ||
be663ab6 | 2002 | /* mac80211 handlers */ |
e2ebc833 | 2003 | int il_mac_config(struct ieee80211_hw *hw, u32 changed); |
e7392364 SG |
2004 | void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif); |
2005 | void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
2006 | struct ieee80211_bss_conf *bss_conf, u32 changes); | |
2007 | void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info, | |
1722f8e1 | 2008 | __le16 fc, __le32 *tx_flags); |
be663ab6 | 2009 | |
e2ebc833 | 2010 | irqreturn_t il_isr(int irq, void *data); |
be663ab6 | 2011 | |
17d4eca6 SG |
2012 | extern void il_set_bit(struct il_priv *p, u32 r, u32 m); |
2013 | extern void il_clear_bit(struct il_priv *p, u32 r, u32 m); | |
1e0f32a4 | 2014 | extern bool _il_grab_nic_access(struct il_priv *il); |
17d4eca6 SG |
2015 | extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout); |
2016 | extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout); | |
2017 | extern u32 il_rd_prph(struct il_priv *il, u32 reg); | |
2018 | extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val); | |
2019 | extern u32 il_read_targ_mem(struct il_priv *il, u32 addr); | |
2020 | extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val); | |
e94a4099 | 2021 | |
e7392364 SG |
2022 | static inline void |
2023 | _il_write8(struct il_priv *il, u32 ofs, u8 val) | |
e94a4099 | 2024 | { |
a5f16137 | 2025 | writeb(val, il->hw_base + ofs); |
e94a4099 SG |
2026 | } |
2027 | #define il_write8(il, ofs, val) _il_write8(il, ofs, val) | |
2028 | ||
e7392364 SG |
2029 | static inline void |
2030 | _il_wr(struct il_priv *il, u32 ofs, u32 val) | |
e94a4099 | 2031 | { |
a5f16137 | 2032 | writel(val, il->hw_base + ofs); |
e94a4099 SG |
2033 | } |
2034 | ||
e7392364 SG |
2035 | static inline u32 |
2036 | _il_rd(struct il_priv *il, u32 ofs) | |
e94a4099 | 2037 | { |
a5f16137 | 2038 | return readl(il->hw_base + ofs); |
e94a4099 SG |
2039 | } |
2040 | ||
e94a4099 SG |
2041 | static inline void |
2042 | _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) | |
2043 | { | |
2044 | _il_wr(il, reg, _il_rd(il, reg) & ~mask); | |
2045 | } | |
2046 | ||
e7392364 | 2047 | static inline void |
17d4eca6 | 2048 | _il_set_bit(struct il_priv *il, u32 reg, u32 mask) |
e94a4099 | 2049 | { |
17d4eca6 | 2050 | _il_wr(il, reg, _il_rd(il, reg) | mask); |
e94a4099 SG |
2051 | } |
2052 | ||
e7392364 SG |
2053 | static inline void |
2054 | _il_release_nic_access(struct il_priv *il) | |
e94a4099 | 2055 | { |
e7392364 | 2056 | _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
4e5ea208 SG |
2057 | /* |
2058 | * In above we are reading CSR_GP_CNTRL register, what will flush any | |
2059 | * previous writes, but still want write, which clear MAC_ACCESS_REQ | |
2060 | * bit, be performed on PCI bus before any other writes scheduled on | |
2061 | * different CPUs (after we drop reg_lock). | |
2062 | */ | |
2063 | mmiowb(); | |
e94a4099 SG |
2064 | } |
2065 | ||
e7392364 SG |
2066 | static inline u32 |
2067 | il_rd(struct il_priv *il, u32 reg) | |
e94a4099 SG |
2068 | { |
2069 | u32 value; | |
2070 | unsigned long reg_flags; | |
2071 | ||
2072 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
2073 | _il_grab_nic_access(il); | |
2074 | value = _il_rd(il, reg); | |
2075 | _il_release_nic_access(il); | |
2076 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
2077 | return value; | |
e94a4099 SG |
2078 | } |
2079 | ||
2080 | static inline void | |
2081 | il_wr(struct il_priv *il, u32 reg, u32 value) | |
2082 | { | |
2083 | unsigned long reg_flags; | |
2084 | ||
2085 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 | 2086 | if (likely(_il_grab_nic_access(il))) { |
e94a4099 SG |
2087 | _il_wr(il, reg, value); |
2088 | _il_release_nic_access(il); | |
2089 | } | |
2090 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
2091 | } | |
2092 | ||
e7392364 SG |
2093 | static inline u32 |
2094 | _il_rd_prph(struct il_priv *il, u32 reg) | |
e94a4099 SG |
2095 | { |
2096 | _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); | |
e94a4099 SG |
2097 | return _il_rd(il, HBUS_TARG_PRPH_RDAT); |
2098 | } | |
2099 | ||
e7392364 SG |
2100 | static inline void |
2101 | _il_wr_prph(struct il_priv *il, u32 addr, u32 val) | |
e94a4099 | 2102 | { |
e7392364 | 2103 | _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24))); |
e94a4099 SG |
2104 | _il_wr(il, HBUS_TARG_PRPH_WDAT, val); |
2105 | } | |
2106 | ||
e94a4099 SG |
2107 | static inline void |
2108 | il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask) | |
2109 | { | |
2110 | unsigned long reg_flags; | |
2111 | ||
2112 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 SG |
2113 | if (likely(_il_grab_nic_access(il))) { |
2114 | _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask)); | |
2115 | _il_release_nic_access(il); | |
2116 | } | |
e94a4099 SG |
2117 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2118 | } | |
2119 | ||
e7392364 SG |
2120 | static inline void |
2121 | il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) | |
e94a4099 SG |
2122 | { |
2123 | unsigned long reg_flags; | |
2124 | ||
2125 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 SG |
2126 | if (likely(_il_grab_nic_access(il))) { |
2127 | _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits)); | |
2128 | _il_release_nic_access(il); | |
2129 | } | |
e94a4099 SG |
2130 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2131 | } | |
2132 | ||
e7392364 SG |
2133 | static inline void |
2134 | il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask) | |
e94a4099 SG |
2135 | { |
2136 | unsigned long reg_flags; | |
2137 | u32 val; | |
2138 | ||
2139 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 SG |
2140 | if (likely(_il_grab_nic_access(il))) { |
2141 | val = _il_rd_prph(il, reg); | |
2142 | _il_wr_prph(il, reg, (val & ~mask)); | |
2143 | _il_release_nic_access(il); | |
2144 | } | |
e94a4099 SG |
2145 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2146 | } | |
2147 | ||
e94a4099 SG |
2148 | #define HW_KEY_DYNAMIC 0 |
2149 | #define HW_KEY_DEFAULT 1 | |
2150 | ||
e7392364 SG |
2151 | #define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */ |
2152 | #define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */ | |
2153 | #define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of | |
2154 | being activated */ | |
2155 | #define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211; | |
2156 | (this is for the IBSS BSSID stations) */ | |
2157 | #define IL_STA_BCAST BIT(4) /* this station is the special bcast station */ | |
e94a4099 | 2158 | |
83007196 SG |
2159 | void il_restore_stations(struct il_priv *il); |
2160 | void il_clear_ucode_stations(struct il_priv *il); | |
e94a4099 SG |
2161 | void il_dealloc_bcast_stations(struct il_priv *il); |
2162 | int il_get_free_ucode_key_idx(struct il_priv *il); | |
e7392364 | 2163 | int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags); |
83007196 | 2164 | int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap, |
1722f8e1 | 2165 | struct ieee80211_sta *sta, u8 *sta_id_r); |
e7392364 SG |
2166 | int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr); |
2167 | int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
2168 | struct ieee80211_sta *sta); | |
2169 | ||
83007196 SG |
2170 | u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap, |
2171 | struct ieee80211_sta *sta); | |
e7392364 | 2172 | |
83007196 SG |
2173 | int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq, |
2174 | u8 flags, bool init); | |
e94a4099 SG |
2175 | |
2176 | /** | |
2177 | * il_clear_driver_stations - clear knowledge of all stations from driver | |
2178 | * @il: iwl il struct | |
2179 | * | |
2180 | * This is called during il_down() to make sure that in the case | |
2181 | * we're coming there from a hardware restart mac80211 will be | |
2182 | * able to reconfigure stations -- if we're getting there in the | |
2183 | * normal down flow then the stations will already be cleared. | |
2184 | */ | |
e7392364 SG |
2185 | static inline void |
2186 | il_clear_driver_stations(struct il_priv *il) | |
e94a4099 SG |
2187 | { |
2188 | unsigned long flags; | |
e94a4099 SG |
2189 | |
2190 | spin_lock_irqsave(&il->sta_lock, flags); | |
2191 | memset(il->stations, 0, sizeof(il->stations)); | |
2192 | il->num_stations = 0; | |
e94a4099 | 2193 | il->ucode_key_table = 0; |
e94a4099 SG |
2194 | spin_unlock_irqrestore(&il->sta_lock, flags); |
2195 | } | |
2196 | ||
e7392364 SG |
2197 | static inline int |
2198 | il_sta_id(struct ieee80211_sta *sta) | |
e94a4099 SG |
2199 | { |
2200 | if (WARN_ON(!sta)) | |
2201 | return IL_INVALID_STATION; | |
2202 | ||
2203 | return ((struct il_station_priv_common *)sta->drv_priv)->sta_id; | |
2204 | } | |
2205 | ||
2206 | /** | |
2207 | * il_sta_id_or_broadcast - return sta_id or broadcast sta | |
2208 | * @il: iwl il | |
2209 | * @context: the current context | |
2210 | * @sta: mac80211 station | |
2211 | * | |
2212 | * In certain circumstances mac80211 passes a station pointer | |
2213 | * that may be %NULL, for example during TX or key setup. In | |
2214 | * that case, we need to use the broadcast station, so this | |
2215 | * inline wraps that pattern. | |
2216 | */ | |
e7392364 | 2217 | static inline int |
83007196 | 2218 | il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta) |
e94a4099 SG |
2219 | { |
2220 | int sta_id; | |
2221 | ||
2222 | if (!sta) | |
b16db50a | 2223 | return il->hw_params.bcast_id; |
e94a4099 SG |
2224 | |
2225 | sta_id = il_sta_id(sta); | |
2226 | ||
2227 | /* | |
2228 | * mac80211 should not be passing a partially | |
2229 | * initialised station! | |
2230 | */ | |
2231 | WARN_ON(sta_id == IL_INVALID_STATION); | |
2232 | ||
2233 | return sta_id; | |
2234 | } | |
2235 | ||
2236 | /** | |
2237 | * il_queue_inc_wrap - increment queue idx, wrap back to beginning | |
2238 | * @idx -- current idx | |
2239 | * @n_bd -- total number of entries in queue (must be power of 2) | |
2240 | */ | |
e7392364 SG |
2241 | static inline int |
2242 | il_queue_inc_wrap(int idx, int n_bd) | |
e94a4099 SG |
2243 | { |
2244 | return ++idx & (n_bd - 1); | |
2245 | } | |
2246 | ||
2247 | /** | |
2248 | * il_queue_dec_wrap - decrement queue idx, wrap back to end | |
2249 | * @idx -- current idx | |
2250 | * @n_bd -- total number of entries in queue (must be power of 2) | |
2251 | */ | |
e7392364 SG |
2252 | static inline int |
2253 | il_queue_dec_wrap(int idx, int n_bd) | |
e94a4099 SG |
2254 | { |
2255 | return --idx & (n_bd - 1); | |
2256 | } | |
2257 | ||
2258 | /* TODO: Move fw_desc functions to iwl-pci.ko */ | |
e7392364 SG |
2259 | static inline void |
2260 | il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) | |
e94a4099 SG |
2261 | { |
2262 | if (desc->v_addr) | |
e7392364 SG |
2263 | dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr, |
2264 | desc->p_addr); | |
e94a4099 SG |
2265 | desc->v_addr = NULL; |
2266 | desc->len = 0; | |
2267 | } | |
2268 | ||
e7392364 SG |
2269 | static inline int |
2270 | il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) | |
e94a4099 SG |
2271 | { |
2272 | if (!desc->len) { | |
2273 | desc->v_addr = NULL; | |
2274 | return -EINVAL; | |
2275 | } | |
2276 | ||
e7392364 SG |
2277 | desc->v_addr = |
2278 | dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr, | |
2279 | GFP_KERNEL); | |
e94a4099 SG |
2280 | return (desc->v_addr != NULL) ? 0 : -ENOMEM; |
2281 | } | |
2282 | ||
2283 | /* | |
2284 | * we have 8 bits used like this: | |
2285 | * | |
2286 | * 7 6 5 4 3 2 1 0 | |
2287 | * | | | | | | | | | |
2288 | * | | | | | | +-+-------- AC queue (0-3) | |
2289 | * | | | | | | | |
2290 | * | +-+-+-+-+------------ HW queue ID | |
2291 | * | | |
2292 | * +---------------------- unused | |
2293 | */ | |
2294 | static inline void | |
2295 | il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq) | |
2296 | { | |
e7392364 SG |
2297 | BUG_ON(ac > 3); /* only have 2 bits */ |
2298 | BUG_ON(hwq > 31); /* only use 5 bits */ | |
e94a4099 SG |
2299 | |
2300 | txq->swq_id = (hwq << 2) | ac; | |
2301 | } | |
2302 | ||
e7392364 SG |
2303 | static inline void |
2304 | il_wake_queue(struct il_priv *il, struct il_tx_queue *txq) | |
e94a4099 SG |
2305 | { |
2306 | u8 queue = txq->swq_id; | |
2307 | u8 ac = queue & 3; | |
2308 | u8 hwq = (queue >> 2) & 0x1f; | |
2309 | ||
2310 | if (test_and_clear_bit(hwq, il->queue_stopped)) | |
2311 | if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0) | |
2312 | ieee80211_wake_queue(il->hw, ac); | |
2313 | } | |
2314 | ||
e7392364 SG |
2315 | static inline void |
2316 | il_stop_queue(struct il_priv *il, struct il_tx_queue *txq) | |
e94a4099 SG |
2317 | { |
2318 | u8 queue = txq->swq_id; | |
2319 | u8 ac = queue & 3; | |
2320 | u8 hwq = (queue >> 2) & 0x1f; | |
2321 | ||
2322 | if (!test_and_set_bit(hwq, il->queue_stopped)) | |
2323 | if (atomic_inc_return(&il->queue_stop_count[ac]) > 0) | |
2324 | ieee80211_stop_queue(il->hw, ac); | |
2325 | } | |
2326 | ||
2327 | #ifdef ieee80211_stop_queue | |
2328 | #undef ieee80211_stop_queue | |
2329 | #endif | |
2330 | ||
2331 | #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue | |
2332 | ||
2333 | #ifdef ieee80211_wake_queue | |
2334 | #undef ieee80211_wake_queue | |
2335 | #endif | |
2336 | ||
2337 | #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue | |
2338 | ||
e7392364 SG |
2339 | static inline void |
2340 | il_disable_interrupts(struct il_priv *il) | |
e94a4099 SG |
2341 | { |
2342 | clear_bit(S_INT_ENABLED, &il->status); | |
2343 | ||
2344 | /* disable interrupts from uCode/NIC to host */ | |
2345 | _il_wr(il, CSR_INT_MASK, 0x00000000); | |
2346 | ||
2347 | /* acknowledge/clear/reset any interrupts still pending | |
2348 | * from uCode or flow handler (Rx/Tx DMA) */ | |
2349 | _il_wr(il, CSR_INT, 0xffffffff); | |
2350 | _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff); | |
e94a4099 SG |
2351 | } |
2352 | ||
e7392364 SG |
2353 | static inline void |
2354 | il_enable_rfkill_int(struct il_priv *il) | |
e94a4099 | 2355 | { |
e94a4099 SG |
2356 | _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); |
2357 | } | |
2358 | ||
e7392364 SG |
2359 | static inline void |
2360 | il_enable_interrupts(struct il_priv *il) | |
e94a4099 | 2361 | { |
e94a4099 SG |
2362 | set_bit(S_INT_ENABLED, &il->status); |
2363 | _il_wr(il, CSR_INT_MASK, il->inta_mask); | |
2364 | } | |
2365 | ||
2366 | /** | |
2367 | * il_beacon_time_mask_low - mask of lower 32 bit of beacon time | |
2368 | * @il -- pointer to il_priv data structure | |
2369 | * @tsf_bits -- number of bits need to shift for masking) | |
2370 | */ | |
e7392364 SG |
2371 | static inline u32 |
2372 | il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits) | |
e94a4099 SG |
2373 | { |
2374 | return (1 << tsf_bits) - 1; | |
2375 | } | |
2376 | ||
2377 | /** | |
2378 | * il_beacon_time_mask_high - mask of higher 32 bit of beacon time | |
2379 | * @il -- pointer to il_priv data structure | |
2380 | * @tsf_bits -- number of bits need to shift for masking) | |
2381 | */ | |
e7392364 SG |
2382 | static inline u32 |
2383 | il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits) | |
e94a4099 SG |
2384 | { |
2385 | return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; | |
2386 | } | |
2387 | ||
2388 | /** | |
2389 | * struct il_rb_status - reseve buffer status host memory mapped FH registers | |
2390 | * | |
2391 | * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed | |
2392 | * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed | |
2393 | * @finished_rb_num [0:11] - Indicates the idx of the current RB | |
2394 | * in which the last frame was written to | |
2395 | * @finished_fr_num [0:11] - Indicates the idx of the RX Frame | |
2396 | * which was transferred | |
2397 | */ | |
2398 | struct il_rb_status { | |
2399 | __le16 closed_rb_num; | |
2400 | __le16 closed_fr_num; | |
2401 | __le16 finished_rb_num; | |
2402 | __le16 finished_fr_nam; | |
e7392364 | 2403 | __le32 __unused; /* 3945 only */ |
e94a4099 SG |
2404 | } __packed; |
2405 | ||
d87c771f SG |
2406 | #define TFD_QUEUE_SIZE_MAX 256 |
2407 | #define TFD_QUEUE_SIZE_BC_DUP 64 | |
e94a4099 | 2408 | #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) |
d87c771f | 2409 | #define IL_TX_DMA_MASK DMA_BIT_MASK(36) |
e94a4099 SG |
2410 | #define IL_NUM_OF_TBS 20 |
2411 | ||
e7392364 SG |
2412 | static inline u8 |
2413 | il_get_dma_hi_addr(dma_addr_t addr) | |
e94a4099 SG |
2414 | { |
2415 | return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; | |
2416 | } | |
e7392364 | 2417 | |
e94a4099 SG |
2418 | /** |
2419 | * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor | |
2420 | * | |
2421 | * This structure contains dma address and length of transmission address | |
2422 | * | |
1722f8e1 SG |
2423 | * @lo: low [31:0] portion of the dma address of TX buffer every even is |
2424 | * unaligned on 16 bit boundary | |
2425 | * @hi_n_len: 0-3 [35:32] portion of dma | |
2426 | * 4-15 length of the tx buffer | |
e94a4099 SG |
2427 | */ |
2428 | struct il_tfd_tb { | |
2429 | __le32 lo; | |
2430 | __le16 hi_n_len; | |
2431 | } __packed; | |
2432 | ||
2433 | /** | |
2434 | * struct il_tfd | |
2435 | * | |
2436 | * Transmit Frame Descriptor (TFD) | |
2437 | * | |
2438 | * @ __reserved1[3] reserved | |
2439 | * @ num_tbs 0-4 number of active tbs | |
2440 | * 5 reserved | |
2441 | * 6-7 padding (not used) | |
2442 | * @ tbs[20] transmit frame buffer descriptors | |
1722f8e1 | 2443 | * @ __pad padding |
e94a4099 SG |
2444 | * |
2445 | * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. | |
2446 | * Both driver and device share these circular buffers, each of which must be | |
2447 | * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes | |
2448 | * | |
2449 | * Driver must indicate the physical address of the base of each | |
9a95b370 | 2450 | * circular buffer via the FH49_MEM_CBBC_QUEUE registers. |
e94a4099 SG |
2451 | * |
2452 | * Each TFD contains pointer/size information for up to 20 data buffers | |
2453 | * in host DRAM. These buffers collectively contain the (one) frame described | |
2454 | * by the TFD. Each buffer must be a single contiguous block of memory within | |
2455 | * itself, but buffers may be scattered in host DRAM. Each buffer has max size | |
2456 | * of (4K - 4). The concatenates all of a TFD's buffers into a single | |
2457 | * Tx frame, up to 8 KBytes in size. | |
2458 | * | |
2459 | * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. | |
2460 | */ | |
2461 | struct il_tfd { | |
2462 | u8 __reserved1[3]; | |
2463 | u8 num_tbs; | |
2464 | struct il_tfd_tb tbs[IL_NUM_OF_TBS]; | |
2465 | __le32 __pad; | |
2466 | } __packed; | |
2467 | /* PCI registers */ | |
2468 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
2469 | ||
2470 | /* PCI register values */ | |
2471 | #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 | |
2472 | #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 | |
2473 | ||
3fbbf9a8 | 2474 | struct il_rate_info { |
e7392364 SG |
2475 | u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ |
2476 | u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */ | |
2477 | u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */ | |
2478 | u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */ | |
2479 | u8 prev_ieee; /* previous rate in IEEE speeds */ | |
2480 | u8 next_ieee; /* next rate in IEEE speeds */ | |
2481 | u8 prev_rs; /* previous rate used in rs algo */ | |
2482 | u8 next_rs; /* next rate used in rs algo */ | |
2483 | u8 prev_rs_tgg; /* previous rate used in TGG rs algo */ | |
2484 | u8 next_rs_tgg; /* next rate used in TGG rs algo */ | |
3fbbf9a8 SG |
2485 | }; |
2486 | ||
2487 | struct il3945_rate_info { | |
2488 | u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ | |
2489 | u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */ | |
2490 | u8 prev_ieee; /* previous rate in IEEE speeds */ | |
2491 | u8 next_ieee; /* next rate in IEEE speeds */ | |
2492 | u8 prev_rs; /* previous rate used in rs algo */ | |
2493 | u8 next_rs; /* next rate used in rs algo */ | |
2494 | u8 prev_rs_tgg; /* previous rate used in TGG rs algo */ | |
2495 | u8 next_rs_tgg; /* next rate used in TGG rs algo */ | |
2496 | u8 table_rs_idx; /* idx in rate scale table cmd */ | |
2497 | u8 prev_table_rs; /* prev in rate table cmd */ | |
2498 | }; | |
2499 | ||
3fbbf9a8 SG |
2500 | /* |
2501 | * These serve as idxes into | |
2502 | * struct il_rate_info il_rates[RATE_COUNT]; | |
2503 | */ | |
2504 | enum { | |
2505 | RATE_1M_IDX = 0, | |
2506 | RATE_2M_IDX, | |
2507 | RATE_5M_IDX, | |
2508 | RATE_11M_IDX, | |
2509 | RATE_6M_IDX, | |
2510 | RATE_9M_IDX, | |
2511 | RATE_12M_IDX, | |
2512 | RATE_18M_IDX, | |
2513 | RATE_24M_IDX, | |
2514 | RATE_36M_IDX, | |
2515 | RATE_48M_IDX, | |
2516 | RATE_54M_IDX, | |
2517 | RATE_60M_IDX, | |
2518 | RATE_COUNT, | |
2519 | RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */ | |
2520 | RATE_COUNT_3945 = RATE_COUNT - 1, | |
2521 | RATE_INVM_IDX = RATE_COUNT, | |
2522 | RATE_INVALID = RATE_COUNT, | |
2523 | }; | |
2524 | ||
2525 | enum { | |
2526 | RATE_6M_IDX_TBL = 0, | |
2527 | RATE_9M_IDX_TBL, | |
2528 | RATE_12M_IDX_TBL, | |
2529 | RATE_18M_IDX_TBL, | |
2530 | RATE_24M_IDX_TBL, | |
2531 | RATE_36M_IDX_TBL, | |
2532 | RATE_48M_IDX_TBL, | |
2533 | RATE_54M_IDX_TBL, | |
2534 | RATE_1M_IDX_TBL, | |
2535 | RATE_2M_IDX_TBL, | |
2536 | RATE_5M_IDX_TBL, | |
2537 | RATE_11M_IDX_TBL, | |
2538 | RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1, | |
2539 | }; | |
2540 | ||
2541 | enum { | |
2542 | IL_FIRST_OFDM_RATE = RATE_6M_IDX, | |
2543 | IL39_LAST_OFDM_RATE = RATE_54M_IDX, | |
2544 | IL_LAST_OFDM_RATE = RATE_60M_IDX, | |
2545 | IL_FIRST_CCK_RATE = RATE_1M_IDX, | |
2546 | IL_LAST_CCK_RATE = RATE_11M_IDX, | |
2547 | }; | |
2548 | ||
2549 | /* #define vs. enum to keep from defaulting to 'large integer' */ | |
2550 | #define RATE_6M_MASK (1 << RATE_6M_IDX) | |
2551 | #define RATE_9M_MASK (1 << RATE_9M_IDX) | |
2552 | #define RATE_12M_MASK (1 << RATE_12M_IDX) | |
2553 | #define RATE_18M_MASK (1 << RATE_18M_IDX) | |
2554 | #define RATE_24M_MASK (1 << RATE_24M_IDX) | |
2555 | #define RATE_36M_MASK (1 << RATE_36M_IDX) | |
2556 | #define RATE_48M_MASK (1 << RATE_48M_IDX) | |
2557 | #define RATE_54M_MASK (1 << RATE_54M_IDX) | |
2558 | #define RATE_60M_MASK (1 << RATE_60M_IDX) | |
2559 | #define RATE_1M_MASK (1 << RATE_1M_IDX) | |
2560 | #define RATE_2M_MASK (1 << RATE_2M_IDX) | |
2561 | #define RATE_5M_MASK (1 << RATE_5M_IDX) | |
2562 | #define RATE_11M_MASK (1 << RATE_11M_IDX) | |
2563 | ||
2564 | /* uCode API values for legacy bit rates, both OFDM and CCK */ | |
2565 | enum { | |
e7392364 SG |
2566 | RATE_6M_PLCP = 13, |
2567 | RATE_9M_PLCP = 15, | |
3fbbf9a8 SG |
2568 | RATE_12M_PLCP = 5, |
2569 | RATE_18M_PLCP = 7, | |
2570 | RATE_24M_PLCP = 9, | |
2571 | RATE_36M_PLCP = 11, | |
2572 | RATE_48M_PLCP = 1, | |
2573 | RATE_54M_PLCP = 3, | |
e7392364 SG |
2574 | RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */ |
2575 | RATE_1M_PLCP = 10, | |
2576 | RATE_2M_PLCP = 20, | |
2577 | RATE_5M_PLCP = 55, | |
3fbbf9a8 | 2578 | RATE_11M_PLCP = 110, |
e7392364 | 2579 | /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */ |
3fbbf9a8 SG |
2580 | }; |
2581 | ||
2582 | /* uCode API values for OFDM high-throughput (HT) bit rates */ | |
2583 | enum { | |
2584 | RATE_SISO_6M_PLCP = 0, | |
2585 | RATE_SISO_12M_PLCP = 1, | |
2586 | RATE_SISO_18M_PLCP = 2, | |
2587 | RATE_SISO_24M_PLCP = 3, | |
2588 | RATE_SISO_36M_PLCP = 4, | |
2589 | RATE_SISO_48M_PLCP = 5, | |
2590 | RATE_SISO_54M_PLCP = 6, | |
2591 | RATE_SISO_60M_PLCP = 7, | |
e7392364 | 2592 | RATE_MIMO2_6M_PLCP = 0x8, |
3fbbf9a8 SG |
2593 | RATE_MIMO2_12M_PLCP = 0x9, |
2594 | RATE_MIMO2_18M_PLCP = 0xa, | |
2595 | RATE_MIMO2_24M_PLCP = 0xb, | |
2596 | RATE_MIMO2_36M_PLCP = 0xc, | |
2597 | RATE_MIMO2_48M_PLCP = 0xd, | |
2598 | RATE_MIMO2_54M_PLCP = 0xe, | |
2599 | RATE_MIMO2_60M_PLCP = 0xf, | |
2600 | RATE_SISO_INVM_PLCP, | |
2601 | RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP, | |
2602 | }; | |
2603 | ||
2604 | /* MAC header values for bit rates */ | |
2605 | enum { | |
e7392364 SG |
2606 | RATE_6M_IEEE = 12, |
2607 | RATE_9M_IEEE = 18, | |
3fbbf9a8 SG |
2608 | RATE_12M_IEEE = 24, |
2609 | RATE_18M_IEEE = 36, | |
2610 | RATE_24M_IEEE = 48, | |
2611 | RATE_36M_IEEE = 72, | |
2612 | RATE_48M_IEEE = 96, | |
2613 | RATE_54M_IEEE = 108, | |
2614 | RATE_60M_IEEE = 120, | |
e7392364 SG |
2615 | RATE_1M_IEEE = 2, |
2616 | RATE_2M_IEEE = 4, | |
2617 | RATE_5M_IEEE = 11, | |
3fbbf9a8 SG |
2618 | RATE_11M_IEEE = 22, |
2619 | }; | |
2620 | ||
2621 | #define IL_CCK_BASIC_RATES_MASK \ | |
2622 | (RATE_1M_MASK | \ | |
2623 | RATE_2M_MASK) | |
2624 | ||
2625 | #define IL_CCK_RATES_MASK \ | |
2626 | (IL_CCK_BASIC_RATES_MASK | \ | |
2627 | RATE_5M_MASK | \ | |
2628 | RATE_11M_MASK) | |
2629 | ||
2630 | #define IL_OFDM_BASIC_RATES_MASK \ | |
2631 | (RATE_6M_MASK | \ | |
2632 | RATE_12M_MASK | \ | |
2633 | RATE_24M_MASK) | |
2634 | ||
2635 | #define IL_OFDM_RATES_MASK \ | |
2636 | (IL_OFDM_BASIC_RATES_MASK | \ | |
2637 | RATE_9M_MASK | \ | |
2638 | RATE_18M_MASK | \ | |
2639 | RATE_36M_MASK | \ | |
2640 | RATE_48M_MASK | \ | |
2641 | RATE_54M_MASK) | |
2642 | ||
2643 | #define IL_BASIC_RATES_MASK \ | |
2644 | (IL_OFDM_BASIC_RATES_MASK | \ | |
2645 | IL_CCK_BASIC_RATES_MASK) | |
2646 | ||
2647 | #define RATES_MASK ((1 << RATE_COUNT) - 1) | |
2648 | #define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1) | |
2649 | ||
2650 | #define IL_INVALID_VALUE -1 | |
2651 | ||
2652 | #define IL_MIN_RSSI_VAL -100 | |
2653 | #define IL_MAX_RSSI_VAL 0 | |
2654 | ||
2655 | /* These values specify how many Tx frame attempts before | |
2656 | * searching for a new modulation mode */ | |
2657 | #define IL_LEGACY_FAILURE_LIMIT 160 | |
2658 | #define IL_LEGACY_SUCCESS_LIMIT 480 | |
2659 | #define IL_LEGACY_TBL_COUNT 160 | |
2660 | ||
2661 | #define IL_NONE_LEGACY_FAILURE_LIMIT 400 | |
2662 | #define IL_NONE_LEGACY_SUCCESS_LIMIT 4500 | |
2663 | #define IL_NONE_LEGACY_TBL_COUNT 1500 | |
2664 | ||
2665 | /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */ | |
2666 | #define IL_RS_GOOD_RATIO 12800 /* 100% */ | |
2667 | #define RATE_SCALE_SWITCH 10880 /* 85% */ | |
2668 | #define RATE_HIGH_TH 10880 /* 85% */ | |
2669 | #define RATE_INCREASE_TH 6400 /* 50% */ | |
2670 | #define RATE_DECREASE_TH 1920 /* 15% */ | |
2671 | ||
2672 | /* possible actions when in legacy mode */ | |
2673 | #define IL_LEGACY_SWITCH_ANTENNA1 0 | |
2674 | #define IL_LEGACY_SWITCH_ANTENNA2 1 | |
2675 | #define IL_LEGACY_SWITCH_SISO 2 | |
2676 | #define IL_LEGACY_SWITCH_MIMO2_AB 3 | |
2677 | #define IL_LEGACY_SWITCH_MIMO2_AC 4 | |
2678 | #define IL_LEGACY_SWITCH_MIMO2_BC 5 | |
2679 | ||
2680 | /* possible actions when in siso mode */ | |
2681 | #define IL_SISO_SWITCH_ANTENNA1 0 | |
2682 | #define IL_SISO_SWITCH_ANTENNA2 1 | |
2683 | #define IL_SISO_SWITCH_MIMO2_AB 2 | |
2684 | #define IL_SISO_SWITCH_MIMO2_AC 3 | |
2685 | #define IL_SISO_SWITCH_MIMO2_BC 4 | |
2686 | #define IL_SISO_SWITCH_GI 5 | |
2687 | ||
2688 | /* possible actions when in mimo mode */ | |
2689 | #define IL_MIMO2_SWITCH_ANTENNA1 0 | |
2690 | #define IL_MIMO2_SWITCH_ANTENNA2 1 | |
2691 | #define IL_MIMO2_SWITCH_SISO_A 2 | |
2692 | #define IL_MIMO2_SWITCH_SISO_B 3 | |
2693 | #define IL_MIMO2_SWITCH_SISO_C 4 | |
2694 | #define IL_MIMO2_SWITCH_GI 5 | |
2695 | ||
2696 | #define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI | |
2697 | ||
2698 | #define IL_ACTION_LIMIT 3 /* # possible actions */ | |
2699 | ||
2700 | #define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */ | |
2701 | ||
2702 | /* load per tid defines for A-MPDU activation */ | |
2703 | #define IL_AGG_TPT_THREHOLD 0 | |
2704 | #define IL_AGG_LOAD_THRESHOLD 10 | |
2705 | #define IL_AGG_ALL_TID 0xff | |
2706 | #define TID_QUEUE_CELL_SPACING 50 /*mS */ | |
2707 | #define TID_QUEUE_MAX_SIZE 20 | |
2708 | #define TID_ROUND_VALUE 5 /* mS */ | |
2709 | #define TID_MAX_LOAD_COUNT 8 | |
2710 | ||
2711 | #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING) | |
2712 | #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y)) | |
2713 | ||
2714 | extern const struct il_rate_info il_rates[RATE_COUNT]; | |
2715 | ||
2716 | enum il_table_type { | |
2717 | LQ_NONE, | |
e7392364 | 2718 | LQ_G, /* legacy types */ |
3fbbf9a8 | 2719 | LQ_A, |
e7392364 | 2720 | LQ_SISO, /* high-throughput types */ |
3fbbf9a8 SG |
2721 | LQ_MIMO2, |
2722 | LQ_MAX, | |
2723 | }; | |
2724 | ||
2725 | #define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A) | |
2726 | #define is_siso(tbl) ((tbl) == LQ_SISO) | |
2727 | #define is_mimo2(tbl) ((tbl) == LQ_MIMO2) | |
2728 | #define is_mimo(tbl) (is_mimo2(tbl)) | |
2729 | #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) | |
2730 | #define is_a_band(tbl) ((tbl) == LQ_A) | |
2731 | #define is_g_and(tbl) ((tbl) == LQ_G) | |
2732 | ||
2733 | #define ANT_NONE 0x0 | |
2734 | #define ANT_A BIT(0) | |
2735 | #define ANT_B BIT(1) | |
2736 | #define ANT_AB (ANT_A | ANT_B) | |
2737 | #define ANT_C BIT(2) | |
2738 | #define ANT_AC (ANT_A | ANT_C) | |
2739 | #define ANT_BC (ANT_B | ANT_C) | |
2740 | #define ANT_ABC (ANT_AB | ANT_C) | |
2741 | ||
2742 | #define IL_MAX_MCS_DISPLAY_SIZE 12 | |
2743 | ||
2744 | struct il_rate_mcs_info { | |
e7392364 SG |
2745 | char mbps[IL_MAX_MCS_DISPLAY_SIZE]; |
2746 | char mcs[IL_MAX_MCS_DISPLAY_SIZE]; | |
3fbbf9a8 SG |
2747 | }; |
2748 | ||
2749 | /** | |
2750 | * struct il_rate_scale_data -- tx success history for one rate | |
2751 | */ | |
2752 | struct il_rate_scale_data { | |
2753 | u64 data; /* bitmap of successful frames */ | |
2754 | s32 success_counter; /* number of frames successful */ | |
2755 | s32 success_ratio; /* per-cent * 128 */ | |
2756 | s32 counter; /* number of frames attempted */ | |
2757 | s32 average_tpt; /* success ratio * expected throughput */ | |
2758 | unsigned long stamp; | |
2759 | }; | |
2760 | ||
2761 | /** | |
2762 | * struct il_scale_tbl_info -- tx params and success history for all rates | |
2763 | * | |
2764 | * There are two of these in struct il_lq_sta, | |
2765 | * one for "active", and one for "search". | |
2766 | */ | |
2767 | struct il_scale_tbl_info { | |
2768 | enum il_table_type lq_type; | |
2769 | u8 ant_type; | |
e7392364 SG |
2770 | u8 is_SGI; /* 1 = short guard interval */ |
2771 | u8 is_ht40; /* 1 = 40 MHz channel width */ | |
2772 | u8 is_dup; /* 1 = duplicated data streams */ | |
2773 | u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */ | |
2774 | u8 max_search; /* maximun number of tables we can search */ | |
3fbbf9a8 | 2775 | s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */ |
e7392364 SG |
2776 | u32 current_rate; /* rate_n_flags, uCode API format */ |
2777 | struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */ | |
3fbbf9a8 SG |
2778 | }; |
2779 | ||
2780 | struct il_traffic_load { | |
2781 | unsigned long time_stamp; /* age of the oldest stats */ | |
e7392364 | 2782 | u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time |
3fbbf9a8 | 2783 | * slice */ |
e7392364 SG |
2784 | u32 total; /* total num of packets during the |
2785 | * last TID_MAX_TIME_DIFF */ | |
2786 | u8 queue_count; /* number of queues that has | |
2787 | * been used since the last cleanup */ | |
2788 | u8 head; /* start of the circular buffer */ | |
3fbbf9a8 SG |
2789 | }; |
2790 | ||
2791 | /** | |
2792 | * struct il_lq_sta -- driver's rate scaling ilate structure | |
2793 | * | |
2794 | * Pointer to this gets passed back and forth between driver and mac80211. | |
2795 | */ | |
2796 | struct il_lq_sta { | |
2797 | u8 active_tbl; /* idx of active table, range 0-1 */ | |
2798 | u8 enable_counter; /* indicates HT mode */ | |
2799 | u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */ | |
2800 | u8 search_better_tbl; /* 1: currently trying alternate mode */ | |
2801 | s32 last_tpt; | |
2802 | ||
2803 | /* The following determine when to search for a new mode */ | |
2804 | u32 table_count_limit; | |
2805 | u32 max_failure_limit; /* # failed frames before new search */ | |
2806 | u32 max_success_limit; /* # successful frames before new search */ | |
2807 | u32 table_count; | |
2808 | u32 total_failed; /* total failed frames, any/all rates */ | |
2809 | u32 total_success; /* total successful frames, any/all rates */ | |
2810 | u64 flush_timer; /* time staying in mode before new search */ | |
2811 | ||
2812 | u8 action_counter; /* # mode-switch actions tried */ | |
2813 | u8 is_green; | |
2814 | u8 is_dup; | |
2815 | enum ieee80211_band band; | |
2816 | ||
2817 | /* The following are bitmaps of rates; RATE_6M_MASK, etc. */ | |
2818 | u32 supp_rates; | |
2819 | u16 active_legacy_rate; | |
2820 | u16 active_siso_rate; | |
2821 | u16 active_mimo2_rate; | |
e7392364 | 2822 | s8 max_rate_idx; /* Max rate set by user */ |
3fbbf9a8 SG |
2823 | u8 missed_rate_counter; |
2824 | ||
2825 | struct il_link_quality_cmd lq; | |
e7392364 | 2826 | struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */ |
3fbbf9a8 SG |
2827 | struct il_traffic_load load[TID_MAX_LOAD_COUNT]; |
2828 | u8 tx_agg_tid_en; | |
2829 | #ifdef CONFIG_MAC80211_DEBUGFS | |
2830 | struct dentry *rs_sta_dbgfs_scale_table_file; | |
2831 | struct dentry *rs_sta_dbgfs_stats_table_file; | |
2832 | struct dentry *rs_sta_dbgfs_rate_scale_data_file; | |
2833 | struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file; | |
2834 | u32 dbg_fixed_rate; | |
2835 | #endif | |
2836 | struct il_priv *drv; | |
2837 | ||
2838 | /* used to be in sta_info */ | |
2839 | int last_txrate_idx; | |
2840 | /* last tx rate_n_flags */ | |
2841 | u32 last_rate_n_flags; | |
2842 | /* packets destined for this STA are aggregated */ | |
2843 | u8 is_agg; | |
2844 | }; | |
2845 | ||
2846 | /* | |
2847 | * il_station_priv: Driver's ilate station information | |
2848 | * | |
2849 | * When mac80211 creates a station it reserves some space (hw->sta_data_size) | |
2850 | * in the structure for use by driver. This structure is places in that | |
2851 | * space. | |
2852 | * | |
2853 | * The common struct MUST be first because it is shared between | |
2854 | * 3945 and 4965! | |
2855 | */ | |
2856 | struct il_station_priv { | |
2857 | struct il_station_priv_common common; | |
2858 | struct il_lq_sta lq_sta; | |
2859 | atomic_t pending_frames; | |
2860 | bool client; | |
2861 | bool asleep; | |
2862 | }; | |
2863 | ||
e7392364 SG |
2864 | static inline u8 |
2865 | il4965_num_of_ant(u8 m) | |
3fbbf9a8 SG |
2866 | { |
2867 | return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C); | |
2868 | } | |
2869 | ||
e7392364 SG |
2870 | static inline u8 |
2871 | il4965_first_antenna(u8 mask) | |
3fbbf9a8 SG |
2872 | { |
2873 | if (mask & ANT_A) | |
2874 | return ANT_A; | |
2875 | if (mask & ANT_B) | |
2876 | return ANT_B; | |
2877 | return ANT_C; | |
2878 | } | |
2879 | ||
3fbbf9a8 SG |
2880 | /** |
2881 | * il3945_rate_scale_init - Initialize the rate scale table based on assoc info | |
2882 | * | |
2883 | * The specific throughput table used is based on the type of network | |
2884 | * the associated with, including A, B, G, and G w/ TGG protection | |
2885 | */ | |
2886 | extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id); | |
2887 | ||
2888 | /* Initialize station's rate scaling information after adding station */ | |
e7392364 SG |
2889 | extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta, |
2890 | u8 sta_id); | |
2891 | extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta, | |
2892 | u8 sta_id); | |
3fbbf9a8 SG |
2893 | |
2894 | /** | |
2895 | * il_rate_control_register - Register the rate control algorithm callbacks | |
2896 | * | |
2897 | * Since the rate control algorithm is hardware specific, there is no need | |
2898 | * or reason to place it as a stand alone module. The driver can call | |
2899 | * il_rate_control_register in order to register the rate control callbacks | |
2900 | * with the mac80211 subsystem. This should be performed prior to calling | |
2901 | * ieee80211_register_hw | |
2902 | * | |
2903 | */ | |
2904 | extern int il4965_rate_control_register(void); | |
2905 | extern int il3945_rate_control_register(void); | |
2906 | ||
2907 | /** | |
2908 | * il_rate_control_unregister - Unregister the rate control callbacks | |
2909 | * | |
2910 | * This should be called after calling ieee80211_unregister_hw, but before | |
2911 | * the driver is unloaded. | |
2912 | */ | |
2913 | extern void il4965_rate_control_unregister(void); | |
2914 | extern void il3945_rate_control_unregister(void); | |
2915 | ||
99412002 SG |
2916 | extern int il_power_update_mode(struct il_priv *il, bool force); |
2917 | extern void il_power_initialize(struct il_priv *il); | |
47ef694d | 2918 | |
f02579e3 SG |
2919 | extern u32 il_debug_level; |
2920 | ||
2921 | #ifdef CONFIG_IWLEGACY_DEBUG | |
2922 | /* | |
2923 | * il_get_debug_level: Return active debug level for device | |
2924 | * | |
2925 | * Using sysfs it is possible to set per device debug level. This debug | |
2926 | * level will be used if set, otherwise the global debug level which can be | |
2927 | * set via module parameter is used. | |
2928 | */ | |
e7392364 SG |
2929 | static inline u32 |
2930 | il_get_debug_level(struct il_priv *il) | |
f02579e3 SG |
2931 | { |
2932 | if (il->debug_level) | |
2933 | return il->debug_level; | |
2934 | else | |
2935 | return il_debug_level; | |
2936 | } | |
2937 | #else | |
e7392364 SG |
2938 | static inline u32 |
2939 | il_get_debug_level(struct il_priv *il) | |
f02579e3 SG |
2940 | { |
2941 | return il_debug_level; | |
2942 | } | |
2943 | #endif | |
2944 | ||
2945 | #define il_print_hex_error(il, p, len) \ | |
2946 | do { \ | |
2947 | print_hex_dump(KERN_ERR, "iwl data: ", \ | |
2948 | DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \ | |
2949 | } while (0) | |
2950 | ||
2951 | #ifdef CONFIG_IWLEGACY_DEBUG | |
2952 | #define IL_DBG(level, fmt, args...) \ | |
2953 | do { \ | |
2954 | if (il_get_debug_level(il) & level) \ | |
2955 | dev_printk(KERN_ERR, &il->hw->wiphy->dev, \ | |
2956 | "%c %s " fmt, in_interrupt() ? 'I' : 'U', \ | |
2957 | __func__ , ## args); \ | |
2958 | } while (0) | |
2959 | ||
1722f8e1 | 2960 | #define il_print_hex_dump(il, level, p, len) \ |
f02579e3 SG |
2961 | do { \ |
2962 | if (il_get_debug_level(il) & level) \ | |
2963 | print_hex_dump(KERN_DEBUG, "iwl data: ", \ | |
2964 | DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \ | |
2965 | } while (0) | |
2966 | ||
2967 | #else | |
2968 | #define IL_DBG(level, fmt, args...) | |
e7392364 SG |
2969 | static inline void |
2970 | il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len) | |
2971 | { | |
2972 | } | |
2973 | #endif /* CONFIG_IWLEGACY_DEBUG */ | |
f02579e3 SG |
2974 | |
2975 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
2976 | int il_dbgfs_register(struct il_priv *il, const char *name); | |
2977 | void il_dbgfs_unregister(struct il_priv *il); | |
2978 | #else | |
2979 | static inline int | |
2980 | il_dbgfs_register(struct il_priv *il, const char *name) | |
2981 | { | |
2982 | return 0; | |
2983 | } | |
e7392364 SG |
2984 | |
2985 | static inline void | |
2986 | il_dbgfs_unregister(struct il_priv *il) | |
f02579e3 SG |
2987 | { |
2988 | } | |
e7392364 | 2989 | #endif /* CONFIG_IWLEGACY_DEBUGFS */ |
f02579e3 SG |
2990 | |
2991 | /* | |
2992 | * To use the debug system: | |
2993 | * | |
2994 | * If you are defining a new debug classification, simply add it to the #define | |
2995 | * list here in the form of | |
2996 | * | |
2997 | * #define IL_DL_xxxx VALUE | |
2998 | * | |
2999 | * where xxxx should be the name of the classification (for example, WEP). | |
3000 | * | |
3001 | * You then need to either add a IL_xxxx_DEBUG() macro definition for your | |
3002 | * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want | |
3003 | * to send output to that classification. | |
3004 | * | |
3005 | * The active debug levels can be accessed via files | |
3006 | * | |
1722f8e1 | 3007 | * /sys/module/iwl4965/parameters/debug |
f02579e3 | 3008 | * /sys/module/iwl3945/parameters/debug |
1722f8e1 | 3009 | * /sys/class/net/wlan0/device/debug_level |
f02579e3 SG |
3010 | * |
3011 | * when CONFIG_IWLEGACY_DEBUG=y. | |
3012 | */ | |
3013 | ||
3014 | /* 0x0000000F - 0x00000001 */ | |
3015 | #define IL_DL_INFO (1 << 0) | |
3016 | #define IL_DL_MAC80211 (1 << 1) | |
3017 | #define IL_DL_HCMD (1 << 2) | |
3018 | #define IL_DL_STATE (1 << 3) | |
3019 | /* 0x000000F0 - 0x00000010 */ | |
3020 | #define IL_DL_MACDUMP (1 << 4) | |
3021 | #define IL_DL_HCMD_DUMP (1 << 5) | |
3022 | #define IL_DL_EEPROM (1 << 6) | |
3023 | #define IL_DL_RADIO (1 << 7) | |
3024 | /* 0x00000F00 - 0x00000100 */ | |
3025 | #define IL_DL_POWER (1 << 8) | |
3026 | #define IL_DL_TEMP (1 << 9) | |
3027 | #define IL_DL_NOTIF (1 << 10) | |
3028 | #define IL_DL_SCAN (1 << 11) | |
3029 | /* 0x0000F000 - 0x00001000 */ | |
3030 | #define IL_DL_ASSOC (1 << 12) | |
3031 | #define IL_DL_DROP (1 << 13) | |
3032 | #define IL_DL_TXPOWER (1 << 14) | |
3033 | #define IL_DL_AP (1 << 15) | |
3034 | /* 0x000F0000 - 0x00010000 */ | |
3035 | #define IL_DL_FW (1 << 16) | |
3036 | #define IL_DL_RF_KILL (1 << 17) | |
3037 | #define IL_DL_FW_ERRORS (1 << 18) | |
3038 | #define IL_DL_LED (1 << 19) | |
3039 | /* 0x00F00000 - 0x00100000 */ | |
3040 | #define IL_DL_RATE (1 << 20) | |
3041 | #define IL_DL_CALIB (1 << 21) | |
3042 | #define IL_DL_WEP (1 << 22) | |
3043 | #define IL_DL_TX (1 << 23) | |
3044 | /* 0x0F000000 - 0x01000000 */ | |
3045 | #define IL_DL_RX (1 << 24) | |
3046 | #define IL_DL_ISR (1 << 25) | |
3047 | #define IL_DL_HT (1 << 26) | |
3048 | /* 0xF0000000 - 0x10000000 */ | |
3049 | #define IL_DL_11H (1 << 28) | |
3050 | #define IL_DL_STATS (1 << 29) | |
3051 | #define IL_DL_TX_REPLY (1 << 30) | |
3052 | #define IL_DL_QOS (1 << 31) | |
3053 | ||
3054 | #define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a) | |
3055 | #define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a) | |
3056 | #define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a) | |
3057 | #define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a) | |
3058 | #define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a) | |
3059 | #define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a) | |
3060 | #define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a) | |
3061 | #define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a) | |
3062 | #define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a) | |
3063 | #define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a) | |
3064 | #define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a) | |
3065 | #define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a) | |
3066 | #define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a) | |
3067 | #define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a) | |
3068 | #define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a) | |
3069 | #define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a) | |
3070 | #define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a) | |
3071 | #define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a) | |
3072 | #define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a) | |
3073 | #define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a) | |
3074 | #define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a) | |
3075 | #define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a) | |
3076 | #define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a) | |
3077 | #define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a) | |
3078 | #define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a) | |
3079 | #define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a) | |
3080 | #define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a) | |
3081 | #define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a) | |
3082 | #define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a) | |
3083 | ||
e2ebc833 | 3084 | #endif /* __il_core_h__ */ |