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be663ab6 WYG |
1 | /****************************************************************************** |
2 | * | |
e94a4099 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
be663ab6 | 4 | * |
e94a4099 SG |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of version 2 of the GNU General Public License as | |
be663ab6 WYG |
7 | * published by the Free Software Foundation. |
8 | * | |
e94a4099 SG |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
be663ab6 | 13 | * |
e94a4099 SG |
14 | * You should have received a copy of the GNU General Public License along with |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
be663ab6 | 17 | * |
e94a4099 SG |
18 | * The full GNU General Public License is included in this distribution in the |
19 | * file called LICENSE. | |
be663ab6 WYG |
20 | * |
21 | * Contact Information: | |
22 | * Intel Linux Wireless <ilw@linux.intel.com> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
e94a4099 SG |
25 | *****************************************************************************/ |
26 | #ifndef __il_core_h__ | |
27 | #define __il_core_h__ | |
28 | ||
29 | #include <linux/interrupt.h> | |
e7392364 | 30 | #include <linux/pci.h> /* for struct pci_device_id */ |
e94a4099 SG |
31 | #include <linux/kernel.h> |
32 | #include <linux/leds.h> | |
33 | #include <linux/wait.h> | |
17d4eca6 | 34 | #include <linux/io.h> |
47ef694d | 35 | #include <net/mac80211.h> |
e94a4099 SG |
36 | #include <net/ieee80211_radiotap.h> |
37 | ||
99412002 | 38 | #include "commands.h" |
e94a4099 | 39 | #include "csr.h" |
e8c39d4e | 40 | #include "prph.h" |
e94a4099 SG |
41 | |
42 | struct il_host_cmd; | |
43 | struct il_cmd; | |
44 | struct il_tx_queue; | |
45 | ||
f02579e3 SG |
46 | #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a) |
47 | #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a) | |
48 | #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a) | |
49 | ||
e94a4099 SG |
50 | #define RX_QUEUE_SIZE 256 |
51 | #define RX_QUEUE_MASK 255 | |
52 | #define RX_QUEUE_SIZE_LOG 8 | |
53 | ||
54 | /* | |
55 | * RX related structures and functions | |
56 | */ | |
57 | #define RX_FREE_BUFFERS 64 | |
58 | #define RX_LOW_WATERMARK 8 | |
59 | ||
60 | #define U32_PAD(n) ((4-(n))&0x3) | |
61 | ||
62 | /* CT-KILL constants */ | |
e7392364 | 63 | #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ |
e94a4099 SG |
64 | |
65 | /* Default noise level to report when noise measurement is not available. | |
66 | * This may be because we're: | |
67 | * 1) Not associated (4965, no beacon stats being sent to driver) | |
68 | * 2) Scanning (noise measurement does not apply to associated channel) | |
69 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
70 | * Use default noise value of -127 ... this is below the range of measurable | |
71 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
72 | * Also, -127 works better than 0 when averaging frames with/without | |
73 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
74 | * always negative ... using a negative value as the default keeps all | |
75 | * averages within an s8's (used in some apps) range of negative values. */ | |
76 | #define IL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
77 | ||
78 | /* | |
79 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
80 | * Per spec: | |
81 | * a value of 0 means RTS on all data/management packets | |
82 | * a value > max MSDU size means no RTS | |
83 | * else RTS for data/management frames where MPDU is larger | |
84 | * than RTS value. | |
85 | */ | |
86 | #define DEFAULT_RTS_THRESHOLD 2347U | |
87 | #define MIN_RTS_THRESHOLD 0U | |
88 | #define MAX_RTS_THRESHOLD 2347U | |
89 | #define MAX_MSDU_SIZE 2304U | |
90 | #define MAX_MPDU_SIZE 2346U | |
91 | #define DEFAULT_BEACON_INTERVAL 100U | |
92 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
93 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
94 | ||
95 | struct il_rx_buf { | |
96 | dma_addr_t page_dma; | |
97 | struct page *page; | |
98 | struct list_head list; | |
99 | }; | |
100 | ||
101 | #define rxb_addr(r) page_address(r->page) | |
102 | ||
103 | /* defined below */ | |
104 | struct il_device_cmd; | |
105 | ||
106 | struct il_cmd_meta { | |
107 | /* only for SYNC commands, iff the reply skb is wanted */ | |
108 | struct il_host_cmd *source; | |
109 | /* | |
110 | * only for ASYNC commands | |
111 | * (which is somewhat stupid -- look at common.c for instance | |
112 | * which duplicates a bunch of code because the callback isn't | |
113 | * invoked for SYNC commands, if it were and its result passed | |
114 | * through it would be simpler...) | |
115 | */ | |
1722f8e1 SG |
116 | void (*callback) (struct il_priv *il, struct il_device_cmd *cmd, |
117 | struct il_rx_pkt *pkt); | |
e94a4099 SG |
118 | |
119 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
120 | * structure is stored at the end of the shared queue memory. */ | |
121 | u32 flags; | |
122 | ||
e7392364 SG |
123 | DEFINE_DMA_UNMAP_ADDR(mapping); |
124 | DEFINE_DMA_UNMAP_LEN(len); | |
e94a4099 SG |
125 | }; |
126 | ||
127 | /* | |
128 | * Generic queue structure | |
129 | * | |
130 | * Contains common data for Rx and Tx queues | |
131 | */ | |
132 | struct il_queue { | |
e7392364 SG |
133 | int n_bd; /* number of BDs in this queue */ |
134 | int write_ptr; /* 1-st empty entry (idx) host_w */ | |
135 | int read_ptr; /* last used entry (idx) host_r */ | |
e94a4099 | 136 | /* use for monitoring and recovering the stuck queue */ |
e7392364 SG |
137 | dma_addr_t dma_addr; /* physical addr for BD's */ |
138 | int n_win; /* safe queue win */ | |
e94a4099 | 139 | u32 id; |
e7392364 SG |
140 | int low_mark; /* low watermark, resume queue if free |
141 | * space more than this */ | |
142 | int high_mark; /* high watermark, stop queue if free | |
143 | * space less than this */ | |
e94a4099 SG |
144 | }; |
145 | ||
e94a4099 SG |
146 | /** |
147 | * struct il_tx_queue - Tx Queue for DMA | |
148 | * @q: generic Rx/Tx queue descriptor | |
149 | * @bd: base of circular buffer of TFDs | |
150 | * @cmd: array of command/TX buffer pointers | |
151 | * @meta: array of meta data for each command/tx buffer | |
152 | * @dma_addr_cmd: physical address of cmd/tx buffer array | |
00ea99e1 | 153 | * @skbs: array of per-TFD socket buffer pointers |
e94a4099 SG |
154 | * @time_stamp: time (in jiffies) of last read_ptr change |
155 | * @need_update: indicates need to update read/write idx | |
156 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
157 | * | |
158 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame | |
159 | * descriptors) and required locking structures. | |
160 | */ | |
161 | #define TFD_TX_CMD_SLOTS 256 | |
162 | #define TFD_CMD_SLOTS 32 | |
163 | ||
164 | struct il_tx_queue { | |
165 | struct il_queue q; | |
166 | void *tfds; | |
167 | struct il_device_cmd **cmd; | |
168 | struct il_cmd_meta *meta; | |
00ea99e1 | 169 | struct sk_buff **skbs; |
e94a4099 SG |
170 | unsigned long time_stamp; |
171 | u8 need_update; | |
172 | u8 sched_retry; | |
173 | u8 active; | |
174 | u8 swq_id; | |
175 | }; | |
176 | ||
47ef694d SG |
177 | /* |
178 | * EEPROM access time values: | |
179 | * | |
180 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. | |
181 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). | |
182 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. | |
183 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. | |
184 | */ | |
e7392364 | 185 | #define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ |
47ef694d | 186 | |
e7392364 SG |
187 | #define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ |
188 | #define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
47ef694d SG |
189 | |
190 | /* | |
191 | * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags. | |
192 | * | |
193 | * IBSS and/or AP operation is allowed *only* on those channels with | |
194 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because | |
195 | * RADAR detection is not supported by the 4965 driver, but is a | |
196 | * requirement for establishing a new network for legal operation on channels | |
197 | * requiring RADAR detection or restricting ACTIVE scanning. | |
198 | * | |
199 | * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels. | |
200 | * It only indicates that 20 MHz channel use is supported; HT40 channel | |
201 | * usage is indicated by a separate set of regulatory flags for each | |
202 | * HT40 channel pair. | |
203 | * | |
204 | * NOTE: Using a channel inappropriately will result in a uCode error! | |
205 | */ | |
206 | #define IL_NUM_TX_CALIB_GROUPS 5 | |
207 | enum { | |
208 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ | |
e7392364 | 209 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ |
47ef694d SG |
210 | /* Bit 2 Reserved */ |
211 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ | |
212 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ | |
e7392364 | 213 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ |
47ef694d SG |
214 | /* Bit 6 Reserved (was Narrow Channel) */ |
215 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ | |
216 | }; | |
217 | ||
218 | /* SKU Capabilities */ | |
219 | /* 3945 only */ | |
220 | #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) | |
221 | #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) | |
222 | ||
223 | /* *regulatory* channel data format in eeprom, one for each channel. | |
224 | * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */ | |
225 | struct il_eeprom_channel { | |
226 | u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ | |
227 | s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ | |
228 | } __packed; | |
229 | ||
230 | /* 3945 Specific */ | |
231 | #define EEPROM_3945_EEPROM_VERSION (0x2f) | |
232 | ||
233 | /* 4965 has two radio transmitters (and 3 radio receivers) */ | |
234 | #define EEPROM_TX_POWER_TX_CHAINS (2) | |
235 | ||
236 | /* 4965 has room for up to 8 sets of txpower calibration data */ | |
237 | #define EEPROM_TX_POWER_BANDS (8) | |
238 | ||
239 | /* 4965 factory calibration measures txpower gain settings for | |
240 | * each of 3 target output levels */ | |
241 | #define EEPROM_TX_POWER_MEASUREMENTS (3) | |
242 | ||
243 | /* 4965 Specific */ | |
244 | /* 4965 driver does not work with txpower calibration version < 5 */ | |
245 | #define EEPROM_4965_TX_POWER_VERSION (5) | |
246 | #define EEPROM_4965_EEPROM_VERSION (0x2f) | |
e7392364 SG |
247 | #define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */ |
248 | #define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */ | |
249 | #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */ | |
250 | #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */ | |
47ef694d SG |
251 | |
252 | /* 2.4 GHz */ | |
253 | extern const u8 il_eeprom_band_1[14]; | |
254 | ||
255 | /* | |
256 | * factory calibration data for one txpower level, on one channel, | |
257 | * measured on one of the 2 tx chains (radio transmitter and associated | |
258 | * antenna). EEPROM contains: | |
259 | * | |
260 | * 1) Temperature (degrees Celsius) of device when measurement was made. | |
261 | * | |
262 | * 2) Gain table idx used to achieve the target measurement power. | |
263 | * This refers to the "well-known" gain tables (see 4965.h). | |
264 | * | |
265 | * 3) Actual measured output power, in half-dBm ("34" = 17 dBm). | |
266 | * | |
267 | * 4) RF power amplifier detector level measurement (not used). | |
268 | */ | |
269 | struct il_eeprom_calib_measure { | |
270 | u8 temperature; /* Device temperature (Celsius) */ | |
271 | u8 gain_idx; /* Index into gain table */ | |
272 | u8 actual_pow; /* Measured RF output power, half-dBm */ | |
273 | s8 pa_det; /* Power amp detector level (not used) */ | |
274 | } __packed; | |
275 | ||
47ef694d SG |
276 | /* |
277 | * measurement set for one channel. EEPROM contains: | |
278 | * | |
279 | * 1) Channel number measured | |
280 | * | |
281 | * 2) Measurements for each of 3 power levels for each of 2 radio transmitters | |
282 | * (a.k.a. "tx chains") (6 measurements altogether) | |
283 | */ | |
284 | struct il_eeprom_calib_ch_info { | |
285 | u8 ch_num; | |
286 | struct il_eeprom_calib_measure | |
e7392364 SG |
287 | measurements[EEPROM_TX_POWER_TX_CHAINS] |
288 | [EEPROM_TX_POWER_MEASUREMENTS]; | |
47ef694d SG |
289 | } __packed; |
290 | ||
291 | /* | |
292 | * txpower subband info. | |
293 | * | |
294 | * For each frequency subband, EEPROM contains the following: | |
295 | * | |
296 | * 1) First and last channels within range of the subband. "0" values | |
297 | * indicate that this sample set is not being used. | |
298 | * | |
299 | * 2) Sample measurement sets for 2 channels close to the range endpoints. | |
300 | */ | |
301 | struct il_eeprom_calib_subband_info { | |
e7392364 SG |
302 | u8 ch_from; /* channel number of lowest channel in subband */ |
303 | u8 ch_to; /* channel number of highest channel in subband */ | |
47ef694d SG |
304 | struct il_eeprom_calib_ch_info ch1; |
305 | struct il_eeprom_calib_ch_info ch2; | |
306 | } __packed; | |
307 | ||
47ef694d SG |
308 | /* |
309 | * txpower calibration info. EEPROM contains: | |
310 | * | |
311 | * 1) Factory-measured saturation power levels (maximum levels at which | |
312 | * tx power amplifier can output a signal without too much distortion). | |
313 | * There is one level for 2.4 GHz band and one for 5 GHz band. These | |
314 | * values apply to all channels within each of the bands. | |
315 | * | |
316 | * 2) Factory-measured power supply voltage level. This is assumed to be | |
317 | * constant (i.e. same value applies to all channels/bands) while the | |
318 | * factory measurements are being made. | |
319 | * | |
320 | * 3) Up to 8 sets of factory-measured txpower calibration values. | |
321 | * These are for different frequency ranges, since txpower gain | |
322 | * characteristics of the analog radio circuitry vary with frequency. | |
323 | * | |
324 | * Not all sets need to be filled with data; | |
325 | * struct il_eeprom_calib_subband_info contains range of channels | |
326 | * (0 if unused) for each set of data. | |
327 | */ | |
328 | struct il_eeprom_calib_info { | |
329 | u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */ | |
330 | u8 saturation_power52; /* half-dBm */ | |
331 | __le16 voltage; /* signed */ | |
e7392364 | 332 | struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS]; |
47ef694d SG |
333 | } __packed; |
334 | ||
47ef694d SG |
335 | /* General */ |
336 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ | |
337 | #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ | |
338 | #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ | |
339 | #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ | |
340 | #define EEPROM_VERSION (2*0x44) /* 2 bytes */ | |
341 | #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ | |
342 | #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ | |
343 | #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ | |
344 | #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ | |
345 | #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ | |
346 | ||
347 | /* The following masks are to be applied on EEPROM_RADIO_CONFIG */ | |
e7392364 SG |
348 | #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ |
349 | #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ | |
350 | #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ | |
351 | #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ | |
352 | #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ | |
353 | #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ | |
47ef694d SG |
354 | |
355 | #define EEPROM_3945_RF_CFG_TYPE_MAX 0x0 | |
356 | #define EEPROM_4965_RF_CFG_TYPE_MAX 0x1 | |
357 | ||
358 | /* | |
359 | * Per-channel regulatory data. | |
360 | * | |
361 | * Each channel that *might* be supported by iwl has a fixed location | |
362 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory | |
363 | * txpower (MSB). | |
364 | * | |
365 | * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz) | |
366 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. | |
367 | * | |
368 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
369 | */ | |
e7392364 | 370 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ |
47ef694d SG |
371 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ |
372 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ | |
373 | ||
374 | /* | |
375 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | |
376 | * 5.0 GHz channels 7, 8, 11, 12, 16 | |
377 | * (4915-5080MHz) (none of these is ever supported) | |
378 | */ | |
379 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ | |
380 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ | |
381 | ||
382 | /* | |
383 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
384 | * (5170-5320MHz) | |
385 | */ | |
386 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ | |
387 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ | |
388 | ||
389 | /* | |
390 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
391 | * (5500-5700MHz) | |
392 | */ | |
393 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ | |
394 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ | |
395 | ||
396 | /* | |
397 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | |
398 | * (5725-5825MHz) | |
399 | */ | |
400 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ | |
401 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ | |
402 | ||
403 | /* | |
404 | * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11) | |
405 | * | |
406 | * The channel listed is the center of the lower 20 MHz half of the channel. | |
407 | * The overall center frequency is actually 2 channels (10 MHz) above that, | |
408 | * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away | |
409 | * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5, | |
410 | * and the overall HT40 channel width centers on channel 3. | |
411 | * | |
412 | * NOTE: The RXON command uses 20 MHz channel numbers to specify the | |
413 | * control channel to which to tune. RXON also specifies whether the | |
414 | * control channel is the upper or lower half of a HT40 channel. | |
415 | * | |
416 | * NOTE: 4965 does not support HT40 channels on 2.4 GHz. | |
417 | */ | |
418 | #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */ | |
419 | ||
420 | /* | |
421 | * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64), | |
422 | * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161) | |
423 | */ | |
424 | #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */ | |
425 | ||
426 | #define EEPROM_REGULATORY_BAND_NO_HT40 (0) | |
427 | ||
47ef694d SG |
428 | int il_eeprom_init(struct il_priv *il); |
429 | void il_eeprom_free(struct il_priv *il); | |
e7392364 | 430 | const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset); |
47ef694d SG |
431 | u16 il_eeprom_query16(const struct il_priv *il, size_t offset); |
432 | int il_init_channel_map(struct il_priv *il); | |
433 | void il_free_channel_map(struct il_priv *il); | |
e7392364 SG |
434 | const struct il_channel_info *il_get_channel_info(const struct il_priv *il, |
435 | enum ieee80211_band band, | |
436 | u16 channel); | |
47ef694d | 437 | |
e94a4099 SG |
438 | #define IL_NUM_SCAN_RATES (2) |
439 | ||
440 | struct il4965_channel_tgd_info { | |
441 | u8 type; | |
442 | s8 max_power; | |
443 | }; | |
444 | ||
445 | struct il4965_channel_tgh_info { | |
446 | s64 last_radar_time; | |
447 | }; | |
448 | ||
449 | #define IL4965_MAX_RATE (33) | |
450 | ||
451 | struct il3945_clip_group { | |
452 | /* maximum power level to prevent clipping for each rate, derived by | |
453 | * us from this band's saturation power in EEPROM */ | |
454 | const s8 clip_powers[IL_MAX_RATES]; | |
455 | }; | |
456 | ||
457 | /* current Tx power values to use, one for each rate for each channel. | |
458 | * requested power is limited by: | |
459 | * -- regulatory EEPROM limits for this channel | |
460 | * -- hardware capabilities (clip-powers) | |
461 | * -- spectrum management | |
462 | * -- user preference (e.g. iwconfig) | |
463 | * when requested power is set, base power idx must also be set. */ | |
464 | struct il3945_channel_power_info { | |
465 | struct il3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
466 | s8 power_table_idx; /* actual (compenst'd) idx into gain table */ | |
467 | s8 base_power_idx; /* gain idx for power at factory temp. */ | |
468 | s8 requested_power; /* power (dBm) requested for this chnl/rate */ | |
469 | }; | |
470 | ||
471 | /* current scan Tx power values to use, one for each scan rate for each | |
472 | * channel. */ | |
473 | struct il3945_scan_power_info { | |
474 | struct il3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
475 | s8 power_table_idx; /* actual (compenst'd) idx into gain table */ | |
476 | s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ | |
477 | }; | |
478 | ||
479 | /* | |
480 | * One for each channel, holds all channel setup data | |
481 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
482 | * with one another! | |
483 | */ | |
484 | struct il_channel_info { | |
485 | struct il4965_channel_tgd_info tgd; | |
486 | struct il4965_channel_tgh_info tgh; | |
487 | struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */ | |
488 | struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for | |
489 | * HT40 channel */ | |
490 | ||
e7392364 SG |
491 | u8 channel; /* channel number */ |
492 | u8 flags; /* flags copied from EEPROM */ | |
493 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
494 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ | |
495 | s8 min_power; /* always 0 */ | |
496 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
e94a4099 | 497 | |
e7392364 SG |
498 | u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */ |
499 | u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */ | |
e94a4099 SG |
500 | enum ieee80211_band band; |
501 | ||
502 | /* HT40 channel info */ | |
503 | s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
504 | u8 ht40_flags; /* flags copied from EEPROM */ | |
e7392364 | 505 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ |
e94a4099 SG |
506 | |
507 | /* Radio/DSP gain settings for each "normal" data Tx rate. | |
508 | * These include, in addition to RF and DSP gain, a few fields for | |
509 | * remembering/modifying gain settings (idxes). */ | |
510 | struct il3945_channel_power_info power_info[IL4965_MAX_RATE]; | |
511 | ||
512 | /* Radio/DSP gain settings for each scan rate, for directed scans. */ | |
513 | struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES]; | |
514 | }; | |
515 | ||
516 | #define IL_TX_FIFO_BK 0 /* shared */ | |
517 | #define IL_TX_FIFO_BE 1 | |
518 | #define IL_TX_FIFO_VI 2 /* shared */ | |
519 | #define IL_TX_FIFO_VO 3 | |
520 | #define IL_TX_FIFO_UNUSED -1 | |
521 | ||
522 | /* Minimum number of queues. MAX_NUM is defined in hw specific files. | |
523 | * Set the minimum to accommodate the 4 standard TX queues, 1 command | |
524 | * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ | |
525 | #define IL_MIN_NUM_QUEUES 10 | |
526 | ||
527 | #define IL_DEFAULT_CMD_QUEUE_NUM 4 | |
528 | ||
529 | #define IEEE80211_DATA_LEN 2304 | |
530 | #define IEEE80211_4ADDR_LEN 30 | |
531 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
532 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
533 | ||
534 | struct il_frame { | |
535 | union { | |
536 | struct ieee80211_hdr frame; | |
537 | struct il_tx_beacon_cmd beacon; | |
538 | u8 raw[IEEE80211_FRAME_LEN]; | |
539 | u8 cmd[360]; | |
540 | } u; | |
541 | struct list_head list; | |
542 | }; | |
543 | ||
e94a4099 SG |
544 | enum { |
545 | CMD_SYNC = 0, | |
546 | CMD_SIZE_NORMAL = 0, | |
547 | CMD_NO_SKB = 0, | |
548 | CMD_SIZE_HUGE = (1 << 0), | |
549 | CMD_ASYNC = (1 << 1), | |
550 | CMD_WANT_SKB = (1 << 2), | |
551 | CMD_MAPPED = (1 << 3), | |
552 | }; | |
553 | ||
554 | #define DEF_CMD_PAYLOAD_SIZE 320 | |
555 | ||
556 | /** | |
557 | * struct il_device_cmd | |
558 | * | |
559 | * For allocation of the command and tx queues, this establishes the overall | |
560 | * size of the largest command we send to uCode, except for a scan command | |
561 | * (which is relatively huge; space is allocated separately). | |
562 | */ | |
563 | struct il_device_cmd { | |
564 | struct il_cmd_header hdr; /* uCode API */ | |
565 | union { | |
566 | u32 flags; | |
567 | u8 val8; | |
568 | u16 val16; | |
569 | u32 val32; | |
570 | struct il_tx_cmd tx; | |
571 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | |
572 | } __packed cmd; | |
573 | } __packed; | |
574 | ||
575 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd)) | |
576 | ||
e94a4099 SG |
577 | struct il_host_cmd { |
578 | const void *data; | |
579 | unsigned long reply_page; | |
1722f8e1 SG |
580 | void (*callback) (struct il_priv *il, struct il_device_cmd *cmd, |
581 | struct il_rx_pkt *pkt); | |
e94a4099 SG |
582 | u32 flags; |
583 | u16 len; | |
584 | u8 id; | |
585 | }; | |
586 | ||
587 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 | |
588 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
589 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
590 | ||
591 | /** | |
592 | * struct il_rx_queue - Rx queue | |
593 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) | |
594 | * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) | |
595 | * @read: Shared idx to newest available Rx buffer | |
596 | * @write: Shared idx to oldest written Rx packet | |
597 | * @free_count: Number of pre-allocated buffers in rx_free | |
598 | * @rx_free: list of free SKBs for use | |
599 | * @rx_used: List of Rx buffers with no SKB | |
600 | * @need_update: flag to indicate we need to update read/write idx | |
601 | * @rb_stts: driver's pointer to receive buffer status | |
602 | * @rb_stts_dma: bus address of receive buffer status | |
603 | * | |
604 | * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs | |
605 | */ | |
606 | struct il_rx_queue { | |
607 | __le32 *bd; | |
608 | dma_addr_t bd_dma; | |
609 | struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; | |
610 | struct il_rx_buf *queue[RX_QUEUE_SIZE]; | |
611 | u32 read; | |
612 | u32 write; | |
613 | u32 free_count; | |
614 | u32 write_actual; | |
615 | struct list_head rx_free; | |
616 | struct list_head rx_used; | |
617 | int need_update; | |
618 | struct il_rb_status *rb_stts; | |
619 | dma_addr_t rb_stts_dma; | |
620 | spinlock_t lock; | |
621 | }; | |
622 | ||
623 | #define IL_SUPPORTED_RATES_IE_LEN 8 | |
624 | ||
625 | #define MAX_TID_COUNT 9 | |
626 | ||
627 | #define IL_INVALID_RATE 0xFF | |
628 | #define IL_INVALID_VALUE -1 | |
629 | ||
630 | /** | |
631 | * struct il_ht_agg -- aggregation status while waiting for block-ack | |
632 | * @txq_id: Tx queue used for Tx attempt | |
633 | * @frame_count: # frames attempted by Tx command | |
634 | * @wait_for_ba: Expect block-ack before next Tx reply | |
635 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win | |
636 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win | |
637 | * @bitmap1: High order, one bit for each frame pending ACK in Tx win | |
638 | * @rate_n_flags: Rate at which Tx was attempted | |
639 | * | |
640 | * If C_TX indicates that aggregation was attempted, driver must wait | |
641 | * for block ack (N_COMPRESSED_BA). This struct stores tx reply info | |
642 | * until block ack arrives. | |
643 | */ | |
644 | struct il_ht_agg { | |
645 | u16 txq_id; | |
646 | u16 frame_count; | |
647 | u16 wait_for_ba; | |
648 | u16 start_idx; | |
649 | u64 bitmap; | |
650 | u32 rate_n_flags; | |
651 | #define IL_AGG_OFF 0 | |
652 | #define IL_AGG_ON 1 | |
653 | #define IL_EMPTYING_HW_QUEUE_ADDBA 2 | |
654 | #define IL_EMPTYING_HW_QUEUE_DELBA 3 | |
655 | u8 state; | |
656 | }; | |
657 | ||
e94a4099 | 658 | struct il_tid_data { |
e7392364 | 659 | u16 seq_number; /* 4965 only */ |
e94a4099 SG |
660 | u16 tfds_in_queue; |
661 | struct il_ht_agg agg; | |
662 | }; | |
663 | ||
664 | struct il_hw_key { | |
665 | u32 cipher; | |
666 | int keylen; | |
667 | u8 keyidx; | |
668 | u8 key[32]; | |
669 | }; | |
670 | ||
671 | union il_ht_rate_supp { | |
672 | u16 rates; | |
673 | struct { | |
674 | u8 siso_rate; | |
675 | u8 mimo_rate; | |
676 | }; | |
677 | }; | |
678 | ||
679 | #define CFG_HT_RX_AMPDU_FACTOR_8K (0x0) | |
680 | #define CFG_HT_RX_AMPDU_FACTOR_16K (0x1) | |
681 | #define CFG_HT_RX_AMPDU_FACTOR_32K (0x2) | |
682 | #define CFG_HT_RX_AMPDU_FACTOR_64K (0x3) | |
683 | #define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K | |
684 | #define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K | |
685 | #define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K | |
686 | ||
687 | /* | |
688 | * Maximal MPDU density for TX aggregation | |
689 | * 4 - 2us density | |
690 | * 5 - 4us density | |
691 | * 6 - 8us density | |
692 | * 7 - 16us density | |
693 | */ | |
694 | #define CFG_HT_MPDU_DENSITY_2USEC (0x4) | |
695 | #define CFG_HT_MPDU_DENSITY_4USEC (0x5) | |
696 | #define CFG_HT_MPDU_DENSITY_8USEC (0x6) | |
697 | #define CFG_HT_MPDU_DENSITY_16USEC (0x7) | |
698 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC | |
699 | #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC | |
700 | #define CFG_HT_MPDU_DENSITY_MIN (0x1) | |
701 | ||
702 | struct il_ht_config { | |
703 | bool single_chain_sufficient; | |
e7392364 | 704 | enum ieee80211_smps_mode smps; /* current smps mode */ |
e94a4099 SG |
705 | }; |
706 | ||
707 | /* QoS structures */ | |
708 | struct il_qos_info { | |
709 | int qos_active; | |
710 | struct il_qosparam_cmd def_qos_parm; | |
711 | }; | |
712 | ||
713 | /* | |
714 | * Structure should be accessed with sta_lock held. When station addition | |
715 | * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only | |
716 | * the commands (il_addsta_cmd and il_link_quality_cmd) without | |
717 | * sta_lock held. | |
718 | */ | |
719 | struct il_station_entry { | |
720 | struct il_addsta_cmd sta; | |
721 | struct il_tid_data tid[MAX_TID_COUNT]; | |
6aa0c254 | 722 | u8 used; |
e94a4099 SG |
723 | struct il_hw_key keyinfo; |
724 | struct il_link_quality_cmd *lq; | |
725 | }; | |
726 | ||
727 | struct il_station_priv_common { | |
e94a4099 SG |
728 | u8 sta_id; |
729 | }; | |
730 | ||
e94a4099 SG |
731 | /** |
732 | * struct il_vif_priv - driver's ilate per-interface information | |
733 | * | |
734 | * When mac80211 allocates a virtual interface, it can allocate | |
735 | * space for us to put data into. | |
736 | */ | |
737 | struct il_vif_priv { | |
e94a4099 SG |
738 | u8 ibss_bssid_sta_id; |
739 | }; | |
740 | ||
741 | /* one for each uCode image (inst/data, boot/init/runtime) */ | |
742 | struct fw_desc { | |
743 | void *v_addr; /* access by driver */ | |
744 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
745 | u32 len; /* bytes */ | |
746 | }; | |
747 | ||
748 | /* uCode file layout */ | |
749 | struct il_ucode_header { | |
e7392364 | 750 | __le32 ver; /* major/minor/API/serial */ |
e94a4099 SG |
751 | struct { |
752 | __le32 inst_size; /* bytes of runtime code */ | |
753 | __le32 data_size; /* bytes of runtime data */ | |
754 | __le32 init_size; /* bytes of init code */ | |
755 | __le32 init_data_size; /* bytes of init data */ | |
756 | __le32 boot_size; /* bytes of bootstrap code */ | |
e7392364 | 757 | u8 data[0]; /* in same order as sizes */ |
e94a4099 SG |
758 | } v1; |
759 | }; | |
760 | ||
761 | struct il4965_ibss_seq { | |
762 | u8 mac[ETH_ALEN]; | |
763 | u16 seq_num; | |
764 | u16 frag_num; | |
765 | unsigned long packet_time; | |
766 | struct list_head list; | |
767 | }; | |
768 | ||
769 | struct il_sensitivity_ranges { | |
770 | u16 min_nrg_cck; | |
771 | u16 max_nrg_cck; | |
772 | ||
773 | u16 nrg_th_cck; | |
774 | u16 nrg_th_ofdm; | |
775 | ||
776 | u16 auto_corr_min_ofdm; | |
777 | u16 auto_corr_min_ofdm_mrc; | |
778 | u16 auto_corr_min_ofdm_x1; | |
779 | u16 auto_corr_min_ofdm_mrc_x1; | |
780 | ||
781 | u16 auto_corr_max_ofdm; | |
782 | u16 auto_corr_max_ofdm_mrc; | |
783 | u16 auto_corr_max_ofdm_x1; | |
784 | u16 auto_corr_max_ofdm_mrc_x1; | |
785 | ||
786 | u16 auto_corr_max_cck; | |
787 | u16 auto_corr_max_cck_mrc; | |
788 | u16 auto_corr_min_cck; | |
789 | u16 auto_corr_min_cck_mrc; | |
790 | ||
791 | u16 barker_corr_th_min; | |
792 | u16 barker_corr_th_min_mrc; | |
793 | u16 nrg_th_cca; | |
794 | }; | |
795 | ||
e94a4099 SG |
796 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
797 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
798 | ||
e94a4099 SG |
799 | /** |
800 | * struct il_hw_params | |
b16db50a | 801 | * @bcast_id: f/w broadcast station ID |
e94a4099 SG |
802 | * @max_txq_num: Max # Tx queues supported |
803 | * @dma_chnl_num: Number of Tx DMA/FIFO channels | |
804 | * @scd_bc_tbls_size: size of scheduler byte count tables | |
805 | * @tfd_size: TFD size | |
806 | * @tx/rx_chains_num: Number of TX/RX chains | |
807 | * @valid_tx/rx_ant: usable antennas | |
808 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) | |
809 | * @max_rxq_log: Log-base-2 of max_rxq_size | |
810 | * @rx_page_order: Rx buffer page order | |
811 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR | |
812 | * @max_stations: | |
813 | * @ht40_channel: is 40MHz width possible in band 2.4 | |
814 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) | |
815 | * @sw_crypto: 0 for hw, 1 for sw | |
816 | * @max_xxx_size: for ucode uses | |
817 | * @ct_kill_threshold: temperature threshold | |
818 | * @beacon_time_tsf_bits: number of valid tsf bits for beacon time | |
819 | * @struct il_sensitivity_ranges: range of sensitivity values | |
820 | */ | |
821 | struct il_hw_params { | |
b16db50a | 822 | u8 bcast_id; |
e94a4099 SG |
823 | u8 max_txq_num; |
824 | u8 dma_chnl_num; | |
825 | u16 scd_bc_tbls_size; | |
826 | u32 tfd_size; | |
e7392364 SG |
827 | u8 tx_chains_num; |
828 | u8 rx_chains_num; | |
829 | u8 valid_tx_ant; | |
830 | u8 valid_rx_ant; | |
e94a4099 SG |
831 | u16 max_rxq_size; |
832 | u16 max_rxq_log; | |
833 | u32 rx_page_order; | |
834 | u32 rx_wrt_ptr_reg; | |
e7392364 SG |
835 | u8 max_stations; |
836 | u8 ht40_channel; | |
837 | u8 max_beacon_itrvl; /* in 1024 ms */ | |
e94a4099 SG |
838 | u32 max_inst_size; |
839 | u32 max_data_size; | |
840 | u32 max_bsm_size; | |
e7392364 | 841 | u32 ct_kill_threshold; /* value in hw-dependent units */ |
e94a4099 SG |
842 | u16 beacon_time_tsf_bits; |
843 | const struct il_sensitivity_ranges *sens; | |
844 | }; | |
845 | ||
e94a4099 SG |
846 | /****************************************************************************** |
847 | * | |
848 | * Functions implemented in core module which are forward declared here | |
849 | * for use by iwl-[4-5].c | |
850 | * | |
851 | * NOTE: The implementation of these functions are not hardware specific | |
852 | * which is why they are in the core module files. | |
853 | * | |
854 | * Naming convention -- | |
855 | * il_ <-- Is part of iwlwifi | |
856 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) | |
857 | * il4965_bg_ <-- Called from work queue context | |
858 | * il4965_mac_ <-- mac80211 callback | |
859 | * | |
860 | ****************************************************************************/ | |
6890ba72 | 861 | void il4965_update_chain_flags(struct il_priv *il); |
e94a4099 | 862 | extern const u8 il_bcast_addr[ETH_ALEN]; |
6890ba72 | 863 | int il_queue_space(const struct il_queue *q); |
e7392364 SG |
864 | static inline int |
865 | il_queue_used(const struct il_queue *q, int i) | |
e94a4099 | 866 | { |
e7392364 SG |
867 | return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr && |
868 | i < q->write_ptr) : !(i < | |
869 | q->read_ptr | |
870 | && i >= | |
871 | q-> | |
872 | write_ptr); | |
e94a4099 SG |
873 | } |
874 | ||
e7392364 SG |
875 | static inline u8 |
876 | il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge) | |
e94a4099 SG |
877 | { |
878 | /* | |
879 | * This is for init calibration result and scan command which | |
880 | * required buffer > TFD_MAX_PAYLOAD_SIZE, | |
881 | * the big buffer at end of command array | |
882 | */ | |
883 | if (is_huge) | |
884 | return q->n_win; /* must be power of 2 */ | |
885 | ||
886 | /* Otherwise, use normal size buffers */ | |
887 | return idx & (q->n_win - 1); | |
888 | } | |
889 | ||
e94a4099 SG |
890 | struct il_dma_ptr { |
891 | dma_addr_t dma; | |
892 | void *addr; | |
893 | size_t size; | |
894 | }; | |
895 | ||
896 | #define IL_OPERATION_MODE_AUTO 0 | |
897 | #define IL_OPERATION_MODE_HT_ONLY 1 | |
898 | #define IL_OPERATION_MODE_MIXED 2 | |
899 | #define IL_OPERATION_MODE_20MHZ 3 | |
900 | ||
901 | #define IL_TX_CRC_SIZE 4 | |
902 | #define IL_TX_DELIMITER_SIZE 4 | |
903 | ||
904 | #define TX_POWER_IL_ILLEGAL_VOLTAGE -10000 | |
905 | ||
906 | /* Sensitivity and chain noise calibration */ | |
907 | #define INITIALIZATION_VALUE 0xFFFF | |
908 | #define IL4965_CAL_NUM_BEACONS 20 | |
909 | #define IL_CAL_NUM_BEACONS 16 | |
910 | #define MAXIMUM_ALLOWED_PATHLOSS 15 | |
911 | ||
912 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 | |
913 | ||
914 | #define MAX_FA_OFDM 50 | |
915 | #define MIN_FA_OFDM 5 | |
916 | #define MAX_FA_CCK 50 | |
917 | #define MIN_FA_CCK 5 | |
918 | ||
919 | #define AUTO_CORR_STEP_OFDM 1 | |
920 | ||
921 | #define AUTO_CORR_STEP_CCK 3 | |
922 | #define AUTO_CORR_MAX_TH_CCK 160 | |
923 | ||
924 | #define NRG_DIFF 2 | |
925 | #define NRG_STEP_CCK 2 | |
926 | #define NRG_MARGIN 8 | |
927 | #define MAX_NUMBER_CCK_NO_FA 100 | |
928 | ||
929 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
930 | ||
931 | #define CHAIN_A 0 | |
932 | #define CHAIN_B 1 | |
933 | #define CHAIN_C 2 | |
934 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
935 | #define ALL_BAND_FILTER 0xFF00 | |
936 | #define IN_BAND_FILTER 0xFF | |
937 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
938 | ||
939 | #define NRG_NUM_PREV_STAT_L 20 | |
940 | #define NUM_RX_CHAINS 3 | |
941 | ||
942 | enum il4965_false_alarm_state { | |
943 | IL_FA_TOO_MANY = 0, | |
944 | IL_FA_TOO_FEW = 1, | |
945 | IL_FA_GOOD_RANGE = 2, | |
946 | }; | |
947 | ||
948 | enum il4965_chain_noise_state { | |
e7392364 | 949 | IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
e94a4099 SG |
950 | IL_CHAIN_NOISE_ACCUMULATE, |
951 | IL_CHAIN_NOISE_CALIBRATED, | |
952 | IL_CHAIN_NOISE_DONE, | |
953 | }; | |
954 | ||
e94a4099 SG |
955 | enum ucode_type { |
956 | UCODE_NONE = 0, | |
957 | UCODE_INIT, | |
958 | UCODE_RT | |
959 | }; | |
960 | ||
961 | /* Sensitivity calib data */ | |
962 | struct il_sensitivity_data { | |
963 | u32 auto_corr_ofdm; | |
964 | u32 auto_corr_ofdm_mrc; | |
965 | u32 auto_corr_ofdm_x1; | |
966 | u32 auto_corr_ofdm_mrc_x1; | |
967 | u32 auto_corr_cck; | |
968 | u32 auto_corr_cck_mrc; | |
969 | ||
970 | u32 last_bad_plcp_cnt_ofdm; | |
971 | u32 last_fa_cnt_ofdm; | |
972 | u32 last_bad_plcp_cnt_cck; | |
973 | u32 last_fa_cnt_cck; | |
974 | ||
975 | u32 nrg_curr_state; | |
976 | u32 nrg_prev_state; | |
977 | u32 nrg_value[10]; | |
e7392364 | 978 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; |
e94a4099 SG |
979 | u32 nrg_silence_ref; |
980 | u32 nrg_energy_idx; | |
981 | u32 nrg_silence_idx; | |
982 | u32 nrg_th_cck; | |
983 | s32 nrg_auto_corr_silence_diff; | |
984 | u32 num_in_cck_no_fa; | |
985 | u32 nrg_th_ofdm; | |
986 | ||
987 | u16 barker_corr_th_min; | |
988 | u16 barker_corr_th_min_mrc; | |
989 | u16 nrg_th_cca; | |
990 | }; | |
991 | ||
992 | /* Chain noise (differential Rx gain) calib data */ | |
993 | struct il_chain_noise_data { | |
994 | u32 active_chains; | |
995 | u32 chain_noise_a; | |
996 | u32 chain_noise_b; | |
997 | u32 chain_noise_c; | |
998 | u32 chain_signal_a; | |
999 | u32 chain_signal_b; | |
1000 | u32 chain_signal_c; | |
1001 | u16 beacon_count; | |
1002 | u8 disconn_array[NUM_RX_CHAINS]; | |
1003 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
1004 | u8 radio_write; | |
1005 | u8 state; | |
1006 | }; | |
1007 | ||
e7392364 | 1008 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
e94a4099 SG |
1009 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ |
1010 | ||
1011 | #define IL_TRAFFIC_ENTRIES (256) | |
1012 | #define IL_TRAFFIC_ENTRY_SIZE (64) | |
1013 | ||
1014 | enum { | |
1015 | MEASUREMENT_READY = (1 << 0), | |
1016 | MEASUREMENT_ACTIVE = (1 << 1), | |
1017 | }; | |
1018 | ||
1019 | /* interrupt stats */ | |
1020 | struct isr_stats { | |
1021 | u32 hw; | |
1022 | u32 sw; | |
1023 | u32 err_code; | |
1024 | u32 sch; | |
1025 | u32 alive; | |
1026 | u32 rfkill; | |
1027 | u32 ctkill; | |
1028 | u32 wakeup; | |
1029 | u32 rx; | |
1030 | u32 handlers[IL_CN_MAX]; | |
1031 | u32 tx; | |
1032 | u32 unhandled; | |
1033 | }; | |
1034 | ||
1035 | /* management stats */ | |
1036 | enum il_mgmt_stats { | |
1037 | MANAGEMENT_ASSOC_REQ = 0, | |
1038 | MANAGEMENT_ASSOC_RESP, | |
1039 | MANAGEMENT_REASSOC_REQ, | |
1040 | MANAGEMENT_REASSOC_RESP, | |
1041 | MANAGEMENT_PROBE_REQ, | |
1042 | MANAGEMENT_PROBE_RESP, | |
1043 | MANAGEMENT_BEACON, | |
1044 | MANAGEMENT_ATIM, | |
1045 | MANAGEMENT_DISASSOC, | |
1046 | MANAGEMENT_AUTH, | |
1047 | MANAGEMENT_DEAUTH, | |
1048 | MANAGEMENT_ACTION, | |
1049 | MANAGEMENT_MAX, | |
1050 | }; | |
1051 | /* control stats */ | |
1052 | enum il_ctrl_stats { | |
e7392364 | 1053 | CONTROL_BACK_REQ = 0, |
e94a4099 SG |
1054 | CONTROL_BACK, |
1055 | CONTROL_PSPOLL, | |
1056 | CONTROL_RTS, | |
1057 | CONTROL_CTS, | |
1058 | CONTROL_ACK, | |
1059 | CONTROL_CFEND, | |
1060 | CONTROL_CFENDACK, | |
1061 | CONTROL_MAX, | |
1062 | }; | |
1063 | ||
1064 | struct traffic_stats { | |
1065 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
1066 | u32 mgmt[MANAGEMENT_MAX]; | |
1067 | u32 ctrl[CONTROL_MAX]; | |
1068 | u32 data_cnt; | |
1069 | u64 data_bytes; | |
1070 | #endif | |
1071 | }; | |
1072 | ||
1073 | /* | |
1074 | * host interrupt timeout value | |
1075 | * used with setting interrupt coalescing timer | |
1076 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
1077 | * | |
1078 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
1079 | * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs | |
1080 | */ | |
1081 | #define IL_HOST_INT_TIMEOUT_MAX (0xFF) | |
1082 | #define IL_HOST_INT_TIMEOUT_DEF (0x40) | |
1083 | #define IL_HOST_INT_TIMEOUT_MIN (0x0) | |
1084 | #define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) | |
1085 | #define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) | |
1086 | #define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) | |
1087 | ||
1088 | #define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5) | |
1089 | ||
1090 | /* TX queue watchdog timeouts in mSecs */ | |
1091 | #define IL_DEF_WD_TIMEOUT (2000) | |
1092 | #define IL_LONG_WD_TIMEOUT (10000) | |
1093 | #define IL_MAX_WD_TIMEOUT (120000) | |
1094 | ||
1095 | struct il_force_reset { | |
1096 | int reset_request_count; | |
1097 | int reset_success_count; | |
1098 | int reset_reject_count; | |
1099 | unsigned long reset_duration; | |
1100 | unsigned long last_force_reset_jiffies; | |
1101 | }; | |
1102 | ||
1103 | /* extend beacon time format bit shifting */ | |
1104 | /* | |
1105 | * for _3945 devices | |
1106 | * bits 31:24 - extended | |
1107 | * bits 23:0 - interval | |
1108 | */ | |
1109 | #define IL3945_EXT_BEACON_TIME_POS 24 | |
1110 | /* | |
1111 | * for _4965 devices | |
1112 | * bits 31:22 - extended | |
1113 | * bits 21:0 - interval | |
1114 | */ | |
1115 | #define IL4965_EXT_BEACON_TIME_POS 22 | |
1116 | ||
1117 | struct il_rxon_context { | |
1118 | struct ieee80211_vif *vif; | |
e94a4099 SG |
1119 | }; |
1120 | ||
99412002 SG |
1121 | struct il_power_mgr { |
1122 | struct il_powertable_cmd sleep_cmd; | |
1123 | struct il_powertable_cmd sleep_cmd_next; | |
1124 | int debug_sleep_level_override; | |
1125 | bool pci_pm; | |
dbdac2b5 | 1126 | bool ps_disabled; |
99412002 SG |
1127 | }; |
1128 | ||
e94a4099 | 1129 | struct il_priv { |
e94a4099 SG |
1130 | struct ieee80211_hw *hw; |
1131 | struct ieee80211_channel *ieee_channels; | |
1132 | struct ieee80211_rate *ieee_rates; | |
93b7654e | 1133 | |
e94a4099 | 1134 | struct il_cfg *cfg; |
c39ae9fd | 1135 | const struct il_ops *ops; |
93b7654e SG |
1136 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
1137 | const struct il_debugfs_ops *debugfs_ops; | |
1138 | #endif | |
e94a4099 SG |
1139 | |
1140 | /* temporary frame storage list */ | |
1141 | struct list_head free_frames; | |
1142 | int frames_count; | |
1143 | ||
1144 | enum ieee80211_band band; | |
1145 | int alloc_rxb_page; | |
1146 | ||
1722f8e1 SG |
1147 | void (*handlers[IL_CN_MAX]) (struct il_priv *il, |
1148 | struct il_rx_buf *rxb); | |
e94a4099 SG |
1149 | |
1150 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; | |
1151 | ||
1152 | /* spectrum measurement report caching */ | |
1153 | struct il_spectrum_notification measure_report; | |
1154 | u8 measurement_status; | |
1155 | ||
1156 | /* ucode beacon time */ | |
1157 | u32 ucode_beacon_time; | |
1158 | int missed_beacon_threshold; | |
1159 | ||
1160 | /* track IBSS manager (last beacon) status */ | |
1161 | u32 ibss_manager; | |
1162 | ||
1163 | /* force reset */ | |
1164 | struct il_force_reset force_reset; | |
1165 | ||
1166 | /* we allocate array of il_channel_info for NIC's valid channels. | |
1167 | * Access via channel # using indirect idx array */ | |
1168 | struct il_channel_info *channel_info; /* channel info array */ | |
1169 | u8 channel_count; /* # of channels */ | |
1170 | ||
1171 | /* thermal calibration */ | |
1172 | s32 temperature; /* degrees Kelvin */ | |
1173 | s32 last_temperature; | |
1174 | ||
e94a4099 SG |
1175 | /* Scan related variables */ |
1176 | unsigned long scan_start; | |
1177 | unsigned long scan_start_tsf; | |
1178 | void *scan_cmd; | |
1179 | enum ieee80211_band scan_band; | |
1180 | struct cfg80211_scan_request *scan_request; | |
1181 | struct ieee80211_vif *scan_vif; | |
1182 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; | |
1183 | u8 mgmt_tx_ant; | |
1184 | ||
1185 | /* spinlock */ | |
1186 | spinlock_t lock; /* protect general shared data */ | |
1187 | spinlock_t hcmd_lock; /* protect hcmd */ | |
1188 | spinlock_t reg_lock; /* protect hw register access */ | |
1189 | struct mutex mutex; | |
1190 | ||
1191 | /* basic pci-network driver stuff */ | |
1192 | struct pci_dev *pci_dev; | |
1193 | ||
1194 | /* pci hardware address support */ | |
1195 | void __iomem *hw_base; | |
e7392364 SG |
1196 | u32 hw_rev; |
1197 | u32 hw_wa_rev; | |
1198 | u8 rev_id; | |
e94a4099 SG |
1199 | |
1200 | /* command queue number */ | |
1201 | u8 cmd_queue; | |
1202 | ||
1203 | /* max number of station keys */ | |
1204 | u8 sta_key_max_num; | |
1205 | ||
1206 | /* EEPROM MAC addresses */ | |
1207 | struct mac_address addresses[1]; | |
1208 | ||
1209 | /* uCode images, save to reload in case of failure */ | |
e7392364 SG |
1210 | int fw_idx; /* firmware we're trying to load */ |
1211 | u32 ucode_ver; /* version of ucode, copy of | |
1212 | il_ucode.ver */ | |
e94a4099 SG |
1213 | struct fw_desc ucode_code; /* runtime inst */ |
1214 | struct fw_desc ucode_data; /* runtime data original */ | |
1215 | struct fw_desc ucode_data_backup; /* runtime data save/restore */ | |
1216 | struct fw_desc ucode_init; /* initialization inst */ | |
1217 | struct fw_desc ucode_init_data; /* initialization data */ | |
1218 | struct fw_desc ucode_boot; /* bootstrap inst */ | |
1219 | enum ucode_type ucode_type; | |
1220 | u8 ucode_write_complete; /* the image write is complete */ | |
1221 | char firmware_name[25]; | |
1222 | ||
83007196 | 1223 | struct ieee80211_vif *vif; |
e94a4099 | 1224 | |
8d44f2bd SG |
1225 | struct il_qos_info qos_data; |
1226 | ||
1c03c462 SG |
1227 | struct { |
1228 | bool enabled; | |
1229 | bool is_40mhz; | |
1230 | bool non_gf_sta_present; | |
1231 | u8 protection; | |
1232 | u8 extension_chan_offset; | |
1233 | } ht; | |
1234 | ||
c8b03958 SG |
1235 | /* |
1236 | * We declare this const so it can only be | |
1237 | * changed via explicit cast within the | |
1238 | * routines that actually update the physical | |
1239 | * hardware. | |
1240 | */ | |
1241 | const struct il_rxon_cmd active; | |
1242 | struct il_rxon_cmd staging; | |
1243 | ||
1244 | struct il_rxon_time_cmd timing; | |
1245 | ||
e94a4099 SG |
1246 | __le16 switch_channel; |
1247 | ||
1248 | /* 1st responses from initialize and runtime uCode images. | |
1249 | * _4965's initialize alive response contains some calibration data. */ | |
1250 | struct il_init_alive_resp card_alive_init; | |
1251 | struct il_alive_resp card_alive; | |
1252 | ||
1253 | u16 active_rate; | |
1254 | ||
1255 | u8 start_calib; | |
1256 | struct il_sensitivity_data sensitivity_data; | |
1257 | struct il_chain_noise_data chain_noise_data; | |
1258 | __le16 sensitivity_tbl[HD_TBL_SIZE]; | |
1259 | ||
1260 | struct il_ht_config current_ht_config; | |
1261 | ||
1262 | /* Rate scaling data */ | |
1263 | u8 retry_rate; | |
1264 | ||
1265 | wait_queue_head_t wait_command_queue; | |
1266 | ||
1267 | int activity_timer_active; | |
1268 | ||
1269 | /* Rx and Tx DMA processing queues */ | |
1270 | struct il_rx_queue rxq; | |
1271 | struct il_tx_queue *txq; | |
1272 | unsigned long txq_ctx_active_msk; | |
e7392364 SG |
1273 | struct il_dma_ptr kw; /* keep warm address */ |
1274 | struct il_dma_ptr scd_bc_tbls; | |
e94a4099 SG |
1275 | |
1276 | u32 scd_base_addr; /* scheduler sram base address */ | |
1277 | ||
1278 | unsigned long status; | |
1279 | ||
1280 | /* counts mgmt, ctl, and data packets */ | |
1281 | struct traffic_stats tx_stats; | |
1282 | struct traffic_stats rx_stats; | |
1283 | ||
1284 | /* counts interrupts */ | |
1285 | struct isr_stats isr_stats; | |
1286 | ||
1287 | struct il_power_mgr power_data; | |
1288 | ||
1289 | /* context information */ | |
e7392364 | 1290 | u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */ |
e94a4099 SG |
1291 | |
1292 | /* station table variables */ | |
1293 | ||
1294 | /* Note: if lock and sta_lock are needed, lock must be acquired first */ | |
1295 | spinlock_t sta_lock; | |
1296 | int num_stations; | |
1297 | struct il_station_entry stations[IL_STATION_COUNT]; | |
1298 | unsigned long ucode_key_table; | |
1299 | ||
1300 | /* queue refcounts */ | |
1301 | #define IL_MAX_HW_QUEUES 32 | |
1302 | unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)]; | |
c6af8074 SG |
1303 | #define IL_STOP_REASON_PASSIVE 0 |
1304 | unsigned long stop_reason; | |
e94a4099 SG |
1305 | /* for each AC */ |
1306 | atomic_t queue_stop_count[4]; | |
1307 | ||
1308 | /* Indication if ieee80211_ops->open has been called */ | |
1309 | u8 is_open; | |
1310 | ||
1311 | u8 mac80211_registered; | |
1312 | ||
1313 | /* eeprom -- this is in the card's little endian byte order */ | |
1314 | u8 *eeprom; | |
1315 | struct il_eeprom_calib_info *calib_info; | |
1316 | ||
1317 | enum nl80211_iftype iw_mode; | |
1318 | ||
1319 | /* Last Rx'd beacon timestamp */ | |
1320 | u64 timestamp; | |
1321 | ||
1322 | union { | |
1323 | #if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE) | |
1324 | struct { | |
1325 | void *shared_virt; | |
1326 | dma_addr_t shared_phys; | |
1327 | ||
1328 | struct delayed_work thermal_periodic; | |
1329 | struct delayed_work rfkill_poll; | |
1330 | ||
1331 | struct il3945_notif_stats stats; | |
1332 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
1333 | struct il3945_notif_stats accum_stats; | |
1334 | struct il3945_notif_stats delta_stats; | |
1335 | struct il3945_notif_stats max_delta; | |
1336 | #endif | |
1337 | ||
1338 | u32 sta_supp_rates; | |
1339 | int last_rx_rssi; /* From Rx packet stats */ | |
1340 | ||
1341 | /* Rx'd packet timing information */ | |
1342 | u32 last_beacon_time; | |
1343 | u64 last_tsf; | |
1344 | ||
1345 | /* | |
1346 | * each calibration channel group in the | |
1347 | * EEPROM has a derived clip setting for | |
1348 | * each rate. | |
1349 | */ | |
1350 | const struct il3945_clip_group clip_groups[5]; | |
1351 | ||
1352 | } _3945; | |
1353 | #endif | |
1354 | #if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE) | |
1355 | struct { | |
1356 | struct il_rx_phy_res last_phy_res; | |
1357 | bool last_phy_res_valid; | |
0255beda | 1358 | u32 ampdu_ref; |
e94a4099 SG |
1359 | |
1360 | struct completion firmware_loading_complete; | |
1361 | ||
1362 | /* | |
1363 | * chain noise reset and gain commands are the | |
1364 | * two extra calibration commands follows the standard | |
1365 | * phy calibration commands | |
1366 | */ | |
1367 | u8 phy_calib_chain_noise_reset_cmd; | |
1368 | u8 phy_calib_chain_noise_gain_cmd; | |
1369 | ||
d735f921 SG |
1370 | u8 key_mapping_keys; |
1371 | struct il_wep_key wep_keys[WEP_KEYS_MAX]; | |
1372 | ||
e94a4099 SG |
1373 | struct il_notif_stats stats; |
1374 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
1375 | struct il_notif_stats accum_stats; | |
1376 | struct il_notif_stats delta_stats; | |
1377 | struct il_notif_stats max_delta; | |
1378 | #endif | |
1379 | ||
1380 | } _4965; | |
1381 | #endif | |
1382 | }; | |
1383 | ||
1384 | struct il_hw_params hw_params; | |
1385 | ||
1386 | u32 inta_mask; | |
1387 | ||
1388 | struct workqueue_struct *workqueue; | |
1389 | ||
1390 | struct work_struct restart; | |
1391 | struct work_struct scan_completed; | |
1392 | struct work_struct rx_replenish; | |
1393 | struct work_struct abort_scan; | |
1394 | ||
83007196 | 1395 | bool beacon_enabled; |
e94a4099 SG |
1396 | struct sk_buff *beacon_skb; |
1397 | ||
1398 | struct work_struct tx_flush; | |
1399 | ||
1400 | struct tasklet_struct irq_tasklet; | |
1401 | ||
1402 | struct delayed_work init_alive_start; | |
1403 | struct delayed_work alive_start; | |
1404 | struct delayed_work scan_check; | |
1405 | ||
1406 | /* TX Power */ | |
1407 | s8 tx_power_user_lmt; | |
1408 | s8 tx_power_device_lmt; | |
1409 | s8 tx_power_next; | |
1410 | ||
e94a4099 SG |
1411 | #ifdef CONFIG_IWLEGACY_DEBUG |
1412 | /* debugging info */ | |
e7392364 SG |
1413 | u32 debug_level; /* per device debugging will override global |
1414 | il_debug_level if set */ | |
1415 | #endif /* CONFIG_IWLEGACY_DEBUG */ | |
e94a4099 SG |
1416 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
1417 | /* debugfs */ | |
1418 | u16 tx_traffic_idx; | |
1419 | u16 rx_traffic_idx; | |
1420 | u8 *tx_traffic; | |
1421 | u8 *rx_traffic; | |
1422 | struct dentry *debugfs_dir; | |
1423 | u32 dbgfs_sram_offset, dbgfs_sram_len; | |
1424 | bool disable_ht40; | |
e7392364 | 1425 | #endif /* CONFIG_IWLEGACY_DEBUGFS */ |
e94a4099 SG |
1426 | |
1427 | struct work_struct txpower_work; | |
1428 | u32 disable_sens_cal; | |
1429 | u32 disable_chain_noise_cal; | |
1430 | u32 disable_tx_power_cal; | |
1431 | struct work_struct run_time_calib_work; | |
1432 | struct timer_list stats_periodic; | |
1433 | struct timer_list watchdog; | |
1434 | bool hw_ready; | |
1435 | ||
1436 | struct led_classdev led; | |
1437 | unsigned long blink_on, blink_off; | |
1438 | bool led_registered; | |
e7392364 | 1439 | }; /*il_priv */ |
e94a4099 | 1440 | |
e7392364 SG |
1441 | static inline void |
1442 | il_txq_ctx_activate(struct il_priv *il, int txq_id) | |
e94a4099 SG |
1443 | { |
1444 | set_bit(txq_id, &il->txq_ctx_active_msk); | |
1445 | } | |
1446 | ||
e7392364 SG |
1447 | static inline void |
1448 | il_txq_ctx_deactivate(struct il_priv *il, int txq_id) | |
e94a4099 SG |
1449 | { |
1450 | clear_bit(txq_id, &il->txq_ctx_active_msk); | |
1451 | } | |
1452 | ||
e7392364 SG |
1453 | static inline int |
1454 | il_is_associated(struct il_priv *il) | |
e94a4099 | 1455 | { |
c8b03958 | 1456 | return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; |
e94a4099 SG |
1457 | } |
1458 | ||
e7392364 SG |
1459 | static inline int |
1460 | il_is_any_associated(struct il_priv *il) | |
e94a4099 SG |
1461 | { |
1462 | return il_is_associated(il); | |
1463 | } | |
1464 | ||
e7392364 SG |
1465 | static inline int |
1466 | il_is_channel_valid(const struct il_channel_info *ch_info) | |
e94a4099 SG |
1467 | { |
1468 | if (ch_info == NULL) | |
1469 | return 0; | |
1470 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1471 | } | |
1472 | ||
e7392364 SG |
1473 | static inline int |
1474 | il_is_channel_radar(const struct il_channel_info *ch_info) | |
e94a4099 SG |
1475 | { |
1476 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1477 | } | |
1478 | ||
e7392364 SG |
1479 | static inline u8 |
1480 | il_is_channel_a_band(const struct il_channel_info *ch_info) | |
e94a4099 SG |
1481 | { |
1482 | return ch_info->band == IEEE80211_BAND_5GHZ; | |
1483 | } | |
1484 | ||
1485 | static inline int | |
1486 | il_is_channel_passive(const struct il_channel_info *ch) | |
1487 | { | |
1488 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1489 | } | |
1490 | ||
1491 | static inline int | |
1492 | il_is_channel_ibss(const struct il_channel_info *ch) | |
1493 | { | |
1494 | return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0; | |
1495 | } | |
be663ab6 | 1496 | |
e94a4099 SG |
1497 | static inline void |
1498 | __il_free_pages(struct il_priv *il, struct page *page) | |
1499 | { | |
1500 | __free_pages(page, il->hw_params.rx_page_order); | |
1501 | il->alloc_rxb_page--; | |
1502 | } | |
1503 | ||
e7392364 SG |
1504 | static inline void |
1505 | il_free_pages(struct il_priv *il, unsigned long page) | |
e94a4099 SG |
1506 | { |
1507 | free_pages(page, il->hw_params.rx_page_order); | |
1508 | il->alloc_rxb_page--; | |
1509 | } | |
be663ab6 WYG |
1510 | |
1511 | #define IWLWIFI_VERSION "in-tree:" | |
1512 | #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation" | |
1513 | #define DRV_AUTHOR "<ilw@linux.intel.com>" | |
1514 | ||
e2ebc833 | 1515 | #define IL_PCI_DEVICE(dev, subdev, cfg) \ |
be663ab6 WYG |
1516 | .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ |
1517 | .subvendor = PCI_ANY_ID, .subdevice = (subdev), \ | |
1518 | .driver_data = (kernel_ulong_t)&(cfg) | |
1519 | ||
1520 | #define TIME_UNIT 1024 | |
1521 | ||
e2ebc833 SG |
1522 | #define IL_SKU_G 0x1 |
1523 | #define IL_SKU_A 0x2 | |
1524 | #define IL_SKU_N 0x8 | |
be663ab6 | 1525 | |
e2ebc833 | 1526 | #define IL_CMD(x) case x: return #x |
be663ab6 | 1527 | |
e94a4099 | 1528 | /* Size of one Rx buffer in host DRAM */ |
e7392364 | 1529 | #define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */ |
e94a4099 SG |
1530 | #define IL_RX_BUF_SIZE_4K (4 * 1024) |
1531 | #define IL_RX_BUF_SIZE_8K (8 * 1024) | |
1532 | ||
9b5e2f46 | 1533 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
e2ebc833 | 1534 | struct il_debugfs_ops { |
1722f8e1 SG |
1535 | ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf, |
1536 | size_t count, loff_t *ppos); | |
1537 | ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf, | |
1538 | size_t count, loff_t *ppos); | |
1539 | ssize_t(*general_stats_read) (struct file *file, | |
1540 | char __user *user_buf, size_t count, | |
1541 | loff_t *ppos); | |
be663ab6 | 1542 | }; |
9b5e2f46 | 1543 | #endif |
be663ab6 | 1544 | |
1600b875 | 1545 | struct il_ops { |
be663ab6 | 1546 | /* Handling TX */ |
1722f8e1 SG |
1547 | void (*txq_update_byte_cnt_tbl) (struct il_priv *il, |
1548 | struct il_tx_queue *txq, | |
e7392364 | 1549 | u16 byte_cnt); |
1722f8e1 SG |
1550 | int (*txq_attach_buf_to_tfd) (struct il_priv *il, |
1551 | struct il_tx_queue *txq, dma_addr_t addr, | |
e7392364 | 1552 | u16 len, u8 reset, u8 pad); |
1722f8e1 SG |
1553 | void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq); |
1554 | int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq); | |
be663ab6 | 1555 | /* alive notification after init uCode load */ |
1722f8e1 | 1556 | void (*init_alive_start) (struct il_priv *il); |
be663ab6 | 1557 | /* check validity of rtc data address */ |
e7392364 | 1558 | int (*is_valid_rtc_data_addr) (u32 addr); |
be663ab6 | 1559 | /* 1st ucode load */ |
1722f8e1 | 1560 | int (*load_ucode) (struct il_priv *il); |
1ba2f121 | 1561 | |
1722f8e1 SG |
1562 | void (*dump_nic_error_log) (struct il_priv *il); |
1563 | int (*dump_fh) (struct il_priv *il, char **buf, bool display); | |
1564 | int (*set_channel_switch) (struct il_priv *il, | |
1565 | struct ieee80211_channel_switch *ch_switch); | |
be663ab6 | 1566 | /* power management */ |
f03ee2a8 | 1567 | int (*apm_init) (struct il_priv *il); |
be663ab6 | 1568 | |
f03ee2a8 | 1569 | /* tx power */ |
1722f8e1 SG |
1570 | int (*send_tx_power) (struct il_priv *il); |
1571 | void (*update_chain_flags) (struct il_priv *il); | |
be663ab6 | 1572 | |
47ef694d | 1573 | /* eeprom operations */ |
a89268e8 SG |
1574 | int (*eeprom_acquire_semaphore) (struct il_priv *il); |
1575 | void (*eeprom_release_semaphore) (struct il_priv *il); | |
be663ab6 | 1576 | |
c9363551 SG |
1577 | int (*rxon_assoc) (struct il_priv *il); |
1578 | int (*commit_rxon) (struct il_priv *il); | |
1579 | void (*set_rxon_chain) (struct il_priv *il); | |
1580 | ||
1581 | u16(*get_hcmd_size) (u8 cmd_id, u16 len); | |
1582 | u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data); | |
1583 | ||
1584 | int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif); | |
1585 | void (*post_scan) (struct il_priv *il); | |
1586 | void (*post_associate) (struct il_priv *il); | |
1587 | void (*config_ap) (struct il_priv *il); | |
1588 | /* station management */ | |
1589 | int (*update_bcast_stations) (struct il_priv *il); | |
1590 | int (*manage_ibss_station) (struct il_priv *il, | |
1591 | struct ieee80211_vif *vif, bool add); | |
1592 | ||
1593 | int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd); | |
be663ab6 WYG |
1594 | }; |
1595 | ||
e2ebc833 | 1596 | struct il_mod_params { |
be663ab6 WYG |
1597 | int sw_crypto; /* def: 0 = using hardware encryption */ |
1598 | int disable_hw_scan; /* def: 0 = use h/w scan */ | |
1599 | int num_of_queues; /* def: HW dependent */ | |
1600 | int disable_11n; /* def: 0 = 11n capabilities enabled */ | |
997bc71a | 1601 | int amsdu_size_8K; /* def: 0 = disable 8K amsdu size */ |
e7392364 | 1602 | int antenna; /* def: 0 = both antennas (use diversity) */ |
be663ab6 WYG |
1603 | int restart_fw; /* def: 1 = restart firmware */ |
1604 | }; | |
1605 | ||
47ef694d SG |
1606 | #define IL_LED_SOLID 11 |
1607 | #define IL_DEF_LED_INTRVL cpu_to_le32(1000) | |
1608 | ||
1609 | #define IL_LED_ACTIVITY (0<<1) | |
1610 | #define IL_LED_LINK (1<<1) | |
1611 | ||
1612 | /* | |
1613 | * LED mode | |
1614 | * IL_LED_DEFAULT: use device default | |
1615 | * IL_LED_RF_STATE: turn LED on/off based on RF state | |
1616 | * LED ON = RF ON | |
1617 | * LED OFF = RF OFF | |
1618 | * IL_LED_BLINK: adjust led blink rate based on blink table | |
1619 | */ | |
1620 | enum il_led_mode { | |
1621 | IL_LED_DEFAULT, | |
1622 | IL_LED_RF_STATE, | |
1623 | IL_LED_BLINK, | |
1624 | }; | |
1625 | ||
1626 | void il_leds_init(struct il_priv *il); | |
1627 | void il_leds_exit(struct il_priv *il); | |
1628 | ||
be663ab6 | 1629 | /** |
e2ebc833 | 1630 | * struct il_cfg |
be663ab6 WYG |
1631 | * @fw_name_pre: Firmware filename prefix. The api version and extension |
1632 | * (.ucode) will be added to filename before loading from disk. The | |
1633 | * filename is constructed as fw_name_pre<api>.ucode. | |
1634 | * @ucode_api_max: Highest version of uCode API supported by driver. | |
1635 | * @ucode_api_min: Lowest version of uCode API supported by driver. | |
1636 | * @scan_antennas: available antenna for scan operation | |
1637 | * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off) | |
1638 | * | |
1639 | * We enable the driver to be backward compatible wrt API version. The | |
1640 | * driver specifies which APIs it supports (with @ucode_api_max being the | |
1641 | * highest and @ucode_api_min the lowest). Firmware will only be loaded if | |
1642 | * it has a supported API version. The firmware's API version will be | |
e2ebc833 | 1643 | * stored in @il_priv, enabling the driver to make runtime changes based |
be663ab6 WYG |
1644 | * on firmware version used. |
1645 | * | |
1646 | * For example, | |
46bc8d4b | 1647 | * if (IL_UCODE_API(il->ucode_ver) >= 2) { |
be663ab6 WYG |
1648 | * Driver interacts with Firmware API version >= 2. |
1649 | * } else { | |
1650 | * Driver interacts with Firmware API version 1. | |
1651 | * } | |
1652 | * | |
1653 | * The ideal usage of this infrastructure is to treat a new ucode API | |
1654 | * release as a new hardware revision. That is, through utilizing the | |
e2ebc833 | 1655 | * il_hcmd_utils_ops etc. we accommodate different command structures |
be663ab6 WYG |
1656 | * and flows between hardware versions as well as their API |
1657 | * versions. | |
1658 | * | |
1659 | */ | |
e2ebc833 | 1660 | struct il_cfg { |
be663ab6 WYG |
1661 | /* params specific to an individual device within a device family */ |
1662 | const char *name; | |
1663 | const char *fw_name_pre; | |
1664 | const unsigned int ucode_api_max; | |
1665 | const unsigned int ucode_api_min; | |
e7392364 SG |
1666 | u8 valid_tx_ant; |
1667 | u8 valid_rx_ant; | |
be663ab6 | 1668 | unsigned int sku; |
e7392364 SG |
1669 | u16 eeprom_ver; |
1670 | u16 eeprom_calib_ver; | |
be663ab6 | 1671 | /* module based parameters which can be set from modprobe cmd */ |
e2ebc833 | 1672 | const struct il_mod_params *mod_params; |
be663ab6 | 1673 | /* params not likely to change within a device family */ |
e2ebc833 | 1674 | struct il_base_params *base_params; |
be663ab6 WYG |
1675 | /* params likely to change within a device family */ |
1676 | u8 scan_rx_antennas[IEEE80211_NUM_BANDS]; | |
e2ebc833 | 1677 | enum il_led_mode led_mode; |
89ef1ed2 SG |
1678 | |
1679 | int eeprom_size; | |
1680 | int num_of_queues; /* def: HW dependent */ | |
1681 | int num_of_ampdu_queues; /* def: HW dependent */ | |
1682 | /* for il_apm_init() */ | |
1683 | u32 pll_cfg_val; | |
1684 | bool set_l0s; | |
1685 | bool use_bsm; | |
1686 | ||
1687 | u16 led_compensation; | |
1688 | int chain_noise_num_beacons; | |
1689 | unsigned int wd_timeout; | |
1690 | bool temperature_kelvin; | |
1691 | const bool ucode_tracing; | |
1692 | const bool sensitivity_calib_by_driver; | |
1693 | const bool chain_noise_calib_by_driver; | |
93a984a4 SG |
1694 | |
1695 | const u32 regulatory_bands[7]; | |
be663ab6 WYG |
1696 | }; |
1697 | ||
1698 | /*************************** | |
1699 | * L i b * | |
1700 | ***************************/ | |
1701 | ||
e7392364 SG |
1702 | int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1703 | u16 queue, const struct ieee80211_tx_queue_params *params); | |
e2ebc833 | 1704 | int il_mac_tx_last_beacon(struct ieee80211_hw *hw); |
e7392364 | 1705 | |
83007196 SG |
1706 | void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt); |
1707 | int il_check_rxon_cmd(struct il_priv *il); | |
1708 | int il_full_rxon_required(struct il_priv *il); | |
1709 | int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch); | |
1710 | void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band, | |
1711 | struct ieee80211_vif *vif); | |
e7392364 SG |
1712 | u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band); |
1713 | void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf); | |
83007196 | 1714 | bool il_is_ht40_tx_allowed(struct il_priv *il, |
e7392364 | 1715 | struct ieee80211_sta_ht_cap *ht_cap); |
83007196 | 1716 | void il_connection_init_rx_config(struct il_priv *il); |
46bc8d4b | 1717 | void il_set_rate(struct il_priv *il); |
e7392364 SG |
1718 | int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr, |
1719 | u32 decrypt_res, struct ieee80211_rx_status *stats); | |
46bc8d4b | 1720 | void il_irq_handle_error(struct il_priv *il); |
e7392364 | 1721 | int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif); |
e2ebc833 | 1722 | void il_mac_remove_interface(struct ieee80211_hw *hw, |
e7392364 SG |
1723 | struct ieee80211_vif *vif); |
1724 | int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
1725 | enum nl80211_iftype newtype, bool newp2p); | |
39ecc01d | 1726 | void il_mac_flush(struct ieee80211_hw *hw, u32 queues, bool drop); |
46bc8d4b | 1727 | int il_alloc_txq_mem(struct il_priv *il); |
6668e4eb | 1728 | void il_free_txq_mem(struct il_priv *il); |
be663ab6 | 1729 | |
d3175167 | 1730 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
6890ba72 | 1731 | void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len); |
be663ab6 | 1732 | #else |
e7392364 SG |
1733 | static inline void |
1734 | il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len) | |
be663ab6 WYG |
1735 | { |
1736 | } | |
1737 | #endif | |
288f9954 | 1738 | |
be663ab6 | 1739 | /***************************************************** |
288f9954 SG |
1740 | * Handlers |
1741 | ***************************************************/ | |
e7392364 SG |
1742 | void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb); |
1743 | void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb); | |
1744 | void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb); | |
288f9954 | 1745 | void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb); |
be663ab6 WYG |
1746 | |
1747 | /***************************************************** | |
1748 | * RX | |
1749 | ******************************************************/ | |
46bc8d4b SG |
1750 | void il_cmd_queue_unmap(struct il_priv *il); |
1751 | void il_cmd_queue_free(struct il_priv *il); | |
1752 | int il_rx_queue_alloc(struct il_priv *il); | |
e7392364 | 1753 | void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q); |
e2ebc833 | 1754 | int il_rx_queue_space(const struct il_rx_queue *q); |
e7392364 | 1755 | void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb); |
288f9954 | 1756 | |
e7392364 SG |
1757 | void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb); |
1758 | void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt); | |
46bc8d4b | 1759 | void il_chswitch_done(struct il_priv *il, bool is_success); |
be663ab6 WYG |
1760 | |
1761 | /***************************************************** | |
1762 | * TX | |
1763 | ******************************************************/ | |
6890ba72 JP |
1764 | void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq); |
1765 | int il_tx_queue_init(struct il_priv *il, u32 txq_id); | |
1766 | void il_tx_queue_reset(struct il_priv *il, u32 txq_id); | |
1767 | void il_tx_queue_unmap(struct il_priv *il, int txq_id); | |
1768 | void il_tx_queue_free(struct il_priv *il, int txq_id); | |
1769 | void il_setup_watchdog(struct il_priv *il); | |
be663ab6 WYG |
1770 | /***************************************************** |
1771 | * TX power | |
1772 | ****************************************************/ | |
46bc8d4b | 1773 | int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force); |
be663ab6 WYG |
1774 | |
1775 | /******************************************************************************* | |
1776 | * Rate | |
1777 | ******************************************************************************/ | |
1778 | ||
83007196 | 1779 | u8 il_get_lowest_plcp(struct il_priv *il); |
be663ab6 WYG |
1780 | |
1781 | /******************************************************************************* | |
1782 | * Scanning | |
1783 | ******************************************************************************/ | |
46bc8d4b SG |
1784 | void il_init_scan_params(struct il_priv *il); |
1785 | int il_scan_cancel(struct il_priv *il); | |
1786 | int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms); | |
1787 | void il_force_scan_end(struct il_priv *il); | |
e7392364 SG |
1788 | int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1789 | struct cfg80211_scan_request *req); | |
46bc8d4b SG |
1790 | void il_internal_short_hw_scan(struct il_priv *il); |
1791 | int il_force_reset(struct il_priv *il, bool external); | |
e7392364 | 1792 | u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame, |
1722f8e1 | 1793 | const u8 *ta, const u8 *ie, int ie_len, int left); |
46bc8d4b | 1794 | void il_setup_rx_scan_handlers(struct il_priv *il); |
e7392364 SG |
1795 | u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band, |
1796 | u8 n_probes); | |
1797 | u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band, | |
1798 | struct ieee80211_vif *vif); | |
46bc8d4b SG |
1799 | void il_setup_scan_deferred_work(struct il_priv *il); |
1800 | void il_cancel_scan_deferred_work(struct il_priv *il); | |
be663ab6 WYG |
1801 | |
1802 | /* For faster active scanning, scan will move to the next channel if fewer than | |
1803 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
1804 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
1805 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
1806 | * no other traffic). | |
1807 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
e7392364 SG |
1808 | #define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */ |
1809 | #define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */ | |
be663ab6 | 1810 | |
e2ebc833 | 1811 | #define IL_SCAN_CHECK_WATCHDOG (HZ * 7) |
be663ab6 WYG |
1812 | |
1813 | /***************************************************** | |
1814 | * S e n d i n g H o s t C o m m a n d s * | |
1815 | *****************************************************/ | |
1816 | ||
e2ebc833 | 1817 | const char *il_get_cmd_string(u8 cmd); |
e7392364 | 1818 | int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd); |
46bc8d4b | 1819 | int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd); |
e7392364 SG |
1820 | int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, |
1821 | const void *data); | |
1822 | int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data, | |
1722f8e1 SG |
1823 | void (*callback) (struct il_priv *il, |
1824 | struct il_device_cmd *cmd, | |
1825 | struct il_rx_pkt *pkt)); | |
be663ab6 | 1826 | |
46bc8d4b | 1827 | int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd); |
be663ab6 | 1828 | |
be663ab6 WYG |
1829 | /***************************************************** |
1830 | * PCI * | |
1831 | *****************************************************/ | |
1832 | ||
e2ebc833 | 1833 | void il_bg_watchdog(unsigned long data); |
e7392364 SG |
1834 | u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval); |
1835 | __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, | |
1836 | u32 beacon_interval); | |
be663ab6 | 1837 | |
71aa5bba | 1838 | #ifdef CONFIG_PM_SLEEP |
e2ebc833 | 1839 | extern const struct dev_pm_ops il_pm_ops; |
be663ab6 | 1840 | |
e2ebc833 | 1841 | #define IL_LEGACY_PM_OPS (&il_pm_ops) |
be663ab6 | 1842 | |
71aa5bba | 1843 | #else /* !CONFIG_PM_SLEEP */ |
be663ab6 | 1844 | |
e2ebc833 | 1845 | #define IL_LEGACY_PM_OPS NULL |
be663ab6 | 1846 | |
71aa5bba | 1847 | #endif /* !CONFIG_PM_SLEEP */ |
be663ab6 WYG |
1848 | |
1849 | /***************************************************** | |
1850 | * Error Handling Debugging | |
1851 | ******************************************************/ | |
46bc8d4b | 1852 | void il4965_dump_nic_error_log(struct il_priv *il); |
d3175167 | 1853 | #ifdef CONFIG_IWLEGACY_DEBUG |
83007196 | 1854 | void il_print_rx_config_cmd(struct il_priv *il); |
be663ab6 | 1855 | #else |
e7392364 | 1856 | static inline void |
83007196 | 1857 | il_print_rx_config_cmd(struct il_priv *il) |
be663ab6 WYG |
1858 | { |
1859 | } | |
1860 | #endif | |
1861 | ||
46bc8d4b | 1862 | void il_clear_isr_stats(struct il_priv *il); |
be663ab6 WYG |
1863 | |
1864 | /***************************************************** | |
1865 | * GEOS | |
1866 | ******************************************************/ | |
46bc8d4b SG |
1867 | int il_init_geos(struct il_priv *il); |
1868 | void il_free_geos(struct il_priv *il); | |
be663ab6 WYG |
1869 | |
1870 | /*************** DRIVER STATUS FUNCTIONS *****/ | |
1871 | ||
a6766ccd SG |
1872 | #define S_HCMD_ACTIVE 0 /* host command in progress */ |
1873 | /* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */ | |
1874 | #define S_INT_ENABLED 2 | |
bc269a8e | 1875 | #define S_RFKILL 3 |
a6766ccd SG |
1876 | #define S_CT_KILL 4 |
1877 | #define S_INIT 5 | |
1878 | #define S_ALIVE 6 | |
1879 | #define S_READY 7 | |
1880 | #define S_TEMPERATURE 8 | |
1881 | #define S_GEO_CONFIGURED 9 | |
1882 | #define S_EXIT_PENDING 10 | |
db7746f7 | 1883 | #define S_STATS 12 |
a6766ccd SG |
1884 | #define S_SCANNING 13 |
1885 | #define S_SCAN_ABORTING 14 | |
1886 | #define S_SCAN_HW 15 | |
1887 | #define S_POWER_PMI 16 | |
1888 | #define S_FW_ERROR 17 | |
1889 | #define S_CHANNEL_SWITCH_PENDING 18 | |
be663ab6 | 1890 | |
e7392364 SG |
1891 | static inline int |
1892 | il_is_ready(struct il_priv *il) | |
be663ab6 WYG |
1893 | { |
1894 | /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are | |
1895 | * set but EXIT_PENDING is not */ | |
a6766ccd | 1896 | return test_bit(S_READY, &il->status) && |
e7392364 SG |
1897 | test_bit(S_GEO_CONFIGURED, &il->status) && |
1898 | !test_bit(S_EXIT_PENDING, &il->status); | |
be663ab6 WYG |
1899 | } |
1900 | ||
e7392364 SG |
1901 | static inline int |
1902 | il_is_alive(struct il_priv *il) | |
be663ab6 | 1903 | { |
a6766ccd | 1904 | return test_bit(S_ALIVE, &il->status); |
be663ab6 WYG |
1905 | } |
1906 | ||
e7392364 SG |
1907 | static inline int |
1908 | il_is_init(struct il_priv *il) | |
be663ab6 | 1909 | { |
a6766ccd | 1910 | return test_bit(S_INIT, &il->status); |
be663ab6 WYG |
1911 | } |
1912 | ||
e7392364 SG |
1913 | static inline int |
1914 | il_is_rfkill(struct il_priv *il) | |
be663ab6 | 1915 | { |
4e3bc141 | 1916 | return test_bit(S_RFKILL, &il->status); |
be663ab6 WYG |
1917 | } |
1918 | ||
e7392364 SG |
1919 | static inline int |
1920 | il_is_ctkill(struct il_priv *il) | |
be663ab6 | 1921 | { |
a6766ccd | 1922 | return test_bit(S_CT_KILL, &il->status); |
be663ab6 WYG |
1923 | } |
1924 | ||
e7392364 SG |
1925 | static inline int |
1926 | il_is_ready_rf(struct il_priv *il) | |
be663ab6 WYG |
1927 | { |
1928 | ||
46bc8d4b | 1929 | if (il_is_rfkill(il)) |
be663ab6 WYG |
1930 | return 0; |
1931 | ||
46bc8d4b | 1932 | return il_is_ready(il); |
be663ab6 WYG |
1933 | } |
1934 | ||
6890ba72 JP |
1935 | void il_send_bt_config(struct il_priv *il); |
1936 | int il_send_stats_request(struct il_priv *il, u8 flags, bool clear); | |
1937 | void il_apm_stop(struct il_priv *il); | |
1938 | void _il_apm_stop(struct il_priv *il); | |
775ed8ab | 1939 | |
46bc8d4b | 1940 | int il_apm_init(struct il_priv *il); |
be663ab6 | 1941 | |
83007196 SG |
1942 | int il_send_rxon_timing(struct il_priv *il); |
1943 | ||
e7392364 | 1944 | static inline int |
83007196 | 1945 | il_send_rxon_assoc(struct il_priv *il) |
be663ab6 | 1946 | { |
c9363551 | 1947 | return il->ops->rxon_assoc(il); |
be663ab6 | 1948 | } |
e7392364 SG |
1949 | |
1950 | static inline int | |
83007196 | 1951 | il_commit_rxon(struct il_priv *il) |
be663ab6 | 1952 | { |
c9363551 | 1953 | return il->ops->commit_rxon(il); |
be663ab6 | 1954 | } |
e7392364 SG |
1955 | |
1956 | static inline const struct ieee80211_supported_band * | |
1957 | il_get_hw_mode(struct il_priv *il, enum ieee80211_band band) | |
be663ab6 | 1958 | { |
46bc8d4b | 1959 | return il->hw->wiphy->bands[band]; |
be663ab6 WYG |
1960 | } |
1961 | ||
be663ab6 | 1962 | /* mac80211 handlers */ |
e2ebc833 | 1963 | int il_mac_config(struct ieee80211_hw *hw, u32 changed); |
e7392364 SG |
1964 | void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif); |
1965 | void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
1966 | struct ieee80211_bss_conf *bss_conf, u32 changes); | |
1967 | void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info, | |
1722f8e1 | 1968 | __le16 fc, __le32 *tx_flags); |
be663ab6 | 1969 | |
e2ebc833 | 1970 | irqreturn_t il_isr(int irq, void *data); |
be663ab6 | 1971 | |
6890ba72 JP |
1972 | void il_set_bit(struct il_priv *p, u32 r, u32 m); |
1973 | void il_clear_bit(struct il_priv *p, u32 r, u32 m); | |
1974 | bool _il_grab_nic_access(struct il_priv *il); | |
1975 | int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout); | |
1976 | int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout); | |
1977 | u32 il_rd_prph(struct il_priv *il, u32 reg); | |
1978 | void il_wr_prph(struct il_priv *il, u32 addr, u32 val); | |
1979 | u32 il_read_targ_mem(struct il_priv *il, u32 addr); | |
1980 | void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val); | |
e94a4099 | 1981 | |
8e67427a SG |
1982 | static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt) |
1983 | { | |
1984 | /* Reclaim a command buffer only if this packet is a response | |
1985 | * to a (driver-originated) command. If the packet (e.g. Rx frame) | |
1986 | * originated from uCode, there is no command buffer to reclaim. | |
1987 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, but | |
1988 | * apparently a few don't get set; catch them here. | |
1989 | */ | |
1990 | return !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1991 | pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX && | |
1992 | pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX && | |
1993 | pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA; | |
1994 | } | |
1995 | ||
e7392364 SG |
1996 | static inline void |
1997 | _il_write8(struct il_priv *il, u32 ofs, u8 val) | |
e94a4099 | 1998 | { |
a5f16137 | 1999 | writeb(val, il->hw_base + ofs); |
e94a4099 SG |
2000 | } |
2001 | #define il_write8(il, ofs, val) _il_write8(il, ofs, val) | |
2002 | ||
e7392364 SG |
2003 | static inline void |
2004 | _il_wr(struct il_priv *il, u32 ofs, u32 val) | |
e94a4099 | 2005 | { |
a5f16137 | 2006 | writel(val, il->hw_base + ofs); |
e94a4099 SG |
2007 | } |
2008 | ||
e7392364 SG |
2009 | static inline u32 |
2010 | _il_rd(struct il_priv *il, u32 ofs) | |
e94a4099 | 2011 | { |
a5f16137 | 2012 | return readl(il->hw_base + ofs); |
e94a4099 SG |
2013 | } |
2014 | ||
e94a4099 SG |
2015 | static inline void |
2016 | _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) | |
2017 | { | |
2018 | _il_wr(il, reg, _il_rd(il, reg) & ~mask); | |
2019 | } | |
2020 | ||
e7392364 | 2021 | static inline void |
17d4eca6 | 2022 | _il_set_bit(struct il_priv *il, u32 reg, u32 mask) |
e94a4099 | 2023 | { |
17d4eca6 | 2024 | _il_wr(il, reg, _il_rd(il, reg) | mask); |
e94a4099 SG |
2025 | } |
2026 | ||
e7392364 SG |
2027 | static inline void |
2028 | _il_release_nic_access(struct il_priv *il) | |
e94a4099 | 2029 | { |
e7392364 | 2030 | _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
4e5ea208 SG |
2031 | /* |
2032 | * In above we are reading CSR_GP_CNTRL register, what will flush any | |
2033 | * previous writes, but still want write, which clear MAC_ACCESS_REQ | |
2034 | * bit, be performed on PCI bus before any other writes scheduled on | |
2035 | * different CPUs (after we drop reg_lock). | |
2036 | */ | |
2037 | mmiowb(); | |
e94a4099 SG |
2038 | } |
2039 | ||
e7392364 SG |
2040 | static inline u32 |
2041 | il_rd(struct il_priv *il, u32 reg) | |
e94a4099 SG |
2042 | { |
2043 | u32 value; | |
2044 | unsigned long reg_flags; | |
2045 | ||
2046 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
2047 | _il_grab_nic_access(il); | |
2048 | value = _il_rd(il, reg); | |
2049 | _il_release_nic_access(il); | |
2050 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
2051 | return value; | |
e94a4099 SG |
2052 | } |
2053 | ||
2054 | static inline void | |
2055 | il_wr(struct il_priv *il, u32 reg, u32 value) | |
2056 | { | |
2057 | unsigned long reg_flags; | |
2058 | ||
2059 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 | 2060 | if (likely(_il_grab_nic_access(il))) { |
e94a4099 SG |
2061 | _il_wr(il, reg, value); |
2062 | _il_release_nic_access(il); | |
2063 | } | |
2064 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | |
2065 | } | |
2066 | ||
e7392364 SG |
2067 | static inline u32 |
2068 | _il_rd_prph(struct il_priv *il, u32 reg) | |
e94a4099 SG |
2069 | { |
2070 | _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); | |
e94a4099 SG |
2071 | return _il_rd(il, HBUS_TARG_PRPH_RDAT); |
2072 | } | |
2073 | ||
e7392364 SG |
2074 | static inline void |
2075 | _il_wr_prph(struct il_priv *il, u32 addr, u32 val) | |
e94a4099 | 2076 | { |
e7392364 | 2077 | _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24))); |
e94a4099 SG |
2078 | _il_wr(il, HBUS_TARG_PRPH_WDAT, val); |
2079 | } | |
2080 | ||
e94a4099 SG |
2081 | static inline void |
2082 | il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask) | |
2083 | { | |
2084 | unsigned long reg_flags; | |
2085 | ||
2086 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 SG |
2087 | if (likely(_il_grab_nic_access(il))) { |
2088 | _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask)); | |
2089 | _il_release_nic_access(il); | |
2090 | } | |
e94a4099 SG |
2091 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2092 | } | |
2093 | ||
e7392364 SG |
2094 | static inline void |
2095 | il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) | |
e94a4099 SG |
2096 | { |
2097 | unsigned long reg_flags; | |
2098 | ||
2099 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 SG |
2100 | if (likely(_il_grab_nic_access(il))) { |
2101 | _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits)); | |
2102 | _il_release_nic_access(il); | |
2103 | } | |
e94a4099 SG |
2104 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2105 | } | |
2106 | ||
e7392364 SG |
2107 | static inline void |
2108 | il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask) | |
e94a4099 SG |
2109 | { |
2110 | unsigned long reg_flags; | |
2111 | u32 val; | |
2112 | ||
2113 | spin_lock_irqsave(&il->reg_lock, reg_flags); | |
1e0f32a4 SG |
2114 | if (likely(_il_grab_nic_access(il))) { |
2115 | val = _il_rd_prph(il, reg); | |
2116 | _il_wr_prph(il, reg, (val & ~mask)); | |
2117 | _il_release_nic_access(il); | |
2118 | } | |
e94a4099 SG |
2119 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2120 | } | |
2121 | ||
e94a4099 SG |
2122 | #define HW_KEY_DYNAMIC 0 |
2123 | #define HW_KEY_DEFAULT 1 | |
2124 | ||
e7392364 SG |
2125 | #define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */ |
2126 | #define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */ | |
2127 | #define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of | |
2128 | being activated */ | |
2129 | #define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211; | |
2130 | (this is for the IBSS BSSID stations) */ | |
2131 | #define IL_STA_BCAST BIT(4) /* this station is the special bcast station */ | |
e94a4099 | 2132 | |
83007196 SG |
2133 | void il_restore_stations(struct il_priv *il); |
2134 | void il_clear_ucode_stations(struct il_priv *il); | |
e94a4099 SG |
2135 | void il_dealloc_bcast_stations(struct il_priv *il); |
2136 | int il_get_free_ucode_key_idx(struct il_priv *il); | |
e7392364 | 2137 | int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags); |
83007196 | 2138 | int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap, |
1722f8e1 | 2139 | struct ieee80211_sta *sta, u8 *sta_id_r); |
e7392364 SG |
2140 | int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr); |
2141 | int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
2142 | struct ieee80211_sta *sta); | |
2143 | ||
83007196 SG |
2144 | u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap, |
2145 | struct ieee80211_sta *sta); | |
e7392364 | 2146 | |
83007196 SG |
2147 | int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq, |
2148 | u8 flags, bool init); | |
e94a4099 SG |
2149 | |
2150 | /** | |
2151 | * il_clear_driver_stations - clear knowledge of all stations from driver | |
2152 | * @il: iwl il struct | |
2153 | * | |
2154 | * This is called during il_down() to make sure that in the case | |
2155 | * we're coming there from a hardware restart mac80211 will be | |
2156 | * able to reconfigure stations -- if we're getting there in the | |
2157 | * normal down flow then the stations will already be cleared. | |
2158 | */ | |
e7392364 SG |
2159 | static inline void |
2160 | il_clear_driver_stations(struct il_priv *il) | |
e94a4099 SG |
2161 | { |
2162 | unsigned long flags; | |
e94a4099 SG |
2163 | |
2164 | spin_lock_irqsave(&il->sta_lock, flags); | |
2165 | memset(il->stations, 0, sizeof(il->stations)); | |
2166 | il->num_stations = 0; | |
e94a4099 | 2167 | il->ucode_key_table = 0; |
e94a4099 SG |
2168 | spin_unlock_irqrestore(&il->sta_lock, flags); |
2169 | } | |
2170 | ||
e7392364 SG |
2171 | static inline int |
2172 | il_sta_id(struct ieee80211_sta *sta) | |
e94a4099 SG |
2173 | { |
2174 | if (WARN_ON(!sta)) | |
2175 | return IL_INVALID_STATION; | |
2176 | ||
2177 | return ((struct il_station_priv_common *)sta->drv_priv)->sta_id; | |
2178 | } | |
2179 | ||
2180 | /** | |
2181 | * il_sta_id_or_broadcast - return sta_id or broadcast sta | |
2182 | * @il: iwl il | |
2183 | * @context: the current context | |
2184 | * @sta: mac80211 station | |
2185 | * | |
2186 | * In certain circumstances mac80211 passes a station pointer | |
2187 | * that may be %NULL, for example during TX or key setup. In | |
2188 | * that case, we need to use the broadcast station, so this | |
2189 | * inline wraps that pattern. | |
2190 | */ | |
e7392364 | 2191 | static inline int |
83007196 | 2192 | il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta) |
e94a4099 SG |
2193 | { |
2194 | int sta_id; | |
2195 | ||
2196 | if (!sta) | |
b16db50a | 2197 | return il->hw_params.bcast_id; |
e94a4099 SG |
2198 | |
2199 | sta_id = il_sta_id(sta); | |
2200 | ||
2201 | /* | |
2202 | * mac80211 should not be passing a partially | |
2203 | * initialised station! | |
2204 | */ | |
2205 | WARN_ON(sta_id == IL_INVALID_STATION); | |
2206 | ||
2207 | return sta_id; | |
2208 | } | |
2209 | ||
2210 | /** | |
2211 | * il_queue_inc_wrap - increment queue idx, wrap back to beginning | |
2212 | * @idx -- current idx | |
2213 | * @n_bd -- total number of entries in queue (must be power of 2) | |
2214 | */ | |
e7392364 SG |
2215 | static inline int |
2216 | il_queue_inc_wrap(int idx, int n_bd) | |
e94a4099 SG |
2217 | { |
2218 | return ++idx & (n_bd - 1); | |
2219 | } | |
2220 | ||
2221 | /** | |
2222 | * il_queue_dec_wrap - decrement queue idx, wrap back to end | |
2223 | * @idx -- current idx | |
2224 | * @n_bd -- total number of entries in queue (must be power of 2) | |
2225 | */ | |
e7392364 SG |
2226 | static inline int |
2227 | il_queue_dec_wrap(int idx, int n_bd) | |
e94a4099 SG |
2228 | { |
2229 | return --idx & (n_bd - 1); | |
2230 | } | |
2231 | ||
2232 | /* TODO: Move fw_desc functions to iwl-pci.ko */ | |
e7392364 SG |
2233 | static inline void |
2234 | il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) | |
e94a4099 SG |
2235 | { |
2236 | if (desc->v_addr) | |
e7392364 SG |
2237 | dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr, |
2238 | desc->p_addr); | |
e94a4099 SG |
2239 | desc->v_addr = NULL; |
2240 | desc->len = 0; | |
2241 | } | |
2242 | ||
e7392364 SG |
2243 | static inline int |
2244 | il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) | |
e94a4099 SG |
2245 | { |
2246 | if (!desc->len) { | |
2247 | desc->v_addr = NULL; | |
2248 | return -EINVAL; | |
2249 | } | |
2250 | ||
1f9061d2 JP |
2251 | desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len, |
2252 | &desc->p_addr, GFP_KERNEL); | |
e94a4099 SG |
2253 | return (desc->v_addr != NULL) ? 0 : -ENOMEM; |
2254 | } | |
2255 | ||
2256 | /* | |
2257 | * we have 8 bits used like this: | |
2258 | * | |
2259 | * 7 6 5 4 3 2 1 0 | |
2260 | * | | | | | | | | | |
2261 | * | | | | | | +-+-------- AC queue (0-3) | |
2262 | * | | | | | | | |
2263 | * | +-+-+-+-+------------ HW queue ID | |
2264 | * | | |
2265 | * +---------------------- unused | |
2266 | */ | |
2267 | static inline void | |
2268 | il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq) | |
2269 | { | |
e7392364 SG |
2270 | BUG_ON(ac > 3); /* only have 2 bits */ |
2271 | BUG_ON(hwq > 31); /* only use 5 bits */ | |
e94a4099 SG |
2272 | |
2273 | txq->swq_id = (hwq << 2) | ac; | |
2274 | } | |
2275 | ||
42ce8943 SG |
2276 | static inline void |
2277 | _il_wake_queue(struct il_priv *il, u8 ac) | |
2278 | { | |
2279 | if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0) | |
2280 | ieee80211_wake_queue(il->hw, ac); | |
2281 | } | |
2282 | ||
2283 | static inline void | |
2284 | _il_stop_queue(struct il_priv *il, u8 ac) | |
2285 | { | |
2286 | if (atomic_inc_return(&il->queue_stop_count[ac]) > 0) | |
2287 | ieee80211_stop_queue(il->hw, ac); | |
2288 | } | |
e7392364 SG |
2289 | static inline void |
2290 | il_wake_queue(struct il_priv *il, struct il_tx_queue *txq) | |
e94a4099 SG |
2291 | { |
2292 | u8 queue = txq->swq_id; | |
2293 | u8 ac = queue & 3; | |
2294 | u8 hwq = (queue >> 2) & 0x1f; | |
2295 | ||
2296 | if (test_and_clear_bit(hwq, il->queue_stopped)) | |
42ce8943 | 2297 | _il_wake_queue(il, ac); |
e94a4099 SG |
2298 | } |
2299 | ||
e7392364 SG |
2300 | static inline void |
2301 | il_stop_queue(struct il_priv *il, struct il_tx_queue *txq) | |
e94a4099 SG |
2302 | { |
2303 | u8 queue = txq->swq_id; | |
2304 | u8 ac = queue & 3; | |
2305 | u8 hwq = (queue >> 2) & 0x1f; | |
2306 | ||
2307 | if (!test_and_set_bit(hwq, il->queue_stopped)) | |
42ce8943 | 2308 | _il_stop_queue(il, ac); |
e94a4099 SG |
2309 | } |
2310 | ||
c6af8074 SG |
2311 | static inline void |
2312 | il_wake_queues_by_reason(struct il_priv *il, int reason) | |
2313 | { | |
2314 | u8 ac; | |
2315 | ||
2316 | if (test_and_clear_bit(reason, &il->stop_reason)) | |
2317 | for (ac = 0; ac < 4; ac++) | |
2318 | _il_wake_queue(il, ac); | |
2319 | } | |
2320 | ||
2321 | static inline void | |
2322 | il_stop_queues_by_reason(struct il_priv *il, int reason) | |
2323 | { | |
2324 | u8 ac; | |
2325 | ||
2326 | if (!test_and_set_bit(reason, &il->stop_reason)) | |
2327 | for (ac = 0; ac < 4; ac++) | |
2328 | _il_stop_queue(il, ac); | |
2329 | } | |
2330 | ||
e94a4099 SG |
2331 | #ifdef ieee80211_stop_queue |
2332 | #undef ieee80211_stop_queue | |
2333 | #endif | |
2334 | ||
2335 | #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue | |
2336 | ||
2337 | #ifdef ieee80211_wake_queue | |
2338 | #undef ieee80211_wake_queue | |
2339 | #endif | |
2340 | ||
2341 | #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue | |
2342 | ||
e7392364 SG |
2343 | static inline void |
2344 | il_disable_interrupts(struct il_priv *il) | |
e94a4099 SG |
2345 | { |
2346 | clear_bit(S_INT_ENABLED, &il->status); | |
2347 | ||
2348 | /* disable interrupts from uCode/NIC to host */ | |
2349 | _il_wr(il, CSR_INT_MASK, 0x00000000); | |
2350 | ||
2351 | /* acknowledge/clear/reset any interrupts still pending | |
2352 | * from uCode or flow handler (Rx/Tx DMA) */ | |
2353 | _il_wr(il, CSR_INT, 0xffffffff); | |
2354 | _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff); | |
e94a4099 SG |
2355 | } |
2356 | ||
e7392364 SG |
2357 | static inline void |
2358 | il_enable_rfkill_int(struct il_priv *il) | |
e94a4099 | 2359 | { |
e94a4099 SG |
2360 | _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); |
2361 | } | |
2362 | ||
e7392364 SG |
2363 | static inline void |
2364 | il_enable_interrupts(struct il_priv *il) | |
e94a4099 | 2365 | { |
e94a4099 SG |
2366 | set_bit(S_INT_ENABLED, &il->status); |
2367 | _il_wr(il, CSR_INT_MASK, il->inta_mask); | |
2368 | } | |
2369 | ||
2370 | /** | |
2371 | * il_beacon_time_mask_low - mask of lower 32 bit of beacon time | |
2372 | * @il -- pointer to il_priv data structure | |
2373 | * @tsf_bits -- number of bits need to shift for masking) | |
2374 | */ | |
e7392364 SG |
2375 | static inline u32 |
2376 | il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits) | |
e94a4099 SG |
2377 | { |
2378 | return (1 << tsf_bits) - 1; | |
2379 | } | |
2380 | ||
2381 | /** | |
2382 | * il_beacon_time_mask_high - mask of higher 32 bit of beacon time | |
2383 | * @il -- pointer to il_priv data structure | |
2384 | * @tsf_bits -- number of bits need to shift for masking) | |
2385 | */ | |
e7392364 SG |
2386 | static inline u32 |
2387 | il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits) | |
e94a4099 SG |
2388 | { |
2389 | return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; | |
2390 | } | |
2391 | ||
2392 | /** | |
2393 | * struct il_rb_status - reseve buffer status host memory mapped FH registers | |
2394 | * | |
2395 | * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed | |
2396 | * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed | |
2397 | * @finished_rb_num [0:11] - Indicates the idx of the current RB | |
2398 | * in which the last frame was written to | |
2399 | * @finished_fr_num [0:11] - Indicates the idx of the RX Frame | |
2400 | * which was transferred | |
2401 | */ | |
2402 | struct il_rb_status { | |
2403 | __le16 closed_rb_num; | |
2404 | __le16 closed_fr_num; | |
2405 | __le16 finished_rb_num; | |
2406 | __le16 finished_fr_nam; | |
e7392364 | 2407 | __le32 __unused; /* 3945 only */ |
e94a4099 SG |
2408 | } __packed; |
2409 | ||
d87c771f SG |
2410 | #define TFD_QUEUE_SIZE_MAX 256 |
2411 | #define TFD_QUEUE_SIZE_BC_DUP 64 | |
e94a4099 | 2412 | #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) |
d87c771f | 2413 | #define IL_TX_DMA_MASK DMA_BIT_MASK(36) |
e94a4099 SG |
2414 | #define IL_NUM_OF_TBS 20 |
2415 | ||
e7392364 SG |
2416 | static inline u8 |
2417 | il_get_dma_hi_addr(dma_addr_t addr) | |
e94a4099 SG |
2418 | { |
2419 | return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; | |
2420 | } | |
e7392364 | 2421 | |
e94a4099 SG |
2422 | /** |
2423 | * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor | |
2424 | * | |
2425 | * This structure contains dma address and length of transmission address | |
2426 | * | |
1722f8e1 SG |
2427 | * @lo: low [31:0] portion of the dma address of TX buffer every even is |
2428 | * unaligned on 16 bit boundary | |
2429 | * @hi_n_len: 0-3 [35:32] portion of dma | |
2430 | * 4-15 length of the tx buffer | |
e94a4099 SG |
2431 | */ |
2432 | struct il_tfd_tb { | |
2433 | __le32 lo; | |
2434 | __le16 hi_n_len; | |
2435 | } __packed; | |
2436 | ||
2437 | /** | |
2438 | * struct il_tfd | |
2439 | * | |
2440 | * Transmit Frame Descriptor (TFD) | |
2441 | * | |
2442 | * @ __reserved1[3] reserved | |
2443 | * @ num_tbs 0-4 number of active tbs | |
2444 | * 5 reserved | |
2445 | * 6-7 padding (not used) | |
2446 | * @ tbs[20] transmit frame buffer descriptors | |
1722f8e1 | 2447 | * @ __pad padding |
e94a4099 SG |
2448 | * |
2449 | * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. | |
2450 | * Both driver and device share these circular buffers, each of which must be | |
2451 | * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes | |
2452 | * | |
2453 | * Driver must indicate the physical address of the base of each | |
9a95b370 | 2454 | * circular buffer via the FH49_MEM_CBBC_QUEUE registers. |
e94a4099 SG |
2455 | * |
2456 | * Each TFD contains pointer/size information for up to 20 data buffers | |
2457 | * in host DRAM. These buffers collectively contain the (one) frame described | |
2458 | * by the TFD. Each buffer must be a single contiguous block of memory within | |
2459 | * itself, but buffers may be scattered in host DRAM. Each buffer has max size | |
2460 | * of (4K - 4). The concatenates all of a TFD's buffers into a single | |
2461 | * Tx frame, up to 8 KBytes in size. | |
2462 | * | |
2463 | * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. | |
2464 | */ | |
2465 | struct il_tfd { | |
2466 | u8 __reserved1[3]; | |
2467 | u8 num_tbs; | |
2468 | struct il_tfd_tb tbs[IL_NUM_OF_TBS]; | |
2469 | __le32 __pad; | |
2470 | } __packed; | |
2471 | /* PCI registers */ | |
2472 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
2473 | ||
3fbbf9a8 | 2474 | struct il_rate_info { |
e7392364 SG |
2475 | u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ |
2476 | u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */ | |
2477 | u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */ | |
2478 | u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */ | |
2479 | u8 prev_ieee; /* previous rate in IEEE speeds */ | |
2480 | u8 next_ieee; /* next rate in IEEE speeds */ | |
2481 | u8 prev_rs; /* previous rate used in rs algo */ | |
2482 | u8 next_rs; /* next rate used in rs algo */ | |
2483 | u8 prev_rs_tgg; /* previous rate used in TGG rs algo */ | |
2484 | u8 next_rs_tgg; /* next rate used in TGG rs algo */ | |
3fbbf9a8 SG |
2485 | }; |
2486 | ||
2487 | struct il3945_rate_info { | |
2488 | u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ | |
2489 | u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */ | |
2490 | u8 prev_ieee; /* previous rate in IEEE speeds */ | |
2491 | u8 next_ieee; /* next rate in IEEE speeds */ | |
2492 | u8 prev_rs; /* previous rate used in rs algo */ | |
2493 | u8 next_rs; /* next rate used in rs algo */ | |
2494 | u8 prev_rs_tgg; /* previous rate used in TGG rs algo */ | |
2495 | u8 next_rs_tgg; /* next rate used in TGG rs algo */ | |
2496 | u8 table_rs_idx; /* idx in rate scale table cmd */ | |
2497 | u8 prev_table_rs; /* prev in rate table cmd */ | |
2498 | }; | |
2499 | ||
3fbbf9a8 SG |
2500 | /* |
2501 | * These serve as idxes into | |
2502 | * struct il_rate_info il_rates[RATE_COUNT]; | |
2503 | */ | |
2504 | enum { | |
2505 | RATE_1M_IDX = 0, | |
2506 | RATE_2M_IDX, | |
2507 | RATE_5M_IDX, | |
2508 | RATE_11M_IDX, | |
2509 | RATE_6M_IDX, | |
2510 | RATE_9M_IDX, | |
2511 | RATE_12M_IDX, | |
2512 | RATE_18M_IDX, | |
2513 | RATE_24M_IDX, | |
2514 | RATE_36M_IDX, | |
2515 | RATE_48M_IDX, | |
2516 | RATE_54M_IDX, | |
2517 | RATE_60M_IDX, | |
2518 | RATE_COUNT, | |
2519 | RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */ | |
2520 | RATE_COUNT_3945 = RATE_COUNT - 1, | |
2521 | RATE_INVM_IDX = RATE_COUNT, | |
2522 | RATE_INVALID = RATE_COUNT, | |
2523 | }; | |
2524 | ||
2525 | enum { | |
2526 | RATE_6M_IDX_TBL = 0, | |
2527 | RATE_9M_IDX_TBL, | |
2528 | RATE_12M_IDX_TBL, | |
2529 | RATE_18M_IDX_TBL, | |
2530 | RATE_24M_IDX_TBL, | |
2531 | RATE_36M_IDX_TBL, | |
2532 | RATE_48M_IDX_TBL, | |
2533 | RATE_54M_IDX_TBL, | |
2534 | RATE_1M_IDX_TBL, | |
2535 | RATE_2M_IDX_TBL, | |
2536 | RATE_5M_IDX_TBL, | |
2537 | RATE_11M_IDX_TBL, | |
2538 | RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1, | |
2539 | }; | |
2540 | ||
2541 | enum { | |
2542 | IL_FIRST_OFDM_RATE = RATE_6M_IDX, | |
2543 | IL39_LAST_OFDM_RATE = RATE_54M_IDX, | |
2544 | IL_LAST_OFDM_RATE = RATE_60M_IDX, | |
2545 | IL_FIRST_CCK_RATE = RATE_1M_IDX, | |
2546 | IL_LAST_CCK_RATE = RATE_11M_IDX, | |
2547 | }; | |
2548 | ||
2549 | /* #define vs. enum to keep from defaulting to 'large integer' */ | |
2550 | #define RATE_6M_MASK (1 << RATE_6M_IDX) | |
2551 | #define RATE_9M_MASK (1 << RATE_9M_IDX) | |
2552 | #define RATE_12M_MASK (1 << RATE_12M_IDX) | |
2553 | #define RATE_18M_MASK (1 << RATE_18M_IDX) | |
2554 | #define RATE_24M_MASK (1 << RATE_24M_IDX) | |
2555 | #define RATE_36M_MASK (1 << RATE_36M_IDX) | |
2556 | #define RATE_48M_MASK (1 << RATE_48M_IDX) | |
2557 | #define RATE_54M_MASK (1 << RATE_54M_IDX) | |
2558 | #define RATE_60M_MASK (1 << RATE_60M_IDX) | |
2559 | #define RATE_1M_MASK (1 << RATE_1M_IDX) | |
2560 | #define RATE_2M_MASK (1 << RATE_2M_IDX) | |
2561 | #define RATE_5M_MASK (1 << RATE_5M_IDX) | |
2562 | #define RATE_11M_MASK (1 << RATE_11M_IDX) | |
2563 | ||
2564 | /* uCode API values for legacy bit rates, both OFDM and CCK */ | |
2565 | enum { | |
e7392364 SG |
2566 | RATE_6M_PLCP = 13, |
2567 | RATE_9M_PLCP = 15, | |
3fbbf9a8 SG |
2568 | RATE_12M_PLCP = 5, |
2569 | RATE_18M_PLCP = 7, | |
2570 | RATE_24M_PLCP = 9, | |
2571 | RATE_36M_PLCP = 11, | |
2572 | RATE_48M_PLCP = 1, | |
2573 | RATE_54M_PLCP = 3, | |
e7392364 SG |
2574 | RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */ |
2575 | RATE_1M_PLCP = 10, | |
2576 | RATE_2M_PLCP = 20, | |
2577 | RATE_5M_PLCP = 55, | |
3fbbf9a8 | 2578 | RATE_11M_PLCP = 110, |
e7392364 | 2579 | /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */ |
3fbbf9a8 SG |
2580 | }; |
2581 | ||
2582 | /* uCode API values for OFDM high-throughput (HT) bit rates */ | |
2583 | enum { | |
2584 | RATE_SISO_6M_PLCP = 0, | |
2585 | RATE_SISO_12M_PLCP = 1, | |
2586 | RATE_SISO_18M_PLCP = 2, | |
2587 | RATE_SISO_24M_PLCP = 3, | |
2588 | RATE_SISO_36M_PLCP = 4, | |
2589 | RATE_SISO_48M_PLCP = 5, | |
2590 | RATE_SISO_54M_PLCP = 6, | |
2591 | RATE_SISO_60M_PLCP = 7, | |
e7392364 | 2592 | RATE_MIMO2_6M_PLCP = 0x8, |
3fbbf9a8 SG |
2593 | RATE_MIMO2_12M_PLCP = 0x9, |
2594 | RATE_MIMO2_18M_PLCP = 0xa, | |
2595 | RATE_MIMO2_24M_PLCP = 0xb, | |
2596 | RATE_MIMO2_36M_PLCP = 0xc, | |
2597 | RATE_MIMO2_48M_PLCP = 0xd, | |
2598 | RATE_MIMO2_54M_PLCP = 0xe, | |
2599 | RATE_MIMO2_60M_PLCP = 0xf, | |
2600 | RATE_SISO_INVM_PLCP, | |
2601 | RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP, | |
2602 | }; | |
2603 | ||
2604 | /* MAC header values for bit rates */ | |
2605 | enum { | |
e7392364 SG |
2606 | RATE_6M_IEEE = 12, |
2607 | RATE_9M_IEEE = 18, | |
3fbbf9a8 SG |
2608 | RATE_12M_IEEE = 24, |
2609 | RATE_18M_IEEE = 36, | |
2610 | RATE_24M_IEEE = 48, | |
2611 | RATE_36M_IEEE = 72, | |
2612 | RATE_48M_IEEE = 96, | |
2613 | RATE_54M_IEEE = 108, | |
2614 | RATE_60M_IEEE = 120, | |
e7392364 SG |
2615 | RATE_1M_IEEE = 2, |
2616 | RATE_2M_IEEE = 4, | |
2617 | RATE_5M_IEEE = 11, | |
3fbbf9a8 SG |
2618 | RATE_11M_IEEE = 22, |
2619 | }; | |
2620 | ||
2621 | #define IL_CCK_BASIC_RATES_MASK \ | |
2622 | (RATE_1M_MASK | \ | |
2623 | RATE_2M_MASK) | |
2624 | ||
2625 | #define IL_CCK_RATES_MASK \ | |
2626 | (IL_CCK_BASIC_RATES_MASK | \ | |
2627 | RATE_5M_MASK | \ | |
2628 | RATE_11M_MASK) | |
2629 | ||
2630 | #define IL_OFDM_BASIC_RATES_MASK \ | |
2631 | (RATE_6M_MASK | \ | |
2632 | RATE_12M_MASK | \ | |
2633 | RATE_24M_MASK) | |
2634 | ||
2635 | #define IL_OFDM_RATES_MASK \ | |
2636 | (IL_OFDM_BASIC_RATES_MASK | \ | |
2637 | RATE_9M_MASK | \ | |
2638 | RATE_18M_MASK | \ | |
2639 | RATE_36M_MASK | \ | |
2640 | RATE_48M_MASK | \ | |
2641 | RATE_54M_MASK) | |
2642 | ||
2643 | #define IL_BASIC_RATES_MASK \ | |
2644 | (IL_OFDM_BASIC_RATES_MASK | \ | |
2645 | IL_CCK_BASIC_RATES_MASK) | |
2646 | ||
2647 | #define RATES_MASK ((1 << RATE_COUNT) - 1) | |
2648 | #define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1) | |
2649 | ||
2650 | #define IL_INVALID_VALUE -1 | |
2651 | ||
2652 | #define IL_MIN_RSSI_VAL -100 | |
2653 | #define IL_MAX_RSSI_VAL 0 | |
2654 | ||
2655 | /* These values specify how many Tx frame attempts before | |
2656 | * searching for a new modulation mode */ | |
2657 | #define IL_LEGACY_FAILURE_LIMIT 160 | |
2658 | #define IL_LEGACY_SUCCESS_LIMIT 480 | |
2659 | #define IL_LEGACY_TBL_COUNT 160 | |
2660 | ||
2661 | #define IL_NONE_LEGACY_FAILURE_LIMIT 400 | |
2662 | #define IL_NONE_LEGACY_SUCCESS_LIMIT 4500 | |
2663 | #define IL_NONE_LEGACY_TBL_COUNT 1500 | |
2664 | ||
2665 | /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */ | |
2666 | #define IL_RS_GOOD_RATIO 12800 /* 100% */ | |
2667 | #define RATE_SCALE_SWITCH 10880 /* 85% */ | |
2668 | #define RATE_HIGH_TH 10880 /* 85% */ | |
2669 | #define RATE_INCREASE_TH 6400 /* 50% */ | |
2670 | #define RATE_DECREASE_TH 1920 /* 15% */ | |
2671 | ||
2672 | /* possible actions when in legacy mode */ | |
2673 | #define IL_LEGACY_SWITCH_ANTENNA1 0 | |
2674 | #define IL_LEGACY_SWITCH_ANTENNA2 1 | |
2675 | #define IL_LEGACY_SWITCH_SISO 2 | |
2676 | #define IL_LEGACY_SWITCH_MIMO2_AB 3 | |
2677 | #define IL_LEGACY_SWITCH_MIMO2_AC 4 | |
2678 | #define IL_LEGACY_SWITCH_MIMO2_BC 5 | |
2679 | ||
2680 | /* possible actions when in siso mode */ | |
2681 | #define IL_SISO_SWITCH_ANTENNA1 0 | |
2682 | #define IL_SISO_SWITCH_ANTENNA2 1 | |
2683 | #define IL_SISO_SWITCH_MIMO2_AB 2 | |
2684 | #define IL_SISO_SWITCH_MIMO2_AC 3 | |
2685 | #define IL_SISO_SWITCH_MIMO2_BC 4 | |
2686 | #define IL_SISO_SWITCH_GI 5 | |
2687 | ||
2688 | /* possible actions when in mimo mode */ | |
2689 | #define IL_MIMO2_SWITCH_ANTENNA1 0 | |
2690 | #define IL_MIMO2_SWITCH_ANTENNA2 1 | |
2691 | #define IL_MIMO2_SWITCH_SISO_A 2 | |
2692 | #define IL_MIMO2_SWITCH_SISO_B 3 | |
2693 | #define IL_MIMO2_SWITCH_SISO_C 4 | |
2694 | #define IL_MIMO2_SWITCH_GI 5 | |
2695 | ||
2696 | #define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI | |
2697 | ||
2698 | #define IL_ACTION_LIMIT 3 /* # possible actions */ | |
2699 | ||
2700 | #define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */ | |
2701 | ||
2702 | /* load per tid defines for A-MPDU activation */ | |
2703 | #define IL_AGG_TPT_THREHOLD 0 | |
2704 | #define IL_AGG_LOAD_THRESHOLD 10 | |
2705 | #define IL_AGG_ALL_TID 0xff | |
2706 | #define TID_QUEUE_CELL_SPACING 50 /*mS */ | |
2707 | #define TID_QUEUE_MAX_SIZE 20 | |
2708 | #define TID_ROUND_VALUE 5 /* mS */ | |
2709 | #define TID_MAX_LOAD_COUNT 8 | |
2710 | ||
2711 | #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING) | |
2712 | #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y)) | |
2713 | ||
2714 | extern const struct il_rate_info il_rates[RATE_COUNT]; | |
2715 | ||
2716 | enum il_table_type { | |
2717 | LQ_NONE, | |
e7392364 | 2718 | LQ_G, /* legacy types */ |
3fbbf9a8 | 2719 | LQ_A, |
e7392364 | 2720 | LQ_SISO, /* high-throughput types */ |
3fbbf9a8 SG |
2721 | LQ_MIMO2, |
2722 | LQ_MAX, | |
2723 | }; | |
2724 | ||
2725 | #define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A) | |
2726 | #define is_siso(tbl) ((tbl) == LQ_SISO) | |
2727 | #define is_mimo2(tbl) ((tbl) == LQ_MIMO2) | |
2728 | #define is_mimo(tbl) (is_mimo2(tbl)) | |
2729 | #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) | |
2730 | #define is_a_band(tbl) ((tbl) == LQ_A) | |
2731 | #define is_g_and(tbl) ((tbl) == LQ_G) | |
2732 | ||
2733 | #define ANT_NONE 0x0 | |
2734 | #define ANT_A BIT(0) | |
2735 | #define ANT_B BIT(1) | |
2736 | #define ANT_AB (ANT_A | ANT_B) | |
2737 | #define ANT_C BIT(2) | |
2738 | #define ANT_AC (ANT_A | ANT_C) | |
2739 | #define ANT_BC (ANT_B | ANT_C) | |
2740 | #define ANT_ABC (ANT_AB | ANT_C) | |
2741 | ||
2742 | #define IL_MAX_MCS_DISPLAY_SIZE 12 | |
2743 | ||
2744 | struct il_rate_mcs_info { | |
e7392364 SG |
2745 | char mbps[IL_MAX_MCS_DISPLAY_SIZE]; |
2746 | char mcs[IL_MAX_MCS_DISPLAY_SIZE]; | |
3fbbf9a8 SG |
2747 | }; |
2748 | ||
2749 | /** | |
2750 | * struct il_rate_scale_data -- tx success history for one rate | |
2751 | */ | |
2752 | struct il_rate_scale_data { | |
2753 | u64 data; /* bitmap of successful frames */ | |
2754 | s32 success_counter; /* number of frames successful */ | |
2755 | s32 success_ratio; /* per-cent * 128 */ | |
2756 | s32 counter; /* number of frames attempted */ | |
2757 | s32 average_tpt; /* success ratio * expected throughput */ | |
2758 | unsigned long stamp; | |
2759 | }; | |
2760 | ||
2761 | /** | |
2762 | * struct il_scale_tbl_info -- tx params and success history for all rates | |
2763 | * | |
2764 | * There are two of these in struct il_lq_sta, | |
2765 | * one for "active", and one for "search". | |
2766 | */ | |
2767 | struct il_scale_tbl_info { | |
2768 | enum il_table_type lq_type; | |
2769 | u8 ant_type; | |
e7392364 SG |
2770 | u8 is_SGI; /* 1 = short guard interval */ |
2771 | u8 is_ht40; /* 1 = 40 MHz channel width */ | |
2772 | u8 is_dup; /* 1 = duplicated data streams */ | |
2773 | u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */ | |
2774 | u8 max_search; /* maximun number of tables we can search */ | |
3fbbf9a8 | 2775 | s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */ |
e7392364 SG |
2776 | u32 current_rate; /* rate_n_flags, uCode API format */ |
2777 | struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */ | |
3fbbf9a8 SG |
2778 | }; |
2779 | ||
2780 | struct il_traffic_load { | |
2781 | unsigned long time_stamp; /* age of the oldest stats */ | |
e7392364 | 2782 | u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time |
3fbbf9a8 | 2783 | * slice */ |
e7392364 SG |
2784 | u32 total; /* total num of packets during the |
2785 | * last TID_MAX_TIME_DIFF */ | |
2786 | u8 queue_count; /* number of queues that has | |
2787 | * been used since the last cleanup */ | |
2788 | u8 head; /* start of the circular buffer */ | |
3fbbf9a8 SG |
2789 | }; |
2790 | ||
2791 | /** | |
2792 | * struct il_lq_sta -- driver's rate scaling ilate structure | |
2793 | * | |
2794 | * Pointer to this gets passed back and forth between driver and mac80211. | |
2795 | */ | |
2796 | struct il_lq_sta { | |
2797 | u8 active_tbl; /* idx of active table, range 0-1 */ | |
2798 | u8 enable_counter; /* indicates HT mode */ | |
2799 | u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */ | |
2800 | u8 search_better_tbl; /* 1: currently trying alternate mode */ | |
2801 | s32 last_tpt; | |
2802 | ||
2803 | /* The following determine when to search for a new mode */ | |
2804 | u32 table_count_limit; | |
2805 | u32 max_failure_limit; /* # failed frames before new search */ | |
2806 | u32 max_success_limit; /* # successful frames before new search */ | |
2807 | u32 table_count; | |
2808 | u32 total_failed; /* total failed frames, any/all rates */ | |
2809 | u32 total_success; /* total successful frames, any/all rates */ | |
2810 | u64 flush_timer; /* time staying in mode before new search */ | |
2811 | ||
2812 | u8 action_counter; /* # mode-switch actions tried */ | |
2813 | u8 is_green; | |
2814 | u8 is_dup; | |
2815 | enum ieee80211_band band; | |
2816 | ||
2817 | /* The following are bitmaps of rates; RATE_6M_MASK, etc. */ | |
2818 | u32 supp_rates; | |
2819 | u16 active_legacy_rate; | |
2820 | u16 active_siso_rate; | |
2821 | u16 active_mimo2_rate; | |
e7392364 | 2822 | s8 max_rate_idx; /* Max rate set by user */ |
3fbbf9a8 SG |
2823 | u8 missed_rate_counter; |
2824 | ||
2825 | struct il_link_quality_cmd lq; | |
e7392364 | 2826 | struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */ |
3fbbf9a8 SG |
2827 | struct il_traffic_load load[TID_MAX_LOAD_COUNT]; |
2828 | u8 tx_agg_tid_en; | |
2829 | #ifdef CONFIG_MAC80211_DEBUGFS | |
2830 | struct dentry *rs_sta_dbgfs_scale_table_file; | |
2831 | struct dentry *rs_sta_dbgfs_stats_table_file; | |
2832 | struct dentry *rs_sta_dbgfs_rate_scale_data_file; | |
2833 | struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file; | |
2834 | u32 dbg_fixed_rate; | |
2835 | #endif | |
2836 | struct il_priv *drv; | |
2837 | ||
2838 | /* used to be in sta_info */ | |
2839 | int last_txrate_idx; | |
2840 | /* last tx rate_n_flags */ | |
2841 | u32 last_rate_n_flags; | |
2842 | /* packets destined for this STA are aggregated */ | |
2843 | u8 is_agg; | |
2844 | }; | |
2845 | ||
2846 | /* | |
2847 | * il_station_priv: Driver's ilate station information | |
2848 | * | |
2849 | * When mac80211 creates a station it reserves some space (hw->sta_data_size) | |
2850 | * in the structure for use by driver. This structure is places in that | |
2851 | * space. | |
2852 | * | |
2853 | * The common struct MUST be first because it is shared between | |
2854 | * 3945 and 4965! | |
2855 | */ | |
2856 | struct il_station_priv { | |
2857 | struct il_station_priv_common common; | |
2858 | struct il_lq_sta lq_sta; | |
2859 | atomic_t pending_frames; | |
2860 | bool client; | |
2861 | bool asleep; | |
2862 | }; | |
2863 | ||
e7392364 SG |
2864 | static inline u8 |
2865 | il4965_num_of_ant(u8 m) | |
3fbbf9a8 SG |
2866 | { |
2867 | return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C); | |
2868 | } | |
2869 | ||
e7392364 SG |
2870 | static inline u8 |
2871 | il4965_first_antenna(u8 mask) | |
3fbbf9a8 SG |
2872 | { |
2873 | if (mask & ANT_A) | |
2874 | return ANT_A; | |
2875 | if (mask & ANT_B) | |
2876 | return ANT_B; | |
2877 | return ANT_C; | |
2878 | } | |
2879 | ||
3fbbf9a8 SG |
2880 | /** |
2881 | * il3945_rate_scale_init - Initialize the rate scale table based on assoc info | |
2882 | * | |
2883 | * The specific throughput table used is based on the type of network | |
2884 | * the associated with, including A, B, G, and G w/ TGG protection | |
2885 | */ | |
6890ba72 | 2886 | void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id); |
3fbbf9a8 SG |
2887 | |
2888 | /* Initialize station's rate scaling information after adding station */ | |
6890ba72 JP |
2889 | void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta, |
2890 | u8 sta_id); | |
2891 | void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta, | |
2892 | u8 sta_id); | |
3fbbf9a8 SG |
2893 | |
2894 | /** | |
2895 | * il_rate_control_register - Register the rate control algorithm callbacks | |
2896 | * | |
2897 | * Since the rate control algorithm is hardware specific, there is no need | |
2898 | * or reason to place it as a stand alone module. The driver can call | |
2899 | * il_rate_control_register in order to register the rate control callbacks | |
2900 | * with the mac80211 subsystem. This should be performed prior to calling | |
2901 | * ieee80211_register_hw | |
2902 | * | |
2903 | */ | |
6890ba72 JP |
2904 | int il4965_rate_control_register(void); |
2905 | int il3945_rate_control_register(void); | |
3fbbf9a8 SG |
2906 | |
2907 | /** | |
2908 | * il_rate_control_unregister - Unregister the rate control callbacks | |
2909 | * | |
2910 | * This should be called after calling ieee80211_unregister_hw, but before | |
2911 | * the driver is unloaded. | |
2912 | */ | |
6890ba72 JP |
2913 | void il4965_rate_control_unregister(void); |
2914 | void il3945_rate_control_unregister(void); | |
3fbbf9a8 | 2915 | |
6890ba72 JP |
2916 | int il_power_update_mode(struct il_priv *il, bool force); |
2917 | void il_power_initialize(struct il_priv *il); | |
47ef694d | 2918 | |
f02579e3 SG |
2919 | extern u32 il_debug_level; |
2920 | ||
2921 | #ifdef CONFIG_IWLEGACY_DEBUG | |
2922 | /* | |
2923 | * il_get_debug_level: Return active debug level for device | |
2924 | * | |
2925 | * Using sysfs it is possible to set per device debug level. This debug | |
2926 | * level will be used if set, otherwise the global debug level which can be | |
2927 | * set via module parameter is used. | |
2928 | */ | |
e7392364 SG |
2929 | static inline u32 |
2930 | il_get_debug_level(struct il_priv *il) | |
f02579e3 SG |
2931 | { |
2932 | if (il->debug_level) | |
2933 | return il->debug_level; | |
2934 | else | |
2935 | return il_debug_level; | |
2936 | } | |
2937 | #else | |
e7392364 SG |
2938 | static inline u32 |
2939 | il_get_debug_level(struct il_priv *il) | |
f02579e3 SG |
2940 | { |
2941 | return il_debug_level; | |
2942 | } | |
2943 | #endif | |
2944 | ||
2945 | #define il_print_hex_error(il, p, len) \ | |
2946 | do { \ | |
2947 | print_hex_dump(KERN_ERR, "iwl data: ", \ | |
2948 | DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \ | |
2949 | } while (0) | |
2950 | ||
2951 | #ifdef CONFIG_IWLEGACY_DEBUG | |
2952 | #define IL_DBG(level, fmt, args...) \ | |
2953 | do { \ | |
2954 | if (il_get_debug_level(il) & level) \ | |
6a4b09f8 JP |
2955 | dev_err(&il->hw->wiphy->dev, "%c %s " fmt, \ |
2956 | in_interrupt() ? 'I' : 'U', __func__ , ##args); \ | |
f02579e3 SG |
2957 | } while (0) |
2958 | ||
1722f8e1 | 2959 | #define il_print_hex_dump(il, level, p, len) \ |
f02579e3 SG |
2960 | do { \ |
2961 | if (il_get_debug_level(il) & level) \ | |
2962 | print_hex_dump(KERN_DEBUG, "iwl data: ", \ | |
2963 | DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \ | |
2964 | } while (0) | |
2965 | ||
2966 | #else | |
2967 | #define IL_DBG(level, fmt, args...) | |
e7392364 SG |
2968 | static inline void |
2969 | il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len) | |
2970 | { | |
2971 | } | |
2972 | #endif /* CONFIG_IWLEGACY_DEBUG */ | |
f02579e3 SG |
2973 | |
2974 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
2975 | int il_dbgfs_register(struct il_priv *il, const char *name); | |
2976 | void il_dbgfs_unregister(struct il_priv *il); | |
2977 | #else | |
2978 | static inline int | |
2979 | il_dbgfs_register(struct il_priv *il, const char *name) | |
2980 | { | |
2981 | return 0; | |
2982 | } | |
e7392364 SG |
2983 | |
2984 | static inline void | |
2985 | il_dbgfs_unregister(struct il_priv *il) | |
f02579e3 SG |
2986 | { |
2987 | } | |
e7392364 | 2988 | #endif /* CONFIG_IWLEGACY_DEBUGFS */ |
f02579e3 SG |
2989 | |
2990 | /* | |
2991 | * To use the debug system: | |
2992 | * | |
2993 | * If you are defining a new debug classification, simply add it to the #define | |
2994 | * list here in the form of | |
2995 | * | |
2996 | * #define IL_DL_xxxx VALUE | |
2997 | * | |
2998 | * where xxxx should be the name of the classification (for example, WEP). | |
2999 | * | |
3000 | * You then need to either add a IL_xxxx_DEBUG() macro definition for your | |
3001 | * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want | |
3002 | * to send output to that classification. | |
3003 | * | |
3004 | * The active debug levels can be accessed via files | |
3005 | * | |
1722f8e1 | 3006 | * /sys/module/iwl4965/parameters/debug |
f02579e3 | 3007 | * /sys/module/iwl3945/parameters/debug |
1722f8e1 | 3008 | * /sys/class/net/wlan0/device/debug_level |
f02579e3 SG |
3009 | * |
3010 | * when CONFIG_IWLEGACY_DEBUG=y. | |
3011 | */ | |
3012 | ||
3013 | /* 0x0000000F - 0x00000001 */ | |
3014 | #define IL_DL_INFO (1 << 0) | |
3015 | #define IL_DL_MAC80211 (1 << 1) | |
3016 | #define IL_DL_HCMD (1 << 2) | |
3017 | #define IL_DL_STATE (1 << 3) | |
3018 | /* 0x000000F0 - 0x00000010 */ | |
3019 | #define IL_DL_MACDUMP (1 << 4) | |
3020 | #define IL_DL_HCMD_DUMP (1 << 5) | |
3021 | #define IL_DL_EEPROM (1 << 6) | |
3022 | #define IL_DL_RADIO (1 << 7) | |
3023 | /* 0x00000F00 - 0x00000100 */ | |
3024 | #define IL_DL_POWER (1 << 8) | |
3025 | #define IL_DL_TEMP (1 << 9) | |
3026 | #define IL_DL_NOTIF (1 << 10) | |
3027 | #define IL_DL_SCAN (1 << 11) | |
3028 | /* 0x0000F000 - 0x00001000 */ | |
3029 | #define IL_DL_ASSOC (1 << 12) | |
3030 | #define IL_DL_DROP (1 << 13) | |
3031 | #define IL_DL_TXPOWER (1 << 14) | |
3032 | #define IL_DL_AP (1 << 15) | |
3033 | /* 0x000F0000 - 0x00010000 */ | |
3034 | #define IL_DL_FW (1 << 16) | |
3035 | #define IL_DL_RF_KILL (1 << 17) | |
3036 | #define IL_DL_FW_ERRORS (1 << 18) | |
3037 | #define IL_DL_LED (1 << 19) | |
3038 | /* 0x00F00000 - 0x00100000 */ | |
3039 | #define IL_DL_RATE (1 << 20) | |
3040 | #define IL_DL_CALIB (1 << 21) | |
3041 | #define IL_DL_WEP (1 << 22) | |
3042 | #define IL_DL_TX (1 << 23) | |
3043 | /* 0x0F000000 - 0x01000000 */ | |
3044 | #define IL_DL_RX (1 << 24) | |
3045 | #define IL_DL_ISR (1 << 25) | |
3046 | #define IL_DL_HT (1 << 26) | |
3047 | /* 0xF0000000 - 0x10000000 */ | |
3048 | #define IL_DL_11H (1 << 28) | |
3049 | #define IL_DL_STATS (1 << 29) | |
3050 | #define IL_DL_TX_REPLY (1 << 30) | |
3051 | #define IL_DL_QOS (1 << 31) | |
3052 | ||
3053 | #define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a) | |
3054 | #define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a) | |
3055 | #define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a) | |
3056 | #define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a) | |
3057 | #define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a) | |
3058 | #define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a) | |
3059 | #define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a) | |
3060 | #define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a) | |
3061 | #define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a) | |
3062 | #define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a) | |
3063 | #define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a) | |
3064 | #define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a) | |
3065 | #define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a) | |
3066 | #define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a) | |
3067 | #define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a) | |
3068 | #define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a) | |
3069 | #define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a) | |
3070 | #define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a) | |
3071 | #define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a) | |
3072 | #define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a) | |
3073 | #define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a) | |
3074 | #define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a) | |
3075 | #define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a) | |
3076 | #define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a) | |
3077 | #define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a) | |
3078 | #define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a) | |
3079 | #define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a) | |
3080 | #define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a) | |
3081 | #define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a) | |
3082 | ||
e2ebc833 | 3083 | #endif /* __il_core_h__ */ |