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iwlegacy: move ops out of config
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.h
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
e94a4099 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
be663ab6 4 *
e94a4099
SG		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
be663ab6
WYG		 7 * published by the Free Software Foundation.
8 *
e94a4099
SG		 9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
be663ab6 13 *
e94a4099
SG		 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
be663ab6 17 *
e94a4099
SG		 18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
be663ab6
WYG		 20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
e94a4099
SG		 25 *****************************************************************************/
26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
e7392364 30#include <linux/pci.h> /* for struct pci_device_id */
e94a4099
SG		 31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
17d4eca6 34#include <linux/io.h>
47ef694d 35#include <net/mac80211.h>
e94a4099
SG		 36#include <net/ieee80211_radiotap.h>
37
99412002 38#include "commands.h"
e94a4099 39#include "csr.h"
e8c39d4e 40#include "prph.h"
e94a4099
SG		 41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
f02579e3
SG		 46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
e94a4099
SG		 50#define RX_QUEUE_SIZE 256
51#define RX_QUEUE_MASK 255
52#define RX_QUEUE_SIZE_LOG 8
53
54/*
55 * RX related structures and functions
56 */
57#define RX_FREE_BUFFERS 64
58#define RX_LOW_WATERMARK 8
59
60#define U32_PAD(n) ((4-(n))&0x3)
61
62/* CT-KILL constants */
e7392364 63#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
e94a4099
SG		 64
65/* Default noise level to report when noise measurement is not available.
66 * This may be because we're:
67 * 1) Not associated (4965, no beacon stats being sent to driver)
68 * 2) Scanning (noise measurement does not apply to associated channel)
69 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
70 * Use default noise value of -127 ... this is below the range of measurable
71 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
72 * Also, -127 works better than 0 when averaging frames with/without
73 * noise info (e.g. averaging might be done in app); measured dBm values are
74 * always negative ... using a negative value as the default keeps all
75 * averages within an s8's (used in some apps) range of negative values. */
76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
77
78/*
79 * RTS threshold here is total size [2347] minus 4 FCS bytes
80 * Per spec:
81 * a value of 0 means RTS on all data/management packets
82 * a value > max MSDU size means no RTS
83 * else RTS for data/management frames where MPDU is larger
84 * than RTS value.
85 */
86#define DEFAULT_RTS_THRESHOLD 2347U
87#define MIN_RTS_THRESHOLD 0U
88#define MAX_RTS_THRESHOLD 2347U
89#define MAX_MSDU_SIZE 2304U
90#define MAX_MPDU_SIZE 2346U
91#define DEFAULT_BEACON_INTERVAL 100U
92#define DEFAULT_SHORT_RETRY_LIMIT 7U
93#define DEFAULT_LONG_RETRY_LIMIT 4U
94
95struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99};
100
101#define rxb_addr(r) page_address(r->page)
102
103/* defined below */
104struct il_device_cmd;
105
106struct il_cmd_meta {
107 /* only for SYNC commands, iff the reply skb is wanted */
108 struct il_host_cmd *source;
109 /*
110 * only for ASYNC commands
111 * (which is somewhat stupid -- look at common.c for instance
112 * which duplicates a bunch of code because the callback isn't
113 * invoked for SYNC commands, if it were and its result passed
114 * through it would be simpler...)
115 */
1722f8e1
SG		 116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
e94a4099
SG		 118
119 /* The CMD_SIZE_HUGE flag bit indicates that the command
120 * structure is stored at the end of the shared queue memory. */
121 u32 flags;
122
e7392364
SG		 123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
e94a4099
SG		 125};
126
127/*
128 * Generic queue structure
129 *
130 * Contains common data for Rx and Tx queues
131 */
132struct il_queue {
e7392364
SG		 133 int n_bd; /* number of BDs in this queue */
134 int write_ptr; /* 1-st empty entry (idx) host_w */
135 int read_ptr; /* last used entry (idx) host_r */
e94a4099 136 /* use for monitoring and recovering the stuck queue */
e7392364
SG		 137 dma_addr_t dma_addr; /* physical addr for BD's */
138 int n_win; /* safe queue win */
e94a4099 139 u32 id;
e7392364
SG		 140 int low_mark; /* low watermark, resume queue if free
141 * space more than this */
142 int high_mark; /* high watermark, stop queue if free
143 * space less than this */
e94a4099
SG		 144};
145
146/* One for each TFD */
147struct il_tx_info {
148 struct sk_buff *skb;
e94a4099
SG		 149};
150
151/**
152 * struct il_tx_queue - Tx Queue for DMA
153 * @q: generic Rx/Tx queue descriptor
154 * @bd: base of circular buffer of TFDs
155 * @cmd: array of command/TX buffer pointers
156 * @meta: array of meta data for each command/tx buffer
157 * @dma_addr_cmd: physical address of cmd/tx buffer array
158 * @txb: array of per-TFD driver data
159 * @time_stamp: time (in jiffies) of last read_ptr change
160 * @need_update: indicates need to update read/write idx
161 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
162 *
163 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
164 * descriptors) and required locking structures.
165 */
166#define TFD_TX_CMD_SLOTS 256
167#define TFD_CMD_SLOTS 32
168
169struct il_tx_queue {
170 struct il_queue q;
171 void *tfds;
172 struct il_device_cmd **cmd;
173 struct il_cmd_meta *meta;
174 struct il_tx_info *txb;
175 unsigned long time_stamp;
176 u8 need_update;
177 u8 sched_retry;
178 u8 active;
179 u8 swq_id;
180};
181
47ef694d
SG		 182/*
183 * EEPROM access time values:
184 *
185 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
186 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
187 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
188 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
189 */
e7392364 190#define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
47ef694d 191
e7392364
SG		 192#define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
193#define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
47ef694d
SG		 194
195/*
196 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
197 *
198 * IBSS and/or AP operation is allowed *only* on those channels with
199 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
200 * RADAR detection is not supported by the 4965 driver, but is a
201 * requirement for establishing a new network for legal operation on channels
202 * requiring RADAR detection or restricting ACTIVE scanning.
203 *
204 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
205 * It only indicates that 20 MHz channel use is supported; HT40 channel
206 * usage is indicated by a separate set of regulatory flags for each
207 * HT40 channel pair.
208 *
209 * NOTE: Using a channel inappropriately will result in a uCode error!
210 */
211#define IL_NUM_TX_CALIB_GROUPS 5
212enum {
213 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
e7392364 214 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
47ef694d
SG		 215 /* Bit 2 Reserved */
216 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
217 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
e7392364 218 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
47ef694d
SG		 219 /* Bit 6 Reserved (was Narrow Channel) */
220 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
221};
222
223/* SKU Capabilities */
224/* 3945 only */
225#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
226#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
227
228/* *regulatory* channel data format in eeprom, one for each channel.
229 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
230struct il_eeprom_channel {
231 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
232 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
233} __packed;
234
235/* 3945 Specific */
236#define EEPROM_3945_EEPROM_VERSION (0x2f)
237
238/* 4965 has two radio transmitters (and 3 radio receivers) */
239#define EEPROM_TX_POWER_TX_CHAINS (2)
240
241/* 4965 has room for up to 8 sets of txpower calibration data */
242#define EEPROM_TX_POWER_BANDS (8)
243
244/* 4965 factory calibration measures txpower gain settings for
245 * each of 3 target output levels */
246#define EEPROM_TX_POWER_MEASUREMENTS (3)
247
248/* 4965 Specific */
249/* 4965 driver does not work with txpower calibration version < 5 */
250#define EEPROM_4965_TX_POWER_VERSION (5)
251#define EEPROM_4965_EEPROM_VERSION (0x2f)
e7392364
SG		 252#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
253#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
254#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
255#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
47ef694d
SG		 256
257/* 2.4 GHz */
258extern const u8 il_eeprom_band_1[14];
259
260/*
261 * factory calibration data for one txpower level, on one channel,
262 * measured on one of the 2 tx chains (radio transmitter and associated
263 * antenna). EEPROM contains:
264 *
265 * 1) Temperature (degrees Celsius) of device when measurement was made.
266 *
267 * 2) Gain table idx used to achieve the target measurement power.
268 * This refers to the "well-known" gain tables (see 4965.h).
269 *
270 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
271 *
272 * 4) RF power amplifier detector level measurement (not used).
273 */
274struct il_eeprom_calib_measure {
275 u8 temperature; /* Device temperature (Celsius) */
276 u8 gain_idx; /* Index into gain table */
277 u8 actual_pow; /* Measured RF output power, half-dBm */
278 s8 pa_det; /* Power amp detector level (not used) */
279} __packed;
280
47ef694d
SG		 281/*
282 * measurement set for one channel. EEPROM contains:
283 *
284 * 1) Channel number measured
285 *
286 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
287 * (a.k.a. "tx chains") (6 measurements altogether)
288 */
289struct il_eeprom_calib_ch_info {
290 u8 ch_num;
291 struct il_eeprom_calib_measure
e7392364
SG		 292 measurements[EEPROM_TX_POWER_TX_CHAINS]
293 [EEPROM_TX_POWER_MEASUREMENTS];
47ef694d
SG		 294} __packed;
295
296/*
297 * txpower subband info.
298 *
299 * For each frequency subband, EEPROM contains the following:
300 *
301 * 1) First and last channels within range of the subband. "0" values
302 * indicate that this sample set is not being used.
303 *
304 * 2) Sample measurement sets for 2 channels close to the range endpoints.
305 */
306struct il_eeprom_calib_subband_info {
e7392364
SG		 307 u8 ch_from; /* channel number of lowest channel in subband */
308 u8 ch_to; /* channel number of highest channel in subband */
47ef694d
SG		 309 struct il_eeprom_calib_ch_info ch1;
310 struct il_eeprom_calib_ch_info ch2;
311} __packed;
312
47ef694d
SG		 313/*
314 * txpower calibration info. EEPROM contains:
315 *
316 * 1) Factory-measured saturation power levels (maximum levels at which
317 * tx power amplifier can output a signal without too much distortion).
318 * There is one level for 2.4 GHz band and one for 5 GHz band. These
319 * values apply to all channels within each of the bands.
320 *
321 * 2) Factory-measured power supply voltage level. This is assumed to be
322 * constant (i.e. same value applies to all channels/bands) while the
323 * factory measurements are being made.
324 *
325 * 3) Up to 8 sets of factory-measured txpower calibration values.
326 * These are for different frequency ranges, since txpower gain
327 * characteristics of the analog radio circuitry vary with frequency.
328 *
329 * Not all sets need to be filled with data;
330 * struct il_eeprom_calib_subband_info contains range of channels
331 * (0 if unused) for each set of data.
332 */
333struct il_eeprom_calib_info {
334 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
335 u8 saturation_power52; /* half-dBm */
336 __le16 voltage; /* signed */
e7392364 337 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
47ef694d
SG		 338} __packed;
339
47ef694d
SG		 340/* General */
341#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
342#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
343#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
344#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
345#define EEPROM_VERSION (2*0x44) /* 2 bytes */
346#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
347#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
348#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
349#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
350#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
351
352/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
e7392364
SG		 353#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
354#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
355#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
356#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
357#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
358#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
47ef694d
SG		 359
360#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
361#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
362
363/*
364 * Per-channel regulatory data.
365 *
366 * Each channel that *might* be supported by iwl has a fixed location
367 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
368 * txpower (MSB).
369 *
370 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
371 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
372 *
373 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
374 */
e7392364 375#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
47ef694d
SG		 376#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
377#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
378
379/*
380 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
381 * 5.0 GHz channels 7, 8, 11, 12, 16
382 * (4915-5080MHz) (none of these is ever supported)
383 */
384#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
385#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
386
387/*
388 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
389 * (5170-5320MHz)
390 */
391#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
392#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
393
394/*
395 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
396 * (5500-5700MHz)
397 */
398#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
399#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
400
401/*
402 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
403 * (5725-5825MHz)
404 */
405#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
406#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
407
408/*
409 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
410 *
411 * The channel listed is the center of the lower 20 MHz half of the channel.
412 * The overall center frequency is actually 2 channels (10 MHz) above that,
413 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
414 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
415 * and the overall HT40 channel width centers on channel 3.
416 *
417 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
418 * control channel to which to tune. RXON also specifies whether the
419 * control channel is the upper or lower half of a HT40 channel.
420 *
421 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
422 */
423#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
424
425/*
426 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
427 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
428 */
429#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
430
431#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
432
433struct il_eeprom_ops {
434 const u32 regulatory_bands[7];
1722f8e1
SG		 435 int (*acquire_semaphore) (struct il_priv *il);
436 void (*release_semaphore) (struct il_priv *il);
47ef694d
SG		 437};
438
47ef694d
SG		 439int il_eeprom_init(struct il_priv *il);
440void il_eeprom_free(struct il_priv *il);
e7392364 441const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
47ef694d
SG		 442u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
443int il_init_channel_map(struct il_priv *il);
444void il_free_channel_map(struct il_priv *il);
e7392364
SG		 445const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
446 enum ieee80211_band band,
447 u16 channel);
47ef694d 448
e94a4099
SG		 449#define IL_NUM_SCAN_RATES (2)
450
451struct il4965_channel_tgd_info {
452 u8 type;
453 s8 max_power;
454};
455
456struct il4965_channel_tgh_info {
457 s64 last_radar_time;
458};
459
460#define IL4965_MAX_RATE (33)
461
462struct il3945_clip_group {
463 /* maximum power level to prevent clipping for each rate, derived by
464 * us from this band's saturation power in EEPROM */
465 const s8 clip_powers[IL_MAX_RATES];
466};
467
468/* current Tx power values to use, one for each rate for each channel.
469 * requested power is limited by:
470 * -- regulatory EEPROM limits for this channel
471 * -- hardware capabilities (clip-powers)
472 * -- spectrum management
473 * -- user preference (e.g. iwconfig)
474 * when requested power is set, base power idx must also be set. */
475struct il3945_channel_power_info {
476 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
477 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
478 s8 base_power_idx; /* gain idx for power at factory temp. */
479 s8 requested_power; /* power (dBm) requested for this chnl/rate */
480};
481
482/* current scan Tx power values to use, one for each scan rate for each
483 * channel. */
484struct il3945_scan_power_info {
485 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
486 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
487 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
488};
489
490/*
491 * One for each channel, holds all channel setup data
492 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
493 * with one another!
494 */
495struct il_channel_info {
496 struct il4965_channel_tgd_info tgd;
497 struct il4965_channel_tgh_info tgh;
498 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
499 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
500 * HT40 channel */
501
e7392364
SG		 502 u8 channel; /* channel number */
503 u8 flags; /* flags copied from EEPROM */
504 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
505 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
506 s8 min_power; /* always 0 */
507 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
e94a4099 508
e7392364
SG		 509 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
510 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
e94a4099
SG		 511 enum ieee80211_band band;
512
513 /* HT40 channel info */
514 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
515 u8 ht40_flags; /* flags copied from EEPROM */
e7392364 516 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
e94a4099
SG		 517
518 /* Radio/DSP gain settings for each "normal" data Tx rate.
519 * These include, in addition to RF and DSP gain, a few fields for
520 * remembering/modifying gain settings (idxes). */
521 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
522
523 /* Radio/DSP gain settings for each scan rate, for directed scans. */
524 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
525};
526
527#define IL_TX_FIFO_BK 0 /* shared */
528#define IL_TX_FIFO_BE 1
529#define IL_TX_FIFO_VI 2 /* shared */
530#define IL_TX_FIFO_VO 3
531#define IL_TX_FIFO_UNUSED -1
532
533/* Minimum number of queues. MAX_NUM is defined in hw specific files.
534 * Set the minimum to accommodate the 4 standard TX queues, 1 command
535 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
536#define IL_MIN_NUM_QUEUES 10
537
538#define IL_DEFAULT_CMD_QUEUE_NUM 4
539
540#define IEEE80211_DATA_LEN 2304
541#define IEEE80211_4ADDR_LEN 30
542#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
543#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
544
545struct il_frame {
546 union {
547 struct ieee80211_hdr frame;
548 struct il_tx_beacon_cmd beacon;
549 u8 raw[IEEE80211_FRAME_LEN];
550 u8 cmd[360];
551 } u;
552 struct list_head list;
553};
554
555#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
556#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
557#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
558
559enum {
560 CMD_SYNC = 0,
561 CMD_SIZE_NORMAL = 0,
562 CMD_NO_SKB = 0,
563 CMD_SIZE_HUGE = (1 << 0),
564 CMD_ASYNC = (1 << 1),
565 CMD_WANT_SKB = (1 << 2),
566 CMD_MAPPED = (1 << 3),
567};
568
569#define DEF_CMD_PAYLOAD_SIZE 320
570
571/**
572 * struct il_device_cmd
573 *
574 * For allocation of the command and tx queues, this establishes the overall
575 * size of the largest command we send to uCode, except for a scan command
576 * (which is relatively huge; space is allocated separately).
577 */
578struct il_device_cmd {
579 struct il_cmd_header hdr; /* uCode API */
580 union {
581 u32 flags;
582 u8 val8;
583 u16 val16;
584 u32 val32;
585 struct il_tx_cmd tx;
586 u8 payload[DEF_CMD_PAYLOAD_SIZE];
587 } __packed cmd;
588} __packed;
589
590#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
591
e94a4099
SG		 592struct il_host_cmd {
593 const void *data;
594 unsigned long reply_page;
1722f8e1
SG		 595 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
596 struct il_rx_pkt *pkt);
e94a4099
SG		 597 u32 flags;
598 u16 len;
599 u8 id;
600};
601
602#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
603#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
604#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
605
606/**
607 * struct il_rx_queue - Rx queue
608 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
609 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
610 * @read: Shared idx to newest available Rx buffer
611 * @write: Shared idx to oldest written Rx packet
612 * @free_count: Number of pre-allocated buffers in rx_free
613 * @rx_free: list of free SKBs for use
614 * @rx_used: List of Rx buffers with no SKB
615 * @need_update: flag to indicate we need to update read/write idx
616 * @rb_stts: driver's pointer to receive buffer status
617 * @rb_stts_dma: bus address of receive buffer status
618 *
619 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
620 */
621struct il_rx_queue {
622 __le32 *bd;
623 dma_addr_t bd_dma;
624 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
625 struct il_rx_buf *queue[RX_QUEUE_SIZE];
626 u32 read;
627 u32 write;
628 u32 free_count;
629 u32 write_actual;
630 struct list_head rx_free;
631 struct list_head rx_used;
632 int need_update;
633 struct il_rb_status *rb_stts;
634 dma_addr_t rb_stts_dma;
635 spinlock_t lock;
636};
637
638#define IL_SUPPORTED_RATES_IE_LEN 8
639
640#define MAX_TID_COUNT 9
641
642#define IL_INVALID_RATE 0xFF
643#define IL_INVALID_VALUE -1
644
645/**
646 * struct il_ht_agg -- aggregation status while waiting for block-ack
647 * @txq_id: Tx queue used for Tx attempt
648 * @frame_count: # frames attempted by Tx command
649 * @wait_for_ba: Expect block-ack before next Tx reply
650 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
651 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
652 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
653 * @rate_n_flags: Rate at which Tx was attempted
654 *
655 * If C_TX indicates that aggregation was attempted, driver must wait
656 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
657 * until block ack arrives.
658 */
659struct il_ht_agg {
660 u16 txq_id;
661 u16 frame_count;
662 u16 wait_for_ba;
663 u16 start_idx;
664 u64 bitmap;
665 u32 rate_n_flags;
666#define IL_AGG_OFF 0
667#define IL_AGG_ON 1
668#define IL_EMPTYING_HW_QUEUE_ADDBA 2
669#define IL_EMPTYING_HW_QUEUE_DELBA 3
670 u8 state;
671};
672
e94a4099 673struct il_tid_data {
e7392364 674 u16 seq_number; /* 4965 only */
e94a4099
SG		 675 u16 tfds_in_queue;
676 struct il_ht_agg agg;
677};
678
679struct il_hw_key {
680 u32 cipher;
681 int keylen;
682 u8 keyidx;
683 u8 key[32];
684};
685
686union il_ht_rate_supp {
687 u16 rates;
688 struct {
689 u8 siso_rate;
690 u8 mimo_rate;
691 };
692};
693
694#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
695#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
696#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
697#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
698#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
699#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
700#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
701
702/*
703 * Maximal MPDU density for TX aggregation
704 * 4 - 2us density
705 * 5 - 4us density
706 * 6 - 8us density
707 * 7 - 16us density
708 */
709#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
710#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
711#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
712#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
713#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
714#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
715#define CFG_HT_MPDU_DENSITY_MIN (0x1)
716
717struct il_ht_config {
718 bool single_chain_sufficient;
e7392364 719 enum ieee80211_smps_mode smps; /* current smps mode */
e94a4099
SG		 720};
721
722/* QoS structures */
723struct il_qos_info {
724 int qos_active;
725 struct il_qosparam_cmd def_qos_parm;
726};
727
728/*
729 * Structure should be accessed with sta_lock held. When station addition
730 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
731 * the commands (il_addsta_cmd and il_link_quality_cmd) without
732 * sta_lock held.
733 */
734struct il_station_entry {
735 struct il_addsta_cmd sta;
736 struct il_tid_data tid[MAX_TID_COUNT];
6aa0c254 737 u8 used;
e94a4099
SG		 738 struct il_hw_key keyinfo;
739 struct il_link_quality_cmd *lq;
740};
741
742struct il_station_priv_common {
e94a4099
SG		 743 u8 sta_id;
744};
745
e94a4099
SG		 746/**
747 * struct il_vif_priv - driver's ilate per-interface information
748 *
749 * When mac80211 allocates a virtual interface, it can allocate
750 * space for us to put data into.
751 */
752struct il_vif_priv {
e94a4099
SG		 753 u8 ibss_bssid_sta_id;
754};
755
756/* one for each uCode image (inst/data, boot/init/runtime) */
757struct fw_desc {
758 void *v_addr; /* access by driver */
759 dma_addr_t p_addr; /* access by card's busmaster DMA */
760 u32 len; /* bytes */
761};
762
763/* uCode file layout */
764struct il_ucode_header {
e7392364 765 __le32 ver; /* major/minor/API/serial */
e94a4099
SG		 766 struct {
767 __le32 inst_size; /* bytes of runtime code */
768 __le32 data_size; /* bytes of runtime data */
769 __le32 init_size; /* bytes of init code */
770 __le32 init_data_size; /* bytes of init data */
771 __le32 boot_size; /* bytes of bootstrap code */
e7392364 772 u8 data[0]; /* in same order as sizes */
e94a4099
SG		 773 } v1;
774};
775
776struct il4965_ibss_seq {
777 u8 mac[ETH_ALEN];
778 u16 seq_num;
779 u16 frag_num;
780 unsigned long packet_time;
781 struct list_head list;
782};
783
784struct il_sensitivity_ranges {
785 u16 min_nrg_cck;
786 u16 max_nrg_cck;
787
788 u16 nrg_th_cck;
789 u16 nrg_th_ofdm;
790
791 u16 auto_corr_min_ofdm;
792 u16 auto_corr_min_ofdm_mrc;
793 u16 auto_corr_min_ofdm_x1;
794 u16 auto_corr_min_ofdm_mrc_x1;
795
796 u16 auto_corr_max_ofdm;
797 u16 auto_corr_max_ofdm_mrc;
798 u16 auto_corr_max_ofdm_x1;
799 u16 auto_corr_max_ofdm_mrc_x1;
800
801 u16 auto_corr_max_cck;
802 u16 auto_corr_max_cck_mrc;
803 u16 auto_corr_min_cck;
804 u16 auto_corr_min_cck_mrc;
805
806 u16 barker_corr_th_min;
807 u16 barker_corr_th_min_mrc;
808 u16 nrg_th_cca;
809};
810
e94a4099
SG		 811#define KELVIN_TO_CELSIUS(x) ((x)-273)
812#define CELSIUS_TO_KELVIN(x) ((x)+273)
813
e94a4099
SG		 814/**
815 * struct il_hw_params
b16db50a 816 * @bcast_id: f/w broadcast station ID
e94a4099
SG		 817 * @max_txq_num: Max # Tx queues supported
818 * @dma_chnl_num: Number of Tx DMA/FIFO channels
819 * @scd_bc_tbls_size: size of scheduler byte count tables
820 * @tfd_size: TFD size
821 * @tx/rx_chains_num: Number of TX/RX chains
822 * @valid_tx/rx_ant: usable antennas
823 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
824 * @max_rxq_log: Log-base-2 of max_rxq_size
825 * @rx_page_order: Rx buffer page order
826 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
827 * @max_stations:
828 * @ht40_channel: is 40MHz width possible in band 2.4
829 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
830 * @sw_crypto: 0 for hw, 1 for sw
831 * @max_xxx_size: for ucode uses
832 * @ct_kill_threshold: temperature threshold
833 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
834 * @struct il_sensitivity_ranges: range of sensitivity values
835 */
836struct il_hw_params {
b16db50a 837 u8 bcast_id;
e94a4099
SG		 838 u8 max_txq_num;
839 u8 dma_chnl_num;
840 u16 scd_bc_tbls_size;
841 u32 tfd_size;
e7392364
SG		 842 u8 tx_chains_num;
843 u8 rx_chains_num;
844 u8 valid_tx_ant;
845 u8 valid_rx_ant;
e94a4099
SG		 846 u16 max_rxq_size;
847 u16 max_rxq_log;
848 u32 rx_page_order;
849 u32 rx_wrt_ptr_reg;
e7392364
SG		 850 u8 max_stations;
851 u8 ht40_channel;
852 u8 max_beacon_itrvl; /* in 1024 ms */
e94a4099
SG		 853 u32 max_inst_size;
854 u32 max_data_size;
855 u32 max_bsm_size;
e7392364 856 u32 ct_kill_threshold; /* value in hw-dependent units */
e94a4099
SG		 857 u16 beacon_time_tsf_bits;
858 const struct il_sensitivity_ranges *sens;
859};
860
e94a4099
SG		 861/******************************************************************************
862 *
863 * Functions implemented in core module which are forward declared here
864 * for use by iwl-[4-5].c
865 *
866 * NOTE: The implementation of these functions are not hardware specific
867 * which is why they are in the core module files.
868 *
869 * Naming convention --
870 * il_ <-- Is part of iwlwifi
871 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
872 * il4965_bg_ <-- Called from work queue context
873 * il4965_mac_ <-- mac80211 callback
874 *
875 ****************************************************************************/
876extern void il4965_update_chain_flags(struct il_priv *il);
877extern const u8 il_bcast_addr[ETH_ALEN];
878extern int il_queue_space(const struct il_queue *q);
e7392364
SG		 879static inline int
880il_queue_used(const struct il_queue *q, int i)
e94a4099 881{
e7392364
SG		 882 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
883 i < q->write_ptr) : !(i <
884 q->read_ptr
885 && i >=
886 q->
887 write_ptr);
e94a4099
SG		 888}
889
e7392364
SG		 890static inline u8
891il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
e94a4099
SG		 892{
893 /*
894 * This is for init calibration result and scan command which
895 * required buffer > TFD_MAX_PAYLOAD_SIZE,
896 * the big buffer at end of command array
897 */
898 if (is_huge)
899 return q->n_win; /* must be power of 2 */
900
901 /* Otherwise, use normal size buffers */
902 return idx & (q->n_win - 1);
903}
904
e94a4099
SG		 905struct il_dma_ptr {
906 dma_addr_t dma;
907 void *addr;
908 size_t size;
909};
910
911#define IL_OPERATION_MODE_AUTO 0
912#define IL_OPERATION_MODE_HT_ONLY 1
913#define IL_OPERATION_MODE_MIXED 2
914#define IL_OPERATION_MODE_20MHZ 3
915
916#define IL_TX_CRC_SIZE 4
917#define IL_TX_DELIMITER_SIZE 4
918
919#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
920
921/* Sensitivity and chain noise calibration */
922#define INITIALIZATION_VALUE 0xFFFF
923#define IL4965_CAL_NUM_BEACONS 20
924#define IL_CAL_NUM_BEACONS 16
925#define MAXIMUM_ALLOWED_PATHLOSS 15
926
927#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
928
929#define MAX_FA_OFDM 50
930#define MIN_FA_OFDM 5
931#define MAX_FA_CCK 50
932#define MIN_FA_CCK 5
933
934#define AUTO_CORR_STEP_OFDM 1
935
936#define AUTO_CORR_STEP_CCK 3
937#define AUTO_CORR_MAX_TH_CCK 160
938
939#define NRG_DIFF 2
940#define NRG_STEP_CCK 2
941#define NRG_MARGIN 8
942#define MAX_NUMBER_CCK_NO_FA 100
943
944#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
945
946#define CHAIN_A 0
947#define CHAIN_B 1
948#define CHAIN_C 2
949#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
950#define ALL_BAND_FILTER 0xFF00
951#define IN_BAND_FILTER 0xFF
952#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
953
954#define NRG_NUM_PREV_STAT_L 20
955#define NUM_RX_CHAINS 3
956
957enum il4965_false_alarm_state {
958 IL_FA_TOO_MANY = 0,
959 IL_FA_TOO_FEW = 1,
960 IL_FA_GOOD_RANGE = 2,
961};
962
963enum il4965_chain_noise_state {
e7392364 964 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
e94a4099
SG		 965 IL_CHAIN_NOISE_ACCUMULATE,
966 IL_CHAIN_NOISE_CALIBRATED,
967 IL_CHAIN_NOISE_DONE,
968};
969
970enum il4965_calib_enabled_state {
e7392364 971 IL_CALIB_DISABLED = 0, /* must be 0 */
e94a4099
SG		 972 IL_CALIB_ENABLED = 1,
973};
974
975/*
976 * enum il_calib
977 * defines the order in which results of initial calibrations
978 * should be sent to the runtime uCode
979 */
980enum il_calib {
981 IL_CALIB_MAX,
982};
983
984/* Opaque calibration results */
985struct il_calib_result {
986 void *buf;
987 size_t buf_len;
988};
989
990enum ucode_type {
991 UCODE_NONE = 0,
992 UCODE_INIT,
993 UCODE_RT
994};
995
996/* Sensitivity calib data */
997struct il_sensitivity_data {
998 u32 auto_corr_ofdm;
999 u32 auto_corr_ofdm_mrc;
1000 u32 auto_corr_ofdm_x1;
1001 u32 auto_corr_ofdm_mrc_x1;
1002 u32 auto_corr_cck;
1003 u32 auto_corr_cck_mrc;
1004
1005 u32 last_bad_plcp_cnt_ofdm;
1006 u32 last_fa_cnt_ofdm;
1007 u32 last_bad_plcp_cnt_cck;
1008 u32 last_fa_cnt_cck;
1009
1010 u32 nrg_curr_state;
1011 u32 nrg_prev_state;
1012 u32 nrg_value[10];
e7392364 1013 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
e94a4099
SG		 1014 u32 nrg_silence_ref;
1015 u32 nrg_energy_idx;
1016 u32 nrg_silence_idx;
1017 u32 nrg_th_cck;
1018 s32 nrg_auto_corr_silence_diff;
1019 u32 num_in_cck_no_fa;
1020 u32 nrg_th_ofdm;
1021
1022 u16 barker_corr_th_min;
1023 u16 barker_corr_th_min_mrc;
1024 u16 nrg_th_cca;
1025};
1026
1027/* Chain noise (differential Rx gain) calib data */
1028struct il_chain_noise_data {
1029 u32 active_chains;
1030 u32 chain_noise_a;
1031 u32 chain_noise_b;
1032 u32 chain_noise_c;
1033 u32 chain_signal_a;
1034 u32 chain_signal_b;
1035 u32 chain_signal_c;
1036 u16 beacon_count;
1037 u8 disconn_array[NUM_RX_CHAINS];
1038 u8 delta_gain_code[NUM_RX_CHAINS];
1039 u8 radio_write;
1040 u8 state;
1041};
1042
e7392364 1043#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
e94a4099
SG		 1044#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1045
1046#define IL_TRAFFIC_ENTRIES (256)
1047#define IL_TRAFFIC_ENTRY_SIZE (64)
1048
1049enum {
1050 MEASUREMENT_READY = (1 << 0),
1051 MEASUREMENT_ACTIVE = (1 << 1),
1052};
1053
1054/* interrupt stats */
1055struct isr_stats {
1056 u32 hw;
1057 u32 sw;
1058 u32 err_code;
1059 u32 sch;
1060 u32 alive;
1061 u32 rfkill;
1062 u32 ctkill;
1063 u32 wakeup;
1064 u32 rx;
1065 u32 handlers[IL_CN_MAX];
1066 u32 tx;
1067 u32 unhandled;
1068};
1069
1070/* management stats */
1071enum il_mgmt_stats {
1072 MANAGEMENT_ASSOC_REQ = 0,
1073 MANAGEMENT_ASSOC_RESP,
1074 MANAGEMENT_REASSOC_REQ,
1075 MANAGEMENT_REASSOC_RESP,
1076 MANAGEMENT_PROBE_REQ,
1077 MANAGEMENT_PROBE_RESP,
1078 MANAGEMENT_BEACON,
1079 MANAGEMENT_ATIM,
1080 MANAGEMENT_DISASSOC,
1081 MANAGEMENT_AUTH,
1082 MANAGEMENT_DEAUTH,
1083 MANAGEMENT_ACTION,
1084 MANAGEMENT_MAX,
1085};
1086/* control stats */
1087enum il_ctrl_stats {
e7392364 1088 CONTROL_BACK_REQ = 0,
e94a4099
SG		 1089 CONTROL_BACK,
1090 CONTROL_PSPOLL,
1091 CONTROL_RTS,
1092 CONTROL_CTS,
1093 CONTROL_ACK,
1094 CONTROL_CFEND,
1095 CONTROL_CFENDACK,
1096 CONTROL_MAX,
1097};
1098
1099struct traffic_stats {
1100#ifdef CONFIG_IWLEGACY_DEBUGFS
1101 u32 mgmt[MANAGEMENT_MAX];
1102 u32 ctrl[CONTROL_MAX];
1103 u32 data_cnt;
1104 u64 data_bytes;
1105#endif
1106};
1107
1108/*
1109 * host interrupt timeout value
1110 * used with setting interrupt coalescing timer
1111 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1112 *
1113 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1114 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1115 */
1116#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1117#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1118#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1119#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1120#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1121#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1122
1123#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1124
1125/* TX queue watchdog timeouts in mSecs */
1126#define IL_DEF_WD_TIMEOUT (2000)
1127#define IL_LONG_WD_TIMEOUT (10000)
1128#define IL_MAX_WD_TIMEOUT (120000)
1129
1130struct il_force_reset {
1131 int reset_request_count;
1132 int reset_success_count;
1133 int reset_reject_count;
1134 unsigned long reset_duration;
1135 unsigned long last_force_reset_jiffies;
1136};
1137
1138/* extend beacon time format bit shifting */
1139/*
1140 * for _3945 devices
1141 * bits 31:24 - extended
1142 * bits 23:0 - interval
1143 */
1144#define IL3945_EXT_BEACON_TIME_POS 24
1145/*
1146 * for _4965 devices
1147 * bits 31:22 - extended
1148 * bits 21:0 - interval
1149 */
1150#define IL4965_EXT_BEACON_TIME_POS 22
1151
1152struct il_rxon_context {
1153 struct ieee80211_vif *vif;
e94a4099
SG		 1154};
1155
99412002
SG		 1156struct il_power_mgr {
1157 struct il_powertable_cmd sleep_cmd;
1158 struct il_powertable_cmd sleep_cmd_next;
1159 int debug_sleep_level_override;
1160 bool pci_pm;
1161};
1162
e94a4099
SG		 1163struct il_priv {
1164
1165 /* ieee device used by generic ieee processing code */
1166 struct ieee80211_hw *hw;
1167 struct ieee80211_channel *ieee_channels;
1168 struct ieee80211_rate *ieee_rates;
1169 struct il_cfg *cfg;
c39ae9fd 1170 const struct il_ops *ops;
e94a4099
SG		 1171
1172 /* temporary frame storage list */
1173 struct list_head free_frames;
1174 int frames_count;
1175
1176 enum ieee80211_band band;
1177 int alloc_rxb_page;
1178
1722f8e1
SG		 1179 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1180 struct il_rx_buf *rxb);
e94a4099
SG		 1181
1182 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1183
1184 /* spectrum measurement report caching */
1185 struct il_spectrum_notification measure_report;
1186 u8 measurement_status;
1187
1188 /* ucode beacon time */
1189 u32 ucode_beacon_time;
1190 int missed_beacon_threshold;
1191
1192 /* track IBSS manager (last beacon) status */
1193 u32 ibss_manager;
1194
1195 /* force reset */
1196 struct il_force_reset force_reset;
1197
1198 /* we allocate array of il_channel_info for NIC's valid channels.
1199 * Access via channel # using indirect idx array */
1200 struct il_channel_info *channel_info; /* channel info array */
1201 u8 channel_count; /* # of channels */
1202
1203 /* thermal calibration */
1204 s32 temperature; /* degrees Kelvin */
1205 s32 last_temperature;
1206
1207 /* init calibration results */
1208 struct il_calib_result calib_results[IL_CALIB_MAX];
1209
1210 /* Scan related variables */
1211 unsigned long scan_start;
1212 unsigned long scan_start_tsf;
1213 void *scan_cmd;
1214 enum ieee80211_band scan_band;
1215 struct cfg80211_scan_request *scan_request;
1216 struct ieee80211_vif *scan_vif;
1217 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1218 u8 mgmt_tx_ant;
1219
1220 /* spinlock */
1221 spinlock_t lock; /* protect general shared data */
1222 spinlock_t hcmd_lock; /* protect hcmd */
1223 spinlock_t reg_lock; /* protect hw register access */
1224 struct mutex mutex;
1225
1226 /* basic pci-network driver stuff */
1227 struct pci_dev *pci_dev;
1228
1229 /* pci hardware address support */
1230 void __iomem *hw_base;
e7392364
SG		 1231 u32 hw_rev;
1232 u32 hw_wa_rev;
1233 u8 rev_id;
e94a4099
SG		 1234
1235 /* command queue number */
1236 u8 cmd_queue;
1237
1238 /* max number of station keys */
1239 u8 sta_key_max_num;
1240
1241 /* EEPROM MAC addresses */
1242 struct mac_address addresses[1];
1243
1244 /* uCode images, save to reload in case of failure */
e7392364
SG		 1245 int fw_idx; /* firmware we're trying to load */
1246 u32 ucode_ver; /* version of ucode, copy of
1247 il_ucode.ver */
e94a4099
SG		 1248 struct fw_desc ucode_code; /* runtime inst */
1249 struct fw_desc ucode_data; /* runtime data original */
1250 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1251 struct fw_desc ucode_init; /* initialization inst */
1252 struct fw_desc ucode_init_data; /* initialization data */
1253 struct fw_desc ucode_boot; /* bootstrap inst */
1254 enum ucode_type ucode_type;
1255 u8 ucode_write_complete; /* the image write is complete */
1256 char firmware_name[25];
1257
83007196 1258 struct ieee80211_vif *vif;
e94a4099 1259
8d44f2bd
SG		 1260 struct il_qos_info qos_data;
1261
1c03c462
SG		 1262 struct {
1263 bool enabled;
1264 bool is_40mhz;
1265 bool non_gf_sta_present;
1266 u8 protection;
1267 u8 extension_chan_offset;
1268 } ht;
1269
c8b03958
SG		 1270 /*
1271 * We declare this const so it can only be
1272 * changed via explicit cast within the
1273 * routines that actually update the physical
1274 * hardware.
1275 */
1276 const struct il_rxon_cmd active;
1277 struct il_rxon_cmd staging;
1278
1279 struct il_rxon_time_cmd timing;
1280
e94a4099
SG		 1281 __le16 switch_channel;
1282
1283 /* 1st responses from initialize and runtime uCode images.
1284 * _4965's initialize alive response contains some calibration data. */
1285 struct il_init_alive_resp card_alive_init;
1286 struct il_alive_resp card_alive;
1287
1288 u16 active_rate;
1289
1290 u8 start_calib;
1291 struct il_sensitivity_data sensitivity_data;
1292 struct il_chain_noise_data chain_noise_data;
1293 __le16 sensitivity_tbl[HD_TBL_SIZE];
1294
1295 struct il_ht_config current_ht_config;
1296
1297 /* Rate scaling data */
1298 u8 retry_rate;
1299
1300 wait_queue_head_t wait_command_queue;
1301
1302 int activity_timer_active;
1303
1304 /* Rx and Tx DMA processing queues */
1305 struct il_rx_queue rxq;
1306 struct il_tx_queue *txq;
1307 unsigned long txq_ctx_active_msk;
e7392364
SG		 1308 struct il_dma_ptr kw; /* keep warm address */
1309 struct il_dma_ptr scd_bc_tbls;
e94a4099
SG		 1310
1311 u32 scd_base_addr; /* scheduler sram base address */
1312
1313 unsigned long status;
1314
1315 /* counts mgmt, ctl, and data packets */
1316 struct traffic_stats tx_stats;
1317 struct traffic_stats rx_stats;
1318
1319 /* counts interrupts */
1320 struct isr_stats isr_stats;
1321
1322 struct il_power_mgr power_data;
1323
1324 /* context information */
e7392364 1325 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
e94a4099
SG		 1326
1327 /* station table variables */
1328
1329 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1330 spinlock_t sta_lock;
1331 int num_stations;
1332 struct il_station_entry stations[IL_STATION_COUNT];
1333 unsigned long ucode_key_table;
1334
1335 /* queue refcounts */
1336#define IL_MAX_HW_QUEUES 32
1337 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1338 /* for each AC */
1339 atomic_t queue_stop_count[4];
1340
1341 /* Indication if ieee80211_ops->open has been called */
1342 u8 is_open;
1343
1344 u8 mac80211_registered;
1345
1346 /* eeprom -- this is in the card's little endian byte order */
1347 u8 *eeprom;
1348 struct il_eeprom_calib_info *calib_info;
1349
1350 enum nl80211_iftype iw_mode;
1351
1352 /* Last Rx'd beacon timestamp */
1353 u64 timestamp;
1354
1355 union {
1356#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1357 struct {
1358 void *shared_virt;
1359 dma_addr_t shared_phys;
1360
1361 struct delayed_work thermal_periodic;
1362 struct delayed_work rfkill_poll;
1363
1364 struct il3945_notif_stats stats;
1365#ifdef CONFIG_IWLEGACY_DEBUGFS
1366 struct il3945_notif_stats accum_stats;
1367 struct il3945_notif_stats delta_stats;
1368 struct il3945_notif_stats max_delta;
1369#endif
1370
1371 u32 sta_supp_rates;
1372 int last_rx_rssi; /* From Rx packet stats */
1373
1374 /* Rx'd packet timing information */
1375 u32 last_beacon_time;
1376 u64 last_tsf;
1377
1378 /*
1379 * each calibration channel group in the
1380 * EEPROM has a derived clip setting for
1381 * each rate.
1382 */
1383 const struct il3945_clip_group clip_groups[5];
1384
1385 } _3945;
1386#endif
1387#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1388 struct {
1389 struct il_rx_phy_res last_phy_res;
1390 bool last_phy_res_valid;
1391
1392 struct completion firmware_loading_complete;
1393
1394 /*
1395 * chain noise reset and gain commands are the
1396 * two extra calibration commands follows the standard
1397 * phy calibration commands
1398 */
1399 u8 phy_calib_chain_noise_reset_cmd;
1400 u8 phy_calib_chain_noise_gain_cmd;
1401
d735f921
SG		 1402 u8 key_mapping_keys;
1403 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1404
e94a4099
SG		 1405 struct il_notif_stats stats;
1406#ifdef CONFIG_IWLEGACY_DEBUGFS
1407 struct il_notif_stats accum_stats;
1408 struct il_notif_stats delta_stats;
1409 struct il_notif_stats max_delta;
1410#endif
1411
1412 } _4965;
1413#endif
1414 };
1415
1416 struct il_hw_params hw_params;
1417
1418 u32 inta_mask;
1419
1420 struct workqueue_struct *workqueue;
1421
1422 struct work_struct restart;
1423 struct work_struct scan_completed;
1424 struct work_struct rx_replenish;
1425 struct work_struct abort_scan;
1426
83007196 1427 bool beacon_enabled;
e94a4099
SG		 1428 struct sk_buff *beacon_skb;
1429
1430 struct work_struct tx_flush;
1431
1432 struct tasklet_struct irq_tasklet;
1433
1434 struct delayed_work init_alive_start;
1435 struct delayed_work alive_start;
1436 struct delayed_work scan_check;
1437
1438 /* TX Power */
1439 s8 tx_power_user_lmt;
1440 s8 tx_power_device_lmt;
1441 s8 tx_power_next;
1442
e94a4099
SG		 1443#ifdef CONFIG_IWLEGACY_DEBUG
1444 /* debugging info */
e7392364
SG		 1445 u32 debug_level; /* per device debugging will override global
1446 il_debug_level if set */
1447#endif /* CONFIG_IWLEGACY_DEBUG */
e94a4099
SG		 1448#ifdef CONFIG_IWLEGACY_DEBUGFS
1449 /* debugfs */
1450 u16 tx_traffic_idx;
1451 u16 rx_traffic_idx;
1452 u8 *tx_traffic;
1453 u8 *rx_traffic;
1454 struct dentry *debugfs_dir;
1455 u32 dbgfs_sram_offset, dbgfs_sram_len;
1456 bool disable_ht40;
e7392364 1457#endif /* CONFIG_IWLEGACY_DEBUGFS */
e94a4099
SG		 1458
1459 struct work_struct txpower_work;
1460 u32 disable_sens_cal;
1461 u32 disable_chain_noise_cal;
1462 u32 disable_tx_power_cal;
1463 struct work_struct run_time_calib_work;
1464 struct timer_list stats_periodic;
1465 struct timer_list watchdog;
1466 bool hw_ready;
1467
1468 struct led_classdev led;
1469 unsigned long blink_on, blink_off;
1470 bool led_registered;
e7392364 1471}; /*il_priv */
e94a4099 1472
e7392364
SG		 1473static inline void
1474il_txq_ctx_activate(struct il_priv *il, int txq_id)
e94a4099
SG		 1475{
1476 set_bit(txq_id, &il->txq_ctx_active_msk);
1477}
1478
e7392364
SG		 1479static inline void
1480il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
e94a4099
SG		 1481{
1482 clear_bit(txq_id, &il->txq_ctx_active_msk);
1483}
1484
e94a4099 1485static inline struct ieee80211_hdr *
e7392364 1486il_tx_queue_get_hdr(struct il_priv *il, int txq_id, int idx)
e94a4099
SG		 1487{
1488 if (il->txq[txq_id].txb[idx].skb)
e7392364
SG		 1489 return (struct ieee80211_hdr *)il->txq[txq_id].txb[idx].skb->
1490 data;
e94a4099
SG		 1491 return NULL;
1492}
1493
e7392364
SG		 1494static inline int
1495il_is_associated(struct il_priv *il)
e94a4099 1496{
c8b03958 1497 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
e94a4099
SG		 1498}
1499
e7392364
SG		 1500static inline int
1501il_is_any_associated(struct il_priv *il)
e94a4099
SG		 1502{
1503 return il_is_associated(il);
1504}
1505
e7392364
SG		 1506static inline int
1507il_is_channel_valid(const struct il_channel_info *ch_info)
e94a4099
SG		 1508{
1509 if (ch_info == NULL)
1510 return 0;
1511 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1512}
1513
e7392364
SG		 1514static inline int
1515il_is_channel_radar(const struct il_channel_info *ch_info)
e94a4099
SG		 1516{
1517 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1518}
1519
e7392364
SG		 1520static inline u8
1521il_is_channel_a_band(const struct il_channel_info *ch_info)
e94a4099
SG		 1522{
1523 return ch_info->band == IEEE80211_BAND_5GHZ;
1524}
1525
1526static inline int
1527il_is_channel_passive(const struct il_channel_info *ch)
1528{
1529 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1530}
1531
1532static inline int
1533il_is_channel_ibss(const struct il_channel_info *ch)
1534{
1535 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1536}
be663ab6 1537
e94a4099
SG		 1538static inline void
1539__il_free_pages(struct il_priv *il, struct page *page)
1540{
1541 __free_pages(page, il->hw_params.rx_page_order);
1542 il->alloc_rxb_page--;
1543}
1544
e7392364
SG		 1545static inline void
1546il_free_pages(struct il_priv *il, unsigned long page)
e94a4099
SG		 1547{
1548 free_pages(page, il->hw_params.rx_page_order);
1549 il->alloc_rxb_page--;
1550}
be663ab6
WYG		 1551
1552#define IWLWIFI_VERSION "in-tree:"
1553#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1554#define DRV_AUTHOR "<ilw@linux.intel.com>"
1555
e2ebc833 1556#define IL_PCI_DEVICE(dev, subdev, cfg) \
be663ab6
WYG		 1557 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1558 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1559 .driver_data = (kernel_ulong_t)&(cfg)
1560
1561#define TIME_UNIT 1024
1562
e2ebc833
SG		 1563#define IL_SKU_G 0x1
1564#define IL_SKU_A 0x2
1565#define IL_SKU_N 0x8
be663ab6 1566
e2ebc833 1567#define IL_CMD(x) case x: return #x
be663ab6 1568
e94a4099 1569/* Size of one Rx buffer in host DRAM */
e7392364 1570#define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
e94a4099
SG		 1571#define IL_RX_BUF_SIZE_4K (4 * 1024)
1572#define IL_RX_BUF_SIZE_8K (8 * 1024)
1573
e2ebc833 1574struct il_hcmd_ops {
83007196
SG		 1575 int (*rxon_assoc) (struct il_priv *il);
1576 int (*commit_rxon) (struct il_priv *il);
1577 void (*set_rxon_chain) (struct il_priv *il);
be663ab6
WYG		 1578};
1579
e2ebc833 1580struct il_hcmd_utils_ops {
e7392364 1581 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1722f8e1
SG		 1582 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1583 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1584 void (*post_scan) (struct il_priv *il);
be663ab6
WYG		 1585};
1586
e2ebc833 1587struct il_apm_ops {
1722f8e1
SG		 1588 int (*init) (struct il_priv *il);
1589 void (*config) (struct il_priv *il);
be663ab6
WYG		 1590};
1591
9b5e2f46 1592#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1593struct il_debugfs_ops {
1722f8e1
SG		 1594 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1595 size_t count, loff_t *ppos);
1596 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1597 size_t count, loff_t *ppos);
1598 ssize_t(*general_stats_read) (struct file *file,
1599 char __user *user_buf, size_t count,
1600 loff_t *ppos);
be663ab6 1601};
9b5e2f46 1602#endif
be663ab6 1603
e2ebc833 1604struct il_temp_ops {
1722f8e1 1605 void (*temperature) (struct il_priv *il);
be663ab6
WYG		 1606};
1607
e2ebc833 1608struct il_lib_ops {
be663ab6 1609 /* set hw dependent parameters */
1722f8e1 1610 int (*set_hw_params) (struct il_priv *il);
be663ab6 1611 /* Handling TX */
1722f8e1
SG		 1612 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1613 struct il_tx_queue *txq,
e7392364 1614 u16 byte_cnt);
1722f8e1
SG		 1615 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1616 struct il_tx_queue *txq, dma_addr_t addr,
e7392364 1617 u16 len, u8 reset, u8 pad);
1722f8e1
SG		 1618 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1619 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
be663ab6 1620 /* setup Rx handler */
1722f8e1 1621 void (*handler_setup) (struct il_priv *il);
be663ab6 1622 /* alive notification after init uCode load */
1722f8e1 1623 void (*init_alive_start) (struct il_priv *il);
be663ab6 1624 /* check validity of rtc data address */
e7392364 1625 int (*is_valid_rtc_data_addr) (u32 addr);
be663ab6 1626 /* 1st ucode load */
1722f8e1 1627 int (*load_ucode) (struct il_priv *il);
1ba2f121 1628
1722f8e1
SG		 1629 void (*dump_nic_error_log) (struct il_priv *il);
1630 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1631 int (*set_channel_switch) (struct il_priv *il,
1632 struct ieee80211_channel_switch *ch_switch);
be663ab6 1633 /* power management */
e2ebc833 1634 struct il_apm_ops apm_ops;
be663ab6
WYG		 1635
1636 /* power */
1722f8e1
SG		 1637 int (*send_tx_power) (struct il_priv *il);
1638 void (*update_chain_flags) (struct il_priv *il);
be663ab6 1639
47ef694d 1640 /* eeprom operations */
e2ebc833 1641 struct il_eeprom_ops eeprom_ops;
be663ab6
WYG		 1642
1643 /* temperature */
e2ebc833 1644 struct il_temp_ops temp_ops;
be663ab6 1645
9b5e2f46 1646#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1647 struct il_debugfs_ops debugfs_ops;
9b5e2f46 1648#endif
be663ab6
WYG		 1649
1650};
1651
e2ebc833 1652struct il_led_ops {
1722f8e1 1653 int (*cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
be663ab6
WYG		 1654};
1655
e2ebc833 1656struct il_legacy_ops {
1722f8e1
SG		 1657 void (*post_associate) (struct il_priv *il);
1658 void (*config_ap) (struct il_priv *il);
be663ab6 1659 /* station management */
1722f8e1
SG		 1660 int (*update_bcast_stations) (struct il_priv *il);
1661 int (*manage_ibss_station) (struct il_priv *il,
1662 struct ieee80211_vif *vif, bool add);
be663ab6
WYG		 1663};
1664
e2ebc833
SG		 1665struct il_ops {
1666 const struct il_lib_ops *lib;
1667 const struct il_hcmd_ops *hcmd;
1668 const struct il_hcmd_utils_ops *utils;
1669 const struct il_led_ops *led;
1670 const struct il_nic_ops *nic;
1671 const struct il_legacy_ops *legacy;
be663ab6
WYG		 1672};
1673
e2ebc833 1674struct il_mod_params {
be663ab6
WYG		 1675 int sw_crypto; /* def: 0 = using hardware encryption */
1676 int disable_hw_scan; /* def: 0 = use h/w scan */
1677 int num_of_queues; /* def: HW dependent */
1678 int disable_11n; /* def: 0 = 11n capabilities enabled */
1679 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
e7392364 1680 int antenna; /* def: 0 = both antennas (use diversity) */
be663ab6
WYG		 1681 int restart_fw; /* def: 1 = restart firmware */
1682};
1683
1684/*
1685 * @led_compensation: compensate on the led on/off time per HW according
1686 * to the deviation to achieve the desired led frequency.
47ef694d 1687 * The detail algorithm is described in common.c
be663ab6 1688 * @chain_noise_num_beacons: number of beacons used to compute chain noise
be663ab6
WYG		 1689 * @wd_timeout: TX queues watchdog timeout
1690 * @temperature_kelvin: temperature report by uCode in kelvin
be663ab6
WYG		 1691 * @ucode_tracing: support ucode continuous tracing
1692 * @sensitivity_calib_by_driver: driver has the capability to perform
1693 * sensitivity calibration operation
1694 * @chain_noise_calib_by_driver: driver has the capability to perform
1695 * chain noise calibration operation
1696 */
e2ebc833 1697struct il_base_params {
be663ab6
WYG		 1698 int eeprom_size;
1699 int num_of_queues; /* def: HW dependent */
e7392364 1700 int num_of_ampdu_queues; /* def: HW dependent */
e2ebc833 1701 /* for il_apm_init() */
be663ab6
WYG		 1702 u32 pll_cfg_val;
1703 bool set_l0s;
1704 bool use_bsm;
1705
1706 u16 led_compensation;
1707 int chain_noise_num_beacons;
be663ab6
WYG		 1708 unsigned int wd_timeout;
1709 bool temperature_kelvin;
be663ab6
WYG		 1710 const bool ucode_tracing;
1711 const bool sensitivity_calib_by_driver;
1712 const bool chain_noise_calib_by_driver;
1713};
1714
47ef694d
SG		 1715#define IL_LED_SOLID 11
1716#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1717
1718#define IL_LED_ACTIVITY (0<<1)
1719#define IL_LED_LINK (1<<1)
1720
1721/*
1722 * LED mode
1723 * IL_LED_DEFAULT: use device default
1724 * IL_LED_RF_STATE: turn LED on/off based on RF state
1725 * LED ON = RF ON
1726 * LED OFF = RF OFF
1727 * IL_LED_BLINK: adjust led blink rate based on blink table
1728 */
1729enum il_led_mode {
1730 IL_LED_DEFAULT,
1731 IL_LED_RF_STATE,
1732 IL_LED_BLINK,
1733};
1734
1735void il_leds_init(struct il_priv *il);
1736void il_leds_exit(struct il_priv *il);
1737
be663ab6 1738/**
e2ebc833 1739 * struct il_cfg
be663ab6
WYG		 1740 * @fw_name_pre: Firmware filename prefix. The api version and extension
1741 * (.ucode) will be added to filename before loading from disk. The
1742 * filename is constructed as fw_name_pre<api>.ucode.
1743 * @ucode_api_max: Highest version of uCode API supported by driver.
1744 * @ucode_api_min: Lowest version of uCode API supported by driver.
1745 * @scan_antennas: available antenna for scan operation
1746 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1747 *
1748 * We enable the driver to be backward compatible wrt API version. The
1749 * driver specifies which APIs it supports (with @ucode_api_max being the
1750 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1751 * it has a supported API version. The firmware's API version will be
e2ebc833 1752 * stored in @il_priv, enabling the driver to make runtime changes based
be663ab6
WYG		 1753 * on firmware version used.
1754 *
1755 * For example,
46bc8d4b 1756 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
be663ab6
WYG		 1757 * Driver interacts with Firmware API version >= 2.
1758 * } else {
1759 * Driver interacts with Firmware API version 1.
1760 * }
1761 *
1762 * The ideal usage of this infrastructure is to treat a new ucode API
1763 * release as a new hardware revision. That is, through utilizing the
e2ebc833 1764 * il_hcmd_utils_ops etc. we accommodate different command structures
be663ab6
WYG		 1765 * and flows between hardware versions as well as their API
1766 * versions.
1767 *
1768 */
e2ebc833 1769struct il_cfg {
be663ab6
WYG		 1770 /* params specific to an individual device within a device family */
1771 const char *name;
1772 const char *fw_name_pre;
1773 const unsigned int ucode_api_max;
1774 const unsigned int ucode_api_min;
e7392364
SG		 1775 u8 valid_tx_ant;
1776 u8 valid_rx_ant;
be663ab6 1777 unsigned int sku;
e7392364
SG		 1778 u16 eeprom_ver;
1779 u16 eeprom_calib_ver;
be663ab6 1780 /* module based parameters which can be set from modprobe cmd */
e2ebc833 1781 const struct il_mod_params *mod_params;
be663ab6 1782 /* params not likely to change within a device family */
e2ebc833 1783 struct il_base_params *base_params;
be663ab6
WYG		 1784 /* params likely to change within a device family */
1785 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
e2ebc833 1786 enum il_led_mode led_mode;
be663ab6
WYG		 1787};
1788
1789/***************************
1790 * L i b *
1791 ***************************/
1792
e7392364
SG		 1793int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1794 u16 queue, const struct ieee80211_tx_queue_params *params);
e2ebc833 1795int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
e7392364 1796
83007196
SG		 1797void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1798int il_check_rxon_cmd(struct il_priv *il);
1799int il_full_rxon_required(struct il_priv *il);
1800int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1801void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
1802 struct ieee80211_vif *vif);
e7392364
SG		 1803u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1804void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
83007196 1805bool il_is_ht40_tx_allowed(struct il_priv *il,
e7392364 1806 struct ieee80211_sta_ht_cap *ht_cap);
83007196 1807void il_connection_init_rx_config(struct il_priv *il);
46bc8d4b 1808void il_set_rate(struct il_priv *il);
e7392364
SG		 1809int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1810 u32 decrypt_res, struct ieee80211_rx_status *stats);
46bc8d4b 1811void il_irq_handle_error(struct il_priv *il);
e7392364 1812int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
e2ebc833 1813void il_mac_remove_interface(struct ieee80211_hw *hw,
e7392364
SG		 1814 struct ieee80211_vif *vif);
1815int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1816 enum nl80211_iftype newtype, bool newp2p);
46bc8d4b
SG		 1817int il_alloc_txq_mem(struct il_priv *il);
1818void il_txq_mem(struct il_priv *il);
be663ab6 1819
d3175167 1820#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b
SG		 1821int il_alloc_traffic_mem(struct il_priv *il);
1822void il_free_traffic_mem(struct il_priv *il);
1823void il_reset_traffic_log(struct il_priv *il);
e7392364
SG		 1824void il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1825 struct ieee80211_hdr *header);
1826void il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1827 struct ieee80211_hdr *header);
e2ebc833
SG		 1828const char *il_get_mgmt_string(int cmd);
1829const char *il_get_ctrl_string(int cmd);
46bc8d4b 1830void il_clear_traffic_stats(struct il_priv *il);
e7392364 1831void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
be663ab6 1832#else
e7392364
SG		 1833static inline int
1834il_alloc_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1835{
1836 return 0;
1837}
e7392364
SG		 1838
1839static inline void
1840il_free_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1841{
1842}
e7392364
SG		 1843
1844static inline void
1845il_reset_traffic_log(struct il_priv *il)
be663ab6
WYG		 1846{
1847}
e7392364
SG		 1848
1849static inline void
1850il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1851 struct ieee80211_hdr *header)
be663ab6
WYG		 1852{
1853}
e7392364
SG		 1854
1855static inline void
1856il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1857 struct ieee80211_hdr *header)
be663ab6
WYG		 1858{
1859}
e7392364
SG		 1860
1861static inline void
1862il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6
WYG		 1863{
1864}
1865#endif
1866/*****************************************************
1867 * RX handlers.
1868 * **************************************************/
e7392364
SG		 1869void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1870void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1871void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1872
1873/*****************************************************
1874* RX
1875******************************************************/
46bc8d4b
SG		 1876void il_cmd_queue_unmap(struct il_priv *il);
1877void il_cmd_queue_free(struct il_priv *il);
1878int il_rx_queue_alloc(struct il_priv *il);
e7392364 1879void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
e2ebc833 1880int il_rx_queue_space(const struct il_rx_queue *q);
e7392364 1881void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6 1882/* Handlers */
e7392364
SG		 1883void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1884void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
46bc8d4b 1885void il_chswitch_done(struct il_priv *il, bool is_success);
d2dfb33e 1886void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1887
1888/* TX helpers */
1889
1890/*****************************************************
1891* TX
1892******************************************************/
e7392364
SG		 1893void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1894int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
1895 u32 txq_id);
1896void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
1897 int slots_num, u32 txq_id);
46bc8d4b
SG		 1898void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1899void il_tx_queue_free(struct il_priv *il, int txq_id);
1900void il_setup_watchdog(struct il_priv *il);
be663ab6
WYG		 1901/*****************************************************
1902 * TX power
1903 ****************************************************/
46bc8d4b 1904int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
be663ab6
WYG		 1905
1906/*******************************************************************************
1907 * Rate
1908 ******************************************************************************/
1909
83007196 1910u8 il_get_lowest_plcp(struct il_priv *il);
be663ab6
WYG		 1911
1912/*******************************************************************************
1913 * Scanning
1914 ******************************************************************************/
46bc8d4b
SG		 1915void il_init_scan_params(struct il_priv *il);
1916int il_scan_cancel(struct il_priv *il);
1917int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1918void il_force_scan_end(struct il_priv *il);
e7392364
SG		 1919int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1920 struct cfg80211_scan_request *req);
46bc8d4b
SG		 1921void il_internal_short_hw_scan(struct il_priv *il);
1922int il_force_reset(struct il_priv *il, bool external);
e7392364 1923u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1924 const u8 *ta, const u8 *ie, int ie_len, int left);
46bc8d4b 1925void il_setup_rx_scan_handlers(struct il_priv *il);
e7392364
SG		 1926u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1927 u8 n_probes);
1928u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1929 struct ieee80211_vif *vif);
46bc8d4b
SG		 1930void il_setup_scan_deferred_work(struct il_priv *il);
1931void il_cancel_scan_deferred_work(struct il_priv *il);
be663ab6
WYG		 1932
1933/* For faster active scanning, scan will move to the next channel if fewer than
1934 * PLCP_QUIET_THRESH packets are heard on this channel within
1935 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
1936 * time if it's a quiet channel (nothing responded to our probe, and there's
1937 * no other traffic).
1938 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
e7392364
SG		 1939#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
1940#define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
be663ab6 1941
e2ebc833 1942#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
be663ab6
WYG		 1943
1944/*****************************************************
1945 * S e n d i n g H o s t C o m m a n d s *
1946 *****************************************************/
1947
e2ebc833 1948const char *il_get_cmd_string(u8 cmd);
e7392364 1949int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
46bc8d4b 1950int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
e7392364
SG		 1951int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1952 const void *data);
1953int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 1954 void (*callback) (struct il_priv *il,
1955 struct il_device_cmd *cmd,
1956 struct il_rx_pkt *pkt));
be663ab6 1957
46bc8d4b 1958int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
be663ab6 1959
be663ab6
WYG		 1960/*****************************************************
1961 * PCI *
1962 *****************************************************/
1963
e7392364
SG		 1964static inline u16
1965il_pcie_link_ctl(struct il_priv *il)
be663ab6
WYG		 1966{
1967 int pos;
1968 u16 pci_lnk_ctl;
46bc8d4b
SG		 1969 pos = pci_pcie_cap(il->pci_dev);
1970 pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
be663ab6
WYG		 1971 return pci_lnk_ctl;
1972}
1973
e2ebc833 1974void il_bg_watchdog(unsigned long data);
e7392364
SG		 1975u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1976__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1977 u32 beacon_interval);
be663ab6
WYG		 1978
1979#ifdef CONFIG_PM
e2ebc833
SG		 1980int il_pci_suspend(struct device *device);
1981int il_pci_resume(struct device *device);
1982extern const struct dev_pm_ops il_pm_ops;
be663ab6 1983
e2ebc833 1984#define IL_LEGACY_PM_OPS (&il_pm_ops)
be663ab6
WYG		 1985
1986#else /* !CONFIG_PM */
1987
e2ebc833 1988#define IL_LEGACY_PM_OPS NULL
be663ab6
WYG		 1989
1990#endif /* !CONFIG_PM */
1991
1992/*****************************************************
1993* Error Handling Debugging
1994******************************************************/
46bc8d4b 1995void il4965_dump_nic_error_log(struct il_priv *il);
d3175167 1996#ifdef CONFIG_IWLEGACY_DEBUG
83007196 1997void il_print_rx_config_cmd(struct il_priv *il);
be663ab6 1998#else
e7392364 1999static inline void
83007196 2000il_print_rx_config_cmd(struct il_priv *il)
be663ab6
WYG		 2001{
2002}
2003#endif
2004
46bc8d4b 2005void il_clear_isr_stats(struct il_priv *il);
be663ab6
WYG		 2006
2007/*****************************************************
2008* GEOS
2009******************************************************/
46bc8d4b
SG		 2010int il_init_geos(struct il_priv *il);
2011void il_free_geos(struct il_priv *il);
be663ab6
WYG		 2012
2013/*************** DRIVER STATUS FUNCTIONS *****/
2014
a6766ccd
SG		 2015#define S_HCMD_ACTIVE 0 /* host command in progress */
2016/* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
2017#define S_INT_ENABLED 2
2018#define S_RF_KILL_HW 3
2019#define S_CT_KILL 4
2020#define S_INIT 5
2021#define S_ALIVE 6
2022#define S_READY 7
2023#define S_TEMPERATURE 8
2024#define S_GEO_CONFIGURED 9
2025#define S_EXIT_PENDING 10
db7746f7 2026#define S_STATS 12
a6766ccd
SG		 2027#define S_SCANNING 13
2028#define S_SCAN_ABORTING 14
2029#define S_SCAN_HW 15
2030#define S_POWER_PMI 16
2031#define S_FW_ERROR 17
2032#define S_CHANNEL_SWITCH_PENDING 18
be663ab6 2033
e7392364
SG		 2034static inline int
2035il_is_ready(struct il_priv *il)
be663ab6
WYG		 2036{
2037 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
2038 * set but EXIT_PENDING is not */
a6766ccd 2039 return test_bit(S_READY, &il->status) &&
e7392364
SG		 2040 test_bit(S_GEO_CONFIGURED, &il->status) &&
2041 !test_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 2042}
2043
e7392364
SG		 2044static inline int
2045il_is_alive(struct il_priv *il)
be663ab6 2046{
a6766ccd 2047 return test_bit(S_ALIVE, &il->status);
be663ab6
WYG		 2048}
2049
e7392364
SG		 2050static inline int
2051il_is_init(struct il_priv *il)
be663ab6 2052{
a6766ccd 2053 return test_bit(S_INIT, &il->status);
be663ab6
WYG		 2054}
2055
e7392364
SG		 2056static inline int
2057il_is_rfkill_hw(struct il_priv *il)
be663ab6 2058{
a6766ccd 2059 return test_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 2060}
2061
e7392364
SG		 2062static inline int
2063il_is_rfkill(struct il_priv *il)
be663ab6 2064{
46bc8d4b 2065 return il_is_rfkill_hw(il);
be663ab6
WYG		 2066}
2067
e7392364
SG		 2068static inline int
2069il_is_ctkill(struct il_priv *il)
be663ab6 2070{
a6766ccd 2071 return test_bit(S_CT_KILL, &il->status);
be663ab6
WYG		 2072}
2073
e7392364
SG		 2074static inline int
2075il_is_ready_rf(struct il_priv *il)
be663ab6
WYG		 2076{
2077
46bc8d4b 2078 if (il_is_rfkill(il))
be663ab6
WYG		 2079 return 0;
2080
46bc8d4b 2081 return il_is_ready(il);
be663ab6
WYG		 2082}
2083
46bc8d4b 2084extern void il_send_bt_config(struct il_priv *il);
e7392364 2085extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
46bc8d4b
SG		 2086void il_apm_stop(struct il_priv *il);
2087int il_apm_init(struct il_priv *il);
be663ab6 2088
83007196
SG		 2089int il_send_rxon_timing(struct il_priv *il);
2090
e7392364 2091static inline int
83007196 2092il_send_rxon_assoc(struct il_priv *il)
be663ab6 2093{
c39ae9fd 2094 return il->ops->hcmd->rxon_assoc(il);
be663ab6 2095}
e7392364
SG		 2096
2097static inline int
83007196 2098il_commit_rxon(struct il_priv *il)
be663ab6 2099{
c39ae9fd 2100 return il->ops->hcmd->commit_rxon(il);
be663ab6 2101}
e7392364
SG		 2102
2103static inline const struct ieee80211_supported_band *
2104il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
be663ab6 2105{
46bc8d4b 2106 return il->hw->wiphy->bands[band];
be663ab6
WYG		 2107}
2108
be663ab6 2109/* mac80211 handlers */
e2ebc833 2110int il_mac_config(struct ieee80211_hw *hw, u32 changed);
e7392364
SG		 2111void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
2112void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2113 struct ieee80211_bss_conf *bss_conf, u32 changes);
2114void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 2115 __le16 fc, __le32 *tx_flags);
be663ab6 2116
e2ebc833 2117irqreturn_t il_isr(int irq, void *data);
be663ab6 2118
17d4eca6
SG		 2119extern void il_set_bit(struct il_priv *p, u32 r, u32 m);
2120extern void il_clear_bit(struct il_priv *p, u32 r, u32 m);
2121extern int _il_grab_nic_access(struct il_priv *il);
2122extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
2123extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
2124extern u32 il_rd_prph(struct il_priv *il, u32 reg);
2125extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
2126extern u32 il_read_targ_mem(struct il_priv *il, u32 addr);
2127extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
e94a4099 2128
e7392364
SG		 2129static inline void
2130_il_write8(struct il_priv *il, u32 ofs, u8 val)
e94a4099
SG		 2131{
2132 iowrite8(val, il->hw_base + ofs);
2133}
2134#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2135
e7392364
SG		 2136static inline void
2137_il_wr(struct il_priv *il, u32 ofs, u32 val)
e94a4099
SG		 2138{
2139 iowrite32(val, il->hw_base + ofs);
2140}
2141
e7392364
SG		 2142static inline u32
2143_il_rd(struct il_priv *il, u32 ofs)
e94a4099
SG		 2144{
2145 return ioread32(il->hw_base + ofs);
2146}
2147
e94a4099
SG		 2148static inline void
2149_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2150{
2151 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2152}
2153
e7392364 2154static inline void
17d4eca6 2155_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
e94a4099 2156{
17d4eca6 2157 _il_wr(il, reg, _il_rd(il, reg) | mask);
e94a4099
SG		 2158}
2159
e7392364
SG		 2160static inline void
2161_il_release_nic_access(struct il_priv *il)
e94a4099 2162{
e7392364 2163 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
e94a4099
SG		 2164}
2165
e7392364
SG		 2166static inline u32
2167il_rd(struct il_priv *il, u32 reg)
e94a4099
SG		 2168{
2169 u32 value;
2170 unsigned long reg_flags;
2171
2172 spin_lock_irqsave(&il->reg_lock, reg_flags);
2173 _il_grab_nic_access(il);
2174 value = _il_rd(il, reg);
2175 _il_release_nic_access(il);
2176 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2177 return value;
e94a4099
SG		 2178}
2179
2180static inline void
2181il_wr(struct il_priv *il, u32 reg, u32 value)
2182{
2183 unsigned long reg_flags;
2184
2185 spin_lock_irqsave(&il->reg_lock, reg_flags);
2186 if (!_il_grab_nic_access(il)) {
2187 _il_wr(il, reg, value);
2188 _il_release_nic_access(il);
2189 }
2190 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2191}
2192
e7392364
SG		 2193static inline u32
2194_il_rd_prph(struct il_priv *il, u32 reg)
e94a4099
SG		 2195{
2196 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2197 rmb();
2198 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2199}
2200
e7392364
SG		 2201static inline void
2202_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
e94a4099 2203{
e7392364 2204 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
e94a4099
SG		 2205 wmb();
2206 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2207}
2208
e94a4099
SG		 2209static inline void
2210il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2211{
2212 unsigned long reg_flags;
2213
2214 spin_lock_irqsave(&il->reg_lock, reg_flags);
2215 _il_grab_nic_access(il);
17d4eca6 2216 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
e94a4099
SG		 2217 _il_release_nic_access(il);
2218 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2219}
2220
e7392364
SG		 2221static inline void
2222il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
e94a4099
SG		 2223{
2224 unsigned long reg_flags;
2225
2226 spin_lock_irqsave(&il->reg_lock, reg_flags);
2227 _il_grab_nic_access(il);
17d4eca6 2228 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
e94a4099
SG		 2229 _il_release_nic_access(il);
2230 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2231}
2232
e7392364
SG		 2233static inline void
2234il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
e94a4099
SG		 2235{
2236 unsigned long reg_flags;
2237 u32 val;
2238
2239 spin_lock_irqsave(&il->reg_lock, reg_flags);
2240 _il_grab_nic_access(il);
2241 val = _il_rd_prph(il, reg);
2242 _il_wr_prph(il, reg, (val & ~mask));
2243 _il_release_nic_access(il);
2244 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2245}
2246
e94a4099
SG		 2247#define HW_KEY_DYNAMIC 0
2248#define HW_KEY_DEFAULT 1
2249
e7392364
SG		 2250#define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2251#define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2252#define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2253 being activated */
2254#define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2255 (this is for the IBSS BSSID stations) */
2256#define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
e94a4099 2257
83007196
SG		 2258void il_restore_stations(struct il_priv *il);
2259void il_clear_ucode_stations(struct il_priv *il);
e94a4099
SG		 2260void il_dealloc_bcast_stations(struct il_priv *il);
2261int il_get_free_ucode_key_idx(struct il_priv *il);
e7392364 2262int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
83007196 2263int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
1722f8e1 2264 struct ieee80211_sta *sta, u8 *sta_id_r);
e7392364
SG		 2265int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2266int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2267 struct ieee80211_sta *sta);
2268
83007196
SG		 2269u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2270 struct ieee80211_sta *sta);
e7392364 2271
83007196
SG		 2272int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2273 u8 flags, bool init);
e94a4099
SG		 2274
2275/**
2276 * il_clear_driver_stations - clear knowledge of all stations from driver
2277 * @il: iwl il struct
2278 *
2279 * This is called during il_down() to make sure that in the case
2280 * we're coming there from a hardware restart mac80211 will be
2281 * able to reconfigure stations -- if we're getting there in the
2282 * normal down flow then the stations will already be cleared.
2283 */
e7392364
SG		 2284static inline void
2285il_clear_driver_stations(struct il_priv *il)
e94a4099
SG		 2286{
2287 unsigned long flags;
e94a4099
SG		 2288
2289 spin_lock_irqsave(&il->sta_lock, flags);
2290 memset(il->stations, 0, sizeof(il->stations));
2291 il->num_stations = 0;
e94a4099 2292 il->ucode_key_table = 0;
e94a4099
SG		 2293 spin_unlock_irqrestore(&il->sta_lock, flags);
2294}
2295
e7392364
SG		 2296static inline int
2297il_sta_id(struct ieee80211_sta *sta)
e94a4099
SG		 2298{
2299 if (WARN_ON(!sta))
2300 return IL_INVALID_STATION;
2301
2302 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2303}
2304
2305/**
2306 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2307 * @il: iwl il
2308 * @context: the current context
2309 * @sta: mac80211 station
2310 *
2311 * In certain circumstances mac80211 passes a station pointer
2312 * that may be %NULL, for example during TX or key setup. In
2313 * that case, we need to use the broadcast station, so this
2314 * inline wraps that pattern.
2315 */
e7392364 2316static inline int
83007196 2317il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
e94a4099
SG		 2318{
2319 int sta_id;
2320
2321 if (!sta)
b16db50a 2322 return il->hw_params.bcast_id;
e94a4099
SG		 2323
2324 sta_id = il_sta_id(sta);
2325
2326 /*
2327 * mac80211 should not be passing a partially
2328 * initialised station!
2329 */
2330 WARN_ON(sta_id == IL_INVALID_STATION);
2331
2332 return sta_id;
2333}
2334
2335/**
2336 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2337 * @idx -- current idx
2338 * @n_bd -- total number of entries in queue (must be power of 2)
2339 */
e7392364
SG		 2340static inline int
2341il_queue_inc_wrap(int idx, int n_bd)
e94a4099
SG		 2342{
2343 return ++idx & (n_bd - 1);
2344}
2345
2346/**
2347 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2348 * @idx -- current idx
2349 * @n_bd -- total number of entries in queue (must be power of 2)
2350 */
e7392364
SG		 2351static inline int
2352il_queue_dec_wrap(int idx, int n_bd)
e94a4099
SG		 2353{
2354 return --idx & (n_bd - 1);
2355}
2356
2357/* TODO: Move fw_desc functions to iwl-pci.ko */
e7392364
SG		 2358static inline void
2359il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2360{
2361 if (desc->v_addr)
e7392364
SG		 2362 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2363 desc->p_addr);
e94a4099
SG		 2364 desc->v_addr = NULL;
2365 desc->len = 0;
2366}
2367
e7392364
SG		 2368static inline int
2369il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2370{
2371 if (!desc->len) {
2372 desc->v_addr = NULL;
2373 return -EINVAL;
2374 }
2375
e7392364
SG		 2376 desc->v_addr =
2377 dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2378 GFP_KERNEL);
e94a4099
SG		 2379 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2380}
2381
2382/*
2383 * we have 8 bits used like this:
2384 *
2385 * 7 6 5 4 3 2 1 0
2386 * | | | | | | | |
2387 * | | | | | | +-+-------- AC queue (0-3)
2388 * | | | | | |
2389 * | +-+-+-+-+------------ HW queue ID
2390 * |
2391 * +---------------------- unused
2392 */
2393static inline void
2394il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2395{
e7392364
SG		 2396 BUG_ON(ac > 3); /* only have 2 bits */
2397 BUG_ON(hwq > 31); /* only use 5 bits */
e94a4099
SG		 2398
2399 txq->swq_id = (hwq << 2) | ac;
2400}
2401
e7392364
SG		 2402static inline void
2403il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2404{
2405 u8 queue = txq->swq_id;
2406 u8 ac = queue & 3;
2407 u8 hwq = (queue >> 2) & 0x1f;
2408
2409 if (test_and_clear_bit(hwq, il->queue_stopped))
2410 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2411 ieee80211_wake_queue(il->hw, ac);
2412}
2413
e7392364
SG		 2414static inline void
2415il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2416{
2417 u8 queue = txq->swq_id;
2418 u8 ac = queue & 3;
2419 u8 hwq = (queue >> 2) & 0x1f;
2420
2421 if (!test_and_set_bit(hwq, il->queue_stopped))
2422 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2423 ieee80211_stop_queue(il->hw, ac);
2424}
2425
2426#ifdef ieee80211_stop_queue
2427#undef ieee80211_stop_queue
2428#endif
2429
2430#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2431
2432#ifdef ieee80211_wake_queue
2433#undef ieee80211_wake_queue
2434#endif
2435
2436#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2437
e7392364
SG		 2438static inline void
2439il_disable_interrupts(struct il_priv *il)
e94a4099
SG		 2440{
2441 clear_bit(S_INT_ENABLED, &il->status);
2442
2443 /* disable interrupts from uCode/NIC to host */
2444 _il_wr(il, CSR_INT_MASK, 0x00000000);
2445
2446 /* acknowledge/clear/reset any interrupts still pending
2447 * from uCode or flow handler (Rx/Tx DMA) */
2448 _il_wr(il, CSR_INT, 0xffffffff);
2449 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
e94a4099
SG		 2450}
2451
e7392364
SG		 2452static inline void
2453il_enable_rfkill_int(struct il_priv *il)
e94a4099 2454{
e94a4099
SG		 2455 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2456}
2457
e7392364
SG		 2458static inline void
2459il_enable_interrupts(struct il_priv *il)
e94a4099 2460{
e94a4099
SG		 2461 set_bit(S_INT_ENABLED, &il->status);
2462 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2463}
2464
2465/**
2466 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2467 * @il -- pointer to il_priv data structure
2468 * @tsf_bits -- number of bits need to shift for masking)
2469 */
e7392364
SG		 2470static inline u32
2471il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2472{
2473 return (1 << tsf_bits) - 1;
2474}
2475
2476/**
2477 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2478 * @il -- pointer to il_priv data structure
2479 * @tsf_bits -- number of bits need to shift for masking)
2480 */
e7392364
SG		 2481static inline u32
2482il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2483{
2484 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2485}
2486
2487/**
2488 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2489 *
2490 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2491 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2492 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2493 * in which the last frame was written to
2494 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2495 * which was transferred
2496 */
2497struct il_rb_status {
2498 __le16 closed_rb_num;
2499 __le16 closed_fr_num;
2500 __le16 finished_rb_num;
2501 __le16 finished_fr_nam;
e7392364 2502 __le32 __unused; /* 3945 only */
e94a4099
SG		 2503} __packed;
2504
e94a4099
SG		 2505#define TFD_QUEUE_SIZE_MAX (256)
2506#define TFD_QUEUE_SIZE_BC_DUP (64)
2507#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2508#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2509#define IL_NUM_OF_TBS 20
2510
e7392364
SG		 2511static inline u8
2512il_get_dma_hi_addr(dma_addr_t addr)
e94a4099
SG		 2513{
2514 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2515}
e7392364 2516
e94a4099
SG		 2517/**
2518 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2519 *
2520 * This structure contains dma address and length of transmission address
2521 *
1722f8e1
SG		 2522 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2523 * unaligned on 16 bit boundary
2524 * @hi_n_len: 0-3 [35:32] portion of dma
2525 * 4-15 length of the tx buffer
e94a4099
SG		 2526 */
2527struct il_tfd_tb {
2528 __le32 lo;
2529 __le16 hi_n_len;
2530} __packed;
2531
2532/**
2533 * struct il_tfd
2534 *
2535 * Transmit Frame Descriptor (TFD)
2536 *
2537 * @ __reserved1[3] reserved
2538 * @ num_tbs 0-4 number of active tbs
2539 * 5 reserved
2540 * 6-7 padding (not used)
2541 * @ tbs[20] transmit frame buffer descriptors
1722f8e1 2542 * @ __pad padding
e94a4099
SG		 2543 *
2544 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2545 * Both driver and device share these circular buffers, each of which must be
2546 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2547 *
2548 * Driver must indicate the physical address of the base of each
9a95b370 2549 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
e94a4099
SG		 2550 *
2551 * Each TFD contains pointer/size information for up to 20 data buffers
2552 * in host DRAM. These buffers collectively contain the (one) frame described
2553 * by the TFD. Each buffer must be a single contiguous block of memory within
2554 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2555 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2556 * Tx frame, up to 8 KBytes in size.
2557 *
2558 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2559 */
2560struct il_tfd {
2561 u8 __reserved1[3];
2562 u8 num_tbs;
2563 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2564 __le32 __pad;
2565} __packed;
2566/* PCI registers */
2567#define PCI_CFG_RETRY_TIMEOUT 0x041
2568
2569/* PCI register values */
2570#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2571#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2572
3fbbf9a8 2573struct il_rate_info {
e7392364
SG		 2574 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2575 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2576 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2577 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2578 u8 prev_ieee; /* previous rate in IEEE speeds */
2579 u8 next_ieee; /* next rate in IEEE speeds */
2580 u8 prev_rs; /* previous rate used in rs algo */
2581 u8 next_rs; /* next rate used in rs algo */
2582 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2583 u8 next_rs_tgg; /* next rate used in TGG rs algo */
3fbbf9a8
SG		 2584};
2585
2586struct il3945_rate_info {
2587 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2588 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2589 u8 prev_ieee; /* previous rate in IEEE speeds */
2590 u8 next_ieee; /* next rate in IEEE speeds */
2591 u8 prev_rs; /* previous rate used in rs algo */
2592 u8 next_rs; /* next rate used in rs algo */
2593 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2594 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2595 u8 table_rs_idx; /* idx in rate scale table cmd */
2596 u8 prev_table_rs; /* prev in rate table cmd */
2597};
2598
3fbbf9a8
SG		 2599/*
2600 * These serve as idxes into
2601 * struct il_rate_info il_rates[RATE_COUNT];
2602 */
2603enum {
2604 RATE_1M_IDX = 0,
2605 RATE_2M_IDX,
2606 RATE_5M_IDX,
2607 RATE_11M_IDX,
2608 RATE_6M_IDX,
2609 RATE_9M_IDX,
2610 RATE_12M_IDX,
2611 RATE_18M_IDX,
2612 RATE_24M_IDX,
2613 RATE_36M_IDX,
2614 RATE_48M_IDX,
2615 RATE_54M_IDX,
2616 RATE_60M_IDX,
2617 RATE_COUNT,
2618 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2619 RATE_COUNT_3945 = RATE_COUNT - 1,
2620 RATE_INVM_IDX = RATE_COUNT,
2621 RATE_INVALID = RATE_COUNT,
2622};
2623
2624enum {
2625 RATE_6M_IDX_TBL = 0,
2626 RATE_9M_IDX_TBL,
2627 RATE_12M_IDX_TBL,
2628 RATE_18M_IDX_TBL,
2629 RATE_24M_IDX_TBL,
2630 RATE_36M_IDX_TBL,
2631 RATE_48M_IDX_TBL,
2632 RATE_54M_IDX_TBL,
2633 RATE_1M_IDX_TBL,
2634 RATE_2M_IDX_TBL,
2635 RATE_5M_IDX_TBL,
2636 RATE_11M_IDX_TBL,
2637 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2638};
2639
2640enum {
2641 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2642 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2643 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2644 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2645 IL_LAST_CCK_RATE = RATE_11M_IDX,
2646};
2647
2648/* #define vs. enum to keep from defaulting to 'large integer' */
2649#define RATE_6M_MASK (1 << RATE_6M_IDX)
2650#define RATE_9M_MASK (1 << RATE_9M_IDX)
2651#define RATE_12M_MASK (1 << RATE_12M_IDX)
2652#define RATE_18M_MASK (1 << RATE_18M_IDX)
2653#define RATE_24M_MASK (1 << RATE_24M_IDX)
2654#define RATE_36M_MASK (1 << RATE_36M_IDX)
2655#define RATE_48M_MASK (1 << RATE_48M_IDX)
2656#define RATE_54M_MASK (1 << RATE_54M_IDX)
2657#define RATE_60M_MASK (1 << RATE_60M_IDX)
2658#define RATE_1M_MASK (1 << RATE_1M_IDX)
2659#define RATE_2M_MASK (1 << RATE_2M_IDX)
2660#define RATE_5M_MASK (1 << RATE_5M_IDX)
2661#define RATE_11M_MASK (1 << RATE_11M_IDX)
2662
2663/* uCode API values for legacy bit rates, both OFDM and CCK */
2664enum {
e7392364
SG		 2665 RATE_6M_PLCP = 13,
2666 RATE_9M_PLCP = 15,
3fbbf9a8
SG		 2667 RATE_12M_PLCP = 5,
2668 RATE_18M_PLCP = 7,
2669 RATE_24M_PLCP = 9,
2670 RATE_36M_PLCP = 11,
2671 RATE_48M_PLCP = 1,
2672 RATE_54M_PLCP = 3,
e7392364
SG		 2673 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */
2674 RATE_1M_PLCP = 10,
2675 RATE_2M_PLCP = 20,
2676 RATE_5M_PLCP = 55,
3fbbf9a8 2677 RATE_11M_PLCP = 110,
e7392364 2678 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
3fbbf9a8
SG		 2679};
2680
2681/* uCode API values for OFDM high-throughput (HT) bit rates */
2682enum {
2683 RATE_SISO_6M_PLCP = 0,
2684 RATE_SISO_12M_PLCP = 1,
2685 RATE_SISO_18M_PLCP = 2,
2686 RATE_SISO_24M_PLCP = 3,
2687 RATE_SISO_36M_PLCP = 4,
2688 RATE_SISO_48M_PLCP = 5,
2689 RATE_SISO_54M_PLCP = 6,
2690 RATE_SISO_60M_PLCP = 7,
e7392364 2691 RATE_MIMO2_6M_PLCP = 0x8,
3fbbf9a8
SG		 2692 RATE_MIMO2_12M_PLCP = 0x9,
2693 RATE_MIMO2_18M_PLCP = 0xa,
2694 RATE_MIMO2_24M_PLCP = 0xb,
2695 RATE_MIMO2_36M_PLCP = 0xc,
2696 RATE_MIMO2_48M_PLCP = 0xd,
2697 RATE_MIMO2_54M_PLCP = 0xe,
2698 RATE_MIMO2_60M_PLCP = 0xf,
2699 RATE_SISO_INVM_PLCP,
2700 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2701};
2702
2703/* MAC header values for bit rates */
2704enum {
e7392364
SG		 2705 RATE_6M_IEEE = 12,
2706 RATE_9M_IEEE = 18,
3fbbf9a8
SG		 2707 RATE_12M_IEEE = 24,
2708 RATE_18M_IEEE = 36,
2709 RATE_24M_IEEE = 48,
2710 RATE_36M_IEEE = 72,
2711 RATE_48M_IEEE = 96,
2712 RATE_54M_IEEE = 108,
2713 RATE_60M_IEEE = 120,
e7392364
SG		 2714 RATE_1M_IEEE = 2,
2715 RATE_2M_IEEE = 4,
2716 RATE_5M_IEEE = 11,
3fbbf9a8
SG		 2717 RATE_11M_IEEE = 22,
2718};
2719
2720#define IL_CCK_BASIC_RATES_MASK \
2721 (RATE_1M_MASK | \
2722 RATE_2M_MASK)
2723
2724#define IL_CCK_RATES_MASK \
2725 (IL_CCK_BASIC_RATES_MASK | \
2726 RATE_5M_MASK | \
2727 RATE_11M_MASK)
2728
2729#define IL_OFDM_BASIC_RATES_MASK \
2730 (RATE_6M_MASK | \
2731 RATE_12M_MASK | \
2732 RATE_24M_MASK)
2733
2734#define IL_OFDM_RATES_MASK \
2735 (IL_OFDM_BASIC_RATES_MASK | \
2736 RATE_9M_MASK | \
2737 RATE_18M_MASK | \
2738 RATE_36M_MASK | \
2739 RATE_48M_MASK | \
2740 RATE_54M_MASK)
2741
2742#define IL_BASIC_RATES_MASK \
2743 (IL_OFDM_BASIC_RATES_MASK | \
2744 IL_CCK_BASIC_RATES_MASK)
2745
2746#define RATES_MASK ((1 << RATE_COUNT) - 1)
2747#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2748
2749#define IL_INVALID_VALUE -1
2750
2751#define IL_MIN_RSSI_VAL -100
2752#define IL_MAX_RSSI_VAL 0
2753
2754/* These values specify how many Tx frame attempts before
2755 * searching for a new modulation mode */
2756#define IL_LEGACY_FAILURE_LIMIT 160
2757#define IL_LEGACY_SUCCESS_LIMIT 480
2758#define IL_LEGACY_TBL_COUNT 160
2759
2760#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2761#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2762#define IL_NONE_LEGACY_TBL_COUNT 1500
2763
2764/* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2765#define IL_RS_GOOD_RATIO 12800 /* 100% */
2766#define RATE_SCALE_SWITCH 10880 /* 85% */
2767#define RATE_HIGH_TH 10880 /* 85% */
2768#define RATE_INCREASE_TH 6400 /* 50% */
2769#define RATE_DECREASE_TH 1920 /* 15% */
2770
2771/* possible actions when in legacy mode */
2772#define IL_LEGACY_SWITCH_ANTENNA1 0
2773#define IL_LEGACY_SWITCH_ANTENNA2 1
2774#define IL_LEGACY_SWITCH_SISO 2
2775#define IL_LEGACY_SWITCH_MIMO2_AB 3
2776#define IL_LEGACY_SWITCH_MIMO2_AC 4
2777#define IL_LEGACY_SWITCH_MIMO2_BC 5
2778
2779/* possible actions when in siso mode */
2780#define IL_SISO_SWITCH_ANTENNA1 0
2781#define IL_SISO_SWITCH_ANTENNA2 1
2782#define IL_SISO_SWITCH_MIMO2_AB 2
2783#define IL_SISO_SWITCH_MIMO2_AC 3
2784#define IL_SISO_SWITCH_MIMO2_BC 4
2785#define IL_SISO_SWITCH_GI 5
2786
2787/* possible actions when in mimo mode */
2788#define IL_MIMO2_SWITCH_ANTENNA1 0
2789#define IL_MIMO2_SWITCH_ANTENNA2 1
2790#define IL_MIMO2_SWITCH_SISO_A 2
2791#define IL_MIMO2_SWITCH_SISO_B 3
2792#define IL_MIMO2_SWITCH_SISO_C 4
2793#define IL_MIMO2_SWITCH_GI 5
2794
2795#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2796
2797#define IL_ACTION_LIMIT 3 /* # possible actions */
2798
2799#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
2800
2801/* load per tid defines for A-MPDU activation */
2802#define IL_AGG_TPT_THREHOLD 0
2803#define IL_AGG_LOAD_THRESHOLD 10
2804#define IL_AGG_ALL_TID 0xff
2805#define TID_QUEUE_CELL_SPACING 50 /*mS */
2806#define TID_QUEUE_MAX_SIZE 20
2807#define TID_ROUND_VALUE 5 /* mS */
2808#define TID_MAX_LOAD_COUNT 8
2809
2810#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2811#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2812
2813extern const struct il_rate_info il_rates[RATE_COUNT];
2814
2815enum il_table_type {
2816 LQ_NONE,
e7392364 2817 LQ_G, /* legacy types */
3fbbf9a8 2818 LQ_A,
e7392364 2819 LQ_SISO, /* high-throughput types */
3fbbf9a8
SG		 2820 LQ_MIMO2,
2821 LQ_MAX,
2822};
2823
2824#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2825#define is_siso(tbl) ((tbl) == LQ_SISO)
2826#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2827#define is_mimo(tbl) (is_mimo2(tbl))
2828#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2829#define is_a_band(tbl) ((tbl) == LQ_A)
2830#define is_g_and(tbl) ((tbl) == LQ_G)
2831
2832#define ANT_NONE 0x0
2833#define ANT_A BIT(0)
2834#define ANT_B BIT(1)
2835#define ANT_AB (ANT_A | ANT_B)
2836#define ANT_C BIT(2)
2837#define ANT_AC (ANT_A | ANT_C)
2838#define ANT_BC (ANT_B | ANT_C)
2839#define ANT_ABC (ANT_AB | ANT_C)
2840
2841#define IL_MAX_MCS_DISPLAY_SIZE 12
2842
2843struct il_rate_mcs_info {
e7392364
SG		 2844 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2845 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
3fbbf9a8
SG		 2846};
2847
2848/**
2849 * struct il_rate_scale_data -- tx success history for one rate
2850 */
2851struct il_rate_scale_data {
2852 u64 data; /* bitmap of successful frames */
2853 s32 success_counter; /* number of frames successful */
2854 s32 success_ratio; /* per-cent * 128 */
2855 s32 counter; /* number of frames attempted */
2856 s32 average_tpt; /* success ratio * expected throughput */
2857 unsigned long stamp;
2858};
2859
2860/**
2861 * struct il_scale_tbl_info -- tx params and success history for all rates
2862 *
2863 * There are two of these in struct il_lq_sta,
2864 * one for "active", and one for "search".
2865 */
2866struct il_scale_tbl_info {
2867 enum il_table_type lq_type;
2868 u8 ant_type;
e7392364
SG		 2869 u8 is_SGI; /* 1 = short guard interval */
2870 u8 is_ht40; /* 1 = 40 MHz channel width */
2871 u8 is_dup; /* 1 = duplicated data streams */
2872 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2873 u8 max_search; /* maximun number of tables we can search */
3fbbf9a8 2874 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
e7392364
SG		 2875 u32 current_rate; /* rate_n_flags, uCode API format */
2876 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
3fbbf9a8
SG		 2877};
2878
2879struct il_traffic_load {
2880 unsigned long time_stamp; /* age of the oldest stats */
e7392364 2881 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
3fbbf9a8 2882 * slice */
e7392364
SG		 2883 u32 total; /* total num of packets during the
2884 * last TID_MAX_TIME_DIFF */
2885 u8 queue_count; /* number of queues that has
2886 * been used since the last cleanup */
2887 u8 head; /* start of the circular buffer */
3fbbf9a8
SG		 2888};
2889
2890/**
2891 * struct il_lq_sta -- driver's rate scaling ilate structure
2892 *
2893 * Pointer to this gets passed back and forth between driver and mac80211.
2894 */
2895struct il_lq_sta {
2896 u8 active_tbl; /* idx of active table, range 0-1 */
2897 u8 enable_counter; /* indicates HT mode */
2898 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
2899 u8 search_better_tbl; /* 1: currently trying alternate mode */
2900 s32 last_tpt;
2901
2902 /* The following determine when to search for a new mode */
2903 u32 table_count_limit;
2904 u32 max_failure_limit; /* # failed frames before new search */
2905 u32 max_success_limit; /* # successful frames before new search */
2906 u32 table_count;
2907 u32 total_failed; /* total failed frames, any/all rates */
2908 u32 total_success; /* total successful frames, any/all rates */
2909 u64 flush_timer; /* time staying in mode before new search */
2910
2911 u8 action_counter; /* # mode-switch actions tried */
2912 u8 is_green;
2913 u8 is_dup;
2914 enum ieee80211_band band;
2915
2916 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2917 u32 supp_rates;
2918 u16 active_legacy_rate;
2919 u16 active_siso_rate;
2920 u16 active_mimo2_rate;
e7392364 2921 s8 max_rate_idx; /* Max rate set by user */
3fbbf9a8
SG		 2922 u8 missed_rate_counter;
2923
2924 struct il_link_quality_cmd lq;
e7392364 2925 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
3fbbf9a8
SG		 2926 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2927 u8 tx_agg_tid_en;
2928#ifdef CONFIG_MAC80211_DEBUGFS
2929 struct dentry *rs_sta_dbgfs_scale_table_file;
2930 struct dentry *rs_sta_dbgfs_stats_table_file;
2931 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2932 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2933 u32 dbg_fixed_rate;
2934#endif
2935 struct il_priv *drv;
2936
2937 /* used to be in sta_info */
2938 int last_txrate_idx;
2939 /* last tx rate_n_flags */
2940 u32 last_rate_n_flags;
2941 /* packets destined for this STA are aggregated */
2942 u8 is_agg;
2943};
2944
2945/*
2946 * il_station_priv: Driver's ilate station information
2947 *
2948 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2949 * in the structure for use by driver. This structure is places in that
2950 * space.
2951 *
2952 * The common struct MUST be first because it is shared between
2953 * 3945 and 4965!
2954 */
2955struct il_station_priv {
2956 struct il_station_priv_common common;
2957 struct il_lq_sta lq_sta;
2958 atomic_t pending_frames;
2959 bool client;
2960 bool asleep;
2961};
2962
e7392364
SG		 2963static inline u8
2964il4965_num_of_ant(u8 m)
3fbbf9a8
SG		 2965{
2966 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2967}
2968
e7392364
SG		 2969static inline u8
2970il4965_first_antenna(u8 mask)
3fbbf9a8
SG		 2971{
2972 if (mask & ANT_A)
2973 return ANT_A;
2974 if (mask & ANT_B)
2975 return ANT_B;
2976 return ANT_C;
2977}
2978
3fbbf9a8
SG		 2979/**
2980 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
2981 *
2982 * The specific throughput table used is based on the type of network
2983 * the associated with, including A, B, G, and G w/ TGG protection
2984 */
2985extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2986
2987/* Initialize station's rate scaling information after adding station */
e7392364
SG		 2988extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2989 u8 sta_id);
2990extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2991 u8 sta_id);
3fbbf9a8
SG		 2992
2993/**
2994 * il_rate_control_register - Register the rate control algorithm callbacks
2995 *
2996 * Since the rate control algorithm is hardware specific, there is no need
2997 * or reason to place it as a stand alone module. The driver can call
2998 * il_rate_control_register in order to register the rate control callbacks
2999 * with the mac80211 subsystem. This should be performed prior to calling
3000 * ieee80211_register_hw
3001 *
3002 */
3003extern int il4965_rate_control_register(void);
3004extern int il3945_rate_control_register(void);
3005
3006/**
3007 * il_rate_control_unregister - Unregister the rate control callbacks
3008 *
3009 * This should be called after calling ieee80211_unregister_hw, but before
3010 * the driver is unloaded.
3011 */
3012extern void il4965_rate_control_unregister(void);
3013extern void il3945_rate_control_unregister(void);
3014
99412002
SG		 3015extern int il_power_update_mode(struct il_priv *il, bool force);
3016extern void il_power_initialize(struct il_priv *il);
47ef694d 3017
f02579e3
SG		 3018extern u32 il_debug_level;
3019
3020#ifdef CONFIG_IWLEGACY_DEBUG
3021/*
3022 * il_get_debug_level: Return active debug level for device
3023 *
3024 * Using sysfs it is possible to set per device debug level. This debug
3025 * level will be used if set, otherwise the global debug level which can be
3026 * set via module parameter is used.
3027 */
e7392364
SG		 3028static inline u32
3029il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3030{
3031 if (il->debug_level)
3032 return il->debug_level;
3033 else
3034 return il_debug_level;
3035}
3036#else
e7392364
SG		 3037static inline u32
3038il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3039{
3040 return il_debug_level;
3041}
3042#endif
3043
3044#define il_print_hex_error(il, p, len) \
3045do { \
3046 print_hex_dump(KERN_ERR, "iwl data: ", \
3047 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3048} while (0)
3049
3050#ifdef CONFIG_IWLEGACY_DEBUG
3051#define IL_DBG(level, fmt, args...) \
3052do { \
3053 if (il_get_debug_level(il) & level) \
3054 dev_printk(KERN_ERR, &il->hw->wiphy->dev, \
3055 "%c %s " fmt, in_interrupt() ? 'I' : 'U', \
3056 __func__ , ## args); \
3057} while (0)
3058
1722f8e1 3059#define il_print_hex_dump(il, level, p, len) \
f02579e3
SG		 3060do { \
3061 if (il_get_debug_level(il) & level) \
3062 print_hex_dump(KERN_DEBUG, "iwl data: ", \
3063 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3064} while (0)
3065
3066#else
3067#define IL_DBG(level, fmt, args...)
e7392364
SG		 3068static inline void
3069il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
3070{
3071}
3072#endif /* CONFIG_IWLEGACY_DEBUG */
f02579e3
SG		 3073
3074#ifdef CONFIG_IWLEGACY_DEBUGFS
3075int il_dbgfs_register(struct il_priv *il, const char *name);
3076void il_dbgfs_unregister(struct il_priv *il);
3077#else
3078static inline int
3079il_dbgfs_register(struct il_priv *il, const char *name)
3080{
3081 return 0;
3082}
e7392364
SG		 3083
3084static inline void
3085il_dbgfs_unregister(struct il_priv *il)
f02579e3
SG		 3086{
3087}
e7392364 3088#endif /* CONFIG_IWLEGACY_DEBUGFS */
f02579e3
SG		 3089
3090/*
3091 * To use the debug system:
3092 *
3093 * If you are defining a new debug classification, simply add it to the #define
3094 * list here in the form of
3095 *
3096 * #define IL_DL_xxxx VALUE
3097 *
3098 * where xxxx should be the name of the classification (for example, WEP).
3099 *
3100 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
3101 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
3102 * to send output to that classification.
3103 *
3104 * The active debug levels can be accessed via files
3105 *
1722f8e1 3106 * /sys/module/iwl4965/parameters/debug
f02579e3 3107 * /sys/module/iwl3945/parameters/debug
1722f8e1 3108 * /sys/class/net/wlan0/device/debug_level
f02579e3
SG		 3109 *
3110 * when CONFIG_IWLEGACY_DEBUG=y.
3111 */
3112
3113/* 0x0000000F - 0x00000001 */
3114#define IL_DL_INFO (1 << 0)
3115#define IL_DL_MAC80211 (1 << 1)
3116#define IL_DL_HCMD (1 << 2)
3117#define IL_DL_STATE (1 << 3)
3118/* 0x000000F0 - 0x00000010 */
3119#define IL_DL_MACDUMP (1 << 4)
3120#define IL_DL_HCMD_DUMP (1 << 5)
3121#define IL_DL_EEPROM (1 << 6)
3122#define IL_DL_RADIO (1 << 7)
3123/* 0x00000F00 - 0x00000100 */
3124#define IL_DL_POWER (1 << 8)
3125#define IL_DL_TEMP (1 << 9)
3126#define IL_DL_NOTIF (1 << 10)
3127#define IL_DL_SCAN (1 << 11)
3128/* 0x0000F000 - 0x00001000 */
3129#define IL_DL_ASSOC (1 << 12)
3130#define IL_DL_DROP (1 << 13)
3131#define IL_DL_TXPOWER (1 << 14)
3132#define IL_DL_AP (1 << 15)
3133/* 0x000F0000 - 0x00010000 */
3134#define IL_DL_FW (1 << 16)
3135#define IL_DL_RF_KILL (1 << 17)
3136#define IL_DL_FW_ERRORS (1 << 18)
3137#define IL_DL_LED (1 << 19)
3138/* 0x00F00000 - 0x00100000 */
3139#define IL_DL_RATE (1 << 20)
3140#define IL_DL_CALIB (1 << 21)
3141#define IL_DL_WEP (1 << 22)
3142#define IL_DL_TX (1 << 23)
3143/* 0x0F000000 - 0x01000000 */
3144#define IL_DL_RX (1 << 24)
3145#define IL_DL_ISR (1 << 25)
3146#define IL_DL_HT (1 << 26)
3147/* 0xF0000000 - 0x10000000 */
3148#define IL_DL_11H (1 << 28)
3149#define IL_DL_STATS (1 << 29)
3150#define IL_DL_TX_REPLY (1 << 30)
3151#define IL_DL_QOS (1 << 31)
3152
3153#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3154#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3155#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3156#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3157#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3158#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3159#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3160#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3161#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3162#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3163#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3164#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3165#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3166#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3167#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3168#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3169#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3170#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3171#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3172#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3173#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3174#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3175#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3176#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3177#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3178#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3179#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3180#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3181#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3182
e2ebc833 3183#endif /* __il_core_h__ */
Linux kernel - Deliverables
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