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iwlegacy: off by one in iwl3945_hw_build_tx_cmd_rate()
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.h
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
e94a4099 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
be663ab6 4 *
e94a4099
SG		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
be663ab6
WYG		 7 * published by the Free Software Foundation.
8 *
e94a4099
SG		 9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
be663ab6 13 *
e94a4099
SG		 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
be663ab6 17 *
e94a4099
SG		 18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
be663ab6
WYG		 20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
e94a4099
SG		 25 *****************************************************************************/
26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
e7392364 30#include <linux/pci.h> /* for struct pci_device_id */
e94a4099
SG		 31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
47ef694d 34#include <net/mac80211.h>
e94a4099
SG		 35#include <net/ieee80211_radiotap.h>
36
99412002 37#include "commands.h"
e94a4099 38#include "csr.h"
e8c39d4e 39#include "prph.h"
e94a4099
SG		 40
41struct il_host_cmd;
42struct il_cmd;
43struct il_tx_queue;
44
f02579e3
SG		 45#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
46#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
47#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
48
e94a4099
SG		 49#define RX_QUEUE_SIZE 256
50#define RX_QUEUE_MASK 255
51#define RX_QUEUE_SIZE_LOG 8
52
53/*
54 * RX related structures and functions
55 */
56#define RX_FREE_BUFFERS 64
57#define RX_LOW_WATERMARK 8
58
59#define U32_PAD(n) ((4-(n))&0x3)
60
61/* CT-KILL constants */
e7392364 62#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
e94a4099
SG		 63
64/* Default noise level to report when noise measurement is not available.
65 * This may be because we're:
66 * 1) Not associated (4965, no beacon stats being sent to driver)
67 * 2) Scanning (noise measurement does not apply to associated channel)
68 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
69 * Use default noise value of -127 ... this is below the range of measurable
70 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
71 * Also, -127 works better than 0 when averaging frames with/without
72 * noise info (e.g. averaging might be done in app); measured dBm values are
73 * always negative ... using a negative value as the default keeps all
74 * averages within an s8's (used in some apps) range of negative values. */
75#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
76
77/*
78 * RTS threshold here is total size [2347] minus 4 FCS bytes
79 * Per spec:
80 * a value of 0 means RTS on all data/management packets
81 * a value > max MSDU size means no RTS
82 * else RTS for data/management frames where MPDU is larger
83 * than RTS value.
84 */
85#define DEFAULT_RTS_THRESHOLD 2347U
86#define MIN_RTS_THRESHOLD 0U
87#define MAX_RTS_THRESHOLD 2347U
88#define MAX_MSDU_SIZE 2304U
89#define MAX_MPDU_SIZE 2346U
90#define DEFAULT_BEACON_INTERVAL 100U
91#define DEFAULT_SHORT_RETRY_LIMIT 7U
92#define DEFAULT_LONG_RETRY_LIMIT 4U
93
94struct il_rx_buf {
95 dma_addr_t page_dma;
96 struct page *page;
97 struct list_head list;
98};
99
100#define rxb_addr(r) page_address(r->page)
101
102/* defined below */
103struct il_device_cmd;
104
105struct il_cmd_meta {
106 /* only for SYNC commands, iff the reply skb is wanted */
107 struct il_host_cmd *source;
108 /*
109 * only for ASYNC commands
110 * (which is somewhat stupid -- look at common.c for instance
111 * which duplicates a bunch of code because the callback isn't
112 * invoked for SYNC commands, if it were and its result passed
113 * through it would be simpler...)
114 */
1722f8e1
SG		 115 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
116 struct il_rx_pkt *pkt);
e94a4099
SG		 117
118 /* The CMD_SIZE_HUGE flag bit indicates that the command
119 * structure is stored at the end of the shared queue memory. */
120 u32 flags;
121
e7392364
SG		 122 DEFINE_DMA_UNMAP_ADDR(mapping);
123 DEFINE_DMA_UNMAP_LEN(len);
e94a4099
SG		 124};
125
126/*
127 * Generic queue structure
128 *
129 * Contains common data for Rx and Tx queues
130 */
131struct il_queue {
e7392364
SG		 132 int n_bd; /* number of BDs in this queue */
133 int write_ptr; /* 1-st empty entry (idx) host_w */
134 int read_ptr; /* last used entry (idx) host_r */
e94a4099 135 /* use for monitoring and recovering the stuck queue */
e7392364
SG		 136 dma_addr_t dma_addr; /* physical addr for BD's */
137 int n_win; /* safe queue win */
e94a4099 138 u32 id;
e7392364
SG		 139 int low_mark; /* low watermark, resume queue if free
140 * space more than this */
141 int high_mark; /* high watermark, stop queue if free
142 * space less than this */
e94a4099
SG		 143};
144
145/* One for each TFD */
146struct il_tx_info {
147 struct sk_buff *skb;
148 struct il_rxon_context *ctx;
149};
150
151/**
152 * struct il_tx_queue - Tx Queue for DMA
153 * @q: generic Rx/Tx queue descriptor
154 * @bd: base of circular buffer of TFDs
155 * @cmd: array of command/TX buffer pointers
156 * @meta: array of meta data for each command/tx buffer
157 * @dma_addr_cmd: physical address of cmd/tx buffer array
158 * @txb: array of per-TFD driver data
159 * @time_stamp: time (in jiffies) of last read_ptr change
160 * @need_update: indicates need to update read/write idx
161 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
162 *
163 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
164 * descriptors) and required locking structures.
165 */
166#define TFD_TX_CMD_SLOTS 256
167#define TFD_CMD_SLOTS 32
168
169struct il_tx_queue {
170 struct il_queue q;
171 void *tfds;
172 struct il_device_cmd **cmd;
173 struct il_cmd_meta *meta;
174 struct il_tx_info *txb;
175 unsigned long time_stamp;
176 u8 need_update;
177 u8 sched_retry;
178 u8 active;
179 u8 swq_id;
180};
181
47ef694d
SG		 182/*
183 * EEPROM access time values:
184 *
185 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
186 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
187 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
188 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
189 */
e7392364 190#define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
47ef694d 191
e7392364
SG		 192#define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
193#define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
47ef694d
SG		 194
195/*
196 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
197 *
198 * IBSS and/or AP operation is allowed *only* on those channels with
199 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
200 * RADAR detection is not supported by the 4965 driver, but is a
201 * requirement for establishing a new network for legal operation on channels
202 * requiring RADAR detection or restricting ACTIVE scanning.
203 *
204 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
205 * It only indicates that 20 MHz channel use is supported; HT40 channel
206 * usage is indicated by a separate set of regulatory flags for each
207 * HT40 channel pair.
208 *
209 * NOTE: Using a channel inappropriately will result in a uCode error!
210 */
211#define IL_NUM_TX_CALIB_GROUPS 5
212enum {
213 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
e7392364 214 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
47ef694d
SG		 215 /* Bit 2 Reserved */
216 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
217 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
e7392364 218 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
47ef694d
SG		 219 /* Bit 6 Reserved (was Narrow Channel) */
220 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
221};
222
223/* SKU Capabilities */
224/* 3945 only */
225#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
226#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
227
228/* *regulatory* channel data format in eeprom, one for each channel.
229 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
230struct il_eeprom_channel {
231 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
232 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
233} __packed;
234
235/* 3945 Specific */
236#define EEPROM_3945_EEPROM_VERSION (0x2f)
237
238/* 4965 has two radio transmitters (and 3 radio receivers) */
239#define EEPROM_TX_POWER_TX_CHAINS (2)
240
241/* 4965 has room for up to 8 sets of txpower calibration data */
242#define EEPROM_TX_POWER_BANDS (8)
243
244/* 4965 factory calibration measures txpower gain settings for
245 * each of 3 target output levels */
246#define EEPROM_TX_POWER_MEASUREMENTS (3)
247
248/* 4965 Specific */
249/* 4965 driver does not work with txpower calibration version < 5 */
250#define EEPROM_4965_TX_POWER_VERSION (5)
251#define EEPROM_4965_EEPROM_VERSION (0x2f)
e7392364
SG		 252#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
253#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
254#define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
255#define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
47ef694d
SG		 256
257/* 2.4 GHz */
258extern const u8 il_eeprom_band_1[14];
259
260/*
261 * factory calibration data for one txpower level, on one channel,
262 * measured on one of the 2 tx chains (radio transmitter and associated
263 * antenna). EEPROM contains:
264 *
265 * 1) Temperature (degrees Celsius) of device when measurement was made.
266 *
267 * 2) Gain table idx used to achieve the target measurement power.
268 * This refers to the "well-known" gain tables (see 4965.h).
269 *
270 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
271 *
272 * 4) RF power amplifier detector level measurement (not used).
273 */
274struct il_eeprom_calib_measure {
275 u8 temperature; /* Device temperature (Celsius) */
276 u8 gain_idx; /* Index into gain table */
277 u8 actual_pow; /* Measured RF output power, half-dBm */
278 s8 pa_det; /* Power amp detector level (not used) */
279} __packed;
280
47ef694d
SG		 281/*
282 * measurement set for one channel. EEPROM contains:
283 *
284 * 1) Channel number measured
285 *
286 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
287 * (a.k.a. "tx chains") (6 measurements altogether)
288 */
289struct il_eeprom_calib_ch_info {
290 u8 ch_num;
291 struct il_eeprom_calib_measure
e7392364
SG		 292 measurements[EEPROM_TX_POWER_TX_CHAINS]
293 [EEPROM_TX_POWER_MEASUREMENTS];
47ef694d
SG		 294} __packed;
295
296/*
297 * txpower subband info.
298 *
299 * For each frequency subband, EEPROM contains the following:
300 *
301 * 1) First and last channels within range of the subband. "0" values
302 * indicate that this sample set is not being used.
303 *
304 * 2) Sample measurement sets for 2 channels close to the range endpoints.
305 */
306struct il_eeprom_calib_subband_info {
e7392364
SG		 307 u8 ch_from; /* channel number of lowest channel in subband */
308 u8 ch_to; /* channel number of highest channel in subband */
47ef694d
SG		 309 struct il_eeprom_calib_ch_info ch1;
310 struct il_eeprom_calib_ch_info ch2;
311} __packed;
312
47ef694d
SG		 313/*
314 * txpower calibration info. EEPROM contains:
315 *
316 * 1) Factory-measured saturation power levels (maximum levels at which
317 * tx power amplifier can output a signal without too much distortion).
318 * There is one level for 2.4 GHz band and one for 5 GHz band. These
319 * values apply to all channels within each of the bands.
320 *
321 * 2) Factory-measured power supply voltage level. This is assumed to be
322 * constant (i.e. same value applies to all channels/bands) while the
323 * factory measurements are being made.
324 *
325 * 3) Up to 8 sets of factory-measured txpower calibration values.
326 * These are for different frequency ranges, since txpower gain
327 * characteristics of the analog radio circuitry vary with frequency.
328 *
329 * Not all sets need to be filled with data;
330 * struct il_eeprom_calib_subband_info contains range of channels
331 * (0 if unused) for each set of data.
332 */
333struct il_eeprom_calib_info {
334 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */
335 u8 saturation_power52; /* half-dBm */
336 __le16 voltage; /* signed */
e7392364 337 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
47ef694d
SG		 338} __packed;
339
47ef694d
SG		 340/* General */
341#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
342#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
343#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
344#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
345#define EEPROM_VERSION (2*0x44) /* 2 bytes */
346#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
347#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
348#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
349#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
350#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
351
352/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
e7392364
SG		 353#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
354#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
355#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
356#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
357#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
358#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
47ef694d
SG		 359
360#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
361#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
362
363/*
364 * Per-channel regulatory data.
365 *
366 * Each channel that *might* be supported by iwl has a fixed location
367 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
368 * txpower (MSB).
369 *
370 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz)
371 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
372 *
373 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
374 */
e7392364 375#define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
47ef694d
SG		 376#define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
377#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
378
379/*
380 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
381 * 5.0 GHz channels 7, 8, 11, 12, 16
382 * (4915-5080MHz) (none of these is ever supported)
383 */
384#define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
385#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
386
387/*
388 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
389 * (5170-5320MHz)
390 */
391#define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
392#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
393
394/*
395 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
396 * (5500-5700MHz)
397 */
398#define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
399#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
400
401/*
402 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
403 * (5725-5825MHz)
404 */
405#define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
406#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
407
408/*
409 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
410 *
411 * The channel listed is the center of the lower 20 MHz half of the channel.
412 * The overall center frequency is actually 2 channels (10 MHz) above that,
413 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
414 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
415 * and the overall HT40 channel width centers on channel 3.
416 *
417 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
418 * control channel to which to tune. RXON also specifies whether the
419 * control channel is the upper or lower half of a HT40 channel.
420 *
421 * NOTE: 4965 does not support HT40 channels on 2.4 GHz.
422 */
423#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */
424
425/*
426 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
427 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
428 */
429#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */
430
431#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
432
433struct il_eeprom_ops {
434 const u32 regulatory_bands[7];
1722f8e1
SG		 435 int (*acquire_semaphore) (struct il_priv *il);
436 void (*release_semaphore) (struct il_priv *il);
47ef694d
SG		 437};
438
47ef694d
SG		 439int il_eeprom_init(struct il_priv *il);
440void il_eeprom_free(struct il_priv *il);
e7392364 441const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
47ef694d
SG		 442u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
443int il_init_channel_map(struct il_priv *il);
444void il_free_channel_map(struct il_priv *il);
e7392364
SG		 445const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
446 enum ieee80211_band band,
447 u16 channel);
47ef694d 448
e94a4099
SG		 449#define IL_NUM_SCAN_RATES (2)
450
451struct il4965_channel_tgd_info {
452 u8 type;
453 s8 max_power;
454};
455
456struct il4965_channel_tgh_info {
457 s64 last_radar_time;
458};
459
460#define IL4965_MAX_RATE (33)
461
462struct il3945_clip_group {
463 /* maximum power level to prevent clipping for each rate, derived by
464 * us from this band's saturation power in EEPROM */
465 const s8 clip_powers[IL_MAX_RATES];
466};
467
468/* current Tx power values to use, one for each rate for each channel.
469 * requested power is limited by:
470 * -- regulatory EEPROM limits for this channel
471 * -- hardware capabilities (clip-powers)
472 * -- spectrum management
473 * -- user preference (e.g. iwconfig)
474 * when requested power is set, base power idx must also be set. */
475struct il3945_channel_power_info {
476 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
477 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
478 s8 base_power_idx; /* gain idx for power at factory temp. */
479 s8 requested_power; /* power (dBm) requested for this chnl/rate */
480};
481
482/* current scan Tx power values to use, one for each scan rate for each
483 * channel. */
484struct il3945_scan_power_info {
485 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */
486 s8 power_table_idx; /* actual (compenst'd) idx into gain table */
487 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
488};
489
490/*
491 * One for each channel, holds all channel setup data
492 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
493 * with one another!
494 */
495struct il_channel_info {
496 struct il4965_channel_tgd_info tgd;
497 struct il4965_channel_tgh_info tgh;
498 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */
499 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
500 * HT40 channel */
501
e7392364
SG		 502 u8 channel; /* channel number */
503 u8 flags; /* flags copied from EEPROM */
504 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
505 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
506 s8 min_power; /* always 0 */
507 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
e94a4099 508
e7392364
SG		 509 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */
510 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */
e94a4099
SG		 511 enum ieee80211_band band;
512
513 /* HT40 channel info */
514 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
515 u8 ht40_flags; /* flags copied from EEPROM */
e7392364 516 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
e94a4099
SG		 517
518 /* Radio/DSP gain settings for each "normal" data Tx rate.
519 * These include, in addition to RF and DSP gain, a few fields for
520 * remembering/modifying gain settings (idxes). */
521 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
522
523 /* Radio/DSP gain settings for each scan rate, for directed scans. */
524 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
525};
526
527#define IL_TX_FIFO_BK 0 /* shared */
528#define IL_TX_FIFO_BE 1
529#define IL_TX_FIFO_VI 2 /* shared */
530#define IL_TX_FIFO_VO 3
531#define IL_TX_FIFO_UNUSED -1
532
533/* Minimum number of queues. MAX_NUM is defined in hw specific files.
534 * Set the minimum to accommodate the 4 standard TX queues, 1 command
535 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
536#define IL_MIN_NUM_QUEUES 10
537
538#define IL_DEFAULT_CMD_QUEUE_NUM 4
539
540#define IEEE80211_DATA_LEN 2304
541#define IEEE80211_4ADDR_LEN 30
542#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
543#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
544
545struct il_frame {
546 union {
547 struct ieee80211_hdr frame;
548 struct il_tx_beacon_cmd beacon;
549 u8 raw[IEEE80211_FRAME_LEN];
550 u8 cmd[360];
551 } u;
552 struct list_head list;
553};
554
555#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
556#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
557#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
558
559enum {
560 CMD_SYNC = 0,
561 CMD_SIZE_NORMAL = 0,
562 CMD_NO_SKB = 0,
563 CMD_SIZE_HUGE = (1 << 0),
564 CMD_ASYNC = (1 << 1),
565 CMD_WANT_SKB = (1 << 2),
566 CMD_MAPPED = (1 << 3),
567};
568
569#define DEF_CMD_PAYLOAD_SIZE 320
570
571/**
572 * struct il_device_cmd
573 *
574 * For allocation of the command and tx queues, this establishes the overall
575 * size of the largest command we send to uCode, except for a scan command
576 * (which is relatively huge; space is allocated separately).
577 */
578struct il_device_cmd {
579 struct il_cmd_header hdr; /* uCode API */
580 union {
581 u32 flags;
582 u8 val8;
583 u16 val16;
584 u32 val32;
585 struct il_tx_cmd tx;
586 u8 payload[DEF_CMD_PAYLOAD_SIZE];
587 } __packed cmd;
588} __packed;
589
590#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
591
e94a4099
SG		 592struct il_host_cmd {
593 const void *data;
594 unsigned long reply_page;
1722f8e1
SG		 595 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
596 struct il_rx_pkt *pkt);
e94a4099
SG		 597 u32 flags;
598 u16 len;
599 u8 id;
600};
601
602#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
603#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
604#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
605
606/**
607 * struct il_rx_queue - Rx queue
608 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
609 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
610 * @read: Shared idx to newest available Rx buffer
611 * @write: Shared idx to oldest written Rx packet
612 * @free_count: Number of pre-allocated buffers in rx_free
613 * @rx_free: list of free SKBs for use
614 * @rx_used: List of Rx buffers with no SKB
615 * @need_update: flag to indicate we need to update read/write idx
616 * @rb_stts: driver's pointer to receive buffer status
617 * @rb_stts_dma: bus address of receive buffer status
618 *
619 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs
620 */
621struct il_rx_queue {
622 __le32 *bd;
623 dma_addr_t bd_dma;
624 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
625 struct il_rx_buf *queue[RX_QUEUE_SIZE];
626 u32 read;
627 u32 write;
628 u32 free_count;
629 u32 write_actual;
630 struct list_head rx_free;
631 struct list_head rx_used;
632 int need_update;
633 struct il_rb_status *rb_stts;
634 dma_addr_t rb_stts_dma;
635 spinlock_t lock;
636};
637
638#define IL_SUPPORTED_RATES_IE_LEN 8
639
640#define MAX_TID_COUNT 9
641
642#define IL_INVALID_RATE 0xFF
643#define IL_INVALID_VALUE -1
644
645/**
646 * struct il_ht_agg -- aggregation status while waiting for block-ack
647 * @txq_id: Tx queue used for Tx attempt
648 * @frame_count: # frames attempted by Tx command
649 * @wait_for_ba: Expect block-ack before next Tx reply
650 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
651 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
652 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
653 * @rate_n_flags: Rate at which Tx was attempted
654 *
655 * If C_TX indicates that aggregation was attempted, driver must wait
656 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info
657 * until block ack arrives.
658 */
659struct il_ht_agg {
660 u16 txq_id;
661 u16 frame_count;
662 u16 wait_for_ba;
663 u16 start_idx;
664 u64 bitmap;
665 u32 rate_n_flags;
666#define IL_AGG_OFF 0
667#define IL_AGG_ON 1
668#define IL_EMPTYING_HW_QUEUE_ADDBA 2
669#define IL_EMPTYING_HW_QUEUE_DELBA 3
670 u8 state;
671};
672
e94a4099 673struct il_tid_data {
e7392364 674 u16 seq_number; /* 4965 only */
e94a4099
SG		 675 u16 tfds_in_queue;
676 struct il_ht_agg agg;
677};
678
679struct il_hw_key {
680 u32 cipher;
681 int keylen;
682 u8 keyidx;
683 u8 key[32];
684};
685
686union il_ht_rate_supp {
687 u16 rates;
688 struct {
689 u8 siso_rate;
690 u8 mimo_rate;
691 };
692};
693
694#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
695#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
696#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
697#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
698#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
699#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
700#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
701
702/*
703 * Maximal MPDU density for TX aggregation
704 * 4 - 2us density
705 * 5 - 4us density
706 * 6 - 8us density
707 * 7 - 16us density
708 */
709#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
710#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
711#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
712#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
713#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
714#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
715#define CFG_HT_MPDU_DENSITY_MIN (0x1)
716
717struct il_ht_config {
718 bool single_chain_sufficient;
e7392364 719 enum ieee80211_smps_mode smps; /* current smps mode */
e94a4099
SG		 720};
721
722/* QoS structures */
723struct il_qos_info {
724 int qos_active;
725 struct il_qosparam_cmd def_qos_parm;
726};
727
728/*
729 * Structure should be accessed with sta_lock held. When station addition
730 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
731 * the commands (il_addsta_cmd and il_link_quality_cmd) without
732 * sta_lock held.
733 */
734struct il_station_entry {
735 struct il_addsta_cmd sta;
736 struct il_tid_data tid[MAX_TID_COUNT];
737 u8 used, ctxid;
738 struct il_hw_key keyinfo;
739 struct il_link_quality_cmd *lq;
740};
741
742struct il_station_priv_common {
743 struct il_rxon_context *ctx;
744 u8 sta_id;
745};
746
e94a4099
SG		 747/**
748 * struct il_vif_priv - driver's ilate per-interface information
749 *
750 * When mac80211 allocates a virtual interface, it can allocate
751 * space for us to put data into.
752 */
753struct il_vif_priv {
754 struct il_rxon_context *ctx;
755 u8 ibss_bssid_sta_id;
756};
757
758/* one for each uCode image (inst/data, boot/init/runtime) */
759struct fw_desc {
760 void *v_addr; /* access by driver */
761 dma_addr_t p_addr; /* access by card's busmaster DMA */
762 u32 len; /* bytes */
763};
764
765/* uCode file layout */
766struct il_ucode_header {
e7392364 767 __le32 ver; /* major/minor/API/serial */
e94a4099
SG		 768 struct {
769 __le32 inst_size; /* bytes of runtime code */
770 __le32 data_size; /* bytes of runtime data */
771 __le32 init_size; /* bytes of init code */
772 __le32 init_data_size; /* bytes of init data */
773 __le32 boot_size; /* bytes of bootstrap code */
e7392364 774 u8 data[0]; /* in same order as sizes */
e94a4099
SG		 775 } v1;
776};
777
778struct il4965_ibss_seq {
779 u8 mac[ETH_ALEN];
780 u16 seq_num;
781 u16 frag_num;
782 unsigned long packet_time;
783 struct list_head list;
784};
785
786struct il_sensitivity_ranges {
787 u16 min_nrg_cck;
788 u16 max_nrg_cck;
789
790 u16 nrg_th_cck;
791 u16 nrg_th_ofdm;
792
793 u16 auto_corr_min_ofdm;
794 u16 auto_corr_min_ofdm_mrc;
795 u16 auto_corr_min_ofdm_x1;
796 u16 auto_corr_min_ofdm_mrc_x1;
797
798 u16 auto_corr_max_ofdm;
799 u16 auto_corr_max_ofdm_mrc;
800 u16 auto_corr_max_ofdm_x1;
801 u16 auto_corr_max_ofdm_mrc_x1;
802
803 u16 auto_corr_max_cck;
804 u16 auto_corr_max_cck_mrc;
805 u16 auto_corr_min_cck;
806 u16 auto_corr_min_cck_mrc;
807
808 u16 barker_corr_th_min;
809 u16 barker_corr_th_min_mrc;
810 u16 nrg_th_cca;
811};
812
e94a4099
SG		 813#define KELVIN_TO_CELSIUS(x) ((x)-273)
814#define CELSIUS_TO_KELVIN(x) ((x)+273)
815
e94a4099
SG		 816/**
817 * struct il_hw_params
818 * @max_txq_num: Max # Tx queues supported
819 * @dma_chnl_num: Number of Tx DMA/FIFO channels
820 * @scd_bc_tbls_size: size of scheduler byte count tables
821 * @tfd_size: TFD size
822 * @tx/rx_chains_num: Number of TX/RX chains
823 * @valid_tx/rx_ant: usable antennas
824 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
825 * @max_rxq_log: Log-base-2 of max_rxq_size
826 * @rx_page_order: Rx buffer page order
827 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
828 * @max_stations:
829 * @ht40_channel: is 40MHz width possible in band 2.4
830 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
831 * @sw_crypto: 0 for hw, 1 for sw
832 * @max_xxx_size: for ucode uses
833 * @ct_kill_threshold: temperature threshold
834 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
835 * @struct il_sensitivity_ranges: range of sensitivity values
836 */
837struct il_hw_params {
838 u8 max_txq_num;
839 u8 dma_chnl_num;
840 u16 scd_bc_tbls_size;
841 u32 tfd_size;
e7392364
SG		 842 u8 tx_chains_num;
843 u8 rx_chains_num;
844 u8 valid_tx_ant;
845 u8 valid_rx_ant;
e94a4099
SG		 846 u16 max_rxq_size;
847 u16 max_rxq_log;
848 u32 rx_page_order;
849 u32 rx_wrt_ptr_reg;
e7392364
SG		 850 u8 max_stations;
851 u8 ht40_channel;
852 u8 max_beacon_itrvl; /* in 1024 ms */
e94a4099
SG		 853 u32 max_inst_size;
854 u32 max_data_size;
855 u32 max_bsm_size;
e7392364 856 u32 ct_kill_threshold; /* value in hw-dependent units */
e94a4099
SG		 857 u16 beacon_time_tsf_bits;
858 const struct il_sensitivity_ranges *sens;
859};
860
e94a4099
SG		 861/******************************************************************************
862 *
863 * Functions implemented in core module which are forward declared here
864 * for use by iwl-[4-5].c
865 *
866 * NOTE: The implementation of these functions are not hardware specific
867 * which is why they are in the core module files.
868 *
869 * Naming convention --
870 * il_ <-- Is part of iwlwifi
871 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
872 * il4965_bg_ <-- Called from work queue context
873 * il4965_mac_ <-- mac80211 callback
874 *
875 ****************************************************************************/
876extern void il4965_update_chain_flags(struct il_priv *il);
877extern const u8 il_bcast_addr[ETH_ALEN];
878extern int il_queue_space(const struct il_queue *q);
e7392364
SG		 879static inline int
880il_queue_used(const struct il_queue *q, int i)
e94a4099 881{
e7392364
SG		 882 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
883 i < q->write_ptr) : !(i <
884 q->read_ptr
885 && i >=
886 q->
887 write_ptr);
e94a4099
SG		 888}
889
e7392364
SG		 890static inline u8
891il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
e94a4099
SG		 892{
893 /*
894 * This is for init calibration result and scan command which
895 * required buffer > TFD_MAX_PAYLOAD_SIZE,
896 * the big buffer at end of command array
897 */
898 if (is_huge)
899 return q->n_win; /* must be power of 2 */
900
901 /* Otherwise, use normal size buffers */
902 return idx & (q->n_win - 1);
903}
904
e94a4099
SG		 905struct il_dma_ptr {
906 dma_addr_t dma;
907 void *addr;
908 size_t size;
909};
910
911#define IL_OPERATION_MODE_AUTO 0
912#define IL_OPERATION_MODE_HT_ONLY 1
913#define IL_OPERATION_MODE_MIXED 2
914#define IL_OPERATION_MODE_20MHZ 3
915
916#define IL_TX_CRC_SIZE 4
917#define IL_TX_DELIMITER_SIZE 4
918
919#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
920
921/* Sensitivity and chain noise calibration */
922#define INITIALIZATION_VALUE 0xFFFF
923#define IL4965_CAL_NUM_BEACONS 20
924#define IL_CAL_NUM_BEACONS 16
925#define MAXIMUM_ALLOWED_PATHLOSS 15
926
927#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
928
929#define MAX_FA_OFDM 50
930#define MIN_FA_OFDM 5
931#define MAX_FA_CCK 50
932#define MIN_FA_CCK 5
933
934#define AUTO_CORR_STEP_OFDM 1
935
936#define AUTO_CORR_STEP_CCK 3
937#define AUTO_CORR_MAX_TH_CCK 160
938
939#define NRG_DIFF 2
940#define NRG_STEP_CCK 2
941#define NRG_MARGIN 8
942#define MAX_NUMBER_CCK_NO_FA 100
943
944#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
945
946#define CHAIN_A 0
947#define CHAIN_B 1
948#define CHAIN_C 2
949#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
950#define ALL_BAND_FILTER 0xFF00
951#define IN_BAND_FILTER 0xFF
952#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
953
954#define NRG_NUM_PREV_STAT_L 20
955#define NUM_RX_CHAINS 3
956
957enum il4965_false_alarm_state {
958 IL_FA_TOO_MANY = 0,
959 IL_FA_TOO_FEW = 1,
960 IL_FA_GOOD_RANGE = 2,
961};
962
963enum il4965_chain_noise_state {
e7392364 964 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
e94a4099
SG		 965 IL_CHAIN_NOISE_ACCUMULATE,
966 IL_CHAIN_NOISE_CALIBRATED,
967 IL_CHAIN_NOISE_DONE,
968};
969
970enum il4965_calib_enabled_state {
e7392364 971 IL_CALIB_DISABLED = 0, /* must be 0 */
e94a4099
SG		 972 IL_CALIB_ENABLED = 1,
973};
974
975/*
976 * enum il_calib
977 * defines the order in which results of initial calibrations
978 * should be sent to the runtime uCode
979 */
980enum il_calib {
981 IL_CALIB_MAX,
982};
983
984/* Opaque calibration results */
985struct il_calib_result {
986 void *buf;
987 size_t buf_len;
988};
989
990enum ucode_type {
991 UCODE_NONE = 0,
992 UCODE_INIT,
993 UCODE_RT
994};
995
996/* Sensitivity calib data */
997struct il_sensitivity_data {
998 u32 auto_corr_ofdm;
999 u32 auto_corr_ofdm_mrc;
1000 u32 auto_corr_ofdm_x1;
1001 u32 auto_corr_ofdm_mrc_x1;
1002 u32 auto_corr_cck;
1003 u32 auto_corr_cck_mrc;
1004
1005 u32 last_bad_plcp_cnt_ofdm;
1006 u32 last_fa_cnt_ofdm;
1007 u32 last_bad_plcp_cnt_cck;
1008 u32 last_fa_cnt_cck;
1009
1010 u32 nrg_curr_state;
1011 u32 nrg_prev_state;
1012 u32 nrg_value[10];
e7392364 1013 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
e94a4099
SG		 1014 u32 nrg_silence_ref;
1015 u32 nrg_energy_idx;
1016 u32 nrg_silence_idx;
1017 u32 nrg_th_cck;
1018 s32 nrg_auto_corr_silence_diff;
1019 u32 num_in_cck_no_fa;
1020 u32 nrg_th_ofdm;
1021
1022 u16 barker_corr_th_min;
1023 u16 barker_corr_th_min_mrc;
1024 u16 nrg_th_cca;
1025};
1026
1027/* Chain noise (differential Rx gain) calib data */
1028struct il_chain_noise_data {
1029 u32 active_chains;
1030 u32 chain_noise_a;
1031 u32 chain_noise_b;
1032 u32 chain_noise_c;
1033 u32 chain_signal_a;
1034 u32 chain_signal_b;
1035 u32 chain_signal_c;
1036 u16 beacon_count;
1037 u8 disconn_array[NUM_RX_CHAINS];
1038 u8 delta_gain_code[NUM_RX_CHAINS];
1039 u8 radio_write;
1040 u8 state;
1041};
1042
e7392364 1043#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
e94a4099
SG		 1044#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
1045
1046#define IL_TRAFFIC_ENTRIES (256)
1047#define IL_TRAFFIC_ENTRY_SIZE (64)
1048
1049enum {
1050 MEASUREMENT_READY = (1 << 0),
1051 MEASUREMENT_ACTIVE = (1 << 1),
1052};
1053
1054/* interrupt stats */
1055struct isr_stats {
1056 u32 hw;
1057 u32 sw;
1058 u32 err_code;
1059 u32 sch;
1060 u32 alive;
1061 u32 rfkill;
1062 u32 ctkill;
1063 u32 wakeup;
1064 u32 rx;
1065 u32 handlers[IL_CN_MAX];
1066 u32 tx;
1067 u32 unhandled;
1068};
1069
1070/* management stats */
1071enum il_mgmt_stats {
1072 MANAGEMENT_ASSOC_REQ = 0,
1073 MANAGEMENT_ASSOC_RESP,
1074 MANAGEMENT_REASSOC_REQ,
1075 MANAGEMENT_REASSOC_RESP,
1076 MANAGEMENT_PROBE_REQ,
1077 MANAGEMENT_PROBE_RESP,
1078 MANAGEMENT_BEACON,
1079 MANAGEMENT_ATIM,
1080 MANAGEMENT_DISASSOC,
1081 MANAGEMENT_AUTH,
1082 MANAGEMENT_DEAUTH,
1083 MANAGEMENT_ACTION,
1084 MANAGEMENT_MAX,
1085};
1086/* control stats */
1087enum il_ctrl_stats {
e7392364 1088 CONTROL_BACK_REQ = 0,
e94a4099
SG		 1089 CONTROL_BACK,
1090 CONTROL_PSPOLL,
1091 CONTROL_RTS,
1092 CONTROL_CTS,
1093 CONTROL_ACK,
1094 CONTROL_CFEND,
1095 CONTROL_CFENDACK,
1096 CONTROL_MAX,
1097};
1098
1099struct traffic_stats {
1100#ifdef CONFIG_IWLEGACY_DEBUGFS
1101 u32 mgmt[MANAGEMENT_MAX];
1102 u32 ctrl[CONTROL_MAX];
1103 u32 data_cnt;
1104 u64 data_bytes;
1105#endif
1106};
1107
1108/*
1109 * host interrupt timeout value
1110 * used with setting interrupt coalescing timer
1111 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1112 *
1113 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1114 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1115 */
1116#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1117#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1118#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1119#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1120#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1121#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1122
1123#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1124
1125/* TX queue watchdog timeouts in mSecs */
1126#define IL_DEF_WD_TIMEOUT (2000)
1127#define IL_LONG_WD_TIMEOUT (10000)
1128#define IL_MAX_WD_TIMEOUT (120000)
1129
1130struct il_force_reset {
1131 int reset_request_count;
1132 int reset_success_count;
1133 int reset_reject_count;
1134 unsigned long reset_duration;
1135 unsigned long last_force_reset_jiffies;
1136};
1137
1138/* extend beacon time format bit shifting */
1139/*
1140 * for _3945 devices
1141 * bits 31:24 - extended
1142 * bits 23:0 - interval
1143 */
1144#define IL3945_EXT_BEACON_TIME_POS 24
1145/*
1146 * for _4965 devices
1147 * bits 31:22 - extended
1148 * bits 21:0 - interval
1149 */
1150#define IL4965_EXT_BEACON_TIME_POS 22
1151
1152struct il_rxon_context {
1153 struct ieee80211_vif *vif;
1154
1155 const u8 *ac_to_fifo;
1156 const u8 *ac_to_queue;
1157 u8 mcast_queue;
1158
1159 /*
1160 * We could use the vif to indicate active, but we
1161 * also need it to be active during disabling when
1162 * we already removed the vif for type setting.
1163 */
1164 bool always_active, is_active;
1165
1166 bool ht_need_multiple_chains;
1167
1168 int ctxid;
1169
1170 u32 interface_modes, exclusive_interface_modes;
1171 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1172
1173 /*
1174 * We declare this const so it can only be
1175 * changed via explicit cast within the
1176 * routines that actually update the physical
1177 * hardware.
1178 */
1179 const struct il_rxon_cmd active;
1180 struct il_rxon_cmd staging;
1181
1182 struct il_rxon_time_cmd timing;
1183
1184 struct il_qos_info qos_data;
1185
1186 u8 bcast_sta_id, ap_sta_id;
1187
1188 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
1189 u8 qos_cmd;
1190 u8 wep_key_cmd;
1191
1192 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1193 u8 key_mapping_keys;
1194
1195 __le32 station_flags;
1196
1197 struct {
1198 bool non_gf_sta_present;
1199 u8 protection;
1200 bool enabled, is_40mhz;
1201 u8 extension_chan_offset;
1202 } ht;
1203};
1204
99412002
SG		 1205struct il_power_mgr {
1206 struct il_powertable_cmd sleep_cmd;
1207 struct il_powertable_cmd sleep_cmd_next;
1208 int debug_sleep_level_override;
1209 bool pci_pm;
1210};
1211
e94a4099
SG		 1212struct il_priv {
1213
1214 /* ieee device used by generic ieee processing code */
1215 struct ieee80211_hw *hw;
1216 struct ieee80211_channel *ieee_channels;
1217 struct ieee80211_rate *ieee_rates;
1218 struct il_cfg *cfg;
1219
1220 /* temporary frame storage list */
1221 struct list_head free_frames;
1222 int frames_count;
1223
1224 enum ieee80211_band band;
1225 int alloc_rxb_page;
1226
1722f8e1
SG		 1227 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1228 struct il_rx_buf *rxb);
e94a4099
SG		 1229
1230 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1231
1232 /* spectrum measurement report caching */
1233 struct il_spectrum_notification measure_report;
1234 u8 measurement_status;
1235
1236 /* ucode beacon time */
1237 u32 ucode_beacon_time;
1238 int missed_beacon_threshold;
1239
1240 /* track IBSS manager (last beacon) status */
1241 u32 ibss_manager;
1242
1243 /* force reset */
1244 struct il_force_reset force_reset;
1245
1246 /* we allocate array of il_channel_info for NIC's valid channels.
1247 * Access via channel # using indirect idx array */
1248 struct il_channel_info *channel_info; /* channel info array */
1249 u8 channel_count; /* # of channels */
1250
1251 /* thermal calibration */
1252 s32 temperature; /* degrees Kelvin */
1253 s32 last_temperature;
1254
1255 /* init calibration results */
1256 struct il_calib_result calib_results[IL_CALIB_MAX];
1257
1258 /* Scan related variables */
1259 unsigned long scan_start;
1260 unsigned long scan_start_tsf;
1261 void *scan_cmd;
1262 enum ieee80211_band scan_band;
1263 struct cfg80211_scan_request *scan_request;
1264 struct ieee80211_vif *scan_vif;
1265 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1266 u8 mgmt_tx_ant;
1267
1268 /* spinlock */
1269 spinlock_t lock; /* protect general shared data */
1270 spinlock_t hcmd_lock; /* protect hcmd */
1271 spinlock_t reg_lock; /* protect hw register access */
1272 struct mutex mutex;
1273
1274 /* basic pci-network driver stuff */
1275 struct pci_dev *pci_dev;
1276
1277 /* pci hardware address support */
1278 void __iomem *hw_base;
e7392364
SG		 1279 u32 hw_rev;
1280 u32 hw_wa_rev;
1281 u8 rev_id;
e94a4099
SG		 1282
1283 /* command queue number */
1284 u8 cmd_queue;
1285
1286 /* max number of station keys */
1287 u8 sta_key_max_num;
1288
1289 /* EEPROM MAC addresses */
1290 struct mac_address addresses[1];
1291
1292 /* uCode images, save to reload in case of failure */
e7392364
SG		 1293 int fw_idx; /* firmware we're trying to load */
1294 u32 ucode_ver; /* version of ucode, copy of
1295 il_ucode.ver */
e94a4099
SG		 1296 struct fw_desc ucode_code; /* runtime inst */
1297 struct fw_desc ucode_data; /* runtime data original */
1298 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1299 struct fw_desc ucode_init; /* initialization inst */
1300 struct fw_desc ucode_init_data; /* initialization data */
1301 struct fw_desc ucode_boot; /* bootstrap inst */
1302 enum ucode_type ucode_type;
1303 u8 ucode_write_complete; /* the image write is complete */
1304 char firmware_name[25];
1305
1306 struct il_rxon_context ctx;
1307
1308 __le16 switch_channel;
1309
1310 /* 1st responses from initialize and runtime uCode images.
1311 * _4965's initialize alive response contains some calibration data. */
1312 struct il_init_alive_resp card_alive_init;
1313 struct il_alive_resp card_alive;
1314
1315 u16 active_rate;
1316
1317 u8 start_calib;
1318 struct il_sensitivity_data sensitivity_data;
1319 struct il_chain_noise_data chain_noise_data;
1320 __le16 sensitivity_tbl[HD_TBL_SIZE];
1321
1322 struct il_ht_config current_ht_config;
1323
1324 /* Rate scaling data */
1325 u8 retry_rate;
1326
1327 wait_queue_head_t wait_command_queue;
1328
1329 int activity_timer_active;
1330
1331 /* Rx and Tx DMA processing queues */
1332 struct il_rx_queue rxq;
1333 struct il_tx_queue *txq;
1334 unsigned long txq_ctx_active_msk;
e7392364
SG		 1335 struct il_dma_ptr kw; /* keep warm address */
1336 struct il_dma_ptr scd_bc_tbls;
e94a4099
SG		 1337
1338 u32 scd_base_addr; /* scheduler sram base address */
1339
1340 unsigned long status;
1341
1342 /* counts mgmt, ctl, and data packets */
1343 struct traffic_stats tx_stats;
1344 struct traffic_stats rx_stats;
1345
1346 /* counts interrupts */
1347 struct isr_stats isr_stats;
1348
1349 struct il_power_mgr power_data;
1350
1351 /* context information */
e7392364 1352 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
e94a4099
SG		 1353
1354 /* station table variables */
1355
1356 /* Note: if lock and sta_lock are needed, lock must be acquired first */
1357 spinlock_t sta_lock;
1358 int num_stations;
1359 struct il_station_entry stations[IL_STATION_COUNT];
1360 unsigned long ucode_key_table;
1361
1362 /* queue refcounts */
1363#define IL_MAX_HW_QUEUES 32
1364 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1365 /* for each AC */
1366 atomic_t queue_stop_count[4];
1367
1368 /* Indication if ieee80211_ops->open has been called */
1369 u8 is_open;
1370
1371 u8 mac80211_registered;
1372
1373 /* eeprom -- this is in the card's little endian byte order */
1374 u8 *eeprom;
1375 struct il_eeprom_calib_info *calib_info;
1376
1377 enum nl80211_iftype iw_mode;
1378
1379 /* Last Rx'd beacon timestamp */
1380 u64 timestamp;
1381
1382 union {
1383#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1384 struct {
1385 void *shared_virt;
1386 dma_addr_t shared_phys;
1387
1388 struct delayed_work thermal_periodic;
1389 struct delayed_work rfkill_poll;
1390
1391 struct il3945_notif_stats stats;
1392#ifdef CONFIG_IWLEGACY_DEBUGFS
1393 struct il3945_notif_stats accum_stats;
1394 struct il3945_notif_stats delta_stats;
1395 struct il3945_notif_stats max_delta;
1396#endif
1397
1398 u32 sta_supp_rates;
1399 int last_rx_rssi; /* From Rx packet stats */
1400
1401 /* Rx'd packet timing information */
1402 u32 last_beacon_time;
1403 u64 last_tsf;
1404
1405 /*
1406 * each calibration channel group in the
1407 * EEPROM has a derived clip setting for
1408 * each rate.
1409 */
1410 const struct il3945_clip_group clip_groups[5];
1411
1412 } _3945;
1413#endif
1414#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1415 struct {
1416 struct il_rx_phy_res last_phy_res;
1417 bool last_phy_res_valid;
1418
1419 struct completion firmware_loading_complete;
1420
1421 /*
1422 * chain noise reset and gain commands are the
1423 * two extra calibration commands follows the standard
1424 * phy calibration commands
1425 */
1426 u8 phy_calib_chain_noise_reset_cmd;
1427 u8 phy_calib_chain_noise_gain_cmd;
1428
1429 struct il_notif_stats stats;
1430#ifdef CONFIG_IWLEGACY_DEBUGFS
1431 struct il_notif_stats accum_stats;
1432 struct il_notif_stats delta_stats;
1433 struct il_notif_stats max_delta;
1434#endif
1435
1436 } _4965;
1437#endif
1438 };
1439
1440 struct il_hw_params hw_params;
1441
1442 u32 inta_mask;
1443
1444 struct workqueue_struct *workqueue;
1445
1446 struct work_struct restart;
1447 struct work_struct scan_completed;
1448 struct work_struct rx_replenish;
1449 struct work_struct abort_scan;
1450
1451 struct il_rxon_context *beacon_ctx;
1452 struct sk_buff *beacon_skb;
1453
1454 struct work_struct tx_flush;
1455
1456 struct tasklet_struct irq_tasklet;
1457
1458 struct delayed_work init_alive_start;
1459 struct delayed_work alive_start;
1460 struct delayed_work scan_check;
1461
1462 /* TX Power */
1463 s8 tx_power_user_lmt;
1464 s8 tx_power_device_lmt;
1465 s8 tx_power_next;
1466
e94a4099
SG		 1467#ifdef CONFIG_IWLEGACY_DEBUG
1468 /* debugging info */
e7392364
SG		 1469 u32 debug_level; /* per device debugging will override global
1470 il_debug_level if set */
1471#endif /* CONFIG_IWLEGACY_DEBUG */
e94a4099
SG		 1472#ifdef CONFIG_IWLEGACY_DEBUGFS
1473 /* debugfs */
1474 u16 tx_traffic_idx;
1475 u16 rx_traffic_idx;
1476 u8 *tx_traffic;
1477 u8 *rx_traffic;
1478 struct dentry *debugfs_dir;
1479 u32 dbgfs_sram_offset, dbgfs_sram_len;
1480 bool disable_ht40;
e7392364 1481#endif /* CONFIG_IWLEGACY_DEBUGFS */
e94a4099
SG		 1482
1483 struct work_struct txpower_work;
1484 u32 disable_sens_cal;
1485 u32 disable_chain_noise_cal;
1486 u32 disable_tx_power_cal;
1487 struct work_struct run_time_calib_work;
1488 struct timer_list stats_periodic;
1489 struct timer_list watchdog;
1490 bool hw_ready;
1491
1492 struct led_classdev led;
1493 unsigned long blink_on, blink_off;
1494 bool led_registered;
e7392364 1495}; /*il_priv */
e94a4099 1496
e7392364
SG		 1497static inline void
1498il_txq_ctx_activate(struct il_priv *il, int txq_id)
e94a4099
SG		 1499{
1500 set_bit(txq_id, &il->txq_ctx_active_msk);
1501}
1502
e7392364
SG		 1503static inline void
1504il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
e94a4099
SG		 1505{
1506 clear_bit(txq_id, &il->txq_ctx_active_msk);
1507}
1508
e94a4099 1509static inline struct ieee80211_hdr *
e7392364 1510il_tx_queue_get_hdr(struct il_priv *il, int txq_id, int idx)
e94a4099
SG		 1511{
1512 if (il->txq[txq_id].txb[idx].skb)
e7392364
SG		 1513 return (struct ieee80211_hdr *)il->txq[txq_id].txb[idx].skb->
1514 data;
e94a4099
SG		 1515 return NULL;
1516}
1517
1518static inline struct il_rxon_context *
1519il_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1520{
1521 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1522
1523 return vif_priv->ctx;
1524}
1525
1526#define for_each_context(il, _ctx) \
1527 for (_ctx = &il->ctx; _ctx == &il->ctx; _ctx++)
1528
e7392364
SG		 1529static inline int
1530il_is_associated(struct il_priv *il)
e94a4099
SG		 1531{
1532 return (il->ctx.active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1533}
1534
e7392364
SG		 1535static inline int
1536il_is_any_associated(struct il_priv *il)
e94a4099
SG		 1537{
1538 return il_is_associated(il);
1539}
1540
e7392364
SG		 1541static inline int
1542il_is_associated_ctx(struct il_rxon_context *ctx)
e94a4099
SG		 1543{
1544 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1545}
1546
e7392364
SG		 1547static inline int
1548il_is_channel_valid(const struct il_channel_info *ch_info)
e94a4099
SG		 1549{
1550 if (ch_info == NULL)
1551 return 0;
1552 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1553}
1554
e7392364
SG		 1555static inline int
1556il_is_channel_radar(const struct il_channel_info *ch_info)
e94a4099
SG		 1557{
1558 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1559}
1560
e7392364
SG		 1561static inline u8
1562il_is_channel_a_band(const struct il_channel_info *ch_info)
e94a4099
SG		 1563{
1564 return ch_info->band == IEEE80211_BAND_5GHZ;
1565}
1566
1567static inline int
1568il_is_channel_passive(const struct il_channel_info *ch)
1569{
1570 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1571}
1572
1573static inline int
1574il_is_channel_ibss(const struct il_channel_info *ch)
1575{
1576 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1577}
be663ab6 1578
e94a4099
SG		 1579static inline void
1580__il_free_pages(struct il_priv *il, struct page *page)
1581{
1582 __free_pages(page, il->hw_params.rx_page_order);
1583 il->alloc_rxb_page--;
1584}
1585
e7392364
SG		 1586static inline void
1587il_free_pages(struct il_priv *il, unsigned long page)
e94a4099
SG		 1588{
1589 free_pages(page, il->hw_params.rx_page_order);
1590 il->alloc_rxb_page--;
1591}
be663ab6
WYG		 1592
1593#define IWLWIFI_VERSION "in-tree:"
1594#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1595#define DRV_AUTHOR "<ilw@linux.intel.com>"
1596
e2ebc833 1597#define IL_PCI_DEVICE(dev, subdev, cfg) \
be663ab6
WYG		 1598 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1599 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1600 .driver_data = (kernel_ulong_t)&(cfg)
1601
1602#define TIME_UNIT 1024
1603
e2ebc833
SG		 1604#define IL_SKU_G 0x1
1605#define IL_SKU_A 0x2
1606#define IL_SKU_N 0x8
be663ab6 1607
e2ebc833 1608#define IL_CMD(x) case x: return #x
be663ab6 1609
e94a4099 1610/* Size of one Rx buffer in host DRAM */
e7392364 1611#define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
e94a4099
SG		 1612#define IL_RX_BUF_SIZE_4K (4 * 1024)
1613#define IL_RX_BUF_SIZE_8K (8 * 1024)
1614
e2ebc833 1615struct il_hcmd_ops {
1722f8e1
SG		 1616 int (*rxon_assoc) (struct il_priv *il, struct il_rxon_context *ctx);
1617 int (*commit_rxon) (struct il_priv *il, struct il_rxon_context *ctx);
1618 void (*set_rxon_chain) (struct il_priv *il,
1619 struct il_rxon_context *ctx);
be663ab6
WYG		 1620};
1621
e2ebc833 1622struct il_hcmd_utils_ops {
e7392364 1623 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1722f8e1
SG		 1624 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1625 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1626 void (*post_scan) (struct il_priv *il);
be663ab6
WYG		 1627};
1628
e2ebc833 1629struct il_apm_ops {
1722f8e1
SG		 1630 int (*init) (struct il_priv *il);
1631 void (*config) (struct il_priv *il);
be663ab6
WYG		 1632};
1633
9b5e2f46 1634#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1635struct il_debugfs_ops {
1722f8e1
SG		 1636 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1637 size_t count, loff_t *ppos);
1638 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1639 size_t count, loff_t *ppos);
1640 ssize_t(*general_stats_read) (struct file *file,
1641 char __user *user_buf, size_t count,
1642 loff_t *ppos);
be663ab6 1643};
9b5e2f46 1644#endif
be663ab6 1645
e2ebc833 1646struct il_temp_ops {
1722f8e1 1647 void (*temperature) (struct il_priv *il);
be663ab6
WYG		 1648};
1649
e2ebc833 1650struct il_lib_ops {
be663ab6 1651 /* set hw dependent parameters */
1722f8e1 1652 int (*set_hw_params) (struct il_priv *il);
be663ab6 1653 /* Handling TX */
1722f8e1
SG		 1654 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1655 struct il_tx_queue *txq,
e7392364 1656 u16 byte_cnt);
1722f8e1
SG		 1657 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1658 struct il_tx_queue *txq, dma_addr_t addr,
e7392364 1659 u16 len, u8 reset, u8 pad);
1722f8e1
SG		 1660 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1661 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
be663ab6 1662 /* setup Rx handler */
1722f8e1 1663 void (*handler_setup) (struct il_priv *il);
be663ab6 1664 /* alive notification after init uCode load */
1722f8e1 1665 void (*init_alive_start) (struct il_priv *il);
be663ab6 1666 /* check validity of rtc data address */
e7392364 1667 int (*is_valid_rtc_data_addr) (u32 addr);
be663ab6 1668 /* 1st ucode load */
1722f8e1 1669 int (*load_ucode) (struct il_priv *il);
1ba2f121 1670
1722f8e1
SG		 1671 void (*dump_nic_error_log) (struct il_priv *il);
1672 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1673 int (*set_channel_switch) (struct il_priv *il,
1674 struct ieee80211_channel_switch *ch_switch);
be663ab6 1675 /* power management */
e2ebc833 1676 struct il_apm_ops apm_ops;
be663ab6
WYG		 1677
1678 /* power */
1722f8e1
SG		 1679 int (*send_tx_power) (struct il_priv *il);
1680 void (*update_chain_flags) (struct il_priv *il);
be663ab6 1681
47ef694d 1682 /* eeprom operations */
e2ebc833 1683 struct il_eeprom_ops eeprom_ops;
be663ab6
WYG		 1684
1685 /* temperature */
e2ebc833 1686 struct il_temp_ops temp_ops;
be663ab6 1687
9b5e2f46 1688#ifdef CONFIG_IWLEGACY_DEBUGFS
e2ebc833 1689 struct il_debugfs_ops debugfs_ops;
9b5e2f46 1690#endif
be663ab6
WYG		 1691
1692};
1693
e2ebc833 1694struct il_led_ops {
1722f8e1 1695 int (*cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
be663ab6
WYG		 1696};
1697
e2ebc833 1698struct il_legacy_ops {
1722f8e1
SG		 1699 void (*post_associate) (struct il_priv *il);
1700 void (*config_ap) (struct il_priv *il);
be663ab6 1701 /* station management */
1722f8e1
SG		 1702 int (*update_bcast_stations) (struct il_priv *il);
1703 int (*manage_ibss_station) (struct il_priv *il,
1704 struct ieee80211_vif *vif, bool add);
be663ab6
WYG		 1705};
1706
e2ebc833
SG		 1707struct il_ops {
1708 const struct il_lib_ops *lib;
1709 const struct il_hcmd_ops *hcmd;
1710 const struct il_hcmd_utils_ops *utils;
1711 const struct il_led_ops *led;
1712 const struct il_nic_ops *nic;
1713 const struct il_legacy_ops *legacy;
be663ab6
WYG		 1714 const struct ieee80211_ops *ieee80211_ops;
1715};
1716
e2ebc833 1717struct il_mod_params {
be663ab6
WYG		 1718 int sw_crypto; /* def: 0 = using hardware encryption */
1719 int disable_hw_scan; /* def: 0 = use h/w scan */
1720 int num_of_queues; /* def: HW dependent */
1721 int disable_11n; /* def: 0 = 11n capabilities enabled */
1722 int amsdu_size_8K; /* def: 1 = enable 8K amsdu size */
e7392364 1723 int antenna; /* def: 0 = both antennas (use diversity) */
be663ab6
WYG		 1724 int restart_fw; /* def: 1 = restart firmware */
1725};
1726
1727/*
1728 * @led_compensation: compensate on the led on/off time per HW according
1729 * to the deviation to achieve the desired led frequency.
47ef694d 1730 * The detail algorithm is described in common.c
be663ab6 1731 * @chain_noise_num_beacons: number of beacons used to compute chain noise
be663ab6
WYG		 1732 * @wd_timeout: TX queues watchdog timeout
1733 * @temperature_kelvin: temperature report by uCode in kelvin
be663ab6
WYG		 1734 * @ucode_tracing: support ucode continuous tracing
1735 * @sensitivity_calib_by_driver: driver has the capability to perform
1736 * sensitivity calibration operation
1737 * @chain_noise_calib_by_driver: driver has the capability to perform
1738 * chain noise calibration operation
1739 */
e2ebc833 1740struct il_base_params {
be663ab6
WYG		 1741 int eeprom_size;
1742 int num_of_queues; /* def: HW dependent */
e7392364 1743 int num_of_ampdu_queues; /* def: HW dependent */
e2ebc833 1744 /* for il_apm_init() */
be663ab6
WYG		 1745 u32 pll_cfg_val;
1746 bool set_l0s;
1747 bool use_bsm;
1748
1749 u16 led_compensation;
1750 int chain_noise_num_beacons;
be663ab6
WYG		 1751 unsigned int wd_timeout;
1752 bool temperature_kelvin;
be663ab6
WYG		 1753 const bool ucode_tracing;
1754 const bool sensitivity_calib_by_driver;
1755 const bool chain_noise_calib_by_driver;
1756};
1757
47ef694d
SG		 1758#define IL_LED_SOLID 11
1759#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1760
1761#define IL_LED_ACTIVITY (0<<1)
1762#define IL_LED_LINK (1<<1)
1763
1764/*
1765 * LED mode
1766 * IL_LED_DEFAULT: use device default
1767 * IL_LED_RF_STATE: turn LED on/off based on RF state
1768 * LED ON = RF ON
1769 * LED OFF = RF OFF
1770 * IL_LED_BLINK: adjust led blink rate based on blink table
1771 */
1772enum il_led_mode {
1773 IL_LED_DEFAULT,
1774 IL_LED_RF_STATE,
1775 IL_LED_BLINK,
1776};
1777
1778void il_leds_init(struct il_priv *il);
1779void il_leds_exit(struct il_priv *il);
1780
be663ab6 1781/**
e2ebc833 1782 * struct il_cfg
be663ab6
WYG		 1783 * @fw_name_pre: Firmware filename prefix. The api version and extension
1784 * (.ucode) will be added to filename before loading from disk. The
1785 * filename is constructed as fw_name_pre<api>.ucode.
1786 * @ucode_api_max: Highest version of uCode API supported by driver.
1787 * @ucode_api_min: Lowest version of uCode API supported by driver.
1788 * @scan_antennas: available antenna for scan operation
1789 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1790 *
1791 * We enable the driver to be backward compatible wrt API version. The
1792 * driver specifies which APIs it supports (with @ucode_api_max being the
1793 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1794 * it has a supported API version. The firmware's API version will be
e2ebc833 1795 * stored in @il_priv, enabling the driver to make runtime changes based
be663ab6
WYG		 1796 * on firmware version used.
1797 *
1798 * For example,
46bc8d4b 1799 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
be663ab6
WYG		 1800 * Driver interacts with Firmware API version >= 2.
1801 * } else {
1802 * Driver interacts with Firmware API version 1.
1803 * }
1804 *
1805 * The ideal usage of this infrastructure is to treat a new ucode API
1806 * release as a new hardware revision. That is, through utilizing the
e2ebc833 1807 * il_hcmd_utils_ops etc. we accommodate different command structures
be663ab6
WYG		 1808 * and flows between hardware versions as well as their API
1809 * versions.
1810 *
1811 */
e2ebc833 1812struct il_cfg {
be663ab6
WYG		 1813 /* params specific to an individual device within a device family */
1814 const char *name;
1815 const char *fw_name_pre;
1816 const unsigned int ucode_api_max;
1817 const unsigned int ucode_api_min;
e7392364
SG		 1818 u8 valid_tx_ant;
1819 u8 valid_rx_ant;
be663ab6 1820 unsigned int sku;
e7392364
SG		 1821 u16 eeprom_ver;
1822 u16 eeprom_calib_ver;
e2ebc833 1823 const struct il_ops *ops;
be663ab6 1824 /* module based parameters which can be set from modprobe cmd */
e2ebc833 1825 const struct il_mod_params *mod_params;
be663ab6 1826 /* params not likely to change within a device family */
e2ebc833 1827 struct il_base_params *base_params;
be663ab6
WYG		 1828 /* params likely to change within a device family */
1829 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
e2ebc833 1830 enum il_led_mode led_mode;
be663ab6
WYG		 1831};
1832
1833/***************************
1834 * L i b *
1835 ***************************/
1836
e2ebc833 1837struct ieee80211_hw *il_alloc_all(struct il_cfg *cfg);
e7392364
SG		 1838int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1839 u16 queue, const struct ieee80211_tx_queue_params *params);
e2ebc833 1840int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
e7392364
SG		 1841
1842void il_set_rxon_hwcrypto(struct il_priv *il, struct il_rxon_context *ctx,
1843 int hw_decrypt);
1844int il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx);
1845int il_full_rxon_required(struct il_priv *il, struct il_rxon_context *ctx);
1846int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
e2ebc833 1847 struct il_rxon_context *ctx);
e7392364
SG		 1848void il_set_flags_for_band(struct il_priv *il, struct il_rxon_context *ctx,
1849 enum ieee80211_band band, struct ieee80211_vif *vif);
1850u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1851void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1852bool il_is_ht40_tx_allowed(struct il_priv *il, struct il_rxon_context *ctx,
1853 struct ieee80211_sta_ht_cap *ht_cap);
46bc8d4b 1854void il_connection_init_rx_config(struct il_priv *il,
e7392364 1855 struct il_rxon_context *ctx);
46bc8d4b 1856void il_set_rate(struct il_priv *il);
e7392364
SG		 1857int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1858 u32 decrypt_res, struct ieee80211_rx_status *stats);
46bc8d4b 1859void il_irq_handle_error(struct il_priv *il);
e7392364 1860int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
e2ebc833 1861void il_mac_remove_interface(struct ieee80211_hw *hw,
e7392364
SG		 1862 struct ieee80211_vif *vif);
1863int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1864 enum nl80211_iftype newtype, bool newp2p);
46bc8d4b
SG		 1865int il_alloc_txq_mem(struct il_priv *il);
1866void il_txq_mem(struct il_priv *il);
be663ab6 1867
d3175167 1868#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b
SG		 1869int il_alloc_traffic_mem(struct il_priv *il);
1870void il_free_traffic_mem(struct il_priv *il);
1871void il_reset_traffic_log(struct il_priv *il);
e7392364
SG		 1872void il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1873 struct ieee80211_hdr *header);
1874void il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1875 struct ieee80211_hdr *header);
e2ebc833
SG		 1876const char *il_get_mgmt_string(int cmd);
1877const char *il_get_ctrl_string(int cmd);
46bc8d4b 1878void il_clear_traffic_stats(struct il_priv *il);
e7392364 1879void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
be663ab6 1880#else
e7392364
SG		 1881static inline int
1882il_alloc_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1883{
1884 return 0;
1885}
e7392364
SG		 1886
1887static inline void
1888il_free_traffic_mem(struct il_priv *il)
be663ab6
WYG		 1889{
1890}
e7392364
SG		 1891
1892static inline void
1893il_reset_traffic_log(struct il_priv *il)
be663ab6
WYG		 1894{
1895}
e7392364
SG		 1896
1897static inline void
1898il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
1899 struct ieee80211_hdr *header)
be663ab6
WYG		 1900{
1901}
e7392364
SG		 1902
1903static inline void
1904il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
1905 struct ieee80211_hdr *header)
be663ab6
WYG		 1906{
1907}
e7392364
SG		 1908
1909static inline void
1910il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6
WYG		 1911{
1912}
1913#endif
1914/*****************************************************
1915 * RX handlers.
1916 * **************************************************/
e7392364
SG		 1917void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1918void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1919void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1920
1921/*****************************************************
1922* RX
1923******************************************************/
46bc8d4b
SG		 1924void il_cmd_queue_unmap(struct il_priv *il);
1925void il_cmd_queue_free(struct il_priv *il);
1926int il_rx_queue_alloc(struct il_priv *il);
e7392364 1927void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
e2ebc833 1928int il_rx_queue_space(const struct il_rx_queue *q);
e7392364 1929void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6 1930/* Handlers */
e7392364
SG		 1931void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1932void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
46bc8d4b 1933void il_chswitch_done(struct il_priv *il, bool is_success);
d2dfb33e 1934void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
be663ab6
WYG		 1935
1936/* TX helpers */
1937
1938/*****************************************************
1939* TX
1940******************************************************/
e7392364
SG		 1941void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1942int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
1943 u32 txq_id);
1944void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
1945 int slots_num, u32 txq_id);
46bc8d4b
SG		 1946void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1947void il_tx_queue_free(struct il_priv *il, int txq_id);
1948void il_setup_watchdog(struct il_priv *il);
be663ab6
WYG		 1949/*****************************************************
1950 * TX power
1951 ****************************************************/
46bc8d4b 1952int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
be663ab6
WYG		 1953
1954/*******************************************************************************
1955 * Rate
1956 ******************************************************************************/
1957
e7392364 1958u8 il_get_lowest_plcp(struct il_priv *il, struct il_rxon_context *ctx);
be663ab6
WYG		 1959
1960/*******************************************************************************
1961 * Scanning
1962 ******************************************************************************/
46bc8d4b
SG		 1963void il_init_scan_params(struct il_priv *il);
1964int il_scan_cancel(struct il_priv *il);
1965int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1966void il_force_scan_end(struct il_priv *il);
e7392364
SG		 1967int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1968 struct cfg80211_scan_request *req);
46bc8d4b
SG		 1969void il_internal_short_hw_scan(struct il_priv *il);
1970int il_force_reset(struct il_priv *il, bool external);
e7392364 1971u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1972 const u8 *ta, const u8 *ie, int ie_len, int left);
46bc8d4b 1973void il_setup_rx_scan_handlers(struct il_priv *il);
e7392364
SG		 1974u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1975 u8 n_probes);
1976u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1977 struct ieee80211_vif *vif);
46bc8d4b
SG		 1978void il_setup_scan_deferred_work(struct il_priv *il);
1979void il_cancel_scan_deferred_work(struct il_priv *il);
be663ab6
WYG		 1980
1981/* For faster active scanning, scan will move to the next channel if fewer than
1982 * PLCP_QUIET_THRESH packets are heard on this channel within
1983 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
1984 * time if it's a quiet channel (nothing responded to our probe, and there's
1985 * no other traffic).
1986 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
e7392364
SG		 1987#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */
1988#define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */
be663ab6 1989
e2ebc833 1990#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
be663ab6
WYG		 1991
1992/*****************************************************
1993 * S e n d i n g H o s t C o m m a n d s *
1994 *****************************************************/
1995
e2ebc833 1996const char *il_get_cmd_string(u8 cmd);
e7392364 1997int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
46bc8d4b 1998int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
e7392364
SG		 1999int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
2000 const void *data);
2001int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 2002 void (*callback) (struct il_priv *il,
2003 struct il_device_cmd *cmd,
2004 struct il_rx_pkt *pkt));
be663ab6 2005
46bc8d4b 2006int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
be663ab6 2007
be663ab6
WYG		 2008/*****************************************************
2009 * PCI *
2010 *****************************************************/
2011
e7392364
SG		 2012static inline u16
2013il_pcie_link_ctl(struct il_priv *il)
be663ab6
WYG		 2014{
2015 int pos;
2016 u16 pci_lnk_ctl;
46bc8d4b
SG		 2017 pos = pci_pcie_cap(il->pci_dev);
2018 pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
be663ab6
WYG		 2019 return pci_lnk_ctl;
2020}
2021
e2ebc833 2022void il_bg_watchdog(unsigned long data);
e7392364
SG		 2023u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
2024__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
2025 u32 beacon_interval);
be663ab6
WYG		 2026
2027#ifdef CONFIG_PM
e2ebc833
SG		 2028int il_pci_suspend(struct device *device);
2029int il_pci_resume(struct device *device);
2030extern const struct dev_pm_ops il_pm_ops;
be663ab6 2031
e2ebc833 2032#define IL_LEGACY_PM_OPS (&il_pm_ops)
be663ab6
WYG		 2033
2034#else /* !CONFIG_PM */
2035
e2ebc833 2036#define IL_LEGACY_PM_OPS NULL
be663ab6
WYG		 2037
2038#endif /* !CONFIG_PM */
2039
2040/*****************************************************
2041* Error Handling Debugging
2042******************************************************/
46bc8d4b 2043void il4965_dump_nic_error_log(struct il_priv *il);
d3175167 2044#ifdef CONFIG_IWLEGACY_DEBUG
e7392364 2045void il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx);
be663ab6 2046#else
e7392364
SG		 2047static inline void
2048il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG		 2049{
2050}
2051#endif
2052
46bc8d4b 2053void il_clear_isr_stats(struct il_priv *il);
be663ab6
WYG		 2054
2055/*****************************************************
2056* GEOS
2057******************************************************/
46bc8d4b
SG		 2058int il_init_geos(struct il_priv *il);
2059void il_free_geos(struct il_priv *il);
be663ab6
WYG		 2060
2061/*************** DRIVER STATUS FUNCTIONS *****/
2062
a6766ccd
SG		 2063#define S_HCMD_ACTIVE 0 /* host command in progress */
2064/* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
2065#define S_INT_ENABLED 2
2066#define S_RF_KILL_HW 3
2067#define S_CT_KILL 4
2068#define S_INIT 5
2069#define S_ALIVE 6
2070#define S_READY 7
2071#define S_TEMPERATURE 8
2072#define S_GEO_CONFIGURED 9
2073#define S_EXIT_PENDING 10
db7746f7 2074#define S_STATS 12
a6766ccd
SG		 2075#define S_SCANNING 13
2076#define S_SCAN_ABORTING 14
2077#define S_SCAN_HW 15
2078#define S_POWER_PMI 16
2079#define S_FW_ERROR 17
2080#define S_CHANNEL_SWITCH_PENDING 18
be663ab6 2081
e7392364
SG		 2082static inline int
2083il_is_ready(struct il_priv *il)
be663ab6
WYG		 2084{
2085 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
2086 * set but EXIT_PENDING is not */
a6766ccd 2087 return test_bit(S_READY, &il->status) &&
e7392364
SG		 2088 test_bit(S_GEO_CONFIGURED, &il->status) &&
2089 !test_bit(S_EXIT_PENDING, &il->status);
be663ab6
WYG		 2090}
2091
e7392364
SG		 2092static inline int
2093il_is_alive(struct il_priv *il)
be663ab6 2094{
a6766ccd 2095 return test_bit(S_ALIVE, &il->status);
be663ab6
WYG		 2096}
2097
e7392364
SG		 2098static inline int
2099il_is_init(struct il_priv *il)
be663ab6 2100{
a6766ccd 2101 return test_bit(S_INIT, &il->status);
be663ab6
WYG		 2102}
2103
e7392364
SG		 2104static inline int
2105il_is_rfkill_hw(struct il_priv *il)
be663ab6 2106{
a6766ccd 2107 return test_bit(S_RF_KILL_HW, &il->status);
be663ab6
WYG		 2108}
2109
e7392364
SG		 2110static inline int
2111il_is_rfkill(struct il_priv *il)
be663ab6 2112{
46bc8d4b 2113 return il_is_rfkill_hw(il);
be663ab6
WYG		 2114}
2115
e7392364
SG		 2116static inline int
2117il_is_ctkill(struct il_priv *il)
be663ab6 2118{
a6766ccd 2119 return test_bit(S_CT_KILL, &il->status);
be663ab6
WYG		 2120}
2121
e7392364
SG		 2122static inline int
2123il_is_ready_rf(struct il_priv *il)
be663ab6
WYG		 2124{
2125
46bc8d4b 2126 if (il_is_rfkill(il))
be663ab6
WYG		 2127 return 0;
2128
46bc8d4b 2129 return il_is_ready(il);
be663ab6
WYG		 2130}
2131
46bc8d4b 2132extern void il_send_bt_config(struct il_priv *il);
e7392364 2133extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
46bc8d4b
SG		 2134void il_apm_stop(struct il_priv *il);
2135int il_apm_init(struct il_priv *il);
be663ab6 2136
e7392364
SG		 2137int il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx);
2138static inline int
2139il_send_rxon_assoc(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 2140{
46bc8d4b 2141 return il->cfg->ops->hcmd->rxon_assoc(il, ctx);
be663ab6 2142}
e7392364
SG		 2143
2144static inline int
2145il_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 2146{
46bc8d4b 2147 return il->cfg->ops->hcmd->commit_rxon(il, ctx);
be663ab6 2148}
e7392364
SG		 2149
2150static inline const struct ieee80211_supported_band *
2151il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
be663ab6 2152{
46bc8d4b 2153 return il->hw->wiphy->bands[band];
be663ab6
WYG		 2154}
2155
be663ab6 2156/* mac80211 handlers */
e2ebc833 2157int il_mac_config(struct ieee80211_hw *hw, u32 changed);
e7392364
SG		 2158void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
2159void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2160 struct ieee80211_bss_conf *bss_conf, u32 changes);
2161void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 2162 __le16 fc, __le32 *tx_flags);
be663ab6 2163
e2ebc833 2164irqreturn_t il_isr(int irq, void *data);
be663ab6 2165
e94a4099
SG		 2166#include <linux/io.h>
2167
e7392364
SG		 2168static inline void
2169_il_write8(struct il_priv *il, u32 ofs, u8 val)
e94a4099
SG		 2170{
2171 iowrite8(val, il->hw_base + ofs);
2172}
2173#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2174
e7392364
SG		 2175static inline void
2176_il_wr(struct il_priv *il, u32 ofs, u32 val)
e94a4099
SG		 2177{
2178 iowrite32(val, il->hw_base + ofs);
2179}
2180
e7392364
SG		 2181static inline u32
2182_il_rd(struct il_priv *il, u32 ofs)
e94a4099
SG		 2183{
2184 return ioread32(il->hw_base + ofs);
2185}
2186
2187#define IL_POLL_INTERVAL 10 /* microseconds */
2188static inline int
e7392364 2189_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
e94a4099
SG		 2190{
2191 int t = 0;
2192
2193 do {
2194 if ((_il_rd(il, addr) & mask) == (bits & mask))
2195 return t;
2196 udelay(IL_POLL_INTERVAL);
2197 t += IL_POLL_INTERVAL;
1722f8e1 2198 } while (t < timeout);
e94a4099
SG		 2199
2200 return -ETIMEDOUT;
2201}
2202
e7392364
SG		 2203static inline void
2204_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
e94a4099
SG		 2205{
2206 _il_wr(il, reg, _il_rd(il, reg) | mask);
2207}
2208
e7392364
SG		 2209static inline void
2210il_set_bit(struct il_priv *p, u32 r, u32 m)
e94a4099
SG		 2211{
2212 unsigned long reg_flags;
2213
2214 spin_lock_irqsave(&p->reg_lock, reg_flags);
2215 _il_set_bit(p, r, m);
2216 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
2217}
2218
2219static inline void
2220_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2221{
2222 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2223}
2224
e7392364
SG		 2225static inline void
2226il_clear_bit(struct il_priv *p, u32 r, u32 m)
e94a4099
SG		 2227{
2228 unsigned long reg_flags;
2229
2230 spin_lock_irqsave(&p->reg_lock, reg_flags);
2231 _il_clear_bit(p, r, m);
2232 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
2233}
2234
e7392364
SG		 2235static inline int
2236_il_grab_nic_access(struct il_priv *il)
e94a4099
SG		 2237{
2238 int ret;
2239 u32 val;
2240
2241 /* this bit wakes up the NIC */
e7392364 2242 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
e94a4099
SG		 2243
2244 /*
2245 * These bits say the device is running, and should keep running for
2246 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2247 * but they do not indicate that embedded SRAM is restored yet;
2248 * 3945 and 4965 have volatile SRAM, and must save/restore contents
2249 * to/from host DRAM when sleeping/waking for power-saving.
2250 * Each direction takes approximately 1/4 millisecond; with this
2251 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2252 * series of register accesses are expected (e.g. reading Event Log),
2253 * to keep device from sleeping.
2254 *
2255 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2256 * SRAM is okay/restored. We don't check that here because this call
2257 * is just for hardware register access; but GP1 MAC_SLEEP check is a
2258 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
2259 *
2260 */
e7392364
SG		 2261 ret =
2262 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
2263 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2264 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
e94a4099
SG		 2265 if (ret < 0) {
2266 val = _il_rd(il, CSR_GP_CNTRL);
e7392364
SG		 2267 IL_ERR("MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
2268 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
e94a4099
SG		 2269 return -EIO;
2270 }
2271
2272 return 0;
2273}
2274
e7392364
SG		 2275static inline void
2276_il_release_nic_access(struct il_priv *il)
e94a4099 2277{
e7392364 2278 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
e94a4099
SG		 2279}
2280
e7392364
SG		 2281static inline u32
2282il_rd(struct il_priv *il, u32 reg)
e94a4099
SG		 2283{
2284 u32 value;
2285 unsigned long reg_flags;
2286
2287 spin_lock_irqsave(&il->reg_lock, reg_flags);
2288 _il_grab_nic_access(il);
2289 value = _il_rd(il, reg);
2290 _il_release_nic_access(il);
2291 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2292 return value;
2293
2294}
2295
2296static inline void
2297il_wr(struct il_priv *il, u32 reg, u32 value)
2298{
2299 unsigned long reg_flags;
2300
2301 spin_lock_irqsave(&il->reg_lock, reg_flags);
2302 if (!_il_grab_nic_access(il)) {
2303 _il_wr(il, reg, value);
2304 _il_release_nic_access(il);
2305 }
2306 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2307}
2308
e7392364
SG		 2309static inline void
2310il_write_reg_buf(struct il_priv *il, u32 reg, u32 len, u32 * values)
e94a4099
SG		 2311{
2312 u32 count = sizeof(u32);
2313
2314 if (il != NULL && values != NULL) {
2315 for (; 0 < len; len -= count, reg += count, values++)
2316 il_wr(il, reg, *values);
2317 }
2318}
2319
e7392364
SG		 2320static inline int
2321il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
e94a4099
SG		 2322{
2323 int t = 0;
2324
2325 do {
2326 if ((il_rd(il, addr) & mask) == mask)
2327 return t;
2328 udelay(IL_POLL_INTERVAL);
2329 t += IL_POLL_INTERVAL;
1722f8e1 2330 } while (t < timeout);
e94a4099
SG		 2331
2332 return -ETIMEDOUT;
2333}
2334
e7392364
SG		 2335static inline u32
2336_il_rd_prph(struct il_priv *il, u32 reg)
e94a4099
SG		 2337{
2338 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2339 rmb();
2340 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2341}
2342
e7392364
SG		 2343static inline u32
2344il_rd_prph(struct il_priv *il, u32 reg)
e94a4099
SG		 2345{
2346 unsigned long reg_flags;
2347 u32 val;
2348
2349 spin_lock_irqsave(&il->reg_lock, reg_flags);
2350 _il_grab_nic_access(il);
2351 val = _il_rd_prph(il, reg);
2352 _il_release_nic_access(il);
2353 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2354 return val;
2355}
2356
e7392364
SG		 2357static inline void
2358_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
e94a4099 2359{
e7392364 2360 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
e94a4099
SG		 2361 wmb();
2362 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2363}
2364
2365static inline void
2366il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2367{
2368 unsigned long reg_flags;
2369
2370 spin_lock_irqsave(&il->reg_lock, reg_flags);
2371 if (!_il_grab_nic_access(il)) {
2372 _il_wr_prph(il, addr, val);
2373 _il_release_nic_access(il);
2374 }
2375 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2376}
2377
2378#define _il_set_bits_prph(il, reg, mask) \
2379_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask))
2380
2381static inline void
2382il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2383{
2384 unsigned long reg_flags;
2385
2386 spin_lock_irqsave(&il->reg_lock, reg_flags);
2387 _il_grab_nic_access(il);
2388 _il_set_bits_prph(il, reg, mask);
2389 _il_release_nic_access(il);
2390 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2391}
2392
2393#define _il_set_bits_mask_prph(il, reg, bits, mask) \
2394_il_wr_prph(il, reg, \
2395 ((_il_rd_prph(il, reg) & mask) | bits))
2396
e7392364
SG		 2397static inline void
2398il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
e94a4099
SG		 2399{
2400 unsigned long reg_flags;
2401
2402 spin_lock_irqsave(&il->reg_lock, reg_flags);
2403 _il_grab_nic_access(il);
2404 _il_set_bits_mask_prph(il, reg, bits, mask);
2405 _il_release_nic_access(il);
2406 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2407}
2408
e7392364
SG		 2409static inline void
2410il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
e94a4099
SG		 2411{
2412 unsigned long reg_flags;
2413 u32 val;
2414
2415 spin_lock_irqsave(&il->reg_lock, reg_flags);
2416 _il_grab_nic_access(il);
2417 val = _il_rd_prph(il, reg);
2418 _il_wr_prph(il, reg, (val & ~mask));
2419 _il_release_nic_access(il);
2420 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2421}
2422
e7392364
SG		 2423static inline u32
2424il_read_targ_mem(struct il_priv *il, u32 addr)
e94a4099
SG		 2425{
2426 unsigned long reg_flags;
2427 u32 value;
2428
2429 spin_lock_irqsave(&il->reg_lock, reg_flags);
2430 _il_grab_nic_access(il);
2431
2432 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
2433 rmb();
2434 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
2435
2436 _il_release_nic_access(il);
2437 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2438 return value;
2439}
2440
2441static inline void
2442il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
2443{
2444 unsigned long reg_flags;
2445
2446 spin_lock_irqsave(&il->reg_lock, reg_flags);
2447 if (!_il_grab_nic_access(il)) {
2448 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
2449 wmb();
2450 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
2451 _il_release_nic_access(il);
2452 }
2453 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2454}
2455
2456static inline void
e7392364 2457il_write_targ_mem_buf(struct il_priv *il, u32 addr, u32 len, u32 * values)
e94a4099
SG		 2458{
2459 unsigned long reg_flags;
2460
2461 spin_lock_irqsave(&il->reg_lock, reg_flags);
2462 if (!_il_grab_nic_access(il)) {
2463 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
2464 wmb();
2465 for (; 0 < len; len -= sizeof(u32), values++)
e7392364 2466 _il_wr(il, HBUS_TARG_MEM_WDAT, *values);
e94a4099
SG		 2467
2468 _il_release_nic_access(il);
2469 }
2470 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2471}
2472
2473#define HW_KEY_DYNAMIC 0
2474#define HW_KEY_DEFAULT 1
2475
e7392364
SG		 2476#define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
2477#define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
2478#define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
2479 being activated */
2480#define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211;
2481 (this is for the IBSS BSSID stations) */
2482#define IL_STA_BCAST BIT(4) /* this station is the special bcast station */
e94a4099 2483
e7392364
SG		 2484void il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx);
2485void il_clear_ucode_stations(struct il_priv *il, struct il_rxon_context *ctx);
e94a4099
SG		 2486void il_dealloc_bcast_stations(struct il_priv *il);
2487int il_get_free_ucode_key_idx(struct il_priv *il);
e7392364
SG		 2488int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2489int il_add_station_common(struct il_priv *il, struct il_rxon_context *ctx,
1722f8e1
SG		 2490 const u8 *addr, bool is_ap,
2491 struct ieee80211_sta *sta, u8 *sta_id_r);
e7392364
SG		 2492int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2493int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2494 struct ieee80211_sta *sta);
2495
2496u8 il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
1722f8e1 2497 const u8 *addr, bool is_ap, struct ieee80211_sta *sta);
e7392364
SG		 2498
2499int il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
2500 struct il_link_quality_cmd *lq, u8 flags, bool init);
e94a4099
SG		 2501
2502/**
2503 * il_clear_driver_stations - clear knowledge of all stations from driver
2504 * @il: iwl il struct
2505 *
2506 * This is called during il_down() to make sure that in the case
2507 * we're coming there from a hardware restart mac80211 will be
2508 * able to reconfigure stations -- if we're getting there in the
2509 * normal down flow then the stations will already be cleared.
2510 */
e7392364
SG		 2511static inline void
2512il_clear_driver_stations(struct il_priv *il)
e94a4099
SG		 2513{
2514 unsigned long flags;
2515 struct il_rxon_context *ctx = &il->ctx;
2516
2517 spin_lock_irqsave(&il->sta_lock, flags);
2518 memset(il->stations, 0, sizeof(il->stations));
2519 il->num_stations = 0;
2520
2521 il->ucode_key_table = 0;
2522
2523 /*
2524 * Remove all key information that is not stored as part
2525 * of station information since mac80211 may not have had
2526 * a chance to remove all the keys. When device is
2527 * reconfigured by mac80211 after an error all keys will
2528 * be reconfigured.
2529 */
2530 memset(ctx->wep_keys, 0, sizeof(ctx->wep_keys));
2531 ctx->key_mapping_keys = 0;
2532
2533 spin_unlock_irqrestore(&il->sta_lock, flags);
2534}
2535
e7392364
SG		 2536static inline int
2537il_sta_id(struct ieee80211_sta *sta)
e94a4099
SG		 2538{
2539 if (WARN_ON(!sta))
2540 return IL_INVALID_STATION;
2541
2542 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2543}
2544
2545/**
2546 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2547 * @il: iwl il
2548 * @context: the current context
2549 * @sta: mac80211 station
2550 *
2551 * In certain circumstances mac80211 passes a station pointer
2552 * that may be %NULL, for example during TX or key setup. In
2553 * that case, we need to use the broadcast station, so this
2554 * inline wraps that pattern.
2555 */
e7392364
SG		 2556static inline int
2557il_sta_id_or_broadcast(struct il_priv *il, struct il_rxon_context *context,
2558 struct ieee80211_sta *sta)
e94a4099
SG		 2559{
2560 int sta_id;
2561
2562 if (!sta)
2563 return context->bcast_sta_id;
2564
2565 sta_id = il_sta_id(sta);
2566
2567 /*
2568 * mac80211 should not be passing a partially
2569 * initialised station!
2570 */
2571 WARN_ON(sta_id == IL_INVALID_STATION);
2572
2573 return sta_id;
2574}
2575
2576/**
2577 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2578 * @idx -- current idx
2579 * @n_bd -- total number of entries in queue (must be power of 2)
2580 */
e7392364
SG		 2581static inline int
2582il_queue_inc_wrap(int idx, int n_bd)
e94a4099
SG		 2583{
2584 return ++idx & (n_bd - 1);
2585}
2586
2587/**
2588 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2589 * @idx -- current idx
2590 * @n_bd -- total number of entries in queue (must be power of 2)
2591 */
e7392364
SG		 2592static inline int
2593il_queue_dec_wrap(int idx, int n_bd)
e94a4099
SG		 2594{
2595 return --idx & (n_bd - 1);
2596}
2597
2598/* TODO: Move fw_desc functions to iwl-pci.ko */
e7392364
SG		 2599static inline void
2600il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2601{
2602 if (desc->v_addr)
e7392364
SG		 2603 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2604 desc->p_addr);
e94a4099
SG		 2605 desc->v_addr = NULL;
2606 desc->len = 0;
2607}
2608
e7392364
SG		 2609static inline int
2610il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
e94a4099
SG		 2611{
2612 if (!desc->len) {
2613 desc->v_addr = NULL;
2614 return -EINVAL;
2615 }
2616
e7392364
SG		 2617 desc->v_addr =
2618 dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2619 GFP_KERNEL);
e94a4099
SG		 2620 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2621}
2622
2623/*
2624 * we have 8 bits used like this:
2625 *
2626 * 7 6 5 4 3 2 1 0
2627 * | | | | | | | |
2628 * | | | | | | +-+-------- AC queue (0-3)
2629 * | | | | | |
2630 * | +-+-+-+-+------------ HW queue ID
2631 * |
2632 * +---------------------- unused
2633 */
2634static inline void
2635il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2636{
e7392364
SG		 2637 BUG_ON(ac > 3); /* only have 2 bits */
2638 BUG_ON(hwq > 31); /* only use 5 bits */
e94a4099
SG		 2639
2640 txq->swq_id = (hwq << 2) | ac;
2641}
2642
e7392364
SG		 2643static inline void
2644il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2645{
2646 u8 queue = txq->swq_id;
2647 u8 ac = queue & 3;
2648 u8 hwq = (queue >> 2) & 0x1f;
2649
2650 if (test_and_clear_bit(hwq, il->queue_stopped))
2651 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2652 ieee80211_wake_queue(il->hw, ac);
2653}
2654
e7392364
SG		 2655static inline void
2656il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
e94a4099
SG		 2657{
2658 u8 queue = txq->swq_id;
2659 u8 ac = queue & 3;
2660 u8 hwq = (queue >> 2) & 0x1f;
2661
2662 if (!test_and_set_bit(hwq, il->queue_stopped))
2663 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2664 ieee80211_stop_queue(il->hw, ac);
2665}
2666
2667#ifdef ieee80211_stop_queue
2668#undef ieee80211_stop_queue
2669#endif
2670
2671#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2672
2673#ifdef ieee80211_wake_queue
2674#undef ieee80211_wake_queue
2675#endif
2676
2677#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2678
e7392364
SG		 2679static inline void
2680il_disable_interrupts(struct il_priv *il)
e94a4099
SG		 2681{
2682 clear_bit(S_INT_ENABLED, &il->status);
2683
2684 /* disable interrupts from uCode/NIC to host */
2685 _il_wr(il, CSR_INT_MASK, 0x00000000);
2686
2687 /* acknowledge/clear/reset any interrupts still pending
2688 * from uCode or flow handler (Rx/Tx DMA) */
2689 _il_wr(il, CSR_INT, 0xffffffff);
2690 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
e94a4099
SG		 2691}
2692
e7392364
SG		 2693static inline void
2694il_enable_rfkill_int(struct il_priv *il)
e94a4099 2695{
e94a4099
SG		 2696 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2697}
2698
e7392364
SG		 2699static inline void
2700il_enable_interrupts(struct il_priv *il)
e94a4099 2701{
e94a4099
SG		 2702 set_bit(S_INT_ENABLED, &il->status);
2703 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2704}
2705
2706/**
2707 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2708 * @il -- pointer to il_priv data structure
2709 * @tsf_bits -- number of bits need to shift for masking)
2710 */
e7392364
SG		 2711static inline u32
2712il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2713{
2714 return (1 << tsf_bits) - 1;
2715}
2716
2717/**
2718 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2719 * @il -- pointer to il_priv data structure
2720 * @tsf_bits -- number of bits need to shift for masking)
2721 */
e7392364
SG		 2722static inline u32
2723il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
e94a4099
SG		 2724{
2725 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2726}
2727
2728/**
2729 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2730 *
2731 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2732 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2733 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2734 * in which the last frame was written to
2735 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2736 * which was transferred
2737 */
2738struct il_rb_status {
2739 __le16 closed_rb_num;
2740 __le16 closed_fr_num;
2741 __le16 finished_rb_num;
2742 __le16 finished_fr_nam;
e7392364 2743 __le32 __unused; /* 3945 only */
e94a4099
SG		 2744} __packed;
2745
e94a4099
SG		 2746#define TFD_QUEUE_SIZE_MAX (256)
2747#define TFD_QUEUE_SIZE_BC_DUP (64)
2748#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2749#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2750#define IL_NUM_OF_TBS 20
2751
e7392364
SG		 2752static inline u8
2753il_get_dma_hi_addr(dma_addr_t addr)
e94a4099
SG		 2754{
2755 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2756}
e7392364 2757
e94a4099
SG		 2758/**
2759 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2760 *
2761 * This structure contains dma address and length of transmission address
2762 *
1722f8e1
SG		 2763 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2764 * unaligned on 16 bit boundary
2765 * @hi_n_len: 0-3 [35:32] portion of dma
2766 * 4-15 length of the tx buffer
e94a4099
SG		 2767 */
2768struct il_tfd_tb {
2769 __le32 lo;
2770 __le16 hi_n_len;
2771} __packed;
2772
2773/**
2774 * struct il_tfd
2775 *
2776 * Transmit Frame Descriptor (TFD)
2777 *
2778 * @ __reserved1[3] reserved
2779 * @ num_tbs 0-4 number of active tbs
2780 * 5 reserved
2781 * 6-7 padding (not used)
2782 * @ tbs[20] transmit frame buffer descriptors
1722f8e1 2783 * @ __pad padding
e94a4099
SG		 2784 *
2785 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2786 * Both driver and device share these circular buffers, each of which must be
2787 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2788 *
2789 * Driver must indicate the physical address of the base of each
9a95b370 2790 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
e94a4099
SG		 2791 *
2792 * Each TFD contains pointer/size information for up to 20 data buffers
2793 * in host DRAM. These buffers collectively contain the (one) frame described
2794 * by the TFD. Each buffer must be a single contiguous block of memory within
2795 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
2796 * of (4K - 4). The concatenates all of a TFD's buffers into a single
2797 * Tx frame, up to 8 KBytes in size.
2798 *
2799 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2800 */
2801struct il_tfd {
2802 u8 __reserved1[3];
2803 u8 num_tbs;
2804 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2805 __le32 __pad;
2806} __packed;
2807/* PCI registers */
2808#define PCI_CFG_RETRY_TIMEOUT 0x041
2809
2810/* PCI register values */
2811#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2812#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2813
3fbbf9a8 2814struct il_rate_info {
e7392364
SG		 2815 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2816 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
2817 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */
2818 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2819 u8 prev_ieee; /* previous rate in IEEE speeds */
2820 u8 next_ieee; /* next rate in IEEE speeds */
2821 u8 prev_rs; /* previous rate used in rs algo */
2822 u8 next_rs; /* next rate used in rs algo */
2823 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2824 u8 next_rs_tgg; /* next rate used in TGG rs algo */
3fbbf9a8
SG		 2825};
2826
2827struct il3945_rate_info {
2828 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2829 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */
2830 u8 prev_ieee; /* previous rate in IEEE speeds */
2831 u8 next_ieee; /* next rate in IEEE speeds */
2832 u8 prev_rs; /* previous rate used in rs algo */
2833 u8 next_rs; /* next rate used in rs algo */
2834 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
2835 u8 next_rs_tgg; /* next rate used in TGG rs algo */
2836 u8 table_rs_idx; /* idx in rate scale table cmd */
2837 u8 prev_table_rs; /* prev in rate table cmd */
2838};
2839
3fbbf9a8
SG		 2840/*
2841 * These serve as idxes into
2842 * struct il_rate_info il_rates[RATE_COUNT];
2843 */
2844enum {
2845 RATE_1M_IDX = 0,
2846 RATE_2M_IDX,
2847 RATE_5M_IDX,
2848 RATE_11M_IDX,
2849 RATE_6M_IDX,
2850 RATE_9M_IDX,
2851 RATE_12M_IDX,
2852 RATE_18M_IDX,
2853 RATE_24M_IDX,
2854 RATE_36M_IDX,
2855 RATE_48M_IDX,
2856 RATE_54M_IDX,
2857 RATE_60M_IDX,
2858 RATE_COUNT,
2859 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */
2860 RATE_COUNT_3945 = RATE_COUNT - 1,
2861 RATE_INVM_IDX = RATE_COUNT,
2862 RATE_INVALID = RATE_COUNT,
2863};
2864
2865enum {
2866 RATE_6M_IDX_TBL = 0,
2867 RATE_9M_IDX_TBL,
2868 RATE_12M_IDX_TBL,
2869 RATE_18M_IDX_TBL,
2870 RATE_24M_IDX_TBL,
2871 RATE_36M_IDX_TBL,
2872 RATE_48M_IDX_TBL,
2873 RATE_54M_IDX_TBL,
2874 RATE_1M_IDX_TBL,
2875 RATE_2M_IDX_TBL,
2876 RATE_5M_IDX_TBL,
2877 RATE_11M_IDX_TBL,
2878 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2879};
2880
2881enum {
2882 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2883 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2884 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2885 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2886 IL_LAST_CCK_RATE = RATE_11M_IDX,
2887};
2888
2889/* #define vs. enum to keep from defaulting to 'large integer' */
2890#define RATE_6M_MASK (1 << RATE_6M_IDX)
2891#define RATE_9M_MASK (1 << RATE_9M_IDX)
2892#define RATE_12M_MASK (1 << RATE_12M_IDX)
2893#define RATE_18M_MASK (1 << RATE_18M_IDX)
2894#define RATE_24M_MASK (1 << RATE_24M_IDX)
2895#define RATE_36M_MASK (1 << RATE_36M_IDX)
2896#define RATE_48M_MASK (1 << RATE_48M_IDX)
2897#define RATE_54M_MASK (1 << RATE_54M_IDX)
2898#define RATE_60M_MASK (1 << RATE_60M_IDX)
2899#define RATE_1M_MASK (1 << RATE_1M_IDX)
2900#define RATE_2M_MASK (1 << RATE_2M_IDX)
2901#define RATE_5M_MASK (1 << RATE_5M_IDX)
2902#define RATE_11M_MASK (1 << RATE_11M_IDX)
2903
2904/* uCode API values for legacy bit rates, both OFDM and CCK */
2905enum {
e7392364
SG		 2906 RATE_6M_PLCP = 13,
2907 RATE_9M_PLCP = 15,
3fbbf9a8
SG		 2908 RATE_12M_PLCP = 5,
2909 RATE_18M_PLCP = 7,
2910 RATE_24M_PLCP = 9,
2911 RATE_36M_PLCP = 11,
2912 RATE_48M_PLCP = 1,
2913 RATE_54M_PLCP = 3,
e7392364
SG		 2914 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */
2915 RATE_1M_PLCP = 10,
2916 RATE_2M_PLCP = 20,
2917 RATE_5M_PLCP = 55,
3fbbf9a8 2918 RATE_11M_PLCP = 110,
e7392364 2919 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
3fbbf9a8
SG		 2920};
2921
2922/* uCode API values for OFDM high-throughput (HT) bit rates */
2923enum {
2924 RATE_SISO_6M_PLCP = 0,
2925 RATE_SISO_12M_PLCP = 1,
2926 RATE_SISO_18M_PLCP = 2,
2927 RATE_SISO_24M_PLCP = 3,
2928 RATE_SISO_36M_PLCP = 4,
2929 RATE_SISO_48M_PLCP = 5,
2930 RATE_SISO_54M_PLCP = 6,
2931 RATE_SISO_60M_PLCP = 7,
e7392364 2932 RATE_MIMO2_6M_PLCP = 0x8,
3fbbf9a8
SG		 2933 RATE_MIMO2_12M_PLCP = 0x9,
2934 RATE_MIMO2_18M_PLCP = 0xa,
2935 RATE_MIMO2_24M_PLCP = 0xb,
2936 RATE_MIMO2_36M_PLCP = 0xc,
2937 RATE_MIMO2_48M_PLCP = 0xd,
2938 RATE_MIMO2_54M_PLCP = 0xe,
2939 RATE_MIMO2_60M_PLCP = 0xf,
2940 RATE_SISO_INVM_PLCP,
2941 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2942};
2943
2944/* MAC header values for bit rates */
2945enum {
e7392364
SG		 2946 RATE_6M_IEEE = 12,
2947 RATE_9M_IEEE = 18,
3fbbf9a8
SG		 2948 RATE_12M_IEEE = 24,
2949 RATE_18M_IEEE = 36,
2950 RATE_24M_IEEE = 48,
2951 RATE_36M_IEEE = 72,
2952 RATE_48M_IEEE = 96,
2953 RATE_54M_IEEE = 108,
2954 RATE_60M_IEEE = 120,
e7392364
SG		 2955 RATE_1M_IEEE = 2,
2956 RATE_2M_IEEE = 4,
2957 RATE_5M_IEEE = 11,
3fbbf9a8
SG		 2958 RATE_11M_IEEE = 22,
2959};
2960
2961#define IL_CCK_BASIC_RATES_MASK \
2962 (RATE_1M_MASK | \
2963 RATE_2M_MASK)
2964
2965#define IL_CCK_RATES_MASK \
2966 (IL_CCK_BASIC_RATES_MASK | \
2967 RATE_5M_MASK | \
2968 RATE_11M_MASK)
2969
2970#define IL_OFDM_BASIC_RATES_MASK \
2971 (RATE_6M_MASK | \
2972 RATE_12M_MASK | \
2973 RATE_24M_MASK)
2974
2975#define IL_OFDM_RATES_MASK \
2976 (IL_OFDM_BASIC_RATES_MASK | \
2977 RATE_9M_MASK | \
2978 RATE_18M_MASK | \
2979 RATE_36M_MASK | \
2980 RATE_48M_MASK | \
2981 RATE_54M_MASK)
2982
2983#define IL_BASIC_RATES_MASK \
2984 (IL_OFDM_BASIC_RATES_MASK | \
2985 IL_CCK_BASIC_RATES_MASK)
2986
2987#define RATES_MASK ((1 << RATE_COUNT) - 1)
2988#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2989
2990#define IL_INVALID_VALUE -1
2991
2992#define IL_MIN_RSSI_VAL -100
2993#define IL_MAX_RSSI_VAL 0
2994
2995/* These values specify how many Tx frame attempts before
2996 * searching for a new modulation mode */
2997#define IL_LEGACY_FAILURE_LIMIT 160
2998#define IL_LEGACY_SUCCESS_LIMIT 480
2999#define IL_LEGACY_TBL_COUNT 160
3000
3001#define IL_NONE_LEGACY_FAILURE_LIMIT 400
3002#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
3003#define IL_NONE_LEGACY_TBL_COUNT 1500
3004
3005/* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
3006#define IL_RS_GOOD_RATIO 12800 /* 100% */
3007#define RATE_SCALE_SWITCH 10880 /* 85% */
3008#define RATE_HIGH_TH 10880 /* 85% */
3009#define RATE_INCREASE_TH 6400 /* 50% */
3010#define RATE_DECREASE_TH 1920 /* 15% */
3011
3012/* possible actions when in legacy mode */
3013#define IL_LEGACY_SWITCH_ANTENNA1 0
3014#define IL_LEGACY_SWITCH_ANTENNA2 1
3015#define IL_LEGACY_SWITCH_SISO 2
3016#define IL_LEGACY_SWITCH_MIMO2_AB 3
3017#define IL_LEGACY_SWITCH_MIMO2_AC 4
3018#define IL_LEGACY_SWITCH_MIMO2_BC 5
3019
3020/* possible actions when in siso mode */
3021#define IL_SISO_SWITCH_ANTENNA1 0
3022#define IL_SISO_SWITCH_ANTENNA2 1
3023#define IL_SISO_SWITCH_MIMO2_AB 2
3024#define IL_SISO_SWITCH_MIMO2_AC 3
3025#define IL_SISO_SWITCH_MIMO2_BC 4
3026#define IL_SISO_SWITCH_GI 5
3027
3028/* possible actions when in mimo mode */
3029#define IL_MIMO2_SWITCH_ANTENNA1 0
3030#define IL_MIMO2_SWITCH_ANTENNA2 1
3031#define IL_MIMO2_SWITCH_SISO_A 2
3032#define IL_MIMO2_SWITCH_SISO_B 3
3033#define IL_MIMO2_SWITCH_SISO_C 4
3034#define IL_MIMO2_SWITCH_GI 5
3035
3036#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
3037
3038#define IL_ACTION_LIMIT 3 /* # possible actions */
3039
3040#define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */
3041
3042/* load per tid defines for A-MPDU activation */
3043#define IL_AGG_TPT_THREHOLD 0
3044#define IL_AGG_LOAD_THRESHOLD 10
3045#define IL_AGG_ALL_TID 0xff
3046#define TID_QUEUE_CELL_SPACING 50 /*mS */
3047#define TID_QUEUE_MAX_SIZE 20
3048#define TID_ROUND_VALUE 5 /* mS */
3049#define TID_MAX_LOAD_COUNT 8
3050
3051#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
3052#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
3053
3054extern const struct il_rate_info il_rates[RATE_COUNT];
3055
3056enum il_table_type {
3057 LQ_NONE,
e7392364 3058 LQ_G, /* legacy types */
3fbbf9a8 3059 LQ_A,
e7392364 3060 LQ_SISO, /* high-throughput types */
3fbbf9a8
SG		 3061 LQ_MIMO2,
3062 LQ_MAX,
3063};
3064
3065#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
3066#define is_siso(tbl) ((tbl) == LQ_SISO)
3067#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
3068#define is_mimo(tbl) (is_mimo2(tbl))
3069#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
3070#define is_a_band(tbl) ((tbl) == LQ_A)
3071#define is_g_and(tbl) ((tbl) == LQ_G)
3072
3073#define ANT_NONE 0x0
3074#define ANT_A BIT(0)
3075#define ANT_B BIT(1)
3076#define ANT_AB (ANT_A | ANT_B)
3077#define ANT_C BIT(2)
3078#define ANT_AC (ANT_A | ANT_C)
3079#define ANT_BC (ANT_B | ANT_C)
3080#define ANT_ABC (ANT_AB | ANT_C)
3081
3082#define IL_MAX_MCS_DISPLAY_SIZE 12
3083
3084struct il_rate_mcs_info {
e7392364
SG		 3085 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
3086 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
3fbbf9a8
SG		 3087};
3088
3089/**
3090 * struct il_rate_scale_data -- tx success history for one rate
3091 */
3092struct il_rate_scale_data {
3093 u64 data; /* bitmap of successful frames */
3094 s32 success_counter; /* number of frames successful */
3095 s32 success_ratio; /* per-cent * 128 */
3096 s32 counter; /* number of frames attempted */
3097 s32 average_tpt; /* success ratio * expected throughput */
3098 unsigned long stamp;
3099};
3100
3101/**
3102 * struct il_scale_tbl_info -- tx params and success history for all rates
3103 *
3104 * There are two of these in struct il_lq_sta,
3105 * one for "active", and one for "search".
3106 */
3107struct il_scale_tbl_info {
3108 enum il_table_type lq_type;
3109 u8 ant_type;
e7392364
SG		 3110 u8 is_SGI; /* 1 = short guard interval */
3111 u8 is_ht40; /* 1 = 40 MHz channel width */
3112 u8 is_dup; /* 1 = duplicated data streams */
3113 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
3114 u8 max_search; /* maximun number of tables we can search */
3fbbf9a8 3115 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
e7392364
SG		 3116 u32 current_rate; /* rate_n_flags, uCode API format */
3117 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */
3fbbf9a8
SG		 3118};
3119
3120struct il_traffic_load {
3121 unsigned long time_stamp; /* age of the oldest stats */
e7392364 3122 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time
3fbbf9a8 3123 * slice */
e7392364
SG		 3124 u32 total; /* total num of packets during the
3125 * last TID_MAX_TIME_DIFF */
3126 u8 queue_count; /* number of queues that has
3127 * been used since the last cleanup */
3128 u8 head; /* start of the circular buffer */
3fbbf9a8
SG		 3129};
3130
3131/**
3132 * struct il_lq_sta -- driver's rate scaling ilate structure
3133 *
3134 * Pointer to this gets passed back and forth between driver and mac80211.
3135 */
3136struct il_lq_sta {
3137 u8 active_tbl; /* idx of active table, range 0-1 */
3138 u8 enable_counter; /* indicates HT mode */
3139 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
3140 u8 search_better_tbl; /* 1: currently trying alternate mode */
3141 s32 last_tpt;
3142
3143 /* The following determine when to search for a new mode */
3144 u32 table_count_limit;
3145 u32 max_failure_limit; /* # failed frames before new search */
3146 u32 max_success_limit; /* # successful frames before new search */
3147 u32 table_count;
3148 u32 total_failed; /* total failed frames, any/all rates */
3149 u32 total_success; /* total successful frames, any/all rates */
3150 u64 flush_timer; /* time staying in mode before new search */
3151
3152 u8 action_counter; /* # mode-switch actions tried */
3153 u8 is_green;
3154 u8 is_dup;
3155 enum ieee80211_band band;
3156
3157 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
3158 u32 supp_rates;
3159 u16 active_legacy_rate;
3160 u16 active_siso_rate;
3161 u16 active_mimo2_rate;
e7392364 3162 s8 max_rate_idx; /* Max rate set by user */
3fbbf9a8
SG		 3163 u8 missed_rate_counter;
3164
3165 struct il_link_quality_cmd lq;
e7392364 3166 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */
3fbbf9a8
SG		 3167 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
3168 u8 tx_agg_tid_en;
3169#ifdef CONFIG_MAC80211_DEBUGFS
3170 struct dentry *rs_sta_dbgfs_scale_table_file;
3171 struct dentry *rs_sta_dbgfs_stats_table_file;
3172 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
3173 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
3174 u32 dbg_fixed_rate;
3175#endif
3176 struct il_priv *drv;
3177
3178 /* used to be in sta_info */
3179 int last_txrate_idx;
3180 /* last tx rate_n_flags */
3181 u32 last_rate_n_flags;
3182 /* packets destined for this STA are aggregated */
3183 u8 is_agg;
3184};
3185
3186/*
3187 * il_station_priv: Driver's ilate station information
3188 *
3189 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
3190 * in the structure for use by driver. This structure is places in that
3191 * space.
3192 *
3193 * The common struct MUST be first because it is shared between
3194 * 3945 and 4965!
3195 */
3196struct il_station_priv {
3197 struct il_station_priv_common common;
3198 struct il_lq_sta lq_sta;
3199 atomic_t pending_frames;
3200 bool client;
3201 bool asleep;
3202};
3203
e7392364
SG		 3204static inline u8
3205il4965_num_of_ant(u8 m)
3fbbf9a8
SG		 3206{
3207 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
3208}
3209
e7392364
SG		 3210static inline u8
3211il4965_first_antenna(u8 mask)
3fbbf9a8
SG		 3212{
3213 if (mask & ANT_A)
3214 return ANT_A;
3215 if (mask & ANT_B)
3216 return ANT_B;
3217 return ANT_C;
3218}
3219
3fbbf9a8
SG		 3220/**
3221 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
3222 *
3223 * The specific throughput table used is based on the type of network
3224 * the associated with, including A, B, G, and G w/ TGG protection
3225 */
3226extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
3227
3228/* Initialize station's rate scaling information after adding station */
e7392364
SG		 3229extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
3230 u8 sta_id);
3231extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
3232 u8 sta_id);
3fbbf9a8
SG		 3233
3234/**
3235 * il_rate_control_register - Register the rate control algorithm callbacks
3236 *
3237 * Since the rate control algorithm is hardware specific, there is no need
3238 * or reason to place it as a stand alone module. The driver can call
3239 * il_rate_control_register in order to register the rate control callbacks
3240 * with the mac80211 subsystem. This should be performed prior to calling
3241 * ieee80211_register_hw
3242 *
3243 */
3244extern int il4965_rate_control_register(void);
3245extern int il3945_rate_control_register(void);
3246
3247/**
3248 * il_rate_control_unregister - Unregister the rate control callbacks
3249 *
3250 * This should be called after calling ieee80211_unregister_hw, but before
3251 * the driver is unloaded.
3252 */
3253extern void il4965_rate_control_unregister(void);
3254extern void il3945_rate_control_unregister(void);
3255
99412002
SG		 3256extern int il_power_update_mode(struct il_priv *il, bool force);
3257extern void il_power_initialize(struct il_priv *il);
47ef694d 3258
f02579e3
SG		 3259extern u32 il_debug_level;
3260
3261#ifdef CONFIG_IWLEGACY_DEBUG
3262/*
3263 * il_get_debug_level: Return active debug level for device
3264 *
3265 * Using sysfs it is possible to set per device debug level. This debug
3266 * level will be used if set, otherwise the global debug level which can be
3267 * set via module parameter is used.
3268 */
e7392364
SG		 3269static inline u32
3270il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3271{
3272 if (il->debug_level)
3273 return il->debug_level;
3274 else
3275 return il_debug_level;
3276}
3277#else
e7392364
SG		 3278static inline u32
3279il_get_debug_level(struct il_priv *il)
f02579e3
SG		 3280{
3281 return il_debug_level;
3282}
3283#endif
3284
3285#define il_print_hex_error(il, p, len) \
3286do { \
3287 print_hex_dump(KERN_ERR, "iwl data: ", \
3288 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3289} while (0)
3290
3291#ifdef CONFIG_IWLEGACY_DEBUG
3292#define IL_DBG(level, fmt, args...) \
3293do { \
3294 if (il_get_debug_level(il) & level) \
3295 dev_printk(KERN_ERR, &il->hw->wiphy->dev, \
3296 "%c %s " fmt, in_interrupt() ? 'I' : 'U', \
3297 __func__ , ## args); \
3298} while (0)
3299
1722f8e1 3300#define il_print_hex_dump(il, level, p, len) \
f02579e3
SG		 3301do { \
3302 if (il_get_debug_level(il) & level) \
3303 print_hex_dump(KERN_DEBUG, "iwl data: ", \
3304 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
3305} while (0)
3306
3307#else
3308#define IL_DBG(level, fmt, args...)
e7392364
SG		 3309static inline void
3310il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
3311{
3312}
3313#endif /* CONFIG_IWLEGACY_DEBUG */
f02579e3
SG		 3314
3315#ifdef CONFIG_IWLEGACY_DEBUGFS
3316int il_dbgfs_register(struct il_priv *il, const char *name);
3317void il_dbgfs_unregister(struct il_priv *il);
3318#else
3319static inline int
3320il_dbgfs_register(struct il_priv *il, const char *name)
3321{
3322 return 0;
3323}
e7392364
SG		 3324
3325static inline void
3326il_dbgfs_unregister(struct il_priv *il)
f02579e3
SG		 3327{
3328}
e7392364 3329#endif /* CONFIG_IWLEGACY_DEBUGFS */
f02579e3
SG		 3330
3331/*
3332 * To use the debug system:
3333 *
3334 * If you are defining a new debug classification, simply add it to the #define
3335 * list here in the form of
3336 *
3337 * #define IL_DL_xxxx VALUE
3338 *
3339 * where xxxx should be the name of the classification (for example, WEP).
3340 *
3341 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
3342 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
3343 * to send output to that classification.
3344 *
3345 * The active debug levels can be accessed via files
3346 *
1722f8e1 3347 * /sys/module/iwl4965/parameters/debug
f02579e3 3348 * /sys/module/iwl3945/parameters/debug
1722f8e1 3349 * /sys/class/net/wlan0/device/debug_level
f02579e3
SG		 3350 *
3351 * when CONFIG_IWLEGACY_DEBUG=y.
3352 */
3353
3354/* 0x0000000F - 0x00000001 */
3355#define IL_DL_INFO (1 << 0)
3356#define IL_DL_MAC80211 (1 << 1)
3357#define IL_DL_HCMD (1 << 2)
3358#define IL_DL_STATE (1 << 3)
3359/* 0x000000F0 - 0x00000010 */
3360#define IL_DL_MACDUMP (1 << 4)
3361#define IL_DL_HCMD_DUMP (1 << 5)
3362#define IL_DL_EEPROM (1 << 6)
3363#define IL_DL_RADIO (1 << 7)
3364/* 0x00000F00 - 0x00000100 */
3365#define IL_DL_POWER (1 << 8)
3366#define IL_DL_TEMP (1 << 9)
3367#define IL_DL_NOTIF (1 << 10)
3368#define IL_DL_SCAN (1 << 11)
3369/* 0x0000F000 - 0x00001000 */
3370#define IL_DL_ASSOC (1 << 12)
3371#define IL_DL_DROP (1 << 13)
3372#define IL_DL_TXPOWER (1 << 14)
3373#define IL_DL_AP (1 << 15)
3374/* 0x000F0000 - 0x00010000 */
3375#define IL_DL_FW (1 << 16)
3376#define IL_DL_RF_KILL (1 << 17)
3377#define IL_DL_FW_ERRORS (1 << 18)
3378#define IL_DL_LED (1 << 19)
3379/* 0x00F00000 - 0x00100000 */
3380#define IL_DL_RATE (1 << 20)
3381#define IL_DL_CALIB (1 << 21)
3382#define IL_DL_WEP (1 << 22)
3383#define IL_DL_TX (1 << 23)
3384/* 0x0F000000 - 0x01000000 */
3385#define IL_DL_RX (1 << 24)
3386#define IL_DL_ISR (1 << 25)
3387#define IL_DL_HT (1 << 26)
3388/* 0xF0000000 - 0x10000000 */
3389#define IL_DL_11H (1 << 28)
3390#define IL_DL_STATS (1 << 29)
3391#define IL_DL_TX_REPLY (1 << 30)
3392#define IL_DL_QOS (1 << 31)
3393
3394#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3395#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3396#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3397#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3398#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3399#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3400#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3401#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3402#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3403#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3404#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3405#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3406#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3407#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3408#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3409#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3410#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3411#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3412#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3413#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3414#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3415#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3416#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3417#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3418#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3419#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3420#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3421#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3422#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3423
e2ebc833 3424#endif /* __il_core_h__ */
Linux kernel - Deliverables
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